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1 | /****************************************************************************** |
2 | * | |
3 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
4 | * redistributing this file, you may do so under either license. | |
5 | * | |
6 | * GPL LICENSE SUMMARY | |
7 | * | |
51368bf7 | 8 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
88076015 | 9 | * Copyright(c) 2015 - 2016 Intel Deutschland GmbH |
4b52c39d EG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of version 2 of the GNU General Public License as | |
13 | * published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, | |
23 | * USA | |
24 | * | |
25 | * The full GNU General Public License is included in this distribution | |
410dc5aa | 26 | * in the file called COPYING. |
4b52c39d EG |
27 | * |
28 | * Contact Information: | |
d01c5366 | 29 | * Intel Linux Wireless <linuxwifi@intel.com> |
4b52c39d EG |
30 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
31 | * | |
32 | * BSD LICENSE | |
33 | * | |
51368bf7 | 34 | * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. |
88076015 | 35 | * Copyright(c) 2015 - 2016 Intel Deutschland GmbH |
4b52c39d EG |
36 | * All rights reserved. |
37 | * | |
38 | * Redistribution and use in source and binary forms, with or without | |
39 | * modification, are permitted provided that the following conditions | |
40 | * are met: | |
41 | * | |
42 | * * Redistributions of source code must retain the above copyright | |
43 | * notice, this list of conditions and the following disclaimer. | |
44 | * * Redistributions in binary form must reproduce the above copyright | |
45 | * notice, this list of conditions and the following disclaimer in | |
46 | * the documentation and/or other materials provided with the | |
47 | * distribution. | |
48 | * * Neither the name Intel Corporation nor the names of its | |
49 | * contributors may be used to endorse or promote products derived | |
50 | * from this software without specific prior written permission. | |
51 | * | |
52 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
53 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
54 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
55 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
56 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
57 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
58 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
59 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
60 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
61 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
63 | * | |
64 | *****************************************************************************/ | |
65a0667b TW |
65 | #ifndef __iwl_fh_h__ |
66 | #define __iwl_fh_h__ | |
4b52c39d | 67 | |
a72b8b08 EG |
68 | #include <linux/types.h> |
69 | ||
4b52c39d EG |
70 | /****************************/ |
71 | /* Flow Handler Definitions */ | |
72 | /****************************/ | |
73 | ||
74 | /** | |
75 | * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) | |
76 | * Addresses are offsets from device's PCI hardware base address. | |
77 | */ | |
78 | #define FH_MEM_LOWER_BOUND (0x1000) | |
e0737a77 | 79 | #define FH_MEM_UPPER_BOUND (0x2000) |
4b52c39d EG |
80 | |
81 | /** | |
82 | * Keep-Warm (KW) buffer base address. | |
83 | * | |
8ff84a2c | 84 | * Driver must allocate a 4KByte buffer that is for keeping the |
4b52c39d | 85 | * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency |
8ff84a2c | 86 | * DRAM access when doing Txing or Rxing. The dummy accesses prevent host |
4b52c39d EG |
87 | * from going into a power-savings mode that would cause higher DRAM latency, |
88 | * and possible data over/under-runs, before all Tx/Rx is complete. | |
89 | * | |
90 | * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) | |
8ff84a2c | 91 | * of the buffer, which must be 4K aligned. Once this is set up, the device |
4b52c39d EG |
92 | * automatically invokes keep-warm accesses when normal accesses might not |
93 | * be sufficient to maintain fast DRAM response. | |
94 | * | |
95 | * Bit fields: | |
96 | * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned | |
97 | */ | |
98 | #define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) | |
99 | ||
100 | ||
101 | /** | |
102 | * TFD Circular Buffers Base (CBBC) addresses | |
103 | * | |
8ff84a2c | 104 | * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident |
4b52c39d EG |
105 | * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) |
106 | * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 | |
107 | * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte | |
108 | * aligned (address bits 0-7 must be 0). | |
5ef4acd5 JB |
109 | * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers |
110 | * for them are in different places. | |
4b52c39d EG |
111 | * |
112 | * Bit fields in each pointer register: | |
113 | * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned | |
114 | */ | |
5ef4acd5 JB |
115 | #define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) |
116 | #define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) | |
117 | #define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) | |
118 | #define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
119 | #define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) | |
120 | #define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) | |
4b52c39d | 121 | |
5ef4acd5 JB |
122 | /* Find TFD CB base pointer for given queue */ |
123 | static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl) | |
124 | { | |
125 | if (chnl < 16) | |
126 | return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; | |
127 | if (chnl < 20) | |
128 | return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); | |
129 | WARN_ON_ONCE(chnl >= 32); | |
130 | return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); | |
131 | } | |
4b52c39d EG |
132 | |
133 | ||
134 | /** | |
135 | * Rx SRAM Control and Status Registers (RSCSR) | |
136 | * | |
8ff84a2c | 137 | * These registers provide handshake between driver and device for the Rx queue |
4b52c39d | 138 | * (this queue handles *all* command responses, notifications, Rx data, etc. |
8ff84a2c | 139 | * sent from uCode to host driver). Unlike Tx, there is only one Rx |
4b52c39d EG |
140 | * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can |
141 | * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer | |
142 | * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 | |
143 | * mapping between RBDs and RBs. | |
144 | * | |
145 | * Driver must allocate host DRAM memory for the following, and set the | |
8ff84a2c | 146 | * physical address of each into device registers: |
4b52c39d EG |
147 | * |
148 | * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 | |
149 | * entries (although any power of 2, up to 4096, is selectable by driver). | |
150 | * Each entry (1 dword) points to a receive buffer (RB) of consistent size | |
151 | * (typically 4K, although 8K or 16K are also selectable by driver). | |
152 | * Driver sets up RB size and number of RBDs in the CB via Rx config | |
153 | * register FH_MEM_RCSR_CHNL0_CONFIG_REG. | |
154 | * | |
155 | * Bit fields within one RBD: | |
156 | * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned | |
157 | * | |
158 | * Driver sets physical address [35:8] of base of RBD circular buffer | |
159 | * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. | |
160 | * | |
8ff84a2c | 161 | * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers |
4b52c39d EG |
162 | * (RBs) have been filled, via a "write pointer", actually the index of |
163 | * the RB's corresponding RBD within the circular buffer. Driver sets | |
164 | * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. | |
165 | * | |
166 | * Bit fields in lower dword of Rx status buffer (upper dword not used | |
8ff84a2c | 167 | * by driver: |
4b52c39d EG |
168 | * 31-12: Not used by driver |
169 | * 11- 0: Index of last filled Rx buffer descriptor | |
8ff84a2c | 170 | * (device writes, driver reads this value) |
4b52c39d | 171 | * |
8ff84a2c | 172 | * As the driver prepares Receive Buffers (RBs) for device to fill, driver must |
4b52c39d | 173 | * enter pointers to these RBs into contiguous RBD circular buffer entries, |
8ff84a2c | 174 | * and update the device's "write" index register, |
4b52c39d EG |
175 | * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. |
176 | * | |
177 | * This "write" index corresponds to the *next* RBD that the driver will make | |
178 | * available, i.e. one RBD past the tail of the ready-to-fill RBDs within | |
179 | * the circular buffer. This value should initially be 0 (before preparing any | |
180 | * RBs), should be 8 after preparing the first 8 RBs (for example), and must | |
181 | * wrap back to 0 at the end of the circular buffer (but don't wrap before | |
182 | * "read" index has advanced past 1! See below). | |
8ff84a2c | 183 | * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. |
4b52c39d | 184 | * |
8ff84a2c | 185 | * As the device fills RBs (referenced from contiguous RBDs within the circular |
4b52c39d EG |
186 | * buffer), it updates the Rx status buffer in host DRAM, 2) described above, |
187 | * to tell the driver the index of the latest filled RBD. The driver must | |
8ff84a2c | 188 | * read this "read" index from DRAM after receiving an Rx interrupt from device |
4b52c39d EG |
189 | * |
190 | * The driver must also internally keep track of a third index, which is the | |
191 | * next RBD to process. When receiving an Rx interrupt, driver should process | |
192 | * all filled but unprocessed RBs up to, but not including, the RB | |
193 | * corresponding to the "read" index. For example, if "read" index becomes "1", | |
194 | * driver may process the RB pointed to by RBD 0. Depending on volume of | |
195 | * traffic, there may be many RBs to process. | |
196 | * | |
8ff84a2c | 197 | * If read index == write index, device thinks there is no room to put new data. |
4b52c39d EG |
198 | * Due to this, the maximum number of filled RBs is 255, instead of 256. To |
199 | * be safe, make sure that there is a gap of at least 2 RBDs between "write" | |
200 | * and "read" indexes; that is, make sure that there are no more than 254 | |
201 | * buffers waiting to be filled. | |
202 | */ | |
203 | #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) | |
204 | #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
205 | #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) | |
206 | ||
207 | /** | |
208 | * Physical base address of 8-byte Rx Status buffer. | |
209 | * Bit fields: | |
210 | * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. | |
211 | */ | |
212 | #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) | |
213 | ||
214 | /** | |
215 | * Physical base address of Rx Buffer Descriptor Circular Buffer. | |
216 | * Bit fields: | |
217 | * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. | |
218 | */ | |
219 | #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) | |
220 | ||
221 | /** | |
222 | * Rx write pointer (index, really!). | |
223 | * Bit fields: | |
224 | * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. | |
225 | * NOTE: For 256-entry circular buffer, use only bits [7:0]. | |
226 | */ | |
227 | #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) | |
228 | #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) | |
229 | ||
ddaf5a5b JB |
230 | #define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) |
231 | #define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG | |
4b52c39d EG |
232 | |
233 | /** | |
234 | * Rx Config/Status Registers (RCSR) | |
235 | * Rx Config Reg for channel 0 (only channel used) | |
236 | * | |
237 | * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for | |
238 | * normal operation (see bit fields). | |
239 | * | |
240 | * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. | |
241 | * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for | |
242 | * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. | |
243 | * | |
244 | * Bit fields: | |
245 | * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
246 | * '10' operate normally | |
247 | * 29-24: reserved | |
248 | * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), | |
249 | * min "5" for 32 RBDs, max "12" for 4096 RBDs. | |
250 | * 19-18: reserved | |
251 | * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, | |
252 | * '10' 12K, '11' 16K. | |
253 | * 15-14: reserved | |
254 | * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) | |
255 | * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) | |
256 | * typical value 0x10 (about 1/2 msec) | |
257 | * 3- 0: reserved | |
258 | */ | |
259 | #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) | |
260 | #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) | |
261 | #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) | |
262 | ||
263 | #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) | |
ddaf5a5b JB |
264 | #define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) |
265 | #define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) | |
4b52c39d EG |
266 | |
267 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ | |
268 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ | |
269 | #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ | |
270 | #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ | |
271 | #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ | |
272 | #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ | |
273 | ||
8cd519e8 WT |
274 | #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) |
275 | #define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) | |
c4bfc1c3 | 276 | #define RX_RB_TIMEOUT (0x11) |
4b52c39d EG |
277 | |
278 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) | |
279 | #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) | |
280 | #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) | |
281 | ||
282 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) | |
283 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) | |
284 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) | |
285 | #define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) | |
286 | ||
8cd519e8 WT |
287 | #define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) |
288 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) | |
289 | #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) | |
4b52c39d | 290 | |
4b52c39d EG |
291 | /** |
292 | * Rx Shared Status Registers (RSSR) | |
293 | * | |
294 | * After stopping Rx DMA channel (writing 0 to | |
295 | * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll | |
296 | * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. | |
297 | * | |
298 | * Bit fields: | |
299 | * 24: 1 = Channel 0 is idle | |
300 | * | |
301 | * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV | |
302 | * contain default values that should not be altered by the driver. | |
303 | */ | |
304 | #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) | |
305 | #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
306 | ||
307 | #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) | |
308 | #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) | |
309 | #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ | |
310 | (FH_MEM_RSSR_LOWER_BOUND + 0x008) | |
311 | ||
312 | #define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) | |
313 | ||
f0b9f5cb | 314 | #define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 |
baa21e83 | 315 | #define FH_MEM_TB_MAX_LENGTH (0x00020000) |
4b52c39d | 316 | |
96a6497b SS |
317 | /* 9000 rx series registers */ |
318 | ||
319 | #define RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */ | |
320 | #define RFH_Q_FRBDCB_BA_LSB(q) (RFH_Q0_FRBDCB_BA_LSB + (q) * 8) | |
321 | /* Write index table */ | |
322 | #define RFH_Q0_FRBDCB_WIDX 0xA08080 | |
323 | #define RFH_Q_FRBDCB_WIDX(q) (RFH_Q0_FRBDCB_WIDX + (q) * 4) | |
324 | /* Read index table */ | |
325 | #define RFH_Q0_FRBDCB_RIDX 0xA080C0 | |
326 | #define RFH_Q_FRBDCB_RIDX(q) (RFH_Q0_FRBDCB_RIDX + (q) * 4) | |
327 | /* Used list table */ | |
328 | #define RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */ | |
329 | #define RFH_Q_URBDCB_BA_LSB(q) (RFH_Q0_URBDCB_BA_LSB + (q) * 8) | |
330 | /* Write index table */ | |
331 | #define RFH_Q0_URBDCB_WIDX 0xA08180 | |
332 | #define RFH_Q_URBDCB_WIDX(q) (RFH_Q0_URBDCB_WIDX + (q) * 4) | |
333 | #define RFH_Q0_URBDCB_VAID 0xA081C0 | |
334 | #define RFH_Q_URBDCB_VAID(q) (RFH_Q0_URBDCB_VAID + (q) * 4) | |
335 | /* stts */ | |
336 | #define RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */ | |
337 | #define RFH_Q_URBD_STTS_WPTR_LSB(q) (RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8) | |
338 | ||
339 | #define RFH_Q0_ORB_WPTR_LSB 0xA08280 | |
340 | #define RFH_Q_ORB_WPTR_LSB(q) (RFH_Q0_ORB_WPTR_LSB + (q) * 8) | |
341 | #define RFH_RBDBUF_RBD0_LSB 0xA08300 | |
342 | #define RFH_RBDBUF_RBD_LSB(q) (RFH_RBDBUF_RBD0_LSB + (q) * 8) | |
343 | ||
344 | /* DMA configuration */ | |
345 | #define RFH_RXF_DMA_CFG 0xA09820 | |
346 | /* RB size */ | |
347 | #define RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */ | |
348 | #define RFH_RXF_DMA_RB_SIZE_POS 16 | |
349 | #define RFH_RXF_DMA_RB_SIZE_1K (0x1 << RFH_RXF_DMA_RB_SIZE_POS) | |
350 | #define RFH_RXF_DMA_RB_SIZE_2K (0x2 << RFH_RXF_DMA_RB_SIZE_POS) | |
351 | #define RFH_RXF_DMA_RB_SIZE_4K (0x4 << RFH_RXF_DMA_RB_SIZE_POS) | |
352 | #define RFH_RXF_DMA_RB_SIZE_8K (0x8 << RFH_RXF_DMA_RB_SIZE_POS) | |
353 | #define RFH_RXF_DMA_RB_SIZE_12K (0x9 << RFH_RXF_DMA_RB_SIZE_POS) | |
354 | #define RFH_RXF_DMA_RB_SIZE_16K (0xA << RFH_RXF_DMA_RB_SIZE_POS) | |
355 | #define RFH_RXF_DMA_RB_SIZE_20K (0xB << RFH_RXF_DMA_RB_SIZE_POS) | |
356 | #define RFH_RXF_DMA_RB_SIZE_24K (0xC << RFH_RXF_DMA_RB_SIZE_POS) | |
357 | #define RFH_RXF_DMA_RB_SIZE_28K (0xD << RFH_RXF_DMA_RB_SIZE_POS) | |
358 | #define RFH_RXF_DMA_RB_SIZE_32K (0xE << RFH_RXF_DMA_RB_SIZE_POS) | |
359 | /* RB Circular Buffer size:defines the table sizes in RBD units */ | |
360 | #define RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */ | |
361 | #define RFH_RXF_DMA_RBDCB_SIZE_POS 20 | |
362 | #define RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
363 | #define RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
364 | #define RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
365 | #define RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
366 | #define RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
367 | #define RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
368 | #define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
369 | #define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
370 | #define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS) | |
88076015 | 371 | #define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */ |
96a6497b | 372 | #define RFH_RXF_DMA_MIN_RB_SIZE_POS 24 |
88076015 SS |
373 | #define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS) |
374 | #define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */ | |
375 | #define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */ | |
376 | #define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/ | |
377 | #define RFH_DMA_EN_ENABLE_VAL BIT(31) | |
96a6497b SS |
378 | |
379 | #define RFH_RXF_RXQ_ACTIVE 0xA0980C | |
380 | ||
381 | #define RFH_GEN_CFG 0xA09800 | |
88076015 SS |
382 | #define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0) |
383 | #define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1) | |
384 | #define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) /* 0 - 64B, 1- 128B */ | |
96a6497b | 385 | #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00 |
88076015 SS |
386 | #define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8 |
387 | ||
388 | #define DEFAULT_RXQ_NUM 0 | |
96a6497b SS |
389 | |
390 | /* end of 9000 rx series registers */ | |
391 | ||
e0737a77 TW |
392 | /* TFDB Area - TFDs buffer table */ |
393 | #define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) | |
394 | #define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) | |
395 | #define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) | |
396 | #define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) | |
397 | #define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) | |
398 | ||
4b52c39d EG |
399 | /** |
400 | * Transmit DMA Channel Control/Status Registers (TCSR) | |
401 | * | |
8ff84a2c | 402 | * Device has one configuration register for each of 8 Tx DMA/FIFO channels |
4b52c39d EG |
403 | * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, |
404 | * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. | |
405 | * | |
406 | * To use a Tx DMA channel, driver must initialize its | |
407 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: | |
408 | * | |
409 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | |
410 | * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | |
411 | * | |
412 | * All other bits should be 0. | |
413 | * | |
414 | * Bit fields: | |
415 | * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, | |
416 | * '10' operate normally | |
417 | * 29- 4: Reserved, set to "0" | |
418 | * 3: Enable internal DMA requests (1, normal operation), disable (0) | |
419 | * 2- 0: Reserved, set to "0" | |
420 | */ | |
421 | #define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) | |
422 | #define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) | |
423 | ||
424 | /* Find Control/Status reg for given Tx DMA/FIFO channel */ | |
02f6f659 | 425 | #define FH_TCSR_CHNL_NUM (8) |
4b52c39d | 426 | |
e0737a77 | 427 | /* TCSR: tx_config register values */ |
9c80c502 WT |
428 | #define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ |
429 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) | |
430 | #define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ | |
431 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) | |
432 | #define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ | |
433 | (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) | |
4b52c39d | 434 | |
9c80c502 WT |
435 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) |
436 | #define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) | |
4b52c39d | 437 | |
9c80c502 WT |
438 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) |
439 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) | |
4b52c39d | 440 | |
9c80c502 WT |
441 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) |
442 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) | |
443 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) | |
4b52c39d | 444 | |
9c80c502 WT |
445 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) |
446 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) | |
447 | #define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) | |
4b52c39d | 448 | |
9c80c502 WT |
449 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) |
450 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) | |
451 | #define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) | |
452 | ||
453 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) | |
454 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) | |
455 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) | |
456 | ||
457 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) | |
458 | #define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) | |
4b52c39d EG |
459 | |
460 | /** | |
461 | * Tx Shared Status Registers (TSSR) | |
462 | * | |
463 | * After stopping Tx DMA channel (writing 0 to | |
464 | * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll | |
465 | * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle | |
466 | * (channel's buffers empty | no pending requests). | |
467 | * | |
468 | * Bit fields: | |
469 | * 31-24: 1 = Channel buffers empty (channel 7:0) | |
470 | * 23-16: 1 = No pending requests (channel 7:0) | |
471 | */ | |
472 | #define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) | |
473 | #define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) | |
474 | ||
9c80c502 | 475 | #define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) |
4b52c39d | 476 | |
1b3eb823 WYG |
477 | /** |
478 | * Bit fields for TSSR(Tx Shared Status & Control) error status register: | |
479 | * 31: Indicates an address error when accessed to internal memory | |
480 | * uCode/driver must write "1" in order to clear this flag | |
481 | * 30: Indicates that Host did not send the expected number of dwords to FH | |
482 | * uCode/driver must write "1" in order to clear this flag | |
483 | * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA | |
484 | * command was received from the scheduler while the TRB was already full | |
485 | * with previous command | |
486 | * uCode/driver must write "1" in order to clear this flag | |
487 | * 7-0: Each status bit indicates a channel's TxCredit error. When an error | |
488 | * bit is set, it indicates that the FH has received a full indication | |
489 | * from the RTC TxFIFO and the current value of the TxCredit counter was | |
490 | * not equal to zero. This mean that the credit mechanism was not | |
491 | * synchronized to the TxFIFO status | |
492 | * uCode/driver must write "1" in order to clear this flag | |
493 | */ | |
494 | #define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) | |
99cd4714 | 495 | #define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) |
1b3eb823 | 496 | |
9726f347 | 497 | #define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) |
4b52c39d | 498 | |
4b52c39d | 499 | /* Tx service channels */ |
e0737a77 TW |
500 | #define FH_SRVC_CHNL (9) |
501 | #define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) | |
502 | #define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) | |
4b52c39d EG |
503 | #define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ |
504 | (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) | |
505 | ||
40fc95d5 | 506 | #define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) |
f22d3328 EG |
507 | #define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) |
508 | ||
40fc95d5 WT |
509 | /* Instruct FH to increment the retry count of a packet when |
510 | * it is brought from the memory to TX-FIFO | |
511 | */ | |
512 | #define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) | |
127901ab | 513 | |
7b542436 SS |
514 | #define MQ_RX_TABLE_SIZE 512 |
515 | #define MQ_RX_TABLE_MASK (MQ_RX_TABLE_SIZE - 1) | |
516 | #define MQ_RX_NUM_RBDS (MQ_RX_TABLE_SIZE - 1) | |
517 | #define RX_POOL_SIZE (MQ_RX_NUM_RBDS + \ | |
518 | IWL_MAX_RX_HW_QUEUES * \ | |
519 | (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC)) | |
96a6497b | 520 | |
1e33dc64 WT |
521 | #define RX_QUEUE_SIZE 256 |
522 | #define RX_QUEUE_MASK 255 | |
523 | #define RX_QUEUE_SIZE_LOG 8 | |
524 | ||
8d86422a | 525 | /** |
0d365ae5 | 526 | * struct iwl_rb_status - reserve buffer status |
8d86422a WT |
527 | * host memory mapped FH registers |
528 | * @closed_rb_num [0:11] - Indicates the index of the RB which was closed | |
529 | * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed | |
530 | * @finished_rb_num [0:11] - Indicates the index of the current RB | |
531 | * in which the last frame was written to | |
532 | * @finished_fr_num [0:11] - Indicates the index of the RX Frame | |
25985edc | 533 | * which was transferred |
8d86422a WT |
534 | */ |
535 | struct iwl_rb_status { | |
536 | __le16 closed_rb_num; | |
537 | __le16 closed_fr_num; | |
538 | __le16 finished_rb_num; | |
539 | __le16 finished_fr_nam; | |
ab4bf5ef | 540 | __le32 __unused; |
ba2d3587 | 541 | } __packed; |
127901ab | 542 | |
4ddbb7d0 | 543 | |
e0737a77 TW |
544 | #define TFD_QUEUE_SIZE_MAX (256) |
545 | #define TFD_QUEUE_SIZE_BC_DUP (64) | |
546 | #define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) | |
4ddbb7d0 | 547 | #define IWL_TX_DMA_MASK DMA_BIT_MASK(36) |
4ddbb7d0 TW |
548 | #define IWL_NUM_OF_TBS 20 |
549 | ||
550 | static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) | |
551 | { | |
552 | return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; | |
553 | } | |
554 | /** | |
555 | * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor | |
556 | * | |
557 | * This structure contains dma address and length of transmission address | |
558 | * | |
559 | * @lo: low [31:0] portion of the dma address of TX buffer | |
560 | * every even is unaligned on 16 bit boundary | |
561 | * @hi_n_len 0-3 [35:32] portion of dma | |
34faf780 | 562 | * 4-15 length of the tx buffer |
4ddbb7d0 TW |
563 | */ |
564 | struct iwl_tfd_tb { | |
565 | __le32 lo; | |
566 | __le16 hi_n_len; | |
ba2d3587 | 567 | } __packed; |
4ddbb7d0 TW |
568 | |
569 | /** | |
570 | * struct iwl_tfd | |
571 | * | |
572 | * Transmit Frame Descriptor (TFD) | |
573 | * | |
574 | * @ __reserved1[3] reserved | |
34faf780 ZY |
575 | * @ num_tbs 0-4 number of active tbs |
576 | * 5 reserved | |
4ddbb7d0 TW |
577 | * 6-7 padding (not used) |
578 | * @ tbs[20] transmit frame buffer descriptors | |
579 | * @ __pad padding | |
580 | * | |
581 | * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. | |
582 | * Both driver and device share these circular buffers, each of which must be | |
583 | * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes | |
584 | * | |
585 | * Driver must indicate the physical address of the base of each | |
586 | * circular buffer via the FH_MEM_CBBC_QUEUE registers. | |
587 | * | |
588 | * Each TFD contains pointer/size information for up to 20 data buffers | |
589 | * in host DRAM. These buffers collectively contain the (one) frame described | |
590 | * by the TFD. Each buffer must be a single contiguous block of memory within | |
591 | * itself, but buffers may be scattered in host DRAM. Each buffer has max size | |
592 | * of (4K - 4). The concatenates all of a TFD's buffers into a single | |
593 | * Tx frame, up to 8 KBytes in size. | |
594 | * | |
595 | * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. | |
4ddbb7d0 TW |
596 | */ |
597 | struct iwl_tfd { | |
598 | u8 __reserved1[3]; | |
599 | u8 num_tbs; | |
600 | struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; | |
601 | __le32 __pad; | |
ba2d3587 | 602 | } __packed; |
4ddbb7d0 | 603 | |
4ddbb7d0 | 604 | /* Keep Warm Size */ |
34faf780 | 605 | #define IWL_KW_SIZE 0x1000 /* 4k */ |
4ddbb7d0 | 606 | |
dda61a44 EG |
607 | /* Fixed (non-configurable) rx data from phy */ |
608 | ||
609 | /** | |
610 | * struct iwlagn_schedq_bc_tbl scheduler byte count table | |
611 | * base physical address provided by SCD_DRAM_BASE_ADDR | |
612 | * @tfd_offset 0-12 - tx command byte count | |
613 | * 12-16 - station index | |
614 | */ | |
615 | struct iwlagn_scd_bc_tbl { | |
616 | __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; | |
617 | } __packed; | |
618 | ||
65a0667b | 619 | #endif /* !__iwl_fh_h__ */ |