projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e99ea8d JB |
1 | /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ |
| 2 | /* | |
| 5f06f6bf | 3 | * Copyright (C) 2005-2014, 2018-2022 Intel Corporation |
| 8e99ea8d JB |
4 | * Copyright (C) 2013-2014 Intel Mobile Communications GmbH |
| 5 | * Copyright (C) 2016 Intel Deutschland GmbH | |
| 6 | */ | |
| 65a0667b TW |
7 | #ifndef __iwl_csr_h__ |
| 8 | #define __iwl_csr_h__ | |
| 9e595d24 BC |
9 | /* |
| 10 | * CSR (control and status registers) | |
| 11 | * | |
| 12 | * CSR registers are mapped directly into PCI bus space, and are accessible | |
| 13 | * whenever platform supplies power to device, even when device is in | |
| 14 | * low power states due to driver-invoked device resets | |
| 15 | * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes. | |
| 16 | * | |
| 17 | * Use iwl_write32() and iwl_read32() family to access these registers; | |
| 18 | * these provide simple PCI bus access, without waking up the MAC. | |
| 19 | * Do not use iwl_write_direct32() family for these registers; | |
| 20 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. | |
| 21 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing | |
| 22 | * the CSR registers. | |
| 23 | * | |
| f8701fe3 | 24 | * NOTE: Device does need to be awake in order to read this memory |
| 9e595d24 BC |
25 | * via CSR_EEPROM and CSR_OTP registers |
| 26 | */ | |
| 6f83eaa1 TW |
27 | #define CSR_BASE (0x000) |
| 28 | ||
| 29 | #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */ | |
| 9e595d24 | 30 | #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */ |
| 6f83eaa1 TW |
31 | #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */ |
| 32 | #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */ | |
| 33 | #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/ | |
| 34 | #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */ | |
| 35 | #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/ | |
| 36 | #define CSR_GP_CNTRL (CSR_BASE+0x024) | |
| 595c230b | 37 | #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */ |
| 6f83eaa1 | 38 | |
| 9e595d24 BC |
39 | /* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */ |
| 40 | #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005) | |
| 41 | ||
| 6f83eaa1 TW |
42 | /* |
| 43 | * Hardware revision info | |
| 44 | * Bit fields: | |
| 08838cde EG |
45 | * 31-16: Reserved |
| 46 | * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions | |
| 6f83eaa1 | 47 | * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D |
| 9e595d24 | 48 | * 1-0: "Dash" (-) value, as in A-1, etc. |
| 6f83eaa1 TW |
49 | */ |
| 50 | #define CSR_HW_REV (CSR_BASE+0x028) | |
| 51 | ||
| 1afb0ae4 HD |
52 | /* |
| 53 | * RF ID revision info | |
| 54 | * Bit fields: | |
| 55 | * 31:24: Reserved (set to 0x0) | |
| 56 | * 23:12: Type | |
| 57 | * 11:8: Step (A - 0x0, B - 0x1, etc) | |
| 58 | * 7:4: Dash | |
| 59 | * 3:0: Flavor | |
| 60 | */ | |
| 61 | #define CSR_HW_RF_ID (CSR_BASE+0x09c) | |
| 62 | ||
| 9e595d24 BC |
63 | /* |
| 64 | * EEPROM and OTP (one-time-programmable) memory reads | |
| 65 | * | |
| f8701fe3 RC |
66 | * NOTE: Device must be awake, initialized via apm_ops.init(), |
| 67 | * in order to read. | |
| 9e595d24 | 68 | */ |
| 6f83eaa1 TW |
69 | #define CSR_EEPROM_REG (CSR_BASE+0x02c) |
| 70 | #define CSR_EEPROM_GP (CSR_BASE+0x030) | |
| 0848e297 | 71 | #define CSR_OTP_GP_REG (CSR_BASE+0x034) |
| 9e595d24 | 72 | |
| 8f061891 | 73 | #define CSR_GIO_REG (CSR_BASE+0x03C) |
| 65b7998a WYG |
74 | #define CSR_GP_UCODE_REG (CSR_BASE+0x048) |
| 75 | #define CSR_GP_DRIVER_REG (CSR_BASE+0x050) | |
| 9e595d24 BC |
76 | |
| 77 | /* | |
| 78 | * UCODE-DRIVER GP (general purpose) mailbox registers. | |
| 79 | * SET/CLR registers set/clear bit(s) if "1" is written. | |
| 80 | */ | |
| 6f83eaa1 TW |
81 | #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054) |
| 82 | #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058) | |
| 83 | #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c) | |
| 84 | #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060) | |
| 9e595d24 | 85 | |
| 6a08f514 EG |
86 | #define CSR_MBOX_SET_REG (CSR_BASE + 0x88) |
| 87 | ||
| ab53d8af | 88 | #define CSR_LED_REG (CSR_BASE+0x094) |
| ef850d7c | 89 | #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0) |
| 1316d595 SS |
90 | #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */ |
| 91 | #define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE BIT(20) | |
| 92 | #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC) | |
| 93 | #define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE 0xFFFF | |
| 9e595d24 | 94 | |
| edb62520 JB |
95 | /* LTR control (since IWL_DEVICE_FAMILY_22000) */ |
| 96 | #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4) | |
| 97 | #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000 | |
| 98 | #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE 0x1c000000 | |
| 99 | #define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL 0x03ff0000 | |
| 100 | #define CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000 | |
| 101 | #define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE 0x00001c00 | |
| 102 | #define CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff | |
| 103 | #define CSR_LTR_LONG_VAL_AD_SCALE_USEC 2 | |
| 104 | ||
| 70582b82 JB |
105 | #define CSR_LTR_LAST_MSG (CSR_BASE + 0x0DC) |
| 106 | ||
| 9e595d24 | 107 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
| 8f061891 | 108 | #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) |
| 6f83eaa1 | 109 | |
| af08571d HD |
110 | #define CSR_IPC_SLEEP_CONTROL (CSR_BASE + 0x114) |
| 111 | #define CSR_IPC_SLEEP_CONTROL_SUSPEND 0x3 | |
| 112 | #define CSR_IPC_SLEEP_CONTROL_RESUME 0 | |
| 113 | ||
| fdfde0cb JB |
114 | /* Doorbell - since Bz |
| 115 | * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only) | |
| 116 | */ | |
| 6c0795f1 | 117 | #define CSR_DOORBELL_VECTOR (CSR_BASE + 0x130) |
| 6c0795f1 | 118 | |
| c00ee467 JB |
119 | /* host chicken bits */ |
| 120 | #define CSR_HOST_CHICKEN (CSR_BASE + 0x204) | |
| 121 | #define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME BIT(19) | |
| 122 | ||
| a693f187 | 123 | /* Analog phase-lock-loop configuration */ |
| 6f83eaa1 | 124 | #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) |
| 9e595d24 | 125 | |
| a812cba9 AB |
126 | /* |
| 127 | * CSR HW resources monitor registers | |
| 128 | */ | |
| 129 | #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214) | |
| 130 | #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228) | |
| 131 | #define CSR_MONITOR_XTAL_RESOURCES (0x00000010) | |
| 132 | ||
| 6f83eaa1 | 133 | /* |
| 9e595d24 | 134 | * CSR Hardware Revision Workaround Register. Indicates hardware rev; |
| fb70d49f | 135 | * "step" determines CCK backoff for txpower calculation. |
| 9e595d24 | 136 | * See also CSR_HW_REV register. |
| 6f83eaa1 TW |
137 | * Bit fields: |
| 138 | * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step | |
| 9e595d24 | 139 | * 1-0: "Dash" (-) value, as in C-1, etc. |
| 6f83eaa1 | 140 | */ |
| 32004ee4 | 141 | #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C) |
| 9e595d24 | 142 | |
| 32004ee4 WYG |
143 | #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240) |
| 144 | #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250) | |
| 6f83eaa1 | 145 | |
| 595c230b MG |
146 | /* |
| 147 | * Scratch register initial configuration - this is set on init, and read | |
| 148 | * during a error FW error. | |
| 149 | */ | |
| 150 | #define CSR_FUNC_SCRATCH_INIT_VALUE (0x01010101) | |
| 151 | ||
| 6f83eaa1 | 152 | /* Bits for CSR_HW_IF_CONFIG_REG */ |
| 55c6d8f8 | 153 | #define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH (0x0000000F) |
| e41e2c26 | 154 | #define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM (0x00000080) |
| 7b6a2be9 EG |
155 | #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0) |
| 156 | #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100) | |
| a395b920 | 157 | #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200) |
| 2d8c2615 | 158 | #define CSR_HW_IF_CONFIG_REG_D3_DEBUG (0x00000200) |
| 7b6a2be9 EG |
159 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00) |
| 160 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000) | |
| 161 | #define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000) | |
| 162 | ||
| 163 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0) | |
| 164 | #define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2) | |
| 165 | #define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6) | |
| 166 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10) | |
| 167 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12) | |
| 168 | #define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14) | |
| 6f83eaa1 | 169 | |
| 9e595d24 BC |
170 | #define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000) |
| 171 | #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000) | |
| 172 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */ | |
| 173 | #define CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */ | |
| 174 | #define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */ | |
| b7aaeae4 | 175 | #define CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000) |
| a812cba9 | 176 | #define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */ |
| 4c43e0d0 | 177 | |
| 6a08f514 EG |
178 | #define CSR_MBOX_SET_REG_OS_ALIVE BIT(5) |
| 179 | ||
| 74ba67ed BC |
180 | #define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/ |
| 181 | #define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/ | |
| 6f83eaa1 TW |
182 | |
| 183 | /* interrupt flags in INTA, set by uCode or hardware (e.g. dma), | |
| 184 | * acknowledged (reset) by host writing "1" to flagged bits. */ | |
| 185 | #define CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */ | |
| 186 | #define CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */ | |
| 40cefda9 | 187 | #define CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */ |
| 6f83eaa1 TW |
188 | #define CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */ |
| 189 | #define CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */ | |
| 190 | #define CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */ | |
| 191 | #define CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */ | |
| 192 | #define CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */ | |
| f7d046f9 | 193 | #define CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */ |
| 6f83eaa1 TW |
194 | #define CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */ |
| 195 | #define CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */ | |
| 196 | ||
| 197 | #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \ | |
| 198 | CSR_INT_BIT_HW_ERR | \ | |
| 199 | CSR_INT_BIT_FH_TX | \ | |
| 200 | CSR_INT_BIT_SW_ERR | \ | |
| 201 | CSR_INT_BIT_RF_KILL | \ | |
| 202 | CSR_INT_BIT_SW_RX | \ | |
| 203 | CSR_INT_BIT_WAKEUP | \ | |
| eef31718 EG |
204 | CSR_INT_BIT_ALIVE | \ |
| 205 | CSR_INT_BIT_RX_PERIODIC) | |
| 6f83eaa1 TW |
206 | |
| 207 | /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */ | |
| 208 | #define CSR_FH_INT_BIT_ERR (1 << 31) /* Error */ | |
| 209 | #define CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */ | |
| 6f83eaa1 TW |
210 | #define CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */ |
| 211 | #define CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */ | |
| 6f83eaa1 TW |
212 | #define CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */ |
| 213 | #define CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */ | |
| 214 | ||
| f7d046f9 WYG |
215 | #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \ |
| 216 | CSR_FH_INT_BIT_RX_CHNL1 | \ | |
| 217 | CSR_FH_INT_BIT_RX_CHNL0) | |
| 6f83eaa1 | 218 | |
| f7d046f9 WYG |
219 | #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL1 | \ |
| 220 | CSR_FH_INT_BIT_TX_CHNL0) | |
| 6f83eaa1 | 221 | |
| 6f4083aa TW |
222 | /* GPIO */ |
| 223 | #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200) | |
| 224 | #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000) | |
| 225 | #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200) | |
| 6f83eaa1 TW |
226 | |
| 227 | /* RESET */ | |
| 228 | #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001) | |
| 229 | #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002) | |
| 6dece0e9 | 230 | #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080) |
| 6f83eaa1 TW |
231 | #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100) |
| 232 | #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200) | |
| 32004ee4 | 233 | #define CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000) |
| 6f83eaa1 | 234 | |
| 9e595d24 BC |
235 | /* |
| 236 | * GP (general purpose) CONTROL REGISTER | |
| 237 | * Bit fields: | |
| 238 | * 27: HW_RF_KILL_SW | |
| 239 | * Indicates state of (platform's) hardware RF-Kill switch | |
| 240 | * 26-24: POWER_SAVE_TYPE | |
| 241 | * Indicates current power-saving mode: | |
| 242 | * 000 -- No power saving | |
| 243 | * 001 -- MAC power-down | |
| 244 | * 010 -- PHY (radio) power-down | |
| 245 | * 011 -- Error | |
| a812cba9 | 246 | * 10: XTAL ON request |
| 9e595d24 BC |
247 | * 9-6: SYS_CONFIG |
| 248 | * Indicates current system configuration, reflecting pins on chip | |
| 249 | * as forced high/low by device circuit board. | |
| 250 | * 4: GOING_TO_SLEEP | |
| 251 | * Indicates MAC is entering a power-saving sleep power-down. | |
| 252 | * Not a good time to access device-internal resources. | |
| 6dece0e9 LC |
253 | * 3: MAC_ACCESS_REQ |
| 254 | * Host sets this to request and maintain MAC wakeup, to allow host | |
| 255 | * access to device-internal resources. Host must wait for | |
| 256 | * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR | |
| 257 | * device registers. | |
| 258 | * 2: INIT_DONE | |
| 259 | * Host sets this to put device into fully operational D0 power mode. | |
| 260 | * Host resets this after SW_RESET to put device into low power mode. | |
| 261 | * 0: MAC_CLOCK_READY | |
| 262 | * Indicates MAC (ucode processor, etc.) is powered up and can run. | |
| 263 | * Internal resources are accessible. | |
| 264 | * NOTE: This does not indicate that the processor is actually running. | |
| 265 | * NOTE: This does not indicate that device has completed | |
| 266 | * init or post-power-down restore of internal SRAM memory. | |
| 267 | * Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that | |
| 268 | * SRAM is restored and uCode is in normal operation mode. | |
| 269 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
| 270 | * do not need to save/restore it. | |
| 271 | * NOTE: After device reset, this bit remains "0" until host sets | |
| 272 | * INIT_DONE | |
| 9e595d24 | 273 | */ |
| 6dece0e9 | 274 | #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001) |
| 9a47cb98 | 275 | #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004) |
| 6dece0e9 LC |
276 | #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008) |
| 277 | #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010) | |
| a812cba9 | 278 | #define CSR_GP_CNTRL_REG_FLAG_XTAL_ON (0x00000400) |
| 6f83eaa1 | 279 | |
| 6dece0e9 LC |
280 | #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001) |
| 281 | ||
| 6f83eaa1 | 282 | #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000) |
| ae5bb2a6 | 283 | #define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000) |
| 6f83eaa1 TW |
284 | #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000) |
| 285 | ||
| 9ce041f5 JB |
286 | /* From Bz we use these instead during init/reset flow */ |
| 287 | #define CSR_GP_CNTRL_REG_FLAG_MAC_INIT BIT(6) | |
| 288 | #define CSR_GP_CNTRL_REG_FLAG_ROM_START BIT(7) | |
| 289 | #define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS BIT(20) | |
| 290 | #define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ BIT(21) | |
| 291 | #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS BIT(28) | |
| 292 | #define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ BIT(29) | |
| 293 | #define CSR_GP_CNTRL_REG_FLAG_SW_RESET BIT(31) | |
| 6f83eaa1 | 294 | |
| b661c819 | 295 | /* HW REV */ |
| 55c6d8f8 | 296 | #define CSR_HW_REV_STEP_DASH(_val) ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH) |
| 391481ad | 297 | #define CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4) |
| 08838cde | 298 | |
| 0705b953 HD |
299 | /* HW RFID */ |
| 300 | #define CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0) | |
| 301 | #define CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4) | |
| 302 | #define CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8) | |
| 303 | #define CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12) | |
| b964bfd0 MG |
304 | #define CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28) |
| 305 | #define CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29) | |
| c2a2b28b LK |
306 | |
| 307 | /** | |
| 308 | * hw_rev values | |
| 309 | */ | |
| 310 | enum { | |
| 311 | SILICON_A_STEP = 0, | |
| 312 | SILICON_B_STEP, | |
| 716e48a6 | 313 | SILICON_C_STEP, |
| 72904029 MS |
314 | SILICON_D_STEP, |
| 315 | SILICON_E_STEP, | |
| f738e705 | 316 | SILICON_Z_STEP = 0xf, |
| c2a2b28b LK |
317 | }; |
| 318 | ||
| 319 | ||
| 3fd0d3c1 JB |
320 | #define CSR_HW_REV_TYPE_MSK (0x000FFF0) |
| 321 | #define CSR_HW_REV_TYPE_5300 (0x0000020) | |
| 322 | #define CSR_HW_REV_TYPE_5350 (0x0000030) | |
| 323 | #define CSR_HW_REV_TYPE_5100 (0x0000050) | |
| 324 | #define CSR_HW_REV_TYPE_5150 (0x0000040) | |
| 325 | #define CSR_HW_REV_TYPE_1000 (0x0000060) | |
| 326 | #define CSR_HW_REV_TYPE_6x00 (0x0000070) | |
| 327 | #define CSR_HW_REV_TYPE_6x50 (0x0000080) | |
| 328 | #define CSR_HW_REV_TYPE_6150 (0x0000084) | |
| 329 | #define CSR_HW_REV_TYPE_6x05 (0x00000B0) | |
| 330 | #define CSR_HW_REV_TYPE_6x30 CSR_HW_REV_TYPE_6x05 | |
| 331 | #define CSR_HW_REV_TYPE_6x35 CSR_HW_REV_TYPE_6x05 | |
| 332 | #define CSR_HW_REV_TYPE_2x30 (0x00000C0) | |
| 333 | #define CSR_HW_REV_TYPE_2x00 (0x0000100) | |
| 334 | #define CSR_HW_REV_TYPE_105 (0x0000110) | |
| 335 | #define CSR_HW_REV_TYPE_135 (0x0000120) | |
| 5f06f6bf | 336 | #define CSR_HW_REV_TYPE_3160 (0x0000164) |
| 3fd0d3c1 JB |
337 | #define CSR_HW_REV_TYPE_7265D (0x0000210) |
| 338 | #define CSR_HW_REV_TYPE_NONE (0x00001F0) | |
| 5f19d6dd | 339 | #define CSR_HW_REV_TYPE_QNJ (0x0000360) |
| 55c6d8f8 MG |
340 | #define CSR_HW_REV_TYPE_QNJ_B0 (0x0000361) |
| 341 | #define CSR_HW_REV_TYPE_QU_B0 (0x0000331) | |
| 342 | #define CSR_HW_REV_TYPE_QU_C0 (0x0000332) | |
| 343 | #define CSR_HW_REV_TYPE_QUZ (0x0000351) | |
| 5f19d6dd | 344 | #define CSR_HW_REV_TYPE_HR_CDB (0x0000340) |
| ff911dca ST |
345 | #define CSR_HW_REV_TYPE_SO (0x0000370) |
| 346 | #define CSR_HW_REV_TYPE_TY (0x0000420) | |
| b661c819 | 347 | |
| 1afb0ae4 | 348 | /* RF_ID value */ |
| 36ae4f3a | 349 | #define CSR_HW_RF_ID_TYPE_JF (0x00105100) |
| a85281eb | 350 | #define CSR_HW_RF_ID_TYPE_HR (0x0010A000) |
| 498d3eb5 | 351 | #define CSR_HW_RF_ID_TYPE_HR1 (0x0010c100) |
| 5f19d6dd | 352 | #define CSR_HW_RF_ID_TYPE_HRCDB (0x00109F00) |
| ff911dca | 353 | #define CSR_HW_RF_ID_TYPE_GF (0x0010D000) |
| 5bd757a6 | 354 | #define CSR_HW_RF_ID_TYPE_GF4 (0x0010E000) |
| 7f165fdf | 355 | #define CSR_HW_RF_ID_TYPE_MS (0x00111000) |
| 5f19d6dd | 356 | |
| 33708052 LC |
357 | /* HW_RF CHIP STEP */ |
| 358 | #define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF) | |
| 359 | ||
| 6f83eaa1 TW |
360 | /* EEPROM REG */ |
| 361 | #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001) | |
| 362 | #define CSR_EEPROM_REG_BIT_CMD (0x00000002) | |
| 3d5717ad ZY |
363 | #define CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC) |
| 364 | #define CSR_EEPROM_REG_MSK_DATA (0xFFFF0000) | |
| 6f83eaa1 TW |
365 | |
| 366 | /* EEPROM GP */ | |
| 9e595d24 | 367 | #define CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */ |
| 6f83eaa1 | 368 | #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180) |
| 9e595d24 BC |
369 | #define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000) |
| 370 | #define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001) | |
| 371 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002) | |
| 372 | #define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004) | |
| 373 | ||
| 374 | /* One-time-programmable memory general purpose reg */ | |
| 0848e297 WYG |
375 | #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */ |
| 376 | #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */ | |
| 377 | #define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */ | |
| 378 | #define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */ | |
| 9e595d24 BC |
379 | |
| 380 | /* GP REG */ | |
| c09430ab WYG |
381 | #define CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */ |
| 382 | #define CSR_GP_REG_NO_POWER_SAVE (0x00000000) | |
| 383 | #define CSR_GP_REG_MAC_POWER_SAVE (0x01000000) | |
| 384 | #define CSR_GP_REG_PHY_POWER_SAVE (0x02000000) | |
| 385 | #define CSR_GP_REG_POWER_SAVE_ERROR (0x03000000) | |
| 6f83eaa1 | 386 | |
| f41bb897 | 387 | |
| 8f061891 | 388 | /* CSR GIO */ |
| 3d1b28fd | 389 | #define CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002) |
| 8f061891 | 390 | |
| 9e595d24 BC |
391 | /* |
| 392 | * UCODE-DRIVER GP (general purpose) mailbox register 1 | |
| 393 | * Host driver and uCode write and/or read this register to communicate with | |
| 394 | * each other. | |
| 395 | * Bit fields: | |
| 396 | * 4: UCODE_DISABLE | |
| 397 | * Host sets this to request permanent halt of uCode, same as | |
| 398 | * sending CARD_STATE command with "halt" bit set. | |
| 399 | * 3: CT_KILL_EXIT | |
| 400 | * Host sets this to request exit from CT_KILL state, i.e. host thinks | |
| 401 | * device temperature is low enough to continue normal operation. | |
| 402 | * 2: CMD_BLOCKED | |
| 403 | * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL) | |
| 404 | * to release uCode to clear all Tx and command queues, enter | |
| 405 | * unassociated mode, and power down. | |
| 406 | * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit. | |
| 407 | * 1: SW_BIT_RFKILL | |
| 408 | * Host sets this when issuing CARD_STATE command to request | |
| 409 | * device sleep. | |
| 410 | * 0: MAC_SLEEP | |
| 411 | * uCode sets this when preparing a power-saving power-down. | |
| 412 | * uCode resets this when power-up is complete and SRAM is sane. | |
| f7d046f9 | 413 | * NOTE: device saves internal SRAM data to host when powering down, |
| 9e595d24 BC |
414 | * and must restore this data after powering back up. |
| 415 | * MAC_SLEEP is the best indication that restore is complete. | |
| 416 | * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and | |
| 417 | * do not need to save/restore it. | |
| 418 | */ | |
| 6f83eaa1 TW |
419 | #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001) |
| 420 | #define CSR_UCODE_SW_BIT_RFKILL (0x00000002) | |
| 421 | #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004) | |
| 422 | #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008) | |
| c8ac61cf | 423 | #define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020) |
| 6f83eaa1 | 424 | |
| 65b7998a WYG |
425 | /* GP Driver */ |
| 426 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003) | |
| 427 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000) | |
| 428 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001) | |
| 429 | #define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002) | |
| 02796d77 SZ |
430 | #define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004) |
| 431 | #define CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008) | |
| 65b7998a | 432 | |
| 52e6b85f WYG |
433 | #define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080) |
| 434 | ||
| 9e595d24 | 435 | /* GIO Chicken Bits (PCI Express bus link power management) */ |
| 6f83eaa1 TW |
436 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000) |
| 437 | #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000) | |
| 438 | ||
| ab53d8af MA |
439 | /* LED */ |
| 440 | #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF) | |
| c8f9b0fe EL |
441 | #define CSR_LED_REG_TURN_ON (0x60) |
| 442 | #define CSR_LED_REG_TURN_OFF (0x20) | |
| ab53d8af | 443 | |
| a693f187 | 444 | /* ANA_PLL */ |
| a693f187 TW |
445 | #define CSR50_ANA_PLL_CFG_VAL (0x00880300) |
| 446 | ||
| 4c43e0d0 TW |
447 | /* HPET MEM debug */ |
| 448 | #define CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000) | |
| ef850d7c MA |
449 | |
| 450 | /* DRAM INT TABLE */ | |
| 451 | #define CSR_DRAM_INT_TBL_ENABLE (1 << 31) | |
| 18f5a374 | 452 | #define CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28) |
| ef850d7c MA |
453 | #define CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27) |
| 454 | ||
| a812cba9 AB |
455 | /* |
| 456 | * SHR target access (Shared block memory space) | |
| 457 | * | |
| 458 | * Shared internal registers can be accessed directly from PCI bus through SHR | |
| 459 | * arbiter without need for the MAC HW to be powered up. This is possible due to | |
| 460 | * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and | |
| 461 | * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers. | |
| 462 | * | |
| 463 | * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW | |
| 464 | * need not be powered up so no "grab inc access" is required. | |
| 465 | */ | |
| 466 | ||
| 467 | /* | |
| 468 | * Registers for accessing shared registers (e.g. SHR_APMG_GP1, | |
| 469 | * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC), | |
| 470 | * first, write to the control register: | |
| 471 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
| 472 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access) | |
| 473 | * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0]. | |
| 474 | * | |
| 475 | * To write the register, first, write to the data register | |
| 476 | * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then: | |
| 477 | * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register) | |
| 478 | * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access) | |
| 479 | */ | |
| 480 | #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec) | |
| 481 | #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4) | |
| 482 | ||
| 9e595d24 BC |
483 | /* |
| 484 | * HBUS (Host-side Bus) | |
| 485 | * | |
| 486 | * HBUS registers are mapped directly into PCI bus space, but are used | |
| 487 | * to indirectly access device's internal memory or registers that | |
| 488 | * may be powered-down. | |
| 489 | * | |
| 490 | * Use iwl_write_direct32()/iwl_read_direct32() family for these registers; | |
| 491 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ | |
| 492 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing | |
| 493 | * internal resources. | |
| 494 | * | |
| 495 | * Do not use iwl_write32()/iwl_read32() family to access these registers; | |
| 496 | * these provide only simple PCI bus access, without waking up the MAC. | |
| 497 | */ | |
| 750fe639 | 498 | #define HBUS_BASE (0x400) |
| 9e595d24 | 499 | |
| 750fe639 TW |
500 | /* |
| 501 | * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM | |
| 502 | * structures, error log, event log, verifying uCode load). | |
| 503 | * First write to address register, then read from or write to data register | |
| 504 | * to complete the job. Once the address register is set up, accesses to | |
| 505 | * data registers auto-increment the address by one dword. | |
| 506 | * Bit usage for address registers (read or write): | |
| 507 | * 0-31: memory address within device | |
| 508 | */ | |
| 509 | #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c) | |
| 510 | #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010) | |
| 511 | #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018) | |
| 512 | #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c) | |
| 513 | ||
| 9e595d24 BC |
514 | /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */ |
| 515 | #define HBUS_TARG_MBX_C (HBUS_BASE+0x030) | |
| 516 | #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004) | |
| 517 | ||
| 750fe639 TW |
518 | /* |
| 519 | * Registers for accessing device's internal peripheral registers | |
| 520 | * (e.g. SCD, BSM, etc.). First write to address register, | |
| 521 | * then read from or write to data register to complete the job. | |
| 522 | * Bit usage for address registers (read or write): | |
| 523 | * 0-15: register address (offset) within device | |
| 524 | * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword) | |
| 525 | */ | |
| 526 | #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044) | |
| 527 | #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048) | |
| 528 | #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c) | |
| 529 | #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050) | |
| 530 | ||
| f8c6c6b5 AB |
531 | /* Used to enable DBGM */ |
| 532 | #define HBUS_TARG_TEST_REG (HBUS_BASE+0x05c) | |
| 533 | ||
| 750fe639 | 534 | /* |
| 9e595d24 | 535 | * Per-Tx-queue write pointer (index, really!) |
| 750fe639 TW |
536 | * Indicates index to next TFD that driver will fill (1 past latest filled). |
| 537 | * Bit usage: | |
| 538 | * 0-7: queue write index | |
| 539 | * 11-8: queue selector | |
| 540 | */ | |
| 541 | #define HBUS_TARG_WRPTR (HBUS_BASE+0x060) | |
| fba58d37 MG |
542 | /* This register is common for Tx and Rx, Rx queues start from 512 */ |
| 543 | #define HBUS_TARG_WRPTR_Q_SHIFT (16) | |
| 544 | #define HBUS_TARG_WRPTR_RX_Q(q) (((q) + 512) << HBUS_TARG_WRPTR_Q_SHIFT) | |
| 750fe639 | 545 | |
| 7a10e3e4 EG |
546 | /********************************************************** |
| 547 | * CSR values | |
| 548 | **********************************************************/ | |
| 549 | /* | |
| 550 | * host interrupt timeout value | |
| 551 | * used with setting interrupt coalescing timer | |
| 552 | * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit | |
| 553 | * | |
| 554 | * default interrupt coalescing timer is 64 x 32 = 2048 usecs | |
| 7a10e3e4 EG |
555 | */ |
| 556 | #define IWL_HOST_INT_TIMEOUT_MAX (0xFF) | |
| 557 | #define IWL_HOST_INT_TIMEOUT_DEF (0x40) | |
| 558 | #define IWL_HOST_INT_TIMEOUT_MIN (0x0) | |
| 6960a059 | 559 | #define IWL_HOST_INT_OPER_MODE BIT(31) |
| 7a10e3e4 | 560 | |
| 9ee718aa EL |
561 | /***************************************************************************** |
| 562 | * 7000/3000 series SHR DTS addresses * | |
| 563 | *****************************************************************************/ | |
| 564 | ||
| 565 | /* Diode Results Register Structure: */ | |
| 566 | enum dtd_diode_reg { | |
| 567 | DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */ | |
| 568 | DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */ | |
| 569 | DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */ | |
| 570 | DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */ | |
| 571 | DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */ | |
| 572 | DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */ | |
| 573 | /* Those are the masks INSIDE the flags bit-field: */ | |
| 574 | DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0, | |
| 575 | DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */ | |
| 576 | DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7, | |
| 577 | DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */ | |
| 578 | }; | |
| 579 | ||
| 2e5d4a8f HD |
580 | /***************************************************************************** |
| 581 | * MSIX related registers * | |
| 582 | *****************************************************************************/ | |
| 583 | ||
| 584 | #define CSR_MSIX_BASE (0x2000) | |
| 585 | #define CSR_MSIX_FH_INT_CAUSES_AD (CSR_MSIX_BASE + 0x800) | |
| 586 | #define CSR_MSIX_FH_INT_MASK_AD (CSR_MSIX_BASE + 0x804) | |
| 587 | #define CSR_MSIX_HW_INT_CAUSES_AD (CSR_MSIX_BASE + 0x808) | |
| 588 | #define CSR_MSIX_HW_INT_MASK_AD (CSR_MSIX_BASE + 0x80C) | |
| 589 | #define CSR_MSIX_AUTOMASK_ST_AD (CSR_MSIX_BASE + 0x810) | |
| 590 | #define CSR_MSIX_RX_IVAR_AD_REG (CSR_MSIX_BASE + 0x880) | |
| 591 | #define CSR_MSIX_IVAR_AD_REG (CSR_MSIX_BASE + 0x890) | |
| 592 | #define CSR_MSIX_PENDING_PBA_AD (CSR_MSIX_BASE + 0x1000) | |
| 593 | #define CSR_MSIX_RX_IVAR(cause) (CSR_MSIX_RX_IVAR_AD_REG + (cause)) | |
| 594 | #define CSR_MSIX_IVAR(cause) (CSR_MSIX_IVAR_AD_REG + (cause)) | |
| 595 | ||
| 596 | #define MSIX_FH_INT_CAUSES_Q(q) (q) | |
| 597 | ||
| 598 | /* | |
| 599 | * Causes for the FH register interrupts | |
| 600 | */ | |
| 601 | enum msix_fh_int_causes { | |
| 496d83ca HD |
602 | MSIX_FH_INT_CAUSES_Q0 = BIT(0), |
| 603 | MSIX_FH_INT_CAUSES_Q1 = BIT(1), | |
| 2e5d4a8f HD |
604 | MSIX_FH_INT_CAUSES_D2S_CH0_NUM = BIT(16), |
| 605 | MSIX_FH_INT_CAUSES_D2S_CH1_NUM = BIT(17), | |
| 606 | MSIX_FH_INT_CAUSES_S2D = BIT(19), | |
| 607 | MSIX_FH_INT_CAUSES_FH_ERR = BIT(21), | |
| 608 | }; | |
| 609 | ||
| d4626f91 MG |
610 | /* The low 16 bits are for rx data queue indication */ |
| 611 | #define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff | |
| 612 | ||
| 2e5d4a8f HD |
613 | /* |
| 614 | * Causes for the HW register interrupts | |
| 615 | */ | |
| 616 | enum msix_hw_int_causes { | |
| 617 | MSIX_HW_INT_CAUSES_REG_ALIVE = BIT(0), | |
| 618 | MSIX_HW_INT_CAUSES_REG_WAKEUP = BIT(1), | |
| aa7fd946 | 619 | MSIX_HW_INT_CAUSES_REG_IML = BIT(1), |
| 906d4eb8 | 620 | MSIX_HW_INT_CAUSES_REG_RESET_DONE = BIT(2), |
| 571836a0 | 621 | MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ = BIT(5), |
| 2e5d4a8f HD |
622 | MSIX_HW_INT_CAUSES_REG_CT_KILL = BIT(6), |
| 623 | MSIX_HW_INT_CAUSES_REG_RF_KILL = BIT(7), | |
| 624 | MSIX_HW_INT_CAUSES_REG_PERIODIC = BIT(8), | |
| 625 | MSIX_HW_INT_CAUSES_REG_SW_ERR = BIT(25), | |
| 626 | MSIX_HW_INT_CAUSES_REG_SCD = BIT(26), | |
| 627 | MSIX_HW_INT_CAUSES_REG_FH_TX = BIT(27), | |
| 628 | MSIX_HW_INT_CAUSES_REG_HW_ERR = BIT(29), | |
| 629 | MSIX_HW_INT_CAUSES_REG_HAP = BIT(30), | |
| 630 | }; | |
| 631 | ||
| 632 | #define MSIX_MIN_INTERRUPT_VECTORS 2 | |
| 633 | #define MSIX_AUTO_CLEAR_CAUSE 0 | |
| 634 | #define MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) | |
| 635 | ||
| 17c867bf SS |
636 | /***************************************************************************** |
| 637 | * HW address related registers * | |
| 638 | *****************************************************************************/ | |
| 639 | ||
| 7e6dffda JB |
640 | #define CSR_ADDR_BASE(trans) ((trans)->cfg->mac_addr_from_csr) |
| 641 | #define CSR_MAC_ADDR0_OTP(trans) (CSR_ADDR_BASE(trans) + 0x00) | |
| 642 | #define CSR_MAC_ADDR1_OTP(trans) (CSR_ADDR_BASE(trans) + 0x04) | |
| 643 | #define CSR_MAC_ADDR0_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x08) | |
| 644 | #define CSR_MAC_ADDR1_STRAP(trans) (CSR_ADDR_BASE(trans) + 0x0c) | |
| 17c867bf | 645 | |
| 65a0667b | 646 | #endif /* !__iwl_csr_h__ */ |