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iwlwifi: mvm: don't attempt debug collection in rfkill
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlwifi / fw / file.h
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edf38334
DF		 1/******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
51368bf7 8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
96c285da 9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
fd527eb5 10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
132db31c 11 * Copyright(c) 2018 Intel Corporation
ff418fee 12 * Copyright(c) 2019 Intel Corporation
edf38334
DF		 13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 *
edf38334 23 * The full GNU General Public License is included in this distribution
410dc5aa 24 * in the file called COPYING.
edf38334
DF		 25 *
26 * Contact Information:
cb2f8277 27 * Intel Linux Wireless <linuxwifi@intel.com>
edf38334
DF		 28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *
30 * BSD LICENSE
31 *
51368bf7 32 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
96c285da 33 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
fd527eb5 34 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
132db31c 35 * Copyright(c) 2018 Intel Corporation
ff418fee 36 * Copyright(c) 2019 Intel Corporation
edf38334
DF		 37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 *
43 * * Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * * Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
48 * distribution.
49 * * Neither the name Intel Corporation nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific prior written permission.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
56 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
57 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
58 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
59 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
64 *****************************************************************************/
65
3995deaf
JB		 66#ifndef __iwl_fw_file_h__
67#define __iwl_fw_file_h__
edf38334 68
b1c23d9e 69#include <linux/netdevice.h>
d2709ad7 70#include <linux/nl80211.h>
b1c23d9e 71
edf38334
DF		 72/* v1/v2 uCode file layout */
73struct iwl_ucode_header {
74 __le32 ver; /* major/minor/API/serial */
75 union {
76 struct {
77 __le32 inst_size; /* bytes of runtime code */
78 __le32 data_size; /* bytes of runtime data */
79 __le32 init_size; /* bytes of init code */
80 __le32 init_data_size; /* bytes of init data */
81 __le32 boot_size; /* bytes of bootstrap code */
82 u8 data[0]; /* in same order as sizes */
83 } v1;
84 struct {
85 __le32 build; /* build number */
86 __le32 inst_size; /* bytes of runtime code */
87 __le32 data_size; /* bytes of runtime data */
88 __le32 init_size; /* bytes of init code */
89 __le32 init_data_size; /* bytes of init data */
90 __le32 boot_size; /* bytes of bootstrap code */
91 u8 data[0]; /* in same order as sizes */
92 } v2;
93 } u;
94};
95
f14cda6f
SS		 96#define IWL_UCODE_INI_TLV_GROUP BIT(24)
97
edf38334
DF		 98/*
99 * new TLV uCode file layout
100 *
101 * The new TLV file format contains TLVs, that each specify
0479c19d 102 * some piece of data.
edf38334
DF		 103 */
104
105enum iwl_ucode_tlv_type {
106 IWL_UCODE_TLV_INVALID = 0, /* unused */
107 IWL_UCODE_TLV_INST = 1,
108 IWL_UCODE_TLV_DATA = 2,
109 IWL_UCODE_TLV_INIT = 3,
110 IWL_UCODE_TLV_INIT_DATA = 4,
111 IWL_UCODE_TLV_BOOT = 5,
112 IWL_UCODE_TLV_PROBE_MAX_LEN = 6, /* a u32 value */
113 IWL_UCODE_TLV_PAN = 7,
114 IWL_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
115 IWL_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
116 IWL_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
117 IWL_UCODE_TLV_INIT_EVTLOG_PTR = 11,
118 IWL_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
119 IWL_UCODE_TLV_INIT_ERRLOG_PTR = 13,
120 IWL_UCODE_TLV_ENHANCE_SENS_TBL = 14,
121 IWL_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
122 IWL_UCODE_TLV_WOWLAN_INST = 16,
123 IWL_UCODE_TLV_WOWLAN_DATA = 17,
124 IWL_UCODE_TLV_FLAGS = 18,
ed8c8365
DS		 125 IWL_UCODE_TLV_SEC_RT = 19,
126 IWL_UCODE_TLV_SEC_INIT = 20,
127 IWL_UCODE_TLV_SEC_WOWLAN = 21,
128 IWL_UCODE_TLV_DEF_CALIB = 22,
129 IWL_UCODE_TLV_PHY_SKU = 23,
e2d6f4e7
EH		 130 IWL_UCODE_TLV_SECURE_SEC_RT = 24,
131 IWL_UCODE_TLV_SECURE_SEC_INIT = 25,
132 IWL_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
133 IWL_UCODE_TLV_NUM_OF_CPU = 27,
e36e5433 134 IWL_UCODE_TLV_CSCHEME = 28,
a2978b11
EH		 135 IWL_UCODE_TLV_API_CHANGES_SET = 29,
136 IWL_UCODE_TLV_ENABLED_CAPABILITIES = 30,
762533ba 137 IWL_UCODE_TLV_N_SCAN_CHANNELS = 31,
a6c4fb44 138 IWL_UCODE_TLV_PAGING = 32,
61df750c 139 IWL_UCODE_TLV_SEC_RT_USNIFFER = 34,
fb7eba71 140 /* 35 is unused */
7e1223b5 141 IWL_UCODE_TLV_FW_VERSION = 36,
490fefeb
LK		 142 IWL_UCODE_TLV_FW_DBG_DEST = 38,
143 IWL_UCODE_TLV_FW_DBG_CONF = 39,
d2709ad7 144 IWL_UCODE_TLV_FW_DBG_TRIGGER = 40,
17564dde 145 IWL_UCODE_TLV_FW_GSCAN_CAPA = 50,
a6017b90 146 IWL_UCODE_TLV_FW_MEM_SEG = 51,
132db31c 147 IWL_UCODE_TLV_IML = 52,
22463857
SM		 148 IWL_UCODE_TLV_UMAC_DEBUG_ADDRS = 54,
149 IWL_UCODE_TLV_LMAC_DEBUG_ADDRS = 55,
f130bb75 150 IWL_UCODE_TLV_FW_RECOVERY_INFO = 57,
f14cda6f
SS		 151 IWL_UCODE_TLV_TYPE_BUFFER_ALLOCATION = IWL_UCODE_INI_TLV_GROUP | 0x1,
152 IWL_UCODE_TLV_TYPE_HCMD = IWL_UCODE_INI_TLV_GROUP | 0x2,
153 IWL_UCODE_TLV_TYPE_REGIONS = IWL_UCODE_INI_TLV_GROUP | 0x3,
154 IWL_UCODE_TLV_TYPE_TRIGGERS = IWL_UCODE_INI_TLV_GROUP | 0x4,
155 IWL_UCODE_TLV_TYPE_DEBUG_FLOW = IWL_UCODE_INI_TLV_GROUP | 0x5,
520f03ea
SM		 156
157 /* TLVs 0x1000-0x2000 are for internal driver usage */
158 IWL_UCODE_TLV_FW_DBG_DUMP_LST = 0x1000,
edf38334
DF		 159};
160
edf38334 161struct iwl_ucode_tlv {
0479c19d 162 __le32 type; /* see above */
edf38334
DF		 163 __le32 length; /* not including type/length fields */
164 u8 data[0];
165};
166
06ddbf5a
EG		 167#define IWL_TLV_UCODE_MAGIC 0x0a4c5749
168#define FW_VER_HUMAN_READABLE_SZ 64
edf38334
DF		 169
170struct iwl_tlv_ucode_header {
171 /*
172 * The TLV style ucode header is distinguished from
173 * the v1/v2 style header by first four bytes being
174 * zero, as such is an invalid combination of
175 * major/minor/API/serial versions.
176 */
177 __le32 zero;
178 __le32 magic;
06ddbf5a 179 u8 human_readable[FW_VER_HUMAN_READABLE_SZ];
7e1223b5
EG		 180 /* major/minor/API/serial or major in new format */
181 __le32 ver;
edf38334 182 __le32 build;
0479c19d 183 __le64 ignore;
edf38334
DF		 184 /*
185 * The data contained herein has a TLV layout,
186 * see above for the TLV header and types.
187 * Note that each TLV is padded to a length
188 * that is a multiple of 4 for alignment.
189 */
190 u8 data[0];
191};
192
a2978b11
EH		 193/*
194 * ucode TLVs
195 *
196 * ability to get extension for: flags & capabilities from ucode binaries files
197 */
198struct iwl_ucode_api {
199 __le32 api_index;
200 __le32 api_flags;
201} __packed;
202
203struct iwl_ucode_capa {
204 __le32 api_index;
205 __le32 api_capa;
206} __packed;
207
a52703b2
JB		 208/**
209 * enum iwl_ucode_tlv_flag - ucode API flags
210 * @IWL_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
211 * was a separate TLV but moved here to save space.
0d365ae5 212 * @IWL_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behavior on hidden SSID,
a52703b2
JB		 213 * treats good CRC threshold as a boolean
214 * @IWL_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
a52703b2
JB		 215 * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: This uCode image supports uAPSD
216 * @IWL_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
217 * offload profile config command.
218 * @IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
219 * (rather than two) IPv6 addresses
220 * @IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
221 * from the probe request template.
222 * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
223 * @IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
a52703b2
JB		 224 * @IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
225 * @IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
226 * @IWL_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
a52703b2
JB		 227 * @IWL_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
228 */
229enum iwl_ucode_tlv_flag {
230 IWL_UCODE_TLV_FLAGS_PAN = BIT(0),
231 IWL_UCODE_TLV_FLAGS_NEWSCAN = BIT(1),
232 IWL_UCODE_TLV_FLAGS_MFP = BIT(2),
a52703b2
JB		 233 IWL_UCODE_TLV_FLAGS_SHORT_BL = BIT(7),
234 IWL_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = BIT(10),
235 IWL_UCODE_TLV_FLAGS_NO_BASIC_SSID = BIT(12),
236 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = BIT(15),
237 IWL_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = BIT(16),
a52703b2
JB		 238 IWL_UCODE_TLV_FLAGS_UAPSD_SUPPORT = BIT(24),
239 IWL_UCODE_TLV_FLAGS_EBS_SUPPORT = BIT(25),
240 IWL_UCODE_TLV_FLAGS_P2P_PS_UAPSD = BIT(26),
241 IWL_UCODE_TLV_FLAGS_BCAST_FILTERING = BIT(29),
a52703b2
JB		 242};
243
9efeccac 244typedef unsigned int __bitwise iwl_ucode_tlv_api_t;
859d914c 245
a52703b2
JB		 246/**
247 * enum iwl_ucode_tlv_api - ucode api
a52703b2
JB		 248 * @IWL_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
249 * longer than the passive one, which is essential for fragmented scan.
8ba2d7a1 250 * @IWL_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
c5d679a5 251 * @IWL_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
f0d8f38c 252 * @IWL_UCODE_TLV_API_NEW_VERSION: new versioning format
aacf8f18
AS		 253 * @IWL_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
254 * iteration complete notification, and the timestamp reported for RX
255 * received during scan, are reported in TSF of the mac specified in the
256 * scan request.
45c458b4
SS		 257 * @IWL_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
258 * ADD_MODIFY_STA_KEY_API_S_VER_2.
ced19f26 259 * @IWL_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignement.
1247070d 260 * @IWL_UCODE_TLV_API_NAN2_VER2: This ucode supports NAN API version 2
678d9b6d 261 * @IWL_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
72cbb73e
DS		 262 * @IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY: Quota command includes a field
263 * indicating low latency direction.
57df3839
SS		 264 * @IWL_UCODE_TLV_API_DEPRECATE_TTAK: RX status flag TTAK ok (bit 7) is
265 * deprecated.
66fa2424
AB		 266 * @IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2: This ucode supports version 8
267 * of scan request: SCAN_REQUEST_CMD_UMAC_API_S_VER_8
4c2f445c 268 * @IWL_UCODE_TLV_API_FRAG_EBS: This ucode supports fragmented EBS
0791c2fc
HD		 269 * @IWL_UCODE_TLV_API_REDUCE_TX_POWER: This ucode supports v5 of
270 * the REDUCE_TX_POWER_CMD.
15e28c78
EG		 271 * @IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF: This ucode supports the short
272 * version of the beacon notification.
537ea3bb
AG		 273 * @IWL_UCODE_TLV_API_BEACON_FILTER_V4: This ucode supports v4 of
274 * BEACON_FILTER_CONFIG_API_S_VER_4.
ff418fee
AS		 275 * @IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ: This ucode supports v7 of
276 * LOCATION_RANGE_REQ_CMD_API_S and v6 of LOCATION_RANGE_RESP_NTFY_API_S.
d3f555f4
JB		 277 *
278 * @NUM_IWL_UCODE_TLV_API: number of bits used
a52703b2
JB		 279 */
280enum iwl_ucode_tlv_api {
678d9b6d 281 /* API Set 0 */
859d914c
JB		 282 IWL_UCODE_TLV_API_FRAGMENTED_SCAN = (__force iwl_ucode_tlv_api_t)8,
283 IWL_UCODE_TLV_API_WIFI_MCC_UPDATE = (__force iwl_ucode_tlv_api_t)9,
859d914c 284 IWL_UCODE_TLV_API_LQ_SS_PARAMS = (__force iwl_ucode_tlv_api_t)18,
4b87e5af 285 IWL_UCODE_TLV_API_NEW_VERSION = (__force iwl_ucode_tlv_api_t)20,
aacf8f18 286 IWL_UCODE_TLV_API_SCAN_TSF_REPORT = (__force iwl_ucode_tlv_api_t)28,
45c458b4 287 IWL_UCODE_TLV_API_TKIP_MIC_KEYS = (__force iwl_ucode_tlv_api_t)29,
ced19f26 288 IWL_UCODE_TLV_API_STA_TYPE = (__force iwl_ucode_tlv_api_t)30,
1247070d 289 IWL_UCODE_TLV_API_NAN2_VER2 = (__force iwl_ucode_tlv_api_t)31,
678d9b6d 290 /* API Set 1 */
dac4df1c 291 IWL_UCODE_TLV_API_ADAPTIVE_DWELL = (__force iwl_ucode_tlv_api_t)32,
8f691af9 292 IWL_UCODE_TLV_API_OCE = (__force iwl_ucode_tlv_api_t)33,
6ca33f8b 293 IWL_UCODE_TLV_API_NEW_BEACON_TEMPLATE = (__force iwl_ucode_tlv_api_t)34,
678d9b6d 294 IWL_UCODE_TLV_API_NEW_RX_STATS = (__force iwl_ucode_tlv_api_t)35,
2afa6a73 295 IWL_UCODE_TLV_API_WOWLAN_KEY_MATERIAL = (__force iwl_ucode_tlv_api_t)36,
72cbb73e 296 IWL_UCODE_TLV_API_QUOTA_LOW_LATENCY = (__force iwl_ucode_tlv_api_t)38,
57df3839 297 IWL_UCODE_TLV_API_DEPRECATE_TTAK = (__force iwl_ucode_tlv_api_t)41,
66fa2424 298 IWL_UCODE_TLV_API_ADAPTIVE_DWELL_V2 = (__force iwl_ucode_tlv_api_t)42,
4c2f445c 299 IWL_UCODE_TLV_API_FRAG_EBS = (__force iwl_ucode_tlv_api_t)44,
0791c2fc 300 IWL_UCODE_TLV_API_REDUCE_TX_POWER = (__force iwl_ucode_tlv_api_t)45,
15e28c78 301 IWL_UCODE_TLV_API_SHORT_BEACON_NOTIF = (__force iwl_ucode_tlv_api_t)46,
537ea3bb 302 IWL_UCODE_TLV_API_BEACON_FILTER_V4 = (__force iwl_ucode_tlv_api_t)47,
ff418fee 303 IWL_UCODE_TLV_API_FTM_NEW_RANGE_REQ = (__force iwl_ucode_tlv_api_t)49,
d3f555f4
JB		 304
305 NUM_IWL_UCODE_TLV_API
306#ifdef __CHECKER__
307 /* sparse says it cannot increment the previous enum member */
308 = 128
309#endif
a52703b2
JB		 310};
311
9efeccac 312typedef unsigned int __bitwise iwl_ucode_tlv_capa_t;
859d914c 313
a52703b2
JB		 314/**
315 * enum iwl_ucode_tlv_capa - ucode capabilities
316 * @IWL_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
317 * @IWL_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
318 * @IWL_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
3d44eebf 319 * @IWL_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
a52703b2
JB		 320 * @IWL_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
321 * @IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
322 * tx power value into TPC Report action frame and Link Measurement Report
323 * action frame
324 * @IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
325 * channel in DS parameter set element in probe requests.
326 * @IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
327 * probe requests.
328 * @IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
329 * @IWL_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
330 * which also implies support for the scheduler configuration command
331 * @IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
23ae6128 332 * @IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
a52703b2 333 * @IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
0becb377 334 * @IWL_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
93190fb0 335 * @IWL_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
91a8bcde 336 * @IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
c5241b0c
AS		 337 * @IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD: supports U-APSD on p2p interface when it
338 * is standalone or with a BSS station interface in the same binding.
0522588d 339 * @IWL_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
4d165d12
AN		 340 * @IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
341 * sources for the MCC. This TLV bit is a future replacement to
342 * IWL_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
343 * is supported.
70e90992 344 * @IWL_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
266ab689 345 * @IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan (no longer used)
65e25482 346 * @IWL_UCODE_TLV_CAPA_STA_PM_NOTIF: firmware will send STA PM notification
ecaf71de 347 * @IWL_UCODE_TLV_CAPA_TLC_OFFLOAD: firmware implements rate scaling algorithm
dad3340f 348 * @IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA: firmware implements quota related
50f067b3 349 * @IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2: firmware implements Coex Schema 2
74a10252 350 * IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD: firmware supports CSA command
57e861d9
DS		 351 * @IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band
352 * (6 GHz).
78efc702 353 * @IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
b08dbed7 354 * @IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
e7c2e1fd 355 * @IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
d3a108a4
AO		 356 * @IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD: the firmware supports CSA
357 * countdown offloading. Beacon notifications are not sent to the host.
358 * The fw also offloads TBTT alignment.
1e3c3c35
EG		 359 * @IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
360 * antenna the beacon should be transmitted
0db056d3
SS		 361 * @IWL_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
362 * from AP and will send it upon d0i3 exit.
47fe2f8e 363 * @IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3: support LAR API V3
0a3b7119
CRI		 364 * @IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
365 * @IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
366 * thresholds reporting
5c89e7bc 367 * @IWL_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
3d2d4422
GBA		 368 * @IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
369 * regular image.
5b086414
GBA		 370 * @IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
371 * memory addresses from the firmware.
03098268 372 * @IWL_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
55bfa4b9
LC		 373 * @IWL_UCODE_TLV_CAPA_TX_POWER_ACK: reduced TX power API has larger
374 * command size (command version 4) that supports toggling ACK TX
375 * power reduction.
2d8c2615 376 * @IWL_UCODE_TLV_CAPA_D3_DEBUG: supports debug recording during D3
47fe2f8e
HD		 377 * @IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT: MCC response support 11ax
378 * capability.
5213e8a8
JB		 379 * @IWL_UCODE_TLV_CAPA_CSI_REPORTING: firmware is capable of being configured
380 * to report the CSI information with (certain) RX frames
b73f9a4a
JB		 381 * @IWL_UCODE_TLV_CAPA_FTM_CALIBRATED: has FTM calibrated and thus supports both
382 * initiator and responder
5213e8a8
JB		 383 *
384 * @IWL_UCODE_TLV_CAPA_MLME_OFFLOAD: supports MLME offload
d3f555f4
JB		 385 *
386 * @NUM_IWL_UCODE_TLV_CAPA: number of bits used
a52703b2
JB		 387 */
388enum iwl_ucode_tlv_capa {
b73f9a4a 389 /* set 0 */
859d914c
JB		 390 IWL_UCODE_TLV_CAPA_D0I3_SUPPORT = (__force iwl_ucode_tlv_capa_t)0,
391 IWL_UCODE_TLV_CAPA_LAR_SUPPORT = (__force iwl_ucode_tlv_capa_t)1,
392 IWL_UCODE_TLV_CAPA_UMAC_SCAN = (__force iwl_ucode_tlv_capa_t)2,
393 IWL_UCODE_TLV_CAPA_BEAMFORMER = (__force iwl_ucode_tlv_capa_t)3,
394 IWL_UCODE_TLV_CAPA_TDLS_SUPPORT = (__force iwl_ucode_tlv_capa_t)6,
395 IWL_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = (__force iwl_ucode_tlv_capa_t)8,
396 IWL_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)9,
397 IWL_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = (__force iwl_ucode_tlv_capa_t)10,
398 IWL_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = (__force iwl_ucode_tlv_capa_t)11,
399 IWL_UCODE_TLV_CAPA_DQA_SUPPORT = (__force iwl_ucode_tlv_capa_t)12,
400 IWL_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = (__force iwl_ucode_tlv_capa_t)13,
23ae6128 401 IWL_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = (__force iwl_ucode_tlv_capa_t)17,
859d914c 402 IWL_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = (__force iwl_ucode_tlv_capa_t)18,
0becb377 403 IWL_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = (__force iwl_ucode_tlv_capa_t)19,
93190fb0 404 IWL_UCODE_TLV_CAPA_CSUM_SUPPORT = (__force iwl_ucode_tlv_capa_t)21,
859d914c 405 IWL_UCODE_TLV_CAPA_RADIO_BEACON_STATS = (__force iwl_ucode_tlv_capa_t)22,
c5241b0c 406 IWL_UCODE_TLV_CAPA_P2P_SCM_UAPSD = (__force iwl_ucode_tlv_capa_t)26,
859d914c
JB		 407 IWL_UCODE_TLV_CAPA_BT_COEX_PLCR = (__force iwl_ucode_tlv_capa_t)28,
408 IWL_UCODE_TLV_CAPA_LAR_MULTI_MCC = (__force iwl_ucode_tlv_capa_t)29,
409 IWL_UCODE_TLV_CAPA_BT_COEX_RRC = (__force iwl_ucode_tlv_capa_t)30,
17564dde 410 IWL_UCODE_TLV_CAPA_GSCAN_SUPPORT = (__force iwl_ucode_tlv_capa_t)31,
b73f9a4a
JB		 411
412 /* set 1 */
65e25482 413 IWL_UCODE_TLV_CAPA_STA_PM_NOTIF = (__force iwl_ucode_tlv_capa_t)38,
9415af7f
SS		 414 IWL_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT = (__force iwl_ucode_tlv_capa_t)39,
415 IWL_UCODE_TLV_CAPA_CDB_SUPPORT = (__force iwl_ucode_tlv_capa_t)40,
fcea37b2 416 IWL_UCODE_TLV_CAPA_D0I3_END_FIRST = (__force iwl_ucode_tlv_capa_t)41,
ecaf71de 417 IWL_UCODE_TLV_CAPA_TLC_OFFLOAD = (__force iwl_ucode_tlv_capa_t)43,
dad3340f 418 IWL_UCODE_TLV_CAPA_DYNAMIC_QUOTA = (__force iwl_ucode_tlv_capa_t)44,
50f067b3 419 IWL_UCODE_TLV_CAPA_COEX_SCHEMA_2 = (__force iwl_ucode_tlv_capa_t)45,
74a10252 420 IWL_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD = (__force iwl_ucode_tlv_capa_t)46,
57e861d9 421 IWL_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS = (__force iwl_ucode_tlv_capa_t)48,
b73f9a4a
JB		 422 IWL_UCODE_TLV_CAPA_FTM_CALIBRATED = (__force iwl_ucode_tlv_capa_t)47,
423
424 /* set 2 */
78efc702 425 IWL_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = (__force iwl_ucode_tlv_capa_t)64,
b08dbed7 426 IWL_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = (__force iwl_ucode_tlv_capa_t)65,
e7c2e1fd 427 IWL_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = (__force iwl_ucode_tlv_capa_t)67,
81f02ba3 428 IWL_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = (__force iwl_ucode_tlv_capa_t)68,
d3a108a4 429 IWL_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD = (__force iwl_ucode_tlv_capa_t)70,
1e3c3c35 430 IWL_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = (__force iwl_ucode_tlv_capa_t)71,
0db056d3 431 IWL_UCODE_TLV_CAPA_BEACON_STORING = (__force iwl_ucode_tlv_capa_t)72,
47fe2f8e 432 IWL_UCODE_TLV_CAPA_LAR_SUPPORT_V3 = (__force iwl_ucode_tlv_capa_t)73,
0a3b7119
CRI		 433 IWL_UCODE_TLV_CAPA_CT_KILL_BY_FW = (__force iwl_ucode_tlv_capa_t)74,
434 IWL_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = (__force iwl_ucode_tlv_capa_t)75,
5c89e7bc 435 IWL_UCODE_TLV_CAPA_CTDP_SUPPORT = (__force iwl_ucode_tlv_capa_t)76,
3d2d4422 436 IWL_UCODE_TLV_CAPA_USNIFFER_UNIFIED = (__force iwl_ucode_tlv_capa_t)77,
5b086414 437 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = (__force iwl_ucode_tlv_capa_t)80,
03098268 438 IWL_UCODE_TLV_CAPA_LQM_SUPPORT = (__force iwl_ucode_tlv_capa_t)81,
55bfa4b9 439 IWL_UCODE_TLV_CAPA_TX_POWER_ACK = (__force iwl_ucode_tlv_capa_t)84,
2d8c2615 440 IWL_UCODE_TLV_CAPA_D3_DEBUG = (__force iwl_ucode_tlv_capa_t)87,
4ef66965 441 IWL_UCODE_TLV_CAPA_LED_CMD_SUPPORT = (__force iwl_ucode_tlv_capa_t)88,
47fe2f8e 442 IWL_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT = (__force iwl_ucode_tlv_capa_t)89,
5213e8a8
JB		 443 IWL_UCODE_TLV_CAPA_CSI_REPORTING = (__force iwl_ucode_tlv_capa_t)90,
444
b73f9a4a 445 /* set 3 */
58877d74 446 IWL_UCODE_TLV_CAPA_MLME_OFFLOAD = (__force iwl_ucode_tlv_capa_t)96,
d3f555f4
JB		 447
448 NUM_IWL_UCODE_TLV_CAPA
449#ifdef __CHECKER__
450 /* sparse says it cannot increment the previous enum member */
451 = 128
452#endif
a52703b2
JB		 453};
454
455/* The default calibrate table size if not specified by firmware file */
456#define IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
457#define IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
458#define IWL_MAX_PHY_CALIBRATE_TBL_SIZE 253
459
460/* The default max probe length if not specified by the firmware file */
461#define IWL_DEFAULT_MAX_PROBE_LENGTH 200
462
463/*
464 * For 16.0 uCode and above, there is no differentiation between sections,
465 * just an offset to the HW address.
466 */
a52703b2 467#define CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
a6c4fb44 468#define PAGING_SEPARATOR_SECTION 0xAAAABBBB
a52703b2
JB		 469
470/* uCode version contains 4 values: Major/Minor/API/Serial */
471#define IWL_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
472#define IWL_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
473#define IWL_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
474#define IWL_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
475
31a658b2
JB		 476/**
477 * struct iwl_tlv_calib_ctrl - Calibration control struct.
a52703b2
JB		 478 * Sent as part of the phy configuration command.
479 * @flow_trigger: bitmap for which calibrations to perform according to
480 * flow triggers.
481 * @event_trigger: bitmap for which calibrations to perform according to
482 * event triggers.
483 */
484struct iwl_tlv_calib_ctrl {
485 __le32 flow_trigger;
486 __le32 event_trigger;
487} __packed;
488
489enum iwl_fw_phy_cfg {
490 FW_PHY_CFG_RADIO_TYPE_POS = 0,
491 FW_PHY_CFG_RADIO_TYPE = 0x3 << FW_PHY_CFG_RADIO_TYPE_POS,
492 FW_PHY_CFG_RADIO_STEP_POS = 2,
493 FW_PHY_CFG_RADIO_STEP = 0x3 << FW_PHY_CFG_RADIO_STEP_POS,
494 FW_PHY_CFG_RADIO_DASH_POS = 4,
495 FW_PHY_CFG_RADIO_DASH = 0x3 << FW_PHY_CFG_RADIO_DASH_POS,
496 FW_PHY_CFG_TX_CHAIN_POS = 16,
497 FW_PHY_CFG_TX_CHAIN = 0xf << FW_PHY_CFG_TX_CHAIN_POS,
498 FW_PHY_CFG_RX_CHAIN_POS = 20,
499 FW_PHY_CFG_RX_CHAIN = 0xf << FW_PHY_CFG_RX_CHAIN_POS,
86a2b204 500 FW_PHY_CFG_SHARED_CLK = BIT(31),
a52703b2
JB		 501};
502
503#define IWL_UCODE_MAX_CS 1
504
505/**
506 * struct iwl_fw_cipher_scheme - a cipher scheme supported by FW.
507 * @cipher: a cipher suite selector
508 * @flags: cipher scheme flags (currently reserved for a future use)
509 * @hdr_len: a size of MPDU security header
510 * @pn_len: a size of PN
511 * @pn_off: an offset of pn from the beginning of the security header
512 * @key_idx_off: an offset of key index byte in the security header
513 * @key_idx_mask: a bit mask of key_idx bits
514 * @key_idx_shift: bit shift needed to get key_idx
515 * @mic_len: mic length in bytes
516 * @hw_cipher: a HW cipher index used in host commands
517 */
518struct iwl_fw_cipher_scheme {
519 __le32 cipher;
520 u8 flags;
521 u8 hdr_len;
522 u8 pn_len;
523 u8 pn_off;
524 u8 key_idx_off;
525 u8 key_idx_mask;
526 u8 key_idx_shift;
527 u8 mic_len;
528 u8 hw_cipher;
529} __packed;
530
490fefeb
LK		 531enum iwl_fw_dbg_reg_operator {
532 CSR_ASSIGN,
533 CSR_SETBIT,
534 CSR_CLEARBIT,
535
536 PRPH_ASSIGN,
537 PRPH_SETBIT,
538 PRPH_CLEARBIT,
869f3b15
HD		 539
540 INDIRECT_ASSIGN,
541 INDIRECT_SETBIT,
542 INDIRECT_CLEARBIT,
543
544 PRPH_BLOCKBIT,
490fefeb
LK		 545};
546
547/**
548 * struct iwl_fw_dbg_reg_op - an operation on a register
549 *
69d22e73 550 * @op: &enum iwl_fw_dbg_reg_operator
490fefeb
LK		 551 * @addr: offset of the register
552 * @val: value
553 */
554struct iwl_fw_dbg_reg_op {
555 u8 op;
556 u8 reserved[3];
557 __le32 addr;
558 __le32 val;
559} __packed;
560
561/**
562 * enum iwl_fw_dbg_monitor_mode - available monitor recording modes
563 *
564 * @SMEM_MODE: monitor stores the data in SMEM
565 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM
566 * @MARBH_MODE: monitor stores the data in MARBH buffer
6a8ac59c 567 * @MIPI_MODE: monitor outputs the data through the MIPI interface
490fefeb
LK		 568 */
569enum iwl_fw_dbg_monitor_mode {
570 SMEM_MODE = 0,
571 EXTERNAL_MODE = 1,
572 MARBH_MODE = 2,
6a8ac59c 573 MIPI_MODE = 3,
490fefeb
LK		 574};
575
a6017b90
GBA		 576/**
577 * struct iwl_fw_dbg_mem_seg_tlv - configures the debug data memory segments
578 *
ea7c2bfd 579 * @data_type: the memory segment type to record
a6017b90
GBA		 580 * @ofs: the memory segment offset
581 * @len: the memory segment length, in bytes
582 *
583 * This parses IWL_UCODE_TLV_FW_MEM_SEG
584 */
585struct iwl_fw_dbg_mem_seg_tlv {
586 __le32 data_type;
587 __le32 ofs;
588 __le32 len;
589} __packed;
590
490fefeb 591/**
fd527eb5 592 * struct iwl_fw_dbg_dest_tlv_v1 - configures the destination of the debug data
490fefeb
LK		 593 *
594 * @version: version of the TLV - currently 0
69d22e73 595 * @monitor_mode: &enum iwl_fw_dbg_monitor_mode
96c285da 596 * @size_power: buffer size will be 2^(size_power + 11)
490fefeb
LK		 597 * @base_reg: addr of the base addr register (PRPH)
598 * @end_reg: addr of the end addr register (PRPH)
599 * @write_ptr_reg: the addr of the reg of the write pointer
600 * @wrap_count: the addr of the reg of the wrap_count
601 * @base_shift: shift right of the base addr reg
602 * @end_shift: shift right of the end addr reg
603 * @reg_ops: array of registers operations
604 *
605 * This parses IWL_UCODE_TLV_FW_DBG_DEST
606 */
fd527eb5 607struct iwl_fw_dbg_dest_tlv_v1 {
490fefeb
LK		 608 u8 version;
609 u8 monitor_mode;
96c285da
EG		 610 u8 size_power;
611 u8 reserved;
490fefeb
LK		 612 __le32 base_reg;
613 __le32 end_reg;
614 __le32 write_ptr_reg;
615 __le32 wrap_count;
616 u8 base_shift;
617 u8 end_shift;
618 struct iwl_fw_dbg_reg_op reg_ops[0];
619} __packed;
620
fd527eb5
GBA		 621/* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */
622#define IWL_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000
623/* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */
624#define IWL_LDBG_M2S_BUF_BA_MSK 0x00000fff
625/* The smem buffer chunks are in units of 256 bits */
626#define IWL_M2S_UNIT_SIZE 0x100
627
628struct iwl_fw_dbg_dest_tlv {
629 u8 version;
630 u8 monitor_mode;
631 u8 size_power;
632 u8 reserved;
633 __le32 cfg_reg;
634 __le32 write_ptr_reg;
635 __le32 wrap_count;
636 u8 base_shift;
637 u8 size_shift;
638 struct iwl_fw_dbg_reg_op reg_ops[0];
639} __packed;
640
490fefeb
LK		 641struct iwl_fw_dbg_conf_hcmd {
642 u8 id;
643 u8 reserved;
644 __le16 len;
645 u8 data[0];
646} __packed;
647
648/**
d2709ad7 649 * enum iwl_fw_dbg_trigger_mode - triggers functionalities
490fefeb 650 *
d2709ad7
EG		 651 * @IWL_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism
652 * @IWL_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data
36fb9017
OG		 653 * @IWL_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to
654 * collect only monitor data
490fefeb 655 */
d2709ad7
EG		 656enum iwl_fw_dbg_trigger_mode {
657 IWL_FW_DBG_TRIGGER_START = BIT(0),
658 IWL_FW_DBG_TRIGGER_STOP = BIT(1),
36fb9017 659 IWL_FW_DBG_TRIGGER_MONITOR_ONLY = BIT(2),
d2709ad7 660};
490fefeb 661
378c8931
SM		 662/**
663 * enum iwl_fw_dbg_trigger_flags - the flags supported by wrt triggers
664 * @IWL_FW_DBG_FORCE_RESTART: force a firmware restart
665 */
666enum iwl_fw_dbg_trigger_flags {
667 IWL_FW_DBG_FORCE_RESTART = BIT(0),
668};
669
490fefeb 670/**
d2709ad7
EG		 671 * enum iwl_fw_dbg_trigger_vif_type - define the VIF type for a trigger
672 * @IWL_FW_DBG_CONF_VIF_ANY: any vif type
673 * @IWL_FW_DBG_CONF_VIF_IBSS: IBSS mode
674 * @IWL_FW_DBG_CONF_VIF_STATION: BSS mode
675 * @IWL_FW_DBG_CONF_VIF_AP: AP mode
676 * @IWL_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode
677 * @IWL_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode
678 * @IWL_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device
490fefeb 679 */
d2709ad7
EG		 680enum iwl_fw_dbg_trigger_vif_type {
681 IWL_FW_DBG_CONF_VIF_ANY = NL80211_IFTYPE_UNSPECIFIED,
682 IWL_FW_DBG_CONF_VIF_IBSS = NL80211_IFTYPE_ADHOC,
683 IWL_FW_DBG_CONF_VIF_STATION = NL80211_IFTYPE_STATION,
684 IWL_FW_DBG_CONF_VIF_AP = NL80211_IFTYPE_AP,
685 IWL_FW_DBG_CONF_VIF_P2P_CLIENT = NL80211_IFTYPE_P2P_CLIENT,
686 IWL_FW_DBG_CONF_VIF_P2P_GO = NL80211_IFTYPE_P2P_GO,
687 IWL_FW_DBG_CONF_VIF_P2P_DEVICE = NL80211_IFTYPE_P2P_DEVICE,
490fefeb
LK		 688};
689
690/**
d2709ad7 691 * struct iwl_fw_dbg_trigger_tlv - a TLV that describes the trigger
69d22e73
JB		 692 * @id: &enum iwl_fw_dbg_trigger
693 * @vif_type: &enum iwl_fw_dbg_trigger_vif_type
d2709ad7
EG		 694 * @stop_conf_ids: bitmap of configurations this trigger relates to.
695 * if the mode is %IWL_FW_DBG_TRIGGER_STOP, then if the bit corresponding
696 * to the currently running configuration is set, the data should be
697 * collected.
698 * @stop_delay: how many milliseconds to wait before collecting the data
699 * after the STOP trigger fires.
69d22e73 700 * @mode: &enum iwl_fw_dbg_trigger_mode - can be stop / start of both
d2709ad7
EG		 701 * @start_conf_id: if mode is %IWL_FW_DBG_TRIGGER_START, this defines what
702 * configuration should be applied when the triggers kicks in.
703 * @occurrences: number of occurrences. 0 means the trigger will never fire.
a977a150
GBA		 704 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this
705 * trigger in which another occurrence should be ignored.
378c8931 706 * @flags: &enum iwl_fw_dbg_trigger_flags
d2709ad7
EG		 707 */
708struct iwl_fw_dbg_trigger_tlv {
709 __le32 id;
710 __le32 vif_type;
711 __le32 stop_conf_ids;
712 __le32 stop_delay;
713 u8 mode;
714 u8 start_conf_id;
715 __le16 occurrences;
a977a150 716 __le16 trig_dis_ms;
378c8931
SM		 717 u8 flags;
718 u8 reserved[5];
d2709ad7
EG		 719
720 u8 data[0];
721} __packed;
722
723#define FW_DBG_START_FROM_ALIVE 0
724#define FW_DBG_CONF_MAX 32
725#define FW_DBG_INVALID 0xff
726
9d761fd8
EG		 727/**
728 * struct iwl_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons
729 * @stop_consec_missed_bcon: stop recording if threshold is crossed.
730 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed.
731 * @start_consec_missed_bcon: start recording if threshold is crossed.
732 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed.
733 * @reserved1: reserved
734 * @reserved2: reserved
735 */
736struct iwl_fw_dbg_trigger_missed_bcon {
737 __le32 stop_consec_missed_bcon;
738 __le32 stop_consec_missed_bcon_since_rx;
739 __le32 reserved2[2];
740 __le32 start_consec_missed_bcon;
741 __le32 start_consec_missed_bcon_since_rx;
742 __le32 reserved1[2];
743} __packed;
744
917f39bb
EG		 745/**
746 * struct iwl_fw_dbg_trigger_cmd - configures trigger for messages from FW.
747 * cmds: the list of commands to trigger the collection on
748 */
749struct iwl_fw_dbg_trigger_cmd {
750 struct cmd {
751 u8 cmd_id;
752 u8 group_id;
753 } __packed cmds[16];
754} __packed;
755
5a756c20
EG		 756/**
757 * iwl_fw_dbg_trigger_stats - configures trigger for statistics
758 * @stop_offset: the offset of the value to be monitored
759 * @stop_threshold: the threshold above which to collect
760 * @start_offset: the offset of the value to be monitored
761 * @start_threshold: the threshold above which to start recording
762 */
763struct iwl_fw_dbg_trigger_stats {
764 __le32 stop_offset;
765 __le32 stop_threshold;
766 __le32 start_offset;
767 __le32 start_threshold;
768} __packed;
769
3ec50b5e
EG		 770/**
771 * struct iwl_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI
772 * @rssi: RSSI value to trigger at
773 */
774struct iwl_fw_dbg_trigger_low_rssi {
775 __le32 rssi;
776} __packed;
777
d42f5350
EG		 778/**
779 * struct iwl_fw_dbg_trigger_mlme - configures trigger for mlme events
780 * @stop_auth_denied: number of denied authentication to collect
781 * @stop_auth_timeout: number of authentication timeout to collect
782 * @stop_rx_deauth: number of Rx deauth before to collect
783 * @stop_tx_deauth: number of Tx deauth before to collect
784 * @stop_assoc_denied: number of denied association to collect
785 * @stop_assoc_timeout: number of association timeout to collect
31755207 786 * @stop_connection_loss: number of connection loss to collect
d42f5350
EG		 787 * @start_auth_denied: number of denied authentication to start recording
788 * @start_auth_timeout: number of authentication timeout to start recording
789 * @start_rx_deauth: number of Rx deauth to start recording
790 * @start_tx_deauth: number of Tx deauth to start recording
791 * @start_assoc_denied: number of denied association to start recording
792 * @start_assoc_timeout: number of association timeout to start recording
31755207 793 * @start_connection_loss: number of connection loss to start recording
d42f5350
EG		 794 */
795struct iwl_fw_dbg_trigger_mlme {
796 u8 stop_auth_denied;
797 u8 stop_auth_timeout;
798 u8 stop_rx_deauth;
799 u8 stop_tx_deauth;
800
801 u8 stop_assoc_denied;
802 u8 stop_assoc_timeout;
31755207
EG		 803 u8 stop_connection_loss;
804 u8 reserved;
d42f5350
EG		 805
806 u8 start_auth_denied;
807 u8 start_auth_timeout;
808 u8 start_rx_deauth;
809 u8 start_tx_deauth;
810
811 u8 start_assoc_denied;
812 u8 start_assoc_timeout;
31755207
EG		 813 u8 start_connection_loss;
814 u8 reserved2;
d42f5350
EG		 815} __packed;
816
5d42e7b2
EG		 817/**
818 * struct iwl_fw_dbg_trigger_txq_timer - configures the Tx queue's timer
819 * @command_queue: timeout for the command queue in ms
820 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms
821 * @softap: timeout for the queues of a softAP in ms
822 * @p2p_go: timeout for the queues of a P2P GO in ms
823 * @p2p_client: timeout for the queues of a P2P client in ms
824 * @p2p_device: timeout for the queues of a P2P device in ms
825 * @ibss: timeout for the queues of an IBSS in ms
826 * @tdls: timeout for the queues of a TDLS station in ms
827 */
828struct iwl_fw_dbg_trigger_txq_timer {
829 __le32 command_queue;
830 __le32 bss;
831 __le32 softap;
832 __le32 p2p_go;
833 __le32 p2p_client;
834 __le32 p2p_device;
835 __le32 ibss;
836 __le32 tdls;
837 __le32 reserved[4];
838} __packed;
839
874c174e
EG		 840/**
841 * struct iwl_fw_dbg_trigger_time_event - configures a time event trigger
842 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a
843 * trigger each time a time event notification that relates to time event
844 * id with one of the actions in the bitmap is received and
845 * BIT(notif->status) is set in status_bitmap.
846 *
847 */
848struct iwl_fw_dbg_trigger_time_event {
849 struct {
850 __le32 id;
851 __le32 action_bitmap;
852 __le32 status_bitmap;
853 } __packed time_events[16];
854} __packed;
855
4203263d
EG		 856/**
857 * struct iwl_fw_dbg_trigger_ba - configures BlockAck related trigger
858 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur
859 * when an Rx BlockAck session is started.
860 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur
861 * when an Rx BlockAck session is stopped.
862 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur
863 * when a Tx BlockAck session is started.
864 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur
865 * when a Tx BlockAck session is stopped.
866 * rx_bar: tid bitmap to configure on what tid the trigger should occur
867 * when a BAR is received (for a Tx BlockAck session).
868 * tx_bar: tid bitmap to configure on what tid the trigger should occur
869 * when a BAR is send (for an Rx BlocAck session).
870 * frame_timeout: tid bitmap to configure on what tid the trigger should occur
871 * when a frame times out in the reodering buffer.
872 */
873struct iwl_fw_dbg_trigger_ba {
874 __le16 rx_ba_start;
875 __le16 rx_ba_stop;
876 __le16 tx_ba_start;
877 __le16 tx_ba_stop;
878 __le16 rx_bar;
879 __le16 tx_bar;
880 __le16 frame_timeout;
881} __packed;
882
1e8f1329
GBA		 883/**
884 * struct iwl_fw_dbg_trigger_tdls - configures trigger for TDLS events.
885 * @action_bitmap: the TDLS action to trigger the collection upon
886 * @peer_mode: trigger on specific peer or all
887 * @peer: the TDLS peer to trigger the collection on
888 */
889struct iwl_fw_dbg_trigger_tdls {
890 u8 action_bitmap;
891 u8 peer_mode;
892 u8 peer[ETH_ALEN];
893 u8 reserved[4];
894} __packed;
895
25657fec
GBA		 896/**
897 * struct iwl_fw_dbg_trigger_tx_status - configures trigger for tx response
898 * status.
899 * @statuses: the list of statuses to trigger the collection on
900 */
901struct iwl_fw_dbg_trigger_tx_status {
902 struct tx_status {
903 u8 status;
904 u8 reserved[3];
905 } __packed statuses[16];
906 __le32 reserved[2];
907} __packed;
908
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EG		 909/**
910 * struct iwl_fw_dbg_conf_tlv - a TLV that describes a debug configuration.
911 * @id: conf id
490fefeb
LK		 912 * @usniffer: should the uSniffer image be used
913 * @num_of_hcmds: how many HCMDs to send are present here
914 * @hcmd: a variable length host command to be sent to apply the configuration.
915 * If there is more than one HCMD to send, they will appear one after the
916 * other and be sent in the order that they appear in.
d2709ad7
EG		 917 * This parses IWL_UCODE_TLV_FW_DBG_CONF. The user can add up-to
918 * %FW_DBG_CONF_MAX configuration per run.
490fefeb
LK		 919 */
920struct iwl_fw_dbg_conf_tlv {
921 u8 id;
922 u8 usniffer;
923 u8 reserved;
924 u8 num_of_hcmds;
925 struct iwl_fw_dbg_conf_hcmd hcmd;
490fefeb
LK		 926} __packed;
927
3995deaf 928#endif /* __iwl_fw_file_h__ */
Linux 6.x block layer and io_uring tree(s)