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iwlegacy: Return directly if allocation fails in il_eeprom_init()
[linux-2.6-block.git] / drivers / net / wireless / intel / iwlegacy / common.c
CommitLineData
be663ab6
WYG		 1/******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/etherdevice.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
0cdc2136
SG		 34#include <linux/types.h>
35#include <linux/lockdep.h>
0cdc2136
SG		 36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/delay.h>
39#include <linux/skbuff.h>
be663ab6
WYG		 40#include <net/mac80211.h>
41
98613be0 42#include "common.h"
be663ab6 43
17d4eca6
SG		 44int
45_il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout)
46{
47 const int interval = 10; /* microseconds */
48 int t = 0;
49
50 do {
51 if ((_il_rd(il, addr) & mask) == (bits & mask))
52 return t;
53 udelay(interval);
54 t += interval;
55 } while (t < timeout);
56
57 return -ETIMEDOUT;
58}
59EXPORT_SYMBOL(_il_poll_bit);
60
61void
62il_set_bit(struct il_priv *p, u32 r, u32 m)
63{
64 unsigned long reg_flags;
65
66 spin_lock_irqsave(&p->reg_lock, reg_flags);
67 _il_set_bit(p, r, m);
68 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
69}
70EXPORT_SYMBOL(il_set_bit);
71
72void
73il_clear_bit(struct il_priv *p, u32 r, u32 m)
74{
75 unsigned long reg_flags;
76
77 spin_lock_irqsave(&p->reg_lock, reg_flags);
78 _il_clear_bit(p, r, m);
79 spin_unlock_irqrestore(&p->reg_lock, reg_flags);
80}
81EXPORT_SYMBOL(il_clear_bit);
82
1e0f32a4 83bool
17d4eca6
SG		 84_il_grab_nic_access(struct il_priv *il)
85{
86 int ret;
87 u32 val;
88
89 /* this bit wakes up the NIC */
90 _il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
91
92 /*
93 * These bits say the device is running, and should keep running for
94 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
95 * but they do not indicate that embedded SRAM is restored yet;
96 * 3945 and 4965 have volatile SRAM, and must save/restore contents
97 * to/from host DRAM when sleeping/waking for power-saving.
98 * Each direction takes approximately 1/4 millisecond; with this
99 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
100 * series of register accesses are expected (e.g. reading Event Log),
101 * to keep device from sleeping.
102 *
103 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
104 * SRAM is okay/restored. We don't check that here because this call
105 * is just for hardware register access; but GP1 MAC_SLEEP check is a
106 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
107 *
108 */
109 ret =
110 _il_poll_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
111 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
112 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
b6603036 113 if (unlikely(ret < 0)) {
17d4eca6 114 val = _il_rd(il, CSR_GP_CNTRL);
b6603036
SG		 115 WARN_ONCE(1, "Timeout waiting for ucode processor access "
116 "(CSR_GP_CNTRL 0x%08x)\n", val);
17d4eca6 117 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1e0f32a4 118 return false;
17d4eca6
SG		 119 }
120
1e0f32a4 121 return true;
17d4eca6
SG		 122}
123EXPORT_SYMBOL_GPL(_il_grab_nic_access);
124
125int
126il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout)
127{
128 const int interval = 10; /* microseconds */
129 int t = 0;
130
131 do {
132 if ((il_rd(il, addr) & mask) == mask)
133 return t;
134 udelay(interval);
135 t += interval;
136 } while (t < timeout);
137
138 return -ETIMEDOUT;
139}
140EXPORT_SYMBOL(il_poll_bit);
141
142u32
143il_rd_prph(struct il_priv *il, u32 reg)
144{
145 unsigned long reg_flags;
146 u32 val;
147
148 spin_lock_irqsave(&il->reg_lock, reg_flags);
149 _il_grab_nic_access(il);
150 val = _il_rd_prph(il, reg);
151 _il_release_nic_access(il);
152 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
153 return val;
154}
155EXPORT_SYMBOL(il_rd_prph);
156
157void
158il_wr_prph(struct il_priv *il, u32 addr, u32 val)
159{
160 unsigned long reg_flags;
161
162 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 163 if (likely(_il_grab_nic_access(il))) {
17d4eca6
SG		 164 _il_wr_prph(il, addr, val);
165 _il_release_nic_access(il);
166 }
167 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
168}
169EXPORT_SYMBOL(il_wr_prph);
170
171u32
172il_read_targ_mem(struct il_priv *il, u32 addr)
173{
174 unsigned long reg_flags;
175 u32 value;
176
177 spin_lock_irqsave(&il->reg_lock, reg_flags);
178 _il_grab_nic_access(il);
179
180 _il_wr(il, HBUS_TARG_MEM_RADDR, addr);
17d4eca6
SG		 181 value = _il_rd(il, HBUS_TARG_MEM_RDAT);
182
183 _il_release_nic_access(il);
184 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
185 return value;
186}
187EXPORT_SYMBOL(il_read_targ_mem);
188
189void
190il_write_targ_mem(struct il_priv *il, u32 addr, u32 val)
191{
192 unsigned long reg_flags;
193
194 spin_lock_irqsave(&il->reg_lock, reg_flags);
1e0f32a4 195 if (likely(_il_grab_nic_access(il))) {
17d4eca6 196 _il_wr(il, HBUS_TARG_MEM_WADDR, addr);
17d4eca6
SG		 197 _il_wr(il, HBUS_TARG_MEM_WDAT, val);
198 _il_release_nic_access(il);
199 }
200 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
201}
202EXPORT_SYMBOL(il_write_targ_mem);
203
e7392364
SG		 204const char *
205il_get_cmd_string(u8 cmd)
0cdc2136
SG		 206{
207 switch (cmd) {
208 IL_CMD(N_ALIVE);
209 IL_CMD(N_ERROR);
210 IL_CMD(C_RXON);
211 IL_CMD(C_RXON_ASSOC);
212 IL_CMD(C_QOS_PARAM);
213 IL_CMD(C_RXON_TIMING);
214 IL_CMD(C_ADD_STA);
215 IL_CMD(C_REM_STA);
216 IL_CMD(C_WEPKEY);
217 IL_CMD(N_3945_RX);
218 IL_CMD(C_TX);
219 IL_CMD(C_RATE_SCALE);
220 IL_CMD(C_LEDS);
221 IL_CMD(C_TX_LINK_QUALITY_CMD);
222 IL_CMD(C_CHANNEL_SWITCH);
223 IL_CMD(N_CHANNEL_SWITCH);
224 IL_CMD(C_SPECTRUM_MEASUREMENT);
225 IL_CMD(N_SPECTRUM_MEASUREMENT);
226 IL_CMD(C_POWER_TBL);
227 IL_CMD(N_PM_SLEEP);
228 IL_CMD(N_PM_DEBUG_STATS);
229 IL_CMD(C_SCAN);
230 IL_CMD(C_SCAN_ABORT);
231 IL_CMD(N_SCAN_START);
232 IL_CMD(N_SCAN_RESULTS);
233 IL_CMD(N_SCAN_COMPLETE);
234 IL_CMD(N_BEACON);
235 IL_CMD(C_TX_BEACON);
236 IL_CMD(C_TX_PWR_TBL);
237 IL_CMD(C_BT_CONFIG);
238 IL_CMD(C_STATS);
239 IL_CMD(N_STATS);
240 IL_CMD(N_CARD_STATE);
241 IL_CMD(N_MISSED_BEACONS);
242 IL_CMD(C_CT_KILL_CONFIG);
243 IL_CMD(C_SENSITIVITY);
244 IL_CMD(C_PHY_CALIBRATION);
245 IL_CMD(N_RX_PHY);
246 IL_CMD(N_RX_MPDU);
247 IL_CMD(N_RX);
248 IL_CMD(N_COMPRESSED_BA);
249 default:
250 return "UNKNOWN";
251
252 }
253}
254EXPORT_SYMBOL(il_get_cmd_string);
255
256#define HOST_COMPLETE_TIMEOUT (HZ / 2)
257
e7392364
SG		 258static void
259il_generic_cmd_callback(struct il_priv *il, struct il_device_cmd *cmd,
260 struct il_rx_pkt *pkt)
0cdc2136
SG		 261{
262 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
263 IL_ERR("Bad return from %s (0x%08X)\n",
e7392364 264 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 265 return;
266 }
0cdc2136
SG		 267#ifdef CONFIG_IWLEGACY_DEBUG
268 switch (cmd->hdr.cmd) {
269 case C_TX_LINK_QUALITY_CMD:
270 case C_SENSITIVITY:
271 D_HC_DUMP("back from %s (0x%08X)\n",
e7392364 272 il_get_cmd_string(cmd->hdr.cmd), pkt->hdr.flags);
0cdc2136
SG		 273 break;
274 default:
e7392364
SG		 275 D_HC("back from %s (0x%08X)\n", il_get_cmd_string(cmd->hdr.cmd),
276 pkt->hdr.flags);
0cdc2136
SG		 277 }
278#endif
279}
280
281static int
282il_send_cmd_async(struct il_priv *il, struct il_host_cmd *cmd)
283{
284 int ret;
285
286 BUG_ON(!(cmd->flags & CMD_ASYNC));
287
288 /* An asynchronous command can not expect an SKB to be set. */
289 BUG_ON(cmd->flags & CMD_WANT_SKB);
290
291 /* Assign a generic callback if one is not provided */
292 if (!cmd->callback)
293 cmd->callback = il_generic_cmd_callback;
294
295 if (test_bit(S_EXIT_PENDING, &il->status))
296 return -EBUSY;
297
298 ret = il_enqueue_hcmd(il, cmd);
299 if (ret < 0) {
300 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 301 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 302 return ret;
303 }
304 return 0;
305}
306
e7392364
SG		 307int
308il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 309{
310 int cmd_idx;
311 int ret;
312
313 lockdep_assert_held(&il->mutex);
314
315 BUG_ON(cmd->flags & CMD_ASYNC);
316
e7392364 317 /* A synchronous command can not have a callback set. */
0cdc2136
SG		 318 BUG_ON(cmd->callback);
319
320 D_INFO("Attempting to send sync command %s\n",
e7392364 321 il_get_cmd_string(cmd->id));
0cdc2136
SG		 322
323 set_bit(S_HCMD_ACTIVE, &il->status);
324 D_INFO("Setting HCMD_ACTIVE for command %s\n",
e7392364 325 il_get_cmd_string(cmd->id));
0cdc2136
SG		 326
327 cmd_idx = il_enqueue_hcmd(il, cmd);
328 if (cmd_idx < 0) {
329 ret = cmd_idx;
330 IL_ERR("Error sending %s: enqueue_hcmd failed: %d\n",
e7392364 331 il_get_cmd_string(cmd->id), ret);
0cdc2136
SG		 332 goto out;
333 }
334
335 ret = wait_event_timeout(il->wait_command_queue,
e7392364
SG		 336 !test_bit(S_HCMD_ACTIVE, &il->status),
337 HOST_COMPLETE_TIMEOUT);
0cdc2136
SG		 338 if (!ret) {
339 if (test_bit(S_HCMD_ACTIVE, &il->status)) {
e7392364
SG		 340 IL_ERR("Error sending %s: time out after %dms.\n",
341 il_get_cmd_string(cmd->id),
342 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
0cdc2136
SG		 343
344 clear_bit(S_HCMD_ACTIVE, &il->status);
e7392364
SG		 345 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
346 il_get_cmd_string(cmd->id));
0cdc2136
SG		 347 ret = -ETIMEDOUT;
348 goto cancel;
349 }
350 }
351
bc269a8e 352 if (test_bit(S_RFKILL, &il->status)) {
0cdc2136 353 IL_ERR("Command %s aborted: RF KILL Switch\n",
e7392364 354 il_get_cmd_string(cmd->id));
0cdc2136
SG		 355 ret = -ECANCELED;
356 goto fail;
357 }
358 if (test_bit(S_FW_ERROR, &il->status)) {
359 IL_ERR("Command %s failed: FW Error\n",
e7392364 360 il_get_cmd_string(cmd->id));
0cdc2136
SG		 361 ret = -EIO;
362 goto fail;
363 }
364 if ((cmd->flags & CMD_WANT_SKB) && !cmd->reply_page) {
365 IL_ERR("Error: Response NULL in '%s'\n",
e7392364 366 il_get_cmd_string(cmd->id));
0cdc2136
SG		 367 ret = -EIO;
368 goto cancel;
369 }
370
371 ret = 0;
372 goto out;
373
374cancel:
375 if (cmd->flags & CMD_WANT_SKB) {
376 /*
377 * Cancel the CMD_WANT_SKB flag for the cmd in the
378 * TX cmd queue. Otherwise in case the cmd comes
379 * in later, it will possibly set an invalid
380 * address (cmd->meta.source).
381 */
e7392364 382 il->txq[il->cmd_queue].meta[cmd_idx].flags &= ~CMD_WANT_SKB;
0cdc2136
SG		 383 }
384fail:
385 if (cmd->reply_page) {
386 il_free_pages(il, cmd->reply_page);
387 cmd->reply_page = 0;
388 }
389out:
390 return ret;
391}
392EXPORT_SYMBOL(il_send_cmd_sync);
393
e7392364
SG		 394int
395il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 396{
397 if (cmd->flags & CMD_ASYNC)
398 return il_send_cmd_async(il, cmd);
399
400 return il_send_cmd_sync(il, cmd);
401}
402EXPORT_SYMBOL(il_send_cmd);
403
404int
405il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len, const void *data)
406{
407 struct il_host_cmd cmd = {
408 .id = id,
409 .len = len,
410 .data = data,
411 };
412
413 return il_send_cmd_sync(il, &cmd);
414}
415EXPORT_SYMBOL(il_send_cmd_pdu);
416
e7392364
SG		 417int
418il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1722f8e1
SG		 419 void (*callback) (struct il_priv *il,
420 struct il_device_cmd *cmd,
421 struct il_rx_pkt *pkt))
0cdc2136
SG		 422{
423 struct il_host_cmd cmd = {
424 .id = id,
425 .len = len,
426 .data = data,
427 };
428
429 cmd.flags |= CMD_ASYNC;
430 cmd.callback = callback;
431
432 return il_send_cmd_async(il, &cmd);
433}
434EXPORT_SYMBOL(il_send_cmd_pdu_async);
435
436/* default: IL_LED_BLINK(0) using blinking idx table */
437static int led_mode;
438module_param(led_mode, int, S_IRUGO);
e7392364
SG		 439MODULE_PARM_DESC(led_mode,
440 "0=system default, " "1=On(RF On)/Off(RF Off), 2=blinking");
0cdc2136
SG		 441
442/* Throughput OFF time(ms) ON time (ms)
443 * >300 25 25
444 * >200 to 300 40 40
445 * >100 to 200 55 55
446 * >70 to 100 65 65
447 * >50 to 70 75 75
448 * >20 to 50 85 85
449 * >10 to 20 95 95
450 * >5 to 10 110 110
451 * >1 to 5 130 130
452 * >0 to 1 167 167
453 * <=0 SOLID ON
454 */
455static const struct ieee80211_tpt_blink il_blink[] = {
1722f8e1
SG		 456 {.throughput = 0, .blink_time = 334},
457 {.throughput = 1 * 1024 - 1, .blink_time = 260},
458 {.throughput = 5 * 1024 - 1, .blink_time = 220},
459 {.throughput = 10 * 1024 - 1, .blink_time = 190},
460 {.throughput = 20 * 1024 - 1, .blink_time = 170},
461 {.throughput = 50 * 1024 - 1, .blink_time = 150},
462 {.throughput = 70 * 1024 - 1, .blink_time = 130},
463 {.throughput = 100 * 1024 - 1, .blink_time = 110},
464 {.throughput = 200 * 1024 - 1, .blink_time = 80},
465 {.throughput = 300 * 1024 - 1, .blink_time = 50},
0cdc2136
SG		 466};
467
468/*
469 * Adjust led blink rate to compensate on a MAC Clock difference on every HW
470 * Led blink rate analysis showed an average deviation of 0% on 3945,
471 * 5% on 4965 HW.
472 * Need to compensate on the led on/off time per HW according to the deviation
473 * to achieve the desired led frequency
474 * The calculation is: (100-averageDeviation)/100 * blinkTime
475 * For code efficiency the calculation will be:
476 * compensation = (100 - averageDeviation) * 64 / 100
477 * NewBlinkTime = (compensation * BlinkTime) / 64
478 */
e7392364
SG		 479static inline u8
480il_blink_compensation(struct il_priv *il, u8 time, u16 compensation)
0cdc2136
SG		 481{
482 if (!compensation) {
483 IL_ERR("undefined blink compensation: "
e7392364 484 "use pre-defined blinking time\n");
0cdc2136
SG		 485 return time;
486 }
487
e7392364 488 return (u8) ((time * compensation) >> 6);
0cdc2136
SG		 489}
490
491/* Set led pattern command */
e7392364
SG		 492static int
493il_led_cmd(struct il_priv *il, unsigned long on, unsigned long off)
0cdc2136
SG		 494{
495 struct il_led_cmd led_cmd = {
496 .id = IL_LED_LINK,
497 .interval = IL_DEF_LED_INTRVL
498 };
499 int ret;
500
501 if (!test_bit(S_READY, &il->status))
502 return -EBUSY;
503
504 if (il->blink_on == on && il->blink_off == off)
505 return 0;
506
507 if (off == 0) {
508 /* led is SOLID_ON */
509 on = IL_LED_SOLID;
510 }
511
512 D_LED("Led blink time compensation=%u\n",
89ef1ed2 513 il->cfg->led_compensation);
e7392364
SG		 514 led_cmd.on =
515 il_blink_compensation(il, on,
89ef1ed2 516 il->cfg->led_compensation);
e7392364
SG		 517 led_cmd.off =
518 il_blink_compensation(il, off,
89ef1ed2 519 il->cfg->led_compensation);
0cdc2136 520
c9363551 521 ret = il->ops->send_led_cmd(il, &led_cmd);
0cdc2136
SG		 522 if (!ret) {
523 il->blink_on = on;
524 il->blink_off = off;
525 }
526 return ret;
527}
528
e7392364
SG		 529static void
530il_led_brightness_set(struct led_classdev *led_cdev,
531 enum led_brightness brightness)
0cdc2136
SG		 532{
533 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
534 unsigned long on = 0;
535
536 if (brightness > 0)
537 on = IL_LED_SOLID;
538
539 il_led_cmd(il, on, 0);
540}
541
e7392364
SG		 542static int
543il_led_blink_set(struct led_classdev *led_cdev, unsigned long *delay_on,
544 unsigned long *delay_off)
0cdc2136
SG		 545{
546 struct il_priv *il = container_of(led_cdev, struct il_priv, led);
547
548 return il_led_cmd(il, *delay_on, *delay_off);
549}
550
e7392364
SG		 551void
552il_leds_init(struct il_priv *il)
0cdc2136
SG		 553{
554 int mode = led_mode;
555 int ret;
556
557 if (mode == IL_LED_DEFAULT)
558 mode = il->cfg->led_mode;
559
e7392364
SG		 560 il->led.name =
561 kasprintf(GFP_KERNEL, "%s-led", wiphy_name(il->hw->wiphy));
0cdc2136
SG		 562 il->led.brightness_set = il_led_brightness_set;
563 il->led.blink_set = il_led_blink_set;
564 il->led.max_brightness = 1;
565
566 switch (mode) {
567 case IL_LED_DEFAULT:
568 WARN_ON(1);
569 break;
570 case IL_LED_BLINK:
571 il->led.default_trigger =
e7392364
SG		 572 ieee80211_create_tpt_led_trigger(il->hw,
573 IEEE80211_TPT_LEDTRIG_FL_CONNECTED,
574 il_blink,
575 ARRAY_SIZE(il_blink));
0cdc2136
SG		 576 break;
577 case IL_LED_RF_STATE:
e7392364 578 il->led.default_trigger = ieee80211_get_radio_led_name(il->hw);
0cdc2136
SG		 579 break;
580 }
581
582 ret = led_classdev_register(&il->pci_dev->dev, &il->led);
583 if (ret) {
584 kfree(il->led.name);
585 return;
586 }
587
588 il->led_registered = true;
589}
590EXPORT_SYMBOL(il_leds_init);
591
e7392364
SG		 592void
593il_leds_exit(struct il_priv *il)
0cdc2136
SG		 594{
595 if (!il->led_registered)
596 return;
597
598 led_classdev_unregister(&il->led);
599 kfree(il->led.name);
600}
601EXPORT_SYMBOL(il_leds_exit);
602
603/************************** EEPROM BANDS ****************************
604 *
605 * The il_eeprom_band definitions below provide the mapping from the
606 * EEPROM contents to the specific channel number supported for each
607 * band.
608 *
609 * For example, il_priv->eeprom.band_3_channels[4] from the band_3
610 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
611 * The specific geography and calibration information for that channel
612 * is contained in the eeprom map itself.
613 *
614 * During init, we copy the eeprom information and channel map
615 * information into il->channel_info_24/52 and il->channel_map_24/52
616 *
617 * channel_map_24/52 provides the idx in the channel_info array for a
618 * given channel. We have to have two separate maps as there is channel
619 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
620 * band_2
621 *
622 * A value of 0xff stored in the channel_map indicates that the channel
623 * is not supported by the hardware at all.
624 *
625 * A value of 0xfe in the channel_map indicates that the channel is not
626 * valid for Tx with the current hardware. This means that
627 * while the system can tune and receive on a given channel, it may not
628 * be able to associate or transmit any frames on that
629 * channel. There is no corresponding channel information for that
630 * entry.
631 *
632 *********************************************************************/
633
634/* 2.4 GHz */
635const u8 il_eeprom_band_1[14] = {
636 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
637};
638
639/* 5.2 GHz bands */
640static const u8 il_eeprom_band_2[] = { /* 4915-5080MHz */
641 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
642};
643
644static const u8 il_eeprom_band_3[] = { /* 5170-5320MHz */
645 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
646};
647
648static const u8 il_eeprom_band_4[] = { /* 5500-5700MHz */
649 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
650};
651
652static const u8 il_eeprom_band_5[] = { /* 5725-5825MHz */
653 145, 149, 153, 157, 161, 165
654};
655
e7392364 656static const u8 il_eeprom_band_6[] = { /* 2.4 ht40 channel */
0cdc2136
SG		 657 1, 2, 3, 4, 5, 6, 7
658};
659
e7392364 660static const u8 il_eeprom_band_7[] = { /* 5.2 ht40 channel */
0cdc2136
SG		 661 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
662};
663
664/******************************************************************************
665 *
666 * EEPROM related functions
667 *
668******************************************************************************/
669
e7392364
SG		 670static int
671il_eeprom_verify_signature(struct il_priv *il)
0cdc2136
SG		 672{
673 u32 gp = _il_rd(il, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK;
674 int ret = 0;
675
676 D_EEPROM("EEPROM signature=0x%08x\n", gp);
677 switch (gp) {
678 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K:
679 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K:
680 break;
681 default:
e7392364 682 IL_ERR("bad EEPROM signature," "EEPROM_GP=0x%08x\n", gp);
0cdc2136
SG		 683 ret = -ENOENT;
684 break;
685 }
686 return ret;
687}
688
e7392364
SG		 689const u8 *
690il_eeprom_query_addr(const struct il_priv *il, size_t offset)
0cdc2136 691{
89ef1ed2 692 BUG_ON(offset >= il->cfg->eeprom_size);
0cdc2136
SG		 693 return &il->eeprom[offset];
694}
695EXPORT_SYMBOL(il_eeprom_query_addr);
696
e7392364 697u16
1722f8e1 698il_eeprom_query16(const struct il_priv *il, size_t offset)
0cdc2136
SG		 699{
700 if (!il->eeprom)
701 return 0;
e7392364 702 return (u16) il->eeprom[offset] | ((u16) il->eeprom[offset + 1] << 8);
0cdc2136
SG		 703}
704EXPORT_SYMBOL(il_eeprom_query16);
705
706/**
707 * il_eeprom_init - read EEPROM contents
708 *
709 * Load the EEPROM contents from adapter into il->eeprom
710 *
711 * NOTE: This routine uses the non-debug IO access functions.
712 */
e7392364
SG		 713int
714il_eeprom_init(struct il_priv *il)
0cdc2136
SG		 715{
716 __le16 *e;
717 u32 gp = _il_rd(il, CSR_EEPROM_GP);
718 int sz;
719 int ret;
720 u16 addr;
721
722 /* allocate eeprom */
89ef1ed2 723 sz = il->cfg->eeprom_size;
0cdc2136
SG		 724 D_EEPROM("NVM size = %d\n", sz);
725 il->eeprom = kzalloc(sz, GFP_KERNEL);
fb9693f0
ME		 726 if (!il->eeprom)
727 return -ENOMEM;
728
e7392364 729 e = (__le16 *) il->eeprom;
0cdc2136 730
1600b875 731 il->ops->apm_init(il);
0cdc2136
SG		 732
733 ret = il_eeprom_verify_signature(il);
734 if (ret < 0) {
735 IL_ERR("EEPROM not found, EEPROM_GP=0x%08x\n", gp);
736 ret = -ENOENT;
737 goto err;
738 }
739
740 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
1600b875 741 ret = il->ops->eeprom_acquire_semaphore(il);
0cdc2136
SG		 742 if (ret < 0) {
743 IL_ERR("Failed to acquire EEPROM semaphore.\n");
744 ret = -ENOENT;
745 goto err;
746 }
747
748 /* eeprom is an array of 16bit values */
749 for (addr = 0; addr < sz; addr += sizeof(u16)) {
750 u32 r;
751
752 _il_wr(il, CSR_EEPROM_REG,
e7392364 753 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
0cdc2136 754
e7392364
SG		 755 ret =
756 _il_poll_bit(il, CSR_EEPROM_REG,
757 CSR_EEPROM_REG_READ_VALID_MSK,
758 CSR_EEPROM_REG_READ_VALID_MSK,
759 IL_EEPROM_ACCESS_TIMEOUT);
0cdc2136 760 if (ret < 0) {
e7392364 761 IL_ERR("Time out reading EEPROM[%d]\n", addr);
0cdc2136
SG		 762 goto done;
763 }
764 r = _il_rd(il, CSR_EEPROM_REG);
765 e[addr / 2] = cpu_to_le16(r >> 16);
766 }
767
e7392364
SG		 768 D_EEPROM("NVM Type: %s, version: 0x%x\n", "EEPROM",
769 il_eeprom_query16(il, EEPROM_VERSION));
0cdc2136
SG		 770
771 ret = 0;
772done:
1600b875 773 il->ops->eeprom_release_semaphore(il);
0cdc2136
SG		 774
775err:
776 if (ret)
777 il_eeprom_free(il);
778 /* Reset chip to save power until we load uCode during "up". */
779 il_apm_stop(il);
0cdc2136
SG		 780 return ret;
781}
782EXPORT_SYMBOL(il_eeprom_init);
783
e7392364
SG		 784void
785il_eeprom_free(struct il_priv *il)
0cdc2136
SG		 786{
787 kfree(il->eeprom);
788 il->eeprom = NULL;
789}
790EXPORT_SYMBOL(il_eeprom_free);
791
e7392364
SG		 792static void
793il_init_band_reference(const struct il_priv *il, int eep_band,
794 int *eeprom_ch_count,
795 const struct il_eeprom_channel **eeprom_ch_info,
1722f8e1 796 const u8 **eeprom_ch_idx)
0cdc2136 797{
93a984a4
SG		 798 u32 offset = il->cfg->regulatory_bands[eep_band - 1];
799
0cdc2136
SG		 800 switch (eep_band) {
801 case 1: /* 2.4GHz band */
802 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_1);
e7392364
SG		 803 *eeprom_ch_info =
804 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
805 offset);
0cdc2136
SG		 806 *eeprom_ch_idx = il_eeprom_band_1;
807 break;
808 case 2: /* 4.9GHz band */
809 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_2);
e7392364
SG		 810 *eeprom_ch_info =
811 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
812 offset);
0cdc2136
SG		 813 *eeprom_ch_idx = il_eeprom_band_2;
814 break;
815 case 3: /* 5.2GHz band */
816 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_3);
e7392364
SG		 817 *eeprom_ch_info =
818 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
819 offset);
0cdc2136
SG		 820 *eeprom_ch_idx = il_eeprom_band_3;
821 break;
822 case 4: /* 5.5GHz band */
823 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_4);
e7392364
SG		 824 *eeprom_ch_info =
825 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
826 offset);
0cdc2136
SG		 827 *eeprom_ch_idx = il_eeprom_band_4;
828 break;
829 case 5: /* 5.7GHz band */
830 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_5);
e7392364
SG		 831 *eeprom_ch_info =
832 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
833 offset);
0cdc2136
SG		 834 *eeprom_ch_idx = il_eeprom_band_5;
835 break;
836 case 6: /* 2.4GHz ht40 channels */
837 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_6);
e7392364
SG		 838 *eeprom_ch_info =
839 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
840 offset);
0cdc2136
SG		 841 *eeprom_ch_idx = il_eeprom_band_6;
842 break;
843 case 7: /* 5 GHz ht40 channels */
844 *eeprom_ch_count = ARRAY_SIZE(il_eeprom_band_7);
e7392364
SG		 845 *eeprom_ch_info =
846 (struct il_eeprom_channel *)il_eeprom_query_addr(il,
847 offset);
0cdc2136
SG		 848 *eeprom_ch_idx = il_eeprom_band_7;
849 break;
850 default:
851 BUG();
852 }
853}
854
855#define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
856 ? # x " " : "")
857/**
858 * il_mod_ht40_chan_info - Copy ht40 channel info into driver's il.
859 *
860 * Does not set up a command, or touch hardware.
861 */
e7392364
SG		 862static int
863il_mod_ht40_chan_info(struct il_priv *il, enum ieee80211_band band, u16 channel,
864 const struct il_eeprom_channel *eeprom_ch,
865 u8 clear_ht40_extension_channel)
0cdc2136
SG		 866{
867 struct il_channel_info *ch_info;
868
e7392364
SG		 869 ch_info =
870 (struct il_channel_info *)il_get_channel_info(il, band, channel);
0cdc2136
SG		 871
872 if (!il_is_channel_valid(ch_info))
873 return -1;
874
875 D_EEPROM("HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
e7392364
SG		 876 " Ad-Hoc %ssupported\n", ch_info->channel,
877 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
878 CHECK_AND_PRINT(IBSS), CHECK_AND_PRINT(ACTIVE),
879 CHECK_AND_PRINT(RADAR), CHECK_AND_PRINT(WIDE),
880 CHECK_AND_PRINT(DFS), eeprom_ch->flags,
881 eeprom_ch->max_power_avg,
882 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) &&
883 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" : "not ");
0cdc2136
SG		 884
885 ch_info->ht40_eeprom = *eeprom_ch;
886 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
887 ch_info->ht40_flags = eeprom_ch->flags;
888 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID)
889 ch_info->ht40_extension_channel &=
e7392364 890 ~clear_ht40_extension_channel;
0cdc2136
SG		 891
892 return 0;
893}
894
895#define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
896 ? # x " " : "")
897
898/**
899 * il_init_channel_map - Set up driver's info for all possible channels
900 */
e7392364
SG		 901int
902il_init_channel_map(struct il_priv *il)
0cdc2136
SG		 903{
904 int eeprom_ch_count = 0;
905 const u8 *eeprom_ch_idx = NULL;
906 const struct il_eeprom_channel *eeprom_ch_info = NULL;
907 int band, ch;
908 struct il_channel_info *ch_info;
909
910 if (il->channel_count) {
911 D_EEPROM("Channel map already initialized.\n");
912 return 0;
913 }
914
915 D_EEPROM("Initializing regulatory info from EEPROM\n");
916
917 il->channel_count =
e7392364
SG		 918 ARRAY_SIZE(il_eeprom_band_1) + ARRAY_SIZE(il_eeprom_band_2) +
919 ARRAY_SIZE(il_eeprom_band_3) + ARRAY_SIZE(il_eeprom_band_4) +
0cdc2136
SG		 920 ARRAY_SIZE(il_eeprom_band_5);
921
e7392364 922 D_EEPROM("Parsing data for %d channels.\n", il->channel_count);
0cdc2136 923
e7392364
SG		 924 il->channel_info =
925 kzalloc(sizeof(struct il_channel_info) * il->channel_count,
926 GFP_KERNEL);
0cdc2136
SG		 927 if (!il->channel_info) {
928 IL_ERR("Could not allocate channel_info\n");
929 il->channel_count = 0;
930 return -ENOMEM;
931 }
932
933 ch_info = il->channel_info;
934
935 /* Loop through the 5 EEPROM bands adding them in order to the
936 * channel map we maintain (that contains additional information than
937 * what just in the EEPROM) */
938 for (band = 1; band <= 5; band++) {
939
940 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 941 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 942
943 /* Loop through each band adding each of the channels */
944 for (ch = 0; ch < eeprom_ch_count; ch++) {
945 ch_info->channel = eeprom_ch_idx[ch];
e7392364
SG		 946 ch_info->band =
947 (band ==
948 1) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 949
950 /* permanently store EEPROM's channel regulatory flags
951 * and max power in channel info database. */
952 ch_info->eeprom = eeprom_ch_info[ch];
953
954 /* Copy the run-time flags so they are there even on
955 * invalid channels */
956 ch_info->flags = eeprom_ch_info[ch].flags;
957 /* First write that ht40 is not enabled, and then enable
958 * one by one */
959 ch_info->ht40_extension_channel =
e7392364 960 IEEE80211_CHAN_NO_HT40;
0cdc2136
SG		 961
962 if (!(il_is_channel_valid(ch_info))) {
e7392364
SG		 963 D_EEPROM("Ch. %d Flags %x [%sGHz] - "
964 "No traffic\n", ch_info->channel,
965 ch_info->flags,
966 il_is_channel_a_band(ch_info) ? "5.2" :
967 "2.4");
0cdc2136
SG		 968 ch_info++;
969 continue;
970 }
971
972 /* Initialize regulatory-based run-time data */
973 ch_info->max_power_avg = ch_info->curr_txpow =
974 eeprom_ch_info[ch].max_power_avg;
975 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
976 ch_info->min_power = 0;
977
e7392364
SG		 978 D_EEPROM("Ch. %d [%sGHz] " "%s%s%s%s%s%s(0x%02x %ddBm):"
979 " Ad-Hoc %ssupported\n", ch_info->channel,
980 il_is_channel_a_band(ch_info) ? "5.2" : "2.4",
981 CHECK_AND_PRINT_I(VALID),
982 CHECK_AND_PRINT_I(IBSS),
983 CHECK_AND_PRINT_I(ACTIVE),
984 CHECK_AND_PRINT_I(RADAR),
985 CHECK_AND_PRINT_I(WIDE),
986 CHECK_AND_PRINT_I(DFS),
987 eeprom_ch_info[ch].flags,
988 eeprom_ch_info[ch].max_power_avg,
989 ((eeprom_ch_info[ch].
990 flags & EEPROM_CHANNEL_IBSS) &&
991 !(eeprom_ch_info[ch].
992 flags & EEPROM_CHANNEL_RADAR)) ? "" :
993 "not ");
0cdc2136
SG		 994
995 ch_info++;
996 }
997 }
998
999 /* Check if we do have HT40 channels */
93a984a4
SG		 1000 if (il->cfg->regulatory_bands[5] == EEPROM_REGULATORY_BAND_NO_HT40 &&
1001 il->cfg->regulatory_bands[6] == EEPROM_REGULATORY_BAND_NO_HT40)
0cdc2136
SG		 1002 return 0;
1003
1004 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
1005 for (band = 6; band <= 7; band++) {
1006 enum ieee80211_band ieeeband;
1007
1008 il_init_band_reference(il, band, &eeprom_ch_count,
e7392364 1009 &eeprom_ch_info, &eeprom_ch_idx);
0cdc2136
SG		 1010
1011 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
1012 ieeeband =
e7392364 1013 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
0cdc2136
SG		 1014
1015 /* Loop through each band adding each of the channels */
1016 for (ch = 0; ch < eeprom_ch_count; ch++) {
1017 /* Set up driver's info for lower half */
e7392364
SG		 1018 il_mod_ht40_chan_info(il, ieeeband, eeprom_ch_idx[ch],
1019 &eeprom_ch_info[ch],
1020 IEEE80211_CHAN_NO_HT40PLUS);
0cdc2136
SG		 1021
1022 /* Set up driver's info for upper half */
1023 il_mod_ht40_chan_info(il, ieeeband,
e7392364
SG		 1024 eeprom_ch_idx[ch] + 4,
1025 &eeprom_ch_info[ch],
1026 IEEE80211_CHAN_NO_HT40MINUS);
0cdc2136
SG		 1027 }
1028 }
1029
1030 return 0;
1031}
1032EXPORT_SYMBOL(il_init_channel_map);
1033
1034/*
1035 * il_free_channel_map - undo allocations in il_init_channel_map
1036 */
e7392364
SG		 1037void
1038il_free_channel_map(struct il_priv *il)
0cdc2136
SG		 1039{
1040 kfree(il->channel_info);
1041 il->channel_count = 0;
1042}
1043EXPORT_SYMBOL(il_free_channel_map);
1044
1045/**
1046 * il_get_channel_info - Find driver's ilate channel info
1047 *
1048 * Based on band and channel number.
1049 */
e7392364
SG		 1050const struct il_channel_info *
1051il_get_channel_info(const struct il_priv *il, enum ieee80211_band band,
1052 u16 channel)
0cdc2136
SG		 1053{
1054 int i;
1055
1056 switch (band) {
1057 case IEEE80211_BAND_5GHZ:
1058 for (i = 14; i < il->channel_count; i++) {
1059 if (il->channel_info[i].channel == channel)
1060 return &il->channel_info[i];
1061 }
1062 break;
1063 case IEEE80211_BAND_2GHZ:
1064 if (channel >= 1 && channel <= 14)
1065 return &il->channel_info[channel - 1];
1066 break;
1067 default:
1068 BUG();
1069 }
1070
1071 return NULL;
1072}
1073EXPORT_SYMBOL(il_get_channel_info);
1074
1075/*
1076 * Setting power level allows the card to go to sleep when not busy.
1077 *
1078 * We calculate a sleep command based on the required latency, which
dbdac2b5 1079 * we get from mac80211.
0cdc2136
SG		 1080 */
1081
dbdac2b5
SG		 1082#define SLP_VEC(X0, X1, X2, X3, X4) { \
1083 cpu_to_le32(X0), \
1084 cpu_to_le32(X1), \
1085 cpu_to_le32(X2), \
1086 cpu_to_le32(X3), \
1087 cpu_to_le32(X4) \
1088}
0cdc2136 1089
e7392364 1090static void
dbdac2b5 1091il_build_powertable_cmd(struct il_priv *il, struct il_powertable_cmd *cmd)
0cdc2136 1092{
dbdac2b5
SG		 1093 const __le32 interval[3][IL_POWER_VEC_SIZE] = {
1094 SLP_VEC(2, 2, 4, 6, 0xFF),
1095 SLP_VEC(2, 4, 7, 10, 10),
1096 SLP_VEC(4, 7, 10, 10, 0xFF)
1097 };
1098 int i, dtim_period, no_dtim;
1099 u32 max_sleep;
1100 bool skip;
1101
0cdc2136
SG		 1102 memset(cmd, 0, sizeof(*cmd));
1103
1104 if (il->power_data.pci_pm)
1105 cmd->flags |= IL_POWER_PCI_PM_MSK;
1106
dbdac2b5
SG		 1107 /* if no Power Save, we are done */
1108 if (il->power_data.ps_disabled)
1109 return;
1110
1111 cmd->flags = IL_POWER_DRIVER_ALLOW_SLEEP_MSK;
1112 cmd->keep_alive_seconds = 0;
1113 cmd->debug_flags = 0;
1114 cmd->rx_data_timeout = cpu_to_le32(25 * 1024);
1115 cmd->tx_data_timeout = cpu_to_le32(25 * 1024);
1116 cmd->keep_alive_beacons = 0;
1117
1118 dtim_period = il->vif ? il->vif->bss_conf.dtim_period : 0;
1119
1120 if (dtim_period <= 2) {
1121 memcpy(cmd->sleep_interval, interval[0], sizeof(interval[0]));
1122 no_dtim = 2;
1123 } else if (dtim_period <= 10) {
1124 memcpy(cmd->sleep_interval, interval[1], sizeof(interval[1]));
1125 no_dtim = 2;
1126 } else {
1127 memcpy(cmd->sleep_interval, interval[2], sizeof(interval[2]));
1128 no_dtim = 0;
1129 }
1130
1131 if (dtim_period == 0) {
1132 dtim_period = 1;
1133 skip = false;
1134 } else {
1135 skip = !!no_dtim;
1136 }
1137
1138 if (skip) {
1139 __le32 tmp = cmd->sleep_interval[IL_POWER_VEC_SIZE - 1];
1140
1141 max_sleep = le32_to_cpu(tmp);
1142 if (max_sleep == 0xFF)
1143 max_sleep = dtim_period * (skip + 1);
1144 else if (max_sleep > dtim_period)
1145 max_sleep = (max_sleep / dtim_period) * dtim_period;
1146 cmd->flags |= IL_POWER_SLEEP_OVER_DTIM_MSK;
1147 } else {
1148 max_sleep = dtim_period;
1149 cmd->flags &= ~IL_POWER_SLEEP_OVER_DTIM_MSK;
1150 }
1151
1152 for (i = 0; i < IL_POWER_VEC_SIZE; i++)
1153 if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
1154 cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
0cdc2136
SG		 1155}
1156
1157static int
1158il_set_power(struct il_priv *il, struct il_powertable_cmd *cmd)
1159{
1160 D_POWER("Sending power/sleep command\n");
1161 D_POWER("Flags value = 0x%08X\n", cmd->flags);
e7392364
SG		 1162 D_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
1163 D_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
1164 D_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
1165 le32_to_cpu(cmd->sleep_interval[0]),
1166 le32_to_cpu(cmd->sleep_interval[1]),
1167 le32_to_cpu(cmd->sleep_interval[2]),
1168 le32_to_cpu(cmd->sleep_interval[3]),
1169 le32_to_cpu(cmd->sleep_interval[4]));
0cdc2136
SG		 1170
1171 return il_send_cmd_pdu(il, C_POWER_TBL,
e7392364 1172 sizeof(struct il_powertable_cmd), cmd);
0cdc2136
SG		 1173}
1174
60c46bf8 1175static int
e7392364 1176il_power_set_mode(struct il_priv *il, struct il_powertable_cmd *cmd, bool force)
0cdc2136
SG		 1177{
1178 int ret;
1179 bool update_chains;
1180
1181 lockdep_assert_held(&il->mutex);
1182
1183 /* Don't update the RX chain when chain noise calibration is running */
1184 update_chains = il->chain_noise_data.state == IL_CHAIN_NOISE_DONE ||
e7392364 1185 il->chain_noise_data.state == IL_CHAIN_NOISE_ALIVE;
0cdc2136
SG		 1186
1187 if (!memcmp(&il->power_data.sleep_cmd, cmd, sizeof(*cmd)) && !force)
1188 return 0;
1189
1190 if (!il_is_ready_rf(il))
1191 return -EIO;
1192
1193 /* scan complete use sleep_power_next, need to be updated */
1194 memcpy(&il->power_data.sleep_cmd_next, cmd, sizeof(*cmd));
1195 if (test_bit(S_SCANNING, &il->status) && !force) {
1196 D_INFO("Defer power set mode while scanning\n");
1197 return 0;
1198 }
1199
1200 if (cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK)
1201 set_bit(S_POWER_PMI, &il->status);
1202
1203 ret = il_set_power(il, cmd);
1204 if (!ret) {
1205 if (!(cmd->flags & IL_POWER_DRIVER_ALLOW_SLEEP_MSK))
1206 clear_bit(S_POWER_PMI, &il->status);
1207
1600b875
SG		 1208 if (il->ops->update_chain_flags && update_chains)
1209 il->ops->update_chain_flags(il);
1210 else if (il->ops->update_chain_flags)
e7392364
SG		 1211 D_POWER("Cannot update the power, chain noise "
1212 "calibration running: %d\n",
1213 il->chain_noise_data.state);
0cdc2136
SG		 1214
1215 memcpy(&il->power_data.sleep_cmd, cmd, sizeof(*cmd));
1216 } else
1217 IL_ERR("set power fail, ret = %d", ret);
1218
1219 return ret;
1220}
1221
e7392364
SG		 1222int
1223il_power_update_mode(struct il_priv *il, bool force)
0cdc2136
SG		 1224{
1225 struct il_powertable_cmd cmd;
1226
dbdac2b5
SG		 1227 il_build_powertable_cmd(il, &cmd);
1228
0cdc2136
SG		 1229 return il_power_set_mode(il, &cmd, force);
1230}
1231EXPORT_SYMBOL(il_power_update_mode);
1232
1233/* initialize to default */
e7392364
SG		 1234void
1235il_power_initialize(struct il_priv *il)
0cdc2136 1236{
94e15613 1237 u16 lctl;
0cdc2136 1238
94e15613 1239 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
f93eaffc 1240 il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
0cdc2136
SG		 1241
1242 il->power_data.debug_sleep_level_override = -1;
1243
e7392364 1244 memset(&il->power_data.sleep_cmd, 0, sizeof(il->power_data.sleep_cmd));
0cdc2136
SG		 1245}
1246EXPORT_SYMBOL(il_power_initialize);
1247
1248/* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
1249 * sending probe req. This should be set long enough to hear probe responses
1250 * from more than one AP. */
e7392364 1251#define IL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
0cdc2136
SG		 1252#define IL_ACTIVE_DWELL_TIME_52 (20)
1253
1254#define IL_ACTIVE_DWELL_FACTOR_24GHZ (3)
1255#define IL_ACTIVE_DWELL_FACTOR_52GHZ (2)
1256
1257/* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
1258 * Must be set longer than active dwell time.
1259 * For the most reliable scan, set > AP beacon interval (typically 100msec). */
e7392364 1260#define IL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
0cdc2136
SG		 1261#define IL_PASSIVE_DWELL_TIME_52 (10)
1262#define IL_PASSIVE_DWELL_BASE (100)
1263#define IL_CHANNEL_TUNE_TIME 5
1264
e7392364
SG		 1265static int
1266il_send_scan_abort(struct il_priv *il)
0cdc2136
SG		 1267{
1268 int ret;
1269 struct il_rx_pkt *pkt;
1270 struct il_host_cmd cmd = {
1271 .id = C_SCAN_ABORT,
1272 .flags = CMD_WANT_SKB,
1273 };
1274
1275 /* Exit instantly with error when device is not ready
1276 * to receive scan abort command or it does not perform
1277 * hardware scan currently */
1278 if (!test_bit(S_READY, &il->status) ||
1279 !test_bit(S_GEO_CONFIGURED, &il->status) ||
1280 !test_bit(S_SCAN_HW, &il->status) ||
1281 test_bit(S_FW_ERROR, &il->status) ||
1282 test_bit(S_EXIT_PENDING, &il->status))
1283 return -EIO;
1284
1285 ret = il_send_cmd_sync(il, &cmd);
1286 if (ret)
1287 return ret;
1288
1289 pkt = (struct il_rx_pkt *)cmd.reply_page;
1290 if (pkt->u.status != CAN_ABORT_STATUS) {
1291 /* The scan abort will return 1 for success or
1292 * 2 for "failure". A failure condition can be
1293 * due to simply not being in an active scan which
1294 * can occur if we send the scan abort before we
1295 * the microcode has notified us that a scan is
1296 * completed. */
1297 D_SCAN("SCAN_ABORT ret %d.\n", pkt->u.status);
1298 ret = -EIO;
1299 }
1300
1301 il_free_pages(il, cmd.reply_page);
1302 return ret;
1303}
1304
e7392364
SG		 1305static void
1306il_complete_scan(struct il_priv *il, bool aborted)
0cdc2136
SG		 1307{
1308 /* check if scan was requested from mac80211 */
1309 if (il->scan_request) {
1310 D_SCAN("Complete scan in mac80211\n");
1311 ieee80211_scan_completed(il->hw, aborted);
1312 }
1313
1314 il->scan_vif = NULL;
1315 il->scan_request = NULL;
1316}
1317
e7392364
SG		 1318void
1319il_force_scan_end(struct il_priv *il)
0cdc2136
SG		 1320{
1321 lockdep_assert_held(&il->mutex);
1322
1323 if (!test_bit(S_SCANNING, &il->status)) {
1324 D_SCAN("Forcing scan end while not scanning\n");
1325 return;
1326 }
1327
1328 D_SCAN("Forcing scan end\n");
1329 clear_bit(S_SCANNING, &il->status);
1330 clear_bit(S_SCAN_HW, &il->status);
1331 clear_bit(S_SCAN_ABORTING, &il->status);
1332 il_complete_scan(il, true);
1333}
1334
e7392364
SG		 1335static void
1336il_do_scan_abort(struct il_priv *il)
0cdc2136
SG		 1337{
1338 int ret;
1339
1340 lockdep_assert_held(&il->mutex);
1341
1342 if (!test_bit(S_SCANNING, &il->status)) {
1343 D_SCAN("Not performing scan to abort\n");
1344 return;
1345 }
1346
1347 if (test_and_set_bit(S_SCAN_ABORTING, &il->status)) {
1348 D_SCAN("Scan abort in progress\n");
1349 return;
1350 }
1351
1352 ret = il_send_scan_abort(il);
1353 if (ret) {
1354 D_SCAN("Send scan abort failed %d\n", ret);
1355 il_force_scan_end(il);
1356 } else
1357 D_SCAN("Successfully send scan abort\n");
1358}
1359
1360/**
1361 * il_scan_cancel - Cancel any currently executing HW scan
1362 */
e7392364
SG		 1363int
1364il_scan_cancel(struct il_priv *il)
0cdc2136
SG		 1365{
1366 D_SCAN("Queuing abort scan\n");
1367 queue_work(il->workqueue, &il->abort_scan);
1368 return 0;
1369}
1370EXPORT_SYMBOL(il_scan_cancel);
1371
1372/**
1373 * il_scan_cancel_timeout - Cancel any currently executing HW scan
1374 * @ms: amount of time to wait (in milliseconds) for scan to abort
1375 *
1376 */
e7392364
SG		 1377int
1378il_scan_cancel_timeout(struct il_priv *il, unsigned long ms)
0cdc2136
SG		 1379{
1380 unsigned long timeout = jiffies + msecs_to_jiffies(ms);
1381
1382 lockdep_assert_held(&il->mutex);
1383
1384 D_SCAN("Scan cancel timeout\n");
1385
1386 il_do_scan_abort(il);
1387
1388 while (time_before_eq(jiffies, timeout)) {
1389 if (!test_bit(S_SCAN_HW, &il->status))
1390 break;
1391 msleep(20);
1392 }
1393
1394 return test_bit(S_SCAN_HW, &il->status);
1395}
1396EXPORT_SYMBOL(il_scan_cancel_timeout);
1397
1398/* Service response to C_SCAN (0x80) */
e7392364
SG		 1399static void
1400il_hdl_scan(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1401{
1402#ifdef CONFIG_IWLEGACY_DEBUG
1403 struct il_rx_pkt *pkt = rxb_addr(rxb);
1404 struct il_scanreq_notification *notif =
1405 (struct il_scanreq_notification *)pkt->u.raw;
1406
1407 D_SCAN("Scan request status = 0x%x\n", notif->status);
1408#endif
1409}
1410
1411/* Service N_SCAN_START (0x82) */
e7392364
SG		 1412static void
1413il_hdl_scan_start(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1414{
1415 struct il_rx_pkt *pkt = rxb_addr(rxb);
1416 struct il_scanstart_notification *notif =
1417 (struct il_scanstart_notification *)pkt->u.raw;
1418 il->scan_start_tsf = le32_to_cpu(notif->tsf_low);
e7392364
SG		 1419 D_SCAN("Scan start: " "%d [802.11%s] "
1420 "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n", notif->channel,
1421 notif->band ? "bg" : "a", le32_to_cpu(notif->tsf_high),
1422 le32_to_cpu(notif->tsf_low), notif->status, notif->beacon_timer);
0cdc2136
SG		 1423}
1424
1425/* Service N_SCAN_RESULTS (0x83) */
e7392364
SG		 1426static void
1427il_hdl_scan_results(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1428{
1429#ifdef CONFIG_IWLEGACY_DEBUG
1430 struct il_rx_pkt *pkt = rxb_addr(rxb);
1431 struct il_scanresults_notification *notif =
1432 (struct il_scanresults_notification *)pkt->u.raw;
1433
e7392364
SG		 1434 D_SCAN("Scan ch.res: " "%d [802.11%s] " "(TSF: 0x%08X:%08X) - %d "
1435 "elapsed=%lu usec\n", notif->channel, notif->band ? "bg" : "a",
1436 le32_to_cpu(notif->tsf_high), le32_to_cpu(notif->tsf_low),
1437 le32_to_cpu(notif->stats[0]),
1438 le32_to_cpu(notif->tsf_low) - il->scan_start_tsf);
0cdc2136
SG		 1439#endif
1440}
1441
1442/* Service N_SCAN_COMPLETE (0x84) */
e7392364
SG		 1443static void
1444il_hdl_scan_complete(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 1445{
1446
1447#ifdef CONFIG_IWLEGACY_DEBUG
1448 struct il_rx_pkt *pkt = rxb_addr(rxb);
1449 struct il_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
1450#endif
1451
e7392364
SG		 1452 D_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
1453 scan_notif->scanned_channels, scan_notif->tsf_low,
1454 scan_notif->tsf_high, scan_notif->status);
0cdc2136
SG		 1455
1456 /* The HW is no longer scanning */
1457 clear_bit(S_SCAN_HW, &il->status);
1458
1459 D_SCAN("Scan on %sGHz took %dms\n",
e7392364
SG		 1460 (il->scan_band == IEEE80211_BAND_2GHZ) ? "2.4" : "5.2",
1461 jiffies_to_msecs(jiffies - il->scan_start));
0cdc2136
SG		 1462
1463 queue_work(il->workqueue, &il->scan_completed);
1464}
1465
e7392364
SG		 1466void
1467il_setup_rx_scan_handlers(struct il_priv *il)
0cdc2136
SG		 1468{
1469 /* scan handlers */
1470 il->handlers[C_SCAN] = il_hdl_scan;
e7392364
SG		 1471 il->handlers[N_SCAN_START] = il_hdl_scan_start;
1472 il->handlers[N_SCAN_RESULTS] = il_hdl_scan_results;
1473 il->handlers[N_SCAN_COMPLETE] = il_hdl_scan_complete;
0cdc2136
SG		 1474}
1475EXPORT_SYMBOL(il_setup_rx_scan_handlers);
1476
becdbc59 1477u16
e7392364
SG		 1478il_get_active_dwell_time(struct il_priv *il, enum ieee80211_band band,
1479 u8 n_probes)
0cdc2136
SG		 1480{
1481 if (band == IEEE80211_BAND_5GHZ)
1482 return IL_ACTIVE_DWELL_TIME_52 +
e7392364 1483 IL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
0cdc2136
SG		 1484 else
1485 return IL_ACTIVE_DWELL_TIME_24 +
e7392364 1486 IL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
0cdc2136
SG		 1487}
1488EXPORT_SYMBOL(il_get_active_dwell_time);
1489
e7392364 1490u16
1722f8e1
SG		 1491il_get_passive_dwell_time(struct il_priv *il, enum ieee80211_band band,
1492 struct ieee80211_vif *vif)
0cdc2136 1493{
0cdc2136
SG		 1494 u16 value;
1495
e7392364
SG		 1496 u16 passive =
1497 (band ==
1498 IEEE80211_BAND_2GHZ) ? IL_PASSIVE_DWELL_BASE +
1499 IL_PASSIVE_DWELL_TIME_24 : IL_PASSIVE_DWELL_BASE +
1500 IL_PASSIVE_DWELL_TIME_52;
0cdc2136
SG		 1501
1502 if (il_is_any_associated(il)) {
1503 /*
1504 * If we're associated, we clamp the maximum passive
1505 * dwell time to be 98% of the smallest beacon interval
1506 * (minus 2 * channel tune time)
1507 */
83007196 1508 value = il->vif ? il->vif->bss_conf.beacon_int : 0;
0cdc2136
SG		 1509 if (value > IL_PASSIVE_DWELL_BASE || !value)
1510 value = IL_PASSIVE_DWELL_BASE;
1511 value = (value * 98) / 100 - IL_CHANNEL_TUNE_TIME * 2;
1512 passive = min(value, passive);
1513 }
1514
1515 return passive;
1516}
1517EXPORT_SYMBOL(il_get_passive_dwell_time);
1518
e7392364
SG		 1519void
1520il_init_scan_params(struct il_priv *il)
0cdc2136
SG		 1521{
1522 u8 ant_idx = fls(il->hw_params.valid_tx_ant) - 1;
1523 if (!il->scan_tx_ant[IEEE80211_BAND_5GHZ])
1524 il->scan_tx_ant[IEEE80211_BAND_5GHZ] = ant_idx;
1525 if (!il->scan_tx_ant[IEEE80211_BAND_2GHZ])
1526 il->scan_tx_ant[IEEE80211_BAND_2GHZ] = ant_idx;
1527}
1528EXPORT_SYMBOL(il_init_scan_params);
1529
e7392364
SG		 1530static int
1531il_scan_initiate(struct il_priv *il, struct ieee80211_vif *vif)
0cdc2136
SG		 1532{
1533 int ret;
1534
1535 lockdep_assert_held(&il->mutex);
1536
0cdc2136
SG		 1537 cancel_delayed_work(&il->scan_check);
1538
1539 if (!il_is_ready_rf(il)) {
1540 IL_WARN("Request scan called when driver not ready.\n");
1541 return -EIO;
1542 }
1543
1544 if (test_bit(S_SCAN_HW, &il->status)) {
e7392364 1545 D_SCAN("Multiple concurrent scan requests in parallel.\n");
0cdc2136
SG		 1546 return -EBUSY;
1547 }
1548
1549 if (test_bit(S_SCAN_ABORTING, &il->status)) {
1550 D_SCAN("Scan request while abort pending.\n");
1551 return -EBUSY;
1552 }
1553
1554 D_SCAN("Starting scan...\n");
1555
1556 set_bit(S_SCANNING, &il->status);
1557 il->scan_start = jiffies;
1558
c9363551 1559 ret = il->ops->request_scan(il, vif);
0cdc2136
SG		 1560 if (ret) {
1561 clear_bit(S_SCANNING, &il->status);
1562 return ret;
1563 }
1564
1565 queue_delayed_work(il->workqueue, &il->scan_check,
1566 IL_SCAN_CHECK_WATCHDOG);
1567
1568 return 0;
1569}
1570
e7392364
SG		 1571int
1572il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
c56ef672 1573 struct ieee80211_scan_request *hw_req)
0cdc2136 1574{
c56ef672 1575 struct cfg80211_scan_request *req = &hw_req->req;
0cdc2136
SG		 1576 struct il_priv *il = hw->priv;
1577 int ret;
1578
9ce7b73c
SG		 1579 if (req->n_channels == 0) {
1580 IL_ERR("Can not scan on no channels.\n");
0cdc2136 1581 return -EINVAL;
9ce7b73c 1582 }
0cdc2136
SG		 1583
1584 mutex_lock(&il->mutex);
9ce7b73c 1585 D_MAC80211("enter\n");
0cdc2136
SG		 1586
1587 if (test_bit(S_SCANNING, &il->status)) {
1588 D_SCAN("Scan already in progress.\n");
1589 ret = -EAGAIN;
1590 goto out_unlock;
1591 }
1592
1593 /* mac80211 will only ask for one band at a time */
1594 il->scan_request = req;
1595 il->scan_vif = vif;
1596 il->scan_band = req->channels[0]->band;
1597
1598 ret = il_scan_initiate(il, vif);
1599
0cdc2136 1600out_unlock:
9ce7b73c 1601 D_MAC80211("leave ret %d\n", ret);
0cdc2136
SG		 1602 mutex_unlock(&il->mutex);
1603
1604 return ret;
1605}
1606EXPORT_SYMBOL(il_mac_hw_scan);
1607
e7392364
SG		 1608static void
1609il_bg_scan_check(struct work_struct *data)
0cdc2136
SG		 1610{
1611 struct il_priv *il =
1612 container_of(data, struct il_priv, scan_check.work);
1613
1614 D_SCAN("Scan check work\n");
1615
1616 /* Since we are here firmware does not finish scan and
1617 * most likely is in bad shape, so we don't bother to
1618 * send abort command, just force scan complete to mac80211 */
1619 mutex_lock(&il->mutex);
1620 il_force_scan_end(il);
1621 mutex_unlock(&il->mutex);
1622}
1623
1624/**
1625 * il_fill_probe_req - fill in all required fields and IE for probe request
1626 */
1627
1628u16
1629il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1722f8e1 1630 const u8 *ta, const u8 *ies, int ie_len, int left)
0cdc2136
SG		 1631{
1632 int len = 0;
1633 u8 *pos = NULL;
1634
1635 /* Make sure there is enough space for the probe request,
1636 * two mandatory IEs and the data */
1637 left -= 24;
1638 if (left < 0)
1639 return 0;
1640
1641 frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
742e7a93 1642 eth_broadcast_addr(frame->da);
0cdc2136 1643 memcpy(frame->sa, ta, ETH_ALEN);
742e7a93 1644 eth_broadcast_addr(frame->bssid);
0cdc2136
SG		 1645 frame->seq_ctrl = 0;
1646
1647 len += 24;
1648
1649 /* ...next IE... */
1650 pos = &frame->u.probe_req.variable[0];
1651
1652 /* fill in our indirect SSID IE */
1653 left -= 2;
1654 if (left < 0)
1655 return 0;
1656 *pos++ = WLAN_EID_SSID;
1657 *pos++ = 0;
1658
1659 len += 2;
1660
1661 if (WARN_ON(left < ie_len))
1662 return len;
1663
1664 if (ies && ie_len) {
1665 memcpy(pos, ies, ie_len);
1666 len += ie_len;
1667 }
1668
e7392364 1669 return (u16) len;
0cdc2136
SG		 1670}
1671EXPORT_SYMBOL(il_fill_probe_req);
1672
e7392364
SG		 1673static void
1674il_bg_abort_scan(struct work_struct *work)
0cdc2136
SG		 1675{
1676 struct il_priv *il = container_of(work, struct il_priv, abort_scan);
1677
1678 D_SCAN("Abort scan work\n");
1679
1680 /* We keep scan_check work queued in case when firmware will not
1681 * report back scan completed notification */
1682 mutex_lock(&il->mutex);
1683 il_scan_cancel_timeout(il, 200);
1684 mutex_unlock(&il->mutex);
1685}
1686
e7392364
SG		 1687static void
1688il_bg_scan_completed(struct work_struct *work)
0cdc2136 1689{
e7392364 1690 struct il_priv *il = container_of(work, struct il_priv, scan_completed);
0cdc2136
SG		 1691 bool aborted;
1692
1693 D_SCAN("Completed scan.\n");
1694
1695 cancel_delayed_work(&il->scan_check);
1696
1697 mutex_lock(&il->mutex);
1698
1699 aborted = test_and_clear_bit(S_SCAN_ABORTING, &il->status);
1700 if (aborted)
1701 D_SCAN("Aborted scan completed.\n");
1702
1703 if (!test_and_clear_bit(S_SCANNING, &il->status)) {
1704 D_SCAN("Scan already completed.\n");
1705 goto out_settings;
1706 }
1707
1708 il_complete_scan(il, aborted);
1709
1710out_settings:
1711 /* Can we still talk to firmware ? */
1712 if (!il_is_ready_rf(il))
1713 goto out;
1714
1715 /*
1716 * We do not commit power settings while scan is pending,
1717 * do it now if the settings changed.
1718 */
1719 il_power_set_mode(il, &il->power_data.sleep_cmd_next, false);
1720 il_set_tx_power(il, il->tx_power_next, false);
1721
c9363551 1722 il->ops->post_scan(il);
0cdc2136
SG		 1723
1724out:
1725 mutex_unlock(&il->mutex);
1726}
1727
e7392364
SG		 1728void
1729il_setup_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1730{
1731 INIT_WORK(&il->scan_completed, il_bg_scan_completed);
1732 INIT_WORK(&il->abort_scan, il_bg_abort_scan);
1733 INIT_DELAYED_WORK(&il->scan_check, il_bg_scan_check);
1734}
1735EXPORT_SYMBOL(il_setup_scan_deferred_work);
1736
e7392364
SG		 1737void
1738il_cancel_scan_deferred_work(struct il_priv *il)
0cdc2136
SG		 1739{
1740 cancel_work_sync(&il->abort_scan);
1741 cancel_work_sync(&il->scan_completed);
1742
1743 if (cancel_delayed_work_sync(&il->scan_check)) {
1744 mutex_lock(&il->mutex);
1745 il_force_scan_end(il);
1746 mutex_unlock(&il->mutex);
1747 }
1748}
1749EXPORT_SYMBOL(il_cancel_scan_deferred_work);
1750
1751/* il->sta_lock must be held */
e7392364
SG		 1752static void
1753il_sta_ucode_activate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 1754{
1755
1756 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE))
e7392364
SG		 1757 IL_ERR("ACTIVATE a non DRIVER active station id %u addr %pM\n",
1758 sta_id, il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1759
1760 if (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) {
e7392364
SG		 1761 D_ASSOC("STA id %u addr %pM already present"
1762 " in uCode (according to driver)\n", sta_id,
1763 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1764 } else {
1765 il->stations[sta_id].used |= IL_STA_UCODE_ACTIVE;
e7392364
SG		 1766 D_ASSOC("Added STA id %u addr %pM to uCode\n", sta_id,
1767 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1768 }
1769}
1770
e7392364
SG		 1771static int
1772il_process_add_sta_resp(struct il_priv *il, struct il_addsta_cmd *addsta,
1773 struct il_rx_pkt *pkt, bool sync)
0cdc2136
SG		 1774{
1775 u8 sta_id = addsta->sta.sta_id;
1776 unsigned long flags;
1777 int ret = -EIO;
1778
1779 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 1780 IL_ERR("Bad return from C_ADD_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 1781 return ret;
1782 }
1783
e7392364 1784 D_INFO("Processing response for adding station %u\n", sta_id);
0cdc2136
SG		 1785
1786 spin_lock_irqsave(&il->sta_lock, flags);
1787
1788 switch (pkt->u.add_sta.status) {
1789 case ADD_STA_SUCCESS_MSK:
1790 D_INFO("C_ADD_STA PASSED\n");
1791 il_sta_ucode_activate(il, sta_id);
1792 ret = 0;
1793 break;
1794 case ADD_STA_NO_ROOM_IN_TBL:
e7392364 1795 IL_ERR("Adding station %d failed, no room in table.\n", sta_id);
0cdc2136
SG		 1796 break;
1797 case ADD_STA_NO_BLOCK_ACK_RESOURCE:
e7392364
SG		 1798 IL_ERR("Adding station %d failed, no block ack resource.\n",
1799 sta_id);
0cdc2136
SG		 1800 break;
1801 case ADD_STA_MODIFY_NON_EXIST_STA:
1802 IL_ERR("Attempting to modify non-existing station %d\n",
e7392364 1803 sta_id);
0cdc2136
SG		 1804 break;
1805 default:
e7392364 1806 D_ASSOC("Received C_ADD_STA:(0x%08X)\n", pkt->u.add_sta.status);
0cdc2136
SG		 1807 break;
1808 }
1809
1810 D_INFO("%s station id %u addr %pM\n",
e7392364
SG		 1811 il->stations[sta_id].sta.mode ==
1812 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", sta_id,
1813 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 1814
1815 /*
1816 * XXX: The MAC address in the command buffer is often changed from
1817 * the original sent to the device. That is, the MAC address
1818 * written to the command buffer often is not the same MAC address
1819 * read from the command buffer when the command returns. This
1820 * issue has not yet been resolved and this debugging is left to
1821 * observe the problem.
1822 */
1823 D_INFO("%s station according to cmd buffer %pM\n",
e7392364
SG		 1824 il->stations[sta_id].sta.mode ==
1825 STA_CONTROL_MODIFY_MSK ? "Modified" : "Added", addsta->sta.addr);
0cdc2136
SG		 1826 spin_unlock_irqrestore(&il->sta_lock, flags);
1827
1828 return ret;
1829}
1830
e7392364
SG		 1831static void
1832il_add_sta_callback(struct il_priv *il, struct il_device_cmd *cmd,
1833 struct il_rx_pkt *pkt)
0cdc2136 1834{
e7392364 1835 struct il_addsta_cmd *addsta = (struct il_addsta_cmd *)cmd->cmd.payload;
0cdc2136
SG		 1836
1837 il_process_add_sta_resp(il, addsta, pkt, false);
1838
1839}
1840
e7392364
SG		 1841int
1842il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags)
0cdc2136
SG		 1843{
1844 struct il_rx_pkt *pkt = NULL;
1845 int ret = 0;
1846 u8 data[sizeof(*sta)];
1847 struct il_host_cmd cmd = {
1848 .id = C_ADD_STA,
1849 .flags = flags,
1850 .data = data,
1851 };
1852 u8 sta_id __maybe_unused = sta->sta.sta_id;
1853
e7392364
SG		 1854 D_INFO("Adding sta %u (%pM) %ssynchronously\n", sta_id, sta->sta.addr,
1855 flags & CMD_ASYNC ? "a" : "");
0cdc2136
SG		 1856
1857 if (flags & CMD_ASYNC)
1858 cmd.callback = il_add_sta_callback;
1859 else {
1860 cmd.flags |= CMD_WANT_SKB;
1861 might_sleep();
1862 }
1863
c9363551 1864 cmd.len = il->ops->build_addsta_hcmd(sta, data);
0cdc2136 1865 ret = il_send_cmd(il, &cmd);
3f0267f6 1866 if (ret)
0cdc2136 1867 return ret;
3f0267f6
DC		 1868 if (flags & CMD_ASYNC)
1869 return 0;
1870
1871 pkt = (struct il_rx_pkt *)cmd.reply_page;
1872 ret = il_process_add_sta_resp(il, sta, pkt, true);
0cdc2136 1873
0cdc2136
SG		 1874 il_free_pages(il, cmd.reply_page);
1875
1876 return ret;
1877}
1878EXPORT_SYMBOL(il_send_add_sta);
1879
e7392364 1880static void
83007196 1881il_set_ht_add_station(struct il_priv *il, u8 idx, struct ieee80211_sta *sta)
0cdc2136
SG		 1882{
1883 struct ieee80211_sta_ht_cap *sta_ht_inf = &sta->ht_cap;
1884 __le32 sta_flags;
0cdc2136
SG		 1885
1886 if (!sta || !sta_ht_inf->ht_supported)
1887 goto done;
1888
0cdc2136 1889 D_ASSOC("spatial multiplexing power save mode: %s\n",
af0ed69b
JB		 1890 (sta->smps_mode == IEEE80211_SMPS_STATIC) ? "static" :
1891 (sta->smps_mode == IEEE80211_SMPS_DYNAMIC) ? "dynamic" :
1722f8e1 1892 "disabled");
0cdc2136
SG		 1893
1894 sta_flags = il->stations[idx].sta.station_flags;
1895
1896 sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
1897
af0ed69b
JB		 1898 switch (sta->smps_mode) {
1899 case IEEE80211_SMPS_STATIC:
0cdc2136
SG		 1900 sta_flags |= STA_FLG_MIMO_DIS_MSK;
1901 break;
af0ed69b 1902 case IEEE80211_SMPS_DYNAMIC:
0cdc2136
SG		 1903 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
1904 break;
af0ed69b 1905 case IEEE80211_SMPS_OFF:
0cdc2136
SG		 1906 break;
1907 default:
af0ed69b 1908 IL_WARN("Invalid MIMO PS mode %d\n", sta->smps_mode);
0cdc2136
SG		 1909 break;
1910 }
1911
e7392364
SG		 1912 sta_flags |=
1913 cpu_to_le32((u32) sta_ht_inf->
1914 ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
0cdc2136 1915
e7392364
SG		 1916 sta_flags |=
1917 cpu_to_le32((u32) sta_ht_inf->
1918 ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
0cdc2136 1919
83007196 1920 if (il_is_ht40_tx_allowed(il, &sta->ht_cap))
0cdc2136
SG		 1921 sta_flags |= STA_FLG_HT40_EN_MSK;
1922 else
1923 sta_flags &= ~STA_FLG_HT40_EN_MSK;
1924
1925 il->stations[idx].sta.station_flags = sta_flags;
e7392364 1926done:
0cdc2136
SG		 1927 return;
1928}
1929
1930/**
1931 * il_prep_station - Prepare station information for addition
1932 *
1933 * should be called with sta_lock held
1934 */
e7392364 1935u8
83007196
SG		 1936il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
1937 struct ieee80211_sta *sta)
0cdc2136
SG		 1938{
1939 struct il_station_entry *station;
1940 int i;
1941 u8 sta_id = IL_INVALID_STATION;
1942 u16 rate;
1943
1944 if (is_ap)
8f9e5645 1945 sta_id = IL_AP_ID;
0cdc2136 1946 else if (is_broadcast_ether_addr(addr))
b16db50a 1947 sta_id = il->hw_params.bcast_id;
0cdc2136
SG		 1948 else
1949 for (i = IL_STA_ID; i < il->hw_params.max_stations; i++) {
2e42e474
JP		 1950 if (ether_addr_equal(il->stations[i].sta.sta.addr,
1951 addr)) {
0cdc2136
SG		 1952 sta_id = i;
1953 break;
1954 }
1955
1956 if (!il->stations[i].used &&
1957 sta_id == IL_INVALID_STATION)
1958 sta_id = i;
1959 }
1960
1961 /*
1962 * These two conditions have the same outcome, but keep them
1963 * separate
1964 */
1965 if (unlikely(sta_id == IL_INVALID_STATION))
1966 return sta_id;
1967
1968 /*
1969 * uCode is not able to deal with multiple requests to add a
1970 * station. Keep track if one is in progress so that we do not send
1971 * another.
1972 */
1973 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 1974 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 1975 return sta_id;
1976 }
1977
1978 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
1979 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE) &&
2e42e474 1980 ether_addr_equal(il->stations[sta_id].sta.sta.addr, addr)) {
e7392364
SG		 1981 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
1982 sta_id, addr);
0cdc2136
SG		 1983 return sta_id;
1984 }
1985
1986 station = &il->stations[sta_id];
1987 station->used = IL_STA_DRIVER_ACTIVE;
e7392364 1988 D_ASSOC("Add STA to driver ID %d: %pM\n", sta_id, addr);
0cdc2136
SG		 1989 il->num_stations++;
1990
1991 /* Set up the C_ADD_STA command to send to device */
1992 memset(&station->sta, 0, sizeof(struct il_addsta_cmd));
1993 memcpy(station->sta.sta.addr, addr, ETH_ALEN);
1994 station->sta.mode = 0;
1995 station->sta.sta.sta_id = sta_id;
fd6415bc 1996 station->sta.station_flags = 0;
0cdc2136 1997
0cdc2136
SG		 1998 /*
1999 * OK to call unconditionally, since local stations (IBSS BSSID
2000 * STA and broadcast STA) pass in a NULL sta, and mac80211
2001 * doesn't allow HT IBSS.
2002 */
83007196 2003 il_set_ht_add_station(il, sta_id, sta);
0cdc2136
SG		 2004
2005 /* 3945 only */
e7392364 2006 rate = (il->band == IEEE80211_BAND_5GHZ) ? RATE_6M_PLCP : RATE_1M_PLCP;
0cdc2136
SG		 2007 /* Turn on both antennas for the station... */
2008 station->sta.rate_n_flags = cpu_to_le16(rate | RATE_MCS_ANT_AB_MSK);
2009
2010 return sta_id;
2011
2012}
2013EXPORT_SYMBOL_GPL(il_prep_station);
2014
2015#define STA_WAIT_TIMEOUT (HZ/2)
2016
2017/**
2018 * il_add_station_common -
2019 */
2020int
83007196
SG		 2021il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2022 struct ieee80211_sta *sta, u8 *sta_id_r)
0cdc2136
SG		 2023{
2024 unsigned long flags_spin;
2025 int ret = 0;
2026 u8 sta_id;
2027 struct il_addsta_cmd sta_cmd;
2028
2029 *sta_id_r = 0;
2030 spin_lock_irqsave(&il->sta_lock, flags_spin);
83007196 2031 sta_id = il_prep_station(il, addr, is_ap, sta);
0cdc2136 2032 if (sta_id == IL_INVALID_STATION) {
e7392364 2033 IL_ERR("Unable to prepare station %pM for addition\n", addr);
0cdc2136
SG		 2034 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2035 return -EINVAL;
2036 }
2037
2038 /*
2039 * uCode is not able to deal with multiple requests to add a
2040 * station. Keep track if one is in progress so that we do not send
2041 * another.
2042 */
2043 if (il->stations[sta_id].used & IL_STA_UCODE_INPROGRESS) {
e7392364 2044 D_INFO("STA %d already in process of being added.\n", sta_id);
0cdc2136
SG		 2045 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2046 return -EEXIST;
2047 }
2048
2049 if ((il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE) &&
2050 (il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2051 D_ASSOC("STA %d (%pM) already added, not adding again.\n",
0cdc2136
SG		 2052 sta_id, addr);
2053 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2054 return -EEXIST;
2055 }
2056
2057 il->stations[sta_id].used |= IL_STA_UCODE_INPROGRESS;
2058 memcpy(&sta_cmd, &il->stations[sta_id].sta,
e7392364 2059 sizeof(struct il_addsta_cmd));
0cdc2136
SG		 2060 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2061
2062 /* Add station to device's station table */
2063 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2064 if (ret) {
2065 spin_lock_irqsave(&il->sta_lock, flags_spin);
2066 IL_ERR("Adding station %pM failed.\n",
e7392364 2067 il->stations[sta_id].sta.sta.addr);
0cdc2136
SG		 2068 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2069 il->stations[sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2070 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2071 }
2072 *sta_id_r = sta_id;
2073 return ret;
2074}
2075EXPORT_SYMBOL(il_add_station_common);
2076
2077/**
2078 * il_sta_ucode_deactivate - deactivate ucode status for a station
2079 *
2080 * il->sta_lock must be held
2081 */
e7392364
SG		 2082static void
2083il_sta_ucode_deactivate(struct il_priv *il, u8 sta_id)
0cdc2136
SG		 2084{
2085 /* Ucode must be active and driver must be non active */
e7392364
SG		 2086 if ((il->stations[sta_id].
2087 used & (IL_STA_UCODE_ACTIVE | IL_STA_DRIVER_ACTIVE)) !=
2088 IL_STA_UCODE_ACTIVE)
0cdc2136
SG		 2089 IL_ERR("removed non active STA %u\n", sta_id);
2090
2091 il->stations[sta_id].used &= ~IL_STA_UCODE_ACTIVE;
2092
2093 memset(&il->stations[sta_id], 0, sizeof(struct il_station_entry));
2094 D_ASSOC("Removed STA %u\n", sta_id);
2095}
2096
e7392364
SG		 2097static int
2098il_send_remove_station(struct il_priv *il, const u8 * addr, int sta_id,
2099 bool temporary)
0cdc2136
SG		 2100{
2101 struct il_rx_pkt *pkt;
2102 int ret;
2103
2104 unsigned long flags_spin;
2105 struct il_rem_sta_cmd rm_sta_cmd;
2106
2107 struct il_host_cmd cmd = {
2108 .id = C_REM_STA,
2109 .len = sizeof(struct il_rem_sta_cmd),
2110 .flags = CMD_SYNC,
2111 .data = &rm_sta_cmd,
2112 };
2113
2114 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd));
2115 rm_sta_cmd.num_sta = 1;
2116 memcpy(&rm_sta_cmd.addr, addr, ETH_ALEN);
2117
2118 cmd.flags |= CMD_WANT_SKB;
2119
2120 ret = il_send_cmd(il, &cmd);
2121
2122 if (ret)
2123 return ret;
2124
2125 pkt = (struct il_rx_pkt *)cmd.reply_page;
2126 if (pkt->hdr.flags & IL_CMD_FAILED_MSK) {
e7392364 2127 IL_ERR("Bad return from C_REM_STA (0x%08X)\n", pkt->hdr.flags);
0cdc2136
SG		 2128 ret = -EIO;
2129 }
2130
2131 if (!ret) {
2132 switch (pkt->u.rem_sta.status) {
2133 case REM_STA_SUCCESS_MSK:
2134 if (!temporary) {
2135 spin_lock_irqsave(&il->sta_lock, flags_spin);
2136 il_sta_ucode_deactivate(il, sta_id);
2137 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2138 flags_spin);
0cdc2136
SG		 2139 }
2140 D_ASSOC("C_REM_STA PASSED\n");
2141 break;
2142 default:
2143 ret = -EIO;
2144 IL_ERR("C_REM_STA failed\n");
2145 break;
2146 }
2147 }
2148 il_free_pages(il, cmd.reply_page);
2149
2150 return ret;
2151}
2152
2153/**
2154 * il_remove_station - Remove driver's knowledge of station.
2155 */
e7392364
SG		 2156int
2157il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr)
0cdc2136
SG		 2158{
2159 unsigned long flags;
2160
2161 if (!il_is_ready(il)) {
e7392364
SG		 2162 D_INFO("Unable to remove station %pM, device not ready.\n",
2163 addr);
0cdc2136
SG		 2164 /*
2165 * It is typical for stations to be removed when we are
2166 * going down. Return success since device will be down
2167 * soon anyway
2168 */
2169 return 0;
2170 }
2171
e7392364 2172 D_ASSOC("Removing STA from driver:%d %pM\n", sta_id, addr);
0cdc2136
SG		 2173
2174 if (WARN_ON(sta_id == IL_INVALID_STATION))
2175 return -EINVAL;
2176
2177 spin_lock_irqsave(&il->sta_lock, flags);
2178
2179 if (!(il->stations[sta_id].used & IL_STA_DRIVER_ACTIVE)) {
e7392364 2180 D_INFO("Removing %pM but non DRIVER active\n", addr);
0cdc2136
SG		 2181 goto out_err;
2182 }
2183
2184 if (!(il->stations[sta_id].used & IL_STA_UCODE_ACTIVE)) {
e7392364 2185 D_INFO("Removing %pM but non UCODE active\n", addr);
0cdc2136
SG		 2186 goto out_err;
2187 }
2188
2189 if (il->stations[sta_id].used & IL_STA_LOCAL) {
2190 kfree(il->stations[sta_id].lq);
2191 il->stations[sta_id].lq = NULL;
2192 }
2193
2194 il->stations[sta_id].used &= ~IL_STA_DRIVER_ACTIVE;
2195
2196 il->num_stations--;
2197
2198 BUG_ON(il->num_stations < 0);
2199
2200 spin_unlock_irqrestore(&il->sta_lock, flags);
2201
2202 return il_send_remove_station(il, addr, sta_id, false);
2203out_err:
2204 spin_unlock_irqrestore(&il->sta_lock, flags);
2205 return -EINVAL;
2206}
2207EXPORT_SYMBOL_GPL(il_remove_station);
2208
2209/**
2210 * il_clear_ucode_stations - clear ucode station table bits
2211 *
2212 * This function clears all the bits in the driver indicating
2213 * which stations are active in the ucode. Call when something
2214 * other than explicit station management would cause this in
2215 * the ucode, e.g. unassociated RXON.
2216 */
e7392364 2217void
83007196 2218il_clear_ucode_stations(struct il_priv *il)
0cdc2136
SG		 2219{
2220 int i;
2221 unsigned long flags_spin;
2222 bool cleared = false;
2223
2224 D_INFO("Clearing ucode stations in driver\n");
2225
2226 spin_lock_irqsave(&il->sta_lock, flags_spin);
2227 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136 2228 if (il->stations[i].used & IL_STA_UCODE_ACTIVE) {
e7392364 2229 D_INFO("Clearing ucode active for station %d\n", i);
0cdc2136
SG		 2230 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2231 cleared = true;
2232 }
2233 }
2234 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2235
2236 if (!cleared)
e7392364 2237 D_INFO("No active stations found to be cleared\n");
0cdc2136
SG		 2238}
2239EXPORT_SYMBOL(il_clear_ucode_stations);
2240
2241/**
2242 * il_restore_stations() - Restore driver known stations to device
2243 *
2244 * All stations considered active by driver, but not present in ucode, is
2245 * restored.
2246 *
2247 * Function sleeps.
2248 */
2249void
83007196 2250il_restore_stations(struct il_priv *il)
0cdc2136
SG		 2251{
2252 struct il_addsta_cmd sta_cmd;
2253 struct il_link_quality_cmd lq;
2254 unsigned long flags_spin;
2255 int i;
2256 bool found = false;
2257 int ret;
2258 bool send_lq;
2259
2260 if (!il_is_ready(il)) {
e7392364 2261 D_INFO("Not ready yet, not restoring any stations.\n");
0cdc2136
SG		 2262 return;
2263 }
2264
2265 D_ASSOC("Restoring all known stations ... start.\n");
2266 spin_lock_irqsave(&il->sta_lock, flags_spin);
2267 for (i = 0; i < il->hw_params.max_stations; i++) {
0cdc2136
SG		 2268 if ((il->stations[i].used & IL_STA_DRIVER_ACTIVE) &&
2269 !(il->stations[i].used & IL_STA_UCODE_ACTIVE)) {
2270 D_ASSOC("Restoring sta %pM\n",
e7392364 2271 il->stations[i].sta.sta.addr);
0cdc2136
SG		 2272 il->stations[i].sta.mode = 0;
2273 il->stations[i].used |= IL_STA_UCODE_INPROGRESS;
2274 found = true;
2275 }
2276 }
2277
2278 for (i = 0; i < il->hw_params.max_stations; i++) {
2279 if ((il->stations[i].used & IL_STA_UCODE_INPROGRESS)) {
2280 memcpy(&sta_cmd, &il->stations[i].sta,
2281 sizeof(struct il_addsta_cmd));
2282 send_lq = false;
2283 if (il->stations[i].lq) {
2284 memcpy(&lq, il->stations[i].lq,
2285 sizeof(struct il_link_quality_cmd));
2286 send_lq = true;
2287 }
2288 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2289 ret = il_send_add_sta(il, &sta_cmd, CMD_SYNC);
2290 if (ret) {
2291 spin_lock_irqsave(&il->sta_lock, flags_spin);
2292 IL_ERR("Adding station %pM failed.\n",
e7392364
SG		 2293 il->stations[i].sta.sta.addr);
2294 il->stations[i].used &= ~IL_STA_DRIVER_ACTIVE;
0cdc2136 2295 il->stations[i].used &=
e7392364 2296 ~IL_STA_UCODE_INPROGRESS;
0cdc2136 2297 spin_unlock_irqrestore(&il->sta_lock,
e7392364 2298 flags_spin);
0cdc2136
SG		 2299 }
2300 /*
2301 * Rate scaling has already been initialized, send
2302 * current LQ command
2303 */
2304 if (send_lq)
83007196 2305 il_send_lq_cmd(il, &lq, CMD_SYNC, true);
0cdc2136
SG		 2306 spin_lock_irqsave(&il->sta_lock, flags_spin);
2307 il->stations[i].used &= ~IL_STA_UCODE_INPROGRESS;
2308 }
2309 }
2310
2311 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2312 if (!found)
2313 D_INFO("Restoring all known stations"
e7392364 2314 " .... no stations to be restored.\n");
0cdc2136 2315 else
e7392364 2316 D_INFO("Restoring all known stations" " .... complete.\n");
0cdc2136
SG		 2317}
2318EXPORT_SYMBOL(il_restore_stations);
2319
e7392364
SG		 2320int
2321il_get_free_ucode_key_idx(struct il_priv *il)
0cdc2136
SG		 2322{
2323 int i;
2324
2325 for (i = 0; i < il->sta_key_max_num; i++)
2326 if (!test_and_set_bit(i, &il->ucode_key_table))
2327 return i;
2328
2329 return WEP_INVALID_OFFSET;
2330}
2331EXPORT_SYMBOL(il_get_free_ucode_key_idx);
2332
e7392364
SG		 2333void
2334il_dealloc_bcast_stations(struct il_priv *il)
0cdc2136
SG		 2335{
2336 unsigned long flags;
2337 int i;
2338
2339 spin_lock_irqsave(&il->sta_lock, flags);
2340 for (i = 0; i < il->hw_params.max_stations; i++) {
2341 if (!(il->stations[i].used & IL_STA_BCAST))
2342 continue;
2343
2344 il->stations[i].used &= ~IL_STA_UCODE_ACTIVE;
2345 il->num_stations--;
2346 BUG_ON(il->num_stations < 0);
2347 kfree(il->stations[i].lq);
2348 il->stations[i].lq = NULL;
2349 }
2350 spin_unlock_irqrestore(&il->sta_lock, flags);
2351}
2352EXPORT_SYMBOL_GPL(il_dealloc_bcast_stations);
2353
2354#ifdef CONFIG_IWLEGACY_DEBUG
e7392364
SG		 2355static void
2356il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2357{
2358 int i;
2359 D_RATE("lq station id 0x%x\n", lq->sta_id);
e7392364
SG		 2360 D_RATE("lq ant 0x%X 0x%X\n", lq->general_params.single_stream_ant_msk,
2361 lq->general_params.dual_stream_ant_msk);
0cdc2136
SG		 2362
2363 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++)
e7392364 2364 D_RATE("lq idx %d 0x%X\n", i, lq->rs_table[i].rate_n_flags);
0cdc2136
SG		 2365}
2366#else
e7392364
SG		 2367static inline void
2368il_dump_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2369{
2370}
2371#endif
2372
2373/**
2374 * il_is_lq_table_valid() - Test one aspect of LQ cmd for validity
2375 *
2376 * It sometimes happens when a HT rate has been in use and we
2377 * loose connectivity with AP then mac80211 will first tell us that the
2378 * current channel is not HT anymore before removing the station. In such a
2379 * scenario the RXON flags will be updated to indicate we are not
2380 * communicating HT anymore, but the LQ command may still contain HT rates.
2381 * Test for this to prevent driver from sending LQ command between the time
2382 * RXON flags are updated and when LQ command is updated.
2383 */
e7392364 2384static bool
83007196 2385il_is_lq_table_valid(struct il_priv *il, struct il_link_quality_cmd *lq)
0cdc2136
SG		 2386{
2387 int i;
2388
1c03c462 2389 if (il->ht.enabled)
0cdc2136
SG		 2390 return true;
2391
c8b03958 2392 D_INFO("Channel %u is not an HT channel\n", il->active.channel);
0cdc2136 2393 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
e7392364
SG		 2394 if (le32_to_cpu(lq->rs_table[i].rate_n_flags) & RATE_MCS_HT_MSK) {
2395 D_INFO("idx %d of LQ expects HT channel\n", i);
0cdc2136
SG		 2396 return false;
2397 }
2398 }
2399 return true;
2400}
2401
2402/**
2403 * il_send_lq_cmd() - Send link quality command
2404 * @init: This command is sent as part of station initialization right
2405 * after station has been added.
2406 *
2407 * The link quality command is sent as the last step of station creation.
2408 * This is the special case in which init is set and we call a callback in
2409 * this case to clear the state indicating that station creation is in
2410 * progress.
2411 */
e7392364 2412int
83007196
SG		 2413il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2414 u8 flags, bool init)
0cdc2136
SG		 2415{
2416 int ret = 0;
2417 unsigned long flags_spin;
2418
2419 struct il_host_cmd cmd = {
2420 .id = C_TX_LINK_QUALITY_CMD,
2421 .len = sizeof(struct il_link_quality_cmd),
2422 .flags = flags,
2423 .data = lq,
2424 };
2425
2426 if (WARN_ON(lq->sta_id == IL_INVALID_STATION))
2427 return -EINVAL;
2428
0cdc2136
SG		 2429 spin_lock_irqsave(&il->sta_lock, flags_spin);
2430 if (!(il->stations[lq->sta_id].used & IL_STA_DRIVER_ACTIVE)) {
2431 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2432 return -EINVAL;
2433 }
2434 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2435
2436 il_dump_lq_cmd(il, lq);
2437 BUG_ON(init && (cmd.flags & CMD_ASYNC));
2438
83007196 2439 if (il_is_lq_table_valid(il, lq))
0cdc2136
SG		 2440 ret = il_send_cmd(il, &cmd);
2441 else
2442 ret = -EINVAL;
2443
2444 if (cmd.flags & CMD_ASYNC)
2445 return ret;
2446
2447 if (init) {
2448 D_INFO("init LQ command complete,"
e7392364
SG		 2449 " clearing sta addition status for sta %d\n",
2450 lq->sta_id);
0cdc2136
SG		 2451 spin_lock_irqsave(&il->sta_lock, flags_spin);
2452 il->stations[lq->sta_id].used &= ~IL_STA_UCODE_INPROGRESS;
2453 spin_unlock_irqrestore(&il->sta_lock, flags_spin);
2454 }
2455 return ret;
2456}
2457EXPORT_SYMBOL(il_send_lq_cmd);
2458
e7392364
SG		 2459int
2460il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2461 struct ieee80211_sta *sta)
0cdc2136
SG		 2462{
2463 struct il_priv *il = hw->priv;
2464 struct il_station_priv_common *sta_common = (void *)sta->drv_priv;
2465 int ret;
2466
0cdc2136 2467 mutex_lock(&il->mutex);
9ce7b73c
SG		 2468 D_MAC80211("enter station %pM\n", sta->addr);
2469
0cdc2136
SG		 2470 ret = il_remove_station(il, sta_common->sta_id, sta->addr);
2471 if (ret)
e7392364 2472 IL_ERR("Error removing station %pM\n", sta->addr);
9ce7b73c
SG		 2473
2474 D_MAC80211("leave ret %d\n", ret);
0cdc2136 2475 mutex_unlock(&il->mutex);
9ce7b73c 2476
0cdc2136
SG		 2477 return ret;
2478}
2479EXPORT_SYMBOL(il_mac_sta_remove);
2480
2481/************************** RX-FUNCTIONS ****************************/
2482/*
2483 * Rx theory of operation
2484 *
2485 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
2486 * each of which point to Receive Buffers to be filled by the NIC. These get
2487 * used not only for Rx frames, but for any command response or notification
2488 * from the NIC. The driver and NIC manage the Rx buffers by means
2489 * of idxes into the circular buffer.
2490 *
2491 * Rx Queue Indexes
2492 * The host/firmware share two idx registers for managing the Rx buffers.
2493 *
2494 * The READ idx maps to the first position that the firmware may be writing
2495 * to -- the driver can read up to (but not including) this position and get
2496 * good data.
2497 * The READ idx is managed by the firmware once the card is enabled.
2498 *
2499 * The WRITE idx maps to the last position the driver has read from -- the
2500 * position preceding WRITE is the last slot the firmware can place a packet.
2501 *
2502 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
2503 * WRITE = READ.
2504 *
2505 * During initialization, the host sets up the READ queue position to the first
2506 * IDX position, and WRITE to the last (READ - 1 wrapped)
2507 *
2508 * When the firmware places a packet in a buffer, it will advance the READ idx
2509 * and fire the RX interrupt. The driver can then query the READ idx and
2510 * process as many packets as possible, moving the WRITE idx forward as it
2511 * resets the Rx queue buffers with new memory.
2512 *
2513 * The management in the driver is as follows:
2514 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
2515 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
2516 * to replenish the iwl->rxq->rx_free.
2517 * + In il_rx_replenish (scheduled) if 'processed' != 'read' then the
2518 * iwl->rxq is replenished and the READ IDX is updated (updating the
2519 * 'processed' and 'read' driver idxes as well)
2520 * + A received packet is processed and handed to the kernel network stack,
2521 * detached from the iwl->rxq. The driver 'processed' idx is updated.
2522 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
2523 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
2524 * IDX is not incremented and iwl->status(RX_STALLED) is set. If there
2525 * were enough free buffers and RX_STALLED is set it is cleared.
2526 *
2527 *
2528 * Driver sequence:
2529 *
2530 * il_rx_queue_alloc() Allocates rx_free
2531 * il_rx_replenish() Replenishes rx_free list from rx_used, and calls
2532 * il_rx_queue_restock
2533 * il_rx_queue_restock() Moves available buffers from rx_free into Rx
2534 * queue, updates firmware pointers, and updates
2535 * the WRITE idx. If insufficient rx_free buffers
2536 * are available, schedules il_rx_replenish
2537 *
2538 * -- enable interrupts --
2539 * ISR - il_rx() Detach il_rx_bufs from pool up to the
2540 * READ IDX, detaching the SKB from the pool.
2541 * Moves the packet buffer from queue to rx_used.
2542 * Calls il_rx_queue_restock to refill any empty
2543 * slots.
2544 * ...
2545 *
2546 */
2547
2548/**
2549 * il_rx_queue_space - Return number of free slots available in queue.
2550 */
e7392364
SG		 2551int
2552il_rx_queue_space(const struct il_rx_queue *q)
0cdc2136
SG		 2553{
2554 int s = q->read - q->write;
2555 if (s <= 0)
2556 s += RX_QUEUE_SIZE;
2557 /* keep some buffer to not confuse full and empty queue */
2558 s -= 2;
2559 if (s < 0)
2560 s = 0;
2561 return s;
2562}
2563EXPORT_SYMBOL(il_rx_queue_space);
2564
2565/**
2566 * il_rx_queue_update_write_ptr - Update the write pointer for the RX queue
2567 */
2568void
e7392364 2569il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q)
0cdc2136
SG		 2570{
2571 unsigned long flags;
2572 u32 rx_wrt_ptr_reg = il->hw_params.rx_wrt_ptr_reg;
2573 u32 reg;
2574
2575 spin_lock_irqsave(&q->lock, flags);
2576
2577 if (q->need_update == 0)
2578 goto exit_unlock;
2579
2580 /* If power-saving is in use, make sure device is awake */
2581 if (test_bit(S_POWER_PMI, &il->status)) {
2582 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2583
2584 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2585 D_INFO("Rx queue requesting wakeup," " GP1 = 0x%x\n",
2586 reg);
0cdc2136 2587 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2588 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2589 goto exit_unlock;
2590 }
2591
2592 q->write_actual = (q->write & ~0x7);
e7392364 2593 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136 2594
e7392364 2595 /* Else device is assumed to be awake */
0cdc2136
SG		 2596 } else {
2597 /* Device expects a multiple of 8 */
2598 q->write_actual = (q->write & ~0x7);
e7392364 2599 il_wr(il, rx_wrt_ptr_reg, q->write_actual);
0cdc2136
SG		 2600 }
2601
2602 q->need_update = 0;
2603
e7392364 2604exit_unlock:
0cdc2136
SG		 2605 spin_unlock_irqrestore(&q->lock, flags);
2606}
2607EXPORT_SYMBOL(il_rx_queue_update_write_ptr);
2608
e7392364
SG		 2609int
2610il_rx_queue_alloc(struct il_priv *il)
0cdc2136
SG		 2611{
2612 struct il_rx_queue *rxq = &il->rxq;
2613 struct device *dev = &il->pci_dev->dev;
2614 int i;
2615
2616 spin_lock_init(&rxq->lock);
2617 INIT_LIST_HEAD(&rxq->rx_free);
2618 INIT_LIST_HEAD(&rxq->rx_used);
2619
2620 /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
1f9061d2
JP		 2621 rxq->bd = dma_alloc_coherent(dev, 4 * RX_QUEUE_SIZE, &rxq->bd_dma,
2622 GFP_KERNEL);
0cdc2136
SG		 2623 if (!rxq->bd)
2624 goto err_bd;
2625
1f9061d2
JP		 2626 rxq->rb_stts = dma_alloc_coherent(dev, sizeof(struct il_rb_status),
2627 &rxq->rb_stts_dma, GFP_KERNEL);
0cdc2136
SG		 2628 if (!rxq->rb_stts)
2629 goto err_rb;
2630
2631 /* Fill the rx_used queue with _all_ of the Rx buffers */
2632 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
2633 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
2634
2635 /* Set us so that we have processed and used all buffers, but have
2636 * not restocked the Rx queue with fresh buffers */
2637 rxq->read = rxq->write = 0;
2638 rxq->write_actual = 0;
2639 rxq->free_count = 0;
2640 rxq->need_update = 0;
2641 return 0;
2642
2643err_rb:
2644 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
2645 rxq->bd_dma);
2646err_bd:
2647 return -ENOMEM;
2648}
e7392364 2649EXPORT_SYMBOL(il_rx_queue_alloc);
0cdc2136 2650
e7392364
SG		 2651void
2652il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb)
0cdc2136
SG		 2653{
2654 struct il_rx_pkt *pkt = rxb_addr(rxb);
2655 struct il_spectrum_notification *report = &(pkt->u.spectrum_notif);
2656
2657 if (!report->state) {
e7392364 2658 D_11H("Spectrum Measure Notification: Start\n");
0cdc2136
SG		 2659 return;
2660 }
2661
2662 memcpy(&il->measure_report, report, sizeof(*report));
2663 il->measurement_status |= MEASUREMENT_READY;
2664}
2665EXPORT_SYMBOL(il_hdl_spectrum_measurement);
2666
2667/*
2668 * returns non-zero if packet should be dropped
2669 */
e7392364
SG		 2670int
2671il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
2672 u32 decrypt_res, struct ieee80211_rx_status *stats)
0cdc2136
SG		 2673{
2674 u16 fc = le16_to_cpu(hdr->frame_control);
2675
2676 /*
2677 * All contexts have the same setting here due to it being
2678 * a module parameter, so OK to check any context.
2679 */
c8b03958 2680 if (il->active.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
0cdc2136
SG		 2681 return 0;
2682
2683 if (!(fc & IEEE80211_FCTL_PROTECTED))
2684 return 0;
2685
2686 D_RX("decrypt_res:0x%x\n", decrypt_res);
2687 switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
2688 case RX_RES_STATUS_SEC_TYPE_TKIP:
2689 /* The uCode has got a bad phase 1 Key, pushes the packet.
2690 * Decryption will be done in SW. */
2691 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2692 RX_RES_STATUS_BAD_KEY_TTAK)
2693 break;
2694
2695 case RX_RES_STATUS_SEC_TYPE_WEP:
2696 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2697 RX_RES_STATUS_BAD_ICV_MIC) {
2698 /* bad ICV, the packet is destroyed since the
2699 * decryption is inplace, drop it */
2700 D_RX("Packet destroyed\n");
2701 return -1;
2702 }
2703 case RX_RES_STATUS_SEC_TYPE_CCMP:
2704 if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
2705 RX_RES_STATUS_DECRYPT_OK) {
2706 D_RX("hw decrypt successfully!!!\n");
2707 stats->flag |= RX_FLAG_DECRYPTED;
2708 }
2709 break;
2710
2711 default:
2712 break;
2713 }
2714 return 0;
2715}
2716EXPORT_SYMBOL(il_set_decrypted_flag);
2717
2718/**
2719 * il_txq_update_write_ptr - Send new write idx to hardware
2720 */
2721void
2722il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq)
2723{
2724 u32 reg = 0;
2725 int txq_id = txq->q.id;
2726
2727 if (txq->need_update == 0)
2728 return;
2729
2730 /* if we're trying to save power */
2731 if (test_bit(S_POWER_PMI, &il->status)) {
2732 /* wake up nic if it's powered down ...
2733 * uCode will wake up, and interrupt us again, so next
2734 * time we'll skip this part. */
2735 reg = _il_rd(il, CSR_UCODE_DRV_GP1);
2736
2737 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
e7392364
SG		 2738 D_INFO("Tx queue %d requesting wakeup," " GP1 = 0x%x\n",
2739 txq_id, reg);
0cdc2136 2740 il_set_bit(il, CSR_GP_CNTRL,
e7392364 2741 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
0cdc2136
SG		 2742 return;
2743 }
2744
e7392364 2745 il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2746
2747 /*
2748 * else not in power-save mode,
2749 * uCode will never sleep when we're
2750 * trying to tx (during RFKILL, we're not trying to tx).
2751 */
2752 } else
e7392364 2753 _il_wr(il, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
0cdc2136
SG		 2754 txq->need_update = 0;
2755}
2756EXPORT_SYMBOL(il_txq_update_write_ptr);
2757
2758/**
2759 * il_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
2760 */
e7392364
SG		 2761void
2762il_tx_queue_unmap(struct il_priv *il, int txq_id)
0cdc2136
SG		 2763{
2764 struct il_tx_queue *txq = &il->txq[txq_id];
2765 struct il_queue *q = &txq->q;
2766
2767 if (q->n_bd == 0)
2768 return;
2769
2770 while (q->write_ptr != q->read_ptr) {
1600b875 2771 il->ops->txq_free_tfd(il, txq);
0cdc2136
SG		 2772 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2773 }
2774}
2775EXPORT_SYMBOL(il_tx_queue_unmap);
2776
2777/**
2778 * il_tx_queue_free - Deallocate DMA queue.
2779 * @txq: Transmit queue to deallocate.
2780 *
2781 * Empty queue by removing and destroying all BD's.
2782 * Free all buffers.
2783 * 0-fill, but do not free "txq" descriptor structure.
2784 */
e7392364
SG		 2785void
2786il_tx_queue_free(struct il_priv *il, int txq_id)
0cdc2136
SG		 2787{
2788 struct il_tx_queue *txq = &il->txq[txq_id];
2789 struct device *dev = &il->pci_dev->dev;
2790 int i;
2791
2792 il_tx_queue_unmap(il, txq_id);
2793
2794 /* De-alloc array of command/tx buffers */
2795 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
2796 kfree(txq->cmd[i]);
2797
2798 /* De-alloc circular buffer of TFDs */
2799 if (txq->q.n_bd)
e7392364
SG		 2800 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2801 txq->tfds, txq->q.dma_addr);
0cdc2136
SG		 2802
2803 /* De-alloc array of per-TFD driver data */
00ea99e1
SG		 2804 kfree(txq->skbs);
2805 txq->skbs = NULL;
0cdc2136
SG		 2806
2807 /* deallocate arrays */
2808 kfree(txq->cmd);
2809 kfree(txq->meta);
2810 txq->cmd = NULL;
2811 txq->meta = NULL;
2812
2813 /* 0-fill queue descriptor structure */
2814 memset(txq, 0, sizeof(*txq));
2815}
2816EXPORT_SYMBOL(il_tx_queue_free);
2817
2818/**
2819 * il_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
2820 */
e7392364
SG		 2821void
2822il_cmd_queue_unmap(struct il_priv *il)
0cdc2136
SG		 2823{
2824 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2825 struct il_queue *q = &txq->q;
2826 int i;
2827
2828 if (q->n_bd == 0)
2829 return;
2830
2831 while (q->read_ptr != q->write_ptr) {
2832 i = il_get_cmd_idx(q, q->read_ptr, 0);
2833
2834 if (txq->meta[i].flags & CMD_MAPPED) {
2835 pci_unmap_single(il->pci_dev,
2836 dma_unmap_addr(&txq->meta[i], mapping),
2837 dma_unmap_len(&txq->meta[i], len),
2838 PCI_DMA_BIDIRECTIONAL);
2839 txq->meta[i].flags = 0;
2840 }
2841
2842 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd);
2843 }
2844
2845 i = q->n_win;
2846 if (txq->meta[i].flags & CMD_MAPPED) {
2847 pci_unmap_single(il->pci_dev,
2848 dma_unmap_addr(&txq->meta[i], mapping),
2849 dma_unmap_len(&txq->meta[i], len),
2850 PCI_DMA_BIDIRECTIONAL);
2851 txq->meta[i].flags = 0;
2852 }
2853}
2854EXPORT_SYMBOL(il_cmd_queue_unmap);
2855
2856/**
2857 * il_cmd_queue_free - Deallocate DMA queue.
2858 * @txq: Transmit queue to deallocate.
2859 *
2860 * Empty queue by removing and destroying all BD's.
2861 * Free all buffers.
2862 * 0-fill, but do not free "txq" descriptor structure.
2863 */
e7392364
SG		 2864void
2865il_cmd_queue_free(struct il_priv *il)
0cdc2136
SG		 2866{
2867 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
2868 struct device *dev = &il->pci_dev->dev;
2869 int i;
2870
2871 il_cmd_queue_unmap(il);
2872
2873 /* De-alloc array of command/tx buffers */
2874 for (i = 0; i <= TFD_CMD_SLOTS; i++)
2875 kfree(txq->cmd[i]);
2876
2877 /* De-alloc circular buffer of TFDs */
2878 if (txq->q.n_bd)
2879 dma_free_coherent(dev, il->hw_params.tfd_size * txq->q.n_bd,
2880 txq->tfds, txq->q.dma_addr);
2881
2882 /* deallocate arrays */
2883 kfree(txq->cmd);
2884 kfree(txq->meta);
2885 txq->cmd = NULL;
2886 txq->meta = NULL;
2887
2888 /* 0-fill queue descriptor structure */
2889 memset(txq, 0, sizeof(*txq));
2890}
2891EXPORT_SYMBOL(il_cmd_queue_free);
2892
2893/*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
2894 * DMA services
2895 *
2896 * Theory of operation
2897 *
2898 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
2899 * of buffer descriptors, each of which points to one or more data buffers for
2900 * the device to read from or fill. Driver and device exchange status of each
2901 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
2902 * entries in each circular buffer, to protect against confusing empty and full
2903 * queue states.
2904 *
2905 * The device reads or writes the data in the queues via the device's several
2906 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
2907 *
2908 * For Tx queue, there are low mark and high mark limits. If, after queuing
2909 * the packet for Tx, free space become < low mark, Tx queue stopped. When
2910 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
2911 * Tx queue resumed.
2912 *
2913 * See more detailed info in 4965.h.
2914 ***************************************************/
2915
e7392364
SG		 2916int
2917il_queue_space(const struct il_queue *q)
0cdc2136
SG		 2918{
2919 int s = q->read_ptr - q->write_ptr;
2920
2921 if (q->read_ptr > q->write_ptr)
2922 s -= q->n_bd;
2923
2924 if (s <= 0)
2925 s += q->n_win;
2926 /* keep some reserve to not confuse empty and full situations */
2927 s -= 2;
2928 if (s < 0)
2929 s = 0;
2930 return s;
2931}
2932EXPORT_SYMBOL(il_queue_space);
2933
2934
2935/**
2936 * il_queue_init - Initialize queue's high/low-water and read/write idxes
2937 */
e7392364 2938static int
d87c771f 2939il_queue_init(struct il_priv *il, struct il_queue *q, int slots, u32 id)
0cdc2136 2940{
d87c771f
SG		 2941 /*
2942 * TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
2943 * il_queue_inc_wrap and il_queue_dec_wrap are broken.
2944 */
2945 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
2946 /* FIXME: remove q->n_bd */
2947 q->n_bd = TFD_QUEUE_SIZE_MAX;
0cdc2136 2948
d87c771f
SG		 2949 q->n_win = slots;
2950 q->id = id;
0cdc2136 2951
d87c771f 2952 /* slots_must be power-of-two size, otherwise
0cdc2136 2953 * il_get_cmd_idx is broken. */
d87c771f 2954 BUG_ON(!is_power_of_2(slots));
0cdc2136
SG		 2955
2956 q->low_mark = q->n_win / 4;
2957 if (q->low_mark < 4)
2958 q->low_mark = 4;
2959
2960 q->high_mark = q->n_win / 8;
2961 if (q->high_mark < 2)
2962 q->high_mark = 2;
2963
2964 q->write_ptr = q->read_ptr = 0;
2965
2966 return 0;
2967}
2968
2969/**
2970 * il_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
2971 */
e7392364
SG		 2972static int
2973il_tx_queue_alloc(struct il_priv *il, struct il_tx_queue *txq, u32 id)
0cdc2136
SG		 2974{
2975 struct device *dev = &il->pci_dev->dev;
2976 size_t tfd_sz = il->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
2977
2978 /* Driver ilate data, only for Tx (not command) queues,
2979 * not shared with device. */
2980 if (id != il->cmd_queue) {
9f0b4cbd
JL		 2981 txq->skbs = kcalloc(TFD_QUEUE_SIZE_MAX,
2982 sizeof(struct sk_buff *),
00ea99e1
SG		 2983 GFP_KERNEL);
2984 if (!txq->skbs) {
2985 IL_ERR("Fail to alloc skbs\n");
0cdc2136
SG		 2986 goto error;
2987 }
00ea99e1
SG		 2988 } else
2989 txq->skbs = NULL;
0cdc2136
SG		 2990
2991 /* Circular buffer of transmit frame descriptors (TFDs),
2992 * shared with device */
e7392364
SG		 2993 txq->tfds =
2994 dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr, GFP_KERNEL);
d0320f75 2995 if (!txq->tfds)
0cdc2136 2996 goto error;
d0320f75 2997
0cdc2136
SG		 2998 txq->q.id = id;
2999
3000 return 0;
3001
e7392364 3002error:
00ea99e1
SG		 3003 kfree(txq->skbs);
3004 txq->skbs = NULL;
0cdc2136
SG		 3005
3006 return -ENOMEM;
3007}
3008
3009/**
3010 * il_tx_queue_init - Allocate and initialize one tx/cmd queue
3011 */
e7392364 3012int
d87c771f 3013il_tx_queue_init(struct il_priv *il, u32 txq_id)
0cdc2136 3014{
d87c771f
SG		 3015 int i, len, ret;
3016 int slots, actual_slots;
3017 struct il_tx_queue *txq = &il->txq[txq_id];
0cdc2136
SG		 3018
3019 /*
3020 * Alloc buffer array for commands (Tx or other types of commands).
3021 * For the command queue (#4/#9), allocate command space + one big
3022 * command for scan, since scan command is very huge; the system will
3023 * not have two scans at the same time, so only one is needed.
3024 * For normal Tx queues (all other queues), no super-size command
3025 * space is needed.
3026 */
d87c771f
SG		 3027 if (txq_id == il->cmd_queue) {
3028 slots = TFD_CMD_SLOTS;
3029 actual_slots = slots + 1;
3030 } else {
3031 slots = TFD_TX_CMD_SLOTS;
3032 actual_slots = slots;
3033 }
0cdc2136 3034
e7392364
SG		 3035 txq->meta =
3036 kzalloc(sizeof(struct il_cmd_meta) * actual_slots, GFP_KERNEL);
3037 txq->cmd =
3038 kzalloc(sizeof(struct il_device_cmd *) * actual_slots, GFP_KERNEL);
0cdc2136
SG		 3039
3040 if (!txq->meta || !txq->cmd)
3041 goto out_free_arrays;
3042
3043 len = sizeof(struct il_device_cmd);
3044 for (i = 0; i < actual_slots; i++) {
3045 /* only happens for cmd queue */
d87c771f 3046 if (i == slots)
0cdc2136
SG		 3047 len = IL_MAX_CMD_SIZE;
3048
3049 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
3050 if (!txq->cmd[i])
3051 goto err;
3052 }
3053
3054 /* Alloc driver data array and TFD circular buffer */
3055 ret = il_tx_queue_alloc(il, txq, txq_id);
3056 if (ret)
3057 goto err;
3058
3059 txq->need_update = 0;
3060
3061 /*
3062 * For the default queues 0-3, set up the swq_id
3063 * already -- all others need to get one later
3064 * (if they need one at all).
3065 */
3066 if (txq_id < 4)
3067 il_set_swq_id(txq, txq_id, txq_id);
3068
0cdc2136 3069 /* Initialize queue's high/low-water marks, and head/tail idxes */
d87c771f 3070 il_queue_init(il, &txq->q, slots, txq_id);
0cdc2136
SG		 3071
3072 /* Tell device where to find queue */
1600b875 3073 il->ops->txq_init(il, txq);
0cdc2136
SG		 3074
3075 return 0;
3076err:
3077 for (i = 0; i < actual_slots; i++)
3078 kfree(txq->cmd[i]);
3079out_free_arrays:
3080 kfree(txq->meta);
3081 kfree(txq->cmd);
3082
3083 return -ENOMEM;
3084}
3085EXPORT_SYMBOL(il_tx_queue_init);
3086
e7392364 3087void
d87c771f 3088il_tx_queue_reset(struct il_priv *il, u32 txq_id)
0cdc2136 3089{
d87c771f
SG		 3090 int slots, actual_slots;
3091 struct il_tx_queue *txq = &il->txq[txq_id];
0cdc2136 3092
d87c771f
SG		 3093 if (txq_id == il->cmd_queue) {
3094 slots = TFD_CMD_SLOTS;
3095 actual_slots = TFD_CMD_SLOTS + 1;
3096 } else {
3097 slots = TFD_TX_CMD_SLOTS;
3098 actual_slots = TFD_TX_CMD_SLOTS;
3099 }
0cdc2136
SG		 3100
3101 memset(txq->meta, 0, sizeof(struct il_cmd_meta) * actual_slots);
0cdc2136
SG		 3102 txq->need_update = 0;
3103
3104 /* Initialize queue's high/low-water marks, and head/tail idxes */
d87c771f 3105 il_queue_init(il, &txq->q, slots, txq_id);
0cdc2136
SG		 3106
3107 /* Tell device where to find queue */
1600b875 3108 il->ops->txq_init(il, txq);
0cdc2136
SG		 3109}
3110EXPORT_SYMBOL(il_tx_queue_reset);
3111
3112/*************** HOST COMMAND QUEUE FUNCTIONS *****/
3113
3114/**
3115 * il_enqueue_hcmd - enqueue a uCode command
3116 * @il: device ilate data point
3117 * @cmd: a point to the ucode command structure
3118 *
3119 * The function returns < 0 values to indicate the operation is
3120 * failed. On success, it turns the idx (> 0) of command in the
3121 * command queue.
3122 */
e7392364
SG		 3123int
3124il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd)
0cdc2136
SG		 3125{
3126 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3127 struct il_queue *q = &txq->q;
3128 struct il_device_cmd *out_cmd;
3129 struct il_cmd_meta *out_meta;
3130 dma_addr_t phys_addr;
3131 unsigned long flags;
3132 int len;
3133 u32 idx;
3134 u16 fix_size;
3135
c9363551 3136 cmd->len = il->ops->get_hcmd_size(cmd->id, cmd->len);
e7392364 3137 fix_size = (u16) (cmd->len + sizeof(out_cmd->hdr));
0cdc2136
SG		 3138
3139 /* If any of the command structures end up being larger than
3140 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
3141 * we will need to increase the size of the TFD entries
3142 * Also, check to see if command buffer should not exceed the size
3143 * of device_cmd and max_cmd_size. */
3144 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
3145 !(cmd->flags & CMD_SIZE_HUGE));
3146 BUG_ON(fix_size > IL_MAX_CMD_SIZE);
3147
3148 if (il_is_rfkill(il) || il_is_ctkill(il)) {
3149 IL_WARN("Not sending command - %s KILL\n",
e7392364 3150 il_is_rfkill(il) ? "RF" : "CT");
0cdc2136
SG		 3151 return -EIO;
3152 }
3153
3154 spin_lock_irqsave(&il->hcmd_lock, flags);
3155
3156 if (il_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
3157 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3158
3159 IL_ERR("Restarting adapter due to command queue full\n");
3160 queue_work(il->workqueue, &il->restart);
3161 return -ENOSPC;
3162 }
3163
3164 idx = il_get_cmd_idx(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
3165 out_cmd = txq->cmd[idx];
3166 out_meta = &txq->meta[idx];
3167
3168 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
3169 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3170 return -ENOSPC;
3171 }
3172
3173 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
3174 out_meta->flags = cmd->flags | CMD_MAPPED;
3175 if (cmd->flags & CMD_WANT_SKB)
3176 out_meta->source = cmd;
3177 if (cmd->flags & CMD_ASYNC)
3178 out_meta->callback = cmd->callback;
3179
3180 out_cmd->hdr.cmd = cmd->id;
3181 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
3182
3183 /* At this point, the out_cmd now has all of the incoming cmd
3184 * information */
3185
3186 out_cmd->hdr.flags = 0;
e7392364
SG		 3187 out_cmd->hdr.sequence =
3188 cpu_to_le16(QUEUE_TO_SEQ(il->cmd_queue) | IDX_TO_SEQ(q->write_ptr));
0cdc2136
SG		 3189 if (cmd->flags & CMD_SIZE_HUGE)
3190 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
3191 len = sizeof(struct il_device_cmd);
3192 if (idx == TFD_CMD_SLOTS)
3193 len = IL_MAX_CMD_SIZE;
3194
3195#ifdef CONFIG_IWLEGACY_DEBUG
3196 switch (out_cmd->hdr.cmd) {
3197 case C_TX_LINK_QUALITY_CMD:
3198 case C_SENSITIVITY:
e7392364
SG		 3199 D_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
3200 "%d bytes at %d[%d]:%d\n",
3201 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3202 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
3203 q->write_ptr, idx, il->cmd_queue);
0cdc2136
SG		 3204 break;
3205 default:
3206 D_HC("Sending command %s (#%x), seq: 0x%04X, "
e7392364
SG		 3207 "%d bytes at %d[%d]:%d\n",
3208 il_get_cmd_string(out_cmd->hdr.cmd), out_cmd->hdr.cmd,
3209 le16_to_cpu(out_cmd->hdr.sequence), fix_size, q->write_ptr,
3210 idx, il->cmd_queue);
0cdc2136
SG		 3211 }
3212#endif
0cdc2136 3213
e7392364
SG		 3214 phys_addr =
3215 pci_map_single(il->pci_dev, &out_cmd->hdr, fix_size,
3216 PCI_DMA_BIDIRECTIONAL);
bdb084b2
SG		 3217 if (unlikely(pci_dma_mapping_error(il->pci_dev, phys_addr))) {
3218 idx = -ENOMEM;
3219 goto out;
3220 }
0cdc2136
SG		 3221 dma_unmap_addr_set(out_meta, mapping, phys_addr);
3222 dma_unmap_len_set(out_meta, len, fix_size);
3223
bdb084b2
SG		 3224 txq->need_update = 1;
3225
3226 if (il->ops->txq_update_byte_cnt_tbl)
3227 /* Set up entry in queue's byte count circular buffer */
3228 il->ops->txq_update_byte_cnt_tbl(il, txq, 0);
3229
1600b875 3230 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, fix_size, 1,
c39ae9fd 3231 U32_PAD(cmd->len));
0cdc2136
SG		 3232
3233 /* Increment and update queue's write idx */
3234 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd);
3235 il_txq_update_write_ptr(il, txq);
3236
bdb084b2 3237out:
0cdc2136
SG		 3238 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3239 return idx;
3240}
3241
3242/**
3243 * il_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
3244 *
3245 * When FW advances 'R' idx, all entries between old and new 'R' idx
3246 * need to be reclaimed. As result, some free space forms. If there is
3247 * enough free space (> low mark), wake the stack that feeds us.
3248 */
e7392364
SG		 3249static void
3250il_hcmd_queue_reclaim(struct il_priv *il, int txq_id, int idx, int cmd_idx)
0cdc2136
SG		 3251{
3252 struct il_tx_queue *txq = &il->txq[txq_id];
3253 struct il_queue *q = &txq->q;
3254 int nfreed = 0;
3255
3256 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) {
3257 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, "
e7392364
SG		 3258 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd,
3259 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3260 return;
3261 }
3262
3263 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
3264 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) {
3265
3266 if (nfreed++ > 0) {
3267 IL_ERR("HCMD skipped: idx (%d) %d %d\n", idx,
e7392364 3268 q->write_ptr, q->read_ptr);
0cdc2136
SG		 3269 queue_work(il->workqueue, &il->restart);
3270 }
3271
3272 }
3273}
3274
3275/**
3276 * il_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
3277 * @rxb: Rx buffer to reclaim
3278 *
3279 * If an Rx buffer has an async callback associated with it the callback
3280 * will be executed. The attached skb (if present) will only be freed
3281 * if the callback returns 1
3282 */
3283void
3284il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb)
3285{
3286 struct il_rx_pkt *pkt = rxb_addr(rxb);
3287 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
3288 int txq_id = SEQ_TO_QUEUE(sequence);
3289 int idx = SEQ_TO_IDX(sequence);
3290 int cmd_idx;
3291 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
3292 struct il_device_cmd *cmd;
3293 struct il_cmd_meta *meta;
3294 struct il_tx_queue *txq = &il->txq[il->cmd_queue];
3295 unsigned long flags;
3296
3297 /* If a Tx command is being handled and it isn't in the actual
3298 * command queue then there a command routing bug has been introduced
3299 * in the queue management code. */
e7392364
SG		 3300 if (WARN
3301 (txq_id != il->cmd_queue,
3302 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
3303 txq_id, il->cmd_queue, sequence, il->txq[il->cmd_queue].q.read_ptr,
3304 il->txq[il->cmd_queue].q.write_ptr)) {
0cdc2136
SG		 3305 il_print_hex_error(il, pkt, 32);
3306 return;
3307 }
3308
3309 cmd_idx = il_get_cmd_idx(&txq->q, idx, huge);
3310 cmd = txq->cmd[cmd_idx];
3311 meta = &txq->meta[cmd_idx];
3312
3313 txq->time_stamp = jiffies;
3314
e7392364
SG		 3315 pci_unmap_single(il->pci_dev, dma_unmap_addr(meta, mapping),
3316 dma_unmap_len(meta, len), PCI_DMA_BIDIRECTIONAL);
0cdc2136
SG		 3317
3318 /* Input error checking is done when commands are added to queue. */
3319 if (meta->flags & CMD_WANT_SKB) {
3320 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
3321 rxb->page = NULL;
3322 } else if (meta->callback)
3323 meta->callback(il, cmd, pkt);
3324
3325 spin_lock_irqsave(&il->hcmd_lock, flags);
3326
3327 il_hcmd_queue_reclaim(il, txq_id, idx, cmd_idx);
3328
3329 if (!(meta->flags & CMD_ASYNC)) {
3330 clear_bit(S_HCMD_ACTIVE, &il->status);
3331 D_INFO("Clearing HCMD_ACTIVE for command %s\n",
e7392364 3332 il_get_cmd_string(cmd->hdr.cmd));
0cdc2136
SG		 3333 wake_up(&il->wait_command_queue);
3334 }
3335
3336 /* Mark as unmapped */
3337 meta->flags = 0;
3338
3339 spin_unlock_irqrestore(&il->hcmd_lock, flags);
3340}
3341EXPORT_SYMBOL(il_tx_cmd_complete);
be663ab6
WYG		 3342
3343MODULE_DESCRIPTION("iwl-legacy: common functions for 3945 and 4965");
3344MODULE_VERSION(IWLWIFI_VERSION);
3345MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
3346MODULE_LICENSE("GPL");
3347
3348/*
3349 * set bt_coex_active to true, uCode will do kill/defer
3350 * every time the priority line is asserted (BT is sending signals on the
3351 * priority line in the PCIx).
3352 * set bt_coex_active to false, uCode will ignore the BT activity and
3353 * perform the normal operation
3354 *
3355 * User might experience transmit issue on some platform due to WiFi/BT
3356 * co-exist problem. The possible behaviors are:
3357 * Able to scan and finding all the available AP
3358 * Not able to associate with any AP
3359 * On those platforms, WiFi communication can be restored by set
3360 * "bt_coex_active" module parameter to "false"
3361 *
3362 * default: bt_coex_active = true (BT_COEX_ENABLE)
3363 */
ef33417d 3364static bool bt_coex_active = true;
be663ab6
WYG		 3365module_param(bt_coex_active, bool, S_IRUGO);
3366MODULE_PARM_DESC(bt_coex_active, "enable wifi/bluetooth co-exist");
3367
d2ddf621
SG		 3368u32 il_debug_level;
3369EXPORT_SYMBOL(il_debug_level);
be663ab6 3370
d2ddf621 3371const u8 il_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
e7392364 3372EXPORT_SYMBOL(il_bcast_addr);
be663ab6 3373
e7392364
SG		 3374#define MAX_BIT_RATE_40_MHZ 150 /* Mbps */
3375#define MAX_BIT_RATE_20_MHZ 72 /* Mbps */
3376static void
3377il_init_ht_hw_capab(const struct il_priv *il,
3378 struct ieee80211_sta_ht_cap *ht_info,
3379 enum ieee80211_band band)
be663ab6
WYG		 3380{
3381 u16 max_bit_rate = 0;
46bc8d4b
SG		 3382 u8 rx_chains_num = il->hw_params.rx_chains_num;
3383 u8 tx_chains_num = il->hw_params.tx_chains_num;
be663ab6
WYG		 3384
3385 ht_info->cap = 0;
3386 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
3387
3388 ht_info->ht_supported = true;
3389
3390 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
3391 max_bit_rate = MAX_BIT_RATE_20_MHZ;
46bc8d4b 3392 if (il->hw_params.ht40_channel & BIT(band)) {
be663ab6
WYG		 3393 ht_info->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
3394 ht_info->cap |= IEEE80211_HT_CAP_SGI_40;
3395 ht_info->mcs.rx_mask[4] = 0x01;
3396 max_bit_rate = MAX_BIT_RATE_40_MHZ;
3397 }
3398
46bc8d4b 3399 if (il->cfg->mod_params->amsdu_size_8K)
be663ab6
WYG		 3400 ht_info->cap |= IEEE80211_HT_CAP_MAX_AMSDU;
3401
3402 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3403 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3404
3405 ht_info->mcs.rx_mask[0] = 0xFF;
3406 if (rx_chains_num >= 2)
3407 ht_info->mcs.rx_mask[1] = 0xFF;
3408 if (rx_chains_num >= 3)
3409 ht_info->mcs.rx_mask[2] = 0xFF;
3410
3411 /* Highest supported Rx data rate */
3412 max_bit_rate *= rx_chains_num;
3413 WARN_ON(max_bit_rate & ~IEEE80211_HT_MCS_RX_HIGHEST_MASK);
3414 ht_info->mcs.rx_highest = cpu_to_le16(max_bit_rate);
3415
3416 /* Tx MCS capabilities */
3417 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
3418 if (tx_chains_num != rx_chains_num) {
3419 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
e7392364
SG		 3420 ht_info->mcs.tx_params |=
3421 ((tx_chains_num -
3422 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
be663ab6
WYG		 3423 }
3424}
3425
3426/**
e2ebc833 3427 * il_init_geos - Initialize mac80211's geo/channel info based from eeprom
be663ab6 3428 */
e7392364
SG		 3429int
3430il_init_geos(struct il_priv *il)
be663ab6 3431{
e2ebc833 3432 struct il_channel_info *ch;
be663ab6
WYG		 3433 struct ieee80211_supported_band *sband;
3434 struct ieee80211_channel *channels;
3435 struct ieee80211_channel *geo_ch;
3436 struct ieee80211_rate *rates;
3437 int i = 0;
332704a5 3438 s8 max_tx_power = 0;
be663ab6 3439
46bc8d4b
SG		 3440 if (il->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
3441 il->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
58de00a4 3442 D_INFO("Geography modes already initialized.\n");
a6766ccd 3443 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3444 return 0;
3445 }
3446
e7392364
SG		 3447 channels =
3448 kzalloc(sizeof(struct ieee80211_channel) * il->channel_count,
3449 GFP_KERNEL);
be663ab6
WYG		 3450 if (!channels)
3451 return -ENOMEM;
3452
e7392364
SG		 3453 rates =
3454 kzalloc((sizeof(struct ieee80211_rate) * RATE_COUNT_LEGACY),
3455 GFP_KERNEL);
be663ab6
WYG		 3456 if (!rates) {
3457 kfree(channels);
3458 return -ENOMEM;
3459 }
3460
3461 /* 5.2GHz channels start after the 2.4GHz channels */
46bc8d4b 3462 sband = &il->bands[IEEE80211_BAND_5GHZ];
d2ddf621 3463 sband->channels = &channels[ARRAY_SIZE(il_eeprom_band_1)];
be663ab6 3464 /* just OFDM */
e2ebc833 3465 sband->bitrates = &rates[IL_FIRST_OFDM_RATE];
2eb05816 3466 sband->n_bitrates = RATE_COUNT_LEGACY - IL_FIRST_OFDM_RATE;
be663ab6 3467
46bc8d4b 3468 if (il->cfg->sku & IL_SKU_N)
e7392364 3469 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_5GHZ);
be663ab6 3470
46bc8d4b 3471 sband = &il->bands[IEEE80211_BAND_2GHZ];
be663ab6
WYG		 3472 sband->channels = channels;
3473 /* OFDM & CCK */
3474 sband->bitrates = rates;
2eb05816 3475 sband->n_bitrates = RATE_COUNT_LEGACY;
be663ab6 3476
46bc8d4b 3477 if (il->cfg->sku & IL_SKU_N)
e7392364 3478 il_init_ht_hw_capab(il, &sband->ht_cap, IEEE80211_BAND_2GHZ);
be663ab6 3479
46bc8d4b
SG		 3480 il->ieee_channels = channels;
3481 il->ieee_rates = rates;
be663ab6 3482
e7392364 3483 for (i = 0; i < il->channel_count; i++) {
46bc8d4b 3484 ch = &il->channel_info[i];
be663ab6 3485
e2ebc833 3486 if (!il_is_channel_valid(ch))
be663ab6
WYG		 3487 continue;
3488
46bc8d4b 3489 sband = &il->bands[ch->band];
be663ab6
WYG		 3490
3491 geo_ch = &sband->channels[sband->n_channels++];
3492
3493 geo_ch->center_freq =
e7392364 3494 ieee80211_channel_to_frequency(ch->channel, ch->band);
be663ab6
WYG		 3495 geo_ch->max_power = ch->max_power_avg;
3496 geo_ch->max_antenna_gain = 0xff;
3497 geo_ch->hw_value = ch->channel;
3498
e2ebc833 3499 if (il_is_channel_valid(ch)) {
be663ab6 3500 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
8fe02e16 3501 geo_ch->flags |= IEEE80211_CHAN_NO_IR;
be663ab6
WYG		 3502
3503 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
8fe02e16 3504 geo_ch->flags |= IEEE80211_CHAN_NO_IR;
be663ab6
WYG		 3505
3506 if (ch->flags & EEPROM_CHANNEL_RADAR)
3507 geo_ch->flags |= IEEE80211_CHAN_RADAR;
3508
3509 geo_ch->flags |= ch->ht40_extension_channel;
3510
332704a5
SG		 3511 if (ch->max_power_avg > max_tx_power)
3512 max_tx_power = ch->max_power_avg;
be663ab6
WYG		 3513 } else {
3514 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
3515 }
3516
e7392364
SG		 3517 D_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n", ch->channel,
3518 geo_ch->center_freq,
3519 il_is_channel_a_band(ch) ? "5.2" : "2.4",
3520 geo_ch->
3521 flags & IEEE80211_CHAN_DISABLED ? "restricted" : "valid",
3522 geo_ch->flags);
be663ab6
WYG		 3523 }
3524
46bc8d4b
SG		 3525 il->tx_power_device_lmt = max_tx_power;
3526 il->tx_power_user_lmt = max_tx_power;
3527 il->tx_power_next = max_tx_power;
332704a5 3528
232913b5
SG		 3529 if (il->bands[IEEE80211_BAND_5GHZ].n_channels == 0 &&
3530 (il->cfg->sku & IL_SKU_A)) {
9406f797 3531 IL_INFO("Incorrectly detected BG card as ABG. "
be663ab6 3532 "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
e7392364 3533 il->pci_dev->device, il->pci_dev->subsystem_device);
46bc8d4b 3534 il->cfg->sku &= ~IL_SKU_A;
be663ab6
WYG		 3535 }
3536
9406f797 3537 IL_INFO("Tunable channels: %d 802.11bg, %d 802.11a channels\n",
e7392364
SG		 3538 il->bands[IEEE80211_BAND_2GHZ].n_channels,
3539 il->bands[IEEE80211_BAND_5GHZ].n_channels);
be663ab6 3540
a6766ccd 3541 set_bit(S_GEO_CONFIGURED, &il->status);
be663ab6
WYG		 3542
3543 return 0;
3544}
e2ebc833 3545EXPORT_SYMBOL(il_init_geos);
be663ab6
WYG		 3546
3547/*
e2ebc833 3548 * il_free_geos - undo allocations in il_init_geos
be663ab6 3549 */
e7392364
SG		 3550void
3551il_free_geos(struct il_priv *il)
be663ab6 3552{
46bc8d4b
SG		 3553 kfree(il->ieee_channels);
3554 kfree(il->ieee_rates);
a6766ccd 3555 clear_bit(S_GEO_CONFIGURED, &il->status);
be663ab6 3556}
e2ebc833 3557EXPORT_SYMBOL(il_free_geos);
be663ab6 3558
e7392364
SG		 3559static bool
3560il_is_channel_extension(struct il_priv *il, enum ieee80211_band band,
3561 u16 channel, u8 extension_chan_offset)
be663ab6 3562{
e2ebc833 3563 const struct il_channel_info *ch_info;
be663ab6 3564
46bc8d4b 3565 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3566 if (!il_is_channel_valid(ch_info))
be663ab6
WYG		 3567 return false;
3568
3569 if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
e7392364
SG		 3570 return !(ch_info->
3571 ht40_extension_channel & IEEE80211_CHAN_NO_HT40PLUS);
be663ab6 3572 else if (extension_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
e7392364
SG		 3573 return !(ch_info->
3574 ht40_extension_channel & IEEE80211_CHAN_NO_HT40MINUS);
be663ab6
WYG		 3575
3576 return false;
3577}
3578
e7392364 3579bool
83007196 3580il_is_ht40_tx_allowed(struct il_priv *il, struct ieee80211_sta_ht_cap *ht_cap)
be663ab6 3581{
1c03c462 3582 if (!il->ht.enabled || !il->ht.is_40mhz)
be663ab6
WYG		 3583 return false;
3584
3585 /*
3586 * We do not check for IEEE80211_HT_CAP_SUP_WIDTH_20_40
3587 * the bit will not set if it is pure 40MHz case
3588 */
3589 if (ht_cap && !ht_cap->ht_supported)
3590 return false;
3591
d3175167 3592#ifdef CONFIG_IWLEGACY_DEBUGFS
46bc8d4b 3593 if (il->disable_ht40)
be663ab6
WYG		 3594 return false;
3595#endif
3596
46bc8d4b 3597 return il_is_channel_extension(il, il->band,
c8b03958 3598 le16_to_cpu(il->staging.channel),
1c03c462 3599 il->ht.extension_chan_offset);
be663ab6 3600}
e2ebc833 3601EXPORT_SYMBOL(il_is_ht40_tx_allowed);
be663ab6 3602
31ced24d 3603static u16 noinline
e7392364 3604il_adjust_beacon_interval(u16 beacon_val, u16 max_beacon_val)
be663ab6
WYG		 3605{
3606 u16 new_val;
3607 u16 beacon_factor;
3608
3609 /*
3610 * If mac80211 hasn't given us a beacon interval, program
3611 * the default into the device.
3612 */
3613 if (!beacon_val)
3614 return DEFAULT_BEACON_INTERVAL;
3615
3616 /*
3617 * If the beacon interval we obtained from the peer
3618 * is too large, we'll have to wake up more often
3619 * (and in IBSS case, we'll beacon too much)
3620 *
3621 * For example, if max_beacon_val is 4096, and the
3622 * requested beacon interval is 7000, we'll have to
3623 * use 3500 to be able to wake up on the beacons.
3624 *
3625 * This could badly influence beacon detection stats.
3626 */
3627
3628 beacon_factor = (beacon_val + max_beacon_val) / max_beacon_val;
3629 new_val = beacon_val / beacon_factor;
3630
3631 if (!new_val)
3632 new_val = max_beacon_val;
3633
3634 return new_val;
3635}
3636
3637int
83007196 3638il_send_rxon_timing(struct il_priv *il)
be663ab6
WYG		 3639{
3640 u64 tsf;
3641 s32 interval_tm, rem;
3642 struct ieee80211_conf *conf = NULL;
3643 u16 beacon_int;
83007196 3644 struct ieee80211_vif *vif = il->vif;
be663ab6 3645
6278ddab 3646 conf = &il->hw->conf;
be663ab6 3647
46bc8d4b 3648 lockdep_assert_held(&il->mutex);
be663ab6 3649
c8b03958 3650 memset(&il->timing, 0, sizeof(struct il_rxon_time_cmd));
be663ab6 3651
c8b03958
SG		 3652 il->timing.timestamp = cpu_to_le64(il->timestamp);
3653 il->timing.listen_interval = cpu_to_le16(conf->listen_interval);
be663ab6
WYG		 3654
3655 beacon_int = vif ? vif->bss_conf.beacon_int : 0;
3656
3657 /*
6ce1dc45 3658 * TODO: For IBSS we need to get atim_win from mac80211,
e7392364 3659 * for now just always use 0
be663ab6 3660 */
c8b03958 3661 il->timing.atim_win = 0;
be663ab6 3662
e7392364
SG		 3663 beacon_int =
3664 il_adjust_beacon_interval(beacon_int,
3665 il->hw_params.max_beacon_itrvl *
3666 TIME_UNIT);
c8b03958 3667 il->timing.beacon_interval = cpu_to_le16(beacon_int);
be663ab6 3668
e7392364 3669 tsf = il->timestamp; /* tsf is modifed by do_div: copy it */
be663ab6
WYG		 3670 interval_tm = beacon_int * TIME_UNIT;
3671 rem = do_div(tsf, interval_tm);
c8b03958 3672 il->timing.beacon_init_val = cpu_to_le32(interval_tm - rem);
be663ab6 3673
c8b03958 3674 il->timing.dtim_period = vif ? (vif->bss_conf.dtim_period ? : 1) : 1;
be663ab6 3675
e7392364 3676 D_ASSOC("beacon interval %d beacon timer %d beacon tim %d\n",
c8b03958
SG		 3677 le16_to_cpu(il->timing.beacon_interval),
3678 le32_to_cpu(il->timing.beacon_init_val),
3679 le16_to_cpu(il->timing.atim_win));
be663ab6 3680
63d0f0c5 3681 return il_send_cmd_pdu(il, C_RXON_TIMING, sizeof(il->timing),
c8b03958 3682 &il->timing);
be663ab6 3683}
e2ebc833 3684EXPORT_SYMBOL(il_send_rxon_timing);
be663ab6
WYG		 3685
3686void
83007196 3687il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt)
be663ab6 3688{
c8b03958 3689 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3690
3691 if (hw_decrypt)
3692 rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
3693 else
3694 rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
3695
3696}
e2ebc833 3697EXPORT_SYMBOL(il_set_rxon_hwcrypto);
be663ab6
WYG		 3698
3699/* validate RXON structure is valid */
3700int
83007196 3701il_check_rxon_cmd(struct il_priv *il)
be663ab6 3702{
c8b03958 3703 struct il_rxon_cmd *rxon = &il->staging;
be663ab6
WYG		 3704 bool error = false;
3705
3706 if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
3707 if (rxon->flags & RXON_FLG_TGJ_NARROW_BAND_MSK) {
9406f797 3708 IL_WARN("check 2.4G: wrong narrow\n");
be663ab6
WYG		 3709 error = true;
3710 }
3711 if (rxon->flags & RXON_FLG_RADAR_DETECT_MSK) {
9406f797 3712 IL_WARN("check 2.4G: wrong radar\n");
be663ab6
WYG		 3713 error = true;
3714 }
3715 } else {
3716 if (!(rxon->flags & RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3717 IL_WARN("check 5.2G: not short slot!\n");
be663ab6
WYG		 3718 error = true;
3719 }
3720 if (rxon->flags & RXON_FLG_CCK_MSK) {
9406f797 3721 IL_WARN("check 5.2G: CCK!\n");
be663ab6
WYG		 3722 error = true;
3723 }
3724 }
3725 if ((rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1) {
9406f797 3726 IL_WARN("mac/bssid mcast!\n");
be663ab6
WYG		 3727 error = true;
3728 }
3729
3730 /* make sure basic rates 6Mbps and 1Mbps are supported */
2eb05816
SG		 3731 if ((rxon->ofdm_basic_rates & RATE_6M_MASK) == 0 &&
3732 (rxon->cck_basic_rates & RATE_1M_MASK) == 0) {
9406f797 3733 IL_WARN("neither 1 nor 6 are basic\n");
be663ab6
WYG		 3734 error = true;
3735 }
3736
3737 if (le16_to_cpu(rxon->assoc_id) > 2007) {
9406f797 3738 IL_WARN("aid > 2007\n");
be663ab6
WYG		 3739 error = true;
3740 }
3741
e7392364
SG		 3742 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) ==
3743 (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK)) {
9406f797 3744 IL_WARN("CCK and short slot\n");
be663ab6
WYG		 3745 error = true;
3746 }
3747
e7392364
SG		 3748 if ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) ==
3749 (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK)) {
9406f797 3750 IL_WARN("CCK and auto detect");
be663ab6
WYG		 3751 error = true;
3752 }
3753
e7392364
SG		 3754 if ((rxon->
3755 flags & (RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK)) ==
3756 RXON_FLG_TGG_PROTECT_MSK) {
9406f797 3757 IL_WARN("TGg but no auto-detect\n");
be663ab6
WYG		 3758 error = true;
3759 }
3760
3761 if (error)
e7392364 3762 IL_WARN("Tuning to channel %d\n", le16_to_cpu(rxon->channel));
be663ab6
WYG		 3763
3764 if (error) {
9406f797 3765 IL_ERR("Invalid RXON\n");
be663ab6
WYG		 3766 return -EINVAL;
3767 }
3768 return 0;
3769}
e2ebc833 3770EXPORT_SYMBOL(il_check_rxon_cmd);
be663ab6
WYG		 3771
3772/**
e2ebc833 3773 * il_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
46bc8d4b 3774 * @il: staging_rxon is compared to active_rxon
be663ab6
WYG		 3775 *
3776 * If the RXON structure is changing enough to require a new tune,
3777 * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
3778 * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
3779 */
e7392364 3780int
83007196 3781il_full_rxon_required(struct il_priv *il)
be663ab6 3782{
c8b03958
SG		 3783 const struct il_rxon_cmd *staging = &il->staging;
3784 const struct il_rxon_cmd *active = &il->active;
be663ab6
WYG		 3785
3786#define CHK(cond) \
3787 if ((cond)) { \
58de00a4 3788 D_INFO("need full RXON - " #cond "\n"); \
be663ab6
WYG		 3789 return 1; \
3790 }
3791
3792#define CHK_NEQ(c1, c2) \
3793 if ((c1) != (c2)) { \
58de00a4 3794 D_INFO("need full RXON - " \
be663ab6
WYG		 3795 #c1 " != " #c2 " - %d != %d\n", \
3796 (c1), (c2)); \
3797 return 1; \
3798 }
3799
3800 /* These items are only settable from the full RXON command */
c8b03958 3801 CHK(!il_is_associated(il));
ccbac290
JL		 3802 CHK(!ether_addr_equal_64bits(staging->bssid_addr, active->bssid_addr));
3803 CHK(!ether_addr_equal_64bits(staging->node_addr, active->node_addr));
3804 CHK(!ether_addr_equal_64bits(staging->wlap_bssid_addr,
3805 active->wlap_bssid_addr));
be663ab6
WYG		 3806 CHK_NEQ(staging->dev_type, active->dev_type);
3807 CHK_NEQ(staging->channel, active->channel);
3808 CHK_NEQ(staging->air_propagation, active->air_propagation);
3809 CHK_NEQ(staging->ofdm_ht_single_stream_basic_rates,
3810 active->ofdm_ht_single_stream_basic_rates);
3811 CHK_NEQ(staging->ofdm_ht_dual_stream_basic_rates,
3812 active->ofdm_ht_dual_stream_basic_rates);
3813 CHK_NEQ(staging->assoc_id, active->assoc_id);
3814
3815 /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
3816 * be updated with the RXON_ASSOC command -- however only some
3817 * flag transitions are allowed using RXON_ASSOC */
3818
3819 /* Check if we are not switching bands */
3820 CHK_NEQ(staging->flags & RXON_FLG_BAND_24G_MSK,
3821 active->flags & RXON_FLG_BAND_24G_MSK);
3822
3823 /* Check if we are switching association toggle */
3824 CHK_NEQ(staging->filter_flags & RXON_FILTER_ASSOC_MSK,
3825 active->filter_flags & RXON_FILTER_ASSOC_MSK);
3826
3827#undef CHK
3828#undef CHK_NEQ
3829
3830 return 0;
3831}
e2ebc833 3832EXPORT_SYMBOL(il_full_rxon_required);
be663ab6 3833
e7392364 3834u8
83007196 3835il_get_lowest_plcp(struct il_priv *il)
be663ab6
WYG		 3836{
3837 /*
3838 * Assign the lowest rate -- should really get this from
3839 * the beacon skb from mac80211.
3840 */
c8b03958 3841 if (il->staging.flags & RXON_FLG_BAND_24G_MSK)
2eb05816 3842 return RATE_1M_PLCP;
be663ab6 3843 else
2eb05816 3844 return RATE_6M_PLCP;
be663ab6 3845}
e2ebc833 3846EXPORT_SYMBOL(il_get_lowest_plcp);
be663ab6 3847
e7392364 3848static void
83007196 3849_il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3850{
c8b03958 3851 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 3852
1c03c462 3853 if (!il->ht.enabled) {
e7392364
SG		 3854 rxon->flags &=
3855 ~(RXON_FLG_CHANNEL_MODE_MSK |
3856 RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK | RXON_FLG_HT40_PROT_MSK
3857 | RXON_FLG_HT_PROT_MSK);
be663ab6
WYG		 3858 return;
3859 }
3860
e7392364 3861 rxon->flags |=
1c03c462 3862 cpu_to_le32(il->ht.protection << RXON_FLG_HT_OPERATING_MODE_POS);
be663ab6
WYG		 3863
3864 /* Set up channel bandwidth:
3865 * 20 MHz only, 20/40 mixed or pure 40 if ht40 ok */
3866 /* clear the HT channel mode before set the mode */
e7392364
SG		 3867 rxon->flags &=
3868 ~(RXON_FLG_CHANNEL_MODE_MSK | RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
83007196 3869 if (il_is_ht40_tx_allowed(il, NULL)) {
be663ab6 3870 /* pure ht40 */
1c03c462 3871 if (il->ht.protection == IEEE80211_HT_OP_MODE_PROTECTION_20MHZ) {
be663ab6
WYG		 3872 rxon->flags |= RXON_FLG_CHANNEL_MODE_PURE_40;
3873 /* Note: control channel is opposite of extension channel */
1c03c462 3874 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3875 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3876 rxon->flags &=
e7392364 3877 ~RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3878 break;
3879 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3880 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3881 break;
3882 }
3883 } else {
3884 /* Note: control channel is opposite of extension channel */
1c03c462 3885 switch (il->ht.extension_chan_offset) {
be663ab6
WYG		 3886 case IEEE80211_HT_PARAM_CHA_SEC_ABOVE:
3887 rxon->flags &=
e7392364 3888 ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
be663ab6
WYG		 3889 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3890 break;
3891 case IEEE80211_HT_PARAM_CHA_SEC_BELOW:
e7392364 3892 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
be663ab6
WYG		 3893 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED;
3894 break;
3895 case IEEE80211_HT_PARAM_CHA_SEC_NONE:
3896 default:
3897 /* channel location only valid if in Mixed mode */
e7392364 3898 IL_ERR("invalid extension channel offset\n");
be663ab6
WYG		 3899 break;
3900 }
3901 }
3902 } else {
3903 rxon->flags |= RXON_FLG_CHANNEL_MODE_LEGACY;
3904 }
3905
c9363551
SG		 3906 if (il->ops->set_rxon_chain)
3907 il->ops->set_rxon_chain(il);
be663ab6 3908
58de00a4 3909 D_ASSOC("rxon flags 0x%X operation mode :0x%X "
e7392364 3910 "extension channel offset 0x%x\n", le32_to_cpu(rxon->flags),
1c03c462 3911 il->ht.protection, il->ht.extension_chan_offset);
be663ab6
WYG		 3912}
3913
e7392364
SG		 3914void
3915il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf)
be663ab6 3916{
83007196 3917 _il_set_rxon_ht(il, ht_conf);
be663ab6 3918}
e2ebc833 3919EXPORT_SYMBOL(il_set_rxon_ht);
be663ab6
WYG		 3920
3921/* Return valid, unused, channel for a passive scan to reset the RF */
e7392364
SG		 3922u8
3923il_get_single_channel_number(struct il_priv *il, enum ieee80211_band band)
be663ab6 3924{
e2ebc833 3925 const struct il_channel_info *ch_info;
be663ab6
WYG		 3926 int i;
3927 u8 channel = 0;
3928 u8 min, max;
be663ab6
WYG		 3929
3930 if (band == IEEE80211_BAND_5GHZ) {
3931 min = 14;
46bc8d4b 3932 max = il->channel_count;
be663ab6
WYG		 3933 } else {
3934 min = 0;
3935 max = 14;
3936 }
3937
3938 for (i = min; i < max; i++) {
17d6e557 3939 channel = il->channel_info[i].channel;
c8b03958 3940 if (channel == le16_to_cpu(il->staging.channel))
be663ab6
WYG		 3941 continue;
3942
46bc8d4b 3943 ch_info = il_get_channel_info(il, band, channel);
e2ebc833 3944 if (il_is_channel_valid(ch_info))
be663ab6
WYG		 3945 break;
3946 }
3947
3948 return channel;
3949}
e2ebc833 3950EXPORT_SYMBOL(il_get_single_channel_number);
be663ab6
WYG		 3951
3952/**
e2ebc833 3953 * il_set_rxon_channel - Set the band and channel values in staging RXON
be663ab6
WYG		 3954 * @ch: requested channel as a pointer to struct ieee80211_channel
3955
3956 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
3957 * in the staging RXON flag structure based on the ch->band
3958 */
3959int
83007196 3960il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch)
be663ab6
WYG		 3961{
3962 enum ieee80211_band band = ch->band;
3963 u16 channel = ch->hw_value;
3964
c8b03958 3965 if (le16_to_cpu(il->staging.channel) == channel && il->band == band)
be663ab6
WYG		 3966 return 0;
3967
c8b03958 3968 il->staging.channel = cpu_to_le16(channel);
be663ab6 3969 if (band == IEEE80211_BAND_5GHZ)
c8b03958 3970 il->staging.flags &= ~RXON_FLG_BAND_24G_MSK;
be663ab6 3971 else
c8b03958 3972 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
be663ab6 3973
46bc8d4b 3974 il->band = band;
be663ab6 3975
58de00a4 3976 D_INFO("Staging channel set to %d [%d]\n", channel, band);
be663ab6
WYG		 3977
3978 return 0;
3979}
e2ebc833 3980EXPORT_SYMBOL(il_set_rxon_channel);
be663ab6 3981
e7392364 3982void
83007196
SG		 3983il_set_flags_for_band(struct il_priv *il, enum ieee80211_band band,
3984 struct ieee80211_vif *vif)
be663ab6
WYG		 3985{
3986 if (band == IEEE80211_BAND_5GHZ) {
c8b03958 3987 il->staging.flags &=
e7392364
SG		 3988 ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK |
3989 RXON_FLG_CCK_MSK);
c8b03958 3990 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3991 } else {
e2ebc833 3992 /* Copied from il_post_associate() */
be663ab6 3993 if (vif && vif->bss_conf.use_short_slot)
c8b03958 3994 il->staging.flags |= RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3995 else
c8b03958 3996 il->staging.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
be663ab6 3997
c8b03958
SG		 3998 il->staging.flags |= RXON_FLG_BAND_24G_MSK;
3999 il->staging.flags |= RXON_FLG_AUTO_DETECT_MSK;
4000 il->staging.flags &= ~RXON_FLG_CCK_MSK;
be663ab6
WYG		 4001 }
4002}
e2ebc833 4003EXPORT_SYMBOL(il_set_flags_for_band);
be663ab6
WYG		 4004
4005/*
4006 * initialize rxon structure with default values from eeprom
4007 */
e7392364 4008void
83007196 4009il_connection_init_rx_config(struct il_priv *il)
be663ab6 4010{
e2ebc833 4011 const struct il_channel_info *ch_info;
be663ab6 4012
c8b03958 4013 memset(&il->staging, 0, sizeof(il->staging));
be663ab6 4014
fa4cffcb
SG		 4015 switch (il->iw_mode) {
4016 case NL80211_IFTYPE_UNSPECIFIED:
0f8b90f5 4017 il->staging.dev_type = RXON_DEV_TYPE_ESS;
fa4cffcb
SG		 4018 break;
4019 case NL80211_IFTYPE_STATION:
83007196
SG		 4020 il->staging.dev_type = RXON_DEV_TYPE_ESS;
4021 il->staging.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
fa4cffcb
SG		 4022 break;
4023 case NL80211_IFTYPE_ADHOC:
83007196
SG		 4024 il->staging.dev_type = RXON_DEV_TYPE_IBSS;
4025 il->staging.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
4026 il->staging.filter_flags =
4027 RXON_FILTER_BCON_AWARE_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
fa4cffcb
SG		 4028 break;
4029 default:
83007196
SG		 4030 IL_ERR("Unsupported interface type %d\n", il->vif->type);
4031 return;
4032 }
be663ab6
WYG		 4033
4034#if 0
4035 /* TODO: Figure out when short_preamble would be set and cache from
4036 * that */
46bc8d4b 4037 if (!hw_to_local(il->hw)->short_preamble)
c8b03958 4038 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 4039 else
c8b03958 4040 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 4041#endif
4042
e7392364 4043 ch_info =
c8b03958 4044 il_get_channel_info(il, il->band, le16_to_cpu(il->active.channel));
be663ab6
WYG		 4045
4046 if (!ch_info)
46bc8d4b 4047 ch_info = &il->channel_info[0];
be663ab6 4048
c8b03958 4049 il->staging.channel = cpu_to_le16(ch_info->channel);
46bc8d4b 4050 il->band = ch_info->band;
be663ab6 4051
83007196 4052 il_set_flags_for_band(il, il->band, il->vif);
be663ab6 4053
c8b03958 4054 il->staging.ofdm_basic_rates =
e2ebc833 4055 (IL_OFDM_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
c8b03958 4056 il->staging.cck_basic_rates =
e2ebc833 4057 (IL_CCK_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6
WYG		 4058
4059 /* clear both MIX and PURE40 mode flag */
c8b03958 4060 il->staging.flags &=
e7392364 4061 ~(RXON_FLG_CHANNEL_MODE_MIXED | RXON_FLG_CHANNEL_MODE_PURE_40);
83007196
SG		 4062 if (il->vif)
4063 memcpy(il->staging.node_addr, il->vif->addr, ETH_ALEN);
be663ab6 4064
c8b03958
SG		 4065 il->staging.ofdm_ht_single_stream_basic_rates = 0xff;
4066 il->staging.ofdm_ht_dual_stream_basic_rates = 0xff;
be663ab6 4067}
e2ebc833 4068EXPORT_SYMBOL(il_connection_init_rx_config);
be663ab6 4069
e7392364
SG		 4070void
4071il_set_rate(struct il_priv *il)
be663ab6
WYG		 4072{
4073 const struct ieee80211_supported_band *hw = NULL;
4074 struct ieee80211_rate *rate;
be663ab6
WYG		 4075 int i;
4076
46bc8d4b 4077 hw = il_get_hw_mode(il, il->band);
be663ab6 4078 if (!hw) {
9406f797 4079 IL_ERR("Failed to set rate: unable to get hw mode\n");
be663ab6
WYG		 4080 return;
4081 }
4082
46bc8d4b 4083 il->active_rate = 0;
be663ab6
WYG		 4084
4085 for (i = 0; i < hw->n_bitrates; i++) {
4086 rate = &(hw->bitrates[i]);
2eb05816 4087 if (rate->hw_value < RATE_COUNT_LEGACY)
46bc8d4b 4088 il->active_rate |= (1 << rate->hw_value);
be663ab6
WYG		 4089 }
4090
58de00a4 4091 D_RATE("Set active_rate = %0x\n", il->active_rate);
be663ab6 4092
c8b03958 4093 il->staging.cck_basic_rates =
e7392364 4094 (IL_CCK_BASIC_RATES_MASK >> IL_FIRST_CCK_RATE) & 0xF;
be663ab6 4095
c8b03958 4096 il->staging.ofdm_basic_rates =
e7392364 4097 (IL_OFDM_BASIC_RATES_MASK >> IL_FIRST_OFDM_RATE) & 0xFF;
be663ab6 4098}
e2ebc833 4099EXPORT_SYMBOL(il_set_rate);
be663ab6 4100
e7392364
SG		 4101void
4102il_chswitch_done(struct il_priv *il, bool is_success)
be663ab6 4103{
a6766ccd 4104 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4105 return;
4106
a6766ccd 4107 if (test_and_clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
83007196 4108 ieee80211_chswitch_done(il->vif, is_success);
be663ab6 4109}
e2ebc833 4110EXPORT_SYMBOL(il_chswitch_done);
be663ab6 4111
e7392364
SG		 4112void
4113il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4114{
dcae1c64 4115 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4116 struct il_csa_notification *csa = &(pkt->u.csa_notif);
c8b03958 4117 struct il_rxon_cmd *rxon = (void *)&il->active;
be663ab6 4118
a6766ccd 4119 if (!test_bit(S_CHANNEL_SWITCH_PENDING, &il->status))
51e65257
SG		 4120 return;
4121
46bc8d4b 4122 if (!le32_to_cpu(csa->status) && csa->channel == il->switch_channel) {
51e65257 4123 rxon->channel = csa->channel;
c8b03958 4124 il->staging.channel = csa->channel;
e7392364 4125 D_11H("CSA notif: channel %d\n", le16_to_cpu(csa->channel));
46bc8d4b 4126 il_chswitch_done(il, true);
51e65257 4127 } else {
9406f797 4128 IL_ERR("CSA notif (fail) : channel %d\n",
e7392364 4129 le16_to_cpu(csa->channel));
46bc8d4b 4130 il_chswitch_done(il, false);
be663ab6
WYG		 4131 }
4132}
d2dfb33e 4133EXPORT_SYMBOL(il_hdl_csa);
be663ab6 4134
d3175167 4135#ifdef CONFIG_IWLEGACY_DEBUG
e7392364 4136void
83007196 4137il_print_rx_config_cmd(struct il_priv *il)
be663ab6 4138{
c8b03958 4139 struct il_rxon_cmd *rxon = &il->staging;
be663ab6 4140
58de00a4 4141 D_RADIO("RX CONFIG:\n");
46bc8d4b 4142 il_print_hex_dump(il, IL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
e7392364 4143 D_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
58de00a4 4144 D_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
e7392364 4145 D_RADIO("u32 filter_flags: 0x%08x\n", le32_to_cpu(rxon->filter_flags));
58de00a4 4146 D_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
e7392364
SG		 4147 D_RADIO("u8 ofdm_basic_rates: 0x%02x\n", rxon->ofdm_basic_rates);
4148 D_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
58de00a4
SG		 4149 D_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
4150 D_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
e7392364 4151 D_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
be663ab6 4152}
e2ebc833 4153EXPORT_SYMBOL(il_print_rx_config_cmd);
be663ab6
WYG		 4154#endif
4155/**
e2ebc833 4156 * il_irq_handle_error - called for HW or SW error interrupt from card
be663ab6 4157 */
e7392364
SG		 4158void
4159il_irq_handle_error(struct il_priv *il)
be663ab6 4160{
e2ebc833 4161 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4162 set_bit(S_FW_ERROR, &il->status);
be663ab6
WYG		 4163
4164 /* Cancel currently queued command. */
a6766ccd 4165 clear_bit(S_HCMD_ACTIVE, &il->status);
be663ab6 4166
e7392364 4167 IL_ERR("Loaded firmware version: %s\n", il->hw->wiphy->fw_version);
be663ab6 4168
1600b875
SG		 4169 il->ops->dump_nic_error_log(il);
4170 if (il->ops->dump_fh)
4171 il->ops->dump_fh(il, NULL, false);
d3175167 4172#ifdef CONFIG_IWLEGACY_DEBUG
46bc8d4b 4173 if (il_get_debug_level(il) & IL_DL_FW_ERRORS)
83007196 4174 il_print_rx_config_cmd(il);
be663ab6
WYG		 4175#endif
4176
46bc8d4b 4177 wake_up(&il->wait_command_queue);
be663ab6
WYG		 4178
4179 /* Keep the restart process from trying to send host
4180 * commands by clearing the INIT status bit */
a6766ccd 4181 clear_bit(S_READY, &il->status);
be663ab6 4182
a6766ccd 4183 if (!test_bit(S_EXIT_PENDING, &il->status)) {
58de00a4 4184 IL_DBG(IL_DL_FW_ERRORS,
e7392364 4185 "Restarting adapter due to uCode error.\n");
be663ab6 4186
46bc8d4b
SG		 4187 if (il->cfg->mod_params->restart_fw)
4188 queue_work(il->workqueue, &il->restart);
be663ab6
WYG		 4189 }
4190}
e2ebc833 4191EXPORT_SYMBOL(il_irq_handle_error);
be663ab6 4192
e7392364 4193static int
775ed8ab 4194_il_apm_stop_master(struct il_priv *il)
be663ab6
WYG		 4195{
4196 int ret = 0;
4197
4198 /* stop device's busmaster DMA activity */
775ed8ab 4199 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
be663ab6 4200
e7392364
SG		 4201 ret =
4202 _il_poll_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
4203 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
586e45e3 4204 if (ret < 0)
9406f797 4205 IL_WARN("Master Disable Timed Out, 100 usec\n");
be663ab6 4206
58de00a4 4207 D_INFO("stop master\n");
be663ab6
WYG		 4208
4209 return ret;
4210}
4211
e7392364 4212void
775ed8ab 4213_il_apm_stop(struct il_priv *il)
be663ab6 4214{
775ed8ab
SG		 4215 lockdep_assert_held(&il->reg_lock);
4216
58de00a4 4217 D_INFO("Stop card, put in low power state\n");
be663ab6
WYG		 4218
4219 /* Stop device's DMA activity */
775ed8ab 4220 _il_apm_stop_master(il);
be663ab6
WYG		 4221
4222 /* Reset the entire device */
775ed8ab 4223 _il_set_bit(il, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
be663ab6
WYG		 4224
4225 udelay(10);
4226
4227 /*
4228 * Clear "initialization complete" bit to move adapter from
4229 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
4230 */
775ed8ab
SG		 4231 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
4232}
4233EXPORT_SYMBOL(_il_apm_stop);
4234
4235void
4236il_apm_stop(struct il_priv *il)
4237{
4238 unsigned long flags;
4239
4240 spin_lock_irqsave(&il->reg_lock, flags);
4241 _il_apm_stop(il);
4242 spin_unlock_irqrestore(&il->reg_lock, flags);
be663ab6 4243}
e7392364 4244EXPORT_SYMBOL(il_apm_stop);
be663ab6
WYG		 4245
4246/*
4247 * Start up NIC's basic functionality after it has been reset
e2ebc833 4248 * (e.g. after platform boot, or shutdown via il_apm_stop())
be663ab6
WYG		 4249 * NOTE: This does not load uCode nor start the embedded processor
4250 */
e7392364
SG		 4251int
4252il_apm_init(struct il_priv *il)
be663ab6
WYG		 4253{
4254 int ret = 0;
4255 u16 lctl;
4256
58de00a4 4257 D_INFO("Init card's basic functions\n");
be663ab6
WYG		 4258
4259 /*
4260 * Use "set_bit" below rather than "write", to preserve any hardware
4261 * bits already set by default after reset.
4262 */
4263
4264 /* Disable L0S exit timer (platform NMI Work/Around) */
46bc8d4b 4265 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4266 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
be663ab6
WYG		 4267
4268 /*
4269 * Disable L0s without affecting L1;
4270 * don't wait for ICH L0s (ICH bug W/A)
4271 */
46bc8d4b 4272 il_set_bit(il, CSR_GIO_CHICKEN_BITS,
e7392364 4273 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
be663ab6
WYG		 4274
4275 /* Set FH wait threshold to maximum (HW error during stress W/A) */
e7392364 4276 il_set_bit(il, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
be663ab6
WYG		 4277
4278 /*
4279 * Enable HAP INTA (interrupt from management bus) to
4280 * wake device's PCI Express link L1a -> L0s
25985edc 4281 * NOTE: This is no-op for 3945 (non-existent bit)
be663ab6 4282 */
46bc8d4b 4283 il_set_bit(il, CSR_HW_IF_CONFIG_REG,
e7392364 4284 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
be663ab6
WYG		 4285
4286 /*
4287 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition.
4288 * Check if BIOS (or OS) enabled L1-ASPM on this device.
4289 * If so (likely), disable L0S, so device moves directly L0->L1;
4290 * costs negligible amount of power savings.
4291 * If not (unlikely), enable L0S, so there is at least some
4292 * power savings, even without L1.
4293 */
89ef1ed2 4294 if (il->cfg->set_l0s) {
94e15613 4295 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
f93eaffc 4296 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
be663ab6 4297 /* L1-ASPM enabled; disable(!) L0S */
46bc8d4b 4298 il_set_bit(il, CSR_GIO_REG,
e7392364 4299 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4300 D_POWER("L1 Enabled; Disabling L0S\n");
be663ab6
WYG		 4301 } else {
4302 /* L1-ASPM disabled; enable(!) L0S */
46bc8d4b 4303 il_clear_bit(il, CSR_GIO_REG,
e7392364 4304 CSR_GIO_REG_VAL_L0S_ENABLED);
58de00a4 4305 D_POWER("L1 Disabled; Enabling L0S\n");
be663ab6
WYG		 4306 }
4307 }
4308
4309 /* Configure analog phase-lock-loop before activating to D0A */
89ef1ed2 4310 if (il->cfg->pll_cfg_val)
46bc8d4b 4311 il_set_bit(il, CSR_ANA_PLL_CFG,
89ef1ed2 4312 il->cfg->pll_cfg_val);
be663ab6
WYG		 4313
4314 /*
4315 * Set "initialization complete" bit to move adapter from
4316 * D0U* --> D0A* (powered-up active) state.
4317 */
46bc8d4b 4318 il_set_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
be663ab6
WYG		 4319
4320 /*
4321 * Wait for clock stabilization; once stabilized, access to
db54eb57 4322 * device-internal resources is supported, e.g. il_wr_prph()
be663ab6
WYG		 4323 * and accesses to uCode SRAM.
4324 */
e7392364
SG		 4325 ret =
4326 _il_poll_bit(il, CSR_GP_CNTRL,
4327 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
4328 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
be663ab6 4329 if (ret < 0) {
58de00a4 4330 D_INFO("Failed to init the card\n");
be663ab6
WYG		 4331 goto out;
4332 }
4333
4334 /*
4335 * Enable DMA and BSM (if used) clocks, wait for them to stabilize.
4336 * BSM (Boostrap State Machine) is only in 3945 and 4965.
4337 *
4338 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
4339 * do not disable clocks. This preserves any hardware bits already
4340 * set by default in "CLK_CTRL_REG" after reset.
4341 */
89ef1ed2 4342 if (il->cfg->use_bsm)
db54eb57 4343 il_wr_prph(il, APMG_CLK_EN_REG,
e7392364 4344 APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
be663ab6 4345 else
e7392364 4346 il_wr_prph(il, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
be663ab6
WYG		 4347 udelay(20);
4348
4349 /* Disable L1-Active */
46bc8d4b 4350 il_set_bits_prph(il, APMG_PCIDEV_STT_REG,
e7392364 4351 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
be663ab6
WYG		 4352
4353out:
4354 return ret;
4355}
e7392364 4356EXPORT_SYMBOL(il_apm_init);
be663ab6 4357
e7392364
SG		 4358int
4359il_set_tx_power(struct il_priv *il, s8 tx_power, bool force)
be663ab6
WYG		 4360{
4361 int ret;
4362 s8 prev_tx_power;
43f12d47 4363 bool defer;
be663ab6 4364
46bc8d4b 4365 lockdep_assert_held(&il->mutex);
be663ab6 4366
46bc8d4b 4367 if (il->tx_power_user_lmt == tx_power && !force)
be663ab6
WYG		 4368 return 0;
4369
1600b875 4370 if (!il->ops->send_tx_power)
be663ab6
WYG		 4371 return -EOPNOTSUPP;
4372
332704a5
SG		 4373 /* 0 dBm mean 1 milliwatt */
4374 if (tx_power < 0) {
e7392364 4375 IL_WARN("Requested user TXPOWER %d below 1 mW.\n", tx_power);
be663ab6
WYG		 4376 return -EINVAL;
4377 }
4378
46bc8d4b 4379 if (tx_power > il->tx_power_device_lmt) {
e7392364
SG		 4380 IL_WARN("Requested user TXPOWER %d above upper limit %d.\n",
4381 tx_power, il->tx_power_device_lmt);
be663ab6
WYG		 4382 return -EINVAL;
4383 }
4384
46bc8d4b 4385 if (!il_is_ready_rf(il))
be663ab6
WYG		 4386 return -EIO;
4387
43f12d47
SG		 4388 /* scan complete and commit_rxon use tx_power_next value,
4389 * it always need to be updated for newest request */
46bc8d4b 4390 il->tx_power_next = tx_power;
43f12d47
SG		 4391
4392 /* do not set tx power when scanning or channel changing */
a6766ccd 4393 defer = test_bit(S_SCANNING, &il->status) ||
c8b03958 4394 memcmp(&il->active, &il->staging, sizeof(il->staging));
43f12d47 4395 if (defer && !force) {
58de00a4 4396 D_INFO("Deferring tx power set\n");
be663ab6
WYG		 4397 return 0;
4398 }
4399
46bc8d4b
SG		 4400 prev_tx_power = il->tx_power_user_lmt;
4401 il->tx_power_user_lmt = tx_power;
be663ab6 4402
1600b875 4403 ret = il->ops->send_tx_power(il);
be663ab6
WYG		 4404
4405 /* if fail to set tx_power, restore the orig. tx power */
4406 if (ret) {
46bc8d4b
SG		 4407 il->tx_power_user_lmt = prev_tx_power;
4408 il->tx_power_next = prev_tx_power;
be663ab6
WYG		 4409 }
4410 return ret;
4411}
e2ebc833 4412EXPORT_SYMBOL(il_set_tx_power);
be663ab6 4413
e7392364
SG		 4414void
4415il_send_bt_config(struct il_priv *il)
be663ab6 4416{
e2ebc833 4417 struct il_bt_cmd bt_cmd = {
be663ab6
WYG		 4418 .lead_time = BT_LEAD_TIME_DEF,
4419 .max_kill = BT_MAX_KILL_DEF,
4420 .kill_ack_mask = 0,
4421 .kill_cts_mask = 0,
4422 };
4423
4424 if (!bt_coex_active)
4425 bt_cmd.flags = BT_COEX_DISABLE;
4426 else
4427 bt_cmd.flags = BT_COEX_ENABLE;
4428
58de00a4 4429 D_INFO("BT coex %s\n",
e7392364 4430 (bt_cmd.flags == BT_COEX_DISABLE) ? "disable" : "active");
be663ab6 4431
e7392364 4432 if (il_send_cmd_pdu(il, C_BT_CONFIG, sizeof(struct il_bt_cmd), &bt_cmd))
9406f797 4433 IL_ERR("failed to send BT Coex Config\n");
be663ab6 4434}
e2ebc833 4435EXPORT_SYMBOL(il_send_bt_config);
be663ab6 4436
e7392364
SG		 4437int
4438il_send_stats_request(struct il_priv *il, u8 flags, bool clear)
be663ab6 4439{
ebf0d90d 4440 struct il_stats_cmd stats_cmd = {
e7392364 4441 .configuration_flags = clear ? IL_STATS_CONF_CLEAR_STATS : 0,
be663ab6
WYG		 4442 };
4443
4444 if (flags & CMD_ASYNC)
e7392364
SG		 4445 return il_send_cmd_pdu_async(il, C_STATS, sizeof(struct il_stats_cmd),
4446 &stats_cmd, NULL);
be663ab6 4447 else
e7392364
SG		 4448 return il_send_cmd_pdu(il, C_STATS, sizeof(struct il_stats_cmd),
4449 &stats_cmd);
be663ab6 4450}
ebf0d90d 4451EXPORT_SYMBOL(il_send_stats_request);
be663ab6 4452
e7392364
SG		 4453void
4454il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4455{
d3175167 4456#ifdef CONFIG_IWLEGACY_DEBUG
dcae1c64 4457 struct il_rx_pkt *pkt = rxb_addr(rxb);
e2ebc833 4458 struct il_sleep_notification *sleep = &(pkt->u.sleep_notif);
58de00a4 4459 D_RX("sleep mode: %d, src: %d\n",
1722f8e1 4460 sleep->pm_sleep_mode, sleep->pm_wakeup_src);
be663ab6
WYG		 4461#endif
4462}
d2dfb33e 4463EXPORT_SYMBOL(il_hdl_pm_sleep);
be663ab6 4464
e7392364
SG		 4465void
4466il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4467{
dcae1c64 4468 struct il_rx_pkt *pkt = rxb_addr(rxb);
e94a4099 4469 u32 len = le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK;
e7392364
SG		 4470 D_RADIO("Dumping %d bytes of unhandled notification for %s:\n", len,
4471 il_get_cmd_string(pkt->hdr.cmd));
46bc8d4b 4472 il_print_hex_dump(il, IL_DL_RADIO, pkt->u.raw, len);
be663ab6 4473}
d2dfb33e 4474EXPORT_SYMBOL(il_hdl_pm_debug_stats);
be663ab6 4475
e7392364
SG		 4476void
4477il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb)
be663ab6 4478{
dcae1c64 4479 struct il_rx_pkt *pkt = rxb_addr(rxb);
be663ab6 4480
9406f797 4481 IL_ERR("Error Reply type 0x%08X cmd %s (0x%02X) "
e7392364
SG		 4482 "seq 0x%04X ser 0x%08X\n",
4483 le32_to_cpu(pkt->u.err_resp.error_type),
4484 il_get_cmd_string(pkt->u.err_resp.cmd_id),
4485 pkt->u.err_resp.cmd_id,
4486 le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
4487 le32_to_cpu(pkt->u.err_resp.error_info));
be663ab6 4488}
6e9848b4 4489EXPORT_SYMBOL(il_hdl_error);
be663ab6 4490
e7392364
SG		 4491void
4492il_clear_isr_stats(struct il_priv *il)
be663ab6 4493{
46bc8d4b 4494 memset(&il->isr_stats, 0, sizeof(il->isr_stats));
be663ab6
WYG		 4495}
4496
e7392364
SG		 4497int
4498il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, u16 queue,
4499 const struct ieee80211_tx_queue_params *params)
be663ab6 4500{
46bc8d4b 4501 struct il_priv *il = hw->priv;
be663ab6
WYG		 4502 unsigned long flags;
4503 int q;
4504
58de00a4 4505 D_MAC80211("enter\n");
be663ab6 4506
46bc8d4b 4507 if (!il_is_ready_rf(il)) {
58de00a4 4508 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 4509 return -EIO;
4510 }
4511
4512 if (queue >= AC_NUM) {
58de00a4 4513 D_MAC80211("leave - queue >= AC_NUM %d\n", queue);
be663ab6
WYG		 4514 return 0;
4515 }
4516
4517 q = AC_NUM - 1 - queue;
4518
46bc8d4b 4519 spin_lock_irqsave(&il->lock, flags);
be663ab6 4520
8d44f2bd 4521 il->qos_data.def_qos_parm.ac[q].cw_min =
e7392364 4522 cpu_to_le16(params->cw_min);
8d44f2bd 4523 il->qos_data.def_qos_parm.ac[q].cw_max =
e7392364 4524 cpu_to_le16(params->cw_max);
8d44f2bd
SG		 4525 il->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
4526 il->qos_data.def_qos_parm.ac[q].edca_txop =
e7392364 4527 cpu_to_le16((params->txop * 32));
be663ab6 4528
8d44f2bd 4529 il->qos_data.def_qos_parm.ac[q].reserved1 = 0;
be663ab6 4530
46bc8d4b 4531 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 4532
58de00a4 4533 D_MAC80211("leave\n");
be663ab6
WYG		 4534 return 0;
4535}
e2ebc833 4536EXPORT_SYMBOL(il_mac_conf_tx);
be663ab6 4537
e7392364
SG		 4538int
4539il_mac_tx_last_beacon(struct ieee80211_hw *hw)
be663ab6 4540{
46bc8d4b 4541 struct il_priv *il = hw->priv;
9ce7b73c 4542 int ret;
be663ab6 4543
9ce7b73c
SG		 4544 D_MAC80211("enter\n");
4545
4546 ret = (il->ibss_manager == IL_IBSS_MANAGER);
4547
4548 D_MAC80211("leave ret %d\n", ret);
4549 return ret;
be663ab6 4550}
e2ebc833 4551EXPORT_SYMBOL_GPL(il_mac_tx_last_beacon);
be663ab6
WYG		 4552
4553static int
83007196 4554il_set_mode(struct il_priv *il)
be663ab6 4555{
83007196 4556 il_connection_init_rx_config(il);
be663ab6 4557
c9363551
SG		 4558 if (il->ops->set_rxon_chain)
4559 il->ops->set_rxon_chain(il);
be663ab6 4560
83007196 4561 return il_commit_rxon(il);
be663ab6
WYG		 4562}
4563
be663ab6 4564int
e2ebc833 4565il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4566{
46bc8d4b 4567 struct il_priv *il = hw->priv;
be663ab6 4568 int err;
883a649b 4569 bool reset;
be663ab6 4570
46bc8d4b 4571 mutex_lock(&il->mutex);
9ce7b73c 4572 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4573
46bc8d4b 4574 if (!il_is_ready_rf(il)) {
9406f797 4575 IL_WARN("Try to add interface when device not ready\n");
be663ab6
WYG		 4576 err = -EINVAL;
4577 goto out;
4578 }
4579
883a649b
SG		 4580 /*
4581 * We do not support multiple virtual interfaces, but on hardware reset
4582 * we have to add the same interface again.
4583 */
4584 reset = (il->vif == vif);
4585 if (il->vif && !reset) {
be663ab6
WYG		 4586 err = -EOPNOTSUPP;
4587 goto out;
4588 }
4589
83007196 4590 il->vif = vif;
20c47eba 4591 il->iw_mode = vif->type;
be663ab6 4592
83007196 4593 err = il_set_mode(il);
17d6e557 4594 if (err) {
883a649b
SG		 4595 IL_WARN("Fail to set mode %d\n", vif->type);
4596 if (!reset) {
4597 il->vif = NULL;
4598 il->iw_mode = NL80211_IFTYPE_STATION;
4599 }
17d6e557 4600 }
be663ab6 4601
e7392364 4602out:
9ce7b73c 4603 D_MAC80211("leave err %d\n", err);
46bc8d4b 4604 mutex_unlock(&il->mutex);
be663ab6 4605
be663ab6
WYG		 4606 return err;
4607}
e2ebc833 4608EXPORT_SYMBOL(il_mac_add_interface);
be663ab6 4609
e7392364 4610static void
fa4cffcb 4611il_teardown_interface(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 4612{
46bc8d4b 4613 lockdep_assert_held(&il->mutex);
be663ab6 4614
46bc8d4b
SG		 4615 if (il->scan_vif == vif) {
4616 il_scan_cancel_timeout(il, 200);
4617 il_force_scan_end(il);
be663ab6
WYG		 4618 }
4619
fa4cffcb 4620 il_set_mode(il);
be663ab6
WYG		 4621}
4622
e7392364
SG		 4623void
4624il_mac_remove_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 4625{
46bc8d4b 4626 struct il_priv *il = hw->priv;
be663ab6 4627
46bc8d4b 4628 mutex_lock(&il->mutex);
9ce7b73c 4629 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 4630
83007196
SG		 4631 WARN_ON(il->vif != vif);
4632 il->vif = NULL;
fa4cffcb
SG		 4633 il->iw_mode = NL80211_IFTYPE_UNSPECIFIED;
4634 il_teardown_interface(il, vif);
93803b33 4635 eth_zero_addr(il->bssid);
be663ab6 4636
58de00a4 4637 D_MAC80211("leave\n");
9ce7b73c 4638 mutex_unlock(&il->mutex);
be663ab6 4639}
e2ebc833 4640EXPORT_SYMBOL(il_mac_remove_interface);
be663ab6 4641
e7392364
SG		 4642int
4643il_alloc_txq_mem(struct il_priv *il)
be663ab6 4644{
46bc8d4b 4645 if (!il->txq)
e7392364
SG		 4646 il->txq =
4647 kzalloc(sizeof(struct il_tx_queue) *
89ef1ed2 4648 il->cfg->num_of_queues, GFP_KERNEL);
46bc8d4b 4649 if (!il->txq) {
9406f797 4650 IL_ERR("Not enough memory for txq\n");
be663ab6
WYG		 4651 return -ENOMEM;
4652 }
4653 return 0;
4654}
e2ebc833 4655EXPORT_SYMBOL(il_alloc_txq_mem);
be663ab6 4656
e7392364 4657void
6668e4eb 4658il_free_txq_mem(struct il_priv *il)
be663ab6 4659{
46bc8d4b
SG		 4660 kfree(il->txq);
4661 il->txq = NULL;
be663ab6 4662}
6668e4eb 4663EXPORT_SYMBOL(il_free_txq_mem);
be663ab6 4664
e7392364
SG		 4665int
4666il_force_reset(struct il_priv *il, bool external)
be663ab6 4667{
e2ebc833 4668 struct il_force_reset *force_reset;
be663ab6 4669
a6766ccd 4670 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4671 return -EINVAL;
4672
46bc8d4b 4673 force_reset = &il->force_reset;
be663ab6
WYG		 4674 force_reset->reset_request_count++;
4675 if (!external) {
4676 if (force_reset->last_force_reset_jiffies &&
4677 time_after(force_reset->last_force_reset_jiffies +
e7392364 4678 force_reset->reset_duration, jiffies)) {
58de00a4 4679 D_INFO("force reset rejected\n");
be663ab6
WYG		 4680 force_reset->reset_reject_count++;
4681 return -EAGAIN;
4682 }
4683 }
4684 force_reset->reset_success_count++;
4685 force_reset->last_force_reset_jiffies = jiffies;
dd6d2a8a
SG		 4686
4687 /*
4688 * if the request is from external(ex: debugfs),
4689 * then always perform the request in regardless the module
4690 * parameter setting
4691 * if the request is from internal (uCode error or driver
4692 * detect failure), then fw_restart module parameter
4693 * need to be check before performing firmware reload
4694 */
4695
46bc8d4b 4696 if (!external && !il->cfg->mod_params->restart_fw) {
58de00a4 4697 D_INFO("Cancel firmware reload based on "
e7392364 4698 "module parameter setting\n");
dd6d2a8a 4699 return 0;
be663ab6 4700 }
dd6d2a8a 4701
9406f797 4702 IL_ERR("On demand firmware reload\n");
dd6d2a8a 4703
e2ebc833 4704 /* Set the FW error flag -- cleared on il_down */
a6766ccd 4705 set_bit(S_FW_ERROR, &il->status);
46bc8d4b 4706 wake_up(&il->wait_command_queue);
dd6d2a8a
SG		 4707 /*
4708 * Keep the restart process from trying to send host
4709 * commands by clearing the INIT status bit
4710 */
a6766ccd 4711 clear_bit(S_READY, &il->status);
46bc8d4b 4712 queue_work(il->workqueue, &il->restart);
dd6d2a8a 4713
be663ab6
WYG		 4714 return 0;
4715}
788f7a56 4716EXPORT_SYMBOL(il_force_reset);
be663ab6
WYG		 4717
4718int
e7392364 4719il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
be663ab6
WYG		 4720 enum nl80211_iftype newtype, bool newp2p)
4721{
46bc8d4b 4722 struct il_priv *il = hw->priv;
be663ab6
WYG		 4723 int err;
4724
46bc8d4b 4725 mutex_lock(&il->mutex);
9ce7b73c
SG		 4726 D_MAC80211("enter: type %d, addr %pM newtype %d newp2p %d\n",
4727 vif->type, vif->addr, newtype, newp2p);
4728
4729 if (newp2p) {
4730 err = -EOPNOTSUPP;
4731 goto out;
4732 }
be663ab6 4733
83007196 4734 if (!il->vif || !il_is_ready_rf(il)) {
ffd8c746
JB		 4735 /*
4736 * Huh? But wait ... this can maybe happen when
4737 * we're in the middle of a firmware restart!
4738 */
4739 err = -EBUSY;
4740 goto out;
4741 }
4742
be663ab6 4743 /* success */
be663ab6 4744 vif->type = newtype;
8c9c48d5 4745 vif->p2p = false;
fa4cffcb
SG		 4746 il->iw_mode = newtype;
4747 il_teardown_interface(il, vif);
be663ab6
WYG		 4748 err = 0;
4749
e7392364 4750out:
9ce7b73c 4751 D_MAC80211("leave err %d\n", err);
46bc8d4b 4752 mutex_unlock(&il->mutex);
9ce7b73c 4753
be663ab6
WYG		 4754 return err;
4755}
e2ebc833 4756EXPORT_SYMBOL(il_mac_change_interface);
be663ab6 4757
77be2c54
EG		 4758void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4759 u32 queues, bool drop)
70277f47
SG		 4760{
4761 struct il_priv *il = hw->priv;
4762 unsigned long timeout = jiffies + msecs_to_jiffies(500);
4763 int i;
4764
4765 mutex_lock(&il->mutex);
4766 D_MAC80211("enter\n");
4767
4768 if (il->txq == NULL)
4769 goto out;
4770
4771 for (i = 0; i < il->hw_params.max_txq_num; i++) {
4772 struct il_queue *q;
4773
4774 if (i == il->cmd_queue)
4775 continue;
4776
4777 q = &il->txq[i].q;
4778 if (q->read_ptr == q->write_ptr)
4779 continue;
4780
4781 if (time_after(jiffies, timeout)) {
4782 IL_ERR("Failed to flush queue %d\n", q->id);
4783 break;
4784 }
4785
4786 msleep(20);
4787 }
4788out:
4789 D_MAC80211("leave\n");
4790 mutex_unlock(&il->mutex);
4791}
4792EXPORT_SYMBOL(il_mac_flush);
4793
be663ab6
WYG		 4794/*
4795 * On every watchdog tick we check (latest) time stamp. If it does not
4796 * change during timeout period and queue is not empty we reset firmware.
4797 */
e7392364
SG		 4798static int
4799il_check_stuck_queue(struct il_priv *il, int cnt)
be663ab6 4800{
46bc8d4b 4801 struct il_tx_queue *txq = &il->txq[cnt];
e2ebc833 4802 struct il_queue *q = &txq->q;
be663ab6 4803 unsigned long timeout;
26b6da6b 4804 unsigned long now = jiffies;
be663ab6
WYG		 4805 int ret;
4806
4807 if (q->read_ptr == q->write_ptr) {
26b6da6b 4808 txq->time_stamp = now;
be663ab6
WYG		 4809 return 0;
4810 }
4811
e7392364
SG		 4812 timeout =
4813 txq->time_stamp +
89ef1ed2 4814 msecs_to_jiffies(il->cfg->wd_timeout);
be663ab6 4815
26b6da6b 4816 if (time_after(now, timeout)) {
e7392364 4817 IL_ERR("Queue %d stuck for %u ms.\n", q->id,
26b6da6b 4818 jiffies_to_msecs(now - txq->time_stamp));
46bc8d4b 4819 ret = il_force_reset(il, false);
be663ab6
WYG		 4820 return (ret == -EAGAIN) ? 0 : 1;
4821 }
4822
4823 return 0;
4824}
4825
4826/*
4827 * Making watchdog tick be a quarter of timeout assure we will
4828 * discover the queue hung between timeout and 1.25*timeout
4829 */
e2ebc833 4830#define IL_WD_TICK(timeout) ((timeout) / 4)
be663ab6
WYG		 4831
4832/*
4833 * Watchdog timer callback, we check each tx queue for stuck, if if hung
4834 * we reset the firmware. If everything is fine just rearm the timer.
4835 */
e7392364
SG		 4836void
4837il_bg_watchdog(unsigned long data)
be663ab6 4838{
46bc8d4b 4839 struct il_priv *il = (struct il_priv *)data;
be663ab6
WYG		 4840 int cnt;
4841 unsigned long timeout;
4842
a6766ccd 4843 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 4844 return;
4845
89ef1ed2 4846 timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4847 if (timeout == 0)
4848 return;
4849
4850 /* monitor and check for stuck cmd queue */
46bc8d4b 4851 if (il_check_stuck_queue(il, il->cmd_queue))
be663ab6
WYG		 4852 return;
4853
4854 /* monitor and check for other stuck queues */
c2ca7d92
SG		 4855 for (cnt = 0; cnt < il->hw_params.max_txq_num; cnt++) {
4856 /* skip as we already checked the command queue */
4857 if (cnt == il->cmd_queue)
4858 continue;
4859 if (il_check_stuck_queue(il, cnt))
4860 return;
be663ab6
WYG		 4861 }
4862
e7392364
SG		 4863 mod_timer(&il->watchdog,
4864 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4865}
e2ebc833 4866EXPORT_SYMBOL(il_bg_watchdog);
be663ab6 4867
e7392364
SG		 4868void
4869il_setup_watchdog(struct il_priv *il)
be663ab6 4870{
89ef1ed2 4871 unsigned int timeout = il->cfg->wd_timeout;
be663ab6
WYG		 4872
4873 if (timeout)
46bc8d4b 4874 mod_timer(&il->watchdog,
e2ebc833 4875 jiffies + msecs_to_jiffies(IL_WD_TICK(timeout)));
be663ab6 4876 else
46bc8d4b 4877 del_timer(&il->watchdog);
be663ab6 4878}
e2ebc833 4879EXPORT_SYMBOL(il_setup_watchdog);
be663ab6
WYG		 4880
4881/*
4882 * extended beacon time format
4883 * time in usec will be changed into a 32-bit value in extended:internal format
4884 * the extended part is the beacon counts
4885 * the internal part is the time in usec within one beacon interval
4886 */
4887u32
e7392364 4888il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval)
be663ab6
WYG		 4889{
4890 u32 quot;
4891 u32 rem;
4892 u32 interval = beacon_interval * TIME_UNIT;
4893
4894 if (!interval || !usec)
4895 return 0;
4896
e7392364
SG		 4897 quot =
4898 (usec /
4899 interval) & (il_beacon_time_mask_high(il,
4900 il->hw_params.
4901 beacon_time_tsf_bits) >> il->
4902 hw_params.beacon_time_tsf_bits);
4903 rem =
4904 (usec % interval) & il_beacon_time_mask_low(il,
4905 il->hw_params.
4906 beacon_time_tsf_bits);
be663ab6 4907
46bc8d4b 4908 return (quot << il->hw_params.beacon_time_tsf_bits) + rem;
be663ab6 4909}
e2ebc833 4910EXPORT_SYMBOL(il_usecs_to_beacons);
be663ab6
WYG		 4911
4912/* base is usually what we get from ucode with each received frame,
4913 * the same as HW timer counter counting down
4914 */
e7392364 4915__le32
1722f8e1 4916il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
e7392364 4917 u32 beacon_interval)
be663ab6 4918{
46bc8d4b 4919 u32 base_low = base & il_beacon_time_mask_low(il,
e7392364
SG		 4920 il->hw_params.
4921 beacon_time_tsf_bits);
46bc8d4b 4922 u32 addon_low = addon & il_beacon_time_mask_low(il,
e7392364
SG		 4923 il->hw_params.
4924 beacon_time_tsf_bits);
be663ab6 4925 u32 interval = beacon_interval * TIME_UNIT;
46bc8d4b 4926 u32 res = (base & il_beacon_time_mask_high(il,
e7392364
SG		 4927 il->hw_params.
4928 beacon_time_tsf_bits)) +
4929 (addon & il_beacon_time_mask_high(il,
4930 il->hw_params.
4931 beacon_time_tsf_bits));
be663ab6
WYG		 4932
4933 if (base_low > addon_low)
4934 res += base_low - addon_low;
4935 else if (base_low < addon_low) {
4936 res += interval + base_low - addon_low;
46bc8d4b 4937 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6 4938 } else
46bc8d4b 4939 res += (1 << il->hw_params.beacon_time_tsf_bits);
be663ab6
WYG		 4940
4941 return cpu_to_le32(res);
4942}
e2ebc833 4943EXPORT_SYMBOL(il_add_beacon_time);
be663ab6 4944
e82add55 4945#ifdef CONFIG_PM_SLEEP
be663ab6 4946
450e9038 4947static int
e7392364 4948il_pci_suspend(struct device *device)
be663ab6
WYG		 4949{
4950 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 4951 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 4952
4953 /*
4954 * This function is called when system goes into suspend state
e2ebc833
SG		 4955 * mac80211 will call il_mac_stop() from the mac80211 suspend function
4956 * first but since il_mac_stop() has no knowledge of who the caller is,
be663ab6
WYG		 4957 * it will not call apm_ops.stop() to stop the DMA operation.
4958 * Calling apm_ops.stop here to make sure we stop the DMA.
4959 */
46bc8d4b 4960 il_apm_stop(il);
be663ab6
WYG		 4961
4962 return 0;
4963}
be663ab6 4964
450e9038 4965static int
e7392364 4966il_pci_resume(struct device *device)
be663ab6
WYG		 4967{
4968 struct pci_dev *pdev = to_pci_dev(device);
46bc8d4b 4969 struct il_priv *il = pci_get_drvdata(pdev);
be663ab6
WYG		 4970 bool hw_rfkill = false;
4971
4972 /*
4973 * We disable the RETRY_TIMEOUT register (0x41) to keep
4974 * PCI Tx retries from interfering with C3 CPU state.
4975 */
4976 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4977
46bc8d4b 4978 il_enable_interrupts(il);
be663ab6 4979
e7392364 4980 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
be663ab6
WYG		 4981 hw_rfkill = true;
4982
4983 if (hw_rfkill)
bc269a8e 4984 set_bit(S_RFKILL, &il->status);
be663ab6 4985 else
bc269a8e 4986 clear_bit(S_RFKILL, &il->status);
be663ab6 4987
46bc8d4b 4988 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rfkill);
be663ab6
WYG		 4989
4990 return 0;
4991}
be663ab6 4992
450e9038 4993SIMPLE_DEV_PM_OPS(il_pm_ops, il_pci_suspend, il_pci_resume);
e2ebc833 4994EXPORT_SYMBOL(il_pm_ops);
be663ab6 4995
e82add55 4996#endif /* CONFIG_PM_SLEEP */
be663ab6
WYG		 4997
4998static void
83007196 4999il_update_qos(struct il_priv *il)
be663ab6 5000{
a6766ccd 5001 if (test_bit(S_EXIT_PENDING, &il->status))
be663ab6
WYG		 5002 return;
5003
8d44f2bd 5004 il->qos_data.def_qos_parm.qos_flags = 0;
be663ab6 5005
8d44f2bd
SG		 5006 if (il->qos_data.qos_active)
5007 il->qos_data.def_qos_parm.qos_flags |=
e7392364 5008 QOS_PARAM_FLG_UPDATE_EDCA_MSK;
be663ab6 5009
1c03c462 5010 if (il->ht.enabled)
8d44f2bd 5011 il->qos_data.def_qos_parm.qos_flags |= QOS_PARAM_FLG_TGN_MSK;
be663ab6 5012
58de00a4 5013 D_QOS("send QoS cmd with Qos active=%d FLAGS=0x%X\n",
8d44f2bd 5014 il->qos_data.qos_active, il->qos_data.def_qos_parm.qos_flags);
be663ab6 5015
b96ed60c 5016 il_send_cmd_pdu_async(il, C_QOS_PARAM, sizeof(struct il_qosparam_cmd),
8d44f2bd 5017 &il->qos_data.def_qos_parm, NULL);
be663ab6
WYG		 5018}
5019
5020/**
e2ebc833 5021 * il_mac_config - mac80211 config callback
be663ab6 5022 */
e7392364
SG		 5023int
5024il_mac_config(struct ieee80211_hw *hw, u32 changed)
be663ab6 5025{
46bc8d4b 5026 struct il_priv *il = hw->priv;
e2ebc833 5027 const struct il_channel_info *ch_info;
be663ab6 5028 struct ieee80211_conf *conf = &hw->conf;
675a0b04 5029 struct ieee80211_channel *channel = conf->chandef.chan;
46bc8d4b 5030 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5031 unsigned long flags = 0;
5032 int ret = 0;
5033 u16 ch;
5034 int scan_active = 0;
7c2cde2e 5035 bool ht_changed = false;
be663ab6 5036
46bc8d4b 5037 mutex_lock(&il->mutex);
9ce7b73c 5038 D_MAC80211("enter: channel %d changed 0x%X\n", channel->hw_value,
e7392364 5039 changed);
be663ab6 5040
a6766ccd 5041 if (unlikely(test_bit(S_SCANNING, &il->status))) {
be663ab6 5042 scan_active = 1;
58de00a4 5043 D_MAC80211("scan active\n");
be663ab6
WYG		 5044 }
5045
e7392364
SG		 5046 if (changed &
5047 (IEEE80211_CONF_CHANGE_SMPS | IEEE80211_CONF_CHANGE_CHANNEL)) {
be663ab6 5048 /* mac80211 uses static for non-HT which is what we want */
46bc8d4b 5049 il->current_ht_config.smps = conf->smps_mode;
be663ab6
WYG		 5050
5051 /*
5052 * Recalculate chain counts.
5053 *
5054 * If monitor mode is enabled then mac80211 will
5055 * set up the SM PS mode to OFF if an HT channel is
5056 * configured.
5057 */
c9363551
SG		 5058 if (il->ops->set_rxon_chain)
5059 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5060 }
5061
5062 /* during scanning mac80211 will delay channel setting until
5063 * scan finish with changed = 0
5064 */
5065 if (!changed || (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
17d6e557 5066
be663ab6
WYG		 5067 if (scan_active)
5068 goto set_ch_out;
5069
5070 ch = channel->hw_value;
46bc8d4b 5071 ch_info = il_get_channel_info(il, channel->band, ch);
e2ebc833 5072 if (!il_is_channel_valid(ch_info)) {
58de00a4 5073 D_MAC80211("leave - invalid channel\n");
be663ab6
WYG		 5074 ret = -EINVAL;
5075 goto set_ch_out;
5076 }
5077
46bc8d4b 5078 if (il->iw_mode == NL80211_IFTYPE_ADHOC &&
e2ebc833 5079 !il_is_channel_ibss(ch_info)) {
58de00a4 5080 D_MAC80211("leave - not IBSS channel\n");
eb85de3f
SG		 5081 ret = -EINVAL;
5082 goto set_ch_out;
5083 }
5084
46bc8d4b 5085 spin_lock_irqsave(&il->lock, flags);
be663ab6 5086
17d6e557 5087 /* Configure HT40 channels */
1c03c462
SG		 5088 if (il->ht.enabled != conf_is_ht(conf)) {
5089 il->ht.enabled = conf_is_ht(conf);
17d6e557
SG		 5090 ht_changed = true;
5091 }
1c03c462 5092 if (il->ht.enabled) {
17d6e557 5093 if (conf_is_ht40_minus(conf)) {
1c03c462 5094 il->ht.extension_chan_offset =
e7392364 5095 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
1c03c462 5096 il->ht.is_40mhz = true;
17d6e557 5097 } else if (conf_is_ht40_plus(conf)) {
1c03c462 5098 il->ht.extension_chan_offset =
e7392364 5099 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
1c03c462 5100 il->ht.is_40mhz = true;
17d6e557 5101 } else {
1c03c462 5102 il->ht.extension_chan_offset =
e7392364 5103 IEEE80211_HT_PARAM_CHA_SEC_NONE;
1c03c462 5104 il->ht.is_40mhz = false;
17d6e557
SG		 5105 }
5106 } else
1c03c462 5107 il->ht.is_40mhz = false;
be663ab6 5108
17d6e557
SG		 5109 /*
5110 * Default to no protection. Protection mode will
5111 * later be set from BSS config in il_ht_conf
5112 */
1c03c462 5113 il->ht.protection = IEEE80211_HT_OP_MODE_PROTECTION_NONE;
be663ab6 5114
17d6e557
SG		 5115 /* if we are switching from ht to 2.4 clear flags
5116 * from any ht related info since 2.4 does not
5117 * support ht */
c8b03958
SG		 5118 if ((le16_to_cpu(il->staging.channel) != ch))
5119 il->staging.flags = 0;
be663ab6 5120
83007196 5121 il_set_rxon_channel(il, channel);
17d6e557 5122 il_set_rxon_ht(il, ht_conf);
be663ab6 5123
83007196 5124 il_set_flags_for_band(il, channel->band, il->vif);
be663ab6 5125
46bc8d4b 5126 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5127
c9363551
SG		 5128 if (il->ops->update_bcast_stations)
5129 ret = il->ops->update_bcast_stations(il);
be663ab6 5130
e7392364 5131set_ch_out:
be663ab6
WYG		 5132 /* The list of supported rates and rate mask can be different
5133 * for each band; since the band may have changed, reset
5134 * the rate mask to what mac80211 lists */
46bc8d4b 5135 il_set_rate(il);
be663ab6
WYG		 5136 }
5137
e7392364 5138 if (changed & (IEEE80211_CONF_CHANGE_PS | IEEE80211_CONF_CHANGE_IDLE)) {
dbdac2b5 5139 il->power_data.ps_disabled = !(conf->flags & IEEE80211_CONF_PS);
46bc8d4b 5140 ret = il_power_update_mode(il, false);
be663ab6 5141 if (ret)
58de00a4 5142 D_MAC80211("Error setting sleep level\n");
be663ab6
WYG		 5143 }
5144
5145 if (changed & IEEE80211_CONF_CHANGE_POWER) {
e7392364
SG		 5146 D_MAC80211("TX Power old=%d new=%d\n", il->tx_power_user_lmt,
5147 conf->power_level);
be663ab6 5148
46bc8d4b 5149 il_set_tx_power(il, conf->power_level, false);
be663ab6
WYG		 5150 }
5151
46bc8d4b 5152 if (!il_is_ready(il)) {
58de00a4 5153 D_MAC80211("leave - not ready\n");
be663ab6
WYG		 5154 goto out;
5155 }
5156
5157 if (scan_active)
5158 goto out;
5159
c8b03958 5160 if (memcmp(&il->active, &il->staging, sizeof(il->staging)))
83007196 5161 il_commit_rxon(il);
17d6e557
SG		 5162 else
5163 D_INFO("Not re-sending same RXON configuration.\n");
5164 if (ht_changed)
83007196 5165 il_update_qos(il);
be663ab6
WYG		 5166
5167out:
9ce7b73c 5168 D_MAC80211("leave ret %d\n", ret);
46bc8d4b 5169 mutex_unlock(&il->mutex);
9ce7b73c 5170
be663ab6
WYG		 5171 return ret;
5172}
e2ebc833 5173EXPORT_SYMBOL(il_mac_config);
be663ab6 5174
e7392364
SG		 5175void
5176il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5177{
46bc8d4b 5178 struct il_priv *il = hw->priv;
be663ab6 5179 unsigned long flags;
be663ab6 5180
46bc8d4b 5181 mutex_lock(&il->mutex);
9ce7b73c 5182 D_MAC80211("enter: type %d, addr %pM\n", vif->type, vif->addr);
be663ab6 5183
46bc8d4b 5184 spin_lock_irqsave(&il->lock, flags);
be663ab6 5185
9ce7b73c 5186 memset(&il->current_ht_config, 0, sizeof(struct il_ht_config));
be663ab6
WYG		 5187
5188 /* new association get rid of ibss beacon skb */
46bc8d4b
SG		 5189 if (il->beacon_skb)
5190 dev_kfree_skb(il->beacon_skb);
46bc8d4b 5191 il->beacon_skb = NULL;
46bc8d4b 5192 il->timestamp = 0;
be663ab6 5193
46bc8d4b 5194 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5195
46bc8d4b
SG		 5196 il_scan_cancel_timeout(il, 100);
5197 if (!il_is_ready_rf(il)) {
58de00a4 5198 D_MAC80211("leave - not ready\n");
46bc8d4b 5199 mutex_unlock(&il->mutex);
be663ab6
WYG		 5200 return;
5201 }
5202
9ce7b73c 5203 /* we are restarting association process */
c8b03958 5204 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
83007196 5205 il_commit_rxon(il);
be663ab6 5206
46bc8d4b 5207 il_set_rate(il);
be663ab6 5208
58de00a4 5209 D_MAC80211("leave\n");
9ce7b73c 5210 mutex_unlock(&il->mutex);
be663ab6 5211}
e2ebc833 5212EXPORT_SYMBOL(il_mac_reset_tsf);
be663ab6 5213
e7392364
SG		 5214static void
5215il_ht_conf(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5216{
46bc8d4b 5217 struct il_ht_config *ht_conf = &il->current_ht_config;
be663ab6
WYG		 5218 struct ieee80211_sta *sta;
5219 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
be663ab6 5220
58de00a4 5221 D_ASSOC("enter:\n");
be663ab6 5222
1c03c462 5223 if (!il->ht.enabled)
be663ab6
WYG		 5224 return;
5225
1c03c462 5226 il->ht.protection =
e7392364 5227 bss_conf->ht_operation_mode & IEEE80211_HT_OP_MODE_PROTECTION;
1c03c462 5228 il->ht.non_gf_sta_present =
e7392364
SG		 5229 !!(bss_conf->
5230 ht_operation_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
be663ab6
WYG		 5231
5232 ht_conf->single_chain_sufficient = false;
5233
5234 switch (vif->type) {
5235 case NL80211_IFTYPE_STATION:
5236 rcu_read_lock();
5237 sta = ieee80211_find_sta(vif, bss_conf->bssid);
5238 if (sta) {
5239 struct ieee80211_sta_ht_cap *ht_cap = &sta->ht_cap;
5240 int maxstreams;
5241
e7392364
SG		 5242 maxstreams =
5243 (ht_cap->mcs.
5244 tx_params & IEEE80211_HT_MCS_TX_MAX_STREAMS_MASK)
5245 >> IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
be663ab6
WYG		 5246 maxstreams += 1;
5247
232913b5
SG		 5248 if (ht_cap->mcs.rx_mask[1] == 0 &&
5249 ht_cap->mcs.rx_mask[2] == 0)
be663ab6
WYG		 5250 ht_conf->single_chain_sufficient = true;
5251 if (maxstreams <= 1)
5252 ht_conf->single_chain_sufficient = true;
5253 } else {
5254 /*
5255 * If at all, this can only happen through a race
5256 * when the AP disconnects us while we're still
5257 * setting up the connection, in that case mac80211
5258 * will soon tell us about that.
5259 */
5260 ht_conf->single_chain_sufficient = true;
5261 }
5262 rcu_read_unlock();
5263 break;
5264 case NL80211_IFTYPE_ADHOC:
5265 ht_conf->single_chain_sufficient = true;
5266 break;
5267 default:
5268 break;
5269 }
5270
58de00a4 5271 D_ASSOC("leave\n");
be663ab6
WYG		 5272}
5273
e7392364
SG		 5274static inline void
5275il_set_no_assoc(struct il_priv *il, struct ieee80211_vif *vif)
be663ab6 5276{
be663ab6
WYG		 5277 /*
5278 * inform the ucode that there is no longer an
5279 * association and that no more packets should be
5280 * sent
5281 */
c8b03958
SG		 5282 il->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
5283 il->staging.assoc_id = 0;
83007196 5284 il_commit_rxon(il);
be663ab6
WYG		 5285}
5286
e7392364
SG		 5287static void
5288il_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
be663ab6 5289{
46bc8d4b 5290 struct il_priv *il = hw->priv;
be663ab6
WYG		 5291 unsigned long flags;
5292 __le64 timestamp;
5293 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
5294
5295 if (!skb)
5296 return;
5297
58de00a4 5298 D_MAC80211("enter\n");
be663ab6 5299
46bc8d4b 5300 lockdep_assert_held(&il->mutex);
be663ab6 5301
83007196
SG		 5302 if (!il->beacon_enabled) {
5303 IL_ERR("update beacon with no beaconing enabled\n");
be663ab6
WYG		 5304 dev_kfree_skb(skb);
5305 return;
5306 }
5307
46bc8d4b 5308 spin_lock_irqsave(&il->lock, flags);
be663ab6 5309
46bc8d4b
SG		 5310 if (il->beacon_skb)
5311 dev_kfree_skb(il->beacon_skb);
be663ab6 5312
46bc8d4b 5313 il->beacon_skb = skb;
be663ab6
WYG		 5314
5315 timestamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
46bc8d4b 5316 il->timestamp = le64_to_cpu(timestamp);
be663ab6 5317
58de00a4 5318 D_MAC80211("leave\n");
46bc8d4b 5319 spin_unlock_irqrestore(&il->lock, flags);
be663ab6 5320
46bc8d4b 5321 if (!il_is_ready_rf(il)) {
58de00a4 5322 D_MAC80211("leave - RF not ready\n");
be663ab6
WYG		 5323 return;
5324 }
5325
c9363551 5326 il->ops->post_associate(il);
be663ab6
WYG		 5327}
5328
e7392364
SG		 5329void
5330il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5331 struct ieee80211_bss_conf *bss_conf, u32 changes)
be663ab6 5332{
46bc8d4b 5333 struct il_priv *il = hw->priv;
be663ab6
WYG		 5334 int ret;
5335
46bc8d4b 5336 mutex_lock(&il->mutex);
9ce7b73c 5337 D_MAC80211("enter: changes 0x%x\n", changes);
be663ab6 5338
46bc8d4b 5339 if (!il_is_alive(il)) {
9ce7b73c 5340 D_MAC80211("leave - not alive\n");
46bc8d4b 5341 mutex_unlock(&il->mutex);
28a6e577
SG		 5342 return;
5343 }
5344
be663ab6
WYG		 5345 if (changes & BSS_CHANGED_QOS) {
5346 unsigned long flags;
5347
46bc8d4b 5348 spin_lock_irqsave(&il->lock, flags);
8d44f2bd 5349 il->qos_data.qos_active = bss_conf->qos;
83007196 5350 il_update_qos(il);
46bc8d4b 5351 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5352 }
5353
5354 if (changes & BSS_CHANGED_BEACON_ENABLED) {
83007196 5355 /* FIXME: can we remove beacon_enabled ? */
be663ab6 5356 if (vif->bss_conf.enable_beacon)
83007196 5357 il->beacon_enabled = true;
be663ab6 5358 else
83007196 5359 il->beacon_enabled = false;
be663ab6
WYG		 5360 }
5361
5362 if (changes & BSS_CHANGED_BSSID) {
58de00a4 5363 D_MAC80211("BSSID %pM\n", bss_conf->bssid);
be663ab6 5364
8cdbab7f
SG		 5365 /*
5366 * On passive channel we wait with blocked queues to see if
5367 * there is traffic on that channel. If no frame will be
5368 * received (what is very unlikely since scan detects AP on
5369 * that channel, but theoretically possible), mac80211 associate
5370 * procedure will time out and mac80211 will call us with NULL
5371 * bssid. We have to unblock queues on such condition.
5372 */
5373 if (is_zero_ether_addr(bss_conf->bssid))
5374 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE);
5375
be663ab6 5376 /*
e92109be
SG		 5377 * If there is currently a HW scan going on in the background,
5378 * then we need to cancel it, otherwise sometimes we are not
5379 * able to authenticate (FIXME: why ?)
be663ab6 5380 */
46bc8d4b 5381 if (il_scan_cancel_timeout(il, 100)) {
9ce7b73c 5382 D_MAC80211("leave - scan abort failed\n");
46bc8d4b 5383 mutex_unlock(&il->mutex);
be663ab6
WYG		 5384 return;
5385 }
5386
5387 /* mac80211 only sets assoc when in STATION mode */
e92109be 5388 memcpy(il->staging.bssid_addr, bss_conf->bssid, ETH_ALEN);
be663ab6 5389
e92109be
SG		 5390 /* FIXME: currently needed in a few places */
5391 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
be663ab6
WYG		 5392 }
5393
5394 /*
5395 * This needs to be after setting the BSSID in case
5396 * mac80211 decides to do both changes at once because
5397 * it will invoke post_associate.
5398 */
232913b5 5399 if (vif->type == NL80211_IFTYPE_ADHOC && (changes & BSS_CHANGED_BEACON))
e2ebc833 5400 il_beacon_update(hw, vif);
be663ab6
WYG		 5401
5402 if (changes & BSS_CHANGED_ERP_PREAMBLE) {
e7392364 5403 D_MAC80211("ERP_PREAMBLE %d\n", bss_conf->use_short_preamble);
be663ab6 5404 if (bss_conf->use_short_preamble)
c8b03958 5405 il->staging.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6 5406 else
c8b03958 5407 il->staging.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
be663ab6
WYG		 5408 }
5409
5410 if (changes & BSS_CHANGED_ERP_CTS_PROT) {
e7392364 5411 D_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
232913b5 5412 if (bss_conf->use_cts_prot && il->band != IEEE80211_BAND_5GHZ)
c8b03958 5413 il->staging.flags |= RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5414 else
c8b03958 5415 il->staging.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
be663ab6 5416 if (bss_conf->use_cts_prot)
c8b03958 5417 il->staging.flags |= RXON_FLG_SELF_CTS_EN;
be663ab6 5418 else
c8b03958 5419 il->staging.flags &= ~RXON_FLG_SELF_CTS_EN;
be663ab6
WYG		 5420 }
5421
5422 if (changes & BSS_CHANGED_BASIC_RATES) {
5423 /* XXX use this information
5424 *
e2ebc833 5425 * To do that, remove code from il_set_rate() and put something
be663ab6
WYG		 5426 * like this here:
5427 *
e7392364 5428 if (A-band)
c8b03958 5429 il->staging.ofdm_basic_rates =
e7392364
SG		 5430 bss_conf->basic_rates;
5431 else
c8b03958 5432 il->staging.ofdm_basic_rates =
e7392364 5433 bss_conf->basic_rates >> 4;
c8b03958 5434 il->staging.cck_basic_rates =
e7392364 5435 bss_conf->basic_rates & 0xF;
be663ab6
WYG		 5436 */
5437 }
5438
5439 if (changes & BSS_CHANGED_HT) {
46bc8d4b 5440 il_ht_conf(il, vif);
be663ab6 5441
c9363551
SG		 5442 if (il->ops->set_rxon_chain)
5443 il->ops->set_rxon_chain(il);
be663ab6
WYG		 5444 }
5445
5446 if (changes & BSS_CHANGED_ASSOC) {
58de00a4 5447 D_MAC80211("ASSOC %d\n", bss_conf->assoc);
be663ab6 5448 if (bss_conf->assoc) {
8c358bcd 5449 il->timestamp = bss_conf->sync_tsf;
be663ab6 5450
46bc8d4b 5451 if (!il_is_rfkill(il))
c9363551 5452 il->ops->post_associate(il);
be663ab6 5453 } else
46bc8d4b 5454 il_set_no_assoc(il, vif);
be663ab6
WYG		 5455 }
5456
c8b03958 5457 if (changes && il_is_associated(il) && bss_conf->aid) {
e7392364 5458 D_MAC80211("Changes (%#x) while associated\n", changes);
83007196 5459 ret = il_send_rxon_assoc(il);
be663ab6
WYG		 5460 if (!ret) {
5461 /* Sync active_rxon with latest change. */
c8b03958 5462 memcpy((void *)&il->active, &il->staging,
e7392364 5463 sizeof(struct il_rxon_cmd));
be663ab6
WYG		 5464 }
5465 }
5466
5467 if (changes & BSS_CHANGED_BEACON_ENABLED) {
5468 if (vif->bss_conf.enable_beacon) {
c8b03958 5469 memcpy(il->staging.bssid_addr, bss_conf->bssid,
e7392364 5470 ETH_ALEN);
46bc8d4b 5471 memcpy(il->bssid, bss_conf->bssid, ETH_ALEN);
c9363551 5472 il->ops->config_ap(il);
be663ab6 5473 } else
46bc8d4b 5474 il_set_no_assoc(il, vif);
be663ab6
WYG		 5475 }
5476
5477 if (changes & BSS_CHANGED_IBSS) {
9ce7b73c
SG		 5478 ret = il->ops->manage_ibss_station(il, vif,
5479 bss_conf->ibss_joined);
be663ab6 5480 if (ret)
9406f797 5481 IL_ERR("failed to %s IBSS station %pM\n",
e7392364
SG		 5482 bss_conf->ibss_joined ? "add" : "remove",
5483 bss_conf->bssid);
be663ab6
WYG		 5484 }
5485
58de00a4 5486 D_MAC80211("leave\n");
9ce7b73c 5487 mutex_unlock(&il->mutex);
be663ab6 5488}
e2ebc833 5489EXPORT_SYMBOL(il_mac_bss_info_changed);
be663ab6 5490
e7392364
SG		 5491irqreturn_t
5492il_isr(int irq, void *data)
be663ab6 5493{
46bc8d4b 5494 struct il_priv *il = data;
be663ab6
WYG		 5495 u32 inta, inta_mask;
5496 u32 inta_fh;
5497 unsigned long flags;
46bc8d4b 5498 if (!il)
be663ab6
WYG		 5499 return IRQ_NONE;
5500
46bc8d4b 5501 spin_lock_irqsave(&il->lock, flags);
be663ab6
WYG		 5502
5503 /* Disable (but don't clear!) interrupts here to avoid
5504 * back-to-back ISRs and sporadic interrupts from our NIC.
5505 * If we have something to service, the tasklet will re-enable ints.
5506 * If we *don't* have something, we'll re-enable before leaving here. */
e7392364 5507 inta_mask = _il_rd(il, CSR_INT_MASK); /* just for debug */
841b2cca 5508 _il_wr(il, CSR_INT_MASK, 0x00000000);
be663ab6
WYG		 5509
5510 /* Discover which interrupts are active/pending */
841b2cca
SG		 5511 inta = _il_rd(il, CSR_INT);
5512 inta_fh = _il_rd(il, CSR_FH_INT_STATUS);
be663ab6
WYG		 5513
5514 /* Ignore interrupt if there's nothing in NIC to service.
5515 * This may be due to IRQ shared with another device,
5516 * or due to sporadic interrupts thrown from our NIC. */
5517 if (!inta && !inta_fh) {
e7392364 5518 D_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
be663ab6
WYG		 5519 goto none;
5520 }
5521
232913b5 5522 if (inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0) {
be663ab6
WYG		 5523 /* Hardware disappeared. It might have already raised
5524 * an interrupt */
9406f797 5525 IL_WARN("HARDWARE GONE?? INTA == 0x%08x\n", inta);
be663ab6
WYG		 5526 goto unplugged;
5527 }
5528
e7392364
SG		 5529 D_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, inta_mask,
5530 inta_fh);
be663ab6
WYG		 5531
5532 inta &= ~CSR_INT_BIT_SCD;
5533
e2ebc833 5534 /* il_irq_tasklet() will service interrupts and re-enable them */
be663ab6 5535 if (likely(inta || inta_fh))
46bc8d4b 5536 tasklet_schedule(&il->irq_tasklet);
be663ab6
WYG		 5537
5538unplugged:
46bc8d4b 5539 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5540 return IRQ_HANDLED;
5541
5542none:
5543 /* re-enable interrupts here since we don't have anything to service. */
93fd74e3 5544 /* only Re-enable if disabled by irq */
a6766ccd 5545 if (test_bit(S_INT_ENABLED, &il->status))
46bc8d4b
SG		 5546 il_enable_interrupts(il);
5547 spin_unlock_irqrestore(&il->lock, flags);
be663ab6
WYG		 5548 return IRQ_NONE;
5549}
e2ebc833 5550EXPORT_SYMBOL(il_isr);
be663ab6
WYG		 5551
5552/*
e2ebc833 5553 * il_tx_cmd_protection: Set rts/cts. 3945 and 4965 only share this
be663ab6
WYG		 5554 * function.
5555 */
e7392364
SG		 5556void
5557il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1722f8e1 5558 __le16 fc, __le32 *tx_flags)
be663ab6
WYG		 5559{
5560 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
5561 *tx_flags |= TX_CMD_FLG_RTS_MSK;
5562 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
5563 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5564
5565 if (!ieee80211_is_mgmt(fc))
5566 return;
5567
5568 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
5569 case cpu_to_le16(IEEE80211_STYPE_AUTH):
5570 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
5571 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
5572 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
5573 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5574 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5575 break;
5576 }
e7392364
SG		 5577 } else if (info->control.rates[0].
5578 flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
be663ab6
WYG		 5579 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
5580 *tx_flags |= TX_CMD_FLG_CTS_MSK;
5581 *tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
5582 }
5583}
e2ebc833 5584EXPORT_SYMBOL(il_tx_cmd_protection);
Linux 6.x block layer and io_uring tree(s)