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5b435de0 AS |
1 | /* |
2 | * Copyright (c) 2010 Broadcom Corporation | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION | |
13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN | |
14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef _SBCHIPC_H | |
18 | #define _SBCHIPC_H | |
19 | ||
20 | #include "defs.h" /* for PAD macro */ | |
21 | ||
373c78e1 AS |
22 | #define CHIPCREGOFFS(field) offsetof(struct chipcregs, field) |
23 | ||
5b435de0 AS |
24 | struct chipcregs { |
25 | u32 chipid; /* 0x0 */ | |
26 | u32 capabilities; | |
27 | u32 corecontrol; /* corerev >= 1 */ | |
28 | u32 bist; | |
29 | ||
30 | /* OTP */ | |
31 | u32 otpstatus; /* 0x10, corerev >= 10 */ | |
32 | u32 otpcontrol; | |
33 | u32 otpprog; | |
34 | u32 otplayout; /* corerev >= 23 */ | |
35 | ||
36 | /* Interrupt control */ | |
37 | u32 intstatus; /* 0x20 */ | |
38 | u32 intmask; | |
39 | ||
40 | /* Chip specific regs */ | |
41 | u32 chipcontrol; /* 0x28, rev >= 11 */ | |
42 | u32 chipstatus; /* 0x2c, rev >= 11 */ | |
43 | ||
44 | /* Jtag Master */ | |
45 | u32 jtagcmd; /* 0x30, rev >= 10 */ | |
46 | u32 jtagir; | |
47 | u32 jtagdr; | |
48 | u32 jtagctrl; | |
49 | ||
50 | /* serial flash interface registers */ | |
51 | u32 flashcontrol; /* 0x40 */ | |
52 | u32 flashaddress; | |
53 | u32 flashdata; | |
54 | u32 PAD[1]; | |
55 | ||
56 | /* Silicon backplane configuration broadcast control */ | |
57 | u32 broadcastaddress; /* 0x50 */ | |
58 | u32 broadcastdata; | |
59 | ||
60 | /* gpio - cleared only by power-on-reset */ | |
61 | u32 gpiopullup; /* 0x58, corerev >= 20 */ | |
62 | u32 gpiopulldown; /* 0x5c, corerev >= 20 */ | |
63 | u32 gpioin; /* 0x60 */ | |
64 | u32 gpioout; /* 0x64 */ | |
65 | u32 gpioouten; /* 0x68 */ | |
66 | u32 gpiocontrol; /* 0x6C */ | |
67 | u32 gpiointpolarity; /* 0x70 */ | |
68 | u32 gpiointmask; /* 0x74 */ | |
69 | ||
70 | /* GPIO events corerev >= 11 */ | |
71 | u32 gpioevent; | |
72 | u32 gpioeventintmask; | |
73 | ||
74 | /* Watchdog timer */ | |
75 | u32 watchdog; /* 0x80 */ | |
76 | ||
77 | /* GPIO events corerev >= 11 */ | |
78 | u32 gpioeventintpolarity; | |
79 | ||
80 | /* GPIO based LED powersave registers corerev >= 16 */ | |
81 | u32 gpiotimerval; /* 0x88 */ | |
82 | u32 gpiotimeroutmask; | |
83 | ||
84 | /* clock control */ | |
85 | u32 clockcontrol_n; /* 0x90 */ | |
86 | u32 clockcontrol_sb; /* aka m0 */ | |
87 | u32 clockcontrol_pci; /* aka m1 */ | |
88 | u32 clockcontrol_m2; /* mii/uart/mipsref */ | |
89 | u32 clockcontrol_m3; /* cpu */ | |
90 | u32 clkdiv; /* corerev >= 3 */ | |
91 | u32 gpiodebugsel; /* corerev >= 28 */ | |
92 | u32 capabilities_ext; /* 0xac */ | |
93 | ||
94 | /* pll delay registers (corerev >= 4) */ | |
95 | u32 pll_on_delay; /* 0xb0 */ | |
96 | u32 fref_sel_delay; | |
97 | u32 slow_clk_ctl; /* 5 < corerev < 10 */ | |
98 | u32 PAD; | |
99 | ||
100 | /* Instaclock registers (corerev >= 10) */ | |
101 | u32 system_clk_ctl; /* 0xc0 */ | |
102 | u32 clkstatestretch; | |
103 | u32 PAD[2]; | |
104 | ||
105 | /* Indirect backplane access (corerev >= 22) */ | |
106 | u32 bp_addrlow; /* 0xd0 */ | |
107 | u32 bp_addrhigh; | |
108 | u32 bp_data; | |
109 | u32 PAD; | |
110 | u32 bp_indaccess; | |
111 | u32 PAD[3]; | |
112 | ||
113 | /* More clock dividers (corerev >= 32) */ | |
114 | u32 clkdiv2; | |
115 | u32 PAD[2]; | |
116 | ||
117 | /* In AI chips, pointer to erom */ | |
118 | u32 eromptr; /* 0xfc */ | |
119 | ||
120 | /* ExtBus control registers (corerev >= 3) */ | |
121 | u32 pcmcia_config; /* 0x100 */ | |
122 | u32 pcmcia_memwait; | |
123 | u32 pcmcia_attrwait; | |
124 | u32 pcmcia_iowait; | |
125 | u32 ide_config; | |
126 | u32 ide_memwait; | |
127 | u32 ide_attrwait; | |
128 | u32 ide_iowait; | |
129 | u32 prog_config; | |
130 | u32 prog_waitcount; | |
131 | u32 flash_config; | |
132 | u32 flash_waitcount; | |
133 | u32 SECI_config; /* 0x130 SECI configuration */ | |
134 | u32 PAD[3]; | |
135 | ||
136 | /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ | |
137 | u32 eci_output; /* 0x140 */ | |
138 | u32 eci_control; | |
139 | u32 eci_inputlo; | |
140 | u32 eci_inputmi; | |
141 | u32 eci_inputhi; | |
142 | u32 eci_inputintpolaritylo; | |
143 | u32 eci_inputintpolaritymi; | |
144 | u32 eci_inputintpolarityhi; | |
145 | u32 eci_intmasklo; | |
146 | u32 eci_intmaskmi; | |
147 | u32 eci_intmaskhi; | |
148 | u32 eci_eventlo; | |
149 | u32 eci_eventmi; | |
150 | u32 eci_eventhi; | |
151 | u32 eci_eventmasklo; | |
152 | u32 eci_eventmaskmi; | |
153 | u32 eci_eventmaskhi; | |
154 | u32 PAD[3]; | |
155 | ||
156 | /* SROM interface (corerev >= 32) */ | |
157 | u32 sromcontrol; /* 0x190 */ | |
158 | u32 sromaddress; | |
159 | u32 sromdata; | |
160 | u32 PAD[17]; | |
161 | ||
162 | /* Clock control and hardware workarounds (corerev >= 20) */ | |
163 | u32 clk_ctl_st; /* 0x1e0 */ | |
164 | u32 hw_war; | |
165 | u32 PAD[70]; | |
166 | ||
167 | /* UARTs */ | |
168 | u8 uart0data; /* 0x300 */ | |
169 | u8 uart0imr; | |
170 | u8 uart0fcr; | |
171 | u8 uart0lcr; | |
172 | u8 uart0mcr; | |
173 | u8 uart0lsr; | |
174 | u8 uart0msr; | |
175 | u8 uart0scratch; | |
176 | u8 PAD[248]; /* corerev >= 1 */ | |
177 | ||
178 | u8 uart1data; /* 0x400 */ | |
179 | u8 uart1imr; | |
180 | u8 uart1fcr; | |
181 | u8 uart1lcr; | |
182 | u8 uart1mcr; | |
183 | u8 uart1lsr; | |
184 | u8 uart1msr; | |
185 | u8 uart1scratch; | |
25911556 AS |
186 | u32 PAD[62]; |
187 | ||
188 | /* save/restore, corerev >= 48 */ | |
189 | u32 sr_capability; /* 0x500 */ | |
190 | u32 sr_control0; /* 0x504 */ | |
191 | u32 sr_control1; /* 0x508 */ | |
192 | u32 gpio_control; /* 0x50C */ | |
193 | u32 PAD[60]; | |
5b435de0 AS |
194 | |
195 | /* PMU registers (corerev >= 20) */ | |
196 | u32 pmucontrol; /* 0x600 */ | |
197 | u32 pmucapabilities; | |
198 | u32 pmustatus; | |
199 | u32 res_state; | |
200 | u32 res_pending; | |
201 | u32 pmutimer; | |
202 | u32 min_res_mask; | |
203 | u32 max_res_mask; | |
204 | u32 res_table_sel; | |
205 | u32 res_dep_mask; | |
206 | u32 res_updn_timer; | |
207 | u32 res_timer; | |
208 | u32 clkstretch; | |
209 | u32 pmuwatchdog; | |
210 | u32 gpiosel; /* 0x638, rev >= 1 */ | |
211 | u32 gpioenable; /* 0x63c, rev >= 1 */ | |
212 | u32 res_req_timer_sel; | |
213 | u32 res_req_timer; | |
214 | u32 res_req_mask; | |
4a3da990 | 215 | u32 pmucapabilities_ext; /* 0x64c, pmurev >=15 */ |
5b435de0 AS |
216 | u32 chipcontrol_addr; /* 0x650 */ |
217 | u32 chipcontrol_data; /* 0x654 */ | |
218 | u32 regcontrol_addr; | |
219 | u32 regcontrol_data; | |
220 | u32 pllcontrol_addr; | |
221 | u32 pllcontrol_data; | |
222 | u32 pmustrapopt; /* 0x668, corerev >= 28 */ | |
223 | u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ | |
4a3da990 PH |
224 | u32 retention_ctl; /* 0x670, pmurev >= 15 */ |
225 | u32 PAD[3]; | |
226 | u32 retention_grpidx; /* 0x680 */ | |
227 | u32 retention_grpctl; /* 0x684 */ | |
228 | u32 PAD[94]; | |
5b435de0 AS |
229 | u16 sromotp[768]; |
230 | }; | |
231 | ||
232 | /* chipid */ | |
233 | #define CID_ID_MASK 0x0000ffff /* Chip Id mask */ | |
234 | #define CID_REV_MASK 0x000f0000 /* Chip Revision mask */ | |
235 | #define CID_REV_SHIFT 16 /* Chip Revision shift */ | |
236 | #define CID_PKG_MASK 0x00f00000 /* Package Option mask */ | |
237 | #define CID_PKG_SHIFT 20 /* Package Option shift */ | |
238 | #define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */ | |
239 | #define CID_CC_SHIFT 24 | |
240 | #define CID_TYPE_MASK 0xf0000000 /* Chip Type */ | |
241 | #define CID_TYPE_SHIFT 28 | |
242 | ||
243 | /* capabilities */ | |
244 | #define CC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */ | |
245 | #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ | |
246 | #define CC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ | |
247 | /* UARTs are driven by internal divided clock */ | |
248 | #define CC_CAP_UINTCLK 0x00000008 | |
249 | #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ | |
250 | #define CC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ | |
251 | #define CC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ | |
252 | #define CC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ | |
253 | #define CC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ | |
254 | #define CC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ | |
255 | #define CC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ | |
256 | #define CC_CAP_PWR_CTL 0x00040000 /* Power control */ | |
257 | #define CC_CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */ | |
258 | #define CC_CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */ | |
259 | #define CC_CAP_OTPSIZE_BASE 5 /* OTP Size base */ | |
260 | #define CC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ | |
261 | #define CC_CAP_ROM 0x00800000 /* Internal boot rom active */ | |
262 | #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ | |
263 | #define CC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ | |
264 | #define CC_CAP_SROM 0x40000000 /* Srom Present, rev >= 32 */ | |
265 | /* Nand flash present, rev >= 35 */ | |
266 | #define CC_CAP_NFLASH 0x80000000 | |
267 | ||
268 | #define CC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ | |
269 | /* GSIO (spi/i2c) present, rev >= 37 */ | |
270 | #define CC_CAP2_GSIO 0x00000002 | |
271 | ||
272 | /* pmucapabilities */ | |
273 | #define PCAP_REV_MASK 0x000000ff | |
274 | #define PCAP_RC_MASK 0x00001f00 | |
275 | #define PCAP_RC_SHIFT 8 | |
276 | #define PCAP_TC_MASK 0x0001e000 | |
277 | #define PCAP_TC_SHIFT 13 | |
278 | #define PCAP_PC_MASK 0x001e0000 | |
279 | #define PCAP_PC_SHIFT 17 | |
280 | #define PCAP_VC_MASK 0x01e00000 | |
281 | #define PCAP_VC_SHIFT 21 | |
282 | #define PCAP_CC_MASK 0x1e000000 | |
283 | #define PCAP_CC_SHIFT 25 | |
284 | #define PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ | |
285 | #define PCAP5_PC_SHIFT 17 | |
286 | #define PCAP5_VC_MASK 0x07c00000 | |
287 | #define PCAP5_VC_SHIFT 22 | |
288 | #define PCAP5_CC_MASK 0xf8000000 | |
289 | #define PCAP5_CC_SHIFT 27 | |
4a3da990 PH |
290 | /* pmucapabilites_ext PMU rev >= 15 */ |
291 | #define PCAPEXT_SR_SUPPORTED_MASK (1 << 1) | |
292 | /* retention_ctl PMU rev >= 15 */ | |
293 | #define PMU_RCTL_MACPHY_DISABLE_MASK (1 << 26) | |
294 | #define PMU_RCTL_LOGIC_DISABLE_MASK (1 << 27) | |
295 | ||
5b435de0 AS |
296 | |
297 | /* | |
298 | * Maximum delay for the PMU state transition in us. | |
299 | * This is an upper bound intended for spinwaits etc. | |
300 | */ | |
301 | #define PMU_MAX_TRANSITION_DLY 15000 | |
302 | ||
303 | #endif /* _SBCHIPC_H */ |