Commit | Line | Data |
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424047e6 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | IEEE 802.11n PHY support | |
5 | ||
6 | Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
21 | Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
819d772b JL |
25 | #include <linux/delay.h> |
26 | #include <linux/types.h> | |
27 | ||
424047e6 | 28 | #include "b43.h" |
3d0da751 | 29 | #include "phy_n.h" |
53a6e234 | 30 | #include "tables_nphy.h" |
bbec398c | 31 | #include "main.h" |
424047e6 | 32 | |
f8187b5b RM |
33 | struct nphy_txgains { |
34 | u16 txgm[2]; | |
35 | u16 pga[2]; | |
36 | u16 pad[2]; | |
37 | u16 ipa[2]; | |
38 | }; | |
39 | ||
40 | struct nphy_iqcal_params { | |
41 | u16 txgm; | |
42 | u16 pga; | |
43 | u16 pad; | |
44 | u16 ipa; | |
45 | u16 cal_gain; | |
46 | u16 ncorr[5]; | |
47 | }; | |
48 | ||
49 | struct nphy_iq_est { | |
50 | s32 iq0_prod; | |
51 | u32 i0_pwr; | |
52 | u32 q0_pwr; | |
53 | s32 iq1_prod; | |
54 | u32 i1_pwr; | |
55 | u32 q1_pwr; | |
56 | }; | |
424047e6 | 57 | |
67c0d6e2 RM |
58 | enum b43_nphy_rf_sequence { |
59 | B43_RFSEQ_RX2TX, | |
60 | B43_RFSEQ_TX2RX, | |
61 | B43_RFSEQ_RESET2RX, | |
62 | B43_RFSEQ_UPDATE_GAINH, | |
63 | B43_RFSEQ_UPDATE_GAINL, | |
64 | B43_RFSEQ_UPDATE_GAINU, | |
65 | }; | |
66 | ||
9501fefe RM |
67 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, |
68 | u8 *events, u8 *delays, u8 length); | |
67c0d6e2 RM |
69 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, |
70 | enum b43_nphy_rf_sequence seq); | |
67cbc3ed RM |
71 | static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, |
72 | u16 value, u8 core, bool off); | |
73 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | |
74 | u16 value, u8 core); | |
eff66c51 | 75 | static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel); |
67c0d6e2 | 76 | |
902db91d RM |
77 | static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec) |
78 | { | |
79 | return !chanspec->channel && !chanspec->sideband && | |
80 | !chanspec->b_width && !chanspec->b_freq; | |
81 | } | |
82 | ||
83 | static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1, | |
84 | struct b43_chanspec *chanspec2) | |
85 | { | |
86 | return (chanspec1->channel == chanspec2->channel && | |
87 | chanspec1->sideband == chanspec2->sideband && | |
88 | chanspec1->b_width == chanspec2->b_width && | |
89 | chanspec1->b_freq == chanspec2->b_freq); | |
90 | } | |
91 | ||
53a6e234 MB |
92 | void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) |
93 | {//TODO | |
94 | } | |
95 | ||
18c8adeb | 96 | static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) |
53a6e234 MB |
97 | {//TODO |
98 | } | |
99 | ||
18c8adeb MB |
100 | static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, |
101 | bool ignore_tssi) | |
102 | {//TODO | |
103 | return B43_TXPWR_RES_DONE; | |
104 | } | |
105 | ||
d1591314 MB |
106 | static void b43_chantab_radio_upload(struct b43_wldev *dev, |
107 | const struct b43_nphy_channeltab_entry *e) | |
108 | { | |
e5255ccc RM |
109 | b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); |
110 | b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); | |
111 | b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); | |
112 | b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); | |
113 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
114 | ||
115 | b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); | |
116 | b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); | |
117 | b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); | |
118 | b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); | |
119 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
120 | ||
121 | b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); | |
122 | b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); | |
123 | b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); | |
124 | b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); | |
125 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
126 | ||
127 | b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); | |
128 | b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); | |
129 | b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); | |
130 | b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); | |
131 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
132 | ||
133 | b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); | |
134 | b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); | |
135 | b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); | |
136 | b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); | |
137 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
138 | ||
139 | b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); | |
140 | b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); | |
d1591314 MB |
141 | } |
142 | ||
143 | static void b43_chantab_phy_upload(struct b43_wldev *dev, | |
b15b3039 | 144 | const struct b43_phy_n_sfo_cfg *e) |
d1591314 MB |
145 | { |
146 | b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); | |
147 | b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); | |
148 | b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); | |
149 | b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); | |
150 | b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); | |
151 | b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); | |
152 | } | |
153 | ||
154 | static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |
155 | { | |
156 | //TODO | |
157 | } | |
158 | ||
7955de0c RM |
159 | |
160 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ | |
161 | static void b43_radio_2055_setup(struct b43_wldev *dev, | |
162 | const struct b43_nphy_channeltab_entry *e) | |
163 | { | |
164 | B43_WARN_ON(dev->phy.rev >= 3); | |
165 | ||
166 | b43_chantab_radio_upload(dev, e); | |
167 | udelay(50); | |
168 | b43_radio_write(dev, B2055_VCO_CAL10, 5); | |
169 | b43_radio_write(dev, B2055_VCO_CAL10, 45); | |
170 | b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ | |
171 | b43_radio_write(dev, B2055_VCO_CAL10, 65); | |
172 | udelay(300); | |
173 | } | |
174 | ||
53a6e234 MB |
175 | static void b43_radio_init2055_pre(struct b43_wldev *dev) |
176 | { | |
177 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
178 | ~B43_NPHY_RFCTL_CMD_PORFORCE); | |
179 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
180 | B43_NPHY_RFCTL_CMD_CHIP0PU | | |
181 | B43_NPHY_RFCTL_CMD_OEPORFORCE); | |
182 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
183 | B43_NPHY_RFCTL_CMD_PORFORCE); | |
184 | } | |
185 | ||
186 | static void b43_radio_init2055_post(struct b43_wldev *dev) | |
187 | { | |
036cafe4 | 188 | struct b43_phy_n *nphy = dev->phy.n; |
53a6e234 MB |
189 | struct ssb_sprom *sprom = &(dev->dev->bus->sprom); |
190 | struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); | |
191 | int i; | |
192 | u16 val; | |
036cafe4 RM |
193 | bool workaround = false; |
194 | ||
195 | if (sprom->revision < 4) | |
196 | workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM || | |
197 | binfo->type != 0x46D || | |
198 | binfo->rev < 0x41); | |
199 | else | |
200 | workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0); | |
53a6e234 MB |
201 | |
202 | b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); | |
036cafe4 RM |
203 | if (workaround) { |
204 | b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); | |
205 | b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); | |
53a6e234 | 206 | } |
036cafe4 RM |
207 | b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); |
208 | b43_radio_write(dev, B2055_CAL_MISC, 0x3C); | |
53a6e234 | 209 | b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); |
53a6e234 | 210 | b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); |
53a6e234 MB |
211 | b43_radio_set(dev, B2055_CAL_MISC, 0x1); |
212 | msleep(1); | |
213 | b43_radio_set(dev, B2055_CAL_MISC, 0x40); | |
036cafe4 RM |
214 | for (i = 0; i < 200; i++) { |
215 | val = b43_radio_read(dev, B2055_CAL_COUT2); | |
216 | if (val & 0x80) { | |
217 | i = 0; | |
53a6e234 | 218 | break; |
036cafe4 | 219 | } |
53a6e234 MB |
220 | udelay(10); |
221 | } | |
036cafe4 RM |
222 | if (i) |
223 | b43err(dev->wl, "radio post init timeout\n"); | |
53a6e234 | 224 | b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); |
ef1a628d | 225 | nphy_channel_switch(dev, dev->phy.channel); |
036cafe4 RM |
226 | b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); |
227 | b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); | |
228 | b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); | |
229 | b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); | |
230 | b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); | |
231 | b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); | |
232 | if (!nphy->gain_boost) { | |
233 | b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); | |
234 | b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); | |
235 | } else { | |
236 | b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); | |
237 | b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); | |
238 | } | |
239 | udelay(2); | |
53a6e234 MB |
240 | } |
241 | ||
c2b7aefd RM |
242 | /* |
243 | * Initialize a Broadcom 2055 N-radio | |
244 | * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init | |
245 | */ | |
53a6e234 MB |
246 | static void b43_radio_init2055(struct b43_wldev *dev) |
247 | { | |
248 | b43_radio_init2055_pre(dev); | |
249 | if (b43_status(dev) < B43_STAT_INITIALIZED) | |
250 | b2055_upload_inittab(dev, 0, 1); | |
251 | else | |
252 | b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0); | |
253 | b43_radio_init2055_post(dev); | |
254 | } | |
255 | ||
d817f4e1 RM |
256 | /* |
257 | * Initialize a Broadcom 2056 N-radio | |
258 | * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init | |
259 | */ | |
260 | static void b43_radio_init2056(struct b43_wldev *dev) | |
261 | { | |
262 | /* TODO */ | |
263 | } | |
264 | ||
265 | ||
4772ae10 RM |
266 | /* |
267 | * Upload the N-PHY tables. | |
268 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables | |
269 | */ | |
95b66bad MB |
270 | static void b43_nphy_tables_init(struct b43_wldev *dev) |
271 | { | |
4772ae10 RM |
272 | if (dev->phy.rev < 3) |
273 | b43_nphy_rev0_1_2_tables_init(dev); | |
274 | else | |
275 | b43_nphy_rev3plus_tables_init(dev); | |
95b66bad MB |
276 | } |
277 | ||
e50cbcf6 RM |
278 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ |
279 | static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) | |
280 | { | |
281 | struct b43_phy_n *nphy = dev->phy.n; | |
282 | enum ieee80211_band band; | |
283 | u16 tmp; | |
284 | ||
285 | if (!enable) { | |
286 | nphy->rfctrl_intc1_save = b43_phy_read(dev, | |
287 | B43_NPHY_RFCTL_INTC1); | |
288 | nphy->rfctrl_intc2_save = b43_phy_read(dev, | |
289 | B43_NPHY_RFCTL_INTC2); | |
290 | band = b43_current_band(dev->wl); | |
291 | if (dev->phy.rev >= 3) { | |
292 | if (band == IEEE80211_BAND_5GHZ) | |
293 | tmp = 0x600; | |
294 | else | |
295 | tmp = 0x480; | |
296 | } else { | |
297 | if (band == IEEE80211_BAND_5GHZ) | |
298 | tmp = 0x180; | |
299 | else | |
300 | tmp = 0x120; | |
301 | } | |
302 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
303 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
304 | } else { | |
305 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, | |
306 | nphy->rfctrl_intc1_save); | |
307 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, | |
308 | nphy->rfctrl_intc2_save); | |
309 | } | |
310 | } | |
311 | ||
fe3e46e8 RM |
312 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ |
313 | static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) | |
314 | { | |
315 | struct b43_phy_n *nphy = dev->phy.n; | |
316 | u16 tmp; | |
317 | enum ieee80211_band band = b43_current_band(dev->wl); | |
318 | bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || | |
319 | (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); | |
320 | ||
321 | if (dev->phy.rev >= 3) { | |
322 | if (ipa) { | |
323 | tmp = 4; | |
324 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, | |
325 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
326 | } | |
327 | ||
328 | tmp = 1; | |
329 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, | |
330 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
331 | } | |
332 | } | |
333 | ||
4a933c85 RM |
334 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ |
335 | static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) | |
336 | { | |
337 | u32 tmslow; | |
338 | ||
339 | if (dev->phy.type != B43_PHYTYPE_N) | |
340 | return; | |
341 | ||
342 | tmslow = ssb_read32(dev->dev, SSB_TMSLOW); | |
343 | if (force) | |
344 | tmslow |= SSB_TMSLOW_FGC; | |
345 | else | |
346 | tmslow &= ~SSB_TMSLOW_FGC; | |
347 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | |
348 | } | |
349 | ||
350 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ | |
95b66bad MB |
351 | static void b43_nphy_reset_cca(struct b43_wldev *dev) |
352 | { | |
353 | u16 bbcfg; | |
354 | ||
4a933c85 | 355 | b43_nphy_bmac_clock_fgc(dev, 1); |
95b66bad | 356 | bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); |
4a933c85 RM |
357 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); |
358 | udelay(1); | |
359 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); | |
360 | b43_nphy_bmac_clock_fgc(dev, 0); | |
67c0d6e2 | 361 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
95b66bad MB |
362 | } |
363 | ||
ad9716e8 RM |
364 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ |
365 | static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) | |
366 | { | |
367 | u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); | |
368 | ||
369 | mimocfg |= B43_NPHY_MIMOCFG_AUTO; | |
370 | if (preamble == 1) | |
371 | mimocfg |= B43_NPHY_MIMOCFG_GFMIX; | |
372 | else | |
373 | mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; | |
374 | ||
375 | b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); | |
376 | } | |
377 | ||
4f4ab6cd RM |
378 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ |
379 | static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) | |
380 | { | |
381 | struct b43_phy_n *nphy = dev->phy.n; | |
382 | ||
383 | bool override = false; | |
384 | u16 chain = 0x33; | |
385 | ||
386 | if (nphy->txrx_chain == 0) { | |
387 | chain = 0x11; | |
388 | override = true; | |
389 | } else if (nphy->txrx_chain == 1) { | |
390 | chain = 0x22; | |
391 | override = true; | |
392 | } | |
393 | ||
394 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
395 | ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), | |
396 | chain); | |
397 | ||
398 | if (override) | |
399 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
400 | B43_NPHY_RFSEQMODE_CAOVER); | |
401 | else | |
402 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, | |
403 | ~B43_NPHY_RFSEQMODE_CAOVER); | |
404 | } | |
405 | ||
2faa6b83 RM |
406 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ |
407 | static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, | |
408 | u16 samps, u8 time, bool wait) | |
409 | { | |
410 | int i; | |
411 | u16 tmp; | |
412 | ||
413 | b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); | |
414 | b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); | |
415 | if (wait) | |
416 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); | |
417 | else | |
418 | b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); | |
419 | ||
420 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); | |
421 | ||
422 | for (i = 1000; i; i--) { | |
423 | tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); | |
424 | if (!(tmp & B43_NPHY_IQEST_CMD_START)) { | |
425 | est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | | |
426 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); | |
427 | est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | | |
428 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); | |
429 | est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | | |
430 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); | |
431 | ||
432 | est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | | |
433 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); | |
434 | est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | | |
435 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); | |
436 | est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | | |
437 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); | |
438 | return; | |
439 | } | |
440 | udelay(10); | |
441 | } | |
442 | memset(est, 0, sizeof(*est)); | |
443 | } | |
444 | ||
a67162ab RM |
445 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ |
446 | static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, | |
447 | struct b43_phy_n_iq_comp *pcomp) | |
448 | { | |
449 | if (write) { | |
450 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); | |
451 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); | |
452 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); | |
453 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); | |
454 | } else { | |
455 | pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); | |
456 | pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); | |
457 | pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); | |
458 | pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); | |
459 | } | |
460 | } | |
461 | ||
026816fc RM |
462 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ |
463 | static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) | |
464 | { | |
465 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
466 | ||
467 | b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); | |
468 | if (core == 0) { | |
469 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); | |
470 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
471 | } else { | |
472 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
473 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
474 | } | |
475 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); | |
476 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); | |
477 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); | |
478 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); | |
479 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); | |
480 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); | |
481 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
482 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
483 | } | |
484 | ||
485 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ | |
486 | static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) | |
487 | { | |
488 | u8 rxval, txval; | |
489 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
490 | ||
491 | regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
492 | if (core == 0) { | |
493 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
494 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
495 | } else { | |
496 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
497 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
498 | } | |
499 | regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
500 | regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
501 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); | |
502 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); | |
503 | regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); | |
504 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); | |
505 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
506 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
507 | ||
508 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
509 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
510 | ||
511 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
512 | ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
513 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
514 | ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); | |
515 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, | |
516 | (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); | |
517 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, | |
518 | (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); | |
519 | ||
520 | if (core == 0) { | |
521 | b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); | |
522 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); | |
523 | } else { | |
524 | b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); | |
525 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); | |
526 | } | |
527 | ||
67cbc3ed RM |
528 | b43_nphy_rf_control_intc_override(dev, 2, 0, 3); |
529 | b43_nphy_rf_control_override(dev, 8, 0, 3, false); | |
67c0d6e2 | 530 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
026816fc RM |
531 | |
532 | if (core == 0) { | |
533 | rxval = 1; | |
534 | txval = 8; | |
535 | } else { | |
536 | rxval = 4; | |
537 | txval = 2; | |
538 | } | |
67cbc3ed RM |
539 | b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); |
540 | b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); | |
026816fc RM |
541 | } |
542 | ||
34a56f2c RM |
543 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ |
544 | static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) | |
545 | { | |
546 | int i; | |
547 | s32 iq; | |
548 | u32 ii; | |
549 | u32 qq; | |
550 | int iq_nbits, qq_nbits; | |
551 | int arsh, brsh; | |
552 | u16 tmp, a, b; | |
553 | ||
554 | struct nphy_iq_est est; | |
555 | struct b43_phy_n_iq_comp old; | |
556 | struct b43_phy_n_iq_comp new = { }; | |
557 | bool error = false; | |
558 | ||
559 | if (mask == 0) | |
560 | return; | |
561 | ||
562 | b43_nphy_rx_iq_coeffs(dev, false, &old); | |
563 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
564 | b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); | |
565 | new = old; | |
566 | ||
567 | for (i = 0; i < 2; i++) { | |
568 | if (i == 0 && (mask & 1)) { | |
569 | iq = est.iq0_prod; | |
570 | ii = est.i0_pwr; | |
571 | qq = est.q0_pwr; | |
572 | } else if (i == 1 && (mask & 2)) { | |
573 | iq = est.iq1_prod; | |
574 | ii = est.i1_pwr; | |
575 | qq = est.q1_pwr; | |
576 | } else { | |
577 | B43_WARN_ON(1); | |
578 | continue; | |
579 | } | |
580 | ||
581 | if (ii + qq < 2) { | |
582 | error = true; | |
583 | break; | |
584 | } | |
585 | ||
586 | iq_nbits = fls(abs(iq)); | |
587 | qq_nbits = fls(qq); | |
588 | ||
589 | arsh = iq_nbits - 20; | |
590 | if (arsh >= 0) { | |
591 | a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); | |
592 | tmp = ii >> arsh; | |
593 | } else { | |
594 | a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); | |
595 | tmp = ii << -arsh; | |
596 | } | |
597 | if (tmp == 0) { | |
598 | error = true; | |
599 | break; | |
600 | } | |
601 | a /= tmp; | |
602 | ||
603 | brsh = qq_nbits - 11; | |
604 | if (brsh >= 0) { | |
605 | b = (qq << (31 - qq_nbits)); | |
606 | tmp = ii >> brsh; | |
607 | } else { | |
608 | b = (qq << (31 - qq_nbits)); | |
609 | tmp = ii << -brsh; | |
610 | } | |
611 | if (tmp == 0) { | |
612 | error = true; | |
613 | break; | |
614 | } | |
615 | b = int_sqrt(b / tmp - a * a) - (1 << 10); | |
616 | ||
617 | if (i == 0 && (mask & 0x1)) { | |
618 | if (dev->phy.rev >= 3) { | |
619 | new.a0 = a & 0x3FF; | |
620 | new.b0 = b & 0x3FF; | |
621 | } else { | |
622 | new.a0 = b & 0x3FF; | |
623 | new.b0 = a & 0x3FF; | |
624 | } | |
625 | } else if (i == 1 && (mask & 0x2)) { | |
626 | if (dev->phy.rev >= 3) { | |
627 | new.a1 = a & 0x3FF; | |
628 | new.b1 = b & 0x3FF; | |
629 | } else { | |
630 | new.a1 = b & 0x3FF; | |
631 | new.b1 = a & 0x3FF; | |
632 | } | |
633 | } | |
634 | } | |
635 | ||
636 | if (error) | |
637 | new = old; | |
638 | ||
639 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
640 | } | |
641 | ||
09146400 RM |
642 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ |
643 | static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) | |
644 | { | |
645 | u16 array[4]; | |
646 | int i; | |
647 | ||
648 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); | |
649 | for (i = 0; i < 4; i++) | |
650 | array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); | |
651 | ||
652 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); | |
653 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); | |
654 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); | |
655 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); | |
656 | } | |
657 | ||
bbec398c RM |
658 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ |
659 | static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
660 | { | |
661 | b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); | |
662 | b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); | |
663 | } | |
664 | ||
665 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ | |
666 | static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
667 | { | |
668 | clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); | |
669 | clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); | |
670 | } | |
671 | ||
8987a9e9 RM |
672 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ |
673 | static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) | |
674 | { | |
675 | if (dev->phy.rev >= 3) { | |
676 | if (!init) | |
677 | return; | |
678 | if (0 /* FIXME */) { | |
679 | b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); | |
680 | b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); | |
681 | b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); | |
682 | b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); | |
683 | } | |
684 | } else { | |
685 | b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); | |
686 | b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); | |
687 | ||
688 | ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00, | |
689 | 0xFC00); | |
690 | b43_write32(dev, B43_MMIO_MACCTL, | |
691 | b43_read32(dev, B43_MMIO_MACCTL) & | |
692 | ~B43_MACCTL_GPOUTSMSK); | |
693 | b43_write16(dev, B43_MMIO_GPIO_MASK, | |
694 | b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00); | |
695 | b43_write16(dev, B43_MMIO_GPIO_CONTROL, | |
696 | b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00); | |
697 | ||
698 | if (init) { | |
699 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | |
700 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | |
701 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | |
702 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | |
703 | } | |
704 | } | |
705 | } | |
706 | ||
bbec398c RM |
707 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ |
708 | static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) | |
709 | { | |
710 | u16 tmp; | |
711 | ||
712 | if (dev->dev->id.revision == 16) | |
713 | b43_mac_suspend(dev); | |
714 | ||
715 | tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); | |
716 | tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | | |
717 | B43_NPHY_CLASSCTL_WAITEDEN); | |
718 | tmp &= ~mask; | |
719 | tmp |= (val & mask); | |
720 | b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); | |
721 | ||
722 | if (dev->dev->id.revision == 16) | |
723 | b43_mac_enable(dev); | |
724 | ||
725 | return tmp; | |
726 | } | |
727 | ||
5c1a140a RM |
728 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ |
729 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) | |
730 | { | |
731 | struct b43_phy *phy = &dev->phy; | |
732 | struct b43_phy_n *nphy = phy->n; | |
733 | ||
734 | if (enable) { | |
735 | u16 clip[] = { 0xFFFF, 0xFFFF }; | |
736 | if (nphy->deaf_count++ == 0) { | |
737 | nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); | |
738 | b43_nphy_classifier(dev, 0x7, 0); | |
739 | b43_nphy_read_clip_detection(dev, nphy->clip_state); | |
740 | b43_nphy_write_clip_detection(dev, clip); | |
741 | } | |
742 | b43_nphy_reset_cca(dev); | |
743 | } else { | |
744 | if (--nphy->deaf_count == 0) { | |
745 | b43_nphy_classifier(dev, 0x7, nphy->classifier_state); | |
746 | b43_nphy_write_clip_detection(dev, nphy->clip_state); | |
747 | } | |
748 | } | |
749 | } | |
750 | ||
53ae8e8c RM |
751 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ |
752 | static void b43_nphy_stop_playback(struct b43_wldev *dev) | |
753 | { | |
754 | struct b43_phy_n *nphy = dev->phy.n; | |
755 | u16 tmp; | |
756 | ||
757 | if (nphy->hang_avoid) | |
758 | b43_nphy_stay_in_carrier_search(dev, 1); | |
759 | ||
760 | tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); | |
761 | if (tmp & 0x1) | |
762 | b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); | |
763 | else if (tmp & 0x2) | |
764 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000); | |
765 | ||
766 | b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); | |
767 | ||
768 | if (nphy->bb_mult_save & 0x80000000) { | |
769 | tmp = nphy->bb_mult_save & 0xFFFF; | |
d41a3552 | 770 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); |
53ae8e8c RM |
771 | nphy->bb_mult_save = 0; |
772 | } | |
773 | ||
774 | if (nphy->hang_avoid) | |
775 | b43_nphy_stay_in_carrier_search(dev, 0); | |
776 | } | |
777 | ||
9442e5b5 RM |
778 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ |
779 | static void b43_nphy_spur_workaround(struct b43_wldev *dev) | |
780 | { | |
781 | struct b43_phy_n *nphy = dev->phy.n; | |
782 | ||
902db91d | 783 | u8 channel = nphy->radio_chanspec.channel; |
9442e5b5 RM |
784 | int tone[2] = { 57, 58 }; |
785 | u32 noise[2] = { 0x3FF, 0x3FF }; | |
786 | ||
787 | B43_WARN_ON(dev->phy.rev < 3); | |
788 | ||
789 | if (nphy->hang_avoid) | |
790 | b43_nphy_stay_in_carrier_search(dev, 1); | |
791 | ||
9442e5b5 RM |
792 | if (nphy->gband_spurwar_en) { |
793 | /* TODO: N PHY Adjust Analog Pfbw (7) */ | |
794 | if (channel == 11 && dev->phy.is_40mhz) | |
795 | ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ | |
796 | else | |
797 | ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ | |
798 | /* TODO: N PHY Adjust CRS Min Power (0x1E) */ | |
799 | } | |
800 | ||
801 | if (nphy->aband_spurwar_en) { | |
802 | if (channel == 54) { | |
803 | tone[0] = 0x20; | |
804 | noise[0] = 0x25F; | |
805 | } else if (channel == 38 || channel == 102 || channel == 118) { | |
806 | if (0 /* FIXME */) { | |
807 | tone[0] = 0x20; | |
808 | noise[0] = 0x21F; | |
809 | } else { | |
810 | tone[0] = 0; | |
811 | noise[0] = 0; | |
812 | } | |
813 | } else if (channel == 134) { | |
814 | tone[0] = 0x20; | |
815 | noise[0] = 0x21F; | |
816 | } else if (channel == 151) { | |
817 | tone[0] = 0x10; | |
818 | noise[0] = 0x23F; | |
819 | } else if (channel == 153 || channel == 161) { | |
820 | tone[0] = 0x30; | |
821 | noise[0] = 0x23F; | |
822 | } else { | |
823 | tone[0] = 0; | |
824 | noise[0] = 0; | |
825 | } | |
826 | ||
827 | if (!tone[0] && !noise[0]) | |
828 | ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ | |
829 | else | |
830 | ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ | |
831 | } | |
832 | ||
833 | if (nphy->hang_avoid) | |
834 | b43_nphy_stay_in_carrier_search(dev, 0); | |
835 | } | |
836 | ||
d24019ad RM |
837 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ |
838 | static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) | |
839 | { | |
840 | struct b43_phy_n *nphy = dev->phy.n; | |
841 | ||
842 | u8 i; | |
843 | s16 tmp; | |
844 | u16 data[4]; | |
845 | s16 gain[2]; | |
846 | u16 minmax[2]; | |
847 | u16 lna_gain[4] = { -2, 10, 19, 25 }; | |
848 | ||
849 | if (nphy->hang_avoid) | |
850 | b43_nphy_stay_in_carrier_search(dev, 1); | |
851 | ||
852 | if (nphy->gain_boost) { | |
853 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
854 | gain[0] = 6; | |
855 | gain[1] = 6; | |
856 | } else { | |
857 | tmp = 40370 - 315 * nphy->radio_chanspec.channel; | |
858 | gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); | |
859 | tmp = 23242 - 224 * nphy->radio_chanspec.channel; | |
860 | gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); | |
861 | } | |
862 | } else { | |
863 | gain[0] = 0; | |
864 | gain[1] = 0; | |
865 | } | |
866 | ||
867 | for (i = 0; i < 2; i++) { | |
868 | if (nphy->elna_gain_config) { | |
869 | data[0] = 19 + gain[i]; | |
870 | data[1] = 25 + gain[i]; | |
871 | data[2] = 25 + gain[i]; | |
872 | data[3] = 25 + gain[i]; | |
873 | } else { | |
874 | data[0] = lna_gain[0] + gain[i]; | |
875 | data[1] = lna_gain[1] + gain[i]; | |
876 | data[2] = lna_gain[2] + gain[i]; | |
877 | data[3] = lna_gain[3] + gain[i]; | |
878 | } | |
879 | b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data); | |
880 | ||
881 | minmax[i] = 23 + gain[i]; | |
882 | } | |
883 | ||
884 | b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, | |
885 | minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); | |
886 | b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, | |
887 | minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); | |
888 | ||
889 | if (nphy->hang_avoid) | |
890 | b43_nphy_stay_in_carrier_search(dev, 0); | |
891 | } | |
892 | ||
ef5127a4 RM |
893 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ |
894 | static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev) | |
895 | { | |
896 | struct b43_phy_n *nphy = dev->phy.n; | |
897 | u8 i, j; | |
898 | u8 code; | |
899 | ||
900 | /* TODO: for PHY >= 3 | |
901 | s8 *lna1_gain, *lna2_gain; | |
902 | u8 *gain_db, *gain_bits; | |
903 | u16 *rfseq_init; | |
904 | u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; | |
905 | u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; | |
906 | */ | |
907 | ||
908 | u8 rfseq_events[3] = { 6, 8, 7 }; | |
909 | u8 rfseq_delays[3] = { 10, 30, 1 }; | |
910 | ||
911 | if (dev->phy.rev >= 3) { | |
912 | /* TODO */ | |
913 | } else { | |
914 | /* Set Clip 2 detect */ | |
915 | b43_phy_set(dev, B43_NPHY_C1_CGAINI, | |
916 | B43_NPHY_C1_CGAINI_CL2DETECT); | |
917 | b43_phy_set(dev, B43_NPHY_C2_CGAINI, | |
918 | B43_NPHY_C2_CGAINI_CL2DETECT); | |
919 | ||
920 | /* Set narrowband clip threshold */ | |
921 | b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); | |
922 | b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); | |
923 | ||
924 | if (!dev->phy.is_40mhz) { | |
925 | /* Set dwell lengths */ | |
926 | b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); | |
927 | b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); | |
928 | b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); | |
929 | b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); | |
930 | } | |
931 | ||
932 | /* Set wideband clip 2 threshold */ | |
933 | b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, | |
934 | ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, | |
935 | 21); | |
936 | b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, | |
937 | ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, | |
938 | 21); | |
939 | ||
940 | if (!dev->phy.is_40mhz) { | |
941 | b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, | |
942 | ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); | |
943 | b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, | |
944 | ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); | |
945 | b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, | |
946 | ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); | |
947 | b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, | |
948 | ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); | |
949 | } | |
950 | ||
951 | b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); | |
952 | ||
953 | if (nphy->gain_boost) { | |
954 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && | |
955 | dev->phy.is_40mhz) | |
956 | code = 4; | |
957 | else | |
958 | code = 5; | |
959 | } else { | |
960 | code = dev->phy.is_40mhz ? 6 : 7; | |
961 | } | |
962 | ||
963 | /* Set HPVGA2 index */ | |
964 | b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, | |
965 | ~B43_NPHY_C1_INITGAIN_HPVGA2, | |
966 | code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); | |
967 | b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, | |
968 | ~B43_NPHY_C2_INITGAIN_HPVGA2, | |
969 | code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); | |
970 | ||
971 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
972 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
973 | (code << 8 | 0x7C)); | |
974 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
975 | (code << 8 | 0x7C)); | |
976 | ||
d24019ad | 977 | b43_nphy_adjust_lna_gain_table(dev); |
ef5127a4 RM |
978 | |
979 | if (nphy->elna_gain_config) { | |
980 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); | |
981 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
982 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
983 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
984 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
985 | ||
986 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); | |
987 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
988 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
989 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
990 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
991 | ||
992 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
993 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
994 | (code << 8 | 0x74)); | |
995 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
996 | (code << 8 | 0x74)); | |
997 | } | |
998 | ||
999 | if (dev->phy.rev == 2) { | |
1000 | for (i = 0; i < 4; i++) { | |
1001 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1002 | (0x0400 * i) + 0x0020); | |
1003 | for (j = 0; j < 21; j++) | |
1004 | b43_phy_write(dev, | |
1005 | B43_NPHY_TABLE_DATALO, 3 * j); | |
1006 | } | |
1007 | ||
9501fefe RM |
1008 | b43_nphy_set_rf_sequence(dev, 5, |
1009 | rfseq_events, rfseq_delays, 3); | |
ef5127a4 RM |
1010 | b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, |
1011 | (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV, | |
1012 | 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); | |
1013 | ||
1014 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
1015 | b43_phy_maskset(dev, B43_PHY_N(0xC5D), | |
1016 | 0xFF80, 4); | |
1017 | } | |
1018 | } | |
1019 | } | |
1020 | ||
28fd7daa RM |
1021 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ |
1022 | static void b43_nphy_workarounds(struct b43_wldev *dev) | |
1023 | { | |
1024 | struct ssb_bus *bus = dev->dev->bus; | |
1025 | struct b43_phy *phy = &dev->phy; | |
1026 | struct b43_phy_n *nphy = phy->n; | |
1027 | ||
1028 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; | |
1029 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | |
1030 | ||
1031 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; | |
1032 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; | |
1033 | ||
1034 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
1035 | b43_nphy_classifier(dev, 1, 0); | |
1036 | else | |
1037 | b43_nphy_classifier(dev, 1, 1); | |
1038 | ||
1039 | if (nphy->hang_avoid) | |
1040 | b43_nphy_stay_in_carrier_search(dev, 1); | |
1041 | ||
1042 | b43_phy_set(dev, B43_NPHY_IQFLIP, | |
1043 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | |
1044 | ||
1045 | if (dev->phy.rev >= 3) { | |
1046 | /* TODO */ | |
1047 | } else { | |
1048 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && | |
1049 | nphy->band5g_pwrgain) { | |
1050 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | |
1051 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | |
1052 | } else { | |
1053 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | |
1054 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | |
1055 | } | |
1056 | ||
1057 | /* TODO: convert to b43_ntab_write? */ | |
1058 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); | |
1059 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
1060 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); | |
1061 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
1062 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); | |
1063 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
1064 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); | |
1065 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
1066 | ||
1067 | if (dev->phy.rev < 2) { | |
1068 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); | |
1069 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
1070 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); | |
1071 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
1072 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); | |
1073 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
1074 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); | |
1075 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
1076 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); | |
1077 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
1078 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); | |
1079 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
1080 | } | |
1081 | ||
1082 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | |
1083 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | |
1084 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | |
1085 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | |
1086 | ||
1087 | if (bus->sprom.boardflags2_lo & 0x100 && | |
1088 | bus->boardinfo.type == 0x8B) { | |
1089 | delays1[0] = 0x1; | |
1090 | delays1[5] = 0x14; | |
1091 | } | |
9501fefe RM |
1092 | b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); |
1093 | b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); | |
28fd7daa | 1094 | |
ef5127a4 | 1095 | b43_nphy_gain_crtl_workarounds(dev); |
28fd7daa RM |
1096 | |
1097 | if (dev->phy.rev < 2) { | |
1098 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) | |
1099 | ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/ | |
1100 | } else if (dev->phy.rev == 2) { | |
1101 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); | |
1102 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); | |
1103 | } | |
1104 | ||
1105 | if (dev->phy.rev < 2) | |
1106 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | |
1107 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | |
1108 | ||
1109 | /* Set phase track alpha and beta */ | |
1110 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | |
1111 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | |
1112 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | |
1113 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | |
1114 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | |
1115 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | |
1116 | ||
1117 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | |
1118 | (u16)~B43_NPHY_PIL_DW_64QAM); | |
1119 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | |
1120 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | |
1121 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | |
1122 | ||
1123 | if (dev->phy.rev == 2) | |
1124 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | |
1125 | B43_NPHY_FINERX2_CGC_DECGC); | |
1126 | } | |
1127 | ||
1128 | if (nphy->hang_avoid) | |
1129 | b43_nphy_stay_in_carrier_search(dev, 0); | |
1130 | } | |
1131 | ||
5f6393ec RM |
1132 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ |
1133 | static int b43_nphy_load_samples(struct b43_wldev *dev, | |
1134 | struct b43_c32 *samples, u16 len) { | |
1135 | struct b43_phy_n *nphy = dev->phy.n; | |
1136 | u16 i; | |
1137 | u32 *data; | |
1138 | ||
1139 | data = kzalloc(len * sizeof(u32), GFP_KERNEL); | |
1140 | if (!data) { | |
1141 | b43err(dev->wl, "allocation for samples loading failed\n"); | |
1142 | return -ENOMEM; | |
1143 | } | |
1144 | if (nphy->hang_avoid) | |
1145 | b43_nphy_stay_in_carrier_search(dev, 1); | |
1146 | ||
1147 | for (i = 0; i < len; i++) { | |
1148 | data[i] = (samples[i].i & 0x3FF << 10); | |
1149 | data[i] |= samples[i].q & 0x3FF; | |
1150 | } | |
1151 | b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); | |
1152 | ||
1153 | kfree(data); | |
1154 | if (nphy->hang_avoid) | |
1155 | b43_nphy_stay_in_carrier_search(dev, 0); | |
1156 | return 0; | |
1157 | } | |
1158 | ||
59af099b RM |
1159 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ |
1160 | static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, | |
1161 | bool test) | |
1162 | { | |
1163 | int i; | |
f2982181 | 1164 | u16 bw, len, rot, angle; |
da860475 | 1165 | struct b43_c32 *samples; |
f2982181 | 1166 | |
59af099b RM |
1167 | |
1168 | bw = (dev->phy.is_40mhz) ? 40 : 20; | |
1169 | len = bw << 3; | |
1170 | ||
1171 | if (test) { | |
1172 | if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) | |
1173 | bw = 82; | |
1174 | else | |
1175 | bw = 80; | |
1176 | ||
1177 | if (dev->phy.is_40mhz) | |
1178 | bw <<= 1; | |
1179 | ||
1180 | len = bw << 1; | |
1181 | } | |
1182 | ||
da860475 | 1183 | samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL); |
40bd5203 RM |
1184 | if (!samples) { |
1185 | b43err(dev->wl, "allocation for samples generation failed\n"); | |
1186 | return 0; | |
1187 | } | |
59af099b RM |
1188 | rot = (((freq * 36) / bw) << 16) / 100; |
1189 | angle = 0; | |
1190 | ||
f2982181 RM |
1191 | for (i = 0; i < len; i++) { |
1192 | samples[i] = b43_cordic(angle); | |
1193 | angle += rot; | |
1194 | samples[i].q = CORDIC_CONVERT(samples[i].q * max); | |
1195 | samples[i].i = CORDIC_CONVERT(samples[i].i * max); | |
59af099b RM |
1196 | } |
1197 | ||
5f6393ec | 1198 | i = b43_nphy_load_samples(dev, samples, len); |
f2982181 | 1199 | kfree(samples); |
5f6393ec | 1200 | return (i < 0) ? 0 : len; |
59af099b RM |
1201 | } |
1202 | ||
10a79873 RM |
1203 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ |
1204 | static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, | |
1205 | u16 wait, bool iqmode, bool dac_test) | |
1206 | { | |
1207 | struct b43_phy_n *nphy = dev->phy.n; | |
1208 | int i; | |
1209 | u16 seq_mode; | |
1210 | u32 tmp; | |
1211 | ||
1212 | if (nphy->hang_avoid) | |
1213 | b43_nphy_stay_in_carrier_search(dev, true); | |
1214 | ||
1215 | if ((nphy->bb_mult_save & 0x80000000) == 0) { | |
1216 | tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); | |
1217 | nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; | |
1218 | } | |
1219 | ||
1220 | if (!dev->phy.is_40mhz) | |
1221 | tmp = 0x6464; | |
1222 | else | |
1223 | tmp = 0x4747; | |
1224 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); | |
1225 | ||
1226 | if (nphy->hang_avoid) | |
1227 | b43_nphy_stay_in_carrier_search(dev, false); | |
1228 | ||
1229 | b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); | |
1230 | ||
1231 | if (loops != 0xFFFF) | |
1232 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); | |
1233 | else | |
1234 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); | |
1235 | ||
1236 | b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); | |
1237 | ||
1238 | seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); | |
1239 | ||
1240 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); | |
1241 | if (iqmode) { | |
1242 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); | |
1243 | b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); | |
1244 | } else { | |
1245 | if (dac_test) | |
1246 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); | |
1247 | else | |
1248 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); | |
1249 | } | |
1250 | for (i = 0; i < 100; i++) { | |
1251 | if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { | |
1252 | i = 0; | |
1253 | break; | |
1254 | } | |
1255 | udelay(10); | |
1256 | } | |
1257 | if (i) | |
1258 | b43err(dev->wl, "run samples timeout\n"); | |
1259 | ||
1260 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); | |
1261 | } | |
1262 | ||
59af099b RM |
1263 | /* |
1264 | * Transmits a known value for LO calibration | |
1265 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone | |
1266 | */ | |
1267 | static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, | |
1268 | bool iqmode, bool dac_test) | |
1269 | { | |
1270 | u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); | |
1271 | if (samp == 0) | |
1272 | return -1; | |
1273 | b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); | |
1274 | return 0; | |
1275 | } | |
1276 | ||
6dcd9d91 RM |
1277 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ |
1278 | static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) | |
1279 | { | |
1280 | struct b43_phy_n *nphy = dev->phy.n; | |
1281 | int i, j; | |
1282 | u32 tmp; | |
1283 | u32 cur_real, cur_imag, real_part, imag_part; | |
1284 | ||
1285 | u16 buffer[7]; | |
1286 | ||
1287 | if (nphy->hang_avoid) | |
1288 | b43_nphy_stay_in_carrier_search(dev, true); | |
1289 | ||
9145834e | 1290 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); |
6dcd9d91 RM |
1291 | |
1292 | for (i = 0; i < 2; i++) { | |
1293 | tmp = ((buffer[i * 2] & 0x3FF) << 10) | | |
1294 | (buffer[i * 2 + 1] & 0x3FF); | |
1295 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1296 | (((i + 26) << 10) | 320)); | |
1297 | for (j = 0; j < 128; j++) { | |
1298 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1299 | ((tmp >> 16) & 0xFFFF)); | |
1300 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1301 | (tmp & 0xFFFF)); | |
1302 | } | |
1303 | } | |
1304 | ||
1305 | for (i = 0; i < 2; i++) { | |
1306 | tmp = buffer[5 + i]; | |
1307 | real_part = (tmp >> 8) & 0xFF; | |
1308 | imag_part = (tmp & 0xFF); | |
1309 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1310 | (((i + 26) << 10) | 448)); | |
1311 | ||
1312 | if (dev->phy.rev >= 3) { | |
1313 | cur_real = real_part; | |
1314 | cur_imag = imag_part; | |
1315 | tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); | |
1316 | } | |
1317 | ||
1318 | for (j = 0; j < 128; j++) { | |
1319 | if (dev->phy.rev < 3) { | |
1320 | cur_real = (real_part * loscale[j] + 128) >> 8; | |
1321 | cur_imag = (imag_part * loscale[j] + 128) >> 8; | |
1322 | tmp = ((cur_real & 0xFF) << 8) | | |
1323 | (cur_imag & 0xFF); | |
1324 | } | |
1325 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1326 | ((tmp >> 16) & 0xFFFF)); | |
1327 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1328 | (tmp & 0xFFFF)); | |
1329 | } | |
1330 | } | |
1331 | ||
1332 | if (dev->phy.rev >= 3) { | |
1333 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1334 | B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); | |
1335 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1336 | B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); | |
1337 | } | |
1338 | ||
1339 | if (nphy->hang_avoid) | |
1340 | b43_nphy_stay_in_carrier_search(dev, false); | |
1341 | } | |
1342 | ||
9501fefe RM |
1343 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ |
1344 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, | |
1345 | u8 *events, u8 *delays, u8 length) | |
1346 | { | |
1347 | struct b43_phy_n *nphy = dev->phy.n; | |
1348 | u8 i; | |
1349 | u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; | |
1350 | u16 offset1 = cmd << 4; | |
1351 | u16 offset2 = offset1 + 0x80; | |
1352 | ||
1353 | if (nphy->hang_avoid) | |
1354 | b43_nphy_stay_in_carrier_search(dev, true); | |
1355 | ||
1356 | b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); | |
1357 | b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); | |
1358 | ||
1359 | for (i = length; i < 16; i++) { | |
1360 | b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); | |
1361 | b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); | |
1362 | } | |
1363 | ||
1364 | if (nphy->hang_avoid) | |
1365 | b43_nphy_stay_in_carrier_search(dev, false); | |
1366 | } | |
1367 | ||
67c0d6e2 | 1368 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ |
95b66bad MB |
1369 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, |
1370 | enum b43_nphy_rf_sequence seq) | |
1371 | { | |
1372 | static const u16 trigger[] = { | |
1373 | [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, | |
1374 | [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, | |
1375 | [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, | |
1376 | [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, | |
1377 | [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, | |
1378 | [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, | |
1379 | }; | |
1380 | int i; | |
c57199bc | 1381 | u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); |
95b66bad MB |
1382 | |
1383 | B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); | |
1384 | ||
1385 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
1386 | B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); | |
1387 | b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); | |
1388 | for (i = 0; i < 200; i++) { | |
1389 | if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) | |
1390 | goto ok; | |
1391 | msleep(1); | |
1392 | } | |
1393 | b43err(dev->wl, "RF sequence status timeout\n"); | |
1394 | ok: | |
c57199bc | 1395 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); |
95b66bad MB |
1396 | } |
1397 | ||
75377b24 RM |
1398 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ |
1399 | static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, | |
1400 | u16 value, u8 core, bool off) | |
1401 | { | |
1402 | int i; | |
1403 | u8 index = fls(field); | |
1404 | u8 addr, en_addr, val_addr; | |
1405 | /* we expect only one bit set */ | |
3ed0fac3 | 1406 | B43_WARN_ON(field & (~(1 << (index - 1)))); |
75377b24 RM |
1407 | |
1408 | if (dev->phy.rev >= 3) { | |
1409 | const struct nphy_rf_control_override_rev3 *rf_ctrl; | |
1410 | for (i = 0; i < 2; i++) { | |
1411 | if (index == 0 || index == 16) { | |
1412 | b43err(dev->wl, | |
1413 | "Unsupported RF Ctrl Override call\n"); | |
1414 | return; | |
1415 | } | |
1416 | ||
1417 | rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; | |
1418 | en_addr = B43_PHY_N((i == 0) ? | |
1419 | rf_ctrl->en_addr0 : rf_ctrl->en_addr1); | |
1420 | val_addr = B43_PHY_N((i == 0) ? | |
1421 | rf_ctrl->val_addr0 : rf_ctrl->val_addr1); | |
1422 | ||
1423 | if (off) { | |
1424 | b43_phy_mask(dev, en_addr, ~(field)); | |
1425 | b43_phy_mask(dev, val_addr, | |
1426 | ~(rf_ctrl->val_mask)); | |
1427 | } else { | |
1428 | if (core == 0 || ((1 << core) & i) != 0) { | |
1429 | b43_phy_set(dev, en_addr, field); | |
1430 | b43_phy_maskset(dev, val_addr, | |
1431 | ~(rf_ctrl->val_mask), | |
1432 | (value << rf_ctrl->val_shift)); | |
1433 | } | |
1434 | } | |
1435 | } | |
1436 | } else { | |
1437 | const struct nphy_rf_control_override_rev2 *rf_ctrl; | |
1438 | if (off) { | |
1439 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); | |
1440 | value = 0; | |
1441 | } else { | |
1442 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); | |
1443 | } | |
1444 | ||
1445 | for (i = 0; i < 2; i++) { | |
1446 | if (index <= 1 || index == 16) { | |
1447 | b43err(dev->wl, | |
1448 | "Unsupported RF Ctrl Override call\n"); | |
1449 | return; | |
1450 | } | |
1451 | ||
1452 | if (index == 2 || index == 10 || | |
1453 | (index >= 13 && index <= 15)) { | |
1454 | core = 1; | |
1455 | } | |
1456 | ||
1457 | rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; | |
1458 | addr = B43_PHY_N((i == 0) ? | |
1459 | rf_ctrl->addr0 : rf_ctrl->addr1); | |
1460 | ||
1461 | if ((core & (1 << i)) != 0) | |
1462 | b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), | |
1463 | (value << rf_ctrl->shift)); | |
1464 | ||
1465 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); | |
1466 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1467 | B43_NPHY_RFCTL_CMD_START); | |
1468 | udelay(1); | |
1469 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); | |
1470 | } | |
1471 | } | |
1472 | } | |
1473 | ||
67cbc3ed RM |
1474 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ |
1475 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | |
1476 | u16 value, u8 core) | |
1477 | { | |
1478 | u8 i, j; | |
1479 | u16 reg, tmp, val; | |
1480 | ||
1481 | B43_WARN_ON(dev->phy.rev < 3); | |
1482 | B43_WARN_ON(field > 4); | |
1483 | ||
1484 | for (i = 0; i < 2; i++) { | |
1485 | if ((core == 1 && i == 1) || (core == 2 && !i)) | |
1486 | continue; | |
1487 | ||
1488 | reg = (i == 0) ? | |
1489 | B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; | |
1490 | b43_phy_mask(dev, reg, 0xFBFF); | |
1491 | ||
1492 | switch (field) { | |
1493 | case 0: | |
1494 | b43_phy_write(dev, reg, 0); | |
1495 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); | |
1496 | break; | |
1497 | case 1: | |
1498 | if (!i) { | |
1499 | b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, | |
1500 | 0xFC3F, (value << 6)); | |
1501 | b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, | |
1502 | 0xFFFE, 1); | |
1503 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1504 | B43_NPHY_RFCTL_CMD_START); | |
1505 | for (j = 0; j < 100; j++) { | |
1506 | if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) { | |
1507 | j = 0; | |
1508 | break; | |
1509 | } | |
1510 | udelay(10); | |
1511 | } | |
1512 | if (j) | |
1513 | b43err(dev->wl, | |
1514 | "intc override timeout\n"); | |
1515 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, | |
1516 | 0xFFFE); | |
1517 | } else { | |
1518 | b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, | |
1519 | 0xFC3F, (value << 6)); | |
1520 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1521 | 0xFFFE, 1); | |
1522 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1523 | B43_NPHY_RFCTL_CMD_RXTX); | |
1524 | for (j = 0; j < 100; j++) { | |
1525 | if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) { | |
1526 | j = 0; | |
1527 | break; | |
1528 | } | |
1529 | udelay(10); | |
1530 | } | |
1531 | if (j) | |
1532 | b43err(dev->wl, | |
1533 | "intc override timeout\n"); | |
1534 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, | |
1535 | 0xFFFE); | |
1536 | } | |
1537 | break; | |
1538 | case 2: | |
1539 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1540 | tmp = 0x0020; | |
1541 | val = value << 5; | |
1542 | } else { | |
1543 | tmp = 0x0010; | |
1544 | val = value << 4; | |
1545 | } | |
1546 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1547 | break; | |
1548 | case 3: | |
1549 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1550 | tmp = 0x0001; | |
1551 | val = value; | |
1552 | } else { | |
1553 | tmp = 0x0004; | |
1554 | val = value << 2; | |
1555 | } | |
1556 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1557 | break; | |
1558 | case 4: | |
1559 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1560 | tmp = 0x0002; | |
1561 | val = value << 1; | |
1562 | } else { | |
1563 | tmp = 0x0008; | |
1564 | val = value << 3; | |
1565 | } | |
1566 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1567 | break; | |
1568 | } | |
1569 | } | |
1570 | } | |
1571 | ||
95b66bad MB |
1572 | static void b43_nphy_bphy_init(struct b43_wldev *dev) |
1573 | { | |
1574 | unsigned int i; | |
1575 | u16 val; | |
1576 | ||
1577 | val = 0x1E1F; | |
1578 | for (i = 0; i < 14; i++) { | |
1579 | b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); | |
1580 | val -= 0x202; | |
1581 | } | |
1582 | val = 0x3E3F; | |
1583 | for (i = 0; i < 16; i++) { | |
1584 | b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val); | |
1585 | val -= 0x202; | |
1586 | } | |
1587 | b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); | |
1588 | } | |
1589 | ||
3c95627d RM |
1590 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ |
1591 | static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |
1592 | s8 offset, u8 core, u8 rail, u8 type) | |
1593 | { | |
1594 | u16 tmp; | |
1595 | bool core1or5 = (core == 1) || (core == 5); | |
1596 | bool core2or5 = (core == 2) || (core == 5); | |
1597 | ||
1598 | offset = clamp_val(offset, -32, 31); | |
1599 | tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); | |
1600 | ||
1601 | if (core1or5 && (rail == 0) && (type == 2)) | |
1602 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); | |
1603 | if (core1or5 && (rail == 1) && (type == 2)) | |
1604 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); | |
1605 | if (core2or5 && (rail == 0) && (type == 2)) | |
1606 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); | |
1607 | if (core2or5 && (rail == 1) && (type == 2)) | |
1608 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); | |
1609 | if (core1or5 && (rail == 0) && (type == 0)) | |
1610 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); | |
1611 | if (core1or5 && (rail == 1) && (type == 0)) | |
1612 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); | |
1613 | if (core2or5 && (rail == 0) && (type == 0)) | |
1614 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); | |
1615 | if (core2or5 && (rail == 1) && (type == 0)) | |
1616 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); | |
1617 | if (core1or5 && (rail == 0) && (type == 1)) | |
1618 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); | |
1619 | if (core1or5 && (rail == 1) && (type == 1)) | |
1620 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); | |
1621 | if (core2or5 && (rail == 0) && (type == 1)) | |
1622 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); | |
1623 | if (core2or5 && (rail == 1) && (type == 1)) | |
1624 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); | |
1625 | if (core1or5 && (rail == 0) && (type == 6)) | |
1626 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); | |
1627 | if (core1or5 && (rail == 1) && (type == 6)) | |
1628 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); | |
1629 | if (core2or5 && (rail == 0) && (type == 6)) | |
1630 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); | |
1631 | if (core2or5 && (rail == 1) && (type == 6)) | |
1632 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); | |
1633 | if (core1or5 && (rail == 0) && (type == 3)) | |
1634 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); | |
1635 | if (core1or5 && (rail == 1) && (type == 3)) | |
1636 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); | |
1637 | if (core2or5 && (rail == 0) && (type == 3)) | |
1638 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); | |
1639 | if (core2or5 && (rail == 1) && (type == 3)) | |
1640 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); | |
1641 | if (core1or5 && (type == 4)) | |
1642 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); | |
1643 | if (core2or5 && (type == 4)) | |
1644 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); | |
1645 | if (core1or5 && (type == 5)) | |
1646 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); | |
1647 | if (core2or5 && (type == 5)) | |
1648 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); | |
1649 | } | |
1650 | ||
99b82c41 | 1651 | static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) |
3c95627d RM |
1652 | { |
1653 | u16 val; | |
1654 | ||
99b82c41 RM |
1655 | if (type < 3) |
1656 | val = 0; | |
1657 | else if (type == 6) | |
1658 | val = 1; | |
1659 | else if (type == 3) | |
1660 | val = 2; | |
1661 | else | |
1662 | val = 3; | |
1663 | ||
1664 | val = (val << 12) | (val << 14); | |
1665 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); | |
1666 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); | |
3c95627d | 1667 | |
99b82c41 RM |
1668 | if (type < 3) { |
1669 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, | |
1670 | (type + 1) << 4); | |
1671 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, | |
1672 | (type + 1) << 4); | |
1673 | } | |
3c95627d | 1674 | |
99b82c41 RM |
1675 | /* TODO use some definitions */ |
1676 | if (code == 0) { | |
1677 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0); | |
3c95627d | 1678 | if (type < 3) { |
99b82c41 RM |
1679 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0); |
1680 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0); | |
1681 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0); | |
1682 | udelay(20); | |
1683 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); | |
3c95627d | 1684 | } |
99b82c41 RM |
1685 | } else { |
1686 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, | |
1687 | 0x3000); | |
1688 | if (type < 3) { | |
1689 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1690 | 0xFEC7, 0x0180); | |
1691 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1692 | 0xEFDC, (code << 1 | 0x1021)); | |
1693 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1); | |
1694 | udelay(20); | |
1695 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); | |
3c95627d RM |
1696 | } |
1697 | } | |
1698 | } | |
1699 | ||
99b82c41 RM |
1700 | static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) |
1701 | { | |
6e3b15a9 RM |
1702 | struct b43_phy_n *nphy = dev->phy.n; |
1703 | u8 i; | |
1704 | u16 reg, val; | |
1705 | ||
1706 | if (code == 0) { | |
1707 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); | |
1708 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); | |
1709 | b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); | |
1710 | b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); | |
1711 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); | |
1712 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); | |
1713 | b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); | |
1714 | b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); | |
1715 | } else { | |
1716 | for (i = 0; i < 2; i++) { | |
1717 | if ((code == 1 && i == 1) || (code == 2 && !i)) | |
1718 | continue; | |
1719 | ||
1720 | reg = (i == 0) ? | |
1721 | B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; | |
1722 | b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); | |
1723 | ||
1724 | if (type < 3) { | |
1725 | reg = (i == 0) ? | |
1726 | B43_NPHY_AFECTL_C1 : | |
1727 | B43_NPHY_AFECTL_C2; | |
1728 | b43_phy_maskset(dev, reg, 0xFCFF, 0); | |
1729 | ||
1730 | reg = (i == 0) ? | |
1731 | B43_NPHY_RFCTL_LUT_TRSW_UP1 : | |
1732 | B43_NPHY_RFCTL_LUT_TRSW_UP2; | |
1733 | b43_phy_maskset(dev, reg, 0xFFC3, 0); | |
1734 | ||
1735 | if (type == 0) | |
1736 | val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; | |
1737 | else if (type == 1) | |
1738 | val = 16; | |
1739 | else | |
1740 | val = 32; | |
1741 | b43_phy_set(dev, reg, val); | |
1742 | ||
1743 | reg = (i == 0) ? | |
1744 | B43_NPHY_TXF_40CO_B1S0 : | |
1745 | B43_NPHY_TXF_40CO_B32S1; | |
1746 | b43_phy_set(dev, reg, 0x0020); | |
1747 | } else { | |
1748 | if (type == 6) | |
1749 | val = 0x0100; | |
1750 | else if (type == 3) | |
1751 | val = 0x0200; | |
1752 | else | |
1753 | val = 0x0300; | |
1754 | ||
1755 | reg = (i == 0) ? | |
1756 | B43_NPHY_AFECTL_C1 : | |
1757 | B43_NPHY_AFECTL_C2; | |
1758 | ||
1759 | b43_phy_maskset(dev, reg, 0xFCFF, val); | |
1760 | b43_phy_maskset(dev, reg, 0xF3FF, val << 2); | |
1761 | ||
1762 | if (type != 3 && type != 6) { | |
1763 | enum ieee80211_band band = | |
1764 | b43_current_band(dev->wl); | |
1765 | ||
1766 | if ((nphy->ipa2g_on && | |
1767 | band == IEEE80211_BAND_2GHZ) || | |
1768 | (nphy->ipa5g_on && | |
1769 | band == IEEE80211_BAND_5GHZ)) | |
1770 | val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; | |
1771 | else | |
1772 | val = 0x11; | |
1773 | reg = (i == 0) ? 0x2000 : 0x3000; | |
1774 | reg |= B2055_PADDRV; | |
1775 | b43_radio_write16(dev, reg, val); | |
1776 | ||
1777 | reg = (i == 0) ? | |
1778 | B43_NPHY_AFECTL_OVER1 : | |
1779 | B43_NPHY_AFECTL_OVER; | |
1780 | b43_phy_set(dev, reg, 0x0200); | |
1781 | } | |
1782 | } | |
1783 | } | |
1784 | } | |
99b82c41 RM |
1785 | } |
1786 | ||
1787 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ | |
1788 | static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | |
1789 | { | |
1790 | if (dev->phy.rev >= 3) | |
1791 | b43_nphy_rev3_rssi_select(dev, code, type); | |
1792 | else | |
1793 | b43_nphy_rev2_rssi_select(dev, code, type); | |
1794 | } | |
1795 | ||
dfb4aa5d RM |
1796 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ |
1797 | static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) | |
1798 | { | |
1799 | int i; | |
1800 | for (i = 0; i < 2; i++) { | |
1801 | if (type == 2) { | |
1802 | if (i == 0) { | |
1803 | b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, | |
1804 | 0xFC, buf[0]); | |
1805 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1806 | 0xFC, buf[1]); | |
1807 | } else { | |
1808 | b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, | |
1809 | 0xFC, buf[2 * i]); | |
1810 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1811 | 0xFC, buf[2 * i + 1]); | |
1812 | } | |
1813 | } else { | |
1814 | if (i == 0) | |
1815 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1816 | 0xF3, buf[0] << 2); | |
1817 | else | |
1818 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1819 | 0xF3, buf[2 * i + 1] << 2); | |
1820 | } | |
1821 | } | |
1822 | } | |
1823 | ||
1824 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ | |
1825 | static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, | |
1826 | u8 nsamp) | |
1827 | { | |
1828 | int i; | |
1829 | int out; | |
1830 | u16 save_regs_phy[9]; | |
1831 | u16 s[2]; | |
1832 | ||
1833 | if (dev->phy.rev >= 3) { | |
1834 | save_regs_phy[0] = b43_phy_read(dev, | |
1835 | B43_NPHY_RFCTL_LUT_TRSW_UP1); | |
1836 | save_regs_phy[1] = b43_phy_read(dev, | |
1837 | B43_NPHY_RFCTL_LUT_TRSW_UP2); | |
1838 | save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
1839 | save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
1840 | save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
1841 | save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
1842 | save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); | |
1843 | save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); | |
1844 | } | |
1845 | ||
1846 | b43_nphy_rssi_select(dev, 5, type); | |
1847 | ||
1848 | if (dev->phy.rev < 2) { | |
1849 | save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); | |
1850 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); | |
1851 | } | |
1852 | ||
1853 | for (i = 0; i < 4; i++) | |
1854 | buf[i] = 0; | |
1855 | ||
1856 | for (i = 0; i < nsamp; i++) { | |
1857 | if (dev->phy.rev < 2) { | |
1858 | s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); | |
1859 | s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); | |
1860 | } else { | |
1861 | s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); | |
1862 | s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); | |
1863 | } | |
1864 | ||
1865 | buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; | |
1866 | buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; | |
1867 | buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; | |
1868 | buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; | |
1869 | } | |
1870 | out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | | |
1871 | (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); | |
1872 | ||
1873 | if (dev->phy.rev < 2) | |
1874 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); | |
1875 | ||
1876 | if (dev->phy.rev >= 3) { | |
1877 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, | |
1878 | save_regs_phy[0]); | |
1879 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, | |
1880 | save_regs_phy[1]); | |
1881 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); | |
1882 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); | |
1883 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); | |
1884 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); | |
1885 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); | |
1886 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); | |
1887 | } | |
1888 | ||
1889 | return out; | |
1890 | } | |
1891 | ||
4cb99775 RM |
1892 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ |
1893 | static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) | |
95b66bad | 1894 | { |
90b9738d RM |
1895 | int i, j; |
1896 | u8 state[4]; | |
1897 | u8 code, val; | |
1898 | u16 class, override; | |
1899 | u8 regs_save_radio[2]; | |
1900 | u16 regs_save_phy[2]; | |
1901 | s8 offset[4]; | |
1902 | ||
1903 | u16 clip_state[2]; | |
1904 | u16 clip_off[2] = { 0xFFFF, 0xFFFF }; | |
1905 | s32 results_min[4] = { }; | |
1906 | u8 vcm_final[4] = { }; | |
1907 | s32 results[4][4] = { }; | |
1908 | s32 miniq[4][2] = { }; | |
1909 | ||
1910 | if (type == 2) { | |
1911 | code = 0; | |
1912 | val = 6; | |
1913 | } else if (type < 2) { | |
1914 | code = 25; | |
1915 | val = 4; | |
1916 | } else { | |
1917 | B43_WARN_ON(1); | |
1918 | return; | |
1919 | } | |
1920 | ||
1921 | class = b43_nphy_classifier(dev, 0, 0); | |
1922 | b43_nphy_classifier(dev, 7, 4); | |
1923 | b43_nphy_read_clip_detection(dev, clip_state); | |
1924 | b43_nphy_write_clip_detection(dev, clip_off); | |
1925 | ||
1926 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
1927 | override = 0x140; | |
1928 | else | |
1929 | override = 0x110; | |
1930 | ||
1931 | regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
1932 | regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); | |
1933 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); | |
1934 | b43_radio_write16(dev, B2055_C1_PD_RXTX, val); | |
1935 | ||
1936 | regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
1937 | regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); | |
1938 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); | |
1939 | b43_radio_write16(dev, B2055_C2_PD_RXTX, val); | |
1940 | ||
1941 | state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; | |
1942 | state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; | |
1943 | b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); | |
1944 | b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); | |
1945 | state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; | |
1946 | state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; | |
1947 | ||
1948 | b43_nphy_rssi_select(dev, 5, type); | |
1949 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); | |
1950 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); | |
1951 | ||
1952 | for (i = 0; i < 4; i++) { | |
1953 | u8 tmp[4]; | |
1954 | for (j = 0; j < 4; j++) | |
1955 | tmp[j] = i; | |
1956 | if (type != 1) | |
1957 | b43_nphy_set_rssi_2055_vcm(dev, type, tmp); | |
1958 | b43_nphy_poll_rssi(dev, type, results[i], 8); | |
1959 | if (type < 2) | |
1960 | for (j = 0; j < 2; j++) | |
1961 | miniq[i][j] = min(results[i][2 * j], | |
1962 | results[i][2 * j + 1]); | |
1963 | } | |
1964 | ||
1965 | for (i = 0; i < 4; i++) { | |
1966 | s32 mind = 40; | |
1967 | u8 minvcm = 0; | |
1968 | s32 minpoll = 249; | |
1969 | s32 curr; | |
1970 | for (j = 0; j < 4; j++) { | |
1971 | if (type == 2) | |
1972 | curr = abs(results[j][i]); | |
1973 | else | |
1974 | curr = abs(miniq[j][i / 2] - code * 8); | |
1975 | ||
1976 | if (curr < mind) { | |
1977 | mind = curr; | |
1978 | minvcm = j; | |
1979 | } | |
1980 | ||
1981 | if (results[j][i] < minpoll) | |
1982 | minpoll = results[j][i]; | |
1983 | } | |
1984 | results_min[i] = minpoll; | |
1985 | vcm_final[i] = minvcm; | |
1986 | } | |
1987 | ||
1988 | if (type != 1) | |
1989 | b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); | |
1990 | ||
1991 | for (i = 0; i < 4; i++) { | |
1992 | offset[i] = (code * 8) - results[vcm_final[i]][i]; | |
1993 | ||
1994 | if (offset[i] < 0) | |
1995 | offset[i] = -((abs(offset[i]) + 4) / 8); | |
1996 | else | |
1997 | offset[i] = (offset[i] + 4) / 8; | |
1998 | ||
1999 | if (results_min[i] == 248) | |
2000 | offset[i] = code - 32; | |
2001 | ||
2002 | if (i % 2 == 0) | |
2003 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0, | |
2004 | type); | |
2005 | else | |
2006 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1, | |
2007 | type); | |
2008 | } | |
2009 | ||
2010 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); | |
2011 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]); | |
2012 | ||
2013 | switch (state[2]) { | |
2014 | case 1: | |
2015 | b43_nphy_rssi_select(dev, 1, 2); | |
2016 | break; | |
2017 | case 4: | |
2018 | b43_nphy_rssi_select(dev, 1, 0); | |
2019 | break; | |
2020 | case 2: | |
2021 | b43_nphy_rssi_select(dev, 1, 1); | |
2022 | break; | |
2023 | default: | |
2024 | b43_nphy_rssi_select(dev, 1, 1); | |
2025 | break; | |
2026 | } | |
2027 | ||
2028 | switch (state[3]) { | |
2029 | case 1: | |
2030 | b43_nphy_rssi_select(dev, 2, 2); | |
2031 | break; | |
2032 | case 4: | |
2033 | b43_nphy_rssi_select(dev, 2, 0); | |
2034 | break; | |
2035 | default: | |
2036 | b43_nphy_rssi_select(dev, 2, 1); | |
2037 | break; | |
2038 | } | |
2039 | ||
2040 | b43_nphy_rssi_select(dev, 0, type); | |
2041 | ||
2042 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); | |
2043 | b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); | |
2044 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); | |
2045 | b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); | |
2046 | ||
2047 | b43_nphy_classifier(dev, 7, class); | |
2048 | b43_nphy_write_clip_detection(dev, clip_state); | |
4cb99775 RM |
2049 | } |
2050 | ||
2051 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ | |
2052 | static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) | |
2053 | { | |
2054 | /* TODO */ | |
2055 | } | |
2056 | ||
2057 | /* | |
2058 | * RSSI Calibration | |
2059 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal | |
2060 | */ | |
2061 | static void b43_nphy_rssi_cal(struct b43_wldev *dev) | |
2062 | { | |
2063 | if (dev->phy.rev >= 3) { | |
2064 | b43_nphy_rev3_rssi_cal(dev); | |
2065 | } else { | |
2066 | b43_nphy_rev2_rssi_cal(dev, 2); | |
2067 | b43_nphy_rev2_rssi_cal(dev, 0); | |
2068 | b43_nphy_rev2_rssi_cal(dev, 1); | |
2069 | } | |
95b66bad MB |
2070 | } |
2071 | ||
42e1547e RM |
2072 | /* |
2073 | * Restore RSSI Calibration | |
2074 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal | |
2075 | */ | |
2076 | static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) | |
2077 | { | |
2078 | struct b43_phy_n *nphy = dev->phy.n; | |
2079 | ||
2080 | u16 *rssical_radio_regs = NULL; | |
2081 | u16 *rssical_phy_regs = NULL; | |
2082 | ||
2083 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
902db91d | 2084 | if (b43_empty_chanspec(&nphy->rssical_chanspec_2G)) |
42e1547e RM |
2085 | return; |
2086 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; | |
2087 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; | |
2088 | } else { | |
902db91d | 2089 | if (b43_empty_chanspec(&nphy->rssical_chanspec_5G)) |
42e1547e RM |
2090 | return; |
2091 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; | |
2092 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; | |
2093 | } | |
2094 | ||
2095 | /* TODO use some definitions */ | |
2096 | b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); | |
2097 | b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); | |
2098 | ||
2099 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); | |
2100 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); | |
2101 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); | |
2102 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); | |
2103 | ||
2104 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); | |
2105 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); | |
2106 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); | |
2107 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); | |
2108 | ||
2109 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); | |
2110 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); | |
2111 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); | |
2112 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); | |
2113 | } | |
2114 | ||
2f258b74 RM |
2115 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ |
2116 | static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) | |
2117 | { | |
2118 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2119 | if (dev->phy.rev >= 6) { | |
2120 | /* TODO If the chip is 47162 | |
2121 | return txpwrctrl_tx_gain_ipa_rev5 */ | |
2122 | return txpwrctrl_tx_gain_ipa_rev6; | |
2123 | } else if (dev->phy.rev >= 5) { | |
2124 | return txpwrctrl_tx_gain_ipa_rev5; | |
2125 | } else { | |
2126 | return txpwrctrl_tx_gain_ipa; | |
2127 | } | |
2128 | } else { | |
2129 | return txpwrctrl_tx_gain_ipa_5g; | |
2130 | } | |
2131 | } | |
2132 | ||
c4a92003 RM |
2133 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ |
2134 | static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) | |
2135 | { | |
2136 | struct b43_phy_n *nphy = dev->phy.n; | |
2137 | u16 *save = nphy->tx_rx_cal_radio_saveregs; | |
52cb5e97 RM |
2138 | u16 tmp; |
2139 | u8 offset, i; | |
c4a92003 RM |
2140 | |
2141 | if (dev->phy.rev >= 3) { | |
52cb5e97 RM |
2142 | for (i = 0; i < 2; i++) { |
2143 | tmp = (i == 0) ? 0x2000 : 0x3000; | |
2144 | offset = i * 11; | |
2145 | ||
2146 | save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); | |
2147 | save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); | |
2148 | save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); | |
2149 | save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); | |
2150 | save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); | |
2151 | save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); | |
2152 | save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); | |
2153 | save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); | |
2154 | save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); | |
2155 | save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); | |
2156 | save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); | |
2157 | ||
2158 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
2159 | b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); | |
2160 | b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); | |
2161 | b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); | |
2162 | b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); | |
2163 | b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); | |
2164 | if (nphy->ipa5g_on) { | |
2165 | b43_radio_write16(dev, tmp | B2055_PADDRV, 4); | |
2166 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); | |
2167 | } else { | |
2168 | b43_radio_write16(dev, tmp | B2055_PADDRV, 0); | |
2169 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); | |
2170 | } | |
2171 | b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); | |
2172 | } else { | |
2173 | b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); | |
2174 | b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); | |
2175 | b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); | |
2176 | b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); | |
2177 | b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); | |
2178 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); | |
2179 | if (nphy->ipa2g_on) { | |
2180 | b43_radio_write16(dev, tmp | B2055_PADDRV, 6); | |
2181 | b43_radio_write16(dev, tmp | B2055_XOCTL2, | |
2182 | (dev->phy.rev < 5) ? 0x11 : 0x01); | |
2183 | } else { | |
2184 | b43_radio_write16(dev, tmp | B2055_PADDRV, 0); | |
2185 | b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); | |
2186 | } | |
2187 | } | |
2188 | b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); | |
2189 | b43_radio_write16(dev, tmp | B2055_XOMISC, 0); | |
2190 | b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); | |
2191 | } | |
c4a92003 RM |
2192 | } else { |
2193 | save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); | |
2194 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); | |
2195 | ||
2196 | save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); | |
2197 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); | |
2198 | ||
2199 | save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); | |
2200 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); | |
2201 | ||
2202 | save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); | |
2203 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); | |
2204 | ||
2205 | save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); | |
2206 | save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); | |
2207 | ||
2208 | if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & | |
2209 | B43_NPHY_BANDCTL_5GHZ)) { | |
2210 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); | |
2211 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); | |
2212 | } else { | |
2213 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); | |
2214 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); | |
2215 | } | |
2216 | ||
2217 | if (dev->phy.rev < 2) { | |
2218 | b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); | |
2219 | b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); | |
2220 | } else { | |
2221 | b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); | |
2222 | b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); | |
2223 | } | |
2224 | } | |
2225 | } | |
2226 | ||
e9762492 RM |
2227 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ |
2228 | static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, | |
2229 | struct nphy_txgains target, | |
2230 | struct nphy_iqcal_params *params) | |
2231 | { | |
2232 | int i, j, indx; | |
2233 | u16 gain; | |
2234 | ||
2235 | if (dev->phy.rev >= 3) { | |
2236 | params->txgm = target.txgm[core]; | |
2237 | params->pga = target.pga[core]; | |
2238 | params->pad = target.pad[core]; | |
2239 | params->ipa = target.ipa[core]; | |
2240 | params->cal_gain = (params->txgm << 12) | (params->pga << 8) | | |
2241 | (params->pad << 4) | (params->ipa); | |
2242 | for (j = 0; j < 5; j++) | |
2243 | params->ncorr[j] = 0x79; | |
2244 | } else { | |
2245 | gain = (target.pad[core]) | (target.pga[core] << 4) | | |
2246 | (target.txgm[core] << 8); | |
2247 | ||
2248 | indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? | |
2249 | 1 : 0; | |
2250 | for (i = 0; i < 9; i++) | |
2251 | if (tbl_iqcal_gainparams[indx][i][0] == gain) | |
2252 | break; | |
2253 | i = min(i, 8); | |
2254 | ||
2255 | params->txgm = tbl_iqcal_gainparams[indx][i][1]; | |
2256 | params->pga = tbl_iqcal_gainparams[indx][i][2]; | |
2257 | params->pad = tbl_iqcal_gainparams[indx][i][3]; | |
2258 | params->cal_gain = (params->txgm << 7) | (params->pga << 4) | | |
2259 | (params->pad << 2); | |
2260 | for (j = 0; j < 4; j++) | |
2261 | params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; | |
2262 | } | |
2263 | } | |
2264 | ||
de7ed0c6 RM |
2265 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ |
2266 | static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) | |
2267 | { | |
2268 | struct b43_phy_n *nphy = dev->phy.n; | |
2269 | int i; | |
2270 | u16 scale, entry; | |
2271 | ||
2272 | u16 tmp = nphy->txcal_bbmult; | |
2273 | if (core == 0) | |
2274 | tmp >>= 8; | |
2275 | tmp &= 0xff; | |
2276 | ||
2277 | for (i = 0; i < 18; i++) { | |
2278 | scale = (ladder_lo[i].percent * tmp) / 100; | |
2279 | entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; | |
d41a3552 | 2280 | b43_ntab_write(dev, B43_NTAB16(15, i), entry); |
de7ed0c6 RM |
2281 | |
2282 | scale = (ladder_iq[i].percent * tmp) / 100; | |
2283 | entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; | |
d41a3552 | 2284 | b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); |
de7ed0c6 RM |
2285 | } |
2286 | } | |
2287 | ||
45ca697e RM |
2288 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ |
2289 | static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
2290 | { | |
2291 | int i; | |
2292 | for (i = 0; i < 15; i++) | |
2293 | b43_phy_write(dev, B43_PHY_N(0x2C5 + i), | |
2294 | tbl_tx_filter_coef_rev4[2][i]); | |
2295 | } | |
2296 | ||
2297 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ | |
2298 | static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
2299 | { | |
2300 | int i, j; | |
2301 | /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ | |
2302 | u16 offset[] = { 0x186, 0x195, 0x2C5 }; | |
2303 | ||
2304 | for (i = 0; i < 3; i++) | |
2305 | for (j = 0; j < 15; j++) | |
2306 | b43_phy_write(dev, B43_PHY_N(offset[i] + j), | |
2307 | tbl_tx_filter_coef_rev4[i][j]); | |
2308 | ||
2309 | if (dev->phy.is_40mhz) { | |
2310 | for (j = 0; j < 15; j++) | |
2311 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2312 | tbl_tx_filter_coef_rev4[3][j]); | |
2313 | } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
2314 | for (j = 0; j < 15; j++) | |
2315 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2316 | tbl_tx_filter_coef_rev4[5][j]); | |
2317 | } | |
2318 | ||
2319 | if (dev->phy.channel == 14) | |
2320 | for (j = 0; j < 15; j++) | |
2321 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2322 | tbl_tx_filter_coef_rev4[6][j]); | |
2323 | } | |
2324 | ||
b0022e15 RM |
2325 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ |
2326 | static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) | |
2327 | { | |
2328 | struct b43_phy_n *nphy = dev->phy.n; | |
2329 | ||
2330 | u16 curr_gain[2]; | |
2331 | struct nphy_txgains target; | |
2332 | const u32 *table = NULL; | |
2333 | ||
2334 | if (nphy->txpwrctrl == 0) { | |
2335 | int i; | |
2336 | ||
2337 | if (nphy->hang_avoid) | |
2338 | b43_nphy_stay_in_carrier_search(dev, true); | |
9145834e | 2339 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); |
b0022e15 RM |
2340 | if (nphy->hang_avoid) |
2341 | b43_nphy_stay_in_carrier_search(dev, false); | |
2342 | ||
2343 | for (i = 0; i < 2; ++i) { | |
2344 | if (dev->phy.rev >= 3) { | |
2345 | target.ipa[i] = curr_gain[i] & 0x000F; | |
2346 | target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; | |
2347 | target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; | |
2348 | target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; | |
2349 | } else { | |
2350 | target.ipa[i] = curr_gain[i] & 0x0003; | |
2351 | target.pad[i] = (curr_gain[i] & 0x000C) >> 2; | |
2352 | target.pga[i] = (curr_gain[i] & 0x0070) >> 4; | |
2353 | target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; | |
2354 | } | |
2355 | } | |
2356 | } else { | |
2357 | int i; | |
2358 | u16 index[2]; | |
2359 | index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & | |
2360 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
2361 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
2362 | index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & | |
2363 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
2364 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
2365 | ||
2366 | for (i = 0; i < 2; ++i) { | |
2367 | if (dev->phy.rev >= 3) { | |
2368 | enum ieee80211_band band = | |
2369 | b43_current_band(dev->wl); | |
2370 | ||
2371 | if ((nphy->ipa2g_on && | |
2372 | band == IEEE80211_BAND_2GHZ) || | |
2373 | (nphy->ipa5g_on && | |
2374 | band == IEEE80211_BAND_5GHZ)) { | |
2375 | table = b43_nphy_get_ipa_gain_table(dev); | |
2376 | } else { | |
2377 | if (band == IEEE80211_BAND_5GHZ) { | |
2378 | if (dev->phy.rev == 3) | |
2379 | table = b43_ntab_tx_gain_rev3_5ghz; | |
2380 | else if (dev->phy.rev == 4) | |
2381 | table = b43_ntab_tx_gain_rev4_5ghz; | |
2382 | else | |
2383 | table = b43_ntab_tx_gain_rev5plus_5ghz; | |
2384 | } else { | |
2385 | table = b43_ntab_tx_gain_rev3plus_2ghz; | |
2386 | } | |
2387 | } | |
2388 | ||
2389 | target.ipa[i] = (table[index[i]] >> 16) & 0xF; | |
2390 | target.pad[i] = (table[index[i]] >> 20) & 0xF; | |
2391 | target.pga[i] = (table[index[i]] >> 24) & 0xF; | |
2392 | target.txgm[i] = (table[index[i]] >> 28) & 0xF; | |
2393 | } else { | |
2394 | table = b43_ntab_tx_gain_rev0_1_2; | |
2395 | ||
2396 | target.ipa[i] = (table[index[i]] >> 16) & 0x3; | |
2397 | target.pad[i] = (table[index[i]] >> 18) & 0x3; | |
2398 | target.pga[i] = (table[index[i]] >> 20) & 0x7; | |
2399 | target.txgm[i] = (table[index[i]] >> 23) & 0x7; | |
2400 | } | |
2401 | } | |
2402 | } | |
2403 | ||
2404 | return target; | |
2405 | } | |
2406 | ||
e53de674 RM |
2407 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ |
2408 | static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) | |
2409 | { | |
2410 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
2411 | ||
2412 | if (dev->phy.rev >= 3) { | |
2413 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); | |
2414 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
2415 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
2416 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); | |
2417 | b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); | |
d41a3552 RM |
2418 | b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); |
2419 | b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); | |
e53de674 RM |
2420 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); |
2421 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); | |
2422 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
2423 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
2424 | b43_nphy_reset_cca(dev); | |
2425 | } else { | |
2426 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); | |
2427 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); | |
2428 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
d41a3552 RM |
2429 | b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); |
2430 | b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); | |
e53de674 RM |
2431 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); |
2432 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); | |
2433 | } | |
2434 | } | |
2435 | ||
2436 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ | |
2437 | static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) | |
2438 | { | |
2439 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
2440 | u16 tmp; | |
2441 | ||
2442 | regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
2443 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
2444 | if (dev->phy.rev >= 3) { | |
2445 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); | |
2446 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); | |
2447 | ||
2448 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
2449 | regs[2] = tmp; | |
2450 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); | |
2451 | ||
2452 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2453 | regs[3] = tmp; | |
2454 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); | |
2455 | ||
2456 | regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); | |
de9a47f9 | 2457 | b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX); |
e53de674 | 2458 | |
c643a66e | 2459 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); |
e53de674 | 2460 | regs[5] = tmp; |
d41a3552 | 2461 | b43_ntab_write(dev, B43_NTAB16(8, 3), 0); |
c643a66e RM |
2462 | |
2463 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); | |
e53de674 | 2464 | regs[6] = tmp; |
d41a3552 | 2465 | b43_ntab_write(dev, B43_NTAB16(8, 19), 0); |
e53de674 RM |
2466 | regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
2467 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2468 | ||
67cbc3ed RM |
2469 | b43_nphy_rf_control_intc_override(dev, 2, 1, 3); |
2470 | b43_nphy_rf_control_intc_override(dev, 1, 2, 1); | |
2471 | b43_nphy_rf_control_intc_override(dev, 1, 8, 2); | |
e53de674 RM |
2472 | |
2473 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
2474 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
2475 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
2476 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
2477 | } else { | |
2478 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); | |
2479 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); | |
2480 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2481 | regs[2] = tmp; | |
2482 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); | |
c643a66e | 2483 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); |
e53de674 RM |
2484 | regs[3] = tmp; |
2485 | tmp |= 0x2000; | |
d41a3552 | 2486 | b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); |
c643a66e | 2487 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); |
e53de674 RM |
2488 | regs[4] = tmp; |
2489 | tmp |= 0x2000; | |
d41a3552 | 2490 | b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); |
e53de674 RM |
2491 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
2492 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2493 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
2494 | tmp = 0x0180; | |
2495 | else | |
2496 | tmp = 0x0120; | |
2497 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
2498 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
2499 | } | |
2500 | } | |
2501 | ||
bbc6dc12 RM |
2502 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ |
2503 | static void b43_nphy_save_cal(struct b43_wldev *dev) | |
2504 | { | |
2505 | struct b43_phy_n *nphy = dev->phy.n; | |
2506 | ||
2507 | struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; | |
2508 | u16 *txcal_radio_regs = NULL; | |
902db91d | 2509 | struct b43_chanspec *iqcal_chanspec; |
bbc6dc12 RM |
2510 | u16 *table = NULL; |
2511 | ||
2512 | if (nphy->hang_avoid) | |
2513 | b43_nphy_stay_in_carrier_search(dev, 1); | |
2514 | ||
2515 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2516 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; | |
2517 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; | |
2518 | iqcal_chanspec = &nphy->iqcal_chanspec_2G; | |
2519 | table = nphy->cal_cache.txcal_coeffs_2G; | |
2520 | } else { | |
2521 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; | |
2522 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; | |
2523 | iqcal_chanspec = &nphy->iqcal_chanspec_5G; | |
2524 | table = nphy->cal_cache.txcal_coeffs_5G; | |
2525 | } | |
2526 | ||
2527 | b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); | |
2528 | /* TODO use some definitions */ | |
2529 | if (dev->phy.rev >= 3) { | |
2530 | txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); | |
2531 | txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); | |
2532 | txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); | |
2533 | txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); | |
2534 | txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); | |
2535 | txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); | |
2536 | txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); | |
2537 | txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); | |
2538 | } else { | |
2539 | txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); | |
2540 | txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); | |
2541 | txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); | |
2542 | txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); | |
2543 | } | |
2544 | *iqcal_chanspec = nphy->radio_chanspec; | |
2545 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table); | |
2546 | ||
2547 | if (nphy->hang_avoid) | |
2548 | b43_nphy_stay_in_carrier_search(dev, 0); | |
2549 | } | |
2550 | ||
2f258b74 RM |
2551 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ |
2552 | static void b43_nphy_restore_cal(struct b43_wldev *dev) | |
2553 | { | |
2554 | struct b43_phy_n *nphy = dev->phy.n; | |
2555 | ||
2556 | u16 coef[4]; | |
2557 | u16 *loft = NULL; | |
2558 | u16 *table = NULL; | |
2559 | ||
2560 | int i; | |
2561 | u16 *txcal_radio_regs = NULL; | |
2562 | struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; | |
2563 | ||
2564 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
902db91d | 2565 | if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G)) |
2f258b74 RM |
2566 | return; |
2567 | table = nphy->cal_cache.txcal_coeffs_2G; | |
2568 | loft = &nphy->cal_cache.txcal_coeffs_2G[5]; | |
2569 | } else { | |
902db91d | 2570 | if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G)) |
2f258b74 RM |
2571 | return; |
2572 | table = nphy->cal_cache.txcal_coeffs_5G; | |
2573 | loft = &nphy->cal_cache.txcal_coeffs_5G[5]; | |
2574 | } | |
2575 | ||
2581b143 | 2576 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); |
2f258b74 RM |
2577 | |
2578 | for (i = 0; i < 4; i++) { | |
2579 | if (dev->phy.rev >= 3) | |
2580 | table[i] = coef[i]; | |
2581 | else | |
2582 | coef[i] = 0; | |
2583 | } | |
2584 | ||
2581b143 RM |
2585 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); |
2586 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); | |
2587 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); | |
2f258b74 RM |
2588 | |
2589 | if (dev->phy.rev < 2) | |
2590 | b43_nphy_tx_iq_workaround(dev); | |
2591 | ||
2592 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2593 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; | |
2594 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; | |
2595 | } else { | |
2596 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; | |
2597 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; | |
2598 | } | |
2599 | ||
2600 | /* TODO use some definitions */ | |
2601 | if (dev->phy.rev >= 3) { | |
2602 | b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); | |
2603 | b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); | |
2604 | b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); | |
2605 | b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); | |
2606 | b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); | |
2607 | b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); | |
2608 | b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); | |
2609 | b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); | |
2610 | } else { | |
2611 | b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); | |
2612 | b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); | |
2613 | b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); | |
2614 | b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); | |
2615 | } | |
2616 | b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); | |
2617 | } | |
2618 | ||
fb43b8e2 RM |
2619 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ |
2620 | static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, | |
2621 | struct nphy_txgains target, | |
2622 | bool full, bool mphase) | |
2623 | { | |
2624 | struct b43_phy_n *nphy = dev->phy.n; | |
2625 | int i; | |
2626 | int error = 0; | |
2627 | int freq; | |
2628 | bool avoid = false; | |
2629 | u8 length; | |
2630 | u16 tmp, core, type, count, max, numb, last, cmd; | |
2631 | const u16 *table; | |
2632 | bool phy6or5x; | |
2633 | ||
2634 | u16 buffer[11]; | |
2635 | u16 diq_start = 0; | |
2636 | u16 save[2]; | |
2637 | u16 gain[2]; | |
2638 | struct nphy_iqcal_params params[2]; | |
2639 | bool updated[2] = { }; | |
2640 | ||
2641 | b43_nphy_stay_in_carrier_search(dev, true); | |
2642 | ||
2643 | if (dev->phy.rev >= 4) { | |
2644 | avoid = nphy->hang_avoid; | |
2645 | nphy->hang_avoid = 0; | |
2646 | } | |
2647 | ||
9145834e | 2648 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2649 | |
2650 | for (i = 0; i < 2; i++) { | |
2651 | b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); | |
2652 | gain[i] = params[i].cal_gain; | |
2653 | } | |
2581b143 RM |
2654 | |
2655 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); | |
fb43b8e2 RM |
2656 | |
2657 | b43_nphy_tx_cal_radio_setup(dev); | |
e53de674 | 2658 | b43_nphy_tx_cal_phy_setup(dev); |
fb43b8e2 RM |
2659 | |
2660 | phy6or5x = dev->phy.rev >= 6 || | |
2661 | (dev->phy.rev == 5 && nphy->ipa2g_on && | |
2662 | b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); | |
2663 | if (phy6or5x) { | |
38bb9029 RM |
2664 | if (dev->phy.is_40mhz) { |
2665 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, | |
2666 | tbl_tx_iqlo_cal_loft_ladder_40); | |
2667 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, | |
2668 | tbl_tx_iqlo_cal_iqimb_ladder_40); | |
2669 | } else { | |
2670 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, | |
2671 | tbl_tx_iqlo_cal_loft_ladder_20); | |
2672 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, | |
2673 | tbl_tx_iqlo_cal_iqimb_ladder_20); | |
2674 | } | |
fb43b8e2 RM |
2675 | } |
2676 | ||
2677 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); | |
2678 | ||
aa4c7b2a | 2679 | if (!dev->phy.is_40mhz) |
fb43b8e2 RM |
2680 | freq = 2500; |
2681 | else | |
2682 | freq = 5000; | |
2683 | ||
2684 | if (nphy->mphase_cal_phase_id > 2) | |
10a79873 RM |
2685 | b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, |
2686 | 0xFFFF, 0, true, false); | |
fb43b8e2 | 2687 | else |
59af099b | 2688 | error = b43_nphy_tx_tone(dev, freq, 250, true, false); |
fb43b8e2 RM |
2689 | |
2690 | if (error == 0) { | |
2691 | if (nphy->mphase_cal_phase_id > 2) { | |
2692 | table = nphy->mphase_txcal_bestcoeffs; | |
2693 | length = 11; | |
2694 | if (dev->phy.rev < 3) | |
2695 | length -= 2; | |
2696 | } else { | |
2697 | if (!full && nphy->txiqlocal_coeffsvalid) { | |
2698 | table = nphy->txiqlocal_bestc; | |
2699 | length = 11; | |
2700 | if (dev->phy.rev < 3) | |
2701 | length -= 2; | |
2702 | } else { | |
2703 | full = true; | |
2704 | if (dev->phy.rev >= 3) { | |
2705 | table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; | |
2706 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; | |
2707 | } else { | |
2708 | table = tbl_tx_iqlo_cal_startcoefs; | |
2709 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; | |
2710 | } | |
2711 | } | |
2712 | } | |
2713 | ||
2581b143 | 2714 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); |
fb43b8e2 RM |
2715 | |
2716 | if (full) { | |
2717 | if (dev->phy.rev >= 3) | |
2718 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; | |
2719 | else | |
2720 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; | |
2721 | } else { | |
2722 | if (dev->phy.rev >= 3) | |
2723 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; | |
2724 | else | |
2725 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; | |
2726 | } | |
2727 | ||
2728 | if (mphase) { | |
2729 | count = nphy->mphase_txcal_cmdidx; | |
2730 | numb = min(max, | |
2731 | (u16)(count + nphy->mphase_txcal_numcmds)); | |
2732 | } else { | |
2733 | count = 0; | |
2734 | numb = max; | |
2735 | } | |
2736 | ||
2737 | for (; count < numb; count++) { | |
2738 | if (full) { | |
2739 | if (dev->phy.rev >= 3) | |
2740 | cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; | |
2741 | else | |
2742 | cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; | |
2743 | } else { | |
2744 | if (dev->phy.rev >= 3) | |
2745 | cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; | |
2746 | else | |
2747 | cmd = tbl_tx_iqlo_cal_cmds_recal[count]; | |
2748 | } | |
2749 | ||
2750 | core = (cmd & 0x3000) >> 12; | |
2751 | type = (cmd & 0x0F00) >> 8; | |
2752 | ||
2753 | if (phy6or5x && updated[core] == 0) { | |
2754 | b43_nphy_update_tx_cal_ladder(dev, core); | |
2755 | updated[core] = 1; | |
2756 | } | |
2757 | ||
2758 | tmp = (params[core].ncorr[type] << 8) | 0x66; | |
2759 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); | |
2760 | ||
2761 | if (type == 1 || type == 3 || type == 4) { | |
c643a66e RM |
2762 | buffer[0] = b43_ntab_read(dev, |
2763 | B43_NTAB16(15, 69 + core)); | |
fb43b8e2 RM |
2764 | diq_start = buffer[0]; |
2765 | buffer[0] = 0; | |
d41a3552 RM |
2766 | b43_ntab_write(dev, B43_NTAB16(15, 69 + core), |
2767 | 0); | |
fb43b8e2 RM |
2768 | } |
2769 | ||
2770 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); | |
2771 | for (i = 0; i < 2000; i++) { | |
2772 | tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); | |
2773 | if (tmp & 0xC000) | |
2774 | break; | |
2775 | udelay(10); | |
2776 | } | |
2777 | ||
9145834e RM |
2778 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2779 | buffer); | |
2581b143 RM |
2780 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, |
2781 | buffer); | |
fb43b8e2 RM |
2782 | |
2783 | if (type == 1 || type == 3 || type == 4) | |
2784 | buffer[0] = diq_start; | |
2785 | } | |
2786 | ||
2787 | if (mphase) | |
2788 | nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; | |
2789 | ||
2790 | last = (dev->phy.rev < 3) ? 6 : 7; | |
2791 | ||
2792 | if (!mphase || nphy->mphase_cal_phase_id == last) { | |
2581b143 | 2793 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); |
9145834e | 2794 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); |
fb43b8e2 RM |
2795 | if (dev->phy.rev < 3) { |
2796 | buffer[0] = 0; | |
2797 | buffer[1] = 0; | |
2798 | buffer[2] = 0; | |
2799 | buffer[3] = 0; | |
2800 | } | |
2581b143 RM |
2801 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, |
2802 | buffer); | |
2803 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2, | |
2804 | buffer); | |
2805 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, | |
2806 | buffer); | |
2807 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, | |
2808 | buffer); | |
fb43b8e2 RM |
2809 | length = 11; |
2810 | if (dev->phy.rev < 3) | |
2811 | length -= 2; | |
9145834e RM |
2812 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2813 | nphy->txiqlocal_bestc); | |
fb43b8e2 | 2814 | nphy->txiqlocal_coeffsvalid = true; |
902db91d | 2815 | nphy->txiqlocal_chanspec = nphy->radio_chanspec; |
fb43b8e2 RM |
2816 | } else { |
2817 | length = 11; | |
2818 | if (dev->phy.rev < 3) | |
2819 | length -= 2; | |
9145834e RM |
2820 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2821 | nphy->mphase_txcal_bestcoeffs); | |
fb43b8e2 RM |
2822 | } |
2823 | ||
53ae8e8c | 2824 | b43_nphy_stop_playback(dev); |
fb43b8e2 RM |
2825 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); |
2826 | } | |
2827 | ||
e53de674 | 2828 | b43_nphy_tx_cal_phy_cleanup(dev); |
2581b143 | 2829 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2830 | |
2831 | if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) | |
2832 | b43_nphy_tx_iq_workaround(dev); | |
2833 | ||
2834 | if (dev->phy.rev >= 4) | |
2835 | nphy->hang_avoid = avoid; | |
2836 | ||
2837 | b43_nphy_stay_in_carrier_search(dev, false); | |
2838 | ||
2839 | return error; | |
2840 | } | |
2841 | ||
984ff4ff RM |
2842 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ |
2843 | static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) | |
2844 | { | |
2845 | struct b43_phy_n *nphy = dev->phy.n; | |
2846 | u8 i; | |
2847 | u16 buffer[7]; | |
2848 | bool equal = true; | |
2849 | ||
902db91d RM |
2850 | if (!nphy->txiqlocal_coeffsvalid || |
2851 | b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec)) | |
984ff4ff RM |
2852 | return; |
2853 | ||
2854 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); | |
2855 | for (i = 0; i < 4; i++) { | |
2856 | if (buffer[i] != nphy->txiqlocal_bestc[i]) { | |
2857 | equal = false; | |
2858 | break; | |
2859 | } | |
2860 | } | |
2861 | ||
2862 | if (!equal) { | |
2863 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, | |
2864 | nphy->txiqlocal_bestc); | |
2865 | for (i = 0; i < 4; i++) | |
2866 | buffer[i] = 0; | |
2867 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, | |
2868 | buffer); | |
2869 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, | |
2870 | &nphy->txiqlocal_bestc[5]); | |
2871 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, | |
2872 | &nphy->txiqlocal_bestc[5]); | |
2873 | } | |
2874 | } | |
2875 | ||
15931e31 RM |
2876 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ |
2877 | static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, | |
2878 | struct nphy_txgains target, u8 type, bool debug) | |
2879 | { | |
2880 | struct b43_phy_n *nphy = dev->phy.n; | |
2881 | int i, j, index; | |
2882 | u8 rfctl[2]; | |
2883 | u8 afectl_core; | |
2884 | u16 tmp[6]; | |
2885 | u16 cur_hpf1, cur_hpf2, cur_lna; | |
2886 | u32 real, imag; | |
2887 | enum ieee80211_band band; | |
2888 | ||
2889 | u8 use; | |
2890 | u16 cur_hpf; | |
2891 | u16 lna[3] = { 3, 3, 1 }; | |
2892 | u16 hpf1[3] = { 7, 2, 0 }; | |
2893 | u16 hpf2[3] = { 2, 0, 0 }; | |
de9a47f9 | 2894 | u32 power[3] = { }; |
15931e31 RM |
2895 | u16 gain_save[2]; |
2896 | u16 cal_gain[2]; | |
2897 | struct nphy_iqcal_params cal_params[2]; | |
2898 | struct nphy_iq_est est; | |
2899 | int ret = 0; | |
2900 | bool playtone = true; | |
2901 | int desired = 13; | |
2902 | ||
2903 | b43_nphy_stay_in_carrier_search(dev, 1); | |
2904 | ||
2905 | if (dev->phy.rev < 2) | |
984ff4ff | 2906 | b43_nphy_reapply_tx_cal_coeffs(dev); |
9145834e | 2907 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
2908 | for (i = 0; i < 2; i++) { |
2909 | b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); | |
2910 | cal_gain[i] = cal_params[i].cal_gain; | |
2911 | } | |
2581b143 | 2912 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); |
15931e31 RM |
2913 | |
2914 | for (i = 0; i < 2; i++) { | |
2915 | if (i == 0) { | |
2916 | rfctl[0] = B43_NPHY_RFCTL_INTC1; | |
2917 | rfctl[1] = B43_NPHY_RFCTL_INTC2; | |
2918 | afectl_core = B43_NPHY_AFECTL_C1; | |
2919 | } else { | |
2920 | rfctl[0] = B43_NPHY_RFCTL_INTC2; | |
2921 | rfctl[1] = B43_NPHY_RFCTL_INTC1; | |
2922 | afectl_core = B43_NPHY_AFECTL_C2; | |
2923 | } | |
2924 | ||
2925 | tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
2926 | tmp[2] = b43_phy_read(dev, afectl_core); | |
2927 | tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2928 | tmp[4] = b43_phy_read(dev, rfctl[0]); | |
2929 | tmp[5] = b43_phy_read(dev, rfctl[1]); | |
2930 | ||
2931 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
2932 | (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
2933 | ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
2934 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
2935 | (1 - i)); | |
2936 | b43_phy_set(dev, afectl_core, 0x0006); | |
2937 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); | |
2938 | ||
2939 | band = b43_current_band(dev->wl); | |
2940 | ||
2941 | if (nphy->rxcalparams & 0xFF000000) { | |
2942 | if (band == IEEE80211_BAND_5GHZ) | |
2943 | b43_phy_write(dev, rfctl[0], 0x140); | |
2944 | else | |
2945 | b43_phy_write(dev, rfctl[0], 0x110); | |
2946 | } else { | |
2947 | if (band == IEEE80211_BAND_5GHZ) | |
2948 | b43_phy_write(dev, rfctl[0], 0x180); | |
2949 | else | |
2950 | b43_phy_write(dev, rfctl[0], 0x120); | |
2951 | } | |
2952 | ||
2953 | if (band == IEEE80211_BAND_5GHZ) | |
2954 | b43_phy_write(dev, rfctl[1], 0x148); | |
2955 | else | |
2956 | b43_phy_write(dev, rfctl[1], 0x114); | |
2957 | ||
2958 | if (nphy->rxcalparams & 0x10000) { | |
2959 | b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, | |
2960 | (i + 1)); | |
2961 | b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, | |
2962 | (2 - i)); | |
2963 | } | |
2964 | ||
2965 | for (j = 0; i < 4; j++) { | |
2966 | if (j < 3) { | |
2967 | cur_lna = lna[j]; | |
2968 | cur_hpf1 = hpf1[j]; | |
2969 | cur_hpf2 = hpf2[j]; | |
2970 | } else { | |
2971 | if (power[1] > 10000) { | |
2972 | use = 1; | |
2973 | cur_hpf = cur_hpf1; | |
2974 | index = 2; | |
2975 | } else { | |
2976 | if (power[0] > 10000) { | |
2977 | use = 1; | |
2978 | cur_hpf = cur_hpf1; | |
2979 | index = 1; | |
2980 | } else { | |
2981 | index = 0; | |
2982 | use = 2; | |
2983 | cur_hpf = cur_hpf2; | |
2984 | } | |
2985 | } | |
2986 | cur_lna = lna[index]; | |
2987 | cur_hpf1 = hpf1[index]; | |
2988 | cur_hpf2 = hpf2[index]; | |
2989 | cur_hpf += desired - hweight32(power[index]); | |
2990 | cur_hpf = clamp_val(cur_hpf, 0, 10); | |
2991 | if (use == 1) | |
2992 | cur_hpf1 = cur_hpf; | |
2993 | else | |
2994 | cur_hpf2 = cur_hpf; | |
2995 | } | |
2996 | ||
2997 | tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | | |
2998 | (cur_lna << 2)); | |
75377b24 RM |
2999 | b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, |
3000 | false); | |
de9a47f9 | 3001 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
53ae8e8c | 3002 | b43_nphy_stop_playback(dev); |
15931e31 RM |
3003 | |
3004 | if (playtone) { | |
59af099b RM |
3005 | ret = b43_nphy_tx_tone(dev, 4000, |
3006 | (nphy->rxcalparams & 0xFFFF), | |
3007 | false, false); | |
15931e31 RM |
3008 | playtone = false; |
3009 | } else { | |
10a79873 RM |
3010 | b43_nphy_run_samples(dev, 160, 0xFFFF, 0, |
3011 | false, false); | |
15931e31 RM |
3012 | } |
3013 | ||
3014 | if (ret == 0) { | |
3015 | if (j < 3) { | |
3016 | b43_nphy_rx_iq_est(dev, &est, 1024, 32, | |
3017 | false); | |
3018 | if (i == 0) { | |
3019 | real = est.i0_pwr; | |
3020 | imag = est.q0_pwr; | |
3021 | } else { | |
3022 | real = est.i1_pwr; | |
3023 | imag = est.q1_pwr; | |
3024 | } | |
3025 | power[i] = ((real + imag) / 1024) + 1; | |
3026 | } else { | |
3027 | b43_nphy_calc_rx_iq_comp(dev, 1 << i); | |
3028 | } | |
53ae8e8c | 3029 | b43_nphy_stop_playback(dev); |
15931e31 RM |
3030 | } |
3031 | ||
3032 | if (ret != 0) | |
3033 | break; | |
3034 | } | |
3035 | ||
3036 | b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); | |
3037 | b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); | |
3038 | b43_phy_write(dev, rfctl[1], tmp[5]); | |
3039 | b43_phy_write(dev, rfctl[0], tmp[4]); | |
3040 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); | |
3041 | b43_phy_write(dev, afectl_core, tmp[2]); | |
3042 | b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); | |
3043 | ||
3044 | if (ret != 0) | |
3045 | break; | |
3046 | } | |
3047 | ||
75377b24 | 3048 | b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); |
67c0d6e2 | 3049 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
2581b143 | 3050 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
3051 | |
3052 | b43_nphy_stay_in_carrier_search(dev, 0); | |
3053 | ||
3054 | return ret; | |
3055 | } | |
3056 | ||
3057 | static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, | |
3058 | struct nphy_txgains target, u8 type, bool debug) | |
3059 | { | |
3060 | return -1; | |
3061 | } | |
3062 | ||
3063 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ | |
3064 | static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, | |
3065 | struct nphy_txgains target, u8 type, bool debug) | |
3066 | { | |
3067 | if (dev->phy.rev >= 3) | |
3068 | return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); | |
3069 | else | |
3070 | return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); | |
3071 | } | |
3072 | ||
0988a7a1 RM |
3073 | /* |
3074 | * Init N-PHY | |
3075 | * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N | |
3076 | */ | |
424047e6 MB |
3077 | int b43_phy_initn(struct b43_wldev *dev) |
3078 | { | |
0988a7a1 | 3079 | struct ssb_bus *bus = dev->dev->bus; |
95b66bad | 3080 | struct b43_phy *phy = &dev->phy; |
0988a7a1 RM |
3081 | struct b43_phy_n *nphy = phy->n; |
3082 | u8 tx_pwr_state; | |
3083 | struct nphy_txgains target; | |
95b66bad | 3084 | u16 tmp; |
0988a7a1 RM |
3085 | enum ieee80211_band tmp2; |
3086 | bool do_rssi_cal; | |
3087 | ||
3088 | u16 clip[2]; | |
3089 | bool do_cal = false; | |
95b66bad | 3090 | |
0988a7a1 RM |
3091 | if ((dev->phy.rev >= 3) && |
3092 | (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && | |
3093 | (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { | |
3094 | chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); | |
3095 | } | |
3096 | nphy->deaf_count = 0; | |
95b66bad | 3097 | b43_nphy_tables_init(dev); |
0988a7a1 RM |
3098 | nphy->crsminpwr_adjusted = false; |
3099 | nphy->noisevars_adjusted = false; | |
95b66bad MB |
3100 | |
3101 | /* Clear all overrides */ | |
0988a7a1 RM |
3102 | if (dev->phy.rev >= 3) { |
3103 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); | |
3104 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
3105 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); | |
3106 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); | |
3107 | } else { | |
3108 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
3109 | } | |
95b66bad MB |
3110 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); |
3111 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); | |
0988a7a1 RM |
3112 | if (dev->phy.rev < 6) { |
3113 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); | |
3114 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); | |
3115 | } | |
95b66bad MB |
3116 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, |
3117 | ~(B43_NPHY_RFSEQMODE_CAOVER | | |
3118 | B43_NPHY_RFSEQMODE_TROVER)); | |
0988a7a1 RM |
3119 | if (dev->phy.rev >= 3) |
3120 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); | |
95b66bad MB |
3121 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); |
3122 | ||
0988a7a1 RM |
3123 | if (dev->phy.rev <= 2) { |
3124 | tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; | |
3125 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, | |
3126 | ~B43_NPHY_BPHY_CTL3_SCALE, | |
3127 | tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); | |
3128 | } | |
95b66bad MB |
3129 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); |
3130 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); | |
3131 | ||
0988a7a1 RM |
3132 | if (bus->sprom.boardflags2_lo & 0x100 || |
3133 | (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && | |
3134 | bus->boardinfo.type == 0x8B)) | |
3135 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); | |
3136 | else | |
3137 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); | |
3138 | b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); | |
3139 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); | |
3140 | b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); | |
424047e6 | 3141 | |
ad9716e8 | 3142 | b43_nphy_update_mimo_config(dev, nphy->preamble_override); |
4f4ab6cd | 3143 | b43_nphy_update_txrx_chain(dev); |
95b66bad MB |
3144 | |
3145 | if (phy->rev < 2) { | |
3146 | b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); | |
3147 | b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); | |
3148 | } | |
0988a7a1 RM |
3149 | |
3150 | tmp2 = b43_current_band(dev->wl); | |
3151 | if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || | |
3152 | (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { | |
3153 | b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); | |
3154 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, | |
3155 | nphy->papd_epsilon_offset[0] << 7); | |
3156 | b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); | |
3157 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, | |
3158 | nphy->papd_epsilon_offset[1] << 7); | |
45ca697e | 3159 | b43_nphy_int_pa_set_tx_dig_filters(dev); |
0988a7a1 | 3160 | } else if (phy->rev >= 5) { |
45ca697e | 3161 | b43_nphy_ext_pa_set_tx_dig_filters(dev); |
0988a7a1 RM |
3162 | } |
3163 | ||
95b66bad | 3164 | b43_nphy_workarounds(dev); |
95b66bad | 3165 | |
0988a7a1 | 3166 | /* Reset CCA, in init code it differs a little from standard way */ |
730dd705 | 3167 | b43_nphy_bmac_clock_fgc(dev, 1); |
0988a7a1 RM |
3168 | tmp = b43_phy_read(dev, B43_NPHY_BBCFG); |
3169 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); | |
3170 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); | |
730dd705 | 3171 | b43_nphy_bmac_clock_fgc(dev, 0); |
0988a7a1 RM |
3172 | |
3173 | /* TODO N PHY MAC PHY Clock Set with argument 1 */ | |
3174 | ||
e50cbcf6 | 3175 | b43_nphy_pa_override(dev, false); |
95b66bad MB |
3176 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
3177 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); | |
e50cbcf6 | 3178 | b43_nphy_pa_override(dev, true); |
0988a7a1 | 3179 | |
bbec398c RM |
3180 | b43_nphy_classifier(dev, 0, 0); |
3181 | b43_nphy_read_clip_detection(dev, clip); | |
0988a7a1 RM |
3182 | tx_pwr_state = nphy->txpwrctrl; |
3183 | /* TODO N PHY TX power control with argument 0 | |
3184 | (turning off power control) */ | |
3185 | /* TODO Fix the TX Power Settings */ | |
3186 | /* TODO N PHY TX Power Control Idle TSSI */ | |
3187 | /* TODO N PHY TX Power Control Setup */ | |
3188 | ||
3189 | if (phy->rev >= 3) { | |
3190 | /* TODO */ | |
3191 | } else { | |
2581b143 RM |
3192 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, |
3193 | b43_ntab_tx_gain_rev0_1_2); | |
3194 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, | |
3195 | b43_ntab_tx_gain_rev0_1_2); | |
0988a7a1 | 3196 | } |
95b66bad | 3197 | |
0988a7a1 RM |
3198 | if (nphy->phyrxchain != 3) |
3199 | ;/* TODO N PHY RX Core Set State with phyrxchain as argument */ | |
3200 | if (nphy->mphase_cal_phase_id > 0) | |
3201 | ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ | |
3202 | ||
3203 | do_rssi_cal = false; | |
3204 | if (phy->rev >= 3) { | |
3205 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
902db91d RM |
3206 | do_rssi_cal = |
3207 | b43_empty_chanspec(&nphy->rssical_chanspec_2G); | |
0988a7a1 | 3208 | else |
902db91d RM |
3209 | do_rssi_cal = |
3210 | b43_empty_chanspec(&nphy->rssical_chanspec_5G); | |
0988a7a1 RM |
3211 | |
3212 | if (do_rssi_cal) | |
4cb99775 | 3213 | b43_nphy_rssi_cal(dev); |
0988a7a1 | 3214 | else |
42e1547e | 3215 | b43_nphy_restore_rssi_cal(dev); |
0988a7a1 | 3216 | } else { |
4cb99775 | 3217 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
3218 | } |
3219 | ||
3220 | if (!((nphy->measure_hold & 0x6) != 0)) { | |
3221 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
902db91d | 3222 | do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G); |
0988a7a1 | 3223 | else |
902db91d | 3224 | do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G); |
0988a7a1 RM |
3225 | |
3226 | if (nphy->mute) | |
3227 | do_cal = false; | |
3228 | ||
3229 | if (do_cal) { | |
b0022e15 | 3230 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
3231 | |
3232 | if (nphy->antsel_type == 2) | |
8987a9e9 | 3233 | b43_nphy_superswitch_init(dev, true); |
0988a7a1 | 3234 | if (nphy->perical != 2) { |
90b9738d | 3235 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
3236 | if (phy->rev >= 3) { |
3237 | nphy->cal_orig_pwr_idx[0] = | |
3238 | nphy->txpwrindex[0].index_internal; | |
3239 | nphy->cal_orig_pwr_idx[1] = | |
3240 | nphy->txpwrindex[1].index_internal; | |
3241 | /* TODO N PHY Pre Calibrate TX Gain */ | |
b0022e15 | 3242 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
3243 | } |
3244 | } | |
3245 | } | |
3246 | } | |
3247 | ||
0988a7a1 RM |
3248 | if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) { |
3249 | if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) | |
bbc6dc12 | 3250 | b43_nphy_save_cal(dev); |
0988a7a1 | 3251 | else if (nphy->mphase_cal_phase_id == 0) |
15931e31 | 3252 | ;/* N PHY Periodic Calibration with argument 3 */ |
0988a7a1 RM |
3253 | } else { |
3254 | b43_nphy_restore_cal(dev); | |
3255 | } | |
0988a7a1 | 3256 | |
6dcd9d91 | 3257 | b43_nphy_tx_pwr_ctrl_coef_setup(dev); |
0988a7a1 RM |
3258 | /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */ |
3259 | b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); | |
3260 | b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); | |
3261 | if (phy->rev >= 3 && phy->rev <= 6) | |
3262 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); | |
fe3e46e8 | 3263 | b43_nphy_tx_lp_fbw(dev); |
9442e5b5 RM |
3264 | if (phy->rev >= 3) |
3265 | b43_nphy_spur_workaround(dev); | |
95b66bad MB |
3266 | |
3267 | b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); | |
53a6e234 | 3268 | return 0; |
424047e6 | 3269 | } |
ef1a628d | 3270 | |
1b69ec7b RM |
3271 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ |
3272 | static void b43_nphy_chanspec_setup(struct b43_wldev *dev, | |
b15b3039 | 3273 | const struct b43_phy_n_sfo_cfg *e, |
1b69ec7b RM |
3274 | struct b43_chanspec chanspec) |
3275 | { | |
3276 | struct b43_phy *phy = &dev->phy; | |
3277 | struct b43_phy_n *nphy = dev->phy.n; | |
3278 | ||
3279 | u16 tmp; | |
3280 | u32 tmp32; | |
3281 | ||
3282 | tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ; | |
3283 | if (chanspec.b_freq == 1 && tmp == 0) { | |
3284 | tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); | |
3285 | b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); | |
3286 | b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000); | |
3287 | b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); | |
3288 | b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); | |
3289 | } else if (chanspec.b_freq == 1) { | |
3290 | b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); | |
3291 | tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR); | |
3292 | b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4); | |
3293 | b43_phy_mask(dev, B43_PHY_B_BBCFG, (u16)~0xC000); | |
3294 | b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32); | |
3295 | } | |
3296 | ||
3297 | b43_chantab_phy_upload(dev, e); | |
3298 | ||
3299 | tmp = chanspec.channel; | |
3300 | if (chanspec.b_freq == 1) | |
3301 | tmp |= 0x0100; | |
3302 | if (chanspec.b_width == 3) | |
3303 | tmp |= 0x0200; | |
3304 | b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp); | |
3305 | ||
3306 | if (nphy->radio_chanspec.channel == 14) { | |
3307 | b43_nphy_classifier(dev, 2, 0); | |
3308 | b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); | |
3309 | } else { | |
3310 | b43_nphy_classifier(dev, 2, 2); | |
3311 | if (chanspec.b_freq == 2) | |
3312 | b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); | |
3313 | } | |
3314 | ||
3315 | if (nphy->txpwrctrl) | |
3316 | b43_nphy_tx_power_fix(dev); | |
3317 | ||
3318 | if (dev->phy.rev < 3) | |
3319 | b43_nphy_adjust_lna_gain_table(dev); | |
3320 | ||
3321 | b43_nphy_tx_lp_fbw(dev); | |
3322 | ||
3323 | if (dev->phy.rev >= 3 && 0) { | |
3324 | /* TODO */ | |
3325 | } | |
3326 | ||
3327 | b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); | |
3328 | ||
3329 | if (phy->rev >= 3) | |
3330 | b43_nphy_spur_workaround(dev); | |
3331 | } | |
3332 | ||
eff66c51 RM |
3333 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ |
3334 | static int b43_nphy_set_chanspec(struct b43_wldev *dev, | |
3335 | struct b43_chanspec chanspec) | |
3336 | { | |
3337 | struct b43_phy_n *nphy = dev->phy.n; | |
3338 | ||
3339 | const struct b43_nphy_channeltab_entry *tabent; | |
3340 | ||
3341 | u8 tmp; | |
3342 | u8 channel = chanspec.channel; | |
3343 | ||
3344 | if (dev->phy.rev >= 3) { | |
3345 | /* TODO */ | |
ffd2d9bd RM |
3346 | } else { |
3347 | tabent = b43_nphy_get_chantabent(dev, channel); | |
3348 | if (!tabent) | |
3349 | return -ESRCH; | |
eff66c51 RM |
3350 | } |
3351 | ||
3352 | nphy->radio_chanspec = chanspec; | |
3353 | ||
3354 | if (chanspec.b_width != nphy->b_width) | |
3355 | ; /* TODO: BMAC BW Set (chanspec.b_width) */ | |
3356 | ||
3357 | /* TODO: use defines */ | |
3358 | if (chanspec.b_width == 3) { | |
3359 | if (chanspec.sideband == 2) | |
3360 | b43_phy_set(dev, B43_NPHY_RXCTL, | |
3361 | B43_NPHY_RXCTL_BSELU20); | |
3362 | else | |
3363 | b43_phy_mask(dev, B43_NPHY_RXCTL, | |
3364 | ~B43_NPHY_RXCTL_BSELU20); | |
3365 | } | |
3366 | ||
3367 | if (dev->phy.rev >= 3) { | |
3368 | tmp = (chanspec.b_freq == 1) ? 4 : 0; | |
3369 | b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); | |
3370 | /* TODO: PHY Radio2056 Setup (chan_info_ptr[i]) */ | |
3371 | /* TODO: N PHY Chanspec Setup (chan_info_ptr[i]) */ | |
3372 | } else { | |
eff66c51 RM |
3373 | tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050; |
3374 | b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); | |
3375 | b43_radio_2055_setup(dev, tabent); | |
b15b3039 | 3376 | b43_nphy_chanspec_setup(dev, &(tabent->phy_regs), chanspec); |
eff66c51 RM |
3377 | } |
3378 | ||
3379 | return 0; | |
3380 | } | |
3381 | ||
3382 | /* Tune the hardware to a new channel */ | |
3383 | static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel) | |
3384 | { | |
3385 | struct b43_phy_n *nphy = dev->phy.n; | |
3386 | ||
3387 | struct b43_chanspec chanspec; | |
3388 | chanspec = nphy->radio_chanspec; | |
3389 | chanspec.channel = channel; | |
3390 | ||
3391 | return b43_nphy_set_chanspec(dev, chanspec); | |
3392 | } | |
3393 | ||
ef1a628d MB |
3394 | static int b43_nphy_op_allocate(struct b43_wldev *dev) |
3395 | { | |
3396 | struct b43_phy_n *nphy; | |
3397 | ||
3398 | nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); | |
3399 | if (!nphy) | |
3400 | return -ENOMEM; | |
3401 | dev->phy.n = nphy; | |
3402 | ||
ef1a628d MB |
3403 | return 0; |
3404 | } | |
3405 | ||
fb11137a | 3406 | static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) |
ef1a628d | 3407 | { |
fb11137a MB |
3408 | struct b43_phy *phy = &dev->phy; |
3409 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 3410 | |
fb11137a | 3411 | memset(nphy, 0, sizeof(*nphy)); |
ef1a628d | 3412 | |
fb11137a | 3413 | //TODO init struct b43_phy_n |
ef1a628d MB |
3414 | } |
3415 | ||
fb11137a | 3416 | static void b43_nphy_op_free(struct b43_wldev *dev) |
ef1a628d | 3417 | { |
fb11137a MB |
3418 | struct b43_phy *phy = &dev->phy; |
3419 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 3420 | |
ef1a628d | 3421 | kfree(nphy); |
fb11137a MB |
3422 | phy->n = NULL; |
3423 | } | |
3424 | ||
3425 | static int b43_nphy_op_init(struct b43_wldev *dev) | |
3426 | { | |
3427 | return b43_phy_initn(dev); | |
ef1a628d MB |
3428 | } |
3429 | ||
3430 | static inline void check_phyreg(struct b43_wldev *dev, u16 offset) | |
3431 | { | |
3432 | #if B43_DEBUG | |
3433 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { | |
3434 | /* OFDM registers are onnly available on A/G-PHYs */ | |
3435 | b43err(dev->wl, "Invalid OFDM PHY access at " | |
3436 | "0x%04X on N-PHY\n", offset); | |
3437 | dump_stack(); | |
3438 | } | |
3439 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { | |
3440 | /* Ext-G registers are only available on G-PHYs */ | |
3441 | b43err(dev->wl, "Invalid EXT-G PHY access at " | |
3442 | "0x%04X on N-PHY\n", offset); | |
3443 | dump_stack(); | |
3444 | } | |
3445 | #endif /* B43_DEBUG */ | |
3446 | } | |
3447 | ||
3448 | static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) | |
3449 | { | |
3450 | check_phyreg(dev, reg); | |
3451 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
3452 | return b43_read16(dev, B43_MMIO_PHY_DATA); | |
3453 | } | |
3454 | ||
3455 | static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) | |
3456 | { | |
3457 | check_phyreg(dev, reg); | |
3458 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
3459 | b43_write16(dev, B43_MMIO_PHY_DATA, value); | |
3460 | } | |
3461 | ||
3462 | static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) | |
3463 | { | |
3464 | /* Register 1 is a 32-bit register. */ | |
3465 | B43_WARN_ON(reg == 1); | |
3466 | /* N-PHY needs 0x100 for read access */ | |
3467 | reg |= 0x100; | |
3468 | ||
3469 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
3470 | return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); | |
3471 | } | |
3472 | ||
3473 | static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) | |
3474 | { | |
3475 | /* Register 1 is a 32-bit register. */ | |
3476 | B43_WARN_ON(reg == 1); | |
3477 | ||
3478 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
3479 | b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); | |
3480 | } | |
3481 | ||
c2b7aefd | 3482 | /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ |
ef1a628d | 3483 | static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, |
19d337df | 3484 | bool blocked) |
c2b7aefd | 3485 | { |
d817f4e1 RM |
3486 | struct b43_phy_n *nphy = dev->phy.n; |
3487 | ||
c2b7aefd RM |
3488 | if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) |
3489 | b43err(dev->wl, "MAC not suspended\n"); | |
3490 | ||
3491 | if (blocked) { | |
3492 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
3493 | ~B43_NPHY_RFCTL_CMD_CHIP0PU); | |
3494 | if (dev->phy.rev >= 3) { | |
3495 | b43_radio_mask(dev, 0x09, ~0x2); | |
3496 | ||
3497 | b43_radio_write(dev, 0x204D, 0); | |
3498 | b43_radio_write(dev, 0x2053, 0); | |
3499 | b43_radio_write(dev, 0x2058, 0); | |
3500 | b43_radio_write(dev, 0x205E, 0); | |
3501 | b43_radio_mask(dev, 0x2062, ~0xF0); | |
3502 | b43_radio_write(dev, 0x2064, 0); | |
3503 | ||
3504 | b43_radio_write(dev, 0x304D, 0); | |
3505 | b43_radio_write(dev, 0x3053, 0); | |
3506 | b43_radio_write(dev, 0x3058, 0); | |
3507 | b43_radio_write(dev, 0x305E, 0); | |
3508 | b43_radio_mask(dev, 0x3062, ~0xF0); | |
3509 | b43_radio_write(dev, 0x3064, 0); | |
3510 | } | |
3511 | } else { | |
3512 | if (dev->phy.rev >= 3) { | |
d817f4e1 RM |
3513 | b43_radio_init2056(dev); |
3514 | b43_nphy_set_chanspec(dev, nphy->radio_chanspec); | |
c2b7aefd RM |
3515 | } else { |
3516 | b43_radio_init2055(dev); | |
3517 | } | |
3518 | } | |
ef1a628d MB |
3519 | } |
3520 | ||
cb24f57f MB |
3521 | static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) |
3522 | { | |
3523 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, | |
3524 | on ? 0 : 0x7FFF); | |
3525 | } | |
3526 | ||
ef1a628d MB |
3527 | static int b43_nphy_op_switch_channel(struct b43_wldev *dev, |
3528 | unsigned int new_channel) | |
3529 | { | |
3530 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
3531 | if ((new_channel < 1) || (new_channel > 14)) | |
3532 | return -EINVAL; | |
3533 | } else { | |
3534 | if (new_channel > 200) | |
3535 | return -EINVAL; | |
3536 | } | |
3537 | ||
3538 | return nphy_channel_switch(dev, new_channel); | |
3539 | } | |
3540 | ||
3541 | static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) | |
3542 | { | |
3543 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
3544 | return 1; | |
3545 | return 36; | |
3546 | } | |
3547 | ||
ef1a628d MB |
3548 | const struct b43_phy_operations b43_phyops_n = { |
3549 | .allocate = b43_nphy_op_allocate, | |
fb11137a MB |
3550 | .free = b43_nphy_op_free, |
3551 | .prepare_structs = b43_nphy_op_prepare_structs, | |
ef1a628d | 3552 | .init = b43_nphy_op_init, |
ef1a628d MB |
3553 | .phy_read = b43_nphy_op_read, |
3554 | .phy_write = b43_nphy_op_write, | |
3555 | .radio_read = b43_nphy_op_radio_read, | |
3556 | .radio_write = b43_nphy_op_radio_write, | |
3557 | .software_rfkill = b43_nphy_op_software_rfkill, | |
cb24f57f | 3558 | .switch_analog = b43_nphy_op_switch_analog, |
ef1a628d MB |
3559 | .switch_channel = b43_nphy_op_switch_channel, |
3560 | .get_default_chan = b43_nphy_op_get_default_chan, | |
18c8adeb MB |
3561 | .recalc_txpower = b43_nphy_op_recalc_txpower, |
3562 | .adjust_txpower = b43_nphy_op_adjust_txpower, | |
ef1a628d | 3563 | }; |