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b43: N-PHY: implement PA overriding (RF control related)
[linux-block.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
53a6e234
MB		 58void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
59{//TODO
60}
61
18c8adeb 62static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 63{//TODO
64}
65
18c8adeb
MB		 66static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
67 bool ignore_tssi)
68{//TODO
69 return B43_TXPWR_RES_DONE;
70}
71
d1591314
MB		 72static void b43_chantab_radio_upload(struct b43_wldev *dev,
73 const struct b43_nphy_channeltab_entry *e)
74{
75 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
76 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
77 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
78 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
79 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
80 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
81 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
82 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
83 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
84 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
85 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
86 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
87 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
88 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
89 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
90 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
91 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
92 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
93 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
94 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
95 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
96 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
97}
98
99static void b43_chantab_phy_upload(struct b43_wldev *dev,
100 const struct b43_nphy_channeltab_entry *e)
101{
102 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
103 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
104 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
105 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
106 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
107 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
108}
109
110static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
111{
112 //TODO
113}
114
ef1a628d
MB		 115/* Tune the hardware to a new channel. */
116static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 117{
d1591314
MB		 118 const struct b43_nphy_channeltab_entry *tabent;
119
120 tabent = b43_nphy_get_chantabent(dev, channel);
121 if (!tabent)
122 return -ESRCH;
123
124 //FIXME enable/disable band select upper20 in RXCTL
125 if (0 /*FIXME 5Ghz*/)
126 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
127 else
128 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
129 b43_chantab_radio_upload(dev, tabent);
130 udelay(50);
131 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
132 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
133 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
134 udelay(300);
135 if (0 /*FIXME 5Ghz*/)
136 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
137 else
138 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
139 b43_chantab_phy_upload(dev, tabent);
140 b43_nphy_tx_power_fix(dev);
53a6e234 141
d1591314 142 return 0;
53a6e234
MB		 143}
144
145static void b43_radio_init2055_pre(struct b43_wldev *dev)
146{
147 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
148 ~B43_NPHY_RFCTL_CMD_PORFORCE);
149 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
150 B43_NPHY_RFCTL_CMD_CHIP0PU |
151 B43_NPHY_RFCTL_CMD_OEPORFORCE);
152 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
153 B43_NPHY_RFCTL_CMD_PORFORCE);
154}
155
156static void b43_radio_init2055_post(struct b43_wldev *dev)
157{
158 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
159 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
160 int i;
161 u16 val;
162
163 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
164 msleep(1);
738f0f43
GS		 165 if ((sprom->revision != 4) ||
166 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 167 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
168 (binfo->type != 0x46D) ||
169 (binfo->rev < 0x41)) {
170 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
171 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
172 msleep(1);
173 }
174 }
175 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
176 msleep(1);
177 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
178 msleep(1);
179 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
180 msleep(1);
181 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
182 msleep(1);
183 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
184 msleep(1);
185 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
186 msleep(1);
187 for (i = 0; i < 100; i++) {
188 val = b43_radio_read16(dev, B2055_CAL_COUT2);
189 if (val & 0x80)
190 break;
191 udelay(10);
192 }
193 msleep(1);
194 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
195 msleep(1);
ef1a628d 196 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 197 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
198 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
199 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
200 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
201}
202
203/* Initialize a Broadcom 2055 N-radio */
204static void b43_radio_init2055(struct b43_wldev *dev)
205{
206 b43_radio_init2055_pre(dev);
207 if (b43_status(dev) < B43_STAT_INITIALIZED)
208 b2055_upload_inittab(dev, 0, 1);
209 else
210 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
211 b43_radio_init2055_post(dev);
212}
213
214void b43_nphy_radio_turn_on(struct b43_wldev *dev)
215{
216 b43_radio_init2055(dev);
217}
218
219void b43_nphy_radio_turn_off(struct b43_wldev *dev)
220{
221 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
222 ~B43_NPHY_RFCTL_CMD_EN);
223}
224
95b66bad
MB		 225#define ntab_upload(dev, offset, data) do { \
226 unsigned int i; \
227 for (i = 0; i < (offset##_SIZE); i++) \
228 b43_ntab_write(dev, (offset) + i, (data)[i]); \
229 } while (0)
230
4772ae10
RM		 231/*
232 * Upload the N-PHY tables.
233 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
234 */
95b66bad
MB		 235static void b43_nphy_tables_init(struct b43_wldev *dev)
236{
4772ae10
RM		 237 if (dev->phy.rev < 3)
238 b43_nphy_rev0_1_2_tables_init(dev);
239 else
240 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 241}
242
243static void b43_nphy_workarounds(struct b43_wldev *dev)
244{
245 struct b43_phy *phy = &dev->phy;
246 unsigned int i;
247
248 b43_phy_set(dev, B43_NPHY_IQFLIP,
249 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 250 if (1 /* FIXME band is 2.4GHz */) {
251 b43_phy_set(dev, B43_NPHY_CLASSCTL,
252 B43_NPHY_CLASSCTL_CCKEN);
253 } else {
254 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
255 ~B43_NPHY_CLASSCTL_CCKEN);
256 }
257 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
258 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
259
260 /* Fixup some tables */
261 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
262 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
263 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
264 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
265 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
266 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
267 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
271
272 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
273 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
274 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
275 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
276
277 //TODO set RF sequence
278
279 /* Set narrowband clip threshold */
280 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
281 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
282
283 /* Set wideband clip 2 threshold */
284 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
285 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
286 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
287 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
288 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
289 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
290
291 /* Set Clip 2 detect */
292 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
293 B43_NPHY_C1_CGAINI_CL2DETECT);
294 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
295 B43_NPHY_C2_CGAINI_CL2DETECT);
296
297 if (0 /*FIXME*/) {
298 /* Set dwell lengths */
299 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
300 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
301 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
302 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
303
304 /* Set gain backoff */
305 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
306 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
307 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
308 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
309 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
310 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
311
312 /* Set HPVGA2 index */
313 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
314 ~B43_NPHY_C1_INITGAIN_HPVGA2,
315 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
316 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
317 ~B43_NPHY_C2_INITGAIN_HPVGA2,
318 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
319
320 //FIXME verify that the specs really mean to use autoinc here.
321 for (i = 0; i < 3; i++)
322 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
323 }
324
325 /* Set minimum gain value */
326 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
327 ~B43_NPHY_C1_MINGAIN,
328 23 << B43_NPHY_C1_MINGAIN_SHIFT);
329 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
330 ~B43_NPHY_C2_MINGAIN,
331 23 << B43_NPHY_C2_MINGAIN_SHIFT);
332
333 if (phy->rev < 2) {
334 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
335 ~B43_NPHY_SCRAM_SIGCTL_SCM);
336 }
337
338 /* Set phase track alpha and beta */
339 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
340 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
341 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
342 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
343 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
344 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
345}
346
e50cbcf6
RM		 347/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
348static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
349{
350 struct b43_phy_n *nphy = dev->phy.n;
351 enum ieee80211_band band;
352 u16 tmp;
353
354 if (!enable) {
355 nphy->rfctrl_intc1_save = b43_phy_read(dev,
356 B43_NPHY_RFCTL_INTC1);
357 nphy->rfctrl_intc2_save = b43_phy_read(dev,
358 B43_NPHY_RFCTL_INTC2);
359 band = b43_current_band(dev->wl);
360 if (dev->phy.rev >= 3) {
361 if (band == IEEE80211_BAND_5GHZ)
362 tmp = 0x600;
363 else
364 tmp = 0x480;
365 } else {
366 if (band == IEEE80211_BAND_5GHZ)
367 tmp = 0x180;
368 else
369 tmp = 0x120;
370 }
371 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
372 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
373 } else {
374 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
375 nphy->rfctrl_intc1_save);
376 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
377 nphy->rfctrl_intc2_save);
378 }
379}
380
4a933c85
RM		 381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
382static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
383{
384 u32 tmslow;
385
386 if (dev->phy.type != B43_PHYTYPE_N)
387 return;
388
389 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
390 if (force)
391 tmslow |= SSB_TMSLOW_FGC;
392 else
393 tmslow &= ~SSB_TMSLOW_FGC;
394 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
395}
396
397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 398static void b43_nphy_reset_cca(struct b43_wldev *dev)
399{
400 u16 bbcfg;
401
4a933c85 402 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 403 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 404 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
405 udelay(1);
406 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
407 b43_nphy_bmac_clock_fgc(dev, 0);
408 /* TODO: N PHY Force RF Seq with argument 2 */
95b66bad
MB		 409}
410
bbec398c
RM		 411/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
412static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
413{
414 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
415 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
416}
417
418/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
419static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
420{
421 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
422 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
423}
424
425/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
426static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
427{
428 u16 tmp;
429
430 if (dev->dev->id.revision == 16)
431 b43_mac_suspend(dev);
432
433 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
434 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
435 B43_NPHY_CLASSCTL_WAITEDEN);
436 tmp &= ~mask;
437 tmp |= (val & mask);
438 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
439
440 if (dev->dev->id.revision == 16)
441 b43_mac_enable(dev);
442
443 return tmp;
444}
445
95b66bad
MB		 446enum b43_nphy_rf_sequence {
447 B43_RFSEQ_RX2TX,
448 B43_RFSEQ_TX2RX,
449 B43_RFSEQ_RESET2RX,
450 B43_RFSEQ_UPDATE_GAINH,
451 B43_RFSEQ_UPDATE_GAINL,
452 B43_RFSEQ_UPDATE_GAINU,
453};
454
455static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
456 enum b43_nphy_rf_sequence seq)
457{
458 static const u16 trigger[] = {
459 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
460 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
461 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
462 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
463 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
464 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
465 };
466 int i;
467
468 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
469
470 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
471 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
472 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
473 for (i = 0; i < 200; i++) {
474 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
475 goto ok;
476 msleep(1);
477 }
478 b43err(dev->wl, "RF sequence status timeout\n");
479ok:
480 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
481 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
482}
483
484static void b43_nphy_bphy_init(struct b43_wldev *dev)
485{
486 unsigned int i;
487 u16 val;
488
489 val = 0x1E1F;
490 for (i = 0; i < 14; i++) {
491 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
492 val -= 0x202;
493 }
494 val = 0x3E3F;
495 for (i = 0; i < 16; i++) {
496 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
497 val -= 0x202;
498 }
499 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
500}
501
3c95627d
RM		 502/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
503static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
504 s8 offset, u8 core, u8 rail, u8 type)
505{
506 u16 tmp;
507 bool core1or5 = (core == 1) || (core == 5);
508 bool core2or5 = (core == 2) || (core == 5);
509
510 offset = clamp_val(offset, -32, 31);
511 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
512
513 if (core1or5 && (rail == 0) && (type == 2))
514 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
515 if (core1or5 && (rail == 1) && (type == 2))
516 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
517 if (core2or5 && (rail == 0) && (type == 2))
518 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
519 if (core2or5 && (rail == 1) && (type == 2))
520 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
521 if (core1or5 && (rail == 0) && (type == 0))
522 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
523 if (core1or5 && (rail == 1) && (type == 0))
524 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
525 if (core2or5 && (rail == 0) && (type == 0))
526 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
527 if (core2or5 && (rail == 1) && (type == 0))
528 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
529 if (core1or5 && (rail == 0) && (type == 1))
530 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
531 if (core1or5 && (rail == 1) && (type == 1))
532 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
533 if (core2or5 && (rail == 0) && (type == 1))
534 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
535 if (core2or5 && (rail == 1) && (type == 1))
536 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
537 if (core1or5 && (rail == 0) && (type == 6))
538 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
539 if (core1or5 && (rail == 1) && (type == 6))
540 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
541 if (core2or5 && (rail == 0) && (type == 6))
542 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
543 if (core2or5 && (rail == 1) && (type == 6))
544 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
545 if (core1or5 && (rail == 0) && (type == 3))
546 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
547 if (core1or5 && (rail == 1) && (type == 3))
548 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
549 if (core2or5 && (rail == 0) && (type == 3))
550 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
551 if (core2or5 && (rail == 1) && (type == 3))
552 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
553 if (core1or5 && (type == 4))
554 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
555 if (core2or5 && (type == 4))
556 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
557 if (core1or5 && (type == 5))
558 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
559 if (core2or5 && (type == 5))
560 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
561}
562
563/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
564static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
565{
566 u16 val;
567
568 if (dev->phy.rev >= 3) {
569 /* TODO */
570 } else {
571 if (type < 3)
572 val = 0;
573 else if (type == 6)
574 val = 1;
575 else if (type == 3)
576 val = 2;
577 else
578 val = 3;
579
580 val = (val << 12) | (val << 14);
581 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
582 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
583
584 if (type < 3) {
585 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
586 (type + 1) << 4);
587 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
588 (type + 1) << 4);
589 }
590
591 /* TODO use some definitions */
592 if (code == 0) {
593 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
594 if (type < 3) {
595 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
596 0xFEC7, 0);
597 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
598 0xEFDC, 0);
599 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
600 0xFFFE, 0);
601 udelay(20);
602 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
603 0xFFFE, 0);
604 }
605 } else {
606 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
607 0x3000);
608 if (type < 3) {
609 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
610 0xFEC7, 0x0180);
611 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
612 0xEFDC, (code << 1 | 0x1021));
613 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
614 0xFFFE, 0x0001);
615 udelay(20);
616 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
617 0xFFFE, 0);
618 }
619 }
620 }
621}
622
dfb4aa5d
RM		 623/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
624static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
625{
626 int i;
627 for (i = 0; i < 2; i++) {
628 if (type == 2) {
629 if (i == 0) {
630 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
631 0xFC, buf[0]);
632 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
633 0xFC, buf[1]);
634 } else {
635 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
636 0xFC, buf[2 * i]);
637 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
638 0xFC, buf[2 * i + 1]);
639 }
640 } else {
641 if (i == 0)
642 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
643 0xF3, buf[0] << 2);
644 else
645 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
646 0xF3, buf[2 * i + 1] << 2);
647 }
648 }
649}
650
651/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
652static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
653 u8 nsamp)
654{
655 int i;
656 int out;
657 u16 save_regs_phy[9];
658 u16 s[2];
659
660 if (dev->phy.rev >= 3) {
661 save_regs_phy[0] = b43_phy_read(dev,
662 B43_NPHY_RFCTL_LUT_TRSW_UP1);
663 save_regs_phy[1] = b43_phy_read(dev,
664 B43_NPHY_RFCTL_LUT_TRSW_UP2);
665 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
666 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
667 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
668 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
669 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
670 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
671 }
672
673 b43_nphy_rssi_select(dev, 5, type);
674
675 if (dev->phy.rev < 2) {
676 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
677 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
678 }
679
680 for (i = 0; i < 4; i++)
681 buf[i] = 0;
682
683 for (i = 0; i < nsamp; i++) {
684 if (dev->phy.rev < 2) {
685 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
686 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
687 } else {
688 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
689 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
690 }
691
692 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
693 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
694 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
695 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
696 }
697 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
698 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
699
700 if (dev->phy.rev < 2)
701 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
702
703 if (dev->phy.rev >= 3) {
704 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
705 save_regs_phy[0]);
706 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
707 save_regs_phy[1]);
708 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
709 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
710 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
711 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
712 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
713 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
714 }
715
716 return out;
717}
718
4cb99775
RM		 719/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
720static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 721{
90b9738d
RM		 722 int i, j;
723 u8 state[4];
724 u8 code, val;
725 u16 class, override;
726 u8 regs_save_radio[2];
727 u16 regs_save_phy[2];
728 s8 offset[4];
729
730 u16 clip_state[2];
731 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
732 s32 results_min[4] = { };
733 u8 vcm_final[4] = { };
734 s32 results[4][4] = { };
735 s32 miniq[4][2] = { };
736
737 if (type == 2) {
738 code = 0;
739 val = 6;
740 } else if (type < 2) {
741 code = 25;
742 val = 4;
743 } else {
744 B43_WARN_ON(1);
745 return;
746 }
747
748 class = b43_nphy_classifier(dev, 0, 0);
749 b43_nphy_classifier(dev, 7, 4);
750 b43_nphy_read_clip_detection(dev, clip_state);
751 b43_nphy_write_clip_detection(dev, clip_off);
752
753 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
754 override = 0x140;
755 else
756 override = 0x110;
757
758 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
759 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
760 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
761 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
762
763 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
764 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
765 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
766 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
767
768 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
769 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
770 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
771 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
772 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
773 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
774
775 b43_nphy_rssi_select(dev, 5, type);
776 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
777 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
778
779 for (i = 0; i < 4; i++) {
780 u8 tmp[4];
781 for (j = 0; j < 4; j++)
782 tmp[j] = i;
783 if (type != 1)
784 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
785 b43_nphy_poll_rssi(dev, type, results[i], 8);
786 if (type < 2)
787 for (j = 0; j < 2; j++)
788 miniq[i][j] = min(results[i][2 * j],
789 results[i][2 * j + 1]);
790 }
791
792 for (i = 0; i < 4; i++) {
793 s32 mind = 40;
794 u8 minvcm = 0;
795 s32 minpoll = 249;
796 s32 curr;
797 for (j = 0; j < 4; j++) {
798 if (type == 2)
799 curr = abs(results[j][i]);
800 else
801 curr = abs(miniq[j][i / 2] - code * 8);
802
803 if (curr < mind) {
804 mind = curr;
805 minvcm = j;
806 }
807
808 if (results[j][i] < minpoll)
809 minpoll = results[j][i];
810 }
811 results_min[i] = minpoll;
812 vcm_final[i] = minvcm;
813 }
814
815 if (type != 1)
816 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
817
818 for (i = 0; i < 4; i++) {
819 offset[i] = (code * 8) - results[vcm_final[i]][i];
820
821 if (offset[i] < 0)
822 offset[i] = -((abs(offset[i]) + 4) / 8);
823 else
824 offset[i] = (offset[i] + 4) / 8;
825
826 if (results_min[i] == 248)
827 offset[i] = code - 32;
828
829 if (i % 2 == 0)
830 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
831 type);
832 else
833 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
834 type);
835 }
836
837 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
838 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
839
840 switch (state[2]) {
841 case 1:
842 b43_nphy_rssi_select(dev, 1, 2);
843 break;
844 case 4:
845 b43_nphy_rssi_select(dev, 1, 0);
846 break;
847 case 2:
848 b43_nphy_rssi_select(dev, 1, 1);
849 break;
850 default:
851 b43_nphy_rssi_select(dev, 1, 1);
852 break;
853 }
854
855 switch (state[3]) {
856 case 1:
857 b43_nphy_rssi_select(dev, 2, 2);
858 break;
859 case 4:
860 b43_nphy_rssi_select(dev, 2, 0);
861 break;
862 default:
863 b43_nphy_rssi_select(dev, 2, 1);
864 break;
865 }
866
867 b43_nphy_rssi_select(dev, 0, type);
868
869 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
870 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
871 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
872 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
873
874 b43_nphy_classifier(dev, 7, class);
875 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 876}
877
878/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
879static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
880{
881 /* TODO */
882}
883
884/*
885 * RSSI Calibration
886 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
887 */
888static void b43_nphy_rssi_cal(struct b43_wldev *dev)
889{
890 if (dev->phy.rev >= 3) {
891 b43_nphy_rev3_rssi_cal(dev);
892 } else {
893 b43_nphy_rev2_rssi_cal(dev, 2);
894 b43_nphy_rev2_rssi_cal(dev, 0);
895 b43_nphy_rev2_rssi_cal(dev, 1);
896 }
95b66bad
MB		 897}
898
0988a7a1
RM		 899/*
900 * Init N-PHY
901 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
902 */
424047e6
MB		 903int b43_phy_initn(struct b43_wldev *dev)
904{
0988a7a1 905 struct ssb_bus *bus = dev->dev->bus;
95b66bad 906 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 907 struct b43_phy_n *nphy = phy->n;
908 u8 tx_pwr_state;
909 struct nphy_txgains target;
95b66bad 910 u16 tmp;
0988a7a1
RM		 911 enum ieee80211_band tmp2;
912 bool do_rssi_cal;
913
914 u16 clip[2];
915 bool do_cal = false;
95b66bad 916
0988a7a1
RM		 917 if ((dev->phy.rev >= 3) &&
918 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
919 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
920 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
921 }
922 nphy->deaf_count = 0;
95b66bad 923 b43_nphy_tables_init(dev);
0988a7a1
RM		 924 nphy->crsminpwr_adjusted = false;
925 nphy->noisevars_adjusted = false;
95b66bad
MB		 926
927 /* Clear all overrides */
0988a7a1
RM		 928 if (dev->phy.rev >= 3) {
929 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
930 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
931 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
932 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
933 } else {
934 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
935 }
95b66bad
MB		 936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
937 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 938 if (dev->phy.rev < 6) {
939 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
940 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
941 }
95b66bad
MB		 942 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
943 ~(B43_NPHY_RFSEQMODE_CAOVER |
944 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 945 if (dev->phy.rev >= 3)
946 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 947 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
948
0988a7a1
RM		 949 if (dev->phy.rev <= 2) {
950 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
951 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
952 ~B43_NPHY_BPHY_CTL3_SCALE,
953 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
954 }
95b66bad
MB		 955 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
956 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
957
0988a7a1
RM		 958 if (bus->sprom.boardflags2_lo & 0x100 ||
959 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
960 bus->boardinfo.type == 0x8B))
961 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
962 else
963 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
964 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
965 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
966 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 967
0988a7a1
RM		 968 /* TODO MIMO-Config */
969 /* TODO Update TX/RX chain */
95b66bad
MB		 970
971 if (phy->rev < 2) {
972 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
973 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
974 }
0988a7a1
RM		 975
976 tmp2 = b43_current_band(dev->wl);
977 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
978 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
979 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
980 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
981 nphy->papd_epsilon_offset[0] << 7);
982 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
983 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
984 nphy->papd_epsilon_offset[1] << 7);
985 /* TODO N PHY IPA Set TX Dig Filters */
986 } else if (phy->rev >= 5) {
987 /* TODO N PHY Ext PA Set TX Dig Filters */
988 }
989
95b66bad 990 b43_nphy_workarounds(dev);
95b66bad 991
0988a7a1
RM		 992 /* Reset CCA, in init code it differs a little from standard way */
993 /* b43_nphy_bmac_clock_fgc(dev, 1); */
994 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
995 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
996 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
997 /* b43_nphy_bmac_clock_fgc(dev, 0); */
998
999 /* TODO N PHY MAC PHY Clock Set with argument 1 */
1000
e50cbcf6 1001 b43_nphy_pa_override(dev, false);
95b66bad
MB		 1002 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
1003 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 1004 b43_nphy_pa_override(dev, true);
0988a7a1 1005
bbec398c
RM		 1006 b43_nphy_classifier(dev, 0, 0);
1007 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 1008 tx_pwr_state = nphy->txpwrctrl;
1009 /* TODO N PHY TX power control with argument 0
1010 (turning off power control) */
1011 /* TODO Fix the TX Power Settings */
1012 /* TODO N PHY TX Power Control Idle TSSI */
1013 /* TODO N PHY TX Power Control Setup */
1014
1015 if (phy->rev >= 3) {
1016 /* TODO */
1017 } else {
1018 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1019 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
1020 }
95b66bad 1021
0988a7a1
RM		 1022 if (nphy->phyrxchain != 3)
1023 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
1024 if (nphy->mphase_cal_phase_id > 0)
1025 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
1026
1027 do_rssi_cal = false;
1028 if (phy->rev >= 3) {
1029 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1030 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
1031 else
1032 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
1033
1034 if (do_rssi_cal)
4cb99775 1035 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1036 else
1037 ;/* b43_nphy_restore_rssi_cal(dev); */
1038 } else {
4cb99775 1039 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1040 }
1041
1042 if (!((nphy->measure_hold & 0x6) != 0)) {
1043 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1044 do_cal = (nphy->iqcal_chanspec_2G == 0);
1045 else
1046 do_cal = (nphy->iqcal_chanspec_5G == 0);
1047
1048 if (nphy->mute)
1049 do_cal = false;
1050
1051 if (do_cal) {
1052 /* target = b43_nphy_get_tx_gains(dev); */
1053
1054 if (nphy->antsel_type == 2)
1055 ;/*TODO NPHY Superswitch Init with argument 1*/
1056 if (nphy->perical != 2) {
90b9738d 1057 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 1058 if (phy->rev >= 3) {
1059 nphy->cal_orig_pwr_idx[0] =
1060 nphy->txpwrindex[0].index_internal;
1061 nphy->cal_orig_pwr_idx[1] =
1062 nphy->txpwrindex[1].index_internal;
1063 /* TODO N PHY Pre Calibrate TX Gain */
1064 /*target = b43_nphy_get_tx_gains(dev)*/
1065 }
1066 }
1067 }
1068 }
1069
1070 /*
1071 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
1072 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
1073 Call N PHY Save Cal
1074 else if (nphy->mphase_cal_phase_id == 0)
1075 N PHY Periodic Calibration with argument 3
1076 } else {
1077 b43_nphy_restore_cal(dev);
1078 }
1079 */
1080
1081 /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
1082 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
1083 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
1084 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
1085 if (phy->rev >= 3 && phy->rev <= 6)
1086 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
1087 /* b43_nphy_tx_lp_fbw(dev); */
1088 /* TODO N PHY Spur Workaround */
95b66bad
MB		 1089
1090 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 1091 return 0;
424047e6 1092}
ef1a628d
MB		 1093
1094static int b43_nphy_op_allocate(struct b43_wldev *dev)
1095{
1096 struct b43_phy_n *nphy;
1097
1098 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
1099 if (!nphy)
1100 return -ENOMEM;
1101 dev->phy.n = nphy;
1102
ef1a628d
MB		 1103 return 0;
1104}
1105
fb11137a 1106static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 1107{
fb11137a
MB		 1108 struct b43_phy *phy = &dev->phy;
1109 struct b43_phy_n *nphy = phy->n;
ef1a628d 1110
fb11137a 1111 memset(nphy, 0, sizeof(*nphy));
ef1a628d 1112
fb11137a 1113 //TODO init struct b43_phy_n
ef1a628d
MB		 1114}
1115
fb11137a 1116static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 1117{
fb11137a
MB		 1118 struct b43_phy *phy = &dev->phy;
1119 struct b43_phy_n *nphy = phy->n;
ef1a628d 1120
ef1a628d 1121 kfree(nphy);
fb11137a
MB		 1122 phy->n = NULL;
1123}
1124
1125static int b43_nphy_op_init(struct b43_wldev *dev)
1126{
1127 return b43_phy_initn(dev);
ef1a628d
MB		 1128}
1129
1130static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
1131{
1132#if B43_DEBUG
1133 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
1134 /* OFDM registers are onnly available on A/G-PHYs */
1135 b43err(dev->wl, "Invalid OFDM PHY access at "
1136 "0x%04X on N-PHY\n", offset);
1137 dump_stack();
1138 }
1139 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
1140 /* Ext-G registers are only available on G-PHYs */
1141 b43err(dev->wl, "Invalid EXT-G PHY access at "
1142 "0x%04X on N-PHY\n", offset);
1143 dump_stack();
1144 }
1145#endif /* B43_DEBUG */
1146}
1147
1148static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
1149{
1150 check_phyreg(dev, reg);
1151 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1152 return b43_read16(dev, B43_MMIO_PHY_DATA);
1153}
1154
1155static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1156{
1157 check_phyreg(dev, reg);
1158 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1159 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1160}
1161
1162static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1163{
1164 /* Register 1 is a 32-bit register. */
1165 B43_WARN_ON(reg == 1);
1166 /* N-PHY needs 0x100 for read access */
1167 reg |= 0x100;
1168
1169 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1170 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1171}
1172
1173static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1174{
1175 /* Register 1 is a 32-bit register. */
1176 B43_WARN_ON(reg == 1);
1177
1178 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1179 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1180}
1181
1182static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 1183 bool blocked)
ef1a628d
MB		 1184{//TODO
1185}
1186
cb24f57f
MB		 1187static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
1188{
1189 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
1190 on ? 0 : 0x7FFF);
1191}
1192
ef1a628d
MB		 1193static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
1194 unsigned int new_channel)
1195{
1196 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1197 if ((new_channel < 1) || (new_channel > 14))
1198 return -EINVAL;
1199 } else {
1200 if (new_channel > 200)
1201 return -EINVAL;
1202 }
1203
1204 return nphy_channel_switch(dev, new_channel);
1205}
1206
1207static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
1208{
1209 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1210 return 1;
1211 return 36;
1212}
1213
ef1a628d
MB		 1214const struct b43_phy_operations b43_phyops_n = {
1215 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 1216 .free = b43_nphy_op_free,
1217 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 1218 .init = b43_nphy_op_init,
ef1a628d
MB		 1219 .phy_read = b43_nphy_op_read,
1220 .phy_write = b43_nphy_op_write,
1221 .radio_read = b43_nphy_op_radio_read,
1222 .radio_write = b43_nphy_op_radio_write,
1223 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 1224 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 1225 .switch_channel = b43_nphy_op_switch_channel,
1226 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 1227 .recalc_txpower = b43_nphy_op_recalc_txpower,
1228 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 1229};
Linux 6.x block layer and io_uring tree(s)