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b43: N-PHY: rev3+: complete workarounds
[linux-2.6-block.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
ab499217 260/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 261static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
262 enum n_intc_override intc_override,
263 u16 value, u8 core)
d4814e69 264{
ab499217
RM		 265 u8 i, j;
266 u16 reg, tmp, val;
38646eba 267
d4814e69
RM		 268 B43_WARN_ON(dev->phy.rev < 3);
269
ab499217
RM		 270 for (i = 0; i < 2; i++) {
271 if ((core == 1 && i == 1) || (core == 2 && !i))
272 continue;
38646eba 273
ab499217
RM		 274 reg = (i == 0) ?
275 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 276 b43_phy_set(dev, reg, 0x400);
38646eba 277
89e43dad
RM		 278 switch (intc_override) {
279 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 280 b43_phy_write(dev, reg, 0);
281 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
282 break;
89e43dad 283 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 284 if (!i) {
285 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
286 0xFC3F, (value << 6));
287 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
288 0xFFFE, 1);
289 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
290 B43_NPHY_RFCTL_CMD_START);
291 for (j = 0; j < 100; j++) {
603431e9 292 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 293 j = 0;
294 break;
295 }
296 udelay(10);
38646eba 297 }
ab499217
RM		 298 if (j)
299 b43err(dev->wl,
300 "intc override timeout\n");
301 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
302 0xFFFE);
38646eba 303 } else {
ab499217
RM		 304 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
305 0xFC3F, (value << 6));
306 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
307 0xFFFE, 1);
308 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
309 B43_NPHY_RFCTL_CMD_RXTX);
310 for (j = 0; j < 100; j++) {
603431e9 311 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 312 j = 0;
313 break;
314 }
315 udelay(10);
316 }
317 if (j)
318 b43err(dev->wl,
319 "intc override timeout\n");
320 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
321 0xFFFE);
38646eba 322 }
ab499217 323 break;
89e43dad 324 case N_INTC_OVERRIDE_PA:
ab499217
RM		 325 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
326 tmp = 0x0020;
327 val = value << 5;
328 } else {
329 tmp = 0x0010;
330 val = value << 4;
331 }
332 b43_phy_maskset(dev, reg, ~tmp, val);
333 break;
89e43dad 334 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 335 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
336 tmp = 0x0001;
337 val = value;
338 } else {
339 tmp = 0x0004;
340 val = value << 2;
341 }
342 b43_phy_maskset(dev, reg, ~tmp, val);
343 break;
89e43dad 344 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 345 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
346 tmp = 0x0002;
347 val = value << 1;
348 } else {
349 tmp = 0x0008;
350 val = value << 3;
351 }
352 b43_phy_maskset(dev, reg, ~tmp, val);
353 break;
38646eba 354 }
38646eba 355 }
ab499217 356}
38646eba 357
ab499217
RM		 358/**************************************************
359 * Various PHY ops
360 **************************************************/
361
362/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
363static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
364 const u16 *clip_st)
365{
366 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
367 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 368}
369
ab499217
RM		 370/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
371static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 372{
ab499217
RM		 373 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
374 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 375}
376
ab499217
RM		 377/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
378static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 379{
ab499217 380 u16 tmp;
161d540c 381
ab499217
RM		 382 if (dev->dev->core_rev == 16)
383 b43_mac_suspend(dev);
161d540c 384
ab499217
RM		 385 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
386 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
387 B43_NPHY_CLASSCTL_WAITEDEN);
388 tmp &= ~mask;
389 tmp |= (val & mask);
390 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 391
ab499217
RM		 392 if (dev->dev->core_rev == 16)
393 b43_mac_enable(dev);
161d540c 394
ab499217
RM		 395 return tmp;
396}
161d540c 397
ab499217
RM		 398/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
399static void b43_nphy_reset_cca(struct b43_wldev *dev)
400{
401 u16 bbcfg;
161d540c 402
ab499217
RM		 403 b43_phy_force_clock(dev, 1);
404 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
405 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
406 udelay(1);
407 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
408 b43_phy_force_clock(dev, 0);
409 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
410}
161d540c 411
ab499217
RM		 412/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
413static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
414{
415 struct b43_phy *phy = &dev->phy;
416 struct b43_phy_n *nphy = phy->n;
161d540c 417
ab499217
RM		 418 if (enable) {
419 static const u16 clip[] = { 0xFFFF, 0xFFFF };
420 if (nphy->deaf_count++ == 0) {
421 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
422 b43_nphy_classifier(dev, 0x7, 0);
423 b43_nphy_read_clip_detection(dev, nphy->clip_state);
424 b43_nphy_write_clip_detection(dev, clip);
425 }
426 b43_nphy_reset_cca(dev);
161d540c 427 } else {
ab499217
RM		 428 if (--nphy->deaf_count == 0) {
429 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
430 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 431 }
161d540c 432 }
161d540c
RM		 433}
434
64712095
RM		 435/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
436static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 437{
161d540c 438 struct b43_phy_n *nphy = dev->phy.n;
161d540c 439
64712095
RM		 440 u8 i;
441 s16 tmp;
442 u16 data[4];
443 s16 gain[2];
444 u16 minmax[2];
445 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 446
447 if (nphy->hang_avoid)
448 b43_nphy_stay_in_carrier_search(dev, 1);
449
64712095 450 if (nphy->gain_boost) {
161d540c 451 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 452 gain[0] = 6;
453 gain[1] = 6;
161d540c 454 } else {
64712095
RM		 455 tmp = 40370 - 315 * dev->phy.channel;
456 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
457 tmp = 23242 - 224 * dev->phy.channel;
458 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 459 }
64712095
RM		 460 } else {
461 gain[0] = 0;
462 gain[1] = 0;
161d540c 463 }
161d540c
RM		 464
465 for (i = 0; i < 2; i++) {
64712095
RM		 466 if (nphy->elna_gain_config) {
467 data[0] = 19 + gain[i];
468 data[1] = 25 + gain[i];
469 data[2] = 25 + gain[i];
470 data[3] = 25 + gain[i];
161d540c 471 } else {
64712095
RM		 472 data[0] = lna_gain[0] + gain[i];
473 data[1] = lna_gain[1] + gain[i];
474 data[2] = lna_gain[2] + gain[i];
475 data[3] = lna_gain[3] + gain[i];
161d540c 476 }
64712095 477 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 478
64712095 479 minmax[i] = 23 + gain[i];
161d540c
RM		 480 }
481
64712095
RM		 482 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
483 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
484 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
485 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 486
487 if (nphy->hang_avoid)
488 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 489}
490
ab499217
RM		 491/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
492static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
493 u8 *events, u8 *delays, u8 length)
0eff8fcd 494{
ab499217
RM		 495 struct b43_phy_n *nphy = dev->phy.n;
496 u8 i;
497 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
498 u16 offset1 = cmd << 4;
499 u16 offset2 = offset1 + 0x80;
0eff8fcd 500
ab499217
RM		 501 if (nphy->hang_avoid)
502 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 503
ab499217
RM		 504 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
505 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 506
ab499217
RM		 507 for (i = length; i < 16; i++) {
508 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
509 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 510 }
ab499217
RM		 511
512 if (nphy->hang_avoid)
513 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 514}
7955de0c 515
572d37a4
RM		 516/**************************************************
517 * Radio 0x2057
518 **************************************************/
519
520/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
521static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
522{
523 struct b43_phy *phy = &dev->phy;
524 u16 tmp;
525
526 if (phy->radio_rev == 5) {
527 b43_phy_mask(dev, 0x342, ~0x2);
528 udelay(10);
529 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
530 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
531 }
532
533 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
534 udelay(10);
535 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
536 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
537 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
538 return 0;
539 }
540 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
541 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
542 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
543
544 if (phy->radio_rev == 5) {
545 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
546 b43_radio_mask(dev, 0x1ca, ~0x2);
547 }
548 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
549 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
550 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
551 tmp << 2);
552 }
553
554 return tmp & 0x3e;
555}
556
557/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
558static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
559{
560 struct b43_phy *phy = &dev->phy;
561 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
562 phy->radio_rev == 6);
563 u16 tmp;
564
565 if (special) {
566 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
567 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
568 } else {
569 b43_radio_write(dev, 0x1AE, 0x61);
570 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
571 }
572 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
573 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
574 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
575 5000000))
576 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
577 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
578 if (special) {
579 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
580 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
581 } else {
582 b43_radio_write(dev, 0x1AE, 0x69);
583 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
584 }
585 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
586 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
587 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
588 5000000))
6c187236 589 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 590 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
591 if (special) {
592 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
593 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
594 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
595 } else {
596 b43_radio_write(dev, 0x1AE, 0x73);
597 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
598 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
599 }
600 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
601 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
602 5000000)) {
603 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
604 return 0;
605 }
606 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
607 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
608 return tmp;
609}
610
611static void b43_radio_2057_init_pre(struct b43_wldev *dev)
612{
613 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
614 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
615 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
616 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
617 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
618}
619
620static void b43_radio_2057_init_post(struct b43_wldev *dev)
621{
622 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
623
624 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
625 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
626 mdelay(2);
627 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
628 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
629
630 if (dev->phy.n->init_por) {
631 b43_radio_2057_rcal(dev);
632 b43_radio_2057_rccal(dev);
633 }
634 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
635
636 dev->phy.n->init_por = false;
637}
638
639/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
640static void b43_radio_2057_init(struct b43_wldev *dev)
641{
642 b43_radio_2057_init_pre(dev);
643 r2057_upload_inittabs(dev);
644 b43_radio_2057_init_post(dev);
645}
646
ab499217 647/**************************************************
884a5228 648 * Radio 0x2056
ab499217 649 **************************************************/
7955de0c 650
d4814e69
RM		 651static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
652 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 653{
d4814e69
RM		 654 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
655 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
656 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
657 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
658 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
659 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
660 e->radio_syn_pll_loopfilter1);
661 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
662 e->radio_syn_pll_loopfilter2);
663 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
664 e->radio_syn_pll_loopfilter3);
665 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
666 e->radio_syn_pll_loopfilter4);
667 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
668 e->radio_syn_pll_loopfilter5);
669 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
670 e->radio_syn_reserved_addr27);
671 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
672 e->radio_syn_reserved_addr28);
673 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
674 e->radio_syn_reserved_addr29);
675 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
676 e->radio_syn_logen_vcobuf1);
677 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
678 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
679 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
680
681 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
682 e->radio_rx0_lnaa_tune);
683 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
684 e->radio_rx0_lnag_tune);
685
686 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
687 e->radio_tx0_intpaa_boost_tune);
688 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
689 e->radio_tx0_intpag_boost_tune);
690 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
691 e->radio_tx0_pada_boost_tune);
692 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
693 e->radio_tx0_padg_boost_tune);
694 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
695 e->radio_tx0_pgaa_boost_tune);
696 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
697 e->radio_tx0_pgag_boost_tune);
698 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
699 e->radio_tx0_mixa_boost_tune);
700 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
701 e->radio_tx0_mixg_boost_tune);
702
703 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
704 e->radio_rx1_lnaa_tune);
705 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
706 e->radio_rx1_lnag_tune);
707
708 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
709 e->radio_tx1_intpaa_boost_tune);
710 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
711 e->radio_tx1_intpag_boost_tune);
712 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
713 e->radio_tx1_pada_boost_tune);
714 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
715 e->radio_tx1_padg_boost_tune);
716 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
717 e->radio_tx1_pgaa_boost_tune);
718 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
719 e->radio_tx1_pgag_boost_tune);
720 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
721 e->radio_tx1_mixa_boost_tune);
722 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
723 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 724}
725
d4814e69
RM		 726/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
727static void b43_radio_2056_setup(struct b43_wldev *dev,
728 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 729{
0581483a 730 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 731 enum ieee80211_band band = b43_current_band(dev->wl);
732 u16 offset;
733 u8 i;
d3d178f0
RM		 734 u16 bias, cbias;
735 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
736 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
036cafe4 737
d4814e69 738 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 739
d4814e69 740 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 741 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
742
743 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
744 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
745 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
746 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
747 if (dev->dev->chip_id == 0x4716) {
748 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
749 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
750 } else {
751 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
752 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 753 }
53a6e234 754 }
38646eba
RM		 755 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
756 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
757 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
758 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
759 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
760 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 761 }
53a6e234 762
38646eba
RM		 763 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
764 for (i = 0; i < 2; i++) {
765 offset = i ? B2056_TX1 : B2056_TX0;
766 if (dev->phy.rev >= 5) {
767 b43_radio_write(dev,
768 offset | B2056_TX_PADG_IDAC, 0xcc);
769
770 if (dev->dev->chip_id == 0x4716) {
771 bias = 0x40;
772 cbias = 0x45;
773 pag_boost = 0x5;
774 pgag_boost = 0x33;
775 mixg_boost = 0x55;
776 } else {
777 bias = 0x25;
778 cbias = 0x20;
779 pag_boost = 0x4;
780 pgag_boost = 0x03;
781 mixg_boost = 0x65;
782 }
783 padg_boost = 0x77;
784
785 b43_radio_write(dev,
786 offset | B2056_TX_INTPAG_IMAIN_STAT,
787 bias);
788 b43_radio_write(dev,
789 offset | B2056_TX_INTPAG_IAUX_STAT,
790 bias);
791 b43_radio_write(dev,
792 offset | B2056_TX_INTPAG_CASCBIAS,
793 cbias);
794 b43_radio_write(dev,
795 offset | B2056_TX_INTPAG_BOOST_TUNE,
796 pag_boost);
797 b43_radio_write(dev,
798 offset | B2056_TX_PGAG_BOOST_TUNE,
799 pgag_boost);
800 b43_radio_write(dev,
801 offset | B2056_TX_PADG_BOOST_TUNE,
802 padg_boost);
803 b43_radio_write(dev,
804 offset | B2056_TX_MIXG_BOOST_TUNE,
805 mixg_boost);
806 } else {
807 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
808 b43_radio_write(dev,
809 offset | B2056_TX_INTPAG_IMAIN_STAT,
810 bias);
811 b43_radio_write(dev,
812 offset | B2056_TX_INTPAG_IAUX_STAT,
813 bias);
814 b43_radio_write(dev,
815 offset | B2056_TX_INTPAG_CASCBIAS,
816 0x30);
817 }
818 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
819 }
820 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 821 u16 freq = dev->phy.channel_freq;
822 if (freq < 5100) {
823 paa_boost = 0xA;
824 pada_boost = 0x77;
825 pgaa_boost = 0xF;
826 mixa_boost = 0xF;
827 } else if (freq < 5340) {
828 paa_boost = 0x8;
829 pada_boost = 0x77;
830 pgaa_boost = 0xFB;
831 mixa_boost = 0xF;
832 } else if (freq < 5650) {
833 paa_boost = 0x0;
834 pada_boost = 0x77;
835 pgaa_boost = 0xB;
836 mixa_boost = 0xF;
837 } else {
838 paa_boost = 0x0;
839 pada_boost = 0x77;
840 if (freq != 5825)
841 pgaa_boost = -(freq - 18) / 36 + 168;
842 else
843 pgaa_boost = 6;
844 mixa_boost = 0xF;
845 }
846
847 for (i = 0; i < 2; i++) {
848 offset = i ? B2056_TX1 : B2056_TX0;
849
850 b43_radio_write(dev,
851 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
852 b43_radio_write(dev,
853 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
854 b43_radio_write(dev,
855 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
856 b43_radio_write(dev,
857 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
858 b43_radio_write(dev,
859 offset | B2056_TX_TXSPARE1, 0x30);
860 b43_radio_write(dev,
861 offset | B2056_TX_PA_SPARE2, 0xee);
862 b43_radio_write(dev,
863 offset | B2056_TX_PADA_CASCBIAS, 0x03);
864 b43_radio_write(dev,
865 offset | B2056_TX_INTPAA_IAUX_STAT, 0x50);
866 b43_radio_write(dev,
867 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x50);
868 b43_radio_write(dev,
869 offset | B2056_TX_INTPAA_CASCBIAS, 0x30);
870 }
a2d9bc6f 871 }
38646eba 872
d4814e69
RM		 873 udelay(50);
874 /* VCO calibration */
875 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
876 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
877 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
878 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
879 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
880 udelay(300);
53a6e234
MB		 881}
882
d3d178f0
RM		 883static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
884{
885 struct b43_phy *phy = &dev->phy;
886 u16 mast2, tmp;
887
888 if (phy->rev != 3)
889 return 0;
890
891 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
892 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
893
894 udelay(10);
895 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
896 udelay(10);
897 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
898
899 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
900 1000000)) {
901 b43err(dev->wl, "Radio recalibration timeout\n");
902 return 0;
903 }
904
905 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
906 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
907 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
908
909 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
910
911 return tmp & 0x1f;
912}
913
ea7ee14b
RM		 914static void b43_radio_init2056_pre(struct b43_wldev *dev)
915{
916 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
917 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
918 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
919 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
920 B43_NPHY_RFCTL_CMD_OEPORFORCE);
921 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
922 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
923 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
924 B43_NPHY_RFCTL_CMD_CHIP0PU);
925}
926
927static void b43_radio_init2056_post(struct b43_wldev *dev)
928{
929 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
930 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
931 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
932 msleep(1);
933 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
934 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
935 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 936 if (dev->phy.n->init_por)
937 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 938}
939
d817f4e1
RM		 940/*
941 * Initialize a Broadcom 2056 N-radio
942 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
943 */
944static void b43_radio_init2056(struct b43_wldev *dev)
945{
ea7ee14b
RM		 946 b43_radio_init2056_pre(dev);
947 b2056_upload_inittabs(dev, 0, 0);
948 b43_radio_init2056_post(dev);
d3d178f0
RM		 949
950 dev->phy.n->init_por = false;
d817f4e1
RM		 951}
952
884a5228
RM		 953/**************************************************
954 * Radio 0x2055
955 **************************************************/
956
957static void b43_chantab_radio_upload(struct b43_wldev *dev,
958 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 959{
884a5228
RM		 960 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
961 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
962 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
963 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
964 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 965
884a5228
RM		 966 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
967 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
968 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
969 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
970 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 971
884a5228
RM		 972 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
973 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
974 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
975 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
976 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 977
884a5228
RM		 978 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
979 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
980 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
981 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
982 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 983
884a5228
RM		 984 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
985 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
986 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
987 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
988 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 989
884a5228
RM		 990 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
991 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 992}
993
884a5228
RM		 994/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
995static void b43_radio_2055_setup(struct b43_wldev *dev,
996 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 997{
884a5228 998 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 999
884a5228
RM		 1000 b43_chantab_radio_upload(dev, e);
1001 udelay(50);
1002 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1003 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1004 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1005 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1006 udelay(300);
95b66bad
MB		 1007}
1008
884a5228 1009static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1010{
884a5228
RM		 1011 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1012 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1013 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1014 B43_NPHY_RFCTL_CMD_CHIP0PU |
1015 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1016 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1017 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1018}
1019
884a5228 1020static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1021{
1022 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1023 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1024 bool workaround = false;
2faa6b83 1025
884a5228
RM		 1026 if (sprom->revision < 4)
1027 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1028 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1029 && dev->dev->board_rev >= 0x41);
2faa6b83 1030 else
884a5228
RM		 1031 workaround =
1032 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1033
884a5228
RM		 1034 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1035 if (workaround) {
1036 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1037 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1038 }
1039 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1040 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1041 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1042 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1043 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1044 msleep(1);
1045 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1046 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1047 b43err(dev->wl, "radio post init timeout\n");
1048 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1049 b43_switch_channel(dev, dev->phy.channel);
1050 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1051 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1052 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1053 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1054 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1055 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1056 if (!nphy->gain_boost) {
1057 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1058 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1059 } else {
1060 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1061 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1062 }
1063 udelay(2);
2faa6b83
RM		 1064}
1065
884a5228
RM		 1066/*
1067 * Initialize a Broadcom 2055 N-radio
1068 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1069 */
1070static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1071{
884a5228
RM		 1072 b43_radio_init2055_pre(dev);
1073 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1074 /* Follow wl, not specs. Do not force uploading all regs */
1075 b2055_upload_inittab(dev, 0, 0);
a67162ab 1076 } else {
884a5228
RM		 1077 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1078 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1079 }
884a5228 1080 b43_radio_init2055_post(dev);
a67162ab
RM		 1081}
1082
8be89535
RM		 1083/**************************************************
1084 * Samples
1085 **************************************************/
026816fc 1086
8be89535
RM		 1087/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1088static int b43_nphy_load_samples(struct b43_wldev *dev,
1089 struct b43_c32 *samples, u16 len) {
1090 struct b43_phy_n *nphy = dev->phy.n;
1091 u16 i;
1092 u32 *data;
1093
1094 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1095 if (!data) {
1096 b43err(dev->wl, "allocation for samples loading failed\n");
1097 return -ENOMEM;
1098 }
1099 if (nphy->hang_avoid)
1100 b43_nphy_stay_in_carrier_search(dev, 1);
1101
1102 for (i = 0; i < len; i++) {
1103 data[i] = (samples[i].i & 0x3FF << 10);
1104 data[i] |= samples[i].q & 0x3FF;
1105 }
1106 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1107
1108 kfree(data);
1109 if (nphy->hang_avoid)
1110 b43_nphy_stay_in_carrier_search(dev, 0);
1111 return 0;
026816fc
RM		 1112}
1113
8be89535
RM		 1114/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1115static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1116 bool test)
026816fc 1117{
8be89535
RM		 1118 int i;
1119 u16 bw, len, rot, angle;
1120 struct b43_c32 *samples;
026816fc 1121
026816fc 1122
8be89535
RM		 1123 bw = (dev->phy.is_40mhz) ? 40 : 20;
1124 len = bw << 3;
026816fc 1125
8be89535
RM		 1126 if (test) {
1127 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1128 bw = 82;
1129 else
1130 bw = 80;
026816fc 1131
8be89535
RM		 1132 if (dev->phy.is_40mhz)
1133 bw <<= 1;
1134
1135 len = bw << 1;
026816fc
RM		 1136 }
1137
8be89535
RM		 1138 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1139 if (!samples) {
1140 b43err(dev->wl, "allocation for samples generation failed\n");
1141 return 0;
1142 }
1143 rot = (((freq * 36) / bw) << 16) / 100;
1144 angle = 0;
026816fc 1145
8be89535
RM		 1146 for (i = 0; i < len; i++) {
1147 samples[i] = b43_cordic(angle);
1148 angle += rot;
1149 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1150 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1151 }
8be89535
RM		 1152
1153 i = b43_nphy_load_samples(dev, samples, len);
1154 kfree(samples);
1155 return (i < 0) ? 0 : len;
026816fc
RM		 1156}
1157
8be89535
RM		 1158/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1159static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1160 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1161{
8be89535 1162 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1163 int i;
8be89535
RM		 1164 u16 seq_mode;
1165 u32 tmp;
34a56f2c 1166
8be89535
RM		 1167 if (nphy->hang_avoid)
1168 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1169
8be89535
RM		 1170 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1171 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1172 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1173 }
34a56f2c 1174
8be89535
RM		 1175 if (!dev->phy.is_40mhz)
1176 tmp = 0x6464;
1177 else
1178 tmp = 0x4747;
1179 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1180
8be89535
RM		 1181 if (nphy->hang_avoid)
1182 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c 1183
8be89535 1184 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1185
8be89535
RM		 1186 if (loops != 0xFFFF)
1187 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1188 else
1189 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1190
8be89535 1191 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1192
8be89535 1193 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1194
8be89535
RM		 1195 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1196 if (iqmode) {
1197 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1198 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1199 } else {
1200 if (dac_test)
1201 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1202 else
1203 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1204 }
1205 for (i = 0; i < 100; i++) {
2c8ac7eb 1206 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1207 i = 0;
1208 break;
34a56f2c 1209 }
8be89535 1210 udelay(10);
34a56f2c 1211 }
8be89535
RM		 1212 if (i)
1213 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1214
8be89535 1215 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
34a56f2c
RM		 1216}
1217
4d9f46ba
RM		 1218/**************************************************
1219 * RSSI
1220 **************************************************/
1221
1222/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1223static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1224 s8 offset, u8 core,
1225 enum n_rail_type rail,
2a2d0589 1226 enum n_rssi_type rssi_type)
09146400 1227{
4d9f46ba
RM		 1228 u16 tmp;
1229 bool core1or5 = (core == 1) || (core == 5);
1230 bool core2or5 = (core == 2) || (core == 5);
09146400 1231
4d9f46ba
RM		 1232 offset = clamp_val(offset, -32, 31);
1233 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1234
e5ab1fd7 1235 switch (rssi_type) {
2a2d0589 1236 case N_RSSI_NB:
e5ab1fd7
RM		 1237 if (core1or5 && rail == N_RAIL_I)
1238 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1239 if (core1or5 && rail == N_RAIL_Q)
1240 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1241 if (core2or5 && rail == N_RAIL_I)
1242 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1243 if (core2or5 && rail == N_RAIL_Q)
1244 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1245 break;
2a2d0589 1246 case N_RSSI_W1:
e5ab1fd7
RM		 1247 if (core1or5 && rail == N_RAIL_I)
1248 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1249 if (core1or5 && rail == N_RAIL_Q)
1250 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1251 if (core2or5 && rail == N_RAIL_I)
1252 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1253 if (core2or5 && rail == N_RAIL_Q)
1254 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1255 break;
2a2d0589 1256 case N_RSSI_W2:
e5ab1fd7
RM		 1257 if (core1or5 && rail == N_RAIL_I)
1258 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1259 if (core1or5 && rail == N_RAIL_Q)
1260 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1261 if (core2or5 && rail == N_RAIL_I)
1262 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1263 if (core2or5 && rail == N_RAIL_Q)
1264 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1265 break;
2a2d0589 1266 case N_RSSI_TBD:
e5ab1fd7
RM		 1267 if (core1or5 && rail == N_RAIL_I)
1268 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1269 if (core1or5 && rail == N_RAIL_Q)
1270 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1271 if (core2or5 && rail == N_RAIL_I)
1272 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1273 if (core2or5 && rail == N_RAIL_Q)
1274 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1275 break;
2a2d0589 1276 case N_RSSI_IQ:
e5ab1fd7
RM		 1277 if (core1or5 && rail == N_RAIL_I)
1278 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1279 if (core1or5 && rail == N_RAIL_Q)
1280 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1281 if (core2or5 && rail == N_RAIL_I)
1282 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1283 if (core2or5 && rail == N_RAIL_Q)
1284 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1285 break;
2a2d0589 1286 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1287 if (core1or5)
1288 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1289 if (core2or5)
1290 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1291 break;
2a2d0589 1292 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1293 if (core1or5)
1294 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1295 if (core2or5)
1296 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1297 break;
1298 }
8987a9e9
RM		 1299}
1300
a3764ef7
RM		 1301static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1302 enum n_rssi_type rssi_type)
bbec398c 1303{
4d9f46ba
RM		 1304 u8 i;
1305 u16 reg, val;
bbec398c 1306
4d9f46ba
RM		 1307 if (code == 0) {
1308 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1309 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1310 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1311 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1312 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1313 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1314 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1315 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1316 } else {
1317 for (i = 0; i < 2; i++) {
1318 if ((code == 1 && i == 1) || (code == 2 && !i))
1319 continue;
bbec398c 1320
4d9f46ba
RM		 1321 reg = (i == 0) ?
1322 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1323 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1324
a3764ef7
RM		 1325 if (rssi_type == N_RSSI_W1 ||
1326 rssi_type == N_RSSI_W2 ||
1327 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1328 reg = (i == 0) ?
1329 B43_NPHY_AFECTL_C1 :
1330 B43_NPHY_AFECTL_C2;
1331 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1332
4d9f46ba
RM		 1333 reg = (i == 0) ?
1334 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1335 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1336 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1337
a3764ef7 1338 if (rssi_type == N_RSSI_W1)
4d9f46ba 1339 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1340 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1341 val = 16;
1342 else
1343 val = 32;
1344 b43_phy_set(dev, reg, val);
5c1a140a 1345
4d9f46ba
RM		 1346 reg = (i == 0) ?
1347 B43_NPHY_TXF_40CO_B1S0 :
1348 B43_NPHY_TXF_40CO_B32S1;
1349 b43_phy_set(dev, reg, 0x0020);
1350 } else {
a3764ef7 1351 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1352 val = 0x0100;
a3764ef7 1353 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1354 val = 0x0200;
1355 else
1356 val = 0x0300;
5c1a140a 1357
4d9f46ba
RM		 1358 reg = (i == 0) ?
1359 B43_NPHY_AFECTL_C1 :
1360 B43_NPHY_AFECTL_C2;
53ae8e8c 1361
4d9f46ba
RM		 1362 b43_phy_maskset(dev, reg, 0xFCFF, val);
1363 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1364
a3764ef7
RM		 1365 if (rssi_type != N_RSSI_IQ &&
1366 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1367 enum ieee80211_band band =
1368 b43_current_band(dev->wl);
53ae8e8c 1369
4d9f46ba
RM		 1370 if (b43_nphy_ipa(dev))
1371 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1372 else
1373 val = 0x11;
1374 reg = (i == 0) ? 0x2000 : 0x3000;
1375 reg |= B2055_PADDRV;
0c201cfb 1376 b43_radio_write(dev, reg, val);
53ae8e8c 1377
4d9f46ba
RM		 1378 reg = (i == 0) ?
1379 B43_NPHY_AFECTL_OVER1 :
1380 B43_NPHY_AFECTL_OVER;
1381 b43_phy_set(dev, reg, 0x0200);
1382 }
1383 }
1384 }
53ae8e8c 1385 }
53ae8e8c
RM		 1386}
1387
a3764ef7
RM		 1388static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1389 enum n_rssi_type rssi_type)
9442e5b5 1390{
4d9f46ba 1391 u16 val;
a3764ef7 1392 bool rssi_w1_w2_nb = false;
9442e5b5 1393
a3764ef7
RM		 1394 switch (rssi_type) {
1395 case N_RSSI_W1:
1396 case N_RSSI_W2:
1397 case N_RSSI_NB:
4d9f46ba 1398 val = 0;
a3764ef7
RM		 1399 rssi_w1_w2_nb = true;
1400 break;
1401 case N_RSSI_TBD:
4d9f46ba 1402 val = 1;
a3764ef7
RM		 1403 break;
1404 case N_RSSI_IQ:
4d9f46ba 1405 val = 2;
a3764ef7
RM		 1406 break;
1407 default:
4d9f46ba 1408 val = 3;
a3764ef7 1409 }
9442e5b5 1410
4d9f46ba
RM		 1411 val = (val << 12) | (val << 14);
1412 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1413 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1414
a3764ef7 1415 if (rssi_w1_w2_nb) {
4d9f46ba 1416 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1417 (rssi_type + 1) << 4);
4d9f46ba 1418 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1419 (rssi_type + 1) << 4);
9442e5b5
RM		 1420 }
1421
4d9f46ba
RM		 1422 if (code == 0) {
1423 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1424 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1425 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1426 ~(B43_NPHY_RFCTL_CMD_RXEN |
1427 B43_NPHY_RFCTL_CMD_CORESEL));
1428 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1429 ~(0x1 << 12 |
1430 0x1 << 5 |
1431 0x1 << 1 |
1432 0x1));
1433 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1434 ~B43_NPHY_RFCTL_CMD_START);
1435 udelay(20);
1436 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1437 }
1438 } else {
1439 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1440 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1441 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1442 ~(B43_NPHY_RFCTL_CMD_RXEN |
1443 B43_NPHY_RFCTL_CMD_CORESEL),
1444 (B43_NPHY_RFCTL_CMD_RXEN |
1445 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1446 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1447 (0x1 << 12 |
1448 0x1 << 5 |
1449 0x1 << 1 |
1450 0x1));
1451 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1452 B43_NPHY_RFCTL_CMD_START);
1453 udelay(20);
1454 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1455 }
9442e5b5 1456 }
9442e5b5
RM		 1457}
1458
4d9f46ba 1459/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1460static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1461 enum n_rssi_type type)
d24019ad 1462{
4d9f46ba
RM		 1463 if (dev->phy.rev >= 3)
1464 b43_nphy_rev3_rssi_select(dev, code, type);
1465 else
1466 b43_nphy_rev2_rssi_select(dev, code, type);
1467}
d24019ad 1468
5ecab603 1469/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1470static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1471 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1472{
1473 int i;
d24019ad 1474 for (i = 0; i < 2; i++) {
a3764ef7 1475 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1476 if (i == 0) {
1477 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1478 0xFC, buf[0]);
1479 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1480 0xFC, buf[1]);
1481 } else {
1482 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1483 0xFC, buf[2 * i]);
1484 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1485 0xFC, buf[2 * i + 1]);
1486 }
d24019ad 1487 } else {
5ecab603
RM		 1488 if (i == 0)
1489 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1490 0xF3, buf[0] << 2);
1491 else
1492 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1493 0xF3, buf[2 * i + 1] << 2);
d24019ad 1494 }
d24019ad 1495 }
d24019ad
RM		 1496}
1497
5ecab603 1498/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1499static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1500 s32 *buf, u8 nsamp)
ef5127a4 1501{
5ecab603
RM		 1502 int i;
1503 int out;
1504 u16 save_regs_phy[9];
1505 u16 s[2];
ef5127a4
RM		 1506
1507 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1508 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1509 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1510 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1511 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1512 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1513 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1514 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1515 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1516 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1517 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1518 save_regs_phy[8] = 0;
ef5127a4 1519 } else {
5ecab603
RM		 1520 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1521 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1522 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1523 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1524 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1525 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1526 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1527 save_regs_phy[7] = 0;
1528 save_regs_phy[8] = 0;
1529 }
ef5127a4 1530
a3764ef7 1531 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1532
5ecab603
RM		 1533 if (dev->phy.rev < 2) {
1534 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1535 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1536 }
ef5127a4 1537
5ecab603
RM		 1538 for (i = 0; i < 4; i++)
1539 buf[i] = 0;
1540
1541 for (i = 0; i < nsamp; i++) {
1542 if (dev->phy.rev < 2) {
1543 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1544 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1545 } else {
5ecab603
RM		 1546 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1547 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1548 }
1549
5ecab603
RM		 1550 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1551 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1552 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1553 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1554 }
1555 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1556 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1557
5ecab603
RM		 1558 if (dev->phy.rev < 2)
1559 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1560
5ecab603 1561 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1562 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1563 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1564 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1565 save_regs_phy[2]);
5ecab603 1566 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1567 save_regs_phy[3]);
5ecab603
RM		 1568 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1569 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1570 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1571 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1572 } else {
1573 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1574 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1575 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1576 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1577 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1578 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1579 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1580 }
ef5127a4 1581
5ecab603
RM		 1582 return out;
1583}
ef5127a4 1584
e0c9a021
RM		 1585/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1586static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1587{
1588 struct b43_phy_n *nphy = dev->phy.n;
1589
1590 u16 saved_regs_phy_rfctl[2];
1591 u16 saved_regs_phy[13];
1592 u16 regs_to_store[] = {
1593 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1594 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1595 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1596 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1597 B43_NPHY_RFCTL_CMD,
1598 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1599 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1600 };
1601
1602 u16 class;
1603
1604 u16 clip_state[2];
1605 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1606
1607 u8 vcm_final = 0;
2e1253d6 1608 s32 offset[4];
e0c9a021
RM		 1609 s32 results[8][4] = { };
1610 s32 results_min[4] = { };
1611 s32 poll_results[4] = { };
1612
1613 u16 *rssical_radio_regs = NULL;
1614 u16 *rssical_phy_regs = NULL;
1615
1616 u16 r; /* routing */
1617 u8 rx_core_state;
37859a75 1618 int core, i, j, vcm;
e0c9a021
RM		 1619
1620 class = b43_nphy_classifier(dev, 0, 0);
1621 b43_nphy_classifier(dev, 7, 4);
1622 b43_nphy_read_clip_detection(dev, clip_state);
1623 b43_nphy_write_clip_detection(dev, clip_off);
1624
1625 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1626 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1627 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1628 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1629
89e43dad
RM		 1630 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1631 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
78ae7532
RM		 1632 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1633 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1634 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1635 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
e0c9a021
RM		 1636
1637 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
78ae7532
RM		 1638 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1639 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
e0c9a021 1640 } else {
78ae7532
RM		 1641 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1642 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
e0c9a021
RM		 1643 }
1644
1645 rx_core_state = b43_nphy_get_rx_core_state(dev);
1646 for (core = 0; core < 2; core++) {
1647 if (!(rx_core_state & (1 << core)))
1648 continue;
1649 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1650 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1651 N_RSSI_NB);
1652 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1653 N_RSSI_NB);
37859a75
RM		 1654
1655 /* Grab RSSI results for every possible VCM */
1656 for (vcm = 0; vcm < 8; vcm++) {
e0c9a021 1657 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
37859a75 1658 vcm << 2);
a3764ef7 1659 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1660 }
37859a75
RM		 1661
1662 /* Find out which VCM got the best results */
cddec902 1663 for (i = 0; i < 4; i += 2) {
37859a75 1664 s32 currd;
e67dd874 1665 s32 mind = 0x100000;
e0c9a021
RM		 1666 s32 minpoll = 249;
1667 u8 minvcm = 0;
1668 if (2 * core != i)
1669 continue;
37859a75
RM		 1670 for (vcm = 0; vcm < 8; vcm++) {
1671 currd = results[vcm][i] * results[vcm][i] +
1672 results[vcm][i + 1] * results[vcm][i];
1673 if (currd < mind) {
1674 mind = currd;
1675 minvcm = vcm;
e0c9a021 1676 }
37859a75
RM		 1677 if (results[vcm][i] < minpoll)
1678 minpoll = results[vcm][i];
e0c9a021
RM		 1679 }
1680 vcm_final = minvcm;
1681 results_min[i] = minpoll;
1682 }
37859a75
RM		 1683
1684 /* Select the best VCM */
e0c9a021
RM		 1685 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1686 vcm_final << 2);
37859a75 1687
e0c9a021
RM		 1688 for (i = 0; i < 4; i++) {
1689 if (core != i / 2)
1690 continue;
1691 offset[i] = -results[vcm_final][i];
1692 if (offset[i] < 0)
1693 offset[i] = -((abs(offset[i]) + 4) / 8);
1694 else
1695 offset[i] = (offset[i] + 4) / 8;
1696 if (results_min[i] == 248)
1697 offset[i] = -32;
1698 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1699 (i / 2 == 0) ? 1 : 2,
6aa38725 1700 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1701 N_RSSI_NB);
e0c9a021
RM		 1702 }
1703 }
37859a75 1704
e0c9a021
RM		 1705 for (core = 0; core < 2; core++) {
1706 if (!(rx_core_state & (1 << core)))
1707 continue;
1708 for (i = 0; i < 2; i++) {
6aa38725
RM		 1709 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1710 N_RAIL_I, i);
1711 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1712 N_RAIL_Q, i);
e0c9a021
RM		 1713 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1714 for (j = 0; j < 4; j++) {
cddec902 1715 if (j / 2 == core) {
e0c9a021 1716 offset[j] = 232 - poll_results[j];
cddec902
RM		 1717 if (offset[j] < 0)
1718 offset[j] = -(abs(offset[j] + 4) / 8);
1719 else
1720 offset[j] = (offset[j] + 4) / 8;
1721 b43_nphy_scale_offset_rssi(dev, 0,
1722 offset[2 * core], core + 1, j % 2, i);
1723 }
e0c9a021
RM		 1724 }
1725 }
1726 }
1727
1728 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1729 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1730
1731 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1732
1733 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1734 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1735 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1736
1737 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1738 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1739 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1740
1741 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1742 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1743
1744 /* Store for future configuration */
1745 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1746 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1747 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1748 } else {
1749 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1750 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1751 }
9a98979e
RM		 1752 if (dev->phy.rev >= 7) {
1753 } else {
1754 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1755 B2056_RX_RSSI_MISC);
1756 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1757 B2056_RX_RSSI_MISC);
1758 }
e0c9a021
RM		 1759 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1760 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1761 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1762 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1763 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1764 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1765 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1766 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1767 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1768 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1769 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1770 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1771
1772 /* Remember for which channel we store configuration */
1773 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1774 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1775 else
1776 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1777
1778 /* End of calibration, restore configuration */
1779 b43_nphy_classifier(dev, 7, class);
1780 b43_nphy_write_clip_detection(dev, clip_state);
1781}
1782
5ecab603 1783/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1784static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1785{
37859a75 1786 int i, j, vcm;
5ecab603
RM		 1787 u8 state[4];
1788 u8 code, val;
1789 u16 class, override;
1790 u8 regs_save_radio[2];
1791 u16 regs_save_phy[2];
1792
2e1253d6 1793 s32 offset[4];
5ecab603
RM		 1794 u8 core;
1795 u8 rail;
1796
1797 u16 clip_state[2];
1798 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1799 s32 results_min[4] = { };
1800 u8 vcm_final[4] = { };
1801 s32 results[4][4] = { };
1802 s32 miniq[4][2] = { };
1803
a3764ef7 1804 if (type == N_RSSI_NB) {
5ecab603
RM		 1805 code = 0;
1806 val = 6;
a3764ef7 1807 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1808 code = 25;
1809 val = 4;
1810 } else {
1811 B43_WARN_ON(1);
1812 return;
1813 }
1814
1815 class = b43_nphy_classifier(dev, 0, 0);
1816 b43_nphy_classifier(dev, 7, 4);
1817 b43_nphy_read_clip_detection(dev, clip_state);
1818 b43_nphy_write_clip_detection(dev, clip_off);
1819
1820 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1821 override = 0x140;
1822 else
1823 override = 0x110;
1824
1825 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 1826 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 1827 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 1828 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 1829
1830 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 1831 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 1832 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 1833 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 1834
0c201cfb
RM		 1835 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1836 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 1837 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1838 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 1839 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1840 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 1841
1842 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1843 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1844 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1845
37859a75 1846 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1847 u8 tmp[4];
1848 for (j = 0; j < 4; j++)
37859a75 1849 tmp[j] = vcm;
a3764ef7 1850 if (type != N_RSSI_W2)
5ecab603 1851 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1852 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1853 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1854 for (j = 0; j < 2; j++)
37859a75
RM		 1855 miniq[vcm][j] = min(results[vcm][2 * j],
1856 results[vcm][2 * j + 1]);
5ecab603
RM		 1857 }
1858
1859 for (i = 0; i < 4; i++) {
e67dd874 1860 s32 mind = 0x100000;
5ecab603
RM		 1861 u8 minvcm = 0;
1862 s32 minpoll = 249;
37859a75
RM		 1863 s32 currd;
1864 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1865 if (type == N_RSSI_NB)
542e15f3 1866 currd = abs(results[vcm][i] - code * 8);
5ecab603 1867 else
37859a75 1868 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1869
37859a75
RM		 1870 if (currd < mind) {
1871 mind = currd;
1872 minvcm = vcm;
5ecab603
RM		 1873 }
1874
37859a75
RM		 1875 if (results[vcm][i] < minpoll)
1876 minpoll = results[vcm][i];
8e60b044 1877 }
5ecab603
RM		 1878 results_min[i] = minpoll;
1879 vcm_final[i] = minvcm;
1880 }
ef5127a4 1881
a3764ef7 1882 if (type != N_RSSI_W2)
5ecab603 1883 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 1884
5ecab603
RM		 1885 for (i = 0; i < 4; i++) {
1886 offset[i] = (code * 8) - results[vcm_final[i]][i];
1887
1888 if (offset[i] < 0)
1889 offset[i] = -((abs(offset[i]) + 4) / 8);
1890 else
1891 offset[i] = (offset[i] + 4) / 8;
1892
1893 if (results_min[i] == 248)
1894 offset[i] = code - 32;
1895
1896 core = (i / 2) ? 2 : 1;
6aa38725 1897 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 1898
1899 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1900 type);
1901 }
1902
1903 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1904 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1905
1906 switch (state[2]) {
1907 case 1:
a3764ef7 1908 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 1909 break;
1910 case 4:
a3764ef7 1911 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 1912 break;
1913 case 2:
a3764ef7 1914 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 1915 break;
1916 default:
a3764ef7 1917 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 1918 break;
1919 }
1920
1921 switch (state[3]) {
1922 case 1:
a3764ef7 1923 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 1924 break;
1925 case 4:
a3764ef7 1926 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 1927 break;
1928 default:
a3764ef7 1929 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 1930 break;
1931 }
1932
1933 b43_nphy_rssi_select(dev, 0, type);
1934
1935 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 1936 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 1937 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 1938 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 1939
1940 b43_nphy_classifier(dev, 7, class);
1941 b43_nphy_write_clip_detection(dev, clip_state);
1942 /* Specs don't say about reset here, but it makes wl and b43 dumps
1943 identical, it really seems wl performs this */
1944 b43_nphy_reset_cca(dev);
1945}
1946
5ecab603
RM		 1947/*
1948 * RSSI Calibration
1949 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1950 */
1951static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1952{
1953 if (dev->phy.rev >= 3) {
1954 b43_nphy_rev3_rssi_cal(dev);
1955 } else {
2a2d0589
RM		 1956 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
1957 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
1958 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 1959 }
1960}
1961
64712095
RM		 1962/**************************************************
1963 * Workarounds
1964 **************************************************/
1965
1966static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1967{
1968 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1969
1970 bool ghz5;
1971 bool ext_lna;
1972 u16 rssi_gain;
1973 struct nphy_gain_ctl_workaround_entry *e;
1974 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1975 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1976
1977 /* Prepare values */
1978 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1979 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 1980 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1981 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 1982 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1983 if (ghz5 && dev->phy.rev >= 5)
1984 rssi_gain = 0x90;
1985 else
1986 rssi_gain = 0x50;
1987
1988 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1989
1990 /* Set Clip 2 detect */
04519dc6
RM		 1991 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1992 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 1993
1994 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1995 0x17);
1996 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1997 0x17);
1998 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1999 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2000 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2001 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2002 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2003 rssi_gain);
2004 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2005 rssi_gain);
2006 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2007 0x17);
2008 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2009 0x17);
2010 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2011 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2012
2013 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2014 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2015 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2016 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2017 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2018 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2019 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2020 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2021 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2022 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2023 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2024 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2025
04519dc6
RM		 2026 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2027 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2028
64712095
RM		 2029 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2030 e->rfseq_init);
64712095 2031
04519dc6
RM		 2032 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2033 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2034 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2035 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2036 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2037 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2038
2039 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2040 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2041 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2042 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2043 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2044 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2045 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2046 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2047 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2048 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2049}
2050
2051static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2052{
2053 struct b43_phy_n *nphy = dev->phy.n;
2054
2055 u8 i, j;
2056 u8 code;
2057 u16 tmp;
2058 u8 rfseq_events[3] = { 6, 8, 7 };
2059 u8 rfseq_delays[3] = { 10, 30, 1 };
2060
2061 /* Set Clip 2 detect */
2062 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2063 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2064
2065 /* Set narrowband clip threshold */
2066 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2067 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2068
2069 if (!dev->phy.is_40mhz) {
2070 /* Set dwell lengths */
2071 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2072 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2073 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2074 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2075 }
2076
2077 /* Set wideband clip 2 threshold */
2078 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2079 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2080 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2081 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2082
2083 if (!dev->phy.is_40mhz) {
2084 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2085 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2086 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2087 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2088 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2089 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2090 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2091 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2092 }
2093
2094 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2095
2096 if (nphy->gain_boost) {
2097 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2098 dev->phy.is_40mhz)
2099 code = 4;
2100 else
2101 code = 5;
2102 } else {
2103 code = dev->phy.is_40mhz ? 6 : 7;
2104 }
2105
2106 /* Set HPVGA2 index */
2107 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2108 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2109 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2110 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2111
2112 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2113 /* specs say about 2 loops, but wl does 4 */
2114 for (i = 0; i < 4; i++)
2115 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2116
2117 b43_nphy_adjust_lna_gain_table(dev);
2118
2119 if (nphy->elna_gain_config) {
2120 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2121 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2122 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2123 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2124 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2125
2126 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2127 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2128 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2129 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2130 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2131
2132 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2133 /* specs say about 2 loops, but wl does 4 */
2134 for (i = 0; i < 4; i++)
2135 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2136 (code << 8 | 0x74));
2137 }
2138
2139 if (dev->phy.rev == 2) {
2140 for (i = 0; i < 4; i++) {
2141 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2142 (0x0400 * i) + 0x0020);
2143 for (j = 0; j < 21; j++) {
2144 tmp = j * (i < 2 ? 3 : 1);
2145 b43_phy_write(dev,
2146 B43_NPHY_TABLE_DATALO, tmp);
2147 }
2148 }
ef5127a4 2149 }
64712095
RM		 2150
2151 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2152 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2153 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2154 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2155
2156 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2157 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2158}
2159
2160/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2161static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2162{
d11d354b
RM		 2163 if (dev->phy.rev >= 7)
2164 ; /* TODO */
2165 else if (dev->phy.rev >= 3)
64712095
RM		 2166 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2167 else
2168 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2169}
2170
d11d354b
RM		 2171/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2172static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2173{
2174 if (!offset)
2175 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2176 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2177}
2178
2179static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2180{
2181 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2182 struct b43_phy *phy = &dev->phy;
2183
2184 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2185 0x1F };
2186 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2187
2188 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2189 u8 ntab7_138_146[] = { 0x11, 0x11 };
2190 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2191
2192 u16 lpf_20, lpf_40, lpf_11b;
2193 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2194 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2195 bool rccal_ovrd = false;
2196
2197 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2198 u16 bias, conv, filt;
2199
2200 u32 tmp32;
2201 u8 core;
2202
2203 if (phy->rev == 7) {
2204 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2205 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2206 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2207 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2208 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2209 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2210 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2211 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2212 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2213 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2214 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2215 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2216 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2217 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2218 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2219 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2220 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2221 }
2222 if (phy->rev <= 8) {
04519dc6
RM		 2223 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2224 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2225 }
2226 if (phy->rev >= 8)
2227 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2228
2229 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2230 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2231 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2232 tmp32 &= 0xffffff;
2233 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2234 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2235 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2236
2237 if (b43_nphy_ipa(dev))
2238 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2239 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2240
04519dc6
RM		 2241 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2242 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2243
2244 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2245 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2246 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2247 if (b43_nphy_ipa(dev)) {
2248 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2249 phy->radio_rev == 7 || phy->radio_rev == 8) {
2250 bcap_val = b43_radio_read(dev, 0x16b);
2251 scap_val = b43_radio_read(dev, 0x16a);
2252 scap_val_11b = scap_val;
2253 bcap_val_11b = bcap_val;
2254 if (phy->radio_rev == 5 && phy->is_40mhz) {
2255 scap_val_11n_20 = scap_val;
2256 bcap_val_11n_20 = bcap_val;
2257 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2258 rccal_ovrd = true;
2259 } else { /* Rev 7/8 */
2260 lpf_20 = 4;
2261 lpf_11b = 1;
2262 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2263 scap_val_11n_20 = 0xc;
2264 bcap_val_11n_20 = 0xc;
2265 scap_val_11n_40 = 0xa;
2266 bcap_val_11n_40 = 0xa;
2267 } else {
2268 scap_val_11n_20 = 0x14;
2269 bcap_val_11n_20 = 0x14;
2270 scap_val_11n_40 = 0xf;
2271 bcap_val_11n_40 = 0xf;
2272 }
2273 rccal_ovrd = true;
2274 }
2275 }
2276 } else {
2277 if (phy->radio_rev == 5) {
2278 lpf_20 = 1;
2279 lpf_40 = 3;
2280 bcap_val = b43_radio_read(dev, 0x16b);
2281 scap_val = b43_radio_read(dev, 0x16a);
2282 scap_val_11b = scap_val;
2283 bcap_val_11b = bcap_val;
2284 scap_val_11n_20 = 0x11;
2285 scap_val_11n_40 = 0x11;
2286 bcap_val_11n_20 = 0x13;
2287 bcap_val_11n_40 = 0x13;
2288 rccal_ovrd = true;
2289 }
2290 }
2291 if (rccal_ovrd) {
2292 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2293 (scap_val_11b << 3) |
2294 lpf_11b;
2295 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2296 (scap_val_11n_20 << 3) |
2297 lpf_20;
2298 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2299 (scap_val_11n_40 << 3) |
2300 lpf_40;
2301 for (core = 0; core < 2; core++) {
2302 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2303 rx2tx_lut_20_11b);
2304 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2305 rx2tx_lut_20_11n);
2306 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2307 rx2tx_lut_20_11n);
2308 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2309 rx2tx_lut_40_11n);
2310 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2311 rx2tx_lut_40_11n);
2312 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2313 rx2tx_lut_40_11n);
2314 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2315 rx2tx_lut_40_11n);
2316 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2317 rx2tx_lut_40_11n);
2318 }
78ae7532 2319 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2320 }
2321 b43_phy_write(dev, 0x32F, 0x3);
2322 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2323 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2324
2325 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2326 if (sprom->revision &&
2327 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2328 b43_radio_write(dev, 0x5, 0x05);
2329 b43_radio_write(dev, 0x6, 0x30);
2330 b43_radio_write(dev, 0x7, 0x00);
2331 b43_radio_set(dev, 0x4f, 0x1);
2332 b43_radio_set(dev, 0xd4, 0x1);
2333 bias = 0x1f;
2334 conv = 0x6f;
2335 filt = 0xaa;
2336 } else {
2337 bias = 0x2b;
2338 conv = 0x7f;
2339 filt = 0xee;
2340 }
2341 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2342 for (core = 0; core < 2; core++) {
2343 if (core == 0) {
2344 b43_radio_write(dev, 0x5F, bias);
2345 b43_radio_write(dev, 0x64, conv);
2346 b43_radio_write(dev, 0x66, filt);
2347 } else {
2348 b43_radio_write(dev, 0xE8, bias);
2349 b43_radio_write(dev, 0xE9, conv);
2350 b43_radio_write(dev, 0xEB, filt);
2351 }
2352 }
2353 }
2354 }
2355
2356 if (b43_nphy_ipa(dev)) {
2357 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2358 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2359 phy->radio_rev == 6) {
2360 for (core = 0; core < 2; core++) {
2361 if (core == 0)
2362 b43_radio_write(dev, 0x51,
2363 0x7f);
2364 else
2365 b43_radio_write(dev, 0xd6,
2366 0x7f);
2367 }
2368 }
2369 if (phy->radio_rev == 3) {
2370 for (core = 0; core < 2; core++) {
2371 if (core == 0) {
2372 b43_radio_write(dev, 0x64,
2373 0x13);
2374 b43_radio_write(dev, 0x5F,
2375 0x1F);
2376 b43_radio_write(dev, 0x66,
2377 0xEE);
2378 b43_radio_write(dev, 0x59,
2379 0x8A);
2380 b43_radio_write(dev, 0x80,
2381 0x3E);
2382 } else {
2383 b43_radio_write(dev, 0x69,
2384 0x13);
2385 b43_radio_write(dev, 0xE8,
2386 0x1F);
2387 b43_radio_write(dev, 0xEB,
2388 0xEE);
2389 b43_radio_write(dev, 0xDE,
2390 0x8A);
2391 b43_radio_write(dev, 0x105,
2392 0x3E);
2393 }
2394 }
2395 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2396 if (!phy->is_40mhz) {
2397 b43_radio_write(dev, 0x5F, 0x14);
2398 b43_radio_write(dev, 0xE8, 0x12);
2399 } else {
2400 b43_radio_write(dev, 0x5F, 0x16);
2401 b43_radio_write(dev, 0xE8, 0x16);
2402 }
2403 }
2404 } else {
2405 u16 freq = phy->channel_freq;
2406 if ((freq >= 5180 && freq <= 5230) ||
2407 (freq >= 5745 && freq <= 5805)) {
2408 b43_radio_write(dev, 0x7D, 0xFF);
2409 b43_radio_write(dev, 0xFE, 0xFF);
2410 }
2411 }
2412 } else {
2413 if (phy->radio_rev != 5) {
2414 for (core = 0; core < 2; core++) {
2415 if (core == 0) {
2416 b43_radio_write(dev, 0x5c, 0x61);
2417 b43_radio_write(dev, 0x51, 0x70);
2418 } else {
2419 b43_radio_write(dev, 0xe1, 0x61);
2420 b43_radio_write(dev, 0xd6, 0x70);
2421 }
2422 }
2423 }
2424 }
2425
2426 if (phy->radio_rev == 4) {
2427 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2428 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2429 for (core = 0; core < 2; core++) {
2430 if (core == 0) {
2431 b43_radio_write(dev, 0x1a1, 0x00);
2432 b43_radio_write(dev, 0x1a2, 0x3f);
2433 b43_radio_write(dev, 0x1a6, 0x3f);
2434 } else {
2435 b43_radio_write(dev, 0x1a7, 0x00);
2436 b43_radio_write(dev, 0x1ab, 0x3f);
2437 b43_radio_write(dev, 0x1ac, 0x3f);
2438 }
2439 }
2440 } else {
2441 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2442 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2443 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2444 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2445
2446 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2447 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2448 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2449 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2450 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2451 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2452
2453 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2454 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2455 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2456 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2457 }
2458
2459 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2460
2461 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2462 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2463 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2464 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2465 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2466 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2467 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2468
2469 if (!phy->is_40mhz) {
2470 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2471 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2472 } else {
2473 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2474 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2475 }
2476
2477 b43_nphy_gain_ctl_workarounds(dev);
2478
2479 /* TODO
2480 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2481 aux_adc_vmid_rev7_core0);
2482 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2483 aux_adc_vmid_rev7_core1);
2484 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2485 aux_adc_gain_rev7);
2486 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2487 aux_adc_gain_rev7);
2488 */
2489}
2490
73d07a39 2491static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2492{
0eff8fcd 2493 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2494 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2495
0eff8fcd 2496 /* TX to RX */
c378bb97
RM		 2497 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2498 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2499 /* RX to TX */
2500 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2501 0x1F };
2502 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2503 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2504 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2505
c378bb97
RM		 2506 u16 vmids[5][4] = {
2507 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2508 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2509 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2510 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2511 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2512 };
2513 u16 gains[5][4] = {
2514 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2515 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2516 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2517 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2518 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2519 };
2520 u16 *vmid, *gain;
2521
2522 u8 pdet_range;
ba9a6214
RM		 2523 u16 tmp16;
2524 u32 tmp32;
2525
04519dc6
RM		 2526 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2527 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2528
73d07a39
RM		 2529 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2530 tmp32 &= 0xffffff;
2531 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2532
73d07a39
RM		 2533 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2534 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2535 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2536 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2537 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2538 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2539
04519dc6
RM		 2540 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2541 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2542
0eff8fcd 2543 /* TX to RX */
c56da252
RM		 2544 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2545 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2546
2547 /* RX to TX */
2548 if (b43_nphy_ipa(dev))
c56da252
RM		 2549 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2550 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2551 if (nphy->hw_phyrxchain != 3 &&
2552 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2553 if (b43_nphy_ipa(dev)) {
2554 rx2tx_delays[5] = 59;
2555 rx2tx_delays[6] = 1;
2556 rx2tx_events[7] = 0x1F;
2557 }
fa0f2b38 2558 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2559 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2560 }
ba9a6214 2561
73d07a39
RM		 2562 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2563 0x2 : 0x9C40;
2564 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2565
04519dc6 2566 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2567
fa0f2b38
RM		 2568 if (!dev->phy.is_40mhz) {
2569 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2570 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2571 } else {
2572 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2573 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2574 }
ba9a6214 2575
3ccd0957 2576 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2577
c56da252
RM		 2578 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2579 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2580
c378bb97
RM		 2581 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2582 pdet_range = sprom->fem.ghz2.pdet_range;
2583 else
2584 pdet_range = sprom->fem.ghz5.pdet_range;
2585 vmid = vmids[min_t(u16, pdet_range, 4)];
2586 gain = gains[min_t(u16, pdet_range, 4)];
2587 switch (pdet_range) {
2588 case 3:
2589 if (!(dev->phy.rev >= 4 &&
2590 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2591 break;
2592 /* FALL THROUGH */
2593 case 0:
2594 case 1:
2595 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2596 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2597 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2598 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2599 break;
2600 case 2:
2601 if (dev->phy.rev >= 6) {
2602 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2603 vmid[3] = 0x94;
2604 else
2605 vmid[3] = 0x8e;
2606 gain[3] = 3;
2607 } else if (dev->phy.rev == 5) {
2608 vmid[3] = 0x84;
2609 gain[3] = 2;
2610 }
2611 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2612 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2613 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2614 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2615 break;
2616 case 4:
2617 case 5:
2618 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2619 if (pdet_range == 4) {
2620 vmid[3] = 0x8e;
2621 tmp16 = 0x96;
2622 gain[3] = 0x2;
2623 } else {
2624 vmid[3] = 0x89;
2625 tmp16 = 0x89;
2626 gain[3] = 0;
2627 }
2628 } else {
2629 if (pdet_range == 4) {
2630 vmid[3] = 0x89;
2631 tmp16 = 0x8b;
2632 gain[3] = 0x2;
2633 } else {
2634 vmid[3] = 0x74;
2635 tmp16 = 0x70;
2636 gain[3] = 0;
2637 }
2638 }
2639 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2640 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2641 vmid[3] = tmp16;
2642 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2643 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2644 break;
2645 }
ba9a6214 2646
73d07a39
RM		 2647 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2648 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2649 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2650 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2651 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2652 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2653 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2654 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2655 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2656 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2657 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2658 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2659
2660 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2661
2662 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2663 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2664 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2665 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2666 tmp32 = 0x00088888;
2667 else
2668 tmp32 = 0x88888888;
2669 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2670 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2671 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2672
2673 if (dev->phy.rev == 4 &&
fa0f2b38 2674 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2675 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2676 0x70);
2677 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2678 0x70);
2679 }
ba9a6214 2680
fa0f2b38 2681 /* Dropped probably-always-true condition */
04519dc6
RM		 2682 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2683 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2684 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2685 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2686 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2687 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2688 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2689 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2690 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2691 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2692 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2693 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2694
2695 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2696 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2697}
ba9a6214 2698
73d07a39
RM		 2699static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2700{
2701 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2702 struct b43_phy *phy = &dev->phy;
2703 struct b43_phy_n *nphy = phy->n;
ba9a6214 2704
73d07a39
RM		 2705 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2706 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2707
73d07a39
RM		 2708 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2709 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2710
fa0f2b38 2711 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2712 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2713 delays1[0] = 0x1;
2714 delays1[5] = 0x14;
2715 }
2716
73d07a39
RM		 2717 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2718 nphy->band5g_pwrgain) {
2719 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2720 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2721 } else {
73d07a39
RM		 2722 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2723 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2724 }
28fd7daa 2725
73d07a39
RM		 2726 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2727 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2728 if (dev->phy.rev < 3) {
2729 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2730 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2731 }
73d07a39
RM		 2732
2733 if (dev->phy.rev < 2) {
2734 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2735 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2736 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2737 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2738 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2739 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2740 }
28fd7daa 2741
73d07a39
RM		 2742 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2743 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2744 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2745 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2746
73d07a39
RM		 2747 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2748 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2749
3ccd0957 2750 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2751
2752 if (dev->phy.rev < 2) {
2753 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2754 b43_hf_write(dev, b43_hf_read(dev) |
2755 B43_HF_MLADVW);
2756 } else if (dev->phy.rev == 2) {
2757 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2758 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2759 }
28fd7daa 2760
73d07a39
RM		 2761 if (dev->phy.rev < 2)
2762 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2763 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2764
2765 /* Set phase track alpha and beta */
2766 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2767 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2768 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2769 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2770 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2771 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2772
fa0f2b38
RM		 2773 if (dev->phy.rev < 3) {
2774 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2775 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2776 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2777 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2778 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2779 }
73d07a39
RM		 2780
2781 if (dev->phy.rev == 2)
2782 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2783 B43_NPHY_FINERX2_CGC_DECGC);
2784}
28fd7daa 2785
73d07a39
RM		 2786/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2787static void b43_nphy_workarounds(struct b43_wldev *dev)
2788{
2789 struct b43_phy *phy = &dev->phy;
2790 struct b43_phy_n *nphy = phy->n;
28fd7daa 2791
73d07a39
RM		 2792 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2793 b43_nphy_classifier(dev, 1, 0);
2794 else
2795 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2796
73d07a39
RM		 2797 if (nphy->hang_avoid)
2798 b43_nphy_stay_in_carrier_search(dev, 1);
2799
2800 b43_phy_set(dev, B43_NPHY_IQFLIP,
2801 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2802
d11d354b
RM		 2803 if (dev->phy.rev >= 7)
2804 b43_nphy_workarounds_rev7plus(dev);
2805 else if (dev->phy.rev >= 3)
73d07a39
RM		 2806 b43_nphy_workarounds_rev3plus(dev);
2807 else
2808 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2809
2810 if (nphy->hang_avoid)
2811 b43_nphy_stay_in_carrier_search(dev, 0);
2812}
2813
9dd4d9b9
RM		 2814/**************************************************
2815 * Tx/Rx common
2816 **************************************************/
2817
2818/*
2819 * Transmits a known value for LO calibration
2820 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2821 */
2822static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2823 bool iqmode, bool dac_test)
2824{
2825 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2826 if (samp == 0)
2827 return -1;
2828 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2829 return 0;
2830}
2831
2832/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2833static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2834{
2835 struct b43_phy_n *nphy = dev->phy.n;
2836
2837 bool override = false;
2838 u16 chain = 0x33;
2839
2840 if (nphy->txrx_chain == 0) {
2841 chain = 0x11;
2842 override = true;
2843 } else if (nphy->txrx_chain == 1) {
2844 chain = 0x22;
2845 override = true;
2846 }
2847
2848 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2849 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2850 chain);
2851
2852 if (override)
2853 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2854 B43_NPHY_RFSEQMODE_CAOVER);
2855 else
2856 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2857 ~B43_NPHY_RFSEQMODE_CAOVER);
2858}
2859
2860/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2861static void b43_nphy_stop_playback(struct b43_wldev *dev)
2862{
2863 struct b43_phy_n *nphy = dev->phy.n;
2864 u16 tmp;
2865
2866 if (nphy->hang_avoid)
2867 b43_nphy_stay_in_carrier_search(dev, 1);
2868
2869 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2870 if (tmp & 0x1)
2871 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2872 else if (tmp & 0x2)
2873 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2874
2875 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2876
2877 if (nphy->bb_mult_save & 0x80000000) {
2878 tmp = nphy->bb_mult_save & 0xFFFF;
2879 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2880 nphy->bb_mult_save = 0;
2881 }
2882
2883 if (nphy->hang_avoid)
2884 b43_nphy_stay_in_carrier_search(dev, 0);
2885}
2886
2887/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2888static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2889 struct nphy_txgains target,
2890 struct nphy_iqcal_params *params)
2891{
2892 int i, j, indx;
2893 u16 gain;
2894
2895 if (dev->phy.rev >= 3) {
2896 params->txgm = target.txgm[core];
2897 params->pga = target.pga[core];
2898 params->pad = target.pad[core];
2899 params->ipa = target.ipa[core];
2900 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2901 (params->pad << 4) | (params->ipa);
2902 for (j = 0; j < 5; j++)
2903 params->ncorr[j] = 0x79;
2904 } else {
2905 gain = (target.pad[core]) | (target.pga[core] << 4) |
2906 (target.txgm[core] << 8);
2907
2908 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2909 1 : 0;
2910 for (i = 0; i < 9; i++)
2911 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2912 break;
2913 i = min(i, 8);
2914
2915 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2916 params->pga = tbl_iqcal_gainparams[indx][i][2];
2917 params->pad = tbl_iqcal_gainparams[indx][i][3];
2918 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2919 (params->pad << 2);
2920 for (j = 0; j < 4; j++)
2921 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2922 }
2923}
2924
884a5228 2925/**************************************************
104cfa88 2926 * Tx and Rx
884a5228 2927 **************************************************/
5f6393ec 2928
884a5228
RM		 2929static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2930{//TODO
2931}
59af099b 2932
884a5228
RM		 2933static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2934 bool ignore_tssi)
2935{//TODO
2936 return B43_TXPWR_RES_DONE;
2937}
59af099b 2938
161d540c
RM		 2939/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2940static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2941{
2942 struct b43_phy_n *nphy = dev->phy.n;
2943 u8 i;
c9c0d9ec
RM		 2944 u16 bmask, val, tmp;
2945 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 2946
161d540c
RM		 2947 if (nphy->hang_avoid)
2948 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 2949
161d540c
RM		 2950 nphy->txpwrctrl = enable;
2951 if (!enable) {
c9c0d9ec
RM		 2952 if (dev->phy.rev >= 3 &&
2953 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2954 (B43_NPHY_TXPCTL_CMD_COEFF |
2955 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2956 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2957 /* We disable enabled TX pwr ctl, save it's state */
2958 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2959 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2960 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2961 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2962 }
59af099b 2963
161d540c
RM		 2964 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2965 for (i = 0; i < 84; i++)
2966 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2967
161d540c
RM		 2968 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2969 for (i = 0; i < 84; i++)
2970 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 2971
161d540c
RM		 2972 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2973 if (dev->phy.rev >= 3)
2974 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2975 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 2976
161d540c
RM		 2977 if (dev->phy.rev >= 3) {
2978 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2979 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2980 } else {
2981 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2982 }
10a79873 2983
161d540c
RM		 2984 if (dev->phy.rev == 2)
2985 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2986 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2987 else if (dev->phy.rev < 2)
2988 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2989 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 2990
c9c0d9ec
RM		 2991 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2992 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 2993 } else {
c9c0d9ec
RM		 2994 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2995 nphy->adj_pwr_tbl);
2996 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2997 nphy->adj_pwr_tbl);
10a79873 2998
c9c0d9ec
RM		 2999 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3000 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3001 /* wl does useless check for "enable" param here */
3002 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3003 if (dev->phy.rev >= 3) {
3004 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3005 if (val)
3006 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3007 }
3008 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3009
c9c0d9ec
RM		 3010 if (band == IEEE80211_BAND_5GHZ) {
3011 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3012 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3013 if (dev->phy.rev > 1)
3014 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3015 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3016 0x64);
3017 }
10a79873 3018
c9c0d9ec
RM		 3019 if (dev->phy.rev >= 3) {
3020 if (nphy->tx_pwr_idx[0] != 128 &&
3021 nphy->tx_pwr_idx[1] != 128) {
3022 /* Recover TX pwr ctl state */
3023 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3024 ~B43_NPHY_TXPCTL_CMD_INIT,
3025 nphy->tx_pwr_idx[0]);
3026 if (dev->phy.rev > 1)
3027 b43_phy_maskset(dev,
3028 B43_NPHY_TXPCTL_INIT,
3029 ~0xff, nphy->tx_pwr_idx[1]);
3030 }
3031 }
10a79873 3032
c9c0d9ec
RM		 3033 if (dev->phy.rev >= 3) {
3034 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3035 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3036 } else {
3037 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3038 }
10a79873 3039
c9c0d9ec
RM		 3040 if (dev->phy.rev == 2)
3041 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3042 else if (dev->phy.rev < 2)
3043 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3044
c9c0d9ec
RM		 3045 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3046 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3047
c002831a 3048 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3049 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3050 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3051 }
10a79873 3052 }
10a79873 3053
161d540c
RM		 3054 if (nphy->hang_avoid)
3055 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3056}
3057
161d540c 3058/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3059static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 3060{
3061 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3062 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3063
161d540c
RM		 3064 u8 txpi[2], bbmult, i;
3065 u16 tmp, radio_gain, dac_gain;
3066 u16 freq = dev->phy.channel_freq;
3067 u32 txgain;
3068 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3069
3070 if (nphy->hang_avoid)
161d540c 3071 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3072
dd5f13b8
RM		 3073 if (dev->phy.rev >= 7) {
3074 txpi[0] = txpi[1] = 30;
3075 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3076 txpi[0] = 40;
3077 txpi[1] = 40;
3078 } else if (sprom->revision < 4) {
3079 txpi[0] = 72;
3080 txpi[1] = 72;
3081 } else {
3082 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3083 txpi[0] = sprom->txpid2g[0];
3084 txpi[1] = sprom->txpid2g[1];
3085 } else if (freq >= 4900 && freq < 5100) {
3086 txpi[0] = sprom->txpid5gl[0];
3087 txpi[1] = sprom->txpid5gl[1];
3088 } else if (freq >= 5100 && freq < 5500) {
3089 txpi[0] = sprom->txpid5g[0];
3090 txpi[1] = sprom->txpid5g[1];
3091 } else if (freq >= 5500) {
3092 txpi[0] = sprom->txpid5gh[0];
3093 txpi[1] = sprom->txpid5gh[1];
3094 } else {
3095 txpi[0] = 91;
3096 txpi[1] = 91;
6dcd9d91
RM		 3097 }
3098 }
dd5f13b8 3099 if (dev->phy.rev < 7 &&
9bd28571 3100 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3101 txpi[0] = txpi[1] = 91;
6dcd9d91 3102
161d540c
RM		 3103 /*
3104 for (i = 0; i < 2; i++) {
3105 nphy->txpwrindex[i].index_internal = txpi[i];
3106 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3107 }
161d540c 3108 */
75377b24 3109
161d540c 3110 for (i = 0; i < 2; i++) {
aeab5751
RM		 3111 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3112
3113 if (dev->phy.rev >= 3)
161d540c 3114 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3115 else
161d540c 3116 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3117
dd5f13b8
RM		 3118 if (dev->phy.rev >= 7)
3119 dac_gain = (txgain >> 8) & 0x7;
3120 else
3121 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3122 bbmult = txgain & 0xFF;
75377b24 3123
161d540c
RM		 3124 if (dev->phy.rev >= 3) {
3125 if (i == 0)
3126 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3127 else
3128 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3129 } else {
3130 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3131 }
75377b24 3132
161d540c
RM		 3133 if (i == 0)
3134 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3135 else
3136 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3137
44f4008b 3138 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3139
44f4008b 3140 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3141 if (i == 0)
3142 tmp = (tmp & 0x00FF) | (bbmult << 8);
3143 else
3144 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3145 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3146
0eff8fcd
RM		 3147 if (b43_nphy_ipa(dev)) {
3148 u32 tmp32;
3149 u16 reg = (i == 0) ?
3150 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3151 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3152 576 + txpi[i]));
0eff8fcd
RM		 3153 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3154 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3155 }
3156 }
75377b24 3157
161d540c 3158 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3159
161d540c
RM		 3160 if (nphy->hang_avoid)
3161 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3162}
67cbc3ed 3163
3dda07b6
RM		 3164static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3165{
3166 struct b43_phy *phy = &dev->phy;
3167
3168 u8 core;
3169 u16 r; /* routing */
3170
3171 if (phy->rev >= 7) {
3172 for (core = 0; core < 2; core++) {
3173 r = core ? 0x190 : 0x170;
3174 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3175 b43_radio_write(dev, r + 0x5, 0x5);
3176 b43_radio_write(dev, r + 0x9, 0xE);
3177 if (phy->rev != 5)
3178 b43_radio_write(dev, r + 0xA, 0);
3179 if (phy->rev != 7)
3180 b43_radio_write(dev, r + 0xB, 1);
3181 else
3182 b43_radio_write(dev, r + 0xB, 0x31);
3183 } else {
3184 b43_radio_write(dev, r + 0x5, 0x9);
3185 b43_radio_write(dev, r + 0x9, 0xC);
3186 b43_radio_write(dev, r + 0xB, 0x0);
3187 if (phy->rev != 5)
3188 b43_radio_write(dev, r + 0xA, 1);
3189 else
3190 b43_radio_write(dev, r + 0xA, 0x31);
3191 }
3192 b43_radio_write(dev, r + 0x6, 0);
3193 b43_radio_write(dev, r + 0x7, 0);
3194 b43_radio_write(dev, r + 0x8, 3);
3195 b43_radio_write(dev, r + 0xC, 0);
3196 }
3197 } else {
3198 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3199 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3200 else
3201 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3202 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3203 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3204
3205 for (core = 0; core < 2; core++) {
3206 r = core ? B2056_TX1 : B2056_TX0;
3207
3208 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3209 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3210 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3211 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3212 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3213 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3214 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3215 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3216 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3217 0x5);
3218 if (phy->rev != 5)
3219 b43_radio_write(dev, r | B2056_TX_TSSIA,
3220 0x00);
3221 if (phy->rev >= 5)
3222 b43_radio_write(dev, r | B2056_TX_TSSIG,
3223 0x31);
3224 else
3225 b43_radio_write(dev, r | B2056_TX_TSSIG,
3226 0x11);
3227 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3228 0xE);
3229 } else {
3230 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3231 0x9);
3232 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3233 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3234 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3235 0xC);
3236 }
3237 }
3238 }
3239}
3240
3241/*
3242 * Stop radio and transmit known signal. Then check received signal strength to
3243 * get TSSI (Transmit Signal Strength Indicator).
3244 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3245 */
3246static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3247{
3248 struct b43_phy *phy = &dev->phy;
3249 struct b43_phy_n *nphy = dev->phy.n;
3250
3251 u32 tmp;
3252 s32 rssi[4] = { };
3253
3254 /* TODO: check if we can transmit */
3255
3256 if (b43_nphy_ipa(dev))
3257 b43_nphy_ipa_internal_tssi_setup(dev);
3258
3259 if (phy->rev >= 7)
78ae7532 3260 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3261 else if (phy->rev >= 3)
78ae7532 3262 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3263
3264 b43_nphy_stop_playback(dev);
3265 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3266 udelay(20);
a3764ef7 3267 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3268 b43_nphy_stop_playback(dev);
a3764ef7 3269 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3270
3271 if (phy->rev >= 7)
78ae7532 3272 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3273 else if (phy->rev >= 3)
78ae7532 3274 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3275
3276 if (phy->rev >= 3) {
3277 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3278 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3279 } else {
3280 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3281 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3282 }
3283 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3284 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3285}
3286
d3fd8bf7
RM		 3287/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3288static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3289{
3290 struct b43_phy_n *nphy = dev->phy.n;
3291
3292 u8 idx, delta;
3293 u8 i, stf_mode;
3294
3295 for (i = 0; i < 4; i++)
3296 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3297
3298 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3299 delta = 0;
3300 switch (stf_mode) {
3301 case 0:
3302 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3303 idx = 68;
3304 } else {
3305 delta = 1;
3306 idx = dev->phy.is_40mhz ? 52 : 4;
3307 }
3308 break;
3309 case 1:
3310 idx = dev->phy.is_40mhz ? 76 : 28;
3311 break;
3312 case 2:
3313 idx = dev->phy.is_40mhz ? 84 : 36;
3314 break;
3315 case 3:
3316 idx = dev->phy.is_40mhz ? 92 : 44;
3317 break;
3318 }
3319
3320 for (i = 0; i < 20; i++) {
3321 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3322 nphy->tx_power_offset[idx];
3323 if (i == 0)
3324 idx += delta;
3325 if (i == 14)
3326 idx += 1 - delta;
3327 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3328 i == 13)
3329 idx += 1;
3330 }
3331 }
3332}
3333
3334/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3335static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3336{
3337 struct b43_phy_n *nphy = dev->phy.n;
3338 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3339
3340 s16 a1[2], b0[2], b1[2];
3341 u8 idle[2];
3342 s8 target[2];
3343 s32 num, den, pwr;
3344 u32 regval[64];
3345
3346 u16 freq = dev->phy.channel_freq;
3347 u16 tmp;
3348 u16 r; /* routing */
3349 u8 i, c;
3350
3351 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3352 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3353 b43_read32(dev, B43_MMIO_MACCTL);
3354 udelay(1);
3355 }
3356
3357 if (nphy->hang_avoid)
3358 b43_nphy_stay_in_carrier_search(dev, true);
3359
3360 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3361 if (dev->phy.rev >= 3)
3362 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3363 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3364 else
3365 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3366 B43_NPHY_TXPCTL_CMD_PCTLEN);
3367
3368 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3369 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3370
3371 if (sprom->revision < 4) {
3372 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3373 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3374 target[0] = target[1] = 52;
3375 a1[0] = a1[1] = -424;
3376 b0[0] = b0[1] = 5612;
3377 b1[0] = b1[1] = -1393;
3378 } else {
3379 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3380 for (c = 0; c < 2; c++) {
3381 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3382 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3383 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3384 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3385 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3386 }
3387 } else if (freq >= 4900 && freq < 5100) {
3388 for (c = 0; c < 2; c++) {
3389 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3390 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3391 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3392 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3393 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3394 }
3395 } else if (freq >= 5100 && freq < 5500) {
3396 for (c = 0; c < 2; c++) {
3397 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3398 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3399 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3400 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3401 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3402 }
3403 } else if (freq >= 5500) {
3404 for (c = 0; c < 2; c++) {
3405 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3406 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3407 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3408 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3409 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3410 }
3411 } else {
3412 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3413 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3414 target[0] = target[1] = 52;
3415 a1[0] = a1[1] = -424;
3416 b0[0] = b0[1] = 5612;
3417 b1[0] = b1[1] = -1393;
3418 }
3419 }
3420 /* target[0] = target[1] = nphy->tx_power_max; */
3421
3422 if (dev->phy.rev >= 3) {
3423 if (sprom->fem.ghz2.tssipos)
3424 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3425 if (dev->phy.rev >= 7) {
3426 for (c = 0; c < 2; c++) {
3427 r = c ? 0x190 : 0x170;
3428 if (b43_nphy_ipa(dev))
3429 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3430 }
3431 } else {
3432 if (b43_nphy_ipa(dev)) {
3433 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3434 b43_radio_write(dev,
3435 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3436 b43_radio_write(dev,
3437 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3438 } else {
3439 b43_radio_write(dev,
3440 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3441 b43_radio_write(dev,
3442 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3443 }
3444 }
3445 }
3446
3447 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3448 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3449 b43_read32(dev, B43_MMIO_MACCTL);
3450 udelay(1);
3451 }
3452
3453 if (dev->phy.rev >= 7) {
3454 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3455 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3456 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3457 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3458 } else {
3459 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3460 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3461 if (dev->phy.rev > 1)
3462 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3463 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3464 }
3465
3466 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3467 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3468
3469 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3470 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3471 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3472 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3473 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3474 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3475 B43_NPHY_TXPCTL_ITSSI_BINF);
3476 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3477 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3478 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3479
3480 for (c = 0; c < 2; c++) {
3481 for (i = 0; i < 64; i++) {
3482 num = 8 * (16 * b0[c] + b1[c] * i);
3483 den = 32768 + a1[c] * i;
3484 pwr = max((4 * num + den / 2) / den, -8);
3485 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3486 pwr = max(pwr, target[c] + 1);
3487 regval[i] = pwr;
3488 }
3489 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3490 }
3491
3492 b43_nphy_tx_prepare_adjusted_power_table(dev);
3493 /*
3494 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3495 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
3496 */
3497
3498 if (nphy->hang_avoid)
3499 b43_nphy_stay_in_carrier_search(dev, false);
3500}
3501
0eff8fcd
RM		 3502static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3503{
3504 struct b43_phy *phy = &dev->phy;
67cbc3ed 3505
0eff8fcd 3506 const u32 *table = NULL;
0eff8fcd
RM		 3507 u32 rfpwr_offset;
3508 u8 pga_gain;
3509 int i;
0eff8fcd 3510
aeab5751 3511 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3512 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3513 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3514
3515 if (phy->rev >= 3) {
3516#if 0
3517 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3518#endif
0eff8fcd
RM		 3519
3520 for (i = 0; i < 128; i++) {
3521 pga_gain = (table[i] >> 24) & 0xF;
3522 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3523 rfpwr_offset =
3524 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3525 else
34c5cf20
RM		 3526 rfpwr_offset =
3527 0; /* FIXME */
0eff8fcd
RM		 3528 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3529 rfpwr_offset);
3530 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3531 rfpwr_offset);
3532 }
67cbc3ed
RM		 3533 }
3534}
3535
e50cbcf6
RM		 3536/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3537static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3538{
e50cbcf6
RM		 3539 struct b43_phy_n *nphy = dev->phy.n;
3540 enum ieee80211_band band;
3541 u16 tmp;
95b66bad 3542
e50cbcf6
RM		 3543 if (!enable) {
3544 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3545 B43_NPHY_RFCTL_INTC1);
3546 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3547 B43_NPHY_RFCTL_INTC2);
3548 band = b43_current_band(dev->wl);
3549 if (dev->phy.rev >= 3) {
3550 if (band == IEEE80211_BAND_5GHZ)
3551 tmp = 0x600;
3552 else
3553 tmp = 0x480;
3554 } else {
3555 if (band == IEEE80211_BAND_5GHZ)
3556 tmp = 0x180;
3557 else
3558 tmp = 0x120;
3559 }
3560 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3561 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3562 } else {
3563 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3564 nphy->rfctrl_intc1_save);
3565 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3566 nphy->rfctrl_intc2_save);
95b66bad 3567 }
95b66bad
MB		 3568}
3569
fe3e46e8
RM		 3570/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3571static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3572{
3573 u16 tmp;
3c95627d 3574
fe3e46e8 3575 if (dev->phy.rev >= 3) {
c002831a 3576 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3577 tmp = 4;
3578 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3579 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3580 }
76b002bd 3581
fe3e46e8
RM		 3582 tmp = 1;
3583 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3584 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3585 }
3586}
76b002bd 3587
2faa6b83
RM		 3588/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3589static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3590 u16 samps, u8 time, bool wait)
3c95627d 3591{
2faa6b83
RM		 3592 int i;
3593 u16 tmp;
3c95627d 3594
2faa6b83
RM		 3595 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3596 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3597 if (wait)
3598 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3599 else
2faa6b83 3600 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3601
2faa6b83 3602 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3603
2faa6b83
RM		 3604 for (i = 1000; i; i--) {
3605 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3606 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3607 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3608 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3609 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3610 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3611 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3612 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3613
2faa6b83
RM		 3614 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3615 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3616 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3617 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3618 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3619 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3620 return;
3c95627d 3621 }
2faa6b83 3622 udelay(10);
3c95627d 3623 }
2faa6b83 3624 memset(est, 0, sizeof(*est));
3c95627d
RM		 3625}
3626
a67162ab
RM		 3627/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3628static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3629 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3630{
a67162ab
RM		 3631 if (write) {
3632 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3633 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3634 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3635 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3636 } else {
a67162ab
RM		 3637 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3638 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3639 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3640 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3641 }
3642}
6e3b15a9 3643
c7455cf9
RM		 3644#if 0
3645/* Ready but not used anywhere */
026816fc
RM		 3646/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3647static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3648{
3649 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3650
026816fc
RM		 3651 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3652 if (core == 0) {
3653 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3654 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3655 } else {
3656 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3657 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3658 }
3659 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3660 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3661 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3662 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3663 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3664 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3665 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3666 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3667}
6e3b15a9 3668
026816fc
RM		 3669/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3670static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3671{
3672 u8 rxval, txval;
3673 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3674
026816fc
RM		 3675 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3676 if (core == 0) {
3677 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3678 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3679 } else {
3680 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3681 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3682 }
3683 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3684 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3685 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3686 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3687 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3688 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3689 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3690 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3691
026816fc
RM		 3692 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3693 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3694
acd82aa8
LF		 3695 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3696 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3697 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3698 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3699 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3700 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3701 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3702 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3703 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3704
026816fc
RM		 3705 if (core == 0) {
3706 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3707 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3708 } else {
3709 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3710 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3711 }
6e3b15a9 3712
89e43dad 3713 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3714 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3715 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3716
026816fc
RM		 3717 if (core == 0) {
3718 rxval = 1;
3719 txval = 8;
3720 } else {
3721 rxval = 4;
3722 txval = 2;
6e3b15a9 3723 }
89e43dad
RM		 3724 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3725 core + 1);
3726 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3727 2 - core);
99b82c41 3728}
c7455cf9 3729#endif
99b82c41 3730
34a56f2c
RM		 3731/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3732static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3733{
3734 int i;
34a56f2c
RM		 3735 s32 iq;
3736 u32 ii;
3737 u32 qq;
3738 int iq_nbits, qq_nbits;
3739 int arsh, brsh;
3740 u16 tmp, a, b;
3741
3742 struct nphy_iq_est est;
3743 struct b43_phy_n_iq_comp old;
3744 struct b43_phy_n_iq_comp new = { };
3745 bool error = false;
3746
3747 if (mask == 0)
3748 return;
3749
3750 b43_nphy_rx_iq_coeffs(dev, false, &old);
3751 b43_nphy_rx_iq_coeffs(dev, true, &new);
3752 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3753 new = old;
3754
dfb4aa5d 3755 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3756 if (i == 0 && (mask & 1)) {
3757 iq = est.iq0_prod;
3758 ii = est.i0_pwr;
3759 qq = est.q0_pwr;
3760 } else if (i == 1 && (mask & 2)) {
3761 iq = est.iq1_prod;
3762 ii = est.i1_pwr;
3763 qq = est.q1_pwr;
dfb4aa5d 3764 } else {
34a56f2c 3765 continue;
dfb4aa5d 3766 }
dfb4aa5d 3767
34a56f2c
RM		 3768 if (ii + qq < 2) {
3769 error = true;
3770 break;
3771 }
dfb4aa5d 3772
34a56f2c
RM		 3773 iq_nbits = fls(abs(iq));
3774 qq_nbits = fls(qq);
dfb4aa5d 3775
34a56f2c
RM		 3776 arsh = iq_nbits - 20;
3777 if (arsh >= 0) {
3778 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3779 tmp = ii >> arsh;
3780 } else {
3781 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3782 tmp = ii << -arsh;
3783 }
3784 if (tmp == 0) {
3785 error = true;
3786 break;
3787 }
3788 a /= tmp;
dfb4aa5d 3789
34a56f2c
RM		 3790 brsh = qq_nbits - 11;
3791 if (brsh >= 0) {
3792 b = (qq << (31 - qq_nbits));
3793 tmp = ii >> brsh;
dfb4aa5d 3794 } else {
34a56f2c
RM		 3795 b = (qq << (31 - qq_nbits));
3796 tmp = ii << -brsh;
3797 }
3798 if (tmp == 0) {
3799 error = true;
3800 break;
dfb4aa5d 3801 }
34a56f2c 3802 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3803
34a56f2c
RM		 3804 if (i == 0 && (mask & 0x1)) {
3805 if (dev->phy.rev >= 3) {
3806 new.a0 = a & 0x3FF;
3807 new.b0 = b & 0x3FF;
3808 } else {
3809 new.a0 = b & 0x3FF;
3810 new.b0 = a & 0x3FF;
3811 }
3812 } else if (i == 1 && (mask & 0x2)) {
3813 if (dev->phy.rev >= 3) {
3814 new.a1 = a & 0x3FF;
3815 new.b1 = b & 0x3FF;
3816 } else {
3817 new.a1 = b & 0x3FF;
3818 new.b1 = a & 0x3FF;
3819 }
3820 }
dfb4aa5d 3821 }
dfb4aa5d 3822
34a56f2c
RM		 3823 if (error)
3824 new = old;
dfb4aa5d 3825
34a56f2c
RM		 3826 b43_nphy_rx_iq_coeffs(dev, true, &new);
3827}
dfb4aa5d 3828
09146400
RM		 3829/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3830static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3831{
3832 u16 array[4];
44f4008b 3833 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3834
3835 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3836 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3837 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3838 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3839}
3840
9442e5b5
RM		 3841/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3842static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3843{
3844 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3845
204a665b 3846 u8 channel = dev->phy.channel;
9442e5b5
RM		 3847 int tone[2] = { 57, 58 };
3848 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3849
9442e5b5 3850 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3851
9442e5b5
RM		 3852 if (nphy->hang_avoid)
3853 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3854
9442e5b5
RM		 3855 if (nphy->gband_spurwar_en) {
3856 /* TODO: N PHY Adjust Analog Pfbw (7) */
3857 if (channel == 11 && dev->phy.is_40mhz)
3858 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3859 else
3860 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3861 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 3862 }
3863
9442e5b5
RM		 3864 if (nphy->aband_spurwar_en) {
3865 if (channel == 54) {
3866 tone[0] = 0x20;
3867 noise[0] = 0x25F;
3868 } else if (channel == 38 || channel == 102 || channel == 118) {
3869 if (0 /* FIXME */) {
3870 tone[0] = 0x20;
3871 noise[0] = 0x21F;
3872 } else {
3873 tone[0] = 0;
3874 noise[0] = 0;
90b9738d 3875 }
9442e5b5
RM		 3876 } else if (channel == 134) {
3877 tone[0] = 0x20;
3878 noise[0] = 0x21F;
3879 } else if (channel == 151) {
3880 tone[0] = 0x10;
3881 noise[0] = 0x23F;
3882 } else if (channel == 153 || channel == 161) {
3883 tone[0] = 0x30;
3884 noise[0] = 0x23F;
3885 } else {
3886 tone[0] = 0;
3887 noise[0] = 0;
90b9738d 3888 }
90b9738d 3889
9442e5b5
RM		 3890 if (!tone[0] && !noise[0])
3891 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 3892 else
9442e5b5
RM		 3893 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3894 }
90b9738d 3895
9442e5b5
RM		 3896 if (nphy->hang_avoid)
3897 b43_nphy_stay_in_carrier_search(dev, 0);
3898}
90b9738d 3899
5ecab603
RM		 3900/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3901static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3902{
3903 struct b43_phy_n *nphy = dev->phy.n;
3904 int i, j;
3905 u32 tmp;
3906 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 3907
5ecab603 3908 u16 buffer[7];
90b9738d 3909
5ecab603
RM		 3910 if (nphy->hang_avoid)
3911 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 3912
5ecab603 3913 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 3914
5ecab603
RM		 3915 for (i = 0; i < 2; i++) {
3916 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3917 (buffer[i * 2 + 1] & 0x3FF);
3918 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3919 (((i + 26) << 10) | 320));
3920 for (j = 0; j < 128; j++) {
3921 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3922 ((tmp >> 16) & 0xFFFF));
3923 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3924 (tmp & 0xFFFF));
90b9738d 3925 }
90b9738d 3926 }
90b9738d 3927
5ecab603
RM		 3928 for (i = 0; i < 2; i++) {
3929 tmp = buffer[5 + i];
3930 real_part = (tmp >> 8) & 0xFF;
3931 imag_part = (tmp & 0xFF);
3932 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3933 (((i + 26) << 10) | 448));
90b9738d 3934
5ecab603
RM		 3935 if (dev->phy.rev >= 3) {
3936 cur_real = real_part;
3937 cur_imag = imag_part;
3938 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3939 }
4cb99775 3940
5ecab603
RM		 3941 for (j = 0; j < 128; j++) {
3942 if (dev->phy.rev < 3) {
3943 cur_real = (real_part * loscale[j] + 128) >> 8;
3944 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3945 tmp = ((cur_real & 0xFF) << 8) |
3946 (cur_imag & 0xFF);
3947 }
3948 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3949 ((tmp >> 16) & 0xFFFF));
3950 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3951 (tmp & 0xFFFF));
3952 }
90b9738d 3953 }
4cb99775 3954
4cb99775 3955 if (dev->phy.rev >= 3) {
5ecab603
RM		 3956 b43_shm_write16(dev, B43_SHM_SHARED,
3957 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3958 b43_shm_write16(dev, B43_SHM_SHARED,
3959 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 3960 }
90b9738d 3961
5ecab603
RM		 3962 if (nphy->hang_avoid)
3963 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 3964}
3965
42e1547e
RM		 3966/*
3967 * Restore RSSI Calibration
3968 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3969 */
3970static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3971{
3972 struct b43_phy_n *nphy = dev->phy.n;
3973
3974 u16 *rssical_radio_regs = NULL;
3975 u16 *rssical_phy_regs = NULL;
3976
3977 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 3978 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 3979 return;
3980 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3981 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3982 } else {
204a665b 3983 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 3984 return;
3985 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3986 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3987 }
3988
9a98979e
RM		 3989 if (dev->phy.rev >= 7) {
3990 } else {
3991 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
3992 rssical_radio_regs[0]);
3993 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
3994 rssical_radio_regs[1]);
3995 }
42e1547e
RM		 3996
3997 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3998 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3999 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4000 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4001
4002 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4003 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4004 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4005 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4006
4007 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4008 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4009 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4010 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4011}
4012
c4a92003
RM		 4013/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4014static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4015{
4016 struct b43_phy_n *nphy = dev->phy.n;
4017 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4018 u16 tmp;
4019 u8 offset, i;
c4a92003
RM		 4020
4021 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4022 for (i = 0; i < 2; i++) {
4023 tmp = (i == 0) ? 0x2000 : 0x3000;
4024 offset = i * 11;
4025
0c201cfb
RM		 4026 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4027 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4028 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4029 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4030 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4031 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4032 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4033 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4034 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4035 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4036 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4037
4038 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4039 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4040 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4041 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4042 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4043 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4044 if (nphy->ipa5g_on) {
0c201cfb
RM		 4045 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4046 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4047 } else {
0c201cfb
RM		 4048 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4049 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4050 }
0c201cfb 4051 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4052 } else {
0c201cfb
RM		 4053 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4054 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4055 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4056 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4057 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4058 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4059 if (nphy->ipa2g_on) {
0c201cfb
RM		 4060 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4061 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4062 (dev->phy.rev < 5) ? 0x11 : 0x01);
4063 } else {
0c201cfb
RM		 4064 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4065 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4066 }
4067 }
0c201cfb
RM		 4068 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4069 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4070 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4071 }
c4a92003 4072 } else {
0c201cfb
RM		 4073 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4074 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4075
0c201cfb
RM		 4076 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4077 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4078
0c201cfb
RM		 4079 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4080 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4081
0c201cfb
RM		 4082 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4083 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4084
0c201cfb
RM		 4085 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4086 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4087
4088 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4089 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4090 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4091 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4092 } else {
0c201cfb
RM		 4093 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4094 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4095 }
4096
4097 if (dev->phy.rev < 2) {
4098 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4099 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4100 } else {
4101 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4102 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4103 }
4104 }
4105}
4106
de7ed0c6
RM		 4107/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4108static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4109{
4110 struct b43_phy_n *nphy = dev->phy.n;
4111 int i;
4112 u16 scale, entry;
4113
4114 u16 tmp = nphy->txcal_bbmult;
4115 if (core == 0)
4116 tmp >>= 8;
4117 tmp &= 0xff;
4118
4119 for (i = 0; i < 18; i++) {
4120 scale = (ladder_lo[i].percent * tmp) / 100;
4121 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4122 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4123
4124 scale = (ladder_iq[i].percent * tmp) / 100;
4125 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4126 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4127 }
4128}
4129
45ca697e
RM		 4130/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4131static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4132{
4133 int i;
4134 for (i = 0; i < 15; i++)
4135 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4136 tbl_tx_filter_coef_rev4[2][i]);
4137}
4138
4139/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4140static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4141{
4142 int i, j;
4143 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4144 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4145
4146 for (i = 0; i < 3; i++)
4147 for (j = 0; j < 15; j++)
4148 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4149 tbl_tx_filter_coef_rev4[i][j]);
4150
4151 if (dev->phy.is_40mhz) {
4152 for (j = 0; j < 15; j++)
4153 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4154 tbl_tx_filter_coef_rev4[3][j]);
4155 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4156 for (j = 0; j < 15; j++)
4157 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4158 tbl_tx_filter_coef_rev4[5][j]);
4159 }
4160
4161 if (dev->phy.channel == 14)
4162 for (j = 0; j < 15; j++)
4163 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4164 tbl_tx_filter_coef_rev4[6][j]);
4165}
4166
b0022e15
RM		 4167/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4168static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4169{
4170 struct b43_phy_n *nphy = dev->phy.n;
4171
4172 u16 curr_gain[2];
4173 struct nphy_txgains target;
4174 const u32 *table = NULL;
4175
161d540c 4176 if (!nphy->txpwrctrl) {
b0022e15
RM		 4177 int i;
4178
4179 if (nphy->hang_avoid)
4180 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4181 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4182 if (nphy->hang_avoid)
4183 b43_nphy_stay_in_carrier_search(dev, false);
4184
4185 for (i = 0; i < 2; ++i) {
4186 if (dev->phy.rev >= 3) {
4187 target.ipa[i] = curr_gain[i] & 0x000F;
4188 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4189 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4190 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4191 } else {
4192 target.ipa[i] = curr_gain[i] & 0x0003;
4193 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4194 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4195 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4196 }
4197 }
4198 } else {
4199 int i;
4200 u16 index[2];
4201 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4202 B43_NPHY_TXPCTL_STAT_BIDX) >>
4203 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4204 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4205 B43_NPHY_TXPCTL_STAT_BIDX) >>
4206 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4207
4208 for (i = 0; i < 2; ++i) {
aeab5751 4209 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4210 if (dev->phy.rev >= 3) {
b0022e15
RM		 4211 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4212 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4213 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4214 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4215 } else {
b0022e15
RM		 4216 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4217 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4218 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4219 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4220 }
4221 }
4222 }
4223
4224 return target;
4225}
4226
e53de674
RM		 4227/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4228static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4229{
4230 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4231
4232 if (dev->phy.rev >= 3) {
4233 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4234 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4235 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4236 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4237 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4238 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4239 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4240 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4241 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4242 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4243 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4244 b43_nphy_reset_cca(dev);
4245 } else {
4246 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4247 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4248 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4249 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4250 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4251 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4252 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4253 }
4254}
4255
4256/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4257static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4258{
4259 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4260 u16 tmp;
4261
4262 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4263 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4264 if (dev->phy.rev >= 3) {
4265 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4266 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4267
4268 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4269 regs[2] = tmp;
4270 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4271
4272 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4273 regs[3] = tmp;
4274 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4275
4276 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4277 b43_phy_mask(dev, B43_NPHY_BBCFG,
4278 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4279
c643a66e 4280 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4281 regs[5] = tmp;
d41a3552 4282 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4283
4284 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4285 regs[6] = tmp;
d41a3552 4286 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4287 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4288 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4289
89e43dad
RM		 4290 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4291 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4292 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4293
4294 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4295 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4296 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4297 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4298 } else {
4299 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4300 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4301 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4302 regs[2] = tmp;
4303 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4304 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4305 regs[3] = tmp;
4306 tmp |= 0x2000;
d41a3552 4307 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4308 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4309 regs[4] = tmp;
4310 tmp |= 0x2000;
d41a3552 4311 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4312 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4313 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4314 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4315 tmp = 0x0180;
4316 else
4317 tmp = 0x0120;
4318 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4319 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4320 }
4321}
4322
bbc6dc12
RM		 4323/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4324static void b43_nphy_save_cal(struct b43_wldev *dev)
4325{
4326 struct b43_phy_n *nphy = dev->phy.n;
4327
4328 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4329 u16 *txcal_radio_regs = NULL;
902db91d 4330 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4331 u16 *table = NULL;
4332
4333 if (nphy->hang_avoid)
4334 b43_nphy_stay_in_carrier_search(dev, 1);
4335
4336 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4337 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4338 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4339 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4340 table = nphy->cal_cache.txcal_coeffs_2G;
4341 } else {
4342 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4343 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4344 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4345 table = nphy->cal_cache.txcal_coeffs_5G;
4346 }
4347
4348 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4349 /* TODO use some definitions */
4350 if (dev->phy.rev >= 3) {
4351 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4352 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4353 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4354 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4355 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4356 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4357 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4358 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4359 } else {
4360 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4361 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4362 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4363 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4364 }
204a665b
RM		 4365 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4366 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4367 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4368
4369 if (nphy->hang_avoid)
4370 b43_nphy_stay_in_carrier_search(dev, 0);
4371}
4372
2f258b74
RM		 4373/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4374static void b43_nphy_restore_cal(struct b43_wldev *dev)
4375{
4376 struct b43_phy_n *nphy = dev->phy.n;
4377
4378 u16 coef[4];
4379 u16 *loft = NULL;
4380 u16 *table = NULL;
4381
4382 int i;
4383 u16 *txcal_radio_regs = NULL;
4384 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4385
4386 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4387 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4388 return;
4389 table = nphy->cal_cache.txcal_coeffs_2G;
4390 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4391 } else {
204a665b 4392 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4393 return;
4394 table = nphy->cal_cache.txcal_coeffs_5G;
4395 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4396 }
4397
2581b143 4398 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4399
4400 for (i = 0; i < 4; i++) {
4401 if (dev->phy.rev >= 3)
4402 table[i] = coef[i];
4403 else
4404 coef[i] = 0;
4405 }
4406
2581b143
RM		 4407 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4408 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4409 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4410
4411 if (dev->phy.rev < 2)
4412 b43_nphy_tx_iq_workaround(dev);
4413
4414 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4415 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4416 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4417 } else {
4418 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4419 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4420 }
4421
4422 /* TODO use some definitions */
4423 if (dev->phy.rev >= 3) {
4424 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4425 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4426 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4427 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4428 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4429 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4430 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4431 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4432 } else {
4433 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4434 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4435 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4436 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4437 }
4438 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4439}
4440
fb43b8e2
RM		 4441/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4442static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4443 struct nphy_txgains target,
4444 bool full, bool mphase)
4445{
4446 struct b43_phy_n *nphy = dev->phy.n;
4447 int i;
4448 int error = 0;
4449 int freq;
4450 bool avoid = false;
4451 u8 length;
fb23d863 4452 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4453 const u16 *table;
4454 bool phy6or5x;
4455
4456 u16 buffer[11];
4457 u16 diq_start = 0;
4458 u16 save[2];
4459 u16 gain[2];
4460 struct nphy_iqcal_params params[2];
4461 bool updated[2] = { };
4462
4463 b43_nphy_stay_in_carrier_search(dev, true);
4464
4465 if (dev->phy.rev >= 4) {
4466 avoid = nphy->hang_avoid;
3db1cd5c 4467 nphy->hang_avoid = false;
fb43b8e2
RM		 4468 }
4469
9145834e 4470 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4471
4472 for (i = 0; i < 2; i++) {
4473 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4474 gain[i] = params[i].cal_gain;
4475 }
2581b143
RM		 4476
4477 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4478
4479 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4480 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4481
4482 phy6or5x = dev->phy.rev >= 6 ||
4483 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4484 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4485 if (phy6or5x) {
38bb9029
RM		 4486 if (dev->phy.is_40mhz) {
4487 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4488 tbl_tx_iqlo_cal_loft_ladder_40);
4489 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4490 tbl_tx_iqlo_cal_iqimb_ladder_40);
4491 } else {
4492 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4493 tbl_tx_iqlo_cal_loft_ladder_20);
4494 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4495 tbl_tx_iqlo_cal_iqimb_ladder_20);
4496 }
fb43b8e2
RM		 4497 }
4498
4499 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4500
aa4c7b2a 4501 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4502 freq = 2500;
4503 else
4504 freq = 5000;
4505
4506 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4507 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4508 0xFFFF, 0, true, false);
fb43b8e2 4509 else
59af099b 4510 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4511
4512 if (error == 0) {
4513 if (nphy->mphase_cal_phase_id > 2) {
4514 table = nphy->mphase_txcal_bestcoeffs;
4515 length = 11;
4516 if (dev->phy.rev < 3)
4517 length -= 2;
4518 } else {
4519 if (!full && nphy->txiqlocal_coeffsvalid) {
4520 table = nphy->txiqlocal_bestc;
4521 length = 11;
4522 if (dev->phy.rev < 3)
4523 length -= 2;
4524 } else {
4525 full = true;
4526 if (dev->phy.rev >= 3) {
4527 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4528 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4529 } else {
4530 table = tbl_tx_iqlo_cal_startcoefs;
4531 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4532 }
4533 }
4534 }
4535
2581b143 4536 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4537
4538 if (full) {
4539 if (dev->phy.rev >= 3)
4540 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4541 else
4542 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4543 } else {
4544 if (dev->phy.rev >= 3)
4545 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4546 else
4547 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4548 }
4549
4550 if (mphase) {
4551 count = nphy->mphase_txcal_cmdidx;
4552 numb = min(max,
4553 (u16)(count + nphy->mphase_txcal_numcmds));
4554 } else {
4555 count = 0;
4556 numb = max;
4557 }
4558
4559 for (; count < numb; count++) {
4560 if (full) {
4561 if (dev->phy.rev >= 3)
4562 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4563 else
4564 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4565 } else {
4566 if (dev->phy.rev >= 3)
4567 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4568 else
4569 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4570 }
4571
4572 core = (cmd & 0x3000) >> 12;
4573 type = (cmd & 0x0F00) >> 8;
4574
4575 if (phy6or5x && updated[core] == 0) {
4576 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4577 updated[core] = true;
fb43b8e2
RM		 4578 }
4579
4580 tmp = (params[core].ncorr[type] << 8) | 0x66;
4581 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4582
4583 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4584 buffer[0] = b43_ntab_read(dev,
4585 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4586 diq_start = buffer[0];
4587 buffer[0] = 0;
d41a3552
RM		 4588 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4589 0);
fb43b8e2
RM		 4590 }
4591
4592 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4593 for (i = 0; i < 2000; i++) {
4594 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4595 if (tmp & 0xC000)
4596 break;
4597 udelay(10);
4598 }
4599
9145834e
RM		 4600 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4601 buffer);
2581b143
RM		 4602 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4603 buffer);
fb43b8e2
RM		 4604
4605 if (type == 1 || type == 3 || type == 4)
4606 buffer[0] = diq_start;
4607 }
4608
4609 if (mphase)
4610 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4611
4612 last = (dev->phy.rev < 3) ? 6 : 7;
4613
4614 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4615 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4616 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4617 if (dev->phy.rev < 3) {
4618 buffer[0] = 0;
4619 buffer[1] = 0;
4620 buffer[2] = 0;
4621 buffer[3] = 0;
4622 }
2581b143
RM		 4623 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4624 buffer);
bc53e512 4625 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4626 buffer);
4627 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4628 buffer);
4629 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4630 buffer);
fb43b8e2
RM		 4631 length = 11;
4632 if (dev->phy.rev < 3)
4633 length -= 2;
9145834e
RM		 4634 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4635 nphy->txiqlocal_bestc);
fb43b8e2 4636 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4637 nphy->txiqlocal_chanspec.center_freq =
4638 dev->phy.channel_freq;
4639 nphy->txiqlocal_chanspec.channel_type =
4640 dev->phy.channel_type;
fb43b8e2
RM		 4641 } else {
4642 length = 11;
4643 if (dev->phy.rev < 3)
4644 length -= 2;
9145834e
RM		 4645 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4646 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4647 }
4648
53ae8e8c 4649 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4650 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4651 }
4652
e53de674 4653 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4654 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4655
4656 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4657 b43_nphy_tx_iq_workaround(dev);
4658
4659 if (dev->phy.rev >= 4)
4660 nphy->hang_avoid = avoid;
4661
4662 b43_nphy_stay_in_carrier_search(dev, false);
4663
4664 return error;
4665}
4666
984ff4ff
RM		 4667/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4668static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4669{
4670 struct b43_phy_n *nphy = dev->phy.n;
4671 u8 i;
4672 u16 buffer[7];
4673 bool equal = true;
4674
902db91d 4675 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4676 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4677 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4678 return;
4679
4680 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4681 for (i = 0; i < 4; i++) {
4682 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4683 equal = false;
4684 break;
4685 }
4686 }
4687
4688 if (!equal) {
4689 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4690 nphy->txiqlocal_bestc);
4691 for (i = 0; i < 4; i++)
4692 buffer[i] = 0;
4693 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4694 buffer);
4695 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4696 &nphy->txiqlocal_bestc[5]);
4697 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4698 &nphy->txiqlocal_bestc[5]);
4699 }
4700}
4701
15931e31
RM		 4702/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4703static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4704 struct nphy_txgains target, u8 type, bool debug)
4705{
4706 struct b43_phy_n *nphy = dev->phy.n;
4707 int i, j, index;
4708 u8 rfctl[2];
4709 u8 afectl_core;
4710 u16 tmp[6];
c7455cf9 4711 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4712 u32 real, imag;
4713 enum ieee80211_band band;
4714
4715 u8 use;
4716 u16 cur_hpf;
4717 u16 lna[3] = { 3, 3, 1 };
4718 u16 hpf1[3] = { 7, 2, 0 };
4719 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4720 u32 power[3] = { };
15931e31
RM		 4721 u16 gain_save[2];
4722 u16 cal_gain[2];
4723 struct nphy_iqcal_params cal_params[2];
4724 struct nphy_iq_est est;
4725 int ret = 0;
4726 bool playtone = true;
4727 int desired = 13;
4728
4729 b43_nphy_stay_in_carrier_search(dev, 1);
4730
4731 if (dev->phy.rev < 2)
984ff4ff 4732 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4733 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4734 for (i = 0; i < 2; i++) {
4735 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4736 cal_gain[i] = cal_params[i].cal_gain;
4737 }
2581b143 4738 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4739
4740 for (i = 0; i < 2; i++) {
4741 if (i == 0) {
4742 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4743 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4744 afectl_core = B43_NPHY_AFECTL_C1;
4745 } else {
4746 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4747 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4748 afectl_core = B43_NPHY_AFECTL_C2;
4749 }
4750
4751 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4752 tmp[2] = b43_phy_read(dev, afectl_core);
4753 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4754 tmp[4] = b43_phy_read(dev, rfctl[0]);
4755 tmp[5] = b43_phy_read(dev, rfctl[1]);
4756
4757 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4758 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4759 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4760 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4761 (1 - i));
4762 b43_phy_set(dev, afectl_core, 0x0006);
4763 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4764
4765 band = b43_current_band(dev->wl);
4766
4767 if (nphy->rxcalparams & 0xFF000000) {
4768 if (band == IEEE80211_BAND_5GHZ)
4769 b43_phy_write(dev, rfctl[0], 0x140);
4770 else
4771 b43_phy_write(dev, rfctl[0], 0x110);
4772 } else {
4773 if (band == IEEE80211_BAND_5GHZ)
4774 b43_phy_write(dev, rfctl[0], 0x180);
4775 else
4776 b43_phy_write(dev, rfctl[0], 0x120);
4777 }
4778
4779 if (band == IEEE80211_BAND_5GHZ)
4780 b43_phy_write(dev, rfctl[1], 0x148);
4781 else
4782 b43_phy_write(dev, rfctl[1], 0x114);
4783
4784 if (nphy->rxcalparams & 0x10000) {
4785 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4786 (i + 1));
4787 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4788 (2 - i));
4789 }
4790
30115c22 4791 for (j = 0; j < 4; j++) {
15931e31
RM		 4792 if (j < 3) {
4793 cur_lna = lna[j];
4794 cur_hpf1 = hpf1[j];
4795 cur_hpf2 = hpf2[j];
4796 } else {
4797 if (power[1] > 10000) {
4798 use = 1;
4799 cur_hpf = cur_hpf1;
4800 index = 2;
4801 } else {
4802 if (power[0] > 10000) {
4803 use = 1;
4804 cur_hpf = cur_hpf1;
4805 index = 1;
4806 } else {
4807 index = 0;
4808 use = 2;
4809 cur_hpf = cur_hpf2;
4810 }
4811 }
4812 cur_lna = lna[index];
4813 cur_hpf1 = hpf1[index];
4814 cur_hpf2 = hpf2[index];
4815 cur_hpf += desired - hweight32(power[index]);
4816 cur_hpf = clamp_val(cur_hpf, 0, 10);
4817 if (use == 1)
4818 cur_hpf1 = cur_hpf;
4819 else
4820 cur_hpf2 = cur_hpf;
4821 }
4822
4823 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4824 (cur_lna << 2));
78ae7532 4825 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 4826 false);
de9a47f9 4827 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4828 b43_nphy_stop_playback(dev);
15931e31
RM		 4829
4830 if (playtone) {
59af099b
RM		 4831 ret = b43_nphy_tx_tone(dev, 4000,
4832 (nphy->rxcalparams & 0xFFFF),
4833 false, false);
15931e31
RM		 4834 playtone = false;
4835 } else {
10a79873
RM		 4836 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4837 false, false);
15931e31
RM		 4838 }
4839
4840 if (ret == 0) {
4841 if (j < 3) {
4842 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4843 false);
4844 if (i == 0) {
4845 real = est.i0_pwr;
4846 imag = est.q0_pwr;
4847 } else {
4848 real = est.i1_pwr;
4849 imag = est.q1_pwr;
4850 }
4851 power[i] = ((real + imag) / 1024) + 1;
4852 } else {
4853 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4854 }
53ae8e8c 4855 b43_nphy_stop_playback(dev);
15931e31
RM		 4856 }
4857
4858 if (ret != 0)
4859 break;
4860 }
4861
4862 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4863 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4864 b43_phy_write(dev, rfctl[1], tmp[5]);
4865 b43_phy_write(dev, rfctl[0], tmp[4]);
4866 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4867 b43_phy_write(dev, afectl_core, tmp[2]);
4868 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4869
4870 if (ret != 0)
4871 break;
4872 }
4873
78ae7532 4874 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 4875 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 4876 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4877
4878 b43_nphy_stay_in_carrier_search(dev, 0);
4879
4880 return ret;
4881}
4882
4883static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4884 struct nphy_txgains target, u8 type, bool debug)
4885{
4886 return -1;
4887}
4888
4889/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4890static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4891 struct nphy_txgains target, u8 type, bool debug)
4892{
4893 if (dev->phy.rev >= 3)
4894 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4895 else
4896 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4897}
4898
4e687b22
GS		 4899/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4900static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4901{
4902 struct b43_phy *phy = &dev->phy;
4903 struct b43_phy_n *nphy = phy->n;
0b81c23d 4904 /* u16 buf[16]; it's rev3+ */
4e687b22 4905
049fbfee
RM		 4906 nphy->phyrxchain = mask;
4907
4e687b22
GS		 4908 if (0 /* FIXME clk */)
4909 return;
4910
4911 b43_mac_suspend(dev);
4912
4913 if (nphy->hang_avoid)
4914 b43_nphy_stay_in_carrier_search(dev, true);
4915
4916 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4917 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4918
049fbfee 4919 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 4920 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4921 if (dev->phy.rev >= 3) {
4922 /* TODO */
4923 }
4924 } else {
4925 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4926 if (dev->phy.rev >= 3) {
4927 /* TODO */
4928 }
4929 }
4930
4931 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4932
4933 if (nphy->hang_avoid)
4934 b43_nphy_stay_in_carrier_search(dev, false);
4935
4936 b43_mac_enable(dev);
4937}
4938
104cfa88
RM		 4939/**************************************************
4940 * N-PHY init
4941 **************************************************/
4942
104cfa88
RM		 4943/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4944static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4945{
4946 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4947
4948 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4949 if (preamble == 1)
4950 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4951 else
4952 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4953
4954 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4955}
4956
4957/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4958static void b43_nphy_bphy_init(struct b43_wldev *dev)
4959{
4960 unsigned int i;
4961 u16 val;
4962
4963 val = 0x1E1F;
4964 for (i = 0; i < 16; i++) {
4965 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4966 val -= 0x202;
4967 }
4968 val = 0x3E3F;
4969 for (i = 0; i < 16; i++) {
4970 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4971 val -= 0x202;
4972 }
4973 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4974}
4975
4976/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4977static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4978{
4979 if (dev->phy.rev >= 3) {
4980 if (!init)
4981 return;
4982 if (0 /* FIXME */) {
4983 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4984 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4985 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4986 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4987 }
4988 } else {
4989 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4990 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4991
4992 switch (dev->dev->bus_type) {
4993#ifdef CONFIG_B43_BCMA
4994 case B43_BUS_BCMA:
4995 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4996 0xFC00, 0xFC00);
4997 break;
4998#endif
4999#ifdef CONFIG_B43_SSB
5000 case B43_BUS_SSB:
5001 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5002 0xFC00, 0xFC00);
5003 break;
5004#endif
5005 }
5006
5056635c
RM		 5007 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5008 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5009 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5010 0);
104cfa88
RM		 5011
5012 if (init) {
5013 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5014 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5015 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5016 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5017 }
5018 }
5019}
5020
5021/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5022static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5023{
0581483a 5024 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5025 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5026 struct b43_phy_n *nphy = phy->n;
5027 u8 tx_pwr_state;
5028 struct nphy_txgains target;
95b66bad 5029 u16 tmp;
0988a7a1
RM		 5030 enum ieee80211_band tmp2;
5031 bool do_rssi_cal;
5032
5033 u16 clip[2];
5034 bool do_cal = false;
95b66bad 5035
0988a7a1 5036 if ((dev->phy.rev >= 3) &&
0581483a 5037 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5038 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5039 switch (dev->dev->bus_type) {
42c9a458
RM		 5040#ifdef CONFIG_B43_BCMA
5041 case B43_BUS_BCMA:
5042 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5043 BCMA_CC_CHIPCTL, 0x40);
5044 break;
5045#endif
6cbab0d9
RM		 5046#ifdef CONFIG_B43_SSB
5047 case B43_BUS_SSB:
5048 chipco_set32(&dev->dev->sdev->bus->chipco,
5049 SSB_CHIPCO_CHIPCTL, 0x40);
5050 break;
5051#endif
5052 }
0988a7a1
RM		 5053 }
5054 nphy->deaf_count = 0;
95b66bad 5055 b43_nphy_tables_init(dev);
0988a7a1
RM		 5056 nphy->crsminpwr_adjusted = false;
5057 nphy->noisevars_adjusted = false;
95b66bad
MB		 5058
5059 /* Clear all overrides */
0988a7a1
RM		 5060 if (dev->phy.rev >= 3) {
5061 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5062 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5063 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5064 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5065 } else {
5066 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5067 }
95b66bad
MB		 5068 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5069 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5070 if (dev->phy.rev < 6) {
5071 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5072 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5073 }
95b66bad
MB		 5074 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5075 ~(B43_NPHY_RFSEQMODE_CAOVER |
5076 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5077 if (dev->phy.rev >= 3)
5078 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5079 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5080
0988a7a1
RM		 5081 if (dev->phy.rev <= 2) {
5082 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5083 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5084 ~B43_NPHY_BPHY_CTL3_SCALE,
5085 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5086 }
95b66bad
MB		 5087 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5088 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5089
0eff8fcd 5090 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5091 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5092 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5093 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5094 else
5095 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5096 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5097 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5098 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5099
ad9716e8 5100 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5101 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5102
5103 if (phy->rev < 2) {
5104 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5105 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5106 }
0988a7a1
RM		 5107
5108 tmp2 = b43_current_band(dev->wl);
c002831a 5109 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5110 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5111 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5112 nphy->papd_epsilon_offset[0] << 7);
5113 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5114 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5115 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5116 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5117 } else if (phy->rev >= 5) {
45ca697e 5118 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5119 }
5120
95b66bad 5121 b43_nphy_workarounds(dev);
95b66bad 5122
0988a7a1 5123 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5124 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5125 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5126 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5127 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5128 b43_phy_force_clock(dev, 0);
0988a7a1 5129
858a1652 5130 b43_mac_phy_clock_set(dev, true);
0988a7a1 5131
e50cbcf6 5132 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5133 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5134 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5135 b43_nphy_pa_override(dev, true);
0988a7a1 5136
bbec398c
RM		 5137 b43_nphy_classifier(dev, 0, 0);
5138 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5139 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5140 b43_nphy_bphy_init(dev);
5141
0988a7a1 5142 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5143 b43_nphy_tx_power_ctrl(dev, false);
5144 b43_nphy_tx_power_fix(dev);
3dda07b6 5145 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5146 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5147 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5148
0988a7a1 5149 if (nphy->phyrxchain != 3)
4e687b22 5150 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5151 if (nphy->mphase_cal_phase_id > 0)
5152 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5153
5154 do_rssi_cal = false;
5155 if (phy->rev >= 3) {
5156 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5157 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5158 else
204a665b 5159 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5160
5161 if (do_rssi_cal)
4cb99775 5162 b43_nphy_rssi_cal(dev);
0988a7a1 5163 else
42e1547e 5164 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5165 } else {
4cb99775 5166 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5167 }
5168
5169 if (!((nphy->measure_hold & 0x6) != 0)) {
5170 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5171 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5172 else
204a665b 5173 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5174
5175 if (nphy->mute)
5176 do_cal = false;
5177
5178 if (do_cal) {
b0022e15 5179 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5180
5181 if (nphy->antsel_type == 2)
8987a9e9 5182 b43_nphy_superswitch_init(dev, true);
0988a7a1 5183 if (nphy->perical != 2) {
90b9738d 5184 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5185 if (phy->rev >= 3) {
5186 nphy->cal_orig_pwr_idx[0] =
5187 nphy->txpwrindex[0].index_internal;
5188 nphy->cal_orig_pwr_idx[1] =
5189 nphy->txpwrindex[1].index_internal;
5190 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5191 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5192 }
e7797bf2
RM		 5193 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5194 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5195 b43_nphy_save_cal(dev);
5196 } else if (nphy->mphase_cal_phase_id == 0)
5197 ;/* N PHY Periodic Calibration with arg 3 */
5198 } else {
5199 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5200 }
5201 }
5202
6dcd9d91 5203 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5204 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5205 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5206 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5207 if (phy->rev >= 3 && phy->rev <= 6)
5208 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 5209 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5210 if (phy->rev >= 3)
5211 b43_nphy_spur_workaround(dev);
95b66bad 5212
53a6e234 5213 return 0;
424047e6 5214}
ef1a628d 5215
104cfa88
RM		 5216/**************************************************
5217 * Channel switching ops.
5218 **************************************************/
5219
5220static void b43_chantab_phy_upload(struct b43_wldev *dev,
5221 const struct b43_phy_n_sfo_cfg *e)
5222{
5223 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5224 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5225 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5226 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5227 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5228 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5229}
5230
49d55cef
RM		 5231/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5232static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5233{
d66be829
RM		 5234 switch (dev->dev->bus_type) {
5235#ifdef CONFIG_B43_BCMA
5236 case B43_BUS_BCMA:
9b383672
HM		 5237 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5238 avoid);
d66be829 5239 break;
8b1fdb53 5240#endif
d66be829
RM		 5241#ifdef CONFIG_B43_SSB
5242 case B43_BUS_SSB:
46fc4c90
RM		 5243 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5244 avoid);
d66be829
RM		 5245 break;
5246#endif
5247 }
49d55cef
RM		 5248}
5249
1b69ec7b 5250/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5251static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5252 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5253 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5254{
5255 struct b43_phy *phy = &dev->phy;
5256 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5257 int ch = new_channel->hw_value;
1b69ec7b 5258
087de74a 5259 u16 old_band_5ghz;
12cd43c6 5260 u16 tmp16;
1b69ec7b 5261
087de74a
RM		 5262 old_band_5ghz =
5263 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5264 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5265 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5266 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5267 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5268 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5269 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5270 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5271 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5272 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5273 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5274 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5275 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5276 }
5277
5278 b43_chantab_phy_upload(dev, e);
5279
a656b6a9 5280 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5281 b43_nphy_classifier(dev, 2, 0);
5282 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5283 } else {
5284 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5285 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5286 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5287 }
5288
161d540c 5289 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5290 b43_nphy_tx_power_fix(dev);
5291
5292 if (dev->phy.rev < 3)
5293 b43_nphy_adjust_lna_gain_table(dev);
5294
5295 b43_nphy_tx_lp_fbw(dev);
5296
49d55cef
RM		 5297 if (dev->phy.rev >= 3 &&
5298 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5299 bool avoid = false;
5300 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5301 avoid = true;
5302 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5303 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5304 avoid = true;
5305 } else { /* 40MHz */
5306 if (nphy->aband_spurwar_en &&
5307 (ch == 38 || ch == 102 || ch == 118))
5308 avoid = dev->dev->chip_id == 0x4716;
5309 }
5310
5311 b43_nphy_pmu_spur_avoid(dev, avoid);
5312
5313 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5314 dev->dev->chip_id == 43225) {
5315 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5316 avoid ? 0x5341 : 0x8889);
5317 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5318 }
5319
5320 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5321 ; /* TODO: reset PLL */
5322
5323 if (avoid)
5324 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5325 else
5326 b43_phy_mask(dev, B43_NPHY_BBCFG,
5327 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5328
5329 b43_nphy_reset_cca(dev);
5330
5331 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5332 }
5333
5334 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5335
5336 if (phy->rev >= 3)
5337 b43_nphy_spur_workaround(dev);
5338}
5339
eff66c51 5340/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5341static int b43_nphy_set_channel(struct b43_wldev *dev,
5342 struct ieee80211_channel *channel,
5343 enum nl80211_channel_type channel_type)
eff66c51 5344{
a656b6a9 5345 struct b43_phy *phy = &dev->phy;
eff66c51 5346
2eeb6fd0
JL		 5347 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5348 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5349
5350 u8 tmp;
eff66c51
RM		 5351
5352 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5353 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5354 channel->center_freq);
f19ebe7d
RM		 5355 if (!tabent_r3)
5356 return -ESRCH;
ffd2d9bd 5357 } else {
a656b6a9
RM		 5358 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5359 channel->hw_value);
f19ebe7d 5360 if (!tabent_r2)
ffd2d9bd 5361 return -ESRCH;
eff66c51
RM		 5362 }
5363
204a665b
RM		 5364 /* Channel is set later in common code, but we need to set it on our
5365 own to let this function's subcalls work properly. */
5366 phy->channel = channel->hw_value;
5367 phy->channel_freq = channel->center_freq;
eff66c51 5368
e5c407f9
RM		 5369 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5370 b43_channel_type_is_40mhz(channel_type))
5371 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5372
a656b6a9
RM		 5373 if (channel_type == NL80211_CHAN_HT40PLUS)
5374 b43_phy_set(dev, B43_NPHY_RXCTL,
5375 B43_NPHY_RXCTL_BSELU20);
5376 else if (channel_type == NL80211_CHAN_HT40MINUS)
5377 b43_phy_mask(dev, B43_NPHY_RXCTL,
5378 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5379
5380 if (dev->phy.rev >= 3) {
a656b6a9 5381 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5382 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5383 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5384 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5385 } else {
a656b6a9 5386 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5387 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5388 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5389 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5390 }
5391
5392 return 0;
5393}
5394
104cfa88
RM		 5395/**************************************************
5396 * Basic PHY ops.
5397 **************************************************/
5398
ef1a628d
MB		 5399static int b43_nphy_op_allocate(struct b43_wldev *dev)
5400{
5401 struct b43_phy_n *nphy;
5402
5403 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5404 if (!nphy)
5405 return -ENOMEM;
5406 dev->phy.n = nphy;
5407
ef1a628d
MB		 5408 return 0;
5409}
5410
fb11137a 5411static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5412{
fb11137a
MB		 5413 struct b43_phy *phy = &dev->phy;
5414 struct b43_phy_n *nphy = phy->n;
c7d64310 5415 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5416
fb11137a 5417 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5418
aca434d3 5419 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5420 nphy->spur_avoid = (phy->rev >= 3) ?
5421 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5422 nphy->init_por = true;
0b81c23d
RM		 5423 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5424 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5425 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5426 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5427 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5428 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5429 nphy->tx_pwr_idx[0] = 128;
5430 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5431
5432 /* Hardware TX power control and 5GHz power gain */
5433 nphy->txpwrctrl = false;
5434 nphy->pwg_gain_5ghz = false;
5435 if (dev->phy.rev >= 3 ||
5436 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5437 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5438 nphy->txpwrctrl = true;
5439 nphy->pwg_gain_5ghz = true;
5440 } else if (sprom->revision >= 4) {
5441 if (dev->phy.rev >= 2 &&
5442 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5443 nphy->txpwrctrl = true;
5444#ifdef CONFIG_B43_SSB
5445 if (dev->dev->bus_type == B43_BUS_SSB &&
5446 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5447 struct pci_dev *pdev =
5448 dev->dev->sdev->bus->host_pci;
5449 if (pdev->device == 0x4328 ||
5450 pdev->device == 0x432a)
5451 nphy->pwg_gain_5ghz = true;
5452 }
5453#endif
5454 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5455 nphy->pwg_gain_5ghz = true;
5456 }
5457 }
5458
5459 if (dev->phy.rev >= 3) {
5460 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5461 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5462 }
572d37a4
RM		 5463
5464 nphy->init_por = true;
ef1a628d
MB		 5465}
5466
fb11137a 5467static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5468{
fb11137a
MB		 5469 struct b43_phy *phy = &dev->phy;
5470 struct b43_phy_n *nphy = phy->n;
ef1a628d 5471
ef1a628d 5472 kfree(nphy);
fb11137a
MB		 5473 phy->n = NULL;
5474}
5475
5476static int b43_nphy_op_init(struct b43_wldev *dev)
5477{
5478 return b43_phy_initn(dev);
ef1a628d
MB		 5479}
5480
5481static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5482{
5483#if B43_DEBUG
5484 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5485 /* OFDM registers are onnly available on A/G-PHYs */
5486 b43err(dev->wl, "Invalid OFDM PHY access at "
5487 "0x%04X on N-PHY\n", offset);
5488 dump_stack();
5489 }
5490 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5491 /* Ext-G registers are only available on G-PHYs */
5492 b43err(dev->wl, "Invalid EXT-G PHY access at "
5493 "0x%04X on N-PHY\n", offset);
5494 dump_stack();
5495 }
5496#endif /* B43_DEBUG */
5497}
5498
5499static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5500{
5501 check_phyreg(dev, reg);
5502 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5503 return b43_read16(dev, B43_MMIO_PHY_DATA);
5504}
5505
5506static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5507{
5508 check_phyreg(dev, reg);
5509 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5510 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5511}
5512
755fd183
RM		 5513static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5514 u16 set)
5515{
5516 check_phyreg(dev, reg);
5517 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5518 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5519}
5520
ef1a628d
MB		 5521static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5522{
5523 /* Register 1 is a 32-bit register. */
5524 B43_WARN_ON(reg == 1);
5525 /* N-PHY needs 0x100 for read access */
5526 reg |= 0x100;
5527
5528 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5529 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5530}
5531
5532static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5533{
5534 /* Register 1 is a 32-bit register. */
5535 B43_WARN_ON(reg == 1);
5536
5537 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5538 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5539}
5540
c2b7aefd 5541/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5542static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5543 bool blocked)
c2b7aefd
RM		 5544{
5545 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5546 b43err(dev->wl, "MAC not suspended\n");
5547
5548 if (blocked) {
5549 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5550 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5551 if (dev->phy.rev >= 7) {
5552 /* TODO */
5553 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5554 b43_radio_mask(dev, 0x09, ~0x2);
5555
5556 b43_radio_write(dev, 0x204D, 0);
5557 b43_radio_write(dev, 0x2053, 0);
5558 b43_radio_write(dev, 0x2058, 0);
5559 b43_radio_write(dev, 0x205E, 0);
5560 b43_radio_mask(dev, 0x2062, ~0xF0);
5561 b43_radio_write(dev, 0x2064, 0);
5562
5563 b43_radio_write(dev, 0x304D, 0);
5564 b43_radio_write(dev, 0x3053, 0);
5565 b43_radio_write(dev, 0x3058, 0);
5566 b43_radio_write(dev, 0x305E, 0);
5567 b43_radio_mask(dev, 0x3062, ~0xF0);
5568 b43_radio_write(dev, 0x3064, 0);
5569 }
5570 } else {
572d37a4
RM		 5571 if (dev->phy.rev >= 7) {
5572 b43_radio_2057_init(dev);
5573 b43_switch_channel(dev, dev->phy.channel);
5574 } else if (dev->phy.rev >= 3) {
d817f4e1 5575 b43_radio_init2056(dev);
78159788 5576 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5577 } else {
5578 b43_radio_init2055(dev);
5579 }
5580 }
ef1a628d
MB		 5581}
5582
0f4091b9 5583/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5584static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5585{
2a870831
RM		 5586 u16 override = on ? 0x0 : 0x7FFF;
5587 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5588
2a870831
RM		 5589 if (dev->phy.rev >= 3) {
5590 if (on) {
5591 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5592 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5593 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5594 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5595 } else {
5596 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5597 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5598 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5599 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5600 }
5601 } else {
5602 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5603 }
cb24f57f
MB		 5604}
5605
ef1a628d
MB		 5606static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5607 unsigned int new_channel)
5608{
675a0b04
KB		 5609 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5610 enum nl80211_channel_type channel_type =
5611 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5612
ef1a628d
MB		 5613 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5614 if ((new_channel < 1) || (new_channel > 14))
5615 return -EINVAL;
5616 } else {
5617 if (new_channel > 200)
5618 return -EINVAL;
5619 }
5620
a656b6a9 5621 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5622}
5623
5624static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5625{
5626 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5627 return 1;
5628 return 36;
5629}
5630
ef1a628d
MB		 5631const struct b43_phy_operations b43_phyops_n = {
5632 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5633 .free = b43_nphy_op_free,
5634 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5635 .init = b43_nphy_op_init,
ef1a628d
MB		 5636 .phy_read = b43_nphy_op_read,
5637 .phy_write = b43_nphy_op_write,
755fd183 5638 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5639 .radio_read = b43_nphy_op_radio_read,
5640 .radio_write = b43_nphy_op_radio_write,
5641 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5642 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5643 .switch_channel = b43_nphy_op_switch_channel,
5644 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5645 .recalc_txpower = b43_nphy_op_recalc_txpower,
5646 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5647};
Linux 6.x block layer and io_uring tree(s)