Commit | Line | Data |
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424047e6 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | IEEE 802.11n PHY support | |
5 | ||
6 | Copyright (c) 2008 Michael Buesch <mb@bu3sch.de> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; see the file COPYING. If not, write to | |
20 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
21 | Boston, MA 02110-1301, USA. | |
22 | ||
23 | */ | |
24 | ||
819d772b JL |
25 | #include <linux/delay.h> |
26 | #include <linux/types.h> | |
27 | ||
424047e6 | 28 | #include "b43.h" |
3d0da751 | 29 | #include "phy_n.h" |
53a6e234 | 30 | #include "tables_nphy.h" |
bbec398c | 31 | #include "main.h" |
424047e6 | 32 | |
f8187b5b RM |
33 | struct nphy_txgains { |
34 | u16 txgm[2]; | |
35 | u16 pga[2]; | |
36 | u16 pad[2]; | |
37 | u16 ipa[2]; | |
38 | }; | |
39 | ||
40 | struct nphy_iqcal_params { | |
41 | u16 txgm; | |
42 | u16 pga; | |
43 | u16 pad; | |
44 | u16 ipa; | |
45 | u16 cal_gain; | |
46 | u16 ncorr[5]; | |
47 | }; | |
48 | ||
49 | struct nphy_iq_est { | |
50 | s32 iq0_prod; | |
51 | u32 i0_pwr; | |
52 | u32 q0_pwr; | |
53 | s32 iq1_prod; | |
54 | u32 i1_pwr; | |
55 | u32 q1_pwr; | |
56 | }; | |
424047e6 | 57 | |
67c0d6e2 RM |
58 | enum b43_nphy_rf_sequence { |
59 | B43_RFSEQ_RX2TX, | |
60 | B43_RFSEQ_TX2RX, | |
61 | B43_RFSEQ_RESET2RX, | |
62 | B43_RFSEQ_UPDATE_GAINH, | |
63 | B43_RFSEQ_UPDATE_GAINL, | |
64 | B43_RFSEQ_UPDATE_GAINU, | |
65 | }; | |
66 | ||
9501fefe RM |
67 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, |
68 | u8 *events, u8 *delays, u8 length); | |
67c0d6e2 RM |
69 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, |
70 | enum b43_nphy_rf_sequence seq); | |
67cbc3ed RM |
71 | static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, |
72 | u16 value, u8 core, bool off); | |
73 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | |
74 | u16 value, u8 core); | |
67c0d6e2 | 75 | |
53a6e234 MB |
76 | void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) |
77 | {//TODO | |
78 | } | |
79 | ||
18c8adeb | 80 | static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) |
53a6e234 MB |
81 | {//TODO |
82 | } | |
83 | ||
18c8adeb MB |
84 | static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, |
85 | bool ignore_tssi) | |
86 | {//TODO | |
87 | return B43_TXPWR_RES_DONE; | |
88 | } | |
89 | ||
d1591314 MB |
90 | static void b43_chantab_radio_upload(struct b43_wldev *dev, |
91 | const struct b43_nphy_channeltab_entry *e) | |
92 | { | |
93 | b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref); | |
94 | b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); | |
95 | b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); | |
96 | b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); | |
97 | b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1); | |
98 | b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2); | |
99 | b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); | |
100 | b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); | |
101 | b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); | |
102 | b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); | |
103 | b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); | |
104 | b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); | |
105 | b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); | |
106 | b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); | |
107 | b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); | |
108 | b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); | |
109 | b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); | |
110 | b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); | |
111 | b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); | |
112 | b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); | |
113 | b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); | |
114 | b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); | |
115 | } | |
116 | ||
117 | static void b43_chantab_phy_upload(struct b43_wldev *dev, | |
118 | const struct b43_nphy_channeltab_entry *e) | |
119 | { | |
120 | b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); | |
121 | b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); | |
122 | b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); | |
123 | b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); | |
124 | b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); | |
125 | b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); | |
126 | } | |
127 | ||
128 | static void b43_nphy_tx_power_fix(struct b43_wldev *dev) | |
129 | { | |
130 | //TODO | |
131 | } | |
132 | ||
ef1a628d MB |
133 | /* Tune the hardware to a new channel. */ |
134 | static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel) | |
53a6e234 | 135 | { |
d1591314 MB |
136 | const struct b43_nphy_channeltab_entry *tabent; |
137 | ||
138 | tabent = b43_nphy_get_chantabent(dev, channel); | |
139 | if (!tabent) | |
140 | return -ESRCH; | |
141 | ||
142 | //FIXME enable/disable band select upper20 in RXCTL | |
143 | if (0 /*FIXME 5Ghz*/) | |
144 | b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20); | |
145 | else | |
146 | b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50); | |
147 | b43_chantab_radio_upload(dev, tabent); | |
148 | udelay(50); | |
149 | b43_radio_write16(dev, B2055_VCO_CAL10, 5); | |
150 | b43_radio_write16(dev, B2055_VCO_CAL10, 45); | |
151 | b43_radio_write16(dev, B2055_VCO_CAL10, 65); | |
152 | udelay(300); | |
153 | if (0 /*FIXME 5Ghz*/) | |
154 | b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); | |
155 | else | |
156 | b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); | |
157 | b43_chantab_phy_upload(dev, tabent); | |
158 | b43_nphy_tx_power_fix(dev); | |
53a6e234 | 159 | |
d1591314 | 160 | return 0; |
53a6e234 MB |
161 | } |
162 | ||
163 | static void b43_radio_init2055_pre(struct b43_wldev *dev) | |
164 | { | |
165 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
166 | ~B43_NPHY_RFCTL_CMD_PORFORCE); | |
167 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
168 | B43_NPHY_RFCTL_CMD_CHIP0PU | | |
169 | B43_NPHY_RFCTL_CMD_OEPORFORCE); | |
170 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
171 | B43_NPHY_RFCTL_CMD_PORFORCE); | |
172 | } | |
173 | ||
174 | static void b43_radio_init2055_post(struct b43_wldev *dev) | |
175 | { | |
176 | struct ssb_sprom *sprom = &(dev->dev->bus->sprom); | |
177 | struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo); | |
178 | int i; | |
179 | u16 val; | |
180 | ||
181 | b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); | |
182 | msleep(1); | |
738f0f43 GS |
183 | if ((sprom->revision != 4) || |
184 | !(sprom->boardflags_hi & B43_BFH_RSSIINV)) { | |
53a6e234 MB |
185 | if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) || |
186 | (binfo->type != 0x46D) || | |
187 | (binfo->rev < 0x41)) { | |
188 | b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); | |
189 | b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); | |
190 | msleep(1); | |
191 | } | |
192 | } | |
193 | b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C); | |
194 | msleep(1); | |
195 | b43_radio_write16(dev, B2055_CAL_MISC, 0x3C); | |
196 | msleep(1); | |
197 | b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); | |
198 | msleep(1); | |
199 | b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); | |
200 | msleep(1); | |
201 | b43_radio_set(dev, B2055_CAL_MISC, 0x1); | |
202 | msleep(1); | |
203 | b43_radio_set(dev, B2055_CAL_MISC, 0x40); | |
204 | msleep(1); | |
205 | for (i = 0; i < 100; i++) { | |
206 | val = b43_radio_read16(dev, B2055_CAL_COUT2); | |
207 | if (val & 0x80) | |
208 | break; | |
209 | udelay(10); | |
210 | } | |
211 | msleep(1); | |
212 | b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); | |
213 | msleep(1); | |
ef1a628d | 214 | nphy_channel_switch(dev, dev->phy.channel); |
53a6e234 MB |
215 | b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9); |
216 | b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9); | |
217 | b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83); | |
218 | b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83); | |
219 | } | |
220 | ||
c2b7aefd RM |
221 | /* |
222 | * Initialize a Broadcom 2055 N-radio | |
223 | * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init | |
224 | */ | |
53a6e234 MB |
225 | static void b43_radio_init2055(struct b43_wldev *dev) |
226 | { | |
227 | b43_radio_init2055_pre(dev); | |
228 | if (b43_status(dev) < B43_STAT_INITIALIZED) | |
229 | b2055_upload_inittab(dev, 0, 1); | |
230 | else | |
231 | b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0); | |
232 | b43_radio_init2055_post(dev); | |
233 | } | |
234 | ||
4772ae10 RM |
235 | /* |
236 | * Upload the N-PHY tables. | |
237 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables | |
238 | */ | |
95b66bad MB |
239 | static void b43_nphy_tables_init(struct b43_wldev *dev) |
240 | { | |
4772ae10 RM |
241 | if (dev->phy.rev < 3) |
242 | b43_nphy_rev0_1_2_tables_init(dev); | |
243 | else | |
244 | b43_nphy_rev3plus_tables_init(dev); | |
95b66bad MB |
245 | } |
246 | ||
e50cbcf6 RM |
247 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ |
248 | static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) | |
249 | { | |
250 | struct b43_phy_n *nphy = dev->phy.n; | |
251 | enum ieee80211_band band; | |
252 | u16 tmp; | |
253 | ||
254 | if (!enable) { | |
255 | nphy->rfctrl_intc1_save = b43_phy_read(dev, | |
256 | B43_NPHY_RFCTL_INTC1); | |
257 | nphy->rfctrl_intc2_save = b43_phy_read(dev, | |
258 | B43_NPHY_RFCTL_INTC2); | |
259 | band = b43_current_band(dev->wl); | |
260 | if (dev->phy.rev >= 3) { | |
261 | if (band == IEEE80211_BAND_5GHZ) | |
262 | tmp = 0x600; | |
263 | else | |
264 | tmp = 0x480; | |
265 | } else { | |
266 | if (band == IEEE80211_BAND_5GHZ) | |
267 | tmp = 0x180; | |
268 | else | |
269 | tmp = 0x120; | |
270 | } | |
271 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
272 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
273 | } else { | |
274 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, | |
275 | nphy->rfctrl_intc1_save); | |
276 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, | |
277 | nphy->rfctrl_intc2_save); | |
278 | } | |
279 | } | |
280 | ||
fe3e46e8 RM |
281 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ |
282 | static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) | |
283 | { | |
284 | struct b43_phy_n *nphy = dev->phy.n; | |
285 | u16 tmp; | |
286 | enum ieee80211_band band = b43_current_band(dev->wl); | |
287 | bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) || | |
288 | (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ); | |
289 | ||
290 | if (dev->phy.rev >= 3) { | |
291 | if (ipa) { | |
292 | tmp = 4; | |
293 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, | |
294 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
295 | } | |
296 | ||
297 | tmp = 1; | |
298 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, | |
299 | (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); | |
300 | } | |
301 | } | |
302 | ||
4a933c85 RM |
303 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ |
304 | static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force) | |
305 | { | |
306 | u32 tmslow; | |
307 | ||
308 | if (dev->phy.type != B43_PHYTYPE_N) | |
309 | return; | |
310 | ||
311 | tmslow = ssb_read32(dev->dev, SSB_TMSLOW); | |
312 | if (force) | |
313 | tmslow |= SSB_TMSLOW_FGC; | |
314 | else | |
315 | tmslow &= ~SSB_TMSLOW_FGC; | |
316 | ssb_write32(dev->dev, SSB_TMSLOW, tmslow); | |
317 | } | |
318 | ||
319 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ | |
95b66bad MB |
320 | static void b43_nphy_reset_cca(struct b43_wldev *dev) |
321 | { | |
322 | u16 bbcfg; | |
323 | ||
4a933c85 | 324 | b43_nphy_bmac_clock_fgc(dev, 1); |
95b66bad | 325 | bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); |
4a933c85 RM |
326 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); |
327 | udelay(1); | |
328 | b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); | |
329 | b43_nphy_bmac_clock_fgc(dev, 0); | |
67c0d6e2 | 330 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
95b66bad MB |
331 | } |
332 | ||
ad9716e8 RM |
333 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ |
334 | static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) | |
335 | { | |
336 | u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); | |
337 | ||
338 | mimocfg |= B43_NPHY_MIMOCFG_AUTO; | |
339 | if (preamble == 1) | |
340 | mimocfg |= B43_NPHY_MIMOCFG_GFMIX; | |
341 | else | |
342 | mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; | |
343 | ||
344 | b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); | |
345 | } | |
346 | ||
4f4ab6cd RM |
347 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ |
348 | static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) | |
349 | { | |
350 | struct b43_phy_n *nphy = dev->phy.n; | |
351 | ||
352 | bool override = false; | |
353 | u16 chain = 0x33; | |
354 | ||
355 | if (nphy->txrx_chain == 0) { | |
356 | chain = 0x11; | |
357 | override = true; | |
358 | } else if (nphy->txrx_chain == 1) { | |
359 | chain = 0x22; | |
360 | override = true; | |
361 | } | |
362 | ||
363 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
364 | ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), | |
365 | chain); | |
366 | ||
367 | if (override) | |
368 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
369 | B43_NPHY_RFSEQMODE_CAOVER); | |
370 | else | |
371 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, | |
372 | ~B43_NPHY_RFSEQMODE_CAOVER); | |
373 | } | |
374 | ||
2faa6b83 RM |
375 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ |
376 | static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, | |
377 | u16 samps, u8 time, bool wait) | |
378 | { | |
379 | int i; | |
380 | u16 tmp; | |
381 | ||
382 | b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); | |
383 | b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); | |
384 | if (wait) | |
385 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); | |
386 | else | |
387 | b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); | |
388 | ||
389 | b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); | |
390 | ||
391 | for (i = 1000; i; i--) { | |
392 | tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); | |
393 | if (!(tmp & B43_NPHY_IQEST_CMD_START)) { | |
394 | est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | | |
395 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); | |
396 | est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | | |
397 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); | |
398 | est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | | |
399 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); | |
400 | ||
401 | est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | | |
402 | b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); | |
403 | est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | | |
404 | b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); | |
405 | est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | | |
406 | b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); | |
407 | return; | |
408 | } | |
409 | udelay(10); | |
410 | } | |
411 | memset(est, 0, sizeof(*est)); | |
412 | } | |
413 | ||
a67162ab RM |
414 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ |
415 | static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, | |
416 | struct b43_phy_n_iq_comp *pcomp) | |
417 | { | |
418 | if (write) { | |
419 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); | |
420 | b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); | |
421 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); | |
422 | b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); | |
423 | } else { | |
424 | pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); | |
425 | pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); | |
426 | pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); | |
427 | pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); | |
428 | } | |
429 | } | |
430 | ||
026816fc RM |
431 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ |
432 | static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) | |
433 | { | |
434 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
435 | ||
436 | b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); | |
437 | if (core == 0) { | |
438 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); | |
439 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
440 | } else { | |
441 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
442 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
443 | } | |
444 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); | |
445 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); | |
446 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); | |
447 | b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); | |
448 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); | |
449 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); | |
450 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
451 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
452 | } | |
453 | ||
454 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ | |
455 | static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) | |
456 | { | |
457 | u8 rxval, txval; | |
458 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
459 | ||
460 | regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
461 | if (core == 0) { | |
462 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
463 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
464 | } else { | |
465 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
466 | regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
467 | } | |
468 | regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
469 | regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
470 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); | |
471 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); | |
472 | regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); | |
473 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); | |
474 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
475 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
476 | ||
477 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
478 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
479 | ||
480 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
481 | ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
482 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
483 | ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); | |
484 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, | |
485 | (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); | |
486 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, | |
487 | (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); | |
488 | ||
489 | if (core == 0) { | |
490 | b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); | |
491 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); | |
492 | } else { | |
493 | b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); | |
494 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); | |
495 | } | |
496 | ||
67cbc3ed RM |
497 | b43_nphy_rf_control_intc_override(dev, 2, 0, 3); |
498 | b43_nphy_rf_control_override(dev, 8, 0, 3, false); | |
67c0d6e2 | 499 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
026816fc RM |
500 | |
501 | if (core == 0) { | |
502 | rxval = 1; | |
503 | txval = 8; | |
504 | } else { | |
505 | rxval = 4; | |
506 | txval = 2; | |
507 | } | |
67cbc3ed RM |
508 | b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1)); |
509 | b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core)); | |
026816fc RM |
510 | } |
511 | ||
34a56f2c RM |
512 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ |
513 | static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) | |
514 | { | |
515 | int i; | |
516 | s32 iq; | |
517 | u32 ii; | |
518 | u32 qq; | |
519 | int iq_nbits, qq_nbits; | |
520 | int arsh, brsh; | |
521 | u16 tmp, a, b; | |
522 | ||
523 | struct nphy_iq_est est; | |
524 | struct b43_phy_n_iq_comp old; | |
525 | struct b43_phy_n_iq_comp new = { }; | |
526 | bool error = false; | |
527 | ||
528 | if (mask == 0) | |
529 | return; | |
530 | ||
531 | b43_nphy_rx_iq_coeffs(dev, false, &old); | |
532 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
533 | b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); | |
534 | new = old; | |
535 | ||
536 | for (i = 0; i < 2; i++) { | |
537 | if (i == 0 && (mask & 1)) { | |
538 | iq = est.iq0_prod; | |
539 | ii = est.i0_pwr; | |
540 | qq = est.q0_pwr; | |
541 | } else if (i == 1 && (mask & 2)) { | |
542 | iq = est.iq1_prod; | |
543 | ii = est.i1_pwr; | |
544 | qq = est.q1_pwr; | |
545 | } else { | |
546 | B43_WARN_ON(1); | |
547 | continue; | |
548 | } | |
549 | ||
550 | if (ii + qq < 2) { | |
551 | error = true; | |
552 | break; | |
553 | } | |
554 | ||
555 | iq_nbits = fls(abs(iq)); | |
556 | qq_nbits = fls(qq); | |
557 | ||
558 | arsh = iq_nbits - 20; | |
559 | if (arsh >= 0) { | |
560 | a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); | |
561 | tmp = ii >> arsh; | |
562 | } else { | |
563 | a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); | |
564 | tmp = ii << -arsh; | |
565 | } | |
566 | if (tmp == 0) { | |
567 | error = true; | |
568 | break; | |
569 | } | |
570 | a /= tmp; | |
571 | ||
572 | brsh = qq_nbits - 11; | |
573 | if (brsh >= 0) { | |
574 | b = (qq << (31 - qq_nbits)); | |
575 | tmp = ii >> brsh; | |
576 | } else { | |
577 | b = (qq << (31 - qq_nbits)); | |
578 | tmp = ii << -brsh; | |
579 | } | |
580 | if (tmp == 0) { | |
581 | error = true; | |
582 | break; | |
583 | } | |
584 | b = int_sqrt(b / tmp - a * a) - (1 << 10); | |
585 | ||
586 | if (i == 0 && (mask & 0x1)) { | |
587 | if (dev->phy.rev >= 3) { | |
588 | new.a0 = a & 0x3FF; | |
589 | new.b0 = b & 0x3FF; | |
590 | } else { | |
591 | new.a0 = b & 0x3FF; | |
592 | new.b0 = a & 0x3FF; | |
593 | } | |
594 | } else if (i == 1 && (mask & 0x2)) { | |
595 | if (dev->phy.rev >= 3) { | |
596 | new.a1 = a & 0x3FF; | |
597 | new.b1 = b & 0x3FF; | |
598 | } else { | |
599 | new.a1 = b & 0x3FF; | |
600 | new.b1 = a & 0x3FF; | |
601 | } | |
602 | } | |
603 | } | |
604 | ||
605 | if (error) | |
606 | new = old; | |
607 | ||
608 | b43_nphy_rx_iq_coeffs(dev, true, &new); | |
609 | } | |
610 | ||
09146400 RM |
611 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ |
612 | static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) | |
613 | { | |
614 | u16 array[4]; | |
615 | int i; | |
616 | ||
617 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50); | |
618 | for (i = 0; i < 4; i++) | |
619 | array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO); | |
620 | ||
621 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); | |
622 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); | |
623 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); | |
624 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); | |
625 | } | |
626 | ||
bbec398c RM |
627 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ |
628 | static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
629 | { | |
630 | b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); | |
631 | b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); | |
632 | } | |
633 | ||
634 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ | |
635 | static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) | |
636 | { | |
637 | clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); | |
638 | clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); | |
639 | } | |
640 | ||
8987a9e9 RM |
641 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ |
642 | static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) | |
643 | { | |
644 | if (dev->phy.rev >= 3) { | |
645 | if (!init) | |
646 | return; | |
647 | if (0 /* FIXME */) { | |
648 | b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); | |
649 | b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); | |
650 | b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); | |
651 | b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); | |
652 | } | |
653 | } else { | |
654 | b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); | |
655 | b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); | |
656 | ||
657 | ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00, | |
658 | 0xFC00); | |
659 | b43_write32(dev, B43_MMIO_MACCTL, | |
660 | b43_read32(dev, B43_MMIO_MACCTL) & | |
661 | ~B43_MACCTL_GPOUTSMSK); | |
662 | b43_write16(dev, B43_MMIO_GPIO_MASK, | |
663 | b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00); | |
664 | b43_write16(dev, B43_MMIO_GPIO_CONTROL, | |
665 | b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00); | |
666 | ||
667 | if (init) { | |
668 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | |
669 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | |
670 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | |
671 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | |
672 | } | |
673 | } | |
674 | } | |
675 | ||
bbec398c RM |
676 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ |
677 | static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) | |
678 | { | |
679 | u16 tmp; | |
680 | ||
681 | if (dev->dev->id.revision == 16) | |
682 | b43_mac_suspend(dev); | |
683 | ||
684 | tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); | |
685 | tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | | |
686 | B43_NPHY_CLASSCTL_WAITEDEN); | |
687 | tmp &= ~mask; | |
688 | tmp |= (val & mask); | |
689 | b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); | |
690 | ||
691 | if (dev->dev->id.revision == 16) | |
692 | b43_mac_enable(dev); | |
693 | ||
694 | return tmp; | |
695 | } | |
696 | ||
5c1a140a RM |
697 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ |
698 | static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) | |
699 | { | |
700 | struct b43_phy *phy = &dev->phy; | |
701 | struct b43_phy_n *nphy = phy->n; | |
702 | ||
703 | if (enable) { | |
704 | u16 clip[] = { 0xFFFF, 0xFFFF }; | |
705 | if (nphy->deaf_count++ == 0) { | |
706 | nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); | |
707 | b43_nphy_classifier(dev, 0x7, 0); | |
708 | b43_nphy_read_clip_detection(dev, nphy->clip_state); | |
709 | b43_nphy_write_clip_detection(dev, clip); | |
710 | } | |
711 | b43_nphy_reset_cca(dev); | |
712 | } else { | |
713 | if (--nphy->deaf_count == 0) { | |
714 | b43_nphy_classifier(dev, 0x7, nphy->classifier_state); | |
715 | b43_nphy_write_clip_detection(dev, nphy->clip_state); | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
53ae8e8c RM |
720 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ |
721 | static void b43_nphy_stop_playback(struct b43_wldev *dev) | |
722 | { | |
723 | struct b43_phy_n *nphy = dev->phy.n; | |
724 | u16 tmp; | |
725 | ||
726 | if (nphy->hang_avoid) | |
727 | b43_nphy_stay_in_carrier_search(dev, 1); | |
728 | ||
729 | tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); | |
730 | if (tmp & 0x1) | |
731 | b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); | |
732 | else if (tmp & 0x2) | |
733 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000); | |
734 | ||
735 | b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); | |
736 | ||
737 | if (nphy->bb_mult_save & 0x80000000) { | |
738 | tmp = nphy->bb_mult_save & 0xFFFF; | |
d41a3552 | 739 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); |
53ae8e8c RM |
740 | nphy->bb_mult_save = 0; |
741 | } | |
742 | ||
743 | if (nphy->hang_avoid) | |
744 | b43_nphy_stay_in_carrier_search(dev, 0); | |
745 | } | |
746 | ||
9442e5b5 RM |
747 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ |
748 | static void b43_nphy_spur_workaround(struct b43_wldev *dev) | |
749 | { | |
750 | struct b43_phy_n *nphy = dev->phy.n; | |
751 | ||
752 | unsigned int channel; | |
753 | int tone[2] = { 57, 58 }; | |
754 | u32 noise[2] = { 0x3FF, 0x3FF }; | |
755 | ||
756 | B43_WARN_ON(dev->phy.rev < 3); | |
757 | ||
758 | if (nphy->hang_avoid) | |
759 | b43_nphy_stay_in_carrier_search(dev, 1); | |
760 | ||
761 | /* FIXME: channel = radio_chanspec */ | |
762 | ||
763 | if (nphy->gband_spurwar_en) { | |
764 | /* TODO: N PHY Adjust Analog Pfbw (7) */ | |
765 | if (channel == 11 && dev->phy.is_40mhz) | |
766 | ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ | |
767 | else | |
768 | ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ | |
769 | /* TODO: N PHY Adjust CRS Min Power (0x1E) */ | |
770 | } | |
771 | ||
772 | if (nphy->aband_spurwar_en) { | |
773 | if (channel == 54) { | |
774 | tone[0] = 0x20; | |
775 | noise[0] = 0x25F; | |
776 | } else if (channel == 38 || channel == 102 || channel == 118) { | |
777 | if (0 /* FIXME */) { | |
778 | tone[0] = 0x20; | |
779 | noise[0] = 0x21F; | |
780 | } else { | |
781 | tone[0] = 0; | |
782 | noise[0] = 0; | |
783 | } | |
784 | } else if (channel == 134) { | |
785 | tone[0] = 0x20; | |
786 | noise[0] = 0x21F; | |
787 | } else if (channel == 151) { | |
788 | tone[0] = 0x10; | |
789 | noise[0] = 0x23F; | |
790 | } else if (channel == 153 || channel == 161) { | |
791 | tone[0] = 0x30; | |
792 | noise[0] = 0x23F; | |
793 | } else { | |
794 | tone[0] = 0; | |
795 | noise[0] = 0; | |
796 | } | |
797 | ||
798 | if (!tone[0] && !noise[0]) | |
799 | ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ | |
800 | else | |
801 | ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ | |
802 | } | |
803 | ||
804 | if (nphy->hang_avoid) | |
805 | b43_nphy_stay_in_carrier_search(dev, 0); | |
806 | } | |
807 | ||
ef5127a4 RM |
808 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ |
809 | static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev) | |
810 | { | |
811 | struct b43_phy_n *nphy = dev->phy.n; | |
812 | u8 i, j; | |
813 | u8 code; | |
814 | ||
815 | /* TODO: for PHY >= 3 | |
816 | s8 *lna1_gain, *lna2_gain; | |
817 | u8 *gain_db, *gain_bits; | |
818 | u16 *rfseq_init; | |
819 | u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; | |
820 | u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; | |
821 | */ | |
822 | ||
823 | u8 rfseq_events[3] = { 6, 8, 7 }; | |
824 | u8 rfseq_delays[3] = { 10, 30, 1 }; | |
825 | ||
826 | if (dev->phy.rev >= 3) { | |
827 | /* TODO */ | |
828 | } else { | |
829 | /* Set Clip 2 detect */ | |
830 | b43_phy_set(dev, B43_NPHY_C1_CGAINI, | |
831 | B43_NPHY_C1_CGAINI_CL2DETECT); | |
832 | b43_phy_set(dev, B43_NPHY_C2_CGAINI, | |
833 | B43_NPHY_C2_CGAINI_CL2DETECT); | |
834 | ||
835 | /* Set narrowband clip threshold */ | |
836 | b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); | |
837 | b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); | |
838 | ||
839 | if (!dev->phy.is_40mhz) { | |
840 | /* Set dwell lengths */ | |
841 | b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); | |
842 | b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); | |
843 | b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); | |
844 | b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); | |
845 | } | |
846 | ||
847 | /* Set wideband clip 2 threshold */ | |
848 | b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, | |
849 | ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, | |
850 | 21); | |
851 | b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, | |
852 | ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, | |
853 | 21); | |
854 | ||
855 | if (!dev->phy.is_40mhz) { | |
856 | b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, | |
857 | ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); | |
858 | b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, | |
859 | ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); | |
860 | b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, | |
861 | ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); | |
862 | b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, | |
863 | ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); | |
864 | } | |
865 | ||
866 | b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); | |
867 | ||
868 | if (nphy->gain_boost) { | |
869 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && | |
870 | dev->phy.is_40mhz) | |
871 | code = 4; | |
872 | else | |
873 | code = 5; | |
874 | } else { | |
875 | code = dev->phy.is_40mhz ? 6 : 7; | |
876 | } | |
877 | ||
878 | /* Set HPVGA2 index */ | |
879 | b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, | |
880 | ~B43_NPHY_C1_INITGAIN_HPVGA2, | |
881 | code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); | |
882 | b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, | |
883 | ~B43_NPHY_C2_INITGAIN_HPVGA2, | |
884 | code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); | |
885 | ||
886 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
887 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
888 | (code << 8 | 0x7C)); | |
889 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
890 | (code << 8 | 0x7C)); | |
891 | ||
892 | /* TODO: b43_nphy_adjust_lna_gain_table(dev); */ | |
893 | ||
894 | if (nphy->elna_gain_config) { | |
895 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); | |
896 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
897 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
898 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
899 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
900 | ||
901 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); | |
902 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); | |
903 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
904 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
905 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); | |
906 | ||
907 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); | |
908 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
909 | (code << 8 | 0x74)); | |
910 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
911 | (code << 8 | 0x74)); | |
912 | } | |
913 | ||
914 | if (dev->phy.rev == 2) { | |
915 | for (i = 0; i < 4; i++) { | |
916 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
917 | (0x0400 * i) + 0x0020); | |
918 | for (j = 0; j < 21; j++) | |
919 | b43_phy_write(dev, | |
920 | B43_NPHY_TABLE_DATALO, 3 * j); | |
921 | } | |
922 | ||
9501fefe RM |
923 | b43_nphy_set_rf_sequence(dev, 5, |
924 | rfseq_events, rfseq_delays, 3); | |
ef5127a4 RM |
925 | b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, |
926 | (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV, | |
927 | 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); | |
928 | ||
929 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
930 | b43_phy_maskset(dev, B43_PHY_N(0xC5D), | |
931 | 0xFF80, 4); | |
932 | } | |
933 | } | |
934 | } | |
935 | ||
28fd7daa RM |
936 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ |
937 | static void b43_nphy_workarounds(struct b43_wldev *dev) | |
938 | { | |
939 | struct ssb_bus *bus = dev->dev->bus; | |
940 | struct b43_phy *phy = &dev->phy; | |
941 | struct b43_phy_n *nphy = phy->n; | |
942 | ||
943 | u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; | |
944 | u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; | |
945 | ||
946 | u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; | |
947 | u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; | |
948 | ||
949 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
950 | b43_nphy_classifier(dev, 1, 0); | |
951 | else | |
952 | b43_nphy_classifier(dev, 1, 1); | |
953 | ||
954 | if (nphy->hang_avoid) | |
955 | b43_nphy_stay_in_carrier_search(dev, 1); | |
956 | ||
957 | b43_phy_set(dev, B43_NPHY_IQFLIP, | |
958 | B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); | |
959 | ||
960 | if (dev->phy.rev >= 3) { | |
961 | /* TODO */ | |
962 | } else { | |
963 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && | |
964 | nphy->band5g_pwrgain) { | |
965 | b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); | |
966 | b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); | |
967 | } else { | |
968 | b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); | |
969 | b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); | |
970 | } | |
971 | ||
972 | /* TODO: convert to b43_ntab_write? */ | |
973 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000); | |
974 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
975 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010); | |
976 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A); | |
977 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002); | |
978 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
979 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012); | |
980 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA); | |
981 | ||
982 | if (dev->phy.rev < 2) { | |
983 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008); | |
984 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
985 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018); | |
986 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000); | |
987 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007); | |
988 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
989 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017); | |
990 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB); | |
991 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006); | |
992 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
993 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016); | |
994 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800); | |
995 | } | |
996 | ||
997 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); | |
998 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); | |
999 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); | |
1000 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); | |
1001 | ||
1002 | if (bus->sprom.boardflags2_lo & 0x100 && | |
1003 | bus->boardinfo.type == 0x8B) { | |
1004 | delays1[0] = 0x1; | |
1005 | delays1[5] = 0x14; | |
1006 | } | |
9501fefe RM |
1007 | b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); |
1008 | b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); | |
28fd7daa | 1009 | |
ef5127a4 | 1010 | b43_nphy_gain_crtl_workarounds(dev); |
28fd7daa RM |
1011 | |
1012 | if (dev->phy.rev < 2) { | |
1013 | if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) | |
1014 | ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/ | |
1015 | } else if (dev->phy.rev == 2) { | |
1016 | b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); | |
1017 | b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); | |
1018 | } | |
1019 | ||
1020 | if (dev->phy.rev < 2) | |
1021 | b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, | |
1022 | ~B43_NPHY_SCRAM_SIGCTL_SCM); | |
1023 | ||
1024 | /* Set phase track alpha and beta */ | |
1025 | b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); | |
1026 | b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); | |
1027 | b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); | |
1028 | b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); | |
1029 | b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); | |
1030 | b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); | |
1031 | ||
1032 | b43_phy_mask(dev, B43_NPHY_PIL_DW1, | |
1033 | (u16)~B43_NPHY_PIL_DW_64QAM); | |
1034 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); | |
1035 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); | |
1036 | b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); | |
1037 | ||
1038 | if (dev->phy.rev == 2) | |
1039 | b43_phy_set(dev, B43_NPHY_FINERX2_CGC, | |
1040 | B43_NPHY_FINERX2_CGC_DECGC); | |
1041 | } | |
1042 | ||
1043 | if (nphy->hang_avoid) | |
1044 | b43_nphy_stay_in_carrier_search(dev, 0); | |
1045 | } | |
1046 | ||
5f6393ec RM |
1047 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ |
1048 | static int b43_nphy_load_samples(struct b43_wldev *dev, | |
1049 | struct b43_c32 *samples, u16 len) { | |
1050 | struct b43_phy_n *nphy = dev->phy.n; | |
1051 | u16 i; | |
1052 | u32 *data; | |
1053 | ||
1054 | data = kzalloc(len * sizeof(u32), GFP_KERNEL); | |
1055 | if (!data) { | |
1056 | b43err(dev->wl, "allocation for samples loading failed\n"); | |
1057 | return -ENOMEM; | |
1058 | } | |
1059 | if (nphy->hang_avoid) | |
1060 | b43_nphy_stay_in_carrier_search(dev, 1); | |
1061 | ||
1062 | for (i = 0; i < len; i++) { | |
1063 | data[i] = (samples[i].i & 0x3FF << 10); | |
1064 | data[i] |= samples[i].q & 0x3FF; | |
1065 | } | |
1066 | b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); | |
1067 | ||
1068 | kfree(data); | |
1069 | if (nphy->hang_avoid) | |
1070 | b43_nphy_stay_in_carrier_search(dev, 0); | |
1071 | return 0; | |
1072 | } | |
1073 | ||
59af099b RM |
1074 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ |
1075 | static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, | |
1076 | bool test) | |
1077 | { | |
1078 | int i; | |
f2982181 | 1079 | u16 bw, len, rot, angle; |
da860475 | 1080 | struct b43_c32 *samples; |
f2982181 | 1081 | |
59af099b RM |
1082 | |
1083 | bw = (dev->phy.is_40mhz) ? 40 : 20; | |
1084 | len = bw << 3; | |
1085 | ||
1086 | if (test) { | |
1087 | if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) | |
1088 | bw = 82; | |
1089 | else | |
1090 | bw = 80; | |
1091 | ||
1092 | if (dev->phy.is_40mhz) | |
1093 | bw <<= 1; | |
1094 | ||
1095 | len = bw << 1; | |
1096 | } | |
1097 | ||
da860475 | 1098 | samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL); |
40bd5203 RM |
1099 | if (!samples) { |
1100 | b43err(dev->wl, "allocation for samples generation failed\n"); | |
1101 | return 0; | |
1102 | } | |
59af099b RM |
1103 | rot = (((freq * 36) / bw) << 16) / 100; |
1104 | angle = 0; | |
1105 | ||
f2982181 RM |
1106 | for (i = 0; i < len; i++) { |
1107 | samples[i] = b43_cordic(angle); | |
1108 | angle += rot; | |
1109 | samples[i].q = CORDIC_CONVERT(samples[i].q * max); | |
1110 | samples[i].i = CORDIC_CONVERT(samples[i].i * max); | |
59af099b RM |
1111 | } |
1112 | ||
5f6393ec | 1113 | i = b43_nphy_load_samples(dev, samples, len); |
f2982181 | 1114 | kfree(samples); |
5f6393ec | 1115 | return (i < 0) ? 0 : len; |
59af099b RM |
1116 | } |
1117 | ||
10a79873 RM |
1118 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ |
1119 | static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, | |
1120 | u16 wait, bool iqmode, bool dac_test) | |
1121 | { | |
1122 | struct b43_phy_n *nphy = dev->phy.n; | |
1123 | int i; | |
1124 | u16 seq_mode; | |
1125 | u32 tmp; | |
1126 | ||
1127 | if (nphy->hang_avoid) | |
1128 | b43_nphy_stay_in_carrier_search(dev, true); | |
1129 | ||
1130 | if ((nphy->bb_mult_save & 0x80000000) == 0) { | |
1131 | tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); | |
1132 | nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; | |
1133 | } | |
1134 | ||
1135 | if (!dev->phy.is_40mhz) | |
1136 | tmp = 0x6464; | |
1137 | else | |
1138 | tmp = 0x4747; | |
1139 | b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); | |
1140 | ||
1141 | if (nphy->hang_avoid) | |
1142 | b43_nphy_stay_in_carrier_search(dev, false); | |
1143 | ||
1144 | b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); | |
1145 | ||
1146 | if (loops != 0xFFFF) | |
1147 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); | |
1148 | else | |
1149 | b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); | |
1150 | ||
1151 | b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); | |
1152 | ||
1153 | seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); | |
1154 | ||
1155 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); | |
1156 | if (iqmode) { | |
1157 | b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); | |
1158 | b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); | |
1159 | } else { | |
1160 | if (dac_test) | |
1161 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5); | |
1162 | else | |
1163 | b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1); | |
1164 | } | |
1165 | for (i = 0; i < 100; i++) { | |
1166 | if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) { | |
1167 | i = 0; | |
1168 | break; | |
1169 | } | |
1170 | udelay(10); | |
1171 | } | |
1172 | if (i) | |
1173 | b43err(dev->wl, "run samples timeout\n"); | |
1174 | ||
1175 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); | |
1176 | } | |
1177 | ||
59af099b RM |
1178 | /* |
1179 | * Transmits a known value for LO calibration | |
1180 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone | |
1181 | */ | |
1182 | static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, | |
1183 | bool iqmode, bool dac_test) | |
1184 | { | |
1185 | u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); | |
1186 | if (samp == 0) | |
1187 | return -1; | |
1188 | b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test); | |
1189 | return 0; | |
1190 | } | |
1191 | ||
6dcd9d91 RM |
1192 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ |
1193 | static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) | |
1194 | { | |
1195 | struct b43_phy_n *nphy = dev->phy.n; | |
1196 | int i, j; | |
1197 | u32 tmp; | |
1198 | u32 cur_real, cur_imag, real_part, imag_part; | |
1199 | ||
1200 | u16 buffer[7]; | |
1201 | ||
1202 | if (nphy->hang_avoid) | |
1203 | b43_nphy_stay_in_carrier_search(dev, true); | |
1204 | ||
9145834e | 1205 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); |
6dcd9d91 RM |
1206 | |
1207 | for (i = 0; i < 2; i++) { | |
1208 | tmp = ((buffer[i * 2] & 0x3FF) << 10) | | |
1209 | (buffer[i * 2 + 1] & 0x3FF); | |
1210 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1211 | (((i + 26) << 10) | 320)); | |
1212 | for (j = 0; j < 128; j++) { | |
1213 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1214 | ((tmp >> 16) & 0xFFFF)); | |
1215 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1216 | (tmp & 0xFFFF)); | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | for (i = 0; i < 2; i++) { | |
1221 | tmp = buffer[5 + i]; | |
1222 | real_part = (tmp >> 8) & 0xFF; | |
1223 | imag_part = (tmp & 0xFF); | |
1224 | b43_phy_write(dev, B43_NPHY_TABLE_ADDR, | |
1225 | (((i + 26) << 10) | 448)); | |
1226 | ||
1227 | if (dev->phy.rev >= 3) { | |
1228 | cur_real = real_part; | |
1229 | cur_imag = imag_part; | |
1230 | tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); | |
1231 | } | |
1232 | ||
1233 | for (j = 0; j < 128; j++) { | |
1234 | if (dev->phy.rev < 3) { | |
1235 | cur_real = (real_part * loscale[j] + 128) >> 8; | |
1236 | cur_imag = (imag_part * loscale[j] + 128) >> 8; | |
1237 | tmp = ((cur_real & 0xFF) << 8) | | |
1238 | (cur_imag & 0xFF); | |
1239 | } | |
1240 | b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, | |
1241 | ((tmp >> 16) & 0xFFFF)); | |
1242 | b43_phy_write(dev, B43_NPHY_TABLE_DATALO, | |
1243 | (tmp & 0xFFFF)); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | if (dev->phy.rev >= 3) { | |
1248 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1249 | B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); | |
1250 | b43_shm_write16(dev, B43_SHM_SHARED, | |
1251 | B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); | |
1252 | } | |
1253 | ||
1254 | if (nphy->hang_avoid) | |
1255 | b43_nphy_stay_in_carrier_search(dev, false); | |
1256 | } | |
1257 | ||
9501fefe RM |
1258 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ |
1259 | static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, | |
1260 | u8 *events, u8 *delays, u8 length) | |
1261 | { | |
1262 | struct b43_phy_n *nphy = dev->phy.n; | |
1263 | u8 i; | |
1264 | u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; | |
1265 | u16 offset1 = cmd << 4; | |
1266 | u16 offset2 = offset1 + 0x80; | |
1267 | ||
1268 | if (nphy->hang_avoid) | |
1269 | b43_nphy_stay_in_carrier_search(dev, true); | |
1270 | ||
1271 | b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); | |
1272 | b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); | |
1273 | ||
1274 | for (i = length; i < 16; i++) { | |
1275 | b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); | |
1276 | b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); | |
1277 | } | |
1278 | ||
1279 | if (nphy->hang_avoid) | |
1280 | b43_nphy_stay_in_carrier_search(dev, false); | |
1281 | } | |
1282 | ||
67c0d6e2 | 1283 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ |
95b66bad MB |
1284 | static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, |
1285 | enum b43_nphy_rf_sequence seq) | |
1286 | { | |
1287 | static const u16 trigger[] = { | |
1288 | [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, | |
1289 | [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, | |
1290 | [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, | |
1291 | [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, | |
1292 | [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, | |
1293 | [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, | |
1294 | }; | |
1295 | int i; | |
c57199bc | 1296 | u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); |
95b66bad MB |
1297 | |
1298 | B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); | |
1299 | ||
1300 | b43_phy_set(dev, B43_NPHY_RFSEQMODE, | |
1301 | B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); | |
1302 | b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); | |
1303 | for (i = 0; i < 200; i++) { | |
1304 | if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) | |
1305 | goto ok; | |
1306 | msleep(1); | |
1307 | } | |
1308 | b43err(dev->wl, "RF sequence status timeout\n"); | |
1309 | ok: | |
c57199bc | 1310 | b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); |
95b66bad MB |
1311 | } |
1312 | ||
75377b24 RM |
1313 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ |
1314 | static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field, | |
1315 | u16 value, u8 core, bool off) | |
1316 | { | |
1317 | int i; | |
1318 | u8 index = fls(field); | |
1319 | u8 addr, en_addr, val_addr; | |
1320 | /* we expect only one bit set */ | |
3ed0fac3 | 1321 | B43_WARN_ON(field & (~(1 << (index - 1)))); |
75377b24 RM |
1322 | |
1323 | if (dev->phy.rev >= 3) { | |
1324 | const struct nphy_rf_control_override_rev3 *rf_ctrl; | |
1325 | for (i = 0; i < 2; i++) { | |
1326 | if (index == 0 || index == 16) { | |
1327 | b43err(dev->wl, | |
1328 | "Unsupported RF Ctrl Override call\n"); | |
1329 | return; | |
1330 | } | |
1331 | ||
1332 | rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; | |
1333 | en_addr = B43_PHY_N((i == 0) ? | |
1334 | rf_ctrl->en_addr0 : rf_ctrl->en_addr1); | |
1335 | val_addr = B43_PHY_N((i == 0) ? | |
1336 | rf_ctrl->val_addr0 : rf_ctrl->val_addr1); | |
1337 | ||
1338 | if (off) { | |
1339 | b43_phy_mask(dev, en_addr, ~(field)); | |
1340 | b43_phy_mask(dev, val_addr, | |
1341 | ~(rf_ctrl->val_mask)); | |
1342 | } else { | |
1343 | if (core == 0 || ((1 << core) & i) != 0) { | |
1344 | b43_phy_set(dev, en_addr, field); | |
1345 | b43_phy_maskset(dev, val_addr, | |
1346 | ~(rf_ctrl->val_mask), | |
1347 | (value << rf_ctrl->val_shift)); | |
1348 | } | |
1349 | } | |
1350 | } | |
1351 | } else { | |
1352 | const struct nphy_rf_control_override_rev2 *rf_ctrl; | |
1353 | if (off) { | |
1354 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); | |
1355 | value = 0; | |
1356 | } else { | |
1357 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); | |
1358 | } | |
1359 | ||
1360 | for (i = 0; i < 2; i++) { | |
1361 | if (index <= 1 || index == 16) { | |
1362 | b43err(dev->wl, | |
1363 | "Unsupported RF Ctrl Override call\n"); | |
1364 | return; | |
1365 | } | |
1366 | ||
1367 | if (index == 2 || index == 10 || | |
1368 | (index >= 13 && index <= 15)) { | |
1369 | core = 1; | |
1370 | } | |
1371 | ||
1372 | rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; | |
1373 | addr = B43_PHY_N((i == 0) ? | |
1374 | rf_ctrl->addr0 : rf_ctrl->addr1); | |
1375 | ||
1376 | if ((core & (1 << i)) != 0) | |
1377 | b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), | |
1378 | (value << rf_ctrl->shift)); | |
1379 | ||
1380 | b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); | |
1381 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1382 | B43_NPHY_RFCTL_CMD_START); | |
1383 | udelay(1); | |
1384 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); | |
1385 | } | |
1386 | } | |
1387 | } | |
1388 | ||
67cbc3ed RM |
1389 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ |
1390 | static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field, | |
1391 | u16 value, u8 core) | |
1392 | { | |
1393 | u8 i, j; | |
1394 | u16 reg, tmp, val; | |
1395 | ||
1396 | B43_WARN_ON(dev->phy.rev < 3); | |
1397 | B43_WARN_ON(field > 4); | |
1398 | ||
1399 | for (i = 0; i < 2; i++) { | |
1400 | if ((core == 1 && i == 1) || (core == 2 && !i)) | |
1401 | continue; | |
1402 | ||
1403 | reg = (i == 0) ? | |
1404 | B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; | |
1405 | b43_phy_mask(dev, reg, 0xFBFF); | |
1406 | ||
1407 | switch (field) { | |
1408 | case 0: | |
1409 | b43_phy_write(dev, reg, 0); | |
1410 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); | |
1411 | break; | |
1412 | case 1: | |
1413 | if (!i) { | |
1414 | b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, | |
1415 | 0xFC3F, (value << 6)); | |
1416 | b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, | |
1417 | 0xFFFE, 1); | |
1418 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1419 | B43_NPHY_RFCTL_CMD_START); | |
1420 | for (j = 0; j < 100; j++) { | |
1421 | if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) { | |
1422 | j = 0; | |
1423 | break; | |
1424 | } | |
1425 | udelay(10); | |
1426 | } | |
1427 | if (j) | |
1428 | b43err(dev->wl, | |
1429 | "intc override timeout\n"); | |
1430 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, | |
1431 | 0xFFFE); | |
1432 | } else { | |
1433 | b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, | |
1434 | 0xFC3F, (value << 6)); | |
1435 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1436 | 0xFFFE, 1); | |
1437 | b43_phy_set(dev, B43_NPHY_RFCTL_CMD, | |
1438 | B43_NPHY_RFCTL_CMD_RXTX); | |
1439 | for (j = 0; j < 100; j++) { | |
1440 | if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) { | |
1441 | j = 0; | |
1442 | break; | |
1443 | } | |
1444 | udelay(10); | |
1445 | } | |
1446 | if (j) | |
1447 | b43err(dev->wl, | |
1448 | "intc override timeout\n"); | |
1449 | b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, | |
1450 | 0xFFFE); | |
1451 | } | |
1452 | break; | |
1453 | case 2: | |
1454 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1455 | tmp = 0x0020; | |
1456 | val = value << 5; | |
1457 | } else { | |
1458 | tmp = 0x0010; | |
1459 | val = value << 4; | |
1460 | } | |
1461 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1462 | break; | |
1463 | case 3: | |
1464 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1465 | tmp = 0x0001; | |
1466 | val = value; | |
1467 | } else { | |
1468 | tmp = 0x0004; | |
1469 | val = value << 2; | |
1470 | } | |
1471 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1472 | break; | |
1473 | case 4: | |
1474 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
1475 | tmp = 0x0002; | |
1476 | val = value << 1; | |
1477 | } else { | |
1478 | tmp = 0x0008; | |
1479 | val = value << 3; | |
1480 | } | |
1481 | b43_phy_maskset(dev, reg, ~tmp, val); | |
1482 | break; | |
1483 | } | |
1484 | } | |
1485 | } | |
1486 | ||
95b66bad MB |
1487 | static void b43_nphy_bphy_init(struct b43_wldev *dev) |
1488 | { | |
1489 | unsigned int i; | |
1490 | u16 val; | |
1491 | ||
1492 | val = 0x1E1F; | |
1493 | for (i = 0; i < 14; i++) { | |
1494 | b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); | |
1495 | val -= 0x202; | |
1496 | } | |
1497 | val = 0x3E3F; | |
1498 | for (i = 0; i < 16; i++) { | |
1499 | b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val); | |
1500 | val -= 0x202; | |
1501 | } | |
1502 | b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); | |
1503 | } | |
1504 | ||
3c95627d RM |
1505 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ |
1506 | static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, | |
1507 | s8 offset, u8 core, u8 rail, u8 type) | |
1508 | { | |
1509 | u16 tmp; | |
1510 | bool core1or5 = (core == 1) || (core == 5); | |
1511 | bool core2or5 = (core == 2) || (core == 5); | |
1512 | ||
1513 | offset = clamp_val(offset, -32, 31); | |
1514 | tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); | |
1515 | ||
1516 | if (core1or5 && (rail == 0) && (type == 2)) | |
1517 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); | |
1518 | if (core1or5 && (rail == 1) && (type == 2)) | |
1519 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); | |
1520 | if (core2or5 && (rail == 0) && (type == 2)) | |
1521 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); | |
1522 | if (core2or5 && (rail == 1) && (type == 2)) | |
1523 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); | |
1524 | if (core1or5 && (rail == 0) && (type == 0)) | |
1525 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); | |
1526 | if (core1or5 && (rail == 1) && (type == 0)) | |
1527 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); | |
1528 | if (core2or5 && (rail == 0) && (type == 0)) | |
1529 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); | |
1530 | if (core2or5 && (rail == 1) && (type == 0)) | |
1531 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); | |
1532 | if (core1or5 && (rail == 0) && (type == 1)) | |
1533 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); | |
1534 | if (core1or5 && (rail == 1) && (type == 1)) | |
1535 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); | |
1536 | if (core2or5 && (rail == 0) && (type == 1)) | |
1537 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); | |
1538 | if (core2or5 && (rail == 1) && (type == 1)) | |
1539 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); | |
1540 | if (core1or5 && (rail == 0) && (type == 6)) | |
1541 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); | |
1542 | if (core1or5 && (rail == 1) && (type == 6)) | |
1543 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); | |
1544 | if (core2or5 && (rail == 0) && (type == 6)) | |
1545 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); | |
1546 | if (core2or5 && (rail == 1) && (type == 6)) | |
1547 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); | |
1548 | if (core1or5 && (rail == 0) && (type == 3)) | |
1549 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); | |
1550 | if (core1or5 && (rail == 1) && (type == 3)) | |
1551 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); | |
1552 | if (core2or5 && (rail == 0) && (type == 3)) | |
1553 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); | |
1554 | if (core2or5 && (rail == 1) && (type == 3)) | |
1555 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); | |
1556 | if (core1or5 && (type == 4)) | |
1557 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); | |
1558 | if (core2or5 && (type == 4)) | |
1559 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); | |
1560 | if (core1or5 && (type == 5)) | |
1561 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); | |
1562 | if (core2or5 && (type == 5)) | |
1563 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); | |
1564 | } | |
1565 | ||
99b82c41 | 1566 | static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type) |
3c95627d RM |
1567 | { |
1568 | u16 val; | |
1569 | ||
99b82c41 RM |
1570 | if (type < 3) |
1571 | val = 0; | |
1572 | else if (type == 6) | |
1573 | val = 1; | |
1574 | else if (type == 3) | |
1575 | val = 2; | |
1576 | else | |
1577 | val = 3; | |
1578 | ||
1579 | val = (val << 12) | (val << 14); | |
1580 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); | |
1581 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); | |
3c95627d | 1582 | |
99b82c41 RM |
1583 | if (type < 3) { |
1584 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, | |
1585 | (type + 1) << 4); | |
1586 | b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, | |
1587 | (type + 1) << 4); | |
1588 | } | |
3c95627d | 1589 | |
99b82c41 RM |
1590 | /* TODO use some definitions */ |
1591 | if (code == 0) { | |
1592 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0); | |
3c95627d | 1593 | if (type < 3) { |
99b82c41 RM |
1594 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0); |
1595 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0); | |
1596 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0); | |
1597 | udelay(20); | |
1598 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); | |
3c95627d | 1599 | } |
99b82c41 RM |
1600 | } else { |
1601 | b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, | |
1602 | 0x3000); | |
1603 | if (type < 3) { | |
1604 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, | |
1605 | 0xFEC7, 0x0180); | |
1606 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, | |
1607 | 0xEFDC, (code << 1 | 0x1021)); | |
1608 | b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1); | |
1609 | udelay(20); | |
1610 | b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0); | |
3c95627d RM |
1611 | } |
1612 | } | |
1613 | } | |
1614 | ||
99b82c41 RM |
1615 | static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type) |
1616 | { | |
6e3b15a9 RM |
1617 | struct b43_phy_n *nphy = dev->phy.n; |
1618 | u8 i; | |
1619 | u16 reg, val; | |
1620 | ||
1621 | if (code == 0) { | |
1622 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); | |
1623 | b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); | |
1624 | b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); | |
1625 | b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); | |
1626 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); | |
1627 | b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); | |
1628 | b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); | |
1629 | b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); | |
1630 | } else { | |
1631 | for (i = 0; i < 2; i++) { | |
1632 | if ((code == 1 && i == 1) || (code == 2 && !i)) | |
1633 | continue; | |
1634 | ||
1635 | reg = (i == 0) ? | |
1636 | B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; | |
1637 | b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); | |
1638 | ||
1639 | if (type < 3) { | |
1640 | reg = (i == 0) ? | |
1641 | B43_NPHY_AFECTL_C1 : | |
1642 | B43_NPHY_AFECTL_C2; | |
1643 | b43_phy_maskset(dev, reg, 0xFCFF, 0); | |
1644 | ||
1645 | reg = (i == 0) ? | |
1646 | B43_NPHY_RFCTL_LUT_TRSW_UP1 : | |
1647 | B43_NPHY_RFCTL_LUT_TRSW_UP2; | |
1648 | b43_phy_maskset(dev, reg, 0xFFC3, 0); | |
1649 | ||
1650 | if (type == 0) | |
1651 | val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; | |
1652 | else if (type == 1) | |
1653 | val = 16; | |
1654 | else | |
1655 | val = 32; | |
1656 | b43_phy_set(dev, reg, val); | |
1657 | ||
1658 | reg = (i == 0) ? | |
1659 | B43_NPHY_TXF_40CO_B1S0 : | |
1660 | B43_NPHY_TXF_40CO_B32S1; | |
1661 | b43_phy_set(dev, reg, 0x0020); | |
1662 | } else { | |
1663 | if (type == 6) | |
1664 | val = 0x0100; | |
1665 | else if (type == 3) | |
1666 | val = 0x0200; | |
1667 | else | |
1668 | val = 0x0300; | |
1669 | ||
1670 | reg = (i == 0) ? | |
1671 | B43_NPHY_AFECTL_C1 : | |
1672 | B43_NPHY_AFECTL_C2; | |
1673 | ||
1674 | b43_phy_maskset(dev, reg, 0xFCFF, val); | |
1675 | b43_phy_maskset(dev, reg, 0xF3FF, val << 2); | |
1676 | ||
1677 | if (type != 3 && type != 6) { | |
1678 | enum ieee80211_band band = | |
1679 | b43_current_band(dev->wl); | |
1680 | ||
1681 | if ((nphy->ipa2g_on && | |
1682 | band == IEEE80211_BAND_2GHZ) || | |
1683 | (nphy->ipa5g_on && | |
1684 | band == IEEE80211_BAND_5GHZ)) | |
1685 | val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; | |
1686 | else | |
1687 | val = 0x11; | |
1688 | reg = (i == 0) ? 0x2000 : 0x3000; | |
1689 | reg |= B2055_PADDRV; | |
1690 | b43_radio_write16(dev, reg, val); | |
1691 | ||
1692 | reg = (i == 0) ? | |
1693 | B43_NPHY_AFECTL_OVER1 : | |
1694 | B43_NPHY_AFECTL_OVER; | |
1695 | b43_phy_set(dev, reg, 0x0200); | |
1696 | } | |
1697 | } | |
1698 | } | |
1699 | } | |
99b82c41 RM |
1700 | } |
1701 | ||
1702 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ | |
1703 | static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) | |
1704 | { | |
1705 | if (dev->phy.rev >= 3) | |
1706 | b43_nphy_rev3_rssi_select(dev, code, type); | |
1707 | else | |
1708 | b43_nphy_rev2_rssi_select(dev, code, type); | |
1709 | } | |
1710 | ||
dfb4aa5d RM |
1711 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ |
1712 | static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) | |
1713 | { | |
1714 | int i; | |
1715 | for (i = 0; i < 2; i++) { | |
1716 | if (type == 2) { | |
1717 | if (i == 0) { | |
1718 | b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, | |
1719 | 0xFC, buf[0]); | |
1720 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1721 | 0xFC, buf[1]); | |
1722 | } else { | |
1723 | b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, | |
1724 | 0xFC, buf[2 * i]); | |
1725 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1726 | 0xFC, buf[2 * i + 1]); | |
1727 | } | |
1728 | } else { | |
1729 | if (i == 0) | |
1730 | b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, | |
1731 | 0xF3, buf[0] << 2); | |
1732 | else | |
1733 | b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, | |
1734 | 0xF3, buf[2 * i + 1] << 2); | |
1735 | } | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ | |
1740 | static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf, | |
1741 | u8 nsamp) | |
1742 | { | |
1743 | int i; | |
1744 | int out; | |
1745 | u16 save_regs_phy[9]; | |
1746 | u16 s[2]; | |
1747 | ||
1748 | if (dev->phy.rev >= 3) { | |
1749 | save_regs_phy[0] = b43_phy_read(dev, | |
1750 | B43_NPHY_RFCTL_LUT_TRSW_UP1); | |
1751 | save_regs_phy[1] = b43_phy_read(dev, | |
1752 | B43_NPHY_RFCTL_LUT_TRSW_UP2); | |
1753 | save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
1754 | save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
1755 | save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
1756 | save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
1757 | save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); | |
1758 | save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); | |
1759 | } | |
1760 | ||
1761 | b43_nphy_rssi_select(dev, 5, type); | |
1762 | ||
1763 | if (dev->phy.rev < 2) { | |
1764 | save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); | |
1765 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); | |
1766 | } | |
1767 | ||
1768 | for (i = 0; i < 4; i++) | |
1769 | buf[i] = 0; | |
1770 | ||
1771 | for (i = 0; i < nsamp; i++) { | |
1772 | if (dev->phy.rev < 2) { | |
1773 | s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); | |
1774 | s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); | |
1775 | } else { | |
1776 | s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); | |
1777 | s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); | |
1778 | } | |
1779 | ||
1780 | buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; | |
1781 | buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; | |
1782 | buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; | |
1783 | buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; | |
1784 | } | |
1785 | out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | | |
1786 | (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); | |
1787 | ||
1788 | if (dev->phy.rev < 2) | |
1789 | b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); | |
1790 | ||
1791 | if (dev->phy.rev >= 3) { | |
1792 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, | |
1793 | save_regs_phy[0]); | |
1794 | b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, | |
1795 | save_regs_phy[1]); | |
1796 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); | |
1797 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]); | |
1798 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); | |
1799 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); | |
1800 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); | |
1801 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); | |
1802 | } | |
1803 | ||
1804 | return out; | |
1805 | } | |
1806 | ||
4cb99775 RM |
1807 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ |
1808 | static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type) | |
95b66bad | 1809 | { |
90b9738d RM |
1810 | int i, j; |
1811 | u8 state[4]; | |
1812 | u8 code, val; | |
1813 | u16 class, override; | |
1814 | u8 regs_save_radio[2]; | |
1815 | u16 regs_save_phy[2]; | |
1816 | s8 offset[4]; | |
1817 | ||
1818 | u16 clip_state[2]; | |
1819 | u16 clip_off[2] = { 0xFFFF, 0xFFFF }; | |
1820 | s32 results_min[4] = { }; | |
1821 | u8 vcm_final[4] = { }; | |
1822 | s32 results[4][4] = { }; | |
1823 | s32 miniq[4][2] = { }; | |
1824 | ||
1825 | if (type == 2) { | |
1826 | code = 0; | |
1827 | val = 6; | |
1828 | } else if (type < 2) { | |
1829 | code = 25; | |
1830 | val = 4; | |
1831 | } else { | |
1832 | B43_WARN_ON(1); | |
1833 | return; | |
1834 | } | |
1835 | ||
1836 | class = b43_nphy_classifier(dev, 0, 0); | |
1837 | b43_nphy_classifier(dev, 7, 4); | |
1838 | b43_nphy_read_clip_detection(dev, clip_state); | |
1839 | b43_nphy_write_clip_detection(dev, clip_off); | |
1840 | ||
1841 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
1842 | override = 0x140; | |
1843 | else | |
1844 | override = 0x110; | |
1845 | ||
1846 | regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); | |
1847 | regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); | |
1848 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); | |
1849 | b43_radio_write16(dev, B2055_C1_PD_RXTX, val); | |
1850 | ||
1851 | regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
1852 | regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); | |
1853 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); | |
1854 | b43_radio_write16(dev, B2055_C2_PD_RXTX, val); | |
1855 | ||
1856 | state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; | |
1857 | state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; | |
1858 | b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); | |
1859 | b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); | |
1860 | state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; | |
1861 | state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; | |
1862 | ||
1863 | b43_nphy_rssi_select(dev, 5, type); | |
1864 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); | |
1865 | b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); | |
1866 | ||
1867 | for (i = 0; i < 4; i++) { | |
1868 | u8 tmp[4]; | |
1869 | for (j = 0; j < 4; j++) | |
1870 | tmp[j] = i; | |
1871 | if (type != 1) | |
1872 | b43_nphy_set_rssi_2055_vcm(dev, type, tmp); | |
1873 | b43_nphy_poll_rssi(dev, type, results[i], 8); | |
1874 | if (type < 2) | |
1875 | for (j = 0; j < 2; j++) | |
1876 | miniq[i][j] = min(results[i][2 * j], | |
1877 | results[i][2 * j + 1]); | |
1878 | } | |
1879 | ||
1880 | for (i = 0; i < 4; i++) { | |
1881 | s32 mind = 40; | |
1882 | u8 minvcm = 0; | |
1883 | s32 minpoll = 249; | |
1884 | s32 curr; | |
1885 | for (j = 0; j < 4; j++) { | |
1886 | if (type == 2) | |
1887 | curr = abs(results[j][i]); | |
1888 | else | |
1889 | curr = abs(miniq[j][i / 2] - code * 8); | |
1890 | ||
1891 | if (curr < mind) { | |
1892 | mind = curr; | |
1893 | minvcm = j; | |
1894 | } | |
1895 | ||
1896 | if (results[j][i] < minpoll) | |
1897 | minpoll = results[j][i]; | |
1898 | } | |
1899 | results_min[i] = minpoll; | |
1900 | vcm_final[i] = minvcm; | |
1901 | } | |
1902 | ||
1903 | if (type != 1) | |
1904 | b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); | |
1905 | ||
1906 | for (i = 0; i < 4; i++) { | |
1907 | offset[i] = (code * 8) - results[vcm_final[i]][i]; | |
1908 | ||
1909 | if (offset[i] < 0) | |
1910 | offset[i] = -((abs(offset[i]) + 4) / 8); | |
1911 | else | |
1912 | offset[i] = (offset[i] + 4) / 8; | |
1913 | ||
1914 | if (results_min[i] == 248) | |
1915 | offset[i] = code - 32; | |
1916 | ||
1917 | if (i % 2 == 0) | |
1918 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0, | |
1919 | type); | |
1920 | else | |
1921 | b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1, | |
1922 | type); | |
1923 | } | |
1924 | ||
1925 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); | |
1926 | b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]); | |
1927 | ||
1928 | switch (state[2]) { | |
1929 | case 1: | |
1930 | b43_nphy_rssi_select(dev, 1, 2); | |
1931 | break; | |
1932 | case 4: | |
1933 | b43_nphy_rssi_select(dev, 1, 0); | |
1934 | break; | |
1935 | case 2: | |
1936 | b43_nphy_rssi_select(dev, 1, 1); | |
1937 | break; | |
1938 | default: | |
1939 | b43_nphy_rssi_select(dev, 1, 1); | |
1940 | break; | |
1941 | } | |
1942 | ||
1943 | switch (state[3]) { | |
1944 | case 1: | |
1945 | b43_nphy_rssi_select(dev, 2, 2); | |
1946 | break; | |
1947 | case 4: | |
1948 | b43_nphy_rssi_select(dev, 2, 0); | |
1949 | break; | |
1950 | default: | |
1951 | b43_nphy_rssi_select(dev, 2, 1); | |
1952 | break; | |
1953 | } | |
1954 | ||
1955 | b43_nphy_rssi_select(dev, 0, type); | |
1956 | ||
1957 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); | |
1958 | b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); | |
1959 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); | |
1960 | b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); | |
1961 | ||
1962 | b43_nphy_classifier(dev, 7, class); | |
1963 | b43_nphy_write_clip_detection(dev, clip_state); | |
4cb99775 RM |
1964 | } |
1965 | ||
1966 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ | |
1967 | static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) | |
1968 | { | |
1969 | /* TODO */ | |
1970 | } | |
1971 | ||
1972 | /* | |
1973 | * RSSI Calibration | |
1974 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal | |
1975 | */ | |
1976 | static void b43_nphy_rssi_cal(struct b43_wldev *dev) | |
1977 | { | |
1978 | if (dev->phy.rev >= 3) { | |
1979 | b43_nphy_rev3_rssi_cal(dev); | |
1980 | } else { | |
1981 | b43_nphy_rev2_rssi_cal(dev, 2); | |
1982 | b43_nphy_rev2_rssi_cal(dev, 0); | |
1983 | b43_nphy_rev2_rssi_cal(dev, 1); | |
1984 | } | |
95b66bad MB |
1985 | } |
1986 | ||
42e1547e RM |
1987 | /* |
1988 | * Restore RSSI Calibration | |
1989 | * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal | |
1990 | */ | |
1991 | static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) | |
1992 | { | |
1993 | struct b43_phy_n *nphy = dev->phy.n; | |
1994 | ||
1995 | u16 *rssical_radio_regs = NULL; | |
1996 | u16 *rssical_phy_regs = NULL; | |
1997 | ||
1998 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
1999 | if (!nphy->rssical_chanspec_2G) | |
2000 | return; | |
2001 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; | |
2002 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; | |
2003 | } else { | |
2004 | if (!nphy->rssical_chanspec_5G) | |
2005 | return; | |
2006 | rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; | |
2007 | rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; | |
2008 | } | |
2009 | ||
2010 | /* TODO use some definitions */ | |
2011 | b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]); | |
2012 | b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]); | |
2013 | ||
2014 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); | |
2015 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); | |
2016 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); | |
2017 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); | |
2018 | ||
2019 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); | |
2020 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); | |
2021 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); | |
2022 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); | |
2023 | ||
2024 | b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); | |
2025 | b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); | |
2026 | b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); | |
2027 | b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); | |
2028 | } | |
2029 | ||
2f258b74 RM |
2030 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ |
2031 | static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev) | |
2032 | { | |
2033 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2034 | if (dev->phy.rev >= 6) { | |
2035 | /* TODO If the chip is 47162 | |
2036 | return txpwrctrl_tx_gain_ipa_rev5 */ | |
2037 | return txpwrctrl_tx_gain_ipa_rev6; | |
2038 | } else if (dev->phy.rev >= 5) { | |
2039 | return txpwrctrl_tx_gain_ipa_rev5; | |
2040 | } else { | |
2041 | return txpwrctrl_tx_gain_ipa; | |
2042 | } | |
2043 | } else { | |
2044 | return txpwrctrl_tx_gain_ipa_5g; | |
2045 | } | |
2046 | } | |
2047 | ||
c4a92003 RM |
2048 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ |
2049 | static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) | |
2050 | { | |
2051 | struct b43_phy_n *nphy = dev->phy.n; | |
2052 | u16 *save = nphy->tx_rx_cal_radio_saveregs; | |
52cb5e97 RM |
2053 | u16 tmp; |
2054 | u8 offset, i; | |
c4a92003 RM |
2055 | |
2056 | if (dev->phy.rev >= 3) { | |
52cb5e97 RM |
2057 | for (i = 0; i < 2; i++) { |
2058 | tmp = (i == 0) ? 0x2000 : 0x3000; | |
2059 | offset = i * 11; | |
2060 | ||
2061 | save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); | |
2062 | save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); | |
2063 | save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); | |
2064 | save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); | |
2065 | save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); | |
2066 | save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); | |
2067 | save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); | |
2068 | save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); | |
2069 | save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); | |
2070 | save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); | |
2071 | save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); | |
2072 | ||
2073 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
2074 | b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); | |
2075 | b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); | |
2076 | b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); | |
2077 | b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); | |
2078 | b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); | |
2079 | if (nphy->ipa5g_on) { | |
2080 | b43_radio_write16(dev, tmp | B2055_PADDRV, 4); | |
2081 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); | |
2082 | } else { | |
2083 | b43_radio_write16(dev, tmp | B2055_PADDRV, 0); | |
2084 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); | |
2085 | } | |
2086 | b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); | |
2087 | } else { | |
2088 | b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); | |
2089 | b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); | |
2090 | b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); | |
2091 | b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); | |
2092 | b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); | |
2093 | b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); | |
2094 | if (nphy->ipa2g_on) { | |
2095 | b43_radio_write16(dev, tmp | B2055_PADDRV, 6); | |
2096 | b43_radio_write16(dev, tmp | B2055_XOCTL2, | |
2097 | (dev->phy.rev < 5) ? 0x11 : 0x01); | |
2098 | } else { | |
2099 | b43_radio_write16(dev, tmp | B2055_PADDRV, 0); | |
2100 | b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); | |
2101 | } | |
2102 | } | |
2103 | b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); | |
2104 | b43_radio_write16(dev, tmp | B2055_XOMISC, 0); | |
2105 | b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); | |
2106 | } | |
c4a92003 RM |
2107 | } else { |
2108 | save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); | |
2109 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); | |
2110 | ||
2111 | save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); | |
2112 | b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); | |
2113 | ||
2114 | save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); | |
2115 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); | |
2116 | ||
2117 | save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); | |
2118 | b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); | |
2119 | ||
2120 | save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); | |
2121 | save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); | |
2122 | ||
2123 | if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & | |
2124 | B43_NPHY_BANDCTL_5GHZ)) { | |
2125 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); | |
2126 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); | |
2127 | } else { | |
2128 | b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); | |
2129 | b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); | |
2130 | } | |
2131 | ||
2132 | if (dev->phy.rev < 2) { | |
2133 | b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); | |
2134 | b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); | |
2135 | } else { | |
2136 | b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); | |
2137 | b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); | |
2138 | } | |
2139 | } | |
2140 | } | |
2141 | ||
e9762492 RM |
2142 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ |
2143 | static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, | |
2144 | struct nphy_txgains target, | |
2145 | struct nphy_iqcal_params *params) | |
2146 | { | |
2147 | int i, j, indx; | |
2148 | u16 gain; | |
2149 | ||
2150 | if (dev->phy.rev >= 3) { | |
2151 | params->txgm = target.txgm[core]; | |
2152 | params->pga = target.pga[core]; | |
2153 | params->pad = target.pad[core]; | |
2154 | params->ipa = target.ipa[core]; | |
2155 | params->cal_gain = (params->txgm << 12) | (params->pga << 8) | | |
2156 | (params->pad << 4) | (params->ipa); | |
2157 | for (j = 0; j < 5; j++) | |
2158 | params->ncorr[j] = 0x79; | |
2159 | } else { | |
2160 | gain = (target.pad[core]) | (target.pga[core] << 4) | | |
2161 | (target.txgm[core] << 8); | |
2162 | ||
2163 | indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? | |
2164 | 1 : 0; | |
2165 | for (i = 0; i < 9; i++) | |
2166 | if (tbl_iqcal_gainparams[indx][i][0] == gain) | |
2167 | break; | |
2168 | i = min(i, 8); | |
2169 | ||
2170 | params->txgm = tbl_iqcal_gainparams[indx][i][1]; | |
2171 | params->pga = tbl_iqcal_gainparams[indx][i][2]; | |
2172 | params->pad = tbl_iqcal_gainparams[indx][i][3]; | |
2173 | params->cal_gain = (params->txgm << 7) | (params->pga << 4) | | |
2174 | (params->pad << 2); | |
2175 | for (j = 0; j < 4; j++) | |
2176 | params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; | |
2177 | } | |
2178 | } | |
2179 | ||
de7ed0c6 RM |
2180 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ |
2181 | static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) | |
2182 | { | |
2183 | struct b43_phy_n *nphy = dev->phy.n; | |
2184 | int i; | |
2185 | u16 scale, entry; | |
2186 | ||
2187 | u16 tmp = nphy->txcal_bbmult; | |
2188 | if (core == 0) | |
2189 | tmp >>= 8; | |
2190 | tmp &= 0xff; | |
2191 | ||
2192 | for (i = 0; i < 18; i++) { | |
2193 | scale = (ladder_lo[i].percent * tmp) / 100; | |
2194 | entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; | |
d41a3552 | 2195 | b43_ntab_write(dev, B43_NTAB16(15, i), entry); |
de7ed0c6 RM |
2196 | |
2197 | scale = (ladder_iq[i].percent * tmp) / 100; | |
2198 | entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; | |
d41a3552 | 2199 | b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); |
de7ed0c6 RM |
2200 | } |
2201 | } | |
2202 | ||
45ca697e RM |
2203 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ |
2204 | static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
2205 | { | |
2206 | int i; | |
2207 | for (i = 0; i < 15; i++) | |
2208 | b43_phy_write(dev, B43_PHY_N(0x2C5 + i), | |
2209 | tbl_tx_filter_coef_rev4[2][i]); | |
2210 | } | |
2211 | ||
2212 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ | |
2213 | static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) | |
2214 | { | |
2215 | int i, j; | |
2216 | /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ | |
2217 | u16 offset[] = { 0x186, 0x195, 0x2C5 }; | |
2218 | ||
2219 | for (i = 0; i < 3; i++) | |
2220 | for (j = 0; j < 15; j++) | |
2221 | b43_phy_write(dev, B43_PHY_N(offset[i] + j), | |
2222 | tbl_tx_filter_coef_rev4[i][j]); | |
2223 | ||
2224 | if (dev->phy.is_40mhz) { | |
2225 | for (j = 0; j < 15; j++) | |
2226 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2227 | tbl_tx_filter_coef_rev4[3][j]); | |
2228 | } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { | |
2229 | for (j = 0; j < 15; j++) | |
2230 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2231 | tbl_tx_filter_coef_rev4[5][j]); | |
2232 | } | |
2233 | ||
2234 | if (dev->phy.channel == 14) | |
2235 | for (j = 0; j < 15; j++) | |
2236 | b43_phy_write(dev, B43_PHY_N(offset[0] + j), | |
2237 | tbl_tx_filter_coef_rev4[6][j]); | |
2238 | } | |
2239 | ||
b0022e15 RM |
2240 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ |
2241 | static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) | |
2242 | { | |
2243 | struct b43_phy_n *nphy = dev->phy.n; | |
2244 | ||
2245 | u16 curr_gain[2]; | |
2246 | struct nphy_txgains target; | |
2247 | const u32 *table = NULL; | |
2248 | ||
2249 | if (nphy->txpwrctrl == 0) { | |
2250 | int i; | |
2251 | ||
2252 | if (nphy->hang_avoid) | |
2253 | b43_nphy_stay_in_carrier_search(dev, true); | |
9145834e | 2254 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); |
b0022e15 RM |
2255 | if (nphy->hang_avoid) |
2256 | b43_nphy_stay_in_carrier_search(dev, false); | |
2257 | ||
2258 | for (i = 0; i < 2; ++i) { | |
2259 | if (dev->phy.rev >= 3) { | |
2260 | target.ipa[i] = curr_gain[i] & 0x000F; | |
2261 | target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; | |
2262 | target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; | |
2263 | target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; | |
2264 | } else { | |
2265 | target.ipa[i] = curr_gain[i] & 0x0003; | |
2266 | target.pad[i] = (curr_gain[i] & 0x000C) >> 2; | |
2267 | target.pga[i] = (curr_gain[i] & 0x0070) >> 4; | |
2268 | target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; | |
2269 | } | |
2270 | } | |
2271 | } else { | |
2272 | int i; | |
2273 | u16 index[2]; | |
2274 | index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & | |
2275 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
2276 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
2277 | index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & | |
2278 | B43_NPHY_TXPCTL_STAT_BIDX) >> | |
2279 | B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; | |
2280 | ||
2281 | for (i = 0; i < 2; ++i) { | |
2282 | if (dev->phy.rev >= 3) { | |
2283 | enum ieee80211_band band = | |
2284 | b43_current_band(dev->wl); | |
2285 | ||
2286 | if ((nphy->ipa2g_on && | |
2287 | band == IEEE80211_BAND_2GHZ) || | |
2288 | (nphy->ipa5g_on && | |
2289 | band == IEEE80211_BAND_5GHZ)) { | |
2290 | table = b43_nphy_get_ipa_gain_table(dev); | |
2291 | } else { | |
2292 | if (band == IEEE80211_BAND_5GHZ) { | |
2293 | if (dev->phy.rev == 3) | |
2294 | table = b43_ntab_tx_gain_rev3_5ghz; | |
2295 | else if (dev->phy.rev == 4) | |
2296 | table = b43_ntab_tx_gain_rev4_5ghz; | |
2297 | else | |
2298 | table = b43_ntab_tx_gain_rev5plus_5ghz; | |
2299 | } else { | |
2300 | table = b43_ntab_tx_gain_rev3plus_2ghz; | |
2301 | } | |
2302 | } | |
2303 | ||
2304 | target.ipa[i] = (table[index[i]] >> 16) & 0xF; | |
2305 | target.pad[i] = (table[index[i]] >> 20) & 0xF; | |
2306 | target.pga[i] = (table[index[i]] >> 24) & 0xF; | |
2307 | target.txgm[i] = (table[index[i]] >> 28) & 0xF; | |
2308 | } else { | |
2309 | table = b43_ntab_tx_gain_rev0_1_2; | |
2310 | ||
2311 | target.ipa[i] = (table[index[i]] >> 16) & 0x3; | |
2312 | target.pad[i] = (table[index[i]] >> 18) & 0x3; | |
2313 | target.pga[i] = (table[index[i]] >> 20) & 0x7; | |
2314 | target.txgm[i] = (table[index[i]] >> 23) & 0x7; | |
2315 | } | |
2316 | } | |
2317 | } | |
2318 | ||
2319 | return target; | |
2320 | } | |
2321 | ||
e53de674 RM |
2322 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ |
2323 | static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) | |
2324 | { | |
2325 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
2326 | ||
2327 | if (dev->phy.rev >= 3) { | |
2328 | b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); | |
2329 | b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); | |
2330 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); | |
2331 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); | |
2332 | b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); | |
d41a3552 RM |
2333 | b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); |
2334 | b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); | |
e53de674 RM |
2335 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); |
2336 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); | |
2337 | b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); | |
2338 | b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); | |
2339 | b43_nphy_reset_cca(dev); | |
2340 | } else { | |
2341 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); | |
2342 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); | |
2343 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); | |
d41a3552 RM |
2344 | b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); |
2345 | b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); | |
e53de674 RM |
2346 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); |
2347 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ | |
2352 | static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) | |
2353 | { | |
2354 | u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; | |
2355 | u16 tmp; | |
2356 | ||
2357 | regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); | |
2358 | regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); | |
2359 | if (dev->phy.rev >= 3) { | |
2360 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); | |
2361 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); | |
2362 | ||
2363 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); | |
2364 | regs[2] = tmp; | |
2365 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); | |
2366 | ||
2367 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2368 | regs[3] = tmp; | |
2369 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); | |
2370 | ||
2371 | regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); | |
de9a47f9 | 2372 | b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX); |
e53de674 | 2373 | |
c643a66e | 2374 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); |
e53de674 | 2375 | regs[5] = tmp; |
d41a3552 | 2376 | b43_ntab_write(dev, B43_NTAB16(8, 3), 0); |
c643a66e RM |
2377 | |
2378 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); | |
e53de674 | 2379 | regs[6] = tmp; |
d41a3552 | 2380 | b43_ntab_write(dev, B43_NTAB16(8, 19), 0); |
e53de674 RM |
2381 | regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
2382 | regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2383 | ||
67cbc3ed RM |
2384 | b43_nphy_rf_control_intc_override(dev, 2, 1, 3); |
2385 | b43_nphy_rf_control_intc_override(dev, 1, 2, 1); | |
2386 | b43_nphy_rf_control_intc_override(dev, 1, 8, 2); | |
e53de674 RM |
2387 | |
2388 | regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); | |
2389 | regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); | |
2390 | b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); | |
2391 | b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); | |
2392 | } else { | |
2393 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); | |
2394 | b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); | |
2395 | tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2396 | regs[2] = tmp; | |
2397 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); | |
c643a66e | 2398 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); |
e53de674 RM |
2399 | regs[3] = tmp; |
2400 | tmp |= 0x2000; | |
d41a3552 | 2401 | b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); |
c643a66e | 2402 | tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); |
e53de674 RM |
2403 | regs[4] = tmp; |
2404 | tmp |= 0x2000; | |
d41a3552 | 2405 | b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); |
e53de674 RM |
2406 | regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); |
2407 | regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); | |
2408 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
2409 | tmp = 0x0180; | |
2410 | else | |
2411 | tmp = 0x0120; | |
2412 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); | |
2413 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); | |
2414 | } | |
2415 | } | |
2416 | ||
bbc6dc12 RM |
2417 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ |
2418 | static void b43_nphy_save_cal(struct b43_wldev *dev) | |
2419 | { | |
2420 | struct b43_phy_n *nphy = dev->phy.n; | |
2421 | ||
2422 | struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; | |
2423 | u16 *txcal_radio_regs = NULL; | |
2424 | u8 *iqcal_chanspec; | |
2425 | u16 *table = NULL; | |
2426 | ||
2427 | if (nphy->hang_avoid) | |
2428 | b43_nphy_stay_in_carrier_search(dev, 1); | |
2429 | ||
2430 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2431 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; | |
2432 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; | |
2433 | iqcal_chanspec = &nphy->iqcal_chanspec_2G; | |
2434 | table = nphy->cal_cache.txcal_coeffs_2G; | |
2435 | } else { | |
2436 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; | |
2437 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; | |
2438 | iqcal_chanspec = &nphy->iqcal_chanspec_5G; | |
2439 | table = nphy->cal_cache.txcal_coeffs_5G; | |
2440 | } | |
2441 | ||
2442 | b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); | |
2443 | /* TODO use some definitions */ | |
2444 | if (dev->phy.rev >= 3) { | |
2445 | txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); | |
2446 | txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); | |
2447 | txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); | |
2448 | txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); | |
2449 | txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); | |
2450 | txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); | |
2451 | txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); | |
2452 | txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); | |
2453 | } else { | |
2454 | txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); | |
2455 | txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); | |
2456 | txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); | |
2457 | txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); | |
2458 | } | |
2459 | *iqcal_chanspec = nphy->radio_chanspec; | |
2460 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table); | |
2461 | ||
2462 | if (nphy->hang_avoid) | |
2463 | b43_nphy_stay_in_carrier_search(dev, 0); | |
2464 | } | |
2465 | ||
2f258b74 RM |
2466 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ |
2467 | static void b43_nphy_restore_cal(struct b43_wldev *dev) | |
2468 | { | |
2469 | struct b43_phy_n *nphy = dev->phy.n; | |
2470 | ||
2471 | u16 coef[4]; | |
2472 | u16 *loft = NULL; | |
2473 | u16 *table = NULL; | |
2474 | ||
2475 | int i; | |
2476 | u16 *txcal_radio_regs = NULL; | |
2477 | struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; | |
2478 | ||
2479 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2480 | if (nphy->iqcal_chanspec_2G == 0) | |
2481 | return; | |
2482 | table = nphy->cal_cache.txcal_coeffs_2G; | |
2483 | loft = &nphy->cal_cache.txcal_coeffs_2G[5]; | |
2484 | } else { | |
2485 | if (nphy->iqcal_chanspec_5G == 0) | |
2486 | return; | |
2487 | table = nphy->cal_cache.txcal_coeffs_5G; | |
2488 | loft = &nphy->cal_cache.txcal_coeffs_5G[5]; | |
2489 | } | |
2490 | ||
2581b143 | 2491 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); |
2f258b74 RM |
2492 | |
2493 | for (i = 0; i < 4; i++) { | |
2494 | if (dev->phy.rev >= 3) | |
2495 | table[i] = coef[i]; | |
2496 | else | |
2497 | coef[i] = 0; | |
2498 | } | |
2499 | ||
2581b143 RM |
2500 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); |
2501 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); | |
2502 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); | |
2f258b74 RM |
2503 | |
2504 | if (dev->phy.rev < 2) | |
2505 | b43_nphy_tx_iq_workaround(dev); | |
2506 | ||
2507 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
2508 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; | |
2509 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; | |
2510 | } else { | |
2511 | txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; | |
2512 | rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; | |
2513 | } | |
2514 | ||
2515 | /* TODO use some definitions */ | |
2516 | if (dev->phy.rev >= 3) { | |
2517 | b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); | |
2518 | b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); | |
2519 | b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); | |
2520 | b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); | |
2521 | b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); | |
2522 | b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); | |
2523 | b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); | |
2524 | b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); | |
2525 | } else { | |
2526 | b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); | |
2527 | b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); | |
2528 | b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); | |
2529 | b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); | |
2530 | } | |
2531 | b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); | |
2532 | } | |
2533 | ||
fb43b8e2 RM |
2534 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ |
2535 | static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, | |
2536 | struct nphy_txgains target, | |
2537 | bool full, bool mphase) | |
2538 | { | |
2539 | struct b43_phy_n *nphy = dev->phy.n; | |
2540 | int i; | |
2541 | int error = 0; | |
2542 | int freq; | |
2543 | bool avoid = false; | |
2544 | u8 length; | |
2545 | u16 tmp, core, type, count, max, numb, last, cmd; | |
2546 | const u16 *table; | |
2547 | bool phy6or5x; | |
2548 | ||
2549 | u16 buffer[11]; | |
2550 | u16 diq_start = 0; | |
2551 | u16 save[2]; | |
2552 | u16 gain[2]; | |
2553 | struct nphy_iqcal_params params[2]; | |
2554 | bool updated[2] = { }; | |
2555 | ||
2556 | b43_nphy_stay_in_carrier_search(dev, true); | |
2557 | ||
2558 | if (dev->phy.rev >= 4) { | |
2559 | avoid = nphy->hang_avoid; | |
2560 | nphy->hang_avoid = 0; | |
2561 | } | |
2562 | ||
9145834e | 2563 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2564 | |
2565 | for (i = 0; i < 2; i++) { | |
2566 | b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); | |
2567 | gain[i] = params[i].cal_gain; | |
2568 | } | |
2581b143 RM |
2569 | |
2570 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); | |
fb43b8e2 RM |
2571 | |
2572 | b43_nphy_tx_cal_radio_setup(dev); | |
e53de674 | 2573 | b43_nphy_tx_cal_phy_setup(dev); |
fb43b8e2 RM |
2574 | |
2575 | phy6or5x = dev->phy.rev >= 6 || | |
2576 | (dev->phy.rev == 5 && nphy->ipa2g_on && | |
2577 | b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); | |
2578 | if (phy6or5x) { | |
38bb9029 RM |
2579 | if (dev->phy.is_40mhz) { |
2580 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, | |
2581 | tbl_tx_iqlo_cal_loft_ladder_40); | |
2582 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, | |
2583 | tbl_tx_iqlo_cal_iqimb_ladder_40); | |
2584 | } else { | |
2585 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, | |
2586 | tbl_tx_iqlo_cal_loft_ladder_20); | |
2587 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, | |
2588 | tbl_tx_iqlo_cal_iqimb_ladder_20); | |
2589 | } | |
fb43b8e2 RM |
2590 | } |
2591 | ||
2592 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); | |
2593 | ||
aa4c7b2a | 2594 | if (!dev->phy.is_40mhz) |
fb43b8e2 RM |
2595 | freq = 2500; |
2596 | else | |
2597 | freq = 5000; | |
2598 | ||
2599 | if (nphy->mphase_cal_phase_id > 2) | |
10a79873 RM |
2600 | b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, |
2601 | 0xFFFF, 0, true, false); | |
fb43b8e2 | 2602 | else |
59af099b | 2603 | error = b43_nphy_tx_tone(dev, freq, 250, true, false); |
fb43b8e2 RM |
2604 | |
2605 | if (error == 0) { | |
2606 | if (nphy->mphase_cal_phase_id > 2) { | |
2607 | table = nphy->mphase_txcal_bestcoeffs; | |
2608 | length = 11; | |
2609 | if (dev->phy.rev < 3) | |
2610 | length -= 2; | |
2611 | } else { | |
2612 | if (!full && nphy->txiqlocal_coeffsvalid) { | |
2613 | table = nphy->txiqlocal_bestc; | |
2614 | length = 11; | |
2615 | if (dev->phy.rev < 3) | |
2616 | length -= 2; | |
2617 | } else { | |
2618 | full = true; | |
2619 | if (dev->phy.rev >= 3) { | |
2620 | table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; | |
2621 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; | |
2622 | } else { | |
2623 | table = tbl_tx_iqlo_cal_startcoefs; | |
2624 | length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; | |
2625 | } | |
2626 | } | |
2627 | } | |
2628 | ||
2581b143 | 2629 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); |
fb43b8e2 RM |
2630 | |
2631 | if (full) { | |
2632 | if (dev->phy.rev >= 3) | |
2633 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; | |
2634 | else | |
2635 | max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; | |
2636 | } else { | |
2637 | if (dev->phy.rev >= 3) | |
2638 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; | |
2639 | else | |
2640 | max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; | |
2641 | } | |
2642 | ||
2643 | if (mphase) { | |
2644 | count = nphy->mphase_txcal_cmdidx; | |
2645 | numb = min(max, | |
2646 | (u16)(count + nphy->mphase_txcal_numcmds)); | |
2647 | } else { | |
2648 | count = 0; | |
2649 | numb = max; | |
2650 | } | |
2651 | ||
2652 | for (; count < numb; count++) { | |
2653 | if (full) { | |
2654 | if (dev->phy.rev >= 3) | |
2655 | cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; | |
2656 | else | |
2657 | cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; | |
2658 | } else { | |
2659 | if (dev->phy.rev >= 3) | |
2660 | cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; | |
2661 | else | |
2662 | cmd = tbl_tx_iqlo_cal_cmds_recal[count]; | |
2663 | } | |
2664 | ||
2665 | core = (cmd & 0x3000) >> 12; | |
2666 | type = (cmd & 0x0F00) >> 8; | |
2667 | ||
2668 | if (phy6or5x && updated[core] == 0) { | |
2669 | b43_nphy_update_tx_cal_ladder(dev, core); | |
2670 | updated[core] = 1; | |
2671 | } | |
2672 | ||
2673 | tmp = (params[core].ncorr[type] << 8) | 0x66; | |
2674 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); | |
2675 | ||
2676 | if (type == 1 || type == 3 || type == 4) { | |
c643a66e RM |
2677 | buffer[0] = b43_ntab_read(dev, |
2678 | B43_NTAB16(15, 69 + core)); | |
fb43b8e2 RM |
2679 | diq_start = buffer[0]; |
2680 | buffer[0] = 0; | |
d41a3552 RM |
2681 | b43_ntab_write(dev, B43_NTAB16(15, 69 + core), |
2682 | 0); | |
fb43b8e2 RM |
2683 | } |
2684 | ||
2685 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); | |
2686 | for (i = 0; i < 2000; i++) { | |
2687 | tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); | |
2688 | if (tmp & 0xC000) | |
2689 | break; | |
2690 | udelay(10); | |
2691 | } | |
2692 | ||
9145834e RM |
2693 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2694 | buffer); | |
2581b143 RM |
2695 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, |
2696 | buffer); | |
fb43b8e2 RM |
2697 | |
2698 | if (type == 1 || type == 3 || type == 4) | |
2699 | buffer[0] = diq_start; | |
2700 | } | |
2701 | ||
2702 | if (mphase) | |
2703 | nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; | |
2704 | ||
2705 | last = (dev->phy.rev < 3) ? 6 : 7; | |
2706 | ||
2707 | if (!mphase || nphy->mphase_cal_phase_id == last) { | |
2581b143 | 2708 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); |
9145834e | 2709 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); |
fb43b8e2 RM |
2710 | if (dev->phy.rev < 3) { |
2711 | buffer[0] = 0; | |
2712 | buffer[1] = 0; | |
2713 | buffer[2] = 0; | |
2714 | buffer[3] = 0; | |
2715 | } | |
2581b143 RM |
2716 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, |
2717 | buffer); | |
2718 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2, | |
2719 | buffer); | |
2720 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, | |
2721 | buffer); | |
2722 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, | |
2723 | buffer); | |
fb43b8e2 RM |
2724 | length = 11; |
2725 | if (dev->phy.rev < 3) | |
2726 | length -= 2; | |
9145834e RM |
2727 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2728 | nphy->txiqlocal_bestc); | |
fb43b8e2 RM |
2729 | nphy->txiqlocal_coeffsvalid = true; |
2730 | /* TODO: Set nphy->txiqlocal_chanspec to | |
2731 | the current channel */ | |
2732 | } else { | |
2733 | length = 11; | |
2734 | if (dev->phy.rev < 3) | |
2735 | length -= 2; | |
9145834e RM |
2736 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, |
2737 | nphy->mphase_txcal_bestcoeffs); | |
fb43b8e2 RM |
2738 | } |
2739 | ||
53ae8e8c | 2740 | b43_nphy_stop_playback(dev); |
fb43b8e2 RM |
2741 | b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); |
2742 | } | |
2743 | ||
e53de674 | 2744 | b43_nphy_tx_cal_phy_cleanup(dev); |
2581b143 | 2745 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); |
fb43b8e2 RM |
2746 | |
2747 | if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) | |
2748 | b43_nphy_tx_iq_workaround(dev); | |
2749 | ||
2750 | if (dev->phy.rev >= 4) | |
2751 | nphy->hang_avoid = avoid; | |
2752 | ||
2753 | b43_nphy_stay_in_carrier_search(dev, false); | |
2754 | ||
2755 | return error; | |
2756 | } | |
2757 | ||
984ff4ff RM |
2758 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ |
2759 | static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) | |
2760 | { | |
2761 | struct b43_phy_n *nphy = dev->phy.n; | |
2762 | u8 i; | |
2763 | u16 buffer[7]; | |
2764 | bool equal = true; | |
2765 | ||
2766 | if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */) | |
2767 | return; | |
2768 | ||
2769 | b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); | |
2770 | for (i = 0; i < 4; i++) { | |
2771 | if (buffer[i] != nphy->txiqlocal_bestc[i]) { | |
2772 | equal = false; | |
2773 | break; | |
2774 | } | |
2775 | } | |
2776 | ||
2777 | if (!equal) { | |
2778 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, | |
2779 | nphy->txiqlocal_bestc); | |
2780 | for (i = 0; i < 4; i++) | |
2781 | buffer[i] = 0; | |
2782 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, | |
2783 | buffer); | |
2784 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, | |
2785 | &nphy->txiqlocal_bestc[5]); | |
2786 | b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, | |
2787 | &nphy->txiqlocal_bestc[5]); | |
2788 | } | |
2789 | } | |
2790 | ||
15931e31 RM |
2791 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ |
2792 | static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, | |
2793 | struct nphy_txgains target, u8 type, bool debug) | |
2794 | { | |
2795 | struct b43_phy_n *nphy = dev->phy.n; | |
2796 | int i, j, index; | |
2797 | u8 rfctl[2]; | |
2798 | u8 afectl_core; | |
2799 | u16 tmp[6]; | |
2800 | u16 cur_hpf1, cur_hpf2, cur_lna; | |
2801 | u32 real, imag; | |
2802 | enum ieee80211_band band; | |
2803 | ||
2804 | u8 use; | |
2805 | u16 cur_hpf; | |
2806 | u16 lna[3] = { 3, 3, 1 }; | |
2807 | u16 hpf1[3] = { 7, 2, 0 }; | |
2808 | u16 hpf2[3] = { 2, 0, 0 }; | |
de9a47f9 | 2809 | u32 power[3] = { }; |
15931e31 RM |
2810 | u16 gain_save[2]; |
2811 | u16 cal_gain[2]; | |
2812 | struct nphy_iqcal_params cal_params[2]; | |
2813 | struct nphy_iq_est est; | |
2814 | int ret = 0; | |
2815 | bool playtone = true; | |
2816 | int desired = 13; | |
2817 | ||
2818 | b43_nphy_stay_in_carrier_search(dev, 1); | |
2819 | ||
2820 | if (dev->phy.rev < 2) | |
984ff4ff | 2821 | b43_nphy_reapply_tx_cal_coeffs(dev); |
9145834e | 2822 | b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
2823 | for (i = 0; i < 2; i++) { |
2824 | b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); | |
2825 | cal_gain[i] = cal_params[i].cal_gain; | |
2826 | } | |
2581b143 | 2827 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); |
15931e31 RM |
2828 | |
2829 | for (i = 0; i < 2; i++) { | |
2830 | if (i == 0) { | |
2831 | rfctl[0] = B43_NPHY_RFCTL_INTC1; | |
2832 | rfctl[1] = B43_NPHY_RFCTL_INTC2; | |
2833 | afectl_core = B43_NPHY_AFECTL_C1; | |
2834 | } else { | |
2835 | rfctl[0] = B43_NPHY_RFCTL_INTC2; | |
2836 | rfctl[1] = B43_NPHY_RFCTL_INTC1; | |
2837 | afectl_core = B43_NPHY_AFECTL_C2; | |
2838 | } | |
2839 | ||
2840 | tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); | |
2841 | tmp[2] = b43_phy_read(dev, afectl_core); | |
2842 | tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); | |
2843 | tmp[4] = b43_phy_read(dev, rfctl[0]); | |
2844 | tmp[5] = b43_phy_read(dev, rfctl[1]); | |
2845 | ||
2846 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, | |
2847 | (u16)~B43_NPHY_RFSEQCA_RXDIS, | |
2848 | ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); | |
2849 | b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, | |
2850 | (1 - i)); | |
2851 | b43_phy_set(dev, afectl_core, 0x0006); | |
2852 | b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); | |
2853 | ||
2854 | band = b43_current_band(dev->wl); | |
2855 | ||
2856 | if (nphy->rxcalparams & 0xFF000000) { | |
2857 | if (band == IEEE80211_BAND_5GHZ) | |
2858 | b43_phy_write(dev, rfctl[0], 0x140); | |
2859 | else | |
2860 | b43_phy_write(dev, rfctl[0], 0x110); | |
2861 | } else { | |
2862 | if (band == IEEE80211_BAND_5GHZ) | |
2863 | b43_phy_write(dev, rfctl[0], 0x180); | |
2864 | else | |
2865 | b43_phy_write(dev, rfctl[0], 0x120); | |
2866 | } | |
2867 | ||
2868 | if (band == IEEE80211_BAND_5GHZ) | |
2869 | b43_phy_write(dev, rfctl[1], 0x148); | |
2870 | else | |
2871 | b43_phy_write(dev, rfctl[1], 0x114); | |
2872 | ||
2873 | if (nphy->rxcalparams & 0x10000) { | |
2874 | b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, | |
2875 | (i + 1)); | |
2876 | b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, | |
2877 | (2 - i)); | |
2878 | } | |
2879 | ||
2880 | for (j = 0; i < 4; j++) { | |
2881 | if (j < 3) { | |
2882 | cur_lna = lna[j]; | |
2883 | cur_hpf1 = hpf1[j]; | |
2884 | cur_hpf2 = hpf2[j]; | |
2885 | } else { | |
2886 | if (power[1] > 10000) { | |
2887 | use = 1; | |
2888 | cur_hpf = cur_hpf1; | |
2889 | index = 2; | |
2890 | } else { | |
2891 | if (power[0] > 10000) { | |
2892 | use = 1; | |
2893 | cur_hpf = cur_hpf1; | |
2894 | index = 1; | |
2895 | } else { | |
2896 | index = 0; | |
2897 | use = 2; | |
2898 | cur_hpf = cur_hpf2; | |
2899 | } | |
2900 | } | |
2901 | cur_lna = lna[index]; | |
2902 | cur_hpf1 = hpf1[index]; | |
2903 | cur_hpf2 = hpf2[index]; | |
2904 | cur_hpf += desired - hweight32(power[index]); | |
2905 | cur_hpf = clamp_val(cur_hpf, 0, 10); | |
2906 | if (use == 1) | |
2907 | cur_hpf1 = cur_hpf; | |
2908 | else | |
2909 | cur_hpf2 = cur_hpf; | |
2910 | } | |
2911 | ||
2912 | tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | | |
2913 | (cur_lna << 2)); | |
75377b24 RM |
2914 | b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3, |
2915 | false); | |
de9a47f9 | 2916 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
53ae8e8c | 2917 | b43_nphy_stop_playback(dev); |
15931e31 RM |
2918 | |
2919 | if (playtone) { | |
59af099b RM |
2920 | ret = b43_nphy_tx_tone(dev, 4000, |
2921 | (nphy->rxcalparams & 0xFFFF), | |
2922 | false, false); | |
15931e31 RM |
2923 | playtone = false; |
2924 | } else { | |
10a79873 RM |
2925 | b43_nphy_run_samples(dev, 160, 0xFFFF, 0, |
2926 | false, false); | |
15931e31 RM |
2927 | } |
2928 | ||
2929 | if (ret == 0) { | |
2930 | if (j < 3) { | |
2931 | b43_nphy_rx_iq_est(dev, &est, 1024, 32, | |
2932 | false); | |
2933 | if (i == 0) { | |
2934 | real = est.i0_pwr; | |
2935 | imag = est.q0_pwr; | |
2936 | } else { | |
2937 | real = est.i1_pwr; | |
2938 | imag = est.q1_pwr; | |
2939 | } | |
2940 | power[i] = ((real + imag) / 1024) + 1; | |
2941 | } else { | |
2942 | b43_nphy_calc_rx_iq_comp(dev, 1 << i); | |
2943 | } | |
53ae8e8c | 2944 | b43_nphy_stop_playback(dev); |
15931e31 RM |
2945 | } |
2946 | ||
2947 | if (ret != 0) | |
2948 | break; | |
2949 | } | |
2950 | ||
2951 | b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); | |
2952 | b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); | |
2953 | b43_phy_write(dev, rfctl[1], tmp[5]); | |
2954 | b43_phy_write(dev, rfctl[0], tmp[4]); | |
2955 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); | |
2956 | b43_phy_write(dev, afectl_core, tmp[2]); | |
2957 | b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); | |
2958 | ||
2959 | if (ret != 0) | |
2960 | break; | |
2961 | } | |
2962 | ||
75377b24 | 2963 | b43_nphy_rf_control_override(dev, 0x400, 0, 3, true); |
67c0d6e2 | 2964 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); |
2581b143 | 2965 | b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); |
15931e31 RM |
2966 | |
2967 | b43_nphy_stay_in_carrier_search(dev, 0); | |
2968 | ||
2969 | return ret; | |
2970 | } | |
2971 | ||
2972 | static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, | |
2973 | struct nphy_txgains target, u8 type, bool debug) | |
2974 | { | |
2975 | return -1; | |
2976 | } | |
2977 | ||
2978 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ | |
2979 | static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, | |
2980 | struct nphy_txgains target, u8 type, bool debug) | |
2981 | { | |
2982 | if (dev->phy.rev >= 3) | |
2983 | return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); | |
2984 | else | |
2985 | return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); | |
2986 | } | |
2987 | ||
0988a7a1 RM |
2988 | /* |
2989 | * Init N-PHY | |
2990 | * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N | |
2991 | */ | |
424047e6 MB |
2992 | int b43_phy_initn(struct b43_wldev *dev) |
2993 | { | |
0988a7a1 | 2994 | struct ssb_bus *bus = dev->dev->bus; |
95b66bad | 2995 | struct b43_phy *phy = &dev->phy; |
0988a7a1 RM |
2996 | struct b43_phy_n *nphy = phy->n; |
2997 | u8 tx_pwr_state; | |
2998 | struct nphy_txgains target; | |
95b66bad | 2999 | u16 tmp; |
0988a7a1 RM |
3000 | enum ieee80211_band tmp2; |
3001 | bool do_rssi_cal; | |
3002 | ||
3003 | u16 clip[2]; | |
3004 | bool do_cal = false; | |
95b66bad | 3005 | |
0988a7a1 RM |
3006 | if ((dev->phy.rev >= 3) && |
3007 | (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) && | |
3008 | (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { | |
3009 | chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40); | |
3010 | } | |
3011 | nphy->deaf_count = 0; | |
95b66bad | 3012 | b43_nphy_tables_init(dev); |
0988a7a1 RM |
3013 | nphy->crsminpwr_adjusted = false; |
3014 | nphy->noisevars_adjusted = false; | |
95b66bad MB |
3015 | |
3016 | /* Clear all overrides */ | |
0988a7a1 RM |
3017 | if (dev->phy.rev >= 3) { |
3018 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); | |
3019 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
3020 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); | |
3021 | b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); | |
3022 | } else { | |
3023 | b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); | |
3024 | } | |
95b66bad MB |
3025 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); |
3026 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); | |
0988a7a1 RM |
3027 | if (dev->phy.rev < 6) { |
3028 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); | |
3029 | b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); | |
3030 | } | |
95b66bad MB |
3031 | b43_phy_mask(dev, B43_NPHY_RFSEQMODE, |
3032 | ~(B43_NPHY_RFSEQMODE_CAOVER | | |
3033 | B43_NPHY_RFSEQMODE_TROVER)); | |
0988a7a1 RM |
3034 | if (dev->phy.rev >= 3) |
3035 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); | |
95b66bad MB |
3036 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); |
3037 | ||
0988a7a1 RM |
3038 | if (dev->phy.rev <= 2) { |
3039 | tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; | |
3040 | b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, | |
3041 | ~B43_NPHY_BPHY_CTL3_SCALE, | |
3042 | tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); | |
3043 | } | |
95b66bad MB |
3044 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); |
3045 | b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); | |
3046 | ||
0988a7a1 RM |
3047 | if (bus->sprom.boardflags2_lo & 0x100 || |
3048 | (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE && | |
3049 | bus->boardinfo.type == 0x8B)) | |
3050 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); | |
3051 | else | |
3052 | b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); | |
3053 | b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); | |
3054 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); | |
3055 | b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); | |
424047e6 | 3056 | |
ad9716e8 | 3057 | b43_nphy_update_mimo_config(dev, nphy->preamble_override); |
4f4ab6cd | 3058 | b43_nphy_update_txrx_chain(dev); |
95b66bad MB |
3059 | |
3060 | if (phy->rev < 2) { | |
3061 | b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); | |
3062 | b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); | |
3063 | } | |
0988a7a1 RM |
3064 | |
3065 | tmp2 = b43_current_band(dev->wl); | |
3066 | if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) || | |
3067 | (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) { | |
3068 | b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); | |
3069 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, | |
3070 | nphy->papd_epsilon_offset[0] << 7); | |
3071 | b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); | |
3072 | b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, | |
3073 | nphy->papd_epsilon_offset[1] << 7); | |
45ca697e | 3074 | b43_nphy_int_pa_set_tx_dig_filters(dev); |
0988a7a1 | 3075 | } else if (phy->rev >= 5) { |
45ca697e | 3076 | b43_nphy_ext_pa_set_tx_dig_filters(dev); |
0988a7a1 RM |
3077 | } |
3078 | ||
95b66bad | 3079 | b43_nphy_workarounds(dev); |
95b66bad | 3080 | |
0988a7a1 | 3081 | /* Reset CCA, in init code it differs a little from standard way */ |
730dd705 | 3082 | b43_nphy_bmac_clock_fgc(dev, 1); |
0988a7a1 RM |
3083 | tmp = b43_phy_read(dev, B43_NPHY_BBCFG); |
3084 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); | |
3085 | b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); | |
730dd705 | 3086 | b43_nphy_bmac_clock_fgc(dev, 0); |
0988a7a1 RM |
3087 | |
3088 | /* TODO N PHY MAC PHY Clock Set with argument 1 */ | |
3089 | ||
e50cbcf6 | 3090 | b43_nphy_pa_override(dev, false); |
95b66bad MB |
3091 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); |
3092 | b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); | |
e50cbcf6 | 3093 | b43_nphy_pa_override(dev, true); |
0988a7a1 | 3094 | |
bbec398c RM |
3095 | b43_nphy_classifier(dev, 0, 0); |
3096 | b43_nphy_read_clip_detection(dev, clip); | |
0988a7a1 RM |
3097 | tx_pwr_state = nphy->txpwrctrl; |
3098 | /* TODO N PHY TX power control with argument 0 | |
3099 | (turning off power control) */ | |
3100 | /* TODO Fix the TX Power Settings */ | |
3101 | /* TODO N PHY TX Power Control Idle TSSI */ | |
3102 | /* TODO N PHY TX Power Control Setup */ | |
3103 | ||
3104 | if (phy->rev >= 3) { | |
3105 | /* TODO */ | |
3106 | } else { | |
2581b143 RM |
3107 | b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, |
3108 | b43_ntab_tx_gain_rev0_1_2); | |
3109 | b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, | |
3110 | b43_ntab_tx_gain_rev0_1_2); | |
0988a7a1 | 3111 | } |
95b66bad | 3112 | |
0988a7a1 RM |
3113 | if (nphy->phyrxchain != 3) |
3114 | ;/* TODO N PHY RX Core Set State with phyrxchain as argument */ | |
3115 | if (nphy->mphase_cal_phase_id > 0) | |
3116 | ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ | |
3117 | ||
3118 | do_rssi_cal = false; | |
3119 | if (phy->rev >= 3) { | |
3120 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
3121 | do_rssi_cal = (nphy->rssical_chanspec_2G == 0); | |
3122 | else | |
3123 | do_rssi_cal = (nphy->rssical_chanspec_5G == 0); | |
3124 | ||
3125 | if (do_rssi_cal) | |
4cb99775 | 3126 | b43_nphy_rssi_cal(dev); |
0988a7a1 | 3127 | else |
42e1547e | 3128 | b43_nphy_restore_rssi_cal(dev); |
0988a7a1 | 3129 | } else { |
4cb99775 | 3130 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
3131 | } |
3132 | ||
3133 | if (!((nphy->measure_hold & 0x6) != 0)) { | |
3134 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
3135 | do_cal = (nphy->iqcal_chanspec_2G == 0); | |
3136 | else | |
3137 | do_cal = (nphy->iqcal_chanspec_5G == 0); | |
3138 | ||
3139 | if (nphy->mute) | |
3140 | do_cal = false; | |
3141 | ||
3142 | if (do_cal) { | |
b0022e15 | 3143 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
3144 | |
3145 | if (nphy->antsel_type == 2) | |
8987a9e9 | 3146 | b43_nphy_superswitch_init(dev, true); |
0988a7a1 | 3147 | if (nphy->perical != 2) { |
90b9738d | 3148 | b43_nphy_rssi_cal(dev); |
0988a7a1 RM |
3149 | if (phy->rev >= 3) { |
3150 | nphy->cal_orig_pwr_idx[0] = | |
3151 | nphy->txpwrindex[0].index_internal; | |
3152 | nphy->cal_orig_pwr_idx[1] = | |
3153 | nphy->txpwrindex[1].index_internal; | |
3154 | /* TODO N PHY Pre Calibrate TX Gain */ | |
b0022e15 | 3155 | target = b43_nphy_get_tx_gains(dev); |
0988a7a1 RM |
3156 | } |
3157 | } | |
3158 | } | |
3159 | } | |
3160 | ||
0988a7a1 RM |
3161 | if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) { |
3162 | if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) | |
bbc6dc12 | 3163 | b43_nphy_save_cal(dev); |
0988a7a1 | 3164 | else if (nphy->mphase_cal_phase_id == 0) |
15931e31 | 3165 | ;/* N PHY Periodic Calibration with argument 3 */ |
0988a7a1 RM |
3166 | } else { |
3167 | b43_nphy_restore_cal(dev); | |
3168 | } | |
0988a7a1 | 3169 | |
6dcd9d91 | 3170 | b43_nphy_tx_pwr_ctrl_coef_setup(dev); |
0988a7a1 RM |
3171 | /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */ |
3172 | b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); | |
3173 | b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); | |
3174 | if (phy->rev >= 3 && phy->rev <= 6) | |
3175 | b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014); | |
fe3e46e8 | 3176 | b43_nphy_tx_lp_fbw(dev); |
9442e5b5 RM |
3177 | if (phy->rev >= 3) |
3178 | b43_nphy_spur_workaround(dev); | |
95b66bad MB |
3179 | |
3180 | b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n"); | |
53a6e234 | 3181 | return 0; |
424047e6 | 3182 | } |
ef1a628d MB |
3183 | |
3184 | static int b43_nphy_op_allocate(struct b43_wldev *dev) | |
3185 | { | |
3186 | struct b43_phy_n *nphy; | |
3187 | ||
3188 | nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); | |
3189 | if (!nphy) | |
3190 | return -ENOMEM; | |
3191 | dev->phy.n = nphy; | |
3192 | ||
ef1a628d MB |
3193 | return 0; |
3194 | } | |
3195 | ||
fb11137a | 3196 | static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) |
ef1a628d | 3197 | { |
fb11137a MB |
3198 | struct b43_phy *phy = &dev->phy; |
3199 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 3200 | |
fb11137a | 3201 | memset(nphy, 0, sizeof(*nphy)); |
ef1a628d | 3202 | |
fb11137a | 3203 | //TODO init struct b43_phy_n |
ef1a628d MB |
3204 | } |
3205 | ||
fb11137a | 3206 | static void b43_nphy_op_free(struct b43_wldev *dev) |
ef1a628d | 3207 | { |
fb11137a MB |
3208 | struct b43_phy *phy = &dev->phy; |
3209 | struct b43_phy_n *nphy = phy->n; | |
ef1a628d | 3210 | |
ef1a628d | 3211 | kfree(nphy); |
fb11137a MB |
3212 | phy->n = NULL; |
3213 | } | |
3214 | ||
3215 | static int b43_nphy_op_init(struct b43_wldev *dev) | |
3216 | { | |
3217 | return b43_phy_initn(dev); | |
ef1a628d MB |
3218 | } |
3219 | ||
3220 | static inline void check_phyreg(struct b43_wldev *dev, u16 offset) | |
3221 | { | |
3222 | #if B43_DEBUG | |
3223 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { | |
3224 | /* OFDM registers are onnly available on A/G-PHYs */ | |
3225 | b43err(dev->wl, "Invalid OFDM PHY access at " | |
3226 | "0x%04X on N-PHY\n", offset); | |
3227 | dump_stack(); | |
3228 | } | |
3229 | if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { | |
3230 | /* Ext-G registers are only available on G-PHYs */ | |
3231 | b43err(dev->wl, "Invalid EXT-G PHY access at " | |
3232 | "0x%04X on N-PHY\n", offset); | |
3233 | dump_stack(); | |
3234 | } | |
3235 | #endif /* B43_DEBUG */ | |
3236 | } | |
3237 | ||
3238 | static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg) | |
3239 | { | |
3240 | check_phyreg(dev, reg); | |
3241 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
3242 | return b43_read16(dev, B43_MMIO_PHY_DATA); | |
3243 | } | |
3244 | ||
3245 | static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value) | |
3246 | { | |
3247 | check_phyreg(dev, reg); | |
3248 | b43_write16(dev, B43_MMIO_PHY_CONTROL, reg); | |
3249 | b43_write16(dev, B43_MMIO_PHY_DATA, value); | |
3250 | } | |
3251 | ||
3252 | static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) | |
3253 | { | |
3254 | /* Register 1 is a 32-bit register. */ | |
3255 | B43_WARN_ON(reg == 1); | |
3256 | /* N-PHY needs 0x100 for read access */ | |
3257 | reg |= 0x100; | |
3258 | ||
3259 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
3260 | return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); | |
3261 | } | |
3262 | ||
3263 | static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) | |
3264 | { | |
3265 | /* Register 1 is a 32-bit register. */ | |
3266 | B43_WARN_ON(reg == 1); | |
3267 | ||
3268 | b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg); | |
3269 | b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); | |
3270 | } | |
3271 | ||
c2b7aefd | 3272 | /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ |
ef1a628d | 3273 | static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, |
19d337df | 3274 | bool blocked) |
c2b7aefd RM |
3275 | { |
3276 | if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) | |
3277 | b43err(dev->wl, "MAC not suspended\n"); | |
3278 | ||
3279 | if (blocked) { | |
3280 | b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, | |
3281 | ~B43_NPHY_RFCTL_CMD_CHIP0PU); | |
3282 | if (dev->phy.rev >= 3) { | |
3283 | b43_radio_mask(dev, 0x09, ~0x2); | |
3284 | ||
3285 | b43_radio_write(dev, 0x204D, 0); | |
3286 | b43_radio_write(dev, 0x2053, 0); | |
3287 | b43_radio_write(dev, 0x2058, 0); | |
3288 | b43_radio_write(dev, 0x205E, 0); | |
3289 | b43_radio_mask(dev, 0x2062, ~0xF0); | |
3290 | b43_radio_write(dev, 0x2064, 0); | |
3291 | ||
3292 | b43_radio_write(dev, 0x304D, 0); | |
3293 | b43_radio_write(dev, 0x3053, 0); | |
3294 | b43_radio_write(dev, 0x3058, 0); | |
3295 | b43_radio_write(dev, 0x305E, 0); | |
3296 | b43_radio_mask(dev, 0x3062, ~0xF0); | |
3297 | b43_radio_write(dev, 0x3064, 0); | |
3298 | } | |
3299 | } else { | |
3300 | if (dev->phy.rev >= 3) { | |
3301 | /* TODO: b43_radio_init2056(dev); */ | |
3302 | /* TODO: PHY Set Channel Spec (dev, radio_chanspec) */ | |
3303 | } else { | |
3304 | b43_radio_init2055(dev); | |
3305 | } | |
3306 | } | |
ef1a628d MB |
3307 | } |
3308 | ||
cb24f57f MB |
3309 | static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) |
3310 | { | |
3311 | b43_phy_write(dev, B43_NPHY_AFECTL_OVER, | |
3312 | on ? 0 : 0x7FFF); | |
3313 | } | |
3314 | ||
ef1a628d MB |
3315 | static int b43_nphy_op_switch_channel(struct b43_wldev *dev, |
3316 | unsigned int new_channel) | |
3317 | { | |
3318 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { | |
3319 | if ((new_channel < 1) || (new_channel > 14)) | |
3320 | return -EINVAL; | |
3321 | } else { | |
3322 | if (new_channel > 200) | |
3323 | return -EINVAL; | |
3324 | } | |
3325 | ||
3326 | return nphy_channel_switch(dev, new_channel); | |
3327 | } | |
3328 | ||
3329 | static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) | |
3330 | { | |
3331 | if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) | |
3332 | return 1; | |
3333 | return 36; | |
3334 | } | |
3335 | ||
ef1a628d MB |
3336 | const struct b43_phy_operations b43_phyops_n = { |
3337 | .allocate = b43_nphy_op_allocate, | |
fb11137a MB |
3338 | .free = b43_nphy_op_free, |
3339 | .prepare_structs = b43_nphy_op_prepare_structs, | |
ef1a628d | 3340 | .init = b43_nphy_op_init, |
ef1a628d MB |
3341 | .phy_read = b43_nphy_op_read, |
3342 | .phy_write = b43_nphy_op_write, | |
3343 | .radio_read = b43_nphy_op_radio_read, | |
3344 | .radio_write = b43_nphy_op_radio_write, | |
3345 | .software_rfkill = b43_nphy_op_software_rfkill, | |
cb24f57f | 3346 | .switch_analog = b43_nphy_op_switch_analog, |
ef1a628d MB |
3347 | .switch_channel = b43_nphy_op_switch_channel, |
3348 | .get_default_chan = b43_nphy_op_get_default_chan, | |
18c8adeb MB |
3349 | .recalc_txpower = b43_nphy_op_recalc_txpower, |
3350 | .adjust_txpower = b43_nphy_op_adjust_txpower, | |
ef1a628d | 3351 | }; |