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b43: PHY: allow init optimizations by tracking PHY state
[linux-block.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
eb032b98 6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
108f4f3c 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
424047e6
MB		 8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24*/
25
819d772b 26#include <linux/delay.h>
5a0e3ad6 27#include <linux/slab.h>
819d772b
JL		 28#include <linux/types.h>
29
424047e6 30#include "b43.h"
3d0da751 31#include "phy_n.h"
53a6e234 32#include "tables_nphy.h"
6db507ff 33#include "radio_2055.h"
5161bec5 34#include "radio_2056.h"
572d37a4 35#include "radio_2057.h"
bbec398c 36#include "main.h"
424047e6 37
f8187b5b
RM		 38struct nphy_txgains {
39 u16 txgm[2];
40 u16 pga[2];
41 u16 pad[2];
42 u16 ipa[2];
43};
44
45struct nphy_iqcal_params {
46 u16 txgm;
47 u16 pga;
48 u16 pad;
49 u16 ipa;
50 u16 cal_gain;
51 u16 ncorr[5];
52};
53
54struct nphy_iq_est {
55 s32 iq0_prod;
56 u32 i0_pwr;
57 u32 q0_pwr;
58 s32 iq1_prod;
59 u32 i1_pwr;
60 u32 q1_pwr;
61};
424047e6 62
67c0d6e2
RM		 63enum b43_nphy_rf_sequence {
64 B43_RFSEQ_RX2TX,
65 B43_RFSEQ_TX2RX,
66 B43_RFSEQ_RESET2RX,
67 B43_RFSEQ_UPDATE_GAINH,
68 B43_RFSEQ_UPDATE_GAINL,
69 B43_RFSEQ_UPDATE_GAINU,
70};
71
89e43dad
RM		 72enum n_intc_override {
73 N_INTC_OVERRIDE_OFF = 0,
74 N_INTC_OVERRIDE_TRSW = 1,
75 N_INTC_OVERRIDE_PA = 2,
76 N_INTC_OVERRIDE_EXT_LNA_PU = 3,
77 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4,
78};
79
2a2d0589
RM		 80enum n_rssi_type {
81 N_RSSI_W1 = 0,
82 N_RSSI_W2,
83 N_RSSI_NB,
84 N_RSSI_IQ,
85 N_RSSI_TSSI_2G,
86 N_RSSI_TSSI_5G,
87 N_RSSI_TBD,
76b002bd
RM		 88};
89
6aa38725
RM		 90enum n_rail_type {
91 N_RAIL_I = 0,
92 N_RAIL_Q = 1,
76b002bd
RM		 93};
94
c002831a
RM		 95static inline bool b43_nphy_ipa(struct b43_wldev *dev)
96{
97 enum ieee80211_band band = b43_current_band(dev->wl);
98 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
99 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
100}
101
e0c9a021
RM		 102/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
103static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
104{
105 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
106 B43_NPHY_RFSEQCA_RXEN_SHIFT;
107}
108
ab499217 109/**************************************************
89e43dad 110 * RF (just without b43_nphy_rf_ctl_intc_override)
ab499217 111 **************************************************/
18c8adeb 112
ab499217
RM		 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
114static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
115 enum b43_nphy_rf_sequence seq)
d1591314 116{
ab499217
RM		 117 static const u16 trigger[] = {
118 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
119 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
120 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
121 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
122 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
123 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
124 };
125 int i;
126 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
e5255ccc 127
ab499217 128 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
e5255ccc 129
ab499217
RM		 130 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
131 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
132 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
133 for (i = 0; i < 200; i++) {
134 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
135 goto ok;
136 msleep(1);
137 }
138 b43err(dev->wl, "RF sequence status timeout\n");
139ok:
140 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
141}
e5255ccc 142
c071b9f6 143/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
78ae7532
RM		 144static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field,
145 u16 value, u8 core, bool off,
146 u8 override)
c071b9f6
RM		 147{
148 const struct nphy_rf_control_override_rev7 *e;
149 u16 en_addrs[3][2] = {
150 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 }
151 };
152 u16 en_addr;
153 u16 en_mask = field;
154 u16 val_addr;
155 u8 i;
156
157 /* Remember: we can get NULL! */
158 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override);
159
160 for (i = 0; i < 2; i++) {
161 if (override >= ARRAY_SIZE(en_addrs)) {
162 b43err(dev->wl, "Invalid override value %d\n", override);
163 return;
164 }
165 en_addr = en_addrs[override][i];
166
8ce9beac
FP		 167 if (e)
168 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1;
c071b9f6
RM		 169
170 if (off) {
171 b43_phy_mask(dev, en_addr, ~en_mask);
172 if (e) /* Do it safer, better than wl */
173 b43_phy_mask(dev, val_addr, ~e->val_mask);
174 } else {
175 if (!core || (core & (1 << i))) {
176 b43_phy_set(dev, en_addr, en_mask);
177 if (e)
178 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift));
179 }
180 }
181 }
182}
183
ab499217 184/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
78ae7532
RM		 185static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field,
186 u16 value, u8 core, bool off)
ab499217
RM		 187{
188 int i;
189 u8 index = fls(field);
190 u8 addr, en_addr, val_addr;
191 /* we expect only one bit set */
192 B43_WARN_ON(field & (~(1 << (index - 1))));
e5255ccc 193
ab499217
RM		 194 if (dev->phy.rev >= 3) {
195 const struct nphy_rf_control_override_rev3 *rf_ctrl;
196 for (i = 0; i < 2; i++) {
197 if (index == 0 || index == 16) {
198 b43err(dev->wl,
199 "Unsupported RF Ctrl Override call\n");
200 return;
201 }
e5255ccc 202
ab499217
RM		 203 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
204 en_addr = B43_PHY_N((i == 0) ?
205 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
206 val_addr = B43_PHY_N((i == 0) ?
207 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
d1591314 208
ab499217
RM		 209 if (off) {
210 b43_phy_mask(dev, en_addr, ~(field));
211 b43_phy_mask(dev, val_addr,
212 ~(rf_ctrl->val_mask));
213 } else {
b97c0718 214 if (core == 0 || ((1 << i) & core)) {
ab499217
RM		 215 b43_phy_set(dev, en_addr, field);
216 b43_phy_maskset(dev, val_addr,
217 ~(rf_ctrl->val_mask),
218 (value << rf_ctrl->val_shift));
219 }
220 }
221 }
222 } else {
223 const struct nphy_rf_control_override_rev2 *rf_ctrl;
224 if (off) {
225 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
226 value = 0;
227 } else {
228 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
229 }
d4814e69 230
ab499217
RM		 231 for (i = 0; i < 2; i++) {
232 if (index <= 1 || index == 16) {
233 b43err(dev->wl,
234 "Unsupported RF Ctrl Override call\n");
235 return;
236 }
d4814e69 237
ab499217
RM		 238 if (index == 2 || index == 10 ||
239 (index >= 13 && index <= 15)) {
240 core = 1;
241 }
d4814e69 242
ab499217
RM		 243 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
244 addr = B43_PHY_N((i == 0) ?
245 rf_ctrl->addr0 : rf_ctrl->addr1);
d4814e69 246
b97c0718 247 if ((1 << i) & core)
ab499217
RM		 248 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
249 (value << rf_ctrl->shift));
250
251 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
252 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
253 B43_NPHY_RFCTL_CMD_START);
254 udelay(1);
255 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
256 }
257 }
d4814e69
RM		 258}
259
4256ba77
RM		 260static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev,
261 enum n_intc_override intc_override,
262 u16 value, u8 core_sel)
263{
264 u16 reg, tmp, tmp2, val;
265 int core;
266
267 for (core = 0; core < 2; core++) {
268 if ((core_sel == 1 && core != 0) ||
269 (core_sel == 2 && core != 1))
270 continue;
271
272 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
273
274 switch (intc_override) {
275 case N_INTC_OVERRIDE_OFF:
276 b43_phy_write(dev, reg, 0);
277 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
278 break;
279 case N_INTC_OVERRIDE_TRSW:
280 b43_phy_maskset(dev, reg, ~0xC0, value << 6);
281 b43_phy_set(dev, reg, 0x400);
282
283 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF);
284 b43_phy_set(dev, 0x2ff, 0x2000);
285 b43_phy_set(dev, 0x2ff, 0x0001);
286 break;
287 case N_INTC_OVERRIDE_PA:
288 tmp = 0x0030;
289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
290 val = value << 5;
291 else
292 val = value << 4;
293 b43_phy_maskset(dev, reg, ~tmp, val);
294 b43_phy_set(dev, reg, 0x1000);
295 break;
296 case N_INTC_OVERRIDE_EXT_LNA_PU:
297 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
298 tmp = 0x0001;
299 tmp2 = 0x0004;
300 val = value;
301 } else {
302 tmp = 0x0004;
303 tmp2 = 0x0001;
304 val = value << 2;
305 }
306 b43_phy_maskset(dev, reg, ~tmp, val);
307 b43_phy_mask(dev, reg, ~tmp2);
308 break;
309 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
310 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
311 tmp = 0x0002;
312 tmp2 = 0x0008;
313 val = value << 1;
314 } else {
315 tmp = 0x0008;
316 tmp2 = 0x0002;
317 val = value << 3;
318 }
319 b43_phy_maskset(dev, reg, ~tmp, val);
320 b43_phy_mask(dev, reg, ~tmp2);
321 break;
322 }
323 }
324}
325
ab499217 326/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
89e43dad
RM		 327static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev,
328 enum n_intc_override intc_override,
329 u16 value, u8 core)
d4814e69 330{
ab499217
RM		 331 u8 i, j;
332 u16 reg, tmp, val;
38646eba 333
4256ba77
RM		 334 if (dev->phy.rev >= 7) {
335 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value,
336 core);
337 return;
338 }
339
d4814e69
RM		 340 B43_WARN_ON(dev->phy.rev < 3);
341
ab499217
RM		 342 for (i = 0; i < 2; i++) {
343 if ((core == 1 && i == 1) || (core == 2 && !i))
344 continue;
38646eba 345
ab499217
RM		 346 reg = (i == 0) ?
347 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
603431e9 348 b43_phy_set(dev, reg, 0x400);
38646eba 349
89e43dad
RM		 350 switch (intc_override) {
351 case N_INTC_OVERRIDE_OFF:
ab499217
RM		 352 b43_phy_write(dev, reg, 0);
353 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
354 break;
89e43dad 355 case N_INTC_OVERRIDE_TRSW:
ab499217
RM		 356 if (!i) {
357 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
358 0xFC3F, (value << 6));
359 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
360 0xFFFE, 1);
361 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
362 B43_NPHY_RFCTL_CMD_START);
363 for (j = 0; j < 100; j++) {
603431e9 364 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
ab499217
RM		 365 j = 0;
366 break;
367 }
368 udelay(10);
38646eba 369 }
ab499217
RM		 370 if (j)
371 b43err(dev->wl,
372 "intc override timeout\n");
373 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
374 0xFFFE);
38646eba 375 } else {
ab499217
RM		 376 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
377 0xFC3F, (value << 6));
378 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
379 0xFFFE, 1);
380 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
381 B43_NPHY_RFCTL_CMD_RXTX);
382 for (j = 0; j < 100; j++) {
603431e9 383 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
ab499217
RM		 384 j = 0;
385 break;
386 }
387 udelay(10);
388 }
389 if (j)
390 b43err(dev->wl,
391 "intc override timeout\n");
392 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
393 0xFFFE);
38646eba 394 }
ab499217 395 break;
89e43dad 396 case N_INTC_OVERRIDE_PA:
ab499217
RM		 397 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
398 tmp = 0x0020;
399 val = value << 5;
400 } else {
401 tmp = 0x0010;
402 val = value << 4;
403 }
404 b43_phy_maskset(dev, reg, ~tmp, val);
405 break;
89e43dad 406 case N_INTC_OVERRIDE_EXT_LNA_PU:
ab499217
RM		 407 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
408 tmp = 0x0001;
409 val = value;
410 } else {
411 tmp = 0x0004;
412 val = value << 2;
413 }
414 b43_phy_maskset(dev, reg, ~tmp, val);
415 break;
89e43dad 416 case N_INTC_OVERRIDE_EXT_LNA_GAIN:
ab499217
RM		 417 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
418 tmp = 0x0002;
419 val = value << 1;
420 } else {
421 tmp = 0x0008;
422 val = value << 3;
423 }
424 b43_phy_maskset(dev, reg, ~tmp, val);
425 break;
38646eba 426 }
38646eba 427 }
ab499217 428}
38646eba 429
ab499217
RM		 430/**************************************************
431 * Various PHY ops
432 **************************************************/
433
434/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
435static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
436 const u16 *clip_st)
437{
438 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
439 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
d4814e69
RM		 440}
441
ab499217
RM		 442/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
443static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
d1591314 444{
ab499217
RM		 445 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
446 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
d1591314
MB		 447}
448
ab499217
RM		 449/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
450static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161d540c 451{
ab499217 452 u16 tmp;
161d540c 453
ab499217
RM		 454 if (dev->dev->core_rev == 16)
455 b43_mac_suspend(dev);
161d540c 456
ab499217
RM		 457 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
458 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
459 B43_NPHY_CLASSCTL_WAITEDEN);
460 tmp &= ~mask;
461 tmp |= (val & mask);
462 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
161d540c 463
ab499217
RM		 464 if (dev->dev->core_rev == 16)
465 b43_mac_enable(dev);
161d540c 466
ab499217
RM		 467 return tmp;
468}
161d540c 469
ab499217
RM		 470/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
471static void b43_nphy_reset_cca(struct b43_wldev *dev)
472{
473 u16 bbcfg;
161d540c 474
ab499217
RM		 475 b43_phy_force_clock(dev, 1);
476 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
477 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
478 udelay(1);
479 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
480 b43_phy_force_clock(dev, 0);
481 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
482}
161d540c 483
ab499217
RM		 484/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
485static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
486{
487 struct b43_phy *phy = &dev->phy;
488 struct b43_phy_n *nphy = phy->n;
161d540c 489
ab499217
RM		 490 if (enable) {
491 static const u16 clip[] = { 0xFFFF, 0xFFFF };
492 if (nphy->deaf_count++ == 0) {
493 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
bc36e994
RM		 494 b43_nphy_classifier(dev, 0x7,
495 B43_NPHY_CLASSCTL_WAITEDEN);
ab499217
RM		 496 b43_nphy_read_clip_detection(dev, nphy->clip_state);
497 b43_nphy_write_clip_detection(dev, clip);
498 }
499 b43_nphy_reset_cca(dev);
161d540c 500 } else {
ab499217
RM		 501 if (--nphy->deaf_count == 0) {
502 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
503 b43_nphy_write_clip_detection(dev, nphy->clip_state);
c9c0d9ec 504 }
161d540c 505 }
161d540c
RM		 506}
507
64712095
RM		 508/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
509static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
d1591314 510{
161d540c 511 struct b43_phy_n *nphy = dev->phy.n;
161d540c 512
64712095
RM		 513 u8 i;
514 s16 tmp;
515 u16 data[4];
516 s16 gain[2];
517 u16 minmax[2];
518 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
161d540c
RM		 519
520 if (nphy->hang_avoid)
521 b43_nphy_stay_in_carrier_search(dev, 1);
522
64712095 523 if (nphy->gain_boost) {
161d540c 524 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
64712095
RM		 525 gain[0] = 6;
526 gain[1] = 6;
161d540c 527 } else {
64712095
RM		 528 tmp = 40370 - 315 * dev->phy.channel;
529 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
530 tmp = 23242 - 224 * dev->phy.channel;
531 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
161d540c 532 }
64712095
RM		 533 } else {
534 gain[0] = 0;
535 gain[1] = 0;
161d540c 536 }
161d540c
RM		 537
538 for (i = 0; i < 2; i++) {
64712095
RM		 539 if (nphy->elna_gain_config) {
540 data[0] = 19 + gain[i];
541 data[1] = 25 + gain[i];
542 data[2] = 25 + gain[i];
543 data[3] = 25 + gain[i];
161d540c 544 } else {
64712095
RM		 545 data[0] = lna_gain[0] + gain[i];
546 data[1] = lna_gain[1] + gain[i];
547 data[2] = lna_gain[2] + gain[i];
548 data[3] = lna_gain[3] + gain[i];
161d540c 549 }
64712095 550 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
161d540c 551
64712095 552 minmax[i] = 23 + gain[i];
161d540c
RM		 553 }
554
64712095
RM		 555 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
556 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
557 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
558 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
161d540c
RM		 559
560 if (nphy->hang_avoid)
561 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314
MB		 562}
563
ab499217
RM		 564/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
565static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
566 u8 *events, u8 *delays, u8 length)
0eff8fcd 567{
ab499217
RM		 568 struct b43_phy_n *nphy = dev->phy.n;
569 u8 i;
570 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
571 u16 offset1 = cmd << 4;
572 u16 offset2 = offset1 + 0x80;
0eff8fcd 573
ab499217
RM		 574 if (nphy->hang_avoid)
575 b43_nphy_stay_in_carrier_search(dev, true);
0eff8fcd 576
ab499217
RM		 577 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
578 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
0eff8fcd 579
ab499217
RM		 580 for (i = length; i < 16; i++) {
581 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
582 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
0eff8fcd 583 }
ab499217
RM		 584
585 if (nphy->hang_avoid)
586 b43_nphy_stay_in_carrier_search(dev, false);
0eff8fcd 587}
7955de0c 588
572d37a4
RM		 589/**************************************************
590 * Radio 0x2057
591 **************************************************/
592
593/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rcal */
594static u8 b43_radio_2057_rcal(struct b43_wldev *dev)
595{
596 struct b43_phy *phy = &dev->phy;
597 u16 tmp;
598
599 if (phy->radio_rev == 5) {
600 b43_phy_mask(dev, 0x342, ~0x2);
601 udelay(10);
602 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1);
603 b43_radio_maskset(dev, 0x1ca, ~0x2, 0x1);
604 }
605
606 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1);
607 udelay(10);
608 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x3);
609 if (!b43_radio_wait_value(dev, R2057_RCCAL_N1_1, 1, 1, 100, 1000000)) {
610 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
611 return 0;
612 }
613 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2);
614 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E;
615 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1);
616
617 if (phy->radio_rev == 5) {
618 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1);
619 b43_radio_mask(dev, 0x1ca, ~0x2);
620 }
621 if (phy->radio_rev <= 4 || phy->radio_rev == 6) {
622 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp);
623 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0,
624 tmp << 2);
625 }
626
627 return tmp & 0x3e;
628}
629
630/* http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */
631static u16 b43_radio_2057_rccal(struct b43_wldev *dev)
632{
633 struct b43_phy *phy = &dev->phy;
634 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 ||
635 phy->radio_rev == 6);
636 u16 tmp;
637
638 if (special) {
639 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61);
640 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0);
641 } else {
642 b43_radio_write(dev, 0x1AE, 0x61);
643 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE1);
644 }
645 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
646 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
647 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
648 5000000))
649 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
650 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
651 if (special) {
652 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69);
653 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
654 } else {
655 b43_radio_write(dev, 0x1AE, 0x69);
656 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5);
657 }
658 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
659 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
660 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
661 5000000))
6c187236 662 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n");
572d37a4
RM		 663 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
664 if (special) {
665 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73);
666 b43_radio_write(dev, R2057_RCCAL_X1, 0x28);
667 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0);
668 } else {
669 b43_radio_write(dev, 0x1AE, 0x73);
670 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E);
671 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99);
672 }
673 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55);
674 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 1, 1, 500,
675 5000000)) {
676 b43err(dev->wl, "Radio 0x2057 rcal timeout\n");
677 return 0;
678 }
679 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP);
680 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15);
681 return tmp;
682}
683
684static void b43_radio_2057_init_pre(struct b43_wldev *dev)
685{
686 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU);
687 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
688 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE);
689 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
690 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU);
691}
692
693static void b43_radio_2057_init_post(struct b43_wldev *dev)
694{
695 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1);
696
697 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78);
698 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80);
699 mdelay(2);
700 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78);
701 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80);
702
703 if (dev->phy.n->init_por) {
704 b43_radio_2057_rcal(dev);
705 b43_radio_2057_rccal(dev);
706 }
707 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8);
708
709 dev->phy.n->init_por = false;
710}
711
712/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */
713static void b43_radio_2057_init(struct b43_wldev *dev)
714{
715 b43_radio_2057_init_pre(dev);
716 r2057_upload_inittabs(dev);
717 b43_radio_2057_init_post(dev);
718}
719
ab499217 720/**************************************************
884a5228 721 * Radio 0x2056
ab499217 722 **************************************************/
7955de0c 723
d4814e69
RM		 724static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
725 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 726{
d4814e69
RM		 727 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
728 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
729 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
730 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
731 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
732 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
733 e->radio_syn_pll_loopfilter1);
734 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
735 e->radio_syn_pll_loopfilter2);
736 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
737 e->radio_syn_pll_loopfilter3);
738 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
739 e->radio_syn_pll_loopfilter4);
740 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
741 e->radio_syn_pll_loopfilter5);
742 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
743 e->radio_syn_reserved_addr27);
744 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
745 e->radio_syn_reserved_addr28);
746 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
747 e->radio_syn_reserved_addr29);
748 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
749 e->radio_syn_logen_vcobuf1);
750 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
751 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
752 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
753
754 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
755 e->radio_rx0_lnaa_tune);
756 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
757 e->radio_rx0_lnag_tune);
758
759 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
760 e->radio_tx0_intpaa_boost_tune);
761 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
762 e->radio_tx0_intpag_boost_tune);
763 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
764 e->radio_tx0_pada_boost_tune);
765 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
766 e->radio_tx0_padg_boost_tune);
767 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
768 e->radio_tx0_pgaa_boost_tune);
769 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
770 e->radio_tx0_pgag_boost_tune);
771 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
772 e->radio_tx0_mixa_boost_tune);
773 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
774 e->radio_tx0_mixg_boost_tune);
775
776 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
777 e->radio_rx1_lnaa_tune);
778 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
779 e->radio_rx1_lnag_tune);
780
781 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
782 e->radio_tx1_intpaa_boost_tune);
783 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
784 e->radio_tx1_intpag_boost_tune);
785 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
786 e->radio_tx1_pada_boost_tune);
787 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
788 e->radio_tx1_padg_boost_tune);
789 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
790 e->radio_tx1_pgaa_boost_tune);
791 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
792 e->radio_tx1_pgag_boost_tune);
793 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
794 e->radio_tx1_mixa_boost_tune);
795 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
796 e->radio_tx1_mixg_boost_tune);
53a6e234
MB		 797}
798
d4814e69
RM		 799/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
800static void b43_radio_2056_setup(struct b43_wldev *dev,
801 const struct b43_nphy_channeltab_entry_rev3 *e)
53a6e234 802{
0581483a 803 struct ssb_sprom *sprom = dev->dev->bus_sprom;
38646eba
RM		 804 enum ieee80211_band band = b43_current_band(dev->wl);
805 u16 offset;
806 u8 i;
d3d178f0
RM		 807 u16 bias, cbias;
808 u16 pag_boost, padg_boost, pgag_boost, mixg_boost;
809 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost;
b88cdde9 810 bool is_pkg_fab_smic;
036cafe4 811
d4814e69 812 B43_WARN_ON(dev->phy.rev < 3);
53a6e234 813
b88cdde9
RM		 814 is_pkg_fab_smic =
815 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 ||
816 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 ||
817 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) &&
818 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC);
819
d4814e69 820 b43_chantab_radio_2056_upload(dev, e);
38646eba
RM		 821 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
822
823 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
824 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
825 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
826 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
b88cdde9
RM		 827 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
828 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 829 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
830 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
831 } else {
832 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
833 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
036cafe4 834 }
53a6e234 835 }
b88cdde9
RM		 836 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 &&
837 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
838 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f);
839 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f);
840 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b);
841 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20);
842 }
38646eba
RM		 843 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
844 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
845 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
846 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
847 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
848 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
036cafe4 849 }
53a6e234 850
38646eba
RM		 851 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
852 for (i = 0; i < 2; i++) {
853 offset = i ? B2056_TX1 : B2056_TX0;
854 if (dev->phy.rev >= 5) {
855 b43_radio_write(dev,
856 offset | B2056_TX_PADG_IDAC, 0xcc);
857
b88cdde9
RM		 858 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 ||
859 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) {
38646eba
RM		 860 bias = 0x40;
861 cbias = 0x45;
862 pag_boost = 0x5;
863 pgag_boost = 0x33;
864 mixg_boost = 0x55;
865 } else {
866 bias = 0x25;
867 cbias = 0x20;
b88cdde9
RM		 868 if (is_pkg_fab_smic) {
869 bias = 0x2a;
870 cbias = 0x38;
871 }
38646eba
RM		 872 pag_boost = 0x4;
873 pgag_boost = 0x03;
874 mixg_boost = 0x65;
875 }
876 padg_boost = 0x77;
877
878 b43_radio_write(dev,
879 offset | B2056_TX_INTPAG_IMAIN_STAT,
880 bias);
881 b43_radio_write(dev,
882 offset | B2056_TX_INTPAG_IAUX_STAT,
883 bias);
884 b43_radio_write(dev,
885 offset | B2056_TX_INTPAG_CASCBIAS,
886 cbias);
887 b43_radio_write(dev,
888 offset | B2056_TX_INTPAG_BOOST_TUNE,
889 pag_boost);
890 b43_radio_write(dev,
891 offset | B2056_TX_PGAG_BOOST_TUNE,
892 pgag_boost);
893 b43_radio_write(dev,
894 offset | B2056_TX_PADG_BOOST_TUNE,
895 padg_boost);
896 b43_radio_write(dev,
897 offset | B2056_TX_MIXG_BOOST_TUNE,
898 mixg_boost);
899 } else {
900 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
901 b43_radio_write(dev,
902 offset | B2056_TX_INTPAG_IMAIN_STAT,
903 bias);
904 b43_radio_write(dev,
905 offset | B2056_TX_INTPAG_IAUX_STAT,
906 bias);
907 b43_radio_write(dev,
908 offset | B2056_TX_INTPAG_CASCBIAS,
909 0x30);
910 }
911 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
912 }
913 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
d3d178f0
RM		 914 u16 freq = dev->phy.channel_freq;
915 if (freq < 5100) {
916 paa_boost = 0xA;
917 pada_boost = 0x77;
918 pgaa_boost = 0xF;
919 mixa_boost = 0xF;
920 } else if (freq < 5340) {
921 paa_boost = 0x8;
922 pada_boost = 0x77;
923 pgaa_boost = 0xFB;
924 mixa_boost = 0xF;
925 } else if (freq < 5650) {
926 paa_boost = 0x0;
927 pada_boost = 0x77;
928 pgaa_boost = 0xB;
929 mixa_boost = 0xF;
930 } else {
931 paa_boost = 0x0;
932 pada_boost = 0x77;
933 if (freq != 5825)
934 pgaa_boost = -(freq - 18) / 36 + 168;
935 else
936 pgaa_boost = 6;
937 mixa_boost = 0xF;
938 }
939
b88cdde9
RM		 940 cbias = is_pkg_fab_smic ? 0x35 : 0x30;
941
d3d178f0
RM		 942 for (i = 0; i < 2; i++) {
943 offset = i ? B2056_TX1 : B2056_TX0;
944
945 b43_radio_write(dev,
946 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost);
947 b43_radio_write(dev,
948 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost);
949 b43_radio_write(dev,
950 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost);
951 b43_radio_write(dev,
952 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost);
953 b43_radio_write(dev,
954 offset | B2056_TX_TXSPARE1, 0x30);
955 b43_radio_write(dev,
956 offset | B2056_TX_PA_SPARE2, 0xee);
957 b43_radio_write(dev,
958 offset | B2056_TX_PADA_CASCBIAS, 0x03);
959 b43_radio_write(dev,
b88cdde9 960 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30);
d3d178f0 961 b43_radio_write(dev,
b88cdde9 962 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30);
d3d178f0 963 b43_radio_write(dev,
b88cdde9 964 offset | B2056_TX_INTPAA_CASCBIAS, cbias);
d3d178f0 965 }
a2d9bc6f 966 }
38646eba 967
d4814e69
RM		 968 udelay(50);
969 /* VCO calibration */
970 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
971 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
972 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
973 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
974 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
975 udelay(300);
53a6e234
MB		 976}
977
d3d178f0
RM		 978static u8 b43_radio_2056_rcal(struct b43_wldev *dev)
979{
980 struct b43_phy *phy = &dev->phy;
981 u16 mast2, tmp;
982
983 if (phy->rev != 3)
984 return 0;
985
986 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2);
987 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7);
988
989 udelay(10);
990 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
991 udelay(10);
992 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09);
993
994 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100,
995 1000000)) {
996 b43err(dev->wl, "Radio recalibration timeout\n");
997 return 0;
998 }
999
1000 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01);
1001 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT);
1002 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00);
1003
1004 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2);
1005
1006 return tmp & 0x1f;
1007}
1008
ea7ee14b
RM		 1009static void b43_radio_init2056_pre(struct b43_wldev *dev)
1010{
1011 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1012 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
1013 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
1014 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1015 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1016 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1017 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
1018 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1019 B43_NPHY_RFCTL_CMD_CHIP0PU);
1020}
1021
1022static void b43_radio_init2056_post(struct b43_wldev *dev)
1023{
1024 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
1025 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
1026 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
1027 msleep(1);
1028 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
1029 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
1030 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
d3d178f0
RM		 1031 if (dev->phy.n->init_por)
1032 b43_radio_2056_rcal(dev);
ea7ee14b
RM		 1033}
1034
d817f4e1
RM		 1035/*
1036 * Initialize a Broadcom 2056 N-radio
1037 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
1038 */
1039static void b43_radio_init2056(struct b43_wldev *dev)
1040{
ea7ee14b
RM		 1041 b43_radio_init2056_pre(dev);
1042 b2056_upload_inittabs(dev, 0, 0);
1043 b43_radio_init2056_post(dev);
d3d178f0
RM		 1044
1045 dev->phy.n->init_por = false;
d817f4e1
RM		 1046}
1047
884a5228
RM		 1048/**************************************************
1049 * Radio 0x2055
1050 **************************************************/
1051
1052static void b43_chantab_radio_upload(struct b43_wldev *dev,
1053 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1054{
884a5228
RM		 1055 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
1056 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
1057 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
1058 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
1059 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
95b66bad 1060
884a5228
RM		 1061 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
1062 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
1063 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
1064 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
1065 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1066
884a5228
RM		 1067 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
1068 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
1069 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
1070 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
1071 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
e50cbcf6 1072
884a5228
RM		 1073 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
1074 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
1075 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
1076 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
1077 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1078
884a5228
RM		 1079 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
1080 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
1081 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
1082 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
1083 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
fe3e46e8 1084
884a5228
RM		 1085 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
1086 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
fe3e46e8
RM		 1087}
1088
884a5228
RM		 1089/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
1090static void b43_radio_2055_setup(struct b43_wldev *dev,
1091 const struct b43_nphy_channeltab_entry_rev2 *e)
95b66bad 1092{
884a5228 1093 B43_WARN_ON(dev->phy.rev >= 3);
95b66bad 1094
884a5228
RM		 1095 b43_chantab_radio_upload(dev, e);
1096 udelay(50);
1097 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
1098 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
1099 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
1100 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
1101 udelay(300);
95b66bad
MB		 1102}
1103
884a5228 1104static void b43_radio_init2055_pre(struct b43_wldev *dev)
ad9716e8 1105{
884a5228
RM		 1106 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1107 ~B43_NPHY_RFCTL_CMD_PORFORCE);
1108 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1109 B43_NPHY_RFCTL_CMD_CHIP0PU |
1110 B43_NPHY_RFCTL_CMD_OEPORFORCE);
1111 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1112 B43_NPHY_RFCTL_CMD_PORFORCE);
ad9716e8
RM		 1113}
1114
884a5228 1115static void b43_radio_init2055_post(struct b43_wldev *dev)
4f4ab6cd
RM		 1116{
1117 struct b43_phy_n *nphy = dev->phy.n;
884a5228 1118 struct ssb_sprom *sprom = dev->dev->bus_sprom;
884a5228 1119 bool workaround = false;
2faa6b83 1120
884a5228
RM		 1121 if (sprom->revision < 4)
1122 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
fb3bc67e 1123 && dev->dev->board_type == SSB_BOARD_CB2_4321
884a5228 1124 && dev->dev->board_rev >= 0x41);
2faa6b83 1125 else
884a5228
RM		 1126 workaround =
1127 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
2faa6b83 1128
884a5228
RM		 1129 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
1130 if (workaround) {
1131 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
1132 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
1133 }
1134 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
1135 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
1136 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
1137 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
1138 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
1139 msleep(1);
1140 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
0f941777 1141 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000))
884a5228
RM		 1142 b43err(dev->wl, "radio post init timeout\n");
1143 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
1144 b43_switch_channel(dev, dev->phy.channel);
1145 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
1146 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
1147 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
1148 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
1149 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
1150 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
1151 if (!nphy->gain_boost) {
1152 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
1153 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
1154 } else {
1155 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
1156 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
1157 }
1158 udelay(2);
2faa6b83
RM		 1159}
1160
884a5228
RM		 1161/*
1162 * Initialize a Broadcom 2055 N-radio
1163 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
1164 */
1165static void b43_radio_init2055(struct b43_wldev *dev)
a67162ab 1166{
884a5228
RM		 1167 b43_radio_init2055_pre(dev);
1168 if (b43_status(dev) < B43_STAT_INITIALIZED) {
1169 /* Follow wl, not specs. Do not force uploading all regs */
1170 b2055_upload_inittab(dev, 0, 0);
a67162ab 1171 } else {
884a5228
RM		 1172 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
1173 b2055_upload_inittab(dev, ghz5, 0);
a67162ab 1174 }
884a5228 1175 b43_radio_init2055_post(dev);
a67162ab
RM		 1176}
1177
8be89535
RM		 1178/**************************************************
1179 * Samples
1180 **************************************************/
026816fc 1181
8be89535
RM		 1182/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1183static int b43_nphy_load_samples(struct b43_wldev *dev,
1184 struct b43_c32 *samples, u16 len) {
1185 struct b43_phy_n *nphy = dev->phy.n;
1186 u16 i;
1187 u32 *data;
1188
1189 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1190 if (!data) {
1191 b43err(dev->wl, "allocation for samples loading failed\n");
1192 return -ENOMEM;
1193 }
1194 if (nphy->hang_avoid)
1195 b43_nphy_stay_in_carrier_search(dev, 1);
1196
1197 for (i = 0; i < len; i++) {
1198 data[i] = (samples[i].i & 0x3FF << 10);
1199 data[i] |= samples[i].q & 0x3FF;
1200 }
1201 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1202
1203 kfree(data);
1204 if (nphy->hang_avoid)
1205 b43_nphy_stay_in_carrier_search(dev, 0);
1206 return 0;
026816fc
RM		 1207}
1208
8be89535
RM		 1209/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1210static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1211 bool test)
026816fc 1212{
8be89535
RM		 1213 int i;
1214 u16 bw, len, rot, angle;
1215 struct b43_c32 *samples;
026816fc 1216
026816fc 1217
8be89535
RM		 1218 bw = (dev->phy.is_40mhz) ? 40 : 20;
1219 len = bw << 3;
026816fc 1220
8be89535
RM		 1221 if (test) {
1222 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1223 bw = 82;
1224 else
1225 bw = 80;
026816fc 1226
8be89535
RM		 1227 if (dev->phy.is_40mhz)
1228 bw <<= 1;
1229
1230 len = bw << 1;
026816fc
RM		 1231 }
1232
8be89535
RM		 1233 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1234 if (!samples) {
1235 b43err(dev->wl, "allocation for samples generation failed\n");
1236 return 0;
1237 }
1238 rot = (((freq * 36) / bw) << 16) / 100;
1239 angle = 0;
026816fc 1240
8be89535
RM		 1241 for (i = 0; i < len; i++) {
1242 samples[i] = b43_cordic(angle);
1243 angle += rot;
1244 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1245 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
026816fc 1246 }
8be89535
RM		 1247
1248 i = b43_nphy_load_samples(dev, samples, len);
1249 kfree(samples);
1250 return (i < 0) ? 0 : len;
026816fc
RM		 1251}
1252
8be89535
RM		 1253/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1254static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1255 u16 wait, bool iqmode, bool dac_test)
34a56f2c 1256{
8be89535 1257 struct b43_phy_n *nphy = dev->phy.n;
34a56f2c 1258 int i;
8be89535
RM		 1259 u16 seq_mode;
1260 u32 tmp;
34a56f2c 1261
bc36e994 1262 b43_nphy_stay_in_carrier_search(dev, true);
34a56f2c 1263
8be89535
RM		 1264 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1265 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1266 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1267 }
34a56f2c 1268
bc36e994 1269 /* TODO: add modify_bbmult argument */
8be89535
RM		 1270 if (!dev->phy.is_40mhz)
1271 tmp = 0x6464;
1272 else
1273 tmp = 0x4747;
1274 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
34a56f2c 1275
8be89535 1276 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
34a56f2c 1277
8be89535
RM		 1278 if (loops != 0xFFFF)
1279 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1280 else
1281 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
34a56f2c 1282
8be89535 1283 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
34a56f2c 1284
8be89535 1285 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
34a56f2c 1286
8be89535
RM		 1287 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1288 if (iqmode) {
1289 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1290 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1291 } else {
1292 if (dac_test)
1293 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1294 else
1295 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1296 }
1297 for (i = 0; i < 100; i++) {
2c8ac7eb 1298 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
8be89535
RM		 1299 i = 0;
1300 break;
34a56f2c 1301 }
8be89535 1302 udelay(10);
34a56f2c 1303 }
8be89535
RM		 1304 if (i)
1305 b43err(dev->wl, "run samples timeout\n");
34a56f2c 1306
8be89535 1307 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
bc36e994
RM		 1308
1309 b43_nphy_stay_in_carrier_search(dev, false);
34a56f2c
RM		 1310}
1311
4d9f46ba
RM		 1312/**************************************************
1313 * RSSI
1314 **************************************************/
1315
1316/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1317static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
6aa38725
RM		 1318 s8 offset, u8 core,
1319 enum n_rail_type rail,
2a2d0589 1320 enum n_rssi_type rssi_type)
09146400 1321{
4d9f46ba
RM		 1322 u16 tmp;
1323 bool core1or5 = (core == 1) || (core == 5);
1324 bool core2or5 = (core == 2) || (core == 5);
09146400 1325
4d9f46ba
RM		 1326 offset = clamp_val(offset, -32, 31);
1327 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
09146400 1328
e5ab1fd7 1329 switch (rssi_type) {
2a2d0589 1330 case N_RSSI_NB:
e5ab1fd7
RM		 1331 if (core1or5 && rail == N_RAIL_I)
1332 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1333 if (core1or5 && rail == N_RAIL_Q)
1334 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1335 if (core2or5 && rail == N_RAIL_I)
1336 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1337 if (core2or5 && rail == N_RAIL_Q)
1338 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1339 break;
2a2d0589 1340 case N_RSSI_W1:
e5ab1fd7
RM		 1341 if (core1or5 && rail == N_RAIL_I)
1342 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1343 if (core1or5 && rail == N_RAIL_Q)
1344 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1345 if (core2or5 && rail == N_RAIL_I)
1346 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1347 if (core2or5 && rail == N_RAIL_Q)
1348 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1349 break;
2a2d0589 1350 case N_RSSI_W2:
e5ab1fd7
RM		 1351 if (core1or5 && rail == N_RAIL_I)
1352 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1353 if (core1or5 && rail == N_RAIL_Q)
1354 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1355 if (core2or5 && rail == N_RAIL_I)
1356 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1357 if (core2or5 && rail == N_RAIL_Q)
1358 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1359 break;
2a2d0589 1360 case N_RSSI_TBD:
e5ab1fd7
RM		 1361 if (core1or5 && rail == N_RAIL_I)
1362 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1363 if (core1or5 && rail == N_RAIL_Q)
1364 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1365 if (core2or5 && rail == N_RAIL_I)
1366 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1367 if (core2or5 && rail == N_RAIL_Q)
1368 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1369 break;
2a2d0589 1370 case N_RSSI_IQ:
e5ab1fd7
RM		 1371 if (core1or5 && rail == N_RAIL_I)
1372 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1373 if (core1or5 && rail == N_RAIL_Q)
1374 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1375 if (core2or5 && rail == N_RAIL_I)
1376 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1377 if (core2or5 && rail == N_RAIL_Q)
1378 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1379 break;
2a2d0589 1380 case N_RSSI_TSSI_2G:
e5ab1fd7
RM		 1381 if (core1or5)
1382 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1383 if (core2or5)
1384 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1385 break;
2a2d0589 1386 case N_RSSI_TSSI_5G:
e5ab1fd7
RM		 1387 if (core1or5)
1388 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1389 if (core2or5)
1390 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1391 break;
1392 }
8987a9e9
RM		 1393}
1394
a3764ef7
RM		 1395static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1396 enum n_rssi_type rssi_type)
bbec398c 1397{
4d9f46ba
RM		 1398 u8 i;
1399 u16 reg, val;
bbec398c 1400
4d9f46ba
RM		 1401 if (code == 0) {
1402 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1403 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1404 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1405 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1406 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1407 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1408 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1409 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1410 } else {
1411 for (i = 0; i < 2; i++) {
1412 if ((code == 1 && i == 1) || (code == 2 && !i))
1413 continue;
bbec398c 1414
4d9f46ba
RM		 1415 reg = (i == 0) ?
1416 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1417 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
bbec398c 1418
a3764ef7
RM		 1419 if (rssi_type == N_RSSI_W1 ||
1420 rssi_type == N_RSSI_W2 ||
1421 rssi_type == N_RSSI_NB) {
4d9f46ba
RM		 1422 reg = (i == 0) ?
1423 B43_NPHY_AFECTL_C1 :
1424 B43_NPHY_AFECTL_C2;
1425 b43_phy_maskset(dev, reg, 0xFCFF, 0);
bbec398c 1426
4d9f46ba
RM		 1427 reg = (i == 0) ?
1428 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1429 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1430 b43_phy_maskset(dev, reg, 0xFFC3, 0);
bbec398c 1431
a3764ef7 1432 if (rssi_type == N_RSSI_W1)
4d9f46ba 1433 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
a3764ef7 1434 else if (rssi_type == N_RSSI_W2)
4d9f46ba
RM		 1435 val = 16;
1436 else
1437 val = 32;
1438 b43_phy_set(dev, reg, val);
5c1a140a 1439
4d9f46ba
RM		 1440 reg = (i == 0) ?
1441 B43_NPHY_TXF_40CO_B1S0 :
1442 B43_NPHY_TXF_40CO_B32S1;
1443 b43_phy_set(dev, reg, 0x0020);
1444 } else {
a3764ef7 1445 if (rssi_type == N_RSSI_TBD)
4d9f46ba 1446 val = 0x0100;
a3764ef7 1447 else if (rssi_type == N_RSSI_IQ)
4d9f46ba
RM		 1448 val = 0x0200;
1449 else
1450 val = 0x0300;
5c1a140a 1451
4d9f46ba
RM		 1452 reg = (i == 0) ?
1453 B43_NPHY_AFECTL_C1 :
1454 B43_NPHY_AFECTL_C2;
53ae8e8c 1455
4d9f46ba
RM		 1456 b43_phy_maskset(dev, reg, 0xFCFF, val);
1457 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
53ae8e8c 1458
a3764ef7
RM		 1459 if (rssi_type != N_RSSI_IQ &&
1460 rssi_type != N_RSSI_TBD) {
4d9f46ba
RM		 1461 enum ieee80211_band band =
1462 b43_current_band(dev->wl);
53ae8e8c 1463
4d9f46ba
RM		 1464 if (b43_nphy_ipa(dev))
1465 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1466 else
1467 val = 0x11;
1468 reg = (i == 0) ? 0x2000 : 0x3000;
1469 reg |= B2055_PADDRV;
0c201cfb 1470 b43_radio_write(dev, reg, val);
53ae8e8c 1471
4d9f46ba
RM		 1472 reg = (i == 0) ?
1473 B43_NPHY_AFECTL_OVER1 :
1474 B43_NPHY_AFECTL_OVER;
1475 b43_phy_set(dev, reg, 0x0200);
1476 }
1477 }
1478 }
53ae8e8c 1479 }
53ae8e8c
RM		 1480}
1481
a3764ef7
RM		 1482static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code,
1483 enum n_rssi_type rssi_type)
9442e5b5 1484{
4d9f46ba 1485 u16 val;
a3764ef7 1486 bool rssi_w1_w2_nb = false;
9442e5b5 1487
a3764ef7
RM		 1488 switch (rssi_type) {
1489 case N_RSSI_W1:
1490 case N_RSSI_W2:
1491 case N_RSSI_NB:
4d9f46ba 1492 val = 0;
a3764ef7
RM		 1493 rssi_w1_w2_nb = true;
1494 break;
1495 case N_RSSI_TBD:
4d9f46ba 1496 val = 1;
a3764ef7
RM		 1497 break;
1498 case N_RSSI_IQ:
4d9f46ba 1499 val = 2;
a3764ef7
RM		 1500 break;
1501 default:
4d9f46ba 1502 val = 3;
a3764ef7 1503 }
9442e5b5 1504
4d9f46ba
RM		 1505 val = (val << 12) | (val << 14);
1506 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1507 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
9442e5b5 1508
a3764ef7 1509 if (rssi_w1_w2_nb) {
4d9f46ba 1510 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
a3764ef7 1511 (rssi_type + 1) << 4);
4d9f46ba 1512 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
a3764ef7 1513 (rssi_type + 1) << 4);
9442e5b5
RM		 1514 }
1515
4d9f46ba
RM		 1516 if (code == 0) {
1517 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
a3764ef7 1518 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1519 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1520 ~(B43_NPHY_RFCTL_CMD_RXEN |
1521 B43_NPHY_RFCTL_CMD_CORESEL));
1522 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1523 ~(0x1 << 12 |
1524 0x1 << 5 |
1525 0x1 << 1 |
1526 0x1));
1527 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1528 ~B43_NPHY_RFCTL_CMD_START);
1529 udelay(20);
1530 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1531 }
1532 } else {
1533 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
a3764ef7 1534 if (rssi_w1_w2_nb) {
4d9f46ba
RM		 1535 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1536 ~(B43_NPHY_RFCTL_CMD_RXEN |
1537 B43_NPHY_RFCTL_CMD_CORESEL),
1538 (B43_NPHY_RFCTL_CMD_RXEN |
1539 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1540 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1541 (0x1 << 12 |
1542 0x1 << 5 |
1543 0x1 << 1 |
1544 0x1));
1545 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1546 B43_NPHY_RFCTL_CMD_START);
1547 udelay(20);
1548 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
9442e5b5 1549 }
9442e5b5 1550 }
9442e5b5
RM		 1551}
1552
4d9f46ba 1553/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
a3764ef7
RM		 1554static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code,
1555 enum n_rssi_type type)
d24019ad 1556{
4d9f46ba
RM		 1557 if (dev->phy.rev >= 3)
1558 b43_nphy_rev3_rssi_select(dev, code, type);
1559 else
1560 b43_nphy_rev2_rssi_select(dev, code, type);
1561}
d24019ad 1562
5ecab603 1563/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
a3764ef7
RM		 1564static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev,
1565 enum n_rssi_type rssi_type, u8 *buf)
5ecab603
RM		 1566{
1567 int i;
d24019ad 1568 for (i = 0; i < 2; i++) {
a3764ef7 1569 if (rssi_type == N_RSSI_NB) {
5ecab603
RM		 1570 if (i == 0) {
1571 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1572 0xFC, buf[0]);
1573 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1574 0xFC, buf[1]);
1575 } else {
1576 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1577 0xFC, buf[2 * i]);
1578 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1579 0xFC, buf[2 * i + 1]);
1580 }
d24019ad 1581 } else {
5ecab603
RM		 1582 if (i == 0)
1583 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1584 0xF3, buf[0] << 2);
1585 else
1586 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1587 0xF3, buf[2 * i + 1] << 2);
d24019ad 1588 }
d24019ad 1589 }
d24019ad
RM		 1590}
1591
5ecab603 1592/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
a3764ef7
RM		 1593static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type,
1594 s32 *buf, u8 nsamp)
ef5127a4 1595{
5ecab603
RM		 1596 int i;
1597 int out;
1598 u16 save_regs_phy[9];
1599 u16 s[2];
ef5127a4
RM		 1600
1601 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1602 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1603 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1604 save_regs_phy[2] = b43_phy_read(dev,
5ecab603 1605 B43_NPHY_RFCTL_LUT_TRSW_UP1);
3084f3b6 1606 save_regs_phy[3] = b43_phy_read(dev,
5ecab603 1607 B43_NPHY_RFCTL_LUT_TRSW_UP2);
5ecab603
RM		 1608 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1609 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1610 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1611 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1612 save_regs_phy[8] = 0;
ef5127a4 1613 } else {
5ecab603
RM		 1614 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1615 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1616 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1617 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1618 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1619 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1620 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1621 save_regs_phy[7] = 0;
1622 save_regs_phy[8] = 0;
1623 }
ef5127a4 1624
a3764ef7 1625 b43_nphy_rssi_select(dev, 5, rssi_type);
ef5127a4 1626
5ecab603
RM		 1627 if (dev->phy.rev < 2) {
1628 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1629 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1630 }
ef5127a4 1631
5ecab603
RM		 1632 for (i = 0; i < 4; i++)
1633 buf[i] = 0;
1634
1635 for (i = 0; i < nsamp; i++) {
1636 if (dev->phy.rev < 2) {
1637 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1638 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
ef5127a4 1639 } else {
5ecab603
RM		 1640 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1641 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
ef5127a4
RM		 1642 }
1643
5ecab603
RM		 1644 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1645 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1646 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1647 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1648 }
1649 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1650 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
ef5127a4 1651
5ecab603
RM		 1652 if (dev->phy.rev < 2)
1653 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
ef5127a4 1654
5ecab603 1655 if (dev->phy.rev >= 3) {
3084f3b6
RM		 1656 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1657 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
5ecab603 1658 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
3084f3b6 1659 save_regs_phy[2]);
5ecab603 1660 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
3084f3b6 1661 save_regs_phy[3]);
5ecab603
RM		 1662 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1663 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1664 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1665 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1666 } else {
1667 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1668 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1669 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1670 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1671 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1672 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1673 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1674 }
ef5127a4 1675
5ecab603
RM		 1676 return out;
1677}
ef5127a4 1678
e0c9a021
RM		 1679/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1680static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1681{
1682 struct b43_phy_n *nphy = dev->phy.n;
1683
1684 u16 saved_regs_phy_rfctl[2];
97e2a1a1
RM		 1685 u16 saved_regs_phy[22];
1686 u16 regs_to_store_rev3[] = {
e0c9a021
RM		 1687 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1688 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1689 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1690 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1691 B43_NPHY_RFCTL_CMD,
1692 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1693 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1694 };
97e2a1a1
RM		 1695 u16 regs_to_store_rev7[] = {
1696 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1697 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1698 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1699 0x342, 0x343, 0x346, 0x347,
1700 0x2ff,
1701 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1702 B43_NPHY_RFCTL_CMD,
1703 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1704 0x340, 0x341, 0x344, 0x345,
1705 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1706 };
1707 u16 *regs_to_store;
1708 int regs_amount;
e0c9a021
RM		 1709
1710 u16 class;
1711
1712 u16 clip_state[2];
1713 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1714
1715 u8 vcm_final = 0;
2e1253d6 1716 s32 offset[4];
e0c9a021
RM		 1717 s32 results[8][4] = { };
1718 s32 results_min[4] = { };
1719 s32 poll_results[4] = { };
1720
1721 u16 *rssical_radio_regs = NULL;
1722 u16 *rssical_phy_regs = NULL;
1723
1724 u16 r; /* routing */
1725 u8 rx_core_state;
37859a75 1726 int core, i, j, vcm;
e0c9a021 1727
97e2a1a1
RM		 1728 if (dev->phy.rev >= 7) {
1729 regs_to_store = regs_to_store_rev7;
1730 regs_amount = ARRAY_SIZE(regs_to_store_rev7);
1731 } else {
1732 regs_to_store = regs_to_store_rev3;
1733 regs_amount = ARRAY_SIZE(regs_to_store_rev3);
1734 }
1735 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy));
1736
e0c9a021
RM		 1737 class = b43_nphy_classifier(dev, 0, 0);
1738 b43_nphy_classifier(dev, 7, 4);
1739 b43_nphy_read_clip_detection(dev, clip_state);
1740 b43_nphy_write_clip_detection(dev, clip_off);
1741
1742 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1743 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
97e2a1a1 1744 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1745 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1746
89e43dad
RM		 1747 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7);
1748 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7);
97e2a1a1
RM		 1749
1750 if (dev->phy.rev >= 7) {
1751 /* TODO */
1752 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1753 } else {
1754 }
e0c9a021 1755 } else {
97e2a1a1
RM		 1756 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false);
1757 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false);
1758 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false);
1759 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false);
1760 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1761 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false);
1762 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false);
1763 } else {
1764 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false);
1765 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false);
1766 }
e0c9a021
RM		 1767 }
1768
1769 rx_core_state = b43_nphy_get_rx_core_state(dev);
1770 for (core = 0; core < 2; core++) {
1771 if (!(rx_core_state & (1 << core)))
1772 continue;
1773 r = core ? B2056_RX1 : B2056_RX0;
a3764ef7
RM		 1774 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I,
1775 N_RSSI_NB);
1776 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q,
1777 N_RSSI_NB);
37859a75
RM		 1778
1779 /* Grab RSSI results for every possible VCM */
1780 for (vcm = 0; vcm < 8; vcm++) {
97e2a1a1
RM		 1781 if (dev->phy.rev >= 7)
1782 ;
1783 else
1784 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1785 0xE3, vcm << 2);
a3764ef7 1786 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8);
e0c9a021 1787 }
37859a75
RM		 1788
1789 /* Find out which VCM got the best results */
cddec902 1790 for (i = 0; i < 4; i += 2) {
37859a75 1791 s32 currd;
e67dd874 1792 s32 mind = 0x100000;
e0c9a021
RM		 1793 s32 minpoll = 249;
1794 u8 minvcm = 0;
1795 if (2 * core != i)
1796 continue;
37859a75
RM		 1797 for (vcm = 0; vcm < 8; vcm++) {
1798 currd = results[vcm][i] * results[vcm][i] +
1799 results[vcm][i + 1] * results[vcm][i];
1800 if (currd < mind) {
1801 mind = currd;
1802 minvcm = vcm;
e0c9a021 1803 }
37859a75
RM		 1804 if (results[vcm][i] < minpoll)
1805 minpoll = results[vcm][i];
e0c9a021
RM		 1806 }
1807 vcm_final = minvcm;
1808 results_min[i] = minpoll;
1809 }
37859a75
RM		 1810
1811 /* Select the best VCM */
97e2a1a1
RM		 1812 if (dev->phy.rev >= 7)
1813 ;
1814 else
1815 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC,
1816 0xE3, vcm_final << 2);
37859a75 1817
e0c9a021
RM		 1818 for (i = 0; i < 4; i++) {
1819 if (core != i / 2)
1820 continue;
1821 offset[i] = -results[vcm_final][i];
1822 if (offset[i] < 0)
1823 offset[i] = -((abs(offset[i]) + 4) / 8);
1824 else
1825 offset[i] = (offset[i] + 4) / 8;
1826 if (results_min[i] == 248)
1827 offset[i] = -32;
1828 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1829 (i / 2 == 0) ? 1 : 2,
6aa38725 1830 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q,
a3764ef7 1831 N_RSSI_NB);
e0c9a021
RM		 1832 }
1833 }
37859a75 1834
e0c9a021
RM		 1835 for (core = 0; core < 2; core++) {
1836 if (!(rx_core_state & (1 << core)))
1837 continue;
1838 for (i = 0; i < 2; i++) {
6aa38725
RM		 1839 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1840 N_RAIL_I, i);
1841 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1,
1842 N_RAIL_Q, i);
e0c9a021
RM		 1843 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1844 for (j = 0; j < 4; j++) {
cddec902 1845 if (j / 2 == core) {
e0c9a021 1846 offset[j] = 232 - poll_results[j];
cddec902
RM		 1847 if (offset[j] < 0)
1848 offset[j] = -(abs(offset[j] + 4) / 8);
1849 else
1850 offset[j] = (offset[j] + 4) / 8;
1851 b43_nphy_scale_offset_rssi(dev, 0,
1852 offset[2 * core], core + 1, j % 2, i);
1853 }
e0c9a021
RM		 1854 }
1855 }
1856 }
1857
1858 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1859 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1860
1861 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1862
1863 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1864 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1865 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1866
1867 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1868 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
bc36e994 1869 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
e0c9a021 1870
97e2a1a1 1871 for (i = 0; i < regs_amount; i++)
e0c9a021
RM		 1872 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1873
1874 /* Store for future configuration */
1875 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1876 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1877 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1878 } else {
1879 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1880 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1881 }
9a98979e
RM		 1882 if (dev->phy.rev >= 7) {
1883 } else {
1884 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 |
1885 B2056_RX_RSSI_MISC);
1886 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 |
1887 B2056_RX_RSSI_MISC);
1888 }
e0c9a021
RM		 1889 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1890 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1891 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1892 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1893 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1894 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1895 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1896 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1897 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1898 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1899 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1900 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1901
1902 /* Remember for which channel we store configuration */
1903 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1904 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1905 else
1906 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1907
1908 /* End of calibration, restore configuration */
1909 b43_nphy_classifier(dev, 7, class);
1910 b43_nphy_write_clip_detection(dev, clip_state);
1911}
1912
5ecab603 1913/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
a3764ef7 1914static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
5ecab603 1915{
37859a75 1916 int i, j, vcm;
5ecab603
RM		 1917 u8 state[4];
1918 u8 code, val;
1919 u16 class, override;
1920 u8 regs_save_radio[2];
1921 u16 regs_save_phy[2];
1922
2e1253d6 1923 s32 offset[4];
5ecab603
RM		 1924 u8 core;
1925 u8 rail;
1926
1927 u16 clip_state[2];
1928 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1929 s32 results_min[4] = { };
1930 u8 vcm_final[4] = { };
1931 s32 results[4][4] = { };
1932 s32 miniq[4][2] = { };
1933
a3764ef7 1934 if (type == N_RSSI_NB) {
5ecab603
RM		 1935 code = 0;
1936 val = 6;
a3764ef7 1937 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) {
5ecab603
RM		 1938 code = 25;
1939 val = 4;
1940 } else {
1941 B43_WARN_ON(1);
1942 return;
1943 }
1944
1945 class = b43_nphy_classifier(dev, 0, 0);
1946 b43_nphy_classifier(dev, 7, 4);
1947 b43_nphy_read_clip_detection(dev, clip_state);
1948 b43_nphy_write_clip_detection(dev, clip_off);
1949
1950 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1951 override = 0x140;
1952 else
1953 override = 0x110;
1954
1955 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
0c201cfb 1956 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
5ecab603 1957 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
0c201cfb 1958 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
5ecab603
RM		 1959
1960 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
0c201cfb 1961 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
5ecab603 1962 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
0c201cfb 1963 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
5ecab603 1964
0c201cfb
RM		 1965 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1966 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
5ecab603
RM		 1967 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1968 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
0c201cfb
RM		 1969 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1970 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
5ecab603
RM		 1971
1972 b43_nphy_rssi_select(dev, 5, type);
6aa38725
RM		 1973 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
1974 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type);
5ecab603 1975
37859a75 1976 for (vcm = 0; vcm < 4; vcm++) {
5ecab603
RM		 1977 u8 tmp[4];
1978 for (j = 0; j < 4; j++)
37859a75 1979 tmp[j] = vcm;
a3764ef7 1980 if (type != N_RSSI_W2)
5ecab603 1981 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
37859a75 1982 b43_nphy_poll_rssi(dev, type, results[vcm], 8);
a3764ef7 1983 if (type == N_RSSI_W1 || type == N_RSSI_W2)
5ecab603 1984 for (j = 0; j < 2; j++)
37859a75
RM		 1985 miniq[vcm][j] = min(results[vcm][2 * j],
1986 results[vcm][2 * j + 1]);
5ecab603
RM		 1987 }
1988
1989 for (i = 0; i < 4; i++) {
e67dd874 1990 s32 mind = 0x100000;
5ecab603
RM		 1991 u8 minvcm = 0;
1992 s32 minpoll = 249;
37859a75
RM		 1993 s32 currd;
1994 for (vcm = 0; vcm < 4; vcm++) {
a3764ef7 1995 if (type == N_RSSI_NB)
542e15f3 1996 currd = abs(results[vcm][i] - code * 8);
5ecab603 1997 else
37859a75 1998 currd = abs(miniq[vcm][i / 2] - code * 8);
5ecab603 1999
37859a75
RM		 2000 if (currd < mind) {
2001 mind = currd;
2002 minvcm = vcm;
5ecab603
RM		 2003 }
2004
37859a75
RM		 2005 if (results[vcm][i] < minpoll)
2006 minpoll = results[vcm][i];
8e60b044 2007 }
5ecab603
RM		 2008 results_min[i] = minpoll;
2009 vcm_final[i] = minvcm;
2010 }
ef5127a4 2011
a3764ef7 2012 if (type != N_RSSI_W2)
5ecab603 2013 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
ef5127a4 2014
5ecab603
RM		 2015 for (i = 0; i < 4; i++) {
2016 offset[i] = (code * 8) - results[vcm_final[i]][i];
2017
2018 if (offset[i] < 0)
2019 offset[i] = -((abs(offset[i]) + 4) / 8);
2020 else
2021 offset[i] = (offset[i] + 4) / 8;
2022
2023 if (results_min[i] == 248)
2024 offset[i] = code - 32;
2025
2026 core = (i / 2) ? 2 : 1;
6aa38725 2027 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I;
5ecab603
RM		 2028
2029 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
2030 type);
2031 }
2032
2033 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2034 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
2035
2036 switch (state[2]) {
2037 case 1:
a3764ef7 2038 b43_nphy_rssi_select(dev, 1, N_RSSI_NB);
5ecab603
RM		 2039 break;
2040 case 4:
a3764ef7 2041 b43_nphy_rssi_select(dev, 1, N_RSSI_W1);
5ecab603
RM		 2042 break;
2043 case 2:
a3764ef7 2044 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2045 break;
2046 default:
a3764ef7 2047 b43_nphy_rssi_select(dev, 1, N_RSSI_W2);
5ecab603
RM		 2048 break;
2049 }
2050
2051 switch (state[3]) {
2052 case 1:
a3764ef7 2053 b43_nphy_rssi_select(dev, 2, N_RSSI_NB);
5ecab603
RM		 2054 break;
2055 case 4:
a3764ef7 2056 b43_nphy_rssi_select(dev, 2, N_RSSI_W1);
5ecab603
RM		 2057 break;
2058 default:
a3764ef7 2059 b43_nphy_rssi_select(dev, 2, N_RSSI_W2);
5ecab603
RM		 2060 break;
2061 }
2062
2063 b43_nphy_rssi_select(dev, 0, type);
2064
2065 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
0c201cfb 2066 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
5ecab603 2067 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
0c201cfb 2068 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
5ecab603
RM		 2069
2070 b43_nphy_classifier(dev, 7, class);
2071 b43_nphy_write_clip_detection(dev, clip_state);
2072 /* Specs don't say about reset here, but it makes wl and b43 dumps
2073 identical, it really seems wl performs this */
2074 b43_nphy_reset_cca(dev);
2075}
2076
5ecab603
RM		 2077/*
2078 * RSSI Calibration
2079 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2080 */
2081static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2082{
2083 if (dev->phy.rev >= 3) {
2084 b43_nphy_rev3_rssi_cal(dev);
2085 } else {
2a2d0589
RM		 2086 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB);
2087 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1);
2088 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2);
5ecab603
RM		 2089 }
2090}
2091
64712095
RM		 2092/**************************************************
2093 * Workarounds
2094 **************************************************/
2095
2096static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2097{
2098 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2099
2100 bool ghz5;
2101 bool ext_lna;
2102 u16 rssi_gain;
2103 struct nphy_gain_ctl_workaround_entry *e;
2104 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
2105 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
2106
2107 /* Prepare values */
2108 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
2109 & B43_NPHY_BANDCTL_5GHZ;
ed5103ed
RM		 2110 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
2111 sprom->boardflags_lo & B43_BFL_EXTLNA;
64712095
RM		 2112 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
2113 if (ghz5 && dev->phy.rev >= 5)
2114 rssi_gain = 0x90;
2115 else
2116 rssi_gain = 0x50;
2117
2118 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
2119
2120 /* Set Clip 2 detect */
04519dc6
RM		 2121 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2122 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
64712095
RM		 2123
2124 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2125 0x17);
2126 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
2127 0x17);
2128 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
2129 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
2130 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
2131 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
2132 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
2133 rssi_gain);
2134 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
2135 rssi_gain);
2136 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2137 0x17);
2138 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
2139 0x17);
2140 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
2141 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
2142
2143 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
2144 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
2145 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
2146 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
2147 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
2148 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
2149 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
2150 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
2151 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
2152 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
2153 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2154 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2155
04519dc6
RM		 2156 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2157 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2158
64712095
RM		 2159 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2160 e->rfseq_init);
64712095 2161
04519dc6
RM		 2162 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2163 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2164 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2165 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2166 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2167 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2168
2169 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2170 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2171 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
64712095
RM		 2172 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2173 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2174 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2175 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
2176 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2177 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
2178 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2179}
2180
2181static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2182{
2183 struct b43_phy_n *nphy = dev->phy.n;
2184
2185 u8 i, j;
2186 u8 code;
2187 u16 tmp;
2188 u8 rfseq_events[3] = { 6, 8, 7 };
2189 u8 rfseq_delays[3] = { 10, 30, 1 };
2190
2191 /* Set Clip 2 detect */
2192 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
2193 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
2194
2195 /* Set narrowband clip threshold */
2196 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2197 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2198
2199 if (!dev->phy.is_40mhz) {
2200 /* Set dwell lengths */
2201 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2202 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
2203 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
2204 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
2205 }
2206
2207 /* Set wideband clip 2 threshold */
2208 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
2209 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
2210 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2211 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2212
2213 if (!dev->phy.is_40mhz) {
2214 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2215 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2216 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
2217 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
2218 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
2219 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
2220 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
2221 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
2222 }
2223
2224 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
2225
2226 if (nphy->gain_boost) {
2227 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2228 dev->phy.is_40mhz)
2229 code = 4;
2230 else
2231 code = 5;
2232 } else {
2233 code = dev->phy.is_40mhz ? 6 : 7;
2234 }
2235
2236 /* Set HPVGA2 index */
2237 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
2238 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
2239 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
2240 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
2241
2242 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2243 /* specs say about 2 loops, but wl does 4 */
2244 for (i = 0; i < 4; i++)
2245 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
2246
2247 b43_nphy_adjust_lna_gain_table(dev);
2248
2249 if (nphy->elna_gain_config) {
2250 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
2251 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2252 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2253 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2254 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2255
2256 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
2257 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
2258 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2259 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2260 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
2261
2262 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
2263 /* specs say about 2 loops, but wl does 4 */
2264 for (i = 0; i < 4; i++)
2265 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
2266 (code << 8 | 0x74));
2267 }
2268
2269 if (dev->phy.rev == 2) {
2270 for (i = 0; i < 4; i++) {
2271 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
2272 (0x0400 * i) + 0x0020);
2273 for (j = 0; j < 21; j++) {
2274 tmp = j * (i < 2 ? 3 : 1);
2275 b43_phy_write(dev,
2276 B43_NPHY_TABLE_DATALO, tmp);
2277 }
2278 }
ef5127a4 2279 }
64712095
RM		 2280
2281 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
2282 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
2283 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
2284 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
2285
2286 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2287 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
2288}
2289
2290/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
2291static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2292{
d11d354b
RM		 2293 if (dev->phy.rev >= 7)
2294 ; /* TODO */
2295 else if (dev->phy.rev >= 3)
64712095
RM		 2296 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
2297 else
2298 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
ef5127a4
RM		 2299}
2300
d11d354b
RM		 2301/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */
2302static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2303{
2304 if (!offset)
2305 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154;
2306 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2307}
2308
2309static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2310{
2311 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2312 struct b43_phy *phy = &dev->phy;
2313
2314 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2315 0x1F };
2316 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2317
2318 u16 ntab7_15e_16e[] = { 0x10f, 0x10f };
2319 u8 ntab7_138_146[] = { 0x11, 0x11 };
2320 u8 ntab7_133[] = { 0x77, 0x11, 0x11 };
2321
2322 u16 lpf_20, lpf_40, lpf_11b;
2323 u16 bcap_val, bcap_val_11b, bcap_val_11n_20, bcap_val_11n_40;
2324 u16 scap_val, scap_val_11b, scap_val_11n_20, scap_val_11n_40;
2325 bool rccal_ovrd = false;
2326
2327 u16 rx2tx_lut_20_11b, rx2tx_lut_20_11n, rx2tx_lut_40_11n;
2328 u16 bias, conv, filt;
2329
2330 u32 tmp32;
2331 u8 core;
2332
2333 if (phy->rev == 7) {
2334 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10);
2335 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020);
2336 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700);
2337 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E);
2338 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300);
2339 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037);
2340 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00);
2341 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C);
2342 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00);
2343 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E);
2344 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00);
2345 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040);
2346 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000);
2347 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040);
2348 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000);
2349 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040);
2350 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2351 }
2352 if (phy->rev <= 8) {
04519dc6
RM		 2353 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2354 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
d11d354b
RM		 2355 }
2356 if (phy->rev >= 8)
2357 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
2358
2359 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2);
2360 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2);
2361 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2362 tmp32 &= 0xffffff;
2363 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
2364 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15e), 2, ntab7_15e_16e);
2365 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16e), 2, ntab7_15e_16e);
2366
2367 if (b43_nphy_ipa(dev))
2368 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2369 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2370
04519dc6
RM		 2371 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2372 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
d11d354b
RM		 2373
2374 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2375 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2376 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2377 if (b43_nphy_ipa(dev)) {
2378 if ((phy->radio_rev == 5 && phy->is_40mhz) ||
2379 phy->radio_rev == 7 || phy->radio_rev == 8) {
2380 bcap_val = b43_radio_read(dev, 0x16b);
2381 scap_val = b43_radio_read(dev, 0x16a);
2382 scap_val_11b = scap_val;
2383 bcap_val_11b = bcap_val;
2384 if (phy->radio_rev == 5 && phy->is_40mhz) {
2385 scap_val_11n_20 = scap_val;
2386 bcap_val_11n_20 = bcap_val;
2387 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
2388 rccal_ovrd = true;
2389 } else { /* Rev 7/8 */
2390 lpf_20 = 4;
2391 lpf_11b = 1;
2392 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2393 scap_val_11n_20 = 0xc;
2394 bcap_val_11n_20 = 0xc;
2395 scap_val_11n_40 = 0xa;
2396 bcap_val_11n_40 = 0xa;
2397 } else {
2398 scap_val_11n_20 = 0x14;
2399 bcap_val_11n_20 = 0x14;
2400 scap_val_11n_40 = 0xf;
2401 bcap_val_11n_40 = 0xf;
2402 }
2403 rccal_ovrd = true;
2404 }
2405 }
2406 } else {
2407 if (phy->radio_rev == 5) {
2408 lpf_20 = 1;
2409 lpf_40 = 3;
2410 bcap_val = b43_radio_read(dev, 0x16b);
2411 scap_val = b43_radio_read(dev, 0x16a);
2412 scap_val_11b = scap_val;
2413 bcap_val_11b = bcap_val;
2414 scap_val_11n_20 = 0x11;
2415 scap_val_11n_40 = 0x11;
2416 bcap_val_11n_20 = 0x13;
2417 bcap_val_11n_40 = 0x13;
2418 rccal_ovrd = true;
2419 }
2420 }
2421 if (rccal_ovrd) {
2422 rx2tx_lut_20_11b = (bcap_val_11b << 8) |
2423 (scap_val_11b << 3) |
2424 lpf_11b;
2425 rx2tx_lut_20_11n = (bcap_val_11n_20 << 8) |
2426 (scap_val_11n_20 << 3) |
2427 lpf_20;
2428 rx2tx_lut_40_11n = (bcap_val_11n_40 << 8) |
2429 (scap_val_11n_40 << 3) |
2430 lpf_40;
2431 for (core = 0; core < 2; core++) {
2432 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16),
2433 rx2tx_lut_20_11b);
2434 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16),
2435 rx2tx_lut_20_11n);
2436 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16),
2437 rx2tx_lut_20_11n);
2438 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16),
2439 rx2tx_lut_40_11n);
2440 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16),
2441 rx2tx_lut_40_11n);
2442 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16),
2443 rx2tx_lut_40_11n);
2444 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16),
2445 rx2tx_lut_40_11n);
2446 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16),
2447 rx2tx_lut_40_11n);
2448 }
78ae7532 2449 b43_nphy_rf_ctl_override_rev7(dev, 16, 1, 3, false, 2);
d11d354b
RM		 2450 }
2451 b43_phy_write(dev, 0x32F, 0x3);
2452 if (phy->radio_rev == 4 || phy->radio_rev == 6)
78ae7532 2453 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0);
d11d354b
RM		 2454
2455 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) {
2456 if (sprom->revision &&
2457 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) {
2458 b43_radio_write(dev, 0x5, 0x05);
2459 b43_radio_write(dev, 0x6, 0x30);
2460 b43_radio_write(dev, 0x7, 0x00);
2461 b43_radio_set(dev, 0x4f, 0x1);
2462 b43_radio_set(dev, 0xd4, 0x1);
2463 bias = 0x1f;
2464 conv = 0x6f;
2465 filt = 0xaa;
2466 } else {
2467 bias = 0x2b;
2468 conv = 0x7f;
2469 filt = 0xee;
2470 }
2471 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2472 for (core = 0; core < 2; core++) {
2473 if (core == 0) {
2474 b43_radio_write(dev, 0x5F, bias);
2475 b43_radio_write(dev, 0x64, conv);
2476 b43_radio_write(dev, 0x66, filt);
2477 } else {
2478 b43_radio_write(dev, 0xE8, bias);
2479 b43_radio_write(dev, 0xE9, conv);
2480 b43_radio_write(dev, 0xEB, filt);
2481 }
2482 }
2483 }
2484 }
2485
2486 if (b43_nphy_ipa(dev)) {
2487 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2488 if (phy->radio_rev == 3 || phy->radio_rev == 4 ||
2489 phy->radio_rev == 6) {
2490 for (core = 0; core < 2; core++) {
2491 if (core == 0)
2492 b43_radio_write(dev, 0x51,
2493 0x7f);
2494 else
2495 b43_radio_write(dev, 0xd6,
2496 0x7f);
2497 }
2498 }
2499 if (phy->radio_rev == 3) {
2500 for (core = 0; core < 2; core++) {
2501 if (core == 0) {
2502 b43_radio_write(dev, 0x64,
2503 0x13);
2504 b43_radio_write(dev, 0x5F,
2505 0x1F);
2506 b43_radio_write(dev, 0x66,
2507 0xEE);
2508 b43_radio_write(dev, 0x59,
2509 0x8A);
2510 b43_radio_write(dev, 0x80,
2511 0x3E);
2512 } else {
2513 b43_radio_write(dev, 0x69,
2514 0x13);
2515 b43_radio_write(dev, 0xE8,
2516 0x1F);
2517 b43_radio_write(dev, 0xEB,
2518 0xEE);
2519 b43_radio_write(dev, 0xDE,
2520 0x8A);
2521 b43_radio_write(dev, 0x105,
2522 0x3E);
2523 }
2524 }
2525 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2526 if (!phy->is_40mhz) {
2527 b43_radio_write(dev, 0x5F, 0x14);
2528 b43_radio_write(dev, 0xE8, 0x12);
2529 } else {
2530 b43_radio_write(dev, 0x5F, 0x16);
2531 b43_radio_write(dev, 0xE8, 0x16);
2532 }
2533 }
2534 } else {
2535 u16 freq = phy->channel_freq;
2536 if ((freq >= 5180 && freq <= 5230) ||
2537 (freq >= 5745 && freq <= 5805)) {
2538 b43_radio_write(dev, 0x7D, 0xFF);
2539 b43_radio_write(dev, 0xFE, 0xFF);
2540 }
2541 }
2542 } else {
2543 if (phy->radio_rev != 5) {
2544 for (core = 0; core < 2; core++) {
2545 if (core == 0) {
2546 b43_radio_write(dev, 0x5c, 0x61);
2547 b43_radio_write(dev, 0x51, 0x70);
2548 } else {
2549 b43_radio_write(dev, 0xe1, 0x61);
2550 b43_radio_write(dev, 0xd6, 0x70);
2551 }
2552 }
2553 }
2554 }
2555
2556 if (phy->radio_rev == 4) {
2557 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2558 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2559 for (core = 0; core < 2; core++) {
2560 if (core == 0) {
2561 b43_radio_write(dev, 0x1a1, 0x00);
2562 b43_radio_write(dev, 0x1a2, 0x3f);
2563 b43_radio_write(dev, 0x1a6, 0x3f);
2564 } else {
2565 b43_radio_write(dev, 0x1a7, 0x00);
2566 b43_radio_write(dev, 0x1ab, 0x3f);
2567 b43_radio_write(dev, 0x1ac, 0x3f);
2568 }
2569 }
2570 } else {
2571 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4);
2572 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4);
2573 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4);
2574 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4);
2575
2576 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1);
2577 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1);
2578 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1);
2579 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1);
2580 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20);
2581 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20);
2582
2583 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4);
2584 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4);
2585 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4);
2586 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4);
2587 }
2588
2589 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2);
2590
2591 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20);
2592 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x138), 2, ntab7_138_146);
2593 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77);
2594 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x133), 3, ntab7_133);
2595 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x146), 2, ntab7_138_146);
2596 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2597 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2598
2599 if (!phy->is_40mhz) {
2600 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2601 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2602 } else {
2603 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x14D);
2604 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x14D);
2605 }
2606
2607 b43_nphy_gain_ctl_workarounds(dev);
2608
2609 /* TODO
2610 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4,
2611 aux_adc_vmid_rev7_core0);
2612 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4,
2613 aux_adc_vmid_rev7_core1);
2614 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4,
2615 aux_adc_gain_rev7);
2616 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4,
2617 aux_adc_gain_rev7);
2618 */
2619}
2620
73d07a39 2621static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
28fd7daa 2622{
0eff8fcd 2623 struct b43_phy_n *nphy = dev->phy.n;
0581483a 2624 struct ssb_sprom *sprom = dev->dev->bus_sprom;
28fd7daa 2625
0eff8fcd 2626 /* TX to RX */
c378bb97
RM		 2627 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F };
2628 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 };
0eff8fcd
RM		 2629 /* RX to TX */
2630 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
2631 0x1F };
2632 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
2633 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
2634 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
2635
c378bb97
RM		 2636 u16 vmids[5][4] = {
2637 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */
2638 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */
2639 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */
2640 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */
2641 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */
2642 };
2643 u16 gains[5][4] = {
2644 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */
2645 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */
2646 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */
2647 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */
2648 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */
2649 };
2650 u16 *vmid, *gain;
2651
2652 u8 pdet_range;
ba9a6214
RM		 2653 u16 tmp16;
2654 u32 tmp32;
2655
04519dc6
RM		 2656 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2657 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
c56da252 2658
73d07a39
RM		 2659 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2660 tmp32 &= 0xffffff;
2661 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
28fd7daa 2662
73d07a39
RM		 2663 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
2664 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
2665 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
2666 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
2667 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2668 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
28fd7daa 2669
04519dc6
RM		 2670 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2671 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
ba9a6214 2672
0eff8fcd 2673 /* TX to RX */
c56da252
RM		 2674 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
2675 ARRAY_SIZE(tx2rx_events));
0eff8fcd
RM		 2676
2677 /* RX to TX */
2678 if (b43_nphy_ipa(dev))
c56da252
RM		 2679 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2680 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
0eff8fcd
RM		 2681 if (nphy->hw_phyrxchain != 3 &&
2682 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
2683 if (b43_nphy_ipa(dev)) {
2684 rx2tx_delays[5] = 59;
2685 rx2tx_delays[6] = 1;
2686 rx2tx_events[7] = 0x1F;
2687 }
fa0f2b38 2688 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays,
c56da252 2689 ARRAY_SIZE(rx2tx_events));
0eff8fcd 2690 }
ba9a6214 2691
73d07a39
RM		 2692 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
2693 0x2 : 0x9C40;
2694 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
ba9a6214 2695
04519dc6 2696 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
ba9a6214 2697
fa0f2b38
RM		 2698 if (!dev->phy.is_40mhz) {
2699 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2700 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2701 } else {
2702 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D);
2703 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D);
2704 }
ba9a6214 2705
3ccd0957 2706 b43_nphy_gain_ctl_workarounds(dev);
ba9a6214 2707
c56da252
RM		 2708 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
2709 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
ba9a6214 2710
c378bb97
RM		 2711 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2712 pdet_range = sprom->fem.ghz2.pdet_range;
2713 else
2714 pdet_range = sprom->fem.ghz5.pdet_range;
2715 vmid = vmids[min_t(u16, pdet_range, 4)];
2716 gain = gains[min_t(u16, pdet_range, 4)];
2717 switch (pdet_range) {
2718 case 3:
2719 if (!(dev->phy.rev >= 4 &&
2720 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2721 break;
2722 /* FALL THROUGH */
2723 case 0:
2724 case 1:
2725 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2726 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2727 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2728 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2729 break;
2730 case 2:
2731 if (dev->phy.rev >= 6) {
2732 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2733 vmid[3] = 0x94;
2734 else
2735 vmid[3] = 0x8e;
2736 gain[3] = 3;
2737 } else if (dev->phy.rev == 5) {
2738 vmid[3] = 0x84;
2739 gain[3] = 2;
2740 }
2741 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2742 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2743 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2744 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2745 break;
2746 case 4:
2747 case 5:
2748 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) {
2749 if (pdet_range == 4) {
2750 vmid[3] = 0x8e;
2751 tmp16 = 0x96;
2752 gain[3] = 0x2;
2753 } else {
2754 vmid[3] = 0x89;
2755 tmp16 = 0x89;
2756 gain[3] = 0;
2757 }
2758 } else {
2759 if (pdet_range == 4) {
2760 vmid[3] = 0x89;
2761 tmp16 = 0x8b;
2762 gain[3] = 0x2;
2763 } else {
2764 vmid[3] = 0x74;
2765 tmp16 = 0x70;
2766 gain[3] = 0;
2767 }
2768 }
2769 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid);
2770 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain);
2771 vmid[3] = tmp16;
2772 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid);
2773 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain);
2774 break;
2775 }
ba9a6214 2776
73d07a39
RM		 2777 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2778 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
2779 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2780 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
2781 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2782 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
2783 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
2784 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
c56da252
RM		 2785 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
2786 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
73d07a39
RM		 2787 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2788 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
2789
2790 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
2791
2792 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
2793 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
2794 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
2795 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
2796 tmp32 = 0x00088888;
2797 else
2798 tmp32 = 0x88888888;
2799 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
2800 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
2801 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
2802
2803 if (dev->phy.rev == 4 &&
fa0f2b38 2804 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
73d07a39
RM		 2805 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
2806 0x70);
2807 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
2808 0x70);
2809 }
ba9a6214 2810
fa0f2b38 2811 /* Dropped probably-always-true condition */
04519dc6
RM		 2812 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2813 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
bc36e994 2814 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341);
04519dc6
RM		 2815 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2816 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2817 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2818 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2819 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2820 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2821 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2822 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2823 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
fa0f2b38
RM		 2824
2825 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2826 ; /* TODO: 0x0080000000000000 HF */
73d07a39 2827}
ba9a6214 2828
73d07a39
RM		 2829static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
2830{
2831 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2832 struct b43_phy *phy = &dev->phy;
2833 struct b43_phy_n *nphy = phy->n;
ba9a6214 2834
73d07a39
RM		 2835 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
2836 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
ba9a6214 2837
73d07a39
RM		 2838 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
2839 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
ba9a6214 2840
fa0f2b38 2841 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
fb3bc67e 2842 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) {
fa0f2b38
RM		 2843 delays1[0] = 0x1;
2844 delays1[5] = 0x14;
2845 }
2846
73d07a39
RM		 2847 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2848 nphy->band5g_pwrgain) {
2849 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2850 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
28fd7daa 2851 } else {
73d07a39
RM		 2852 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2853 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2854 }
28fd7daa 2855
73d07a39
RM		 2856 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2857 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
fa0f2b38
RM		 2858 if (dev->phy.rev < 3) {
2859 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2860 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2861 }
73d07a39
RM		 2862
2863 if (dev->phy.rev < 2) {
2864 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2865 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2866 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2867 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2868 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2869 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2870 }
28fd7daa 2871
73d07a39
RM		 2872 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2873 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2874 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2875 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
28fd7daa 2876
73d07a39
RM		 2877 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2878 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2879
3ccd0957 2880 b43_nphy_gain_ctl_workarounds(dev);
73d07a39
RM		 2881
2882 if (dev->phy.rev < 2) {
2883 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2884 b43_hf_write(dev, b43_hf_read(dev) |
2885 B43_HF_MLADVW);
2886 } else if (dev->phy.rev == 2) {
2887 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2888 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2889 }
28fd7daa 2890
73d07a39
RM		 2891 if (dev->phy.rev < 2)
2892 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2893 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2894
2895 /* Set phase track alpha and beta */
2896 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2897 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2898 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2899 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2900 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2901 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2902
fa0f2b38
RM		 2903 if (dev->phy.rev < 3) {
2904 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2905 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2906 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2907 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2908 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2909 }
73d07a39
RM		 2910
2911 if (dev->phy.rev == 2)
2912 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2913 B43_NPHY_FINERX2_CGC_DECGC);
2914}
28fd7daa 2915
73d07a39
RM		 2916/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2917static void b43_nphy_workarounds(struct b43_wldev *dev)
2918{
2919 struct b43_phy *phy = &dev->phy;
2920 struct b43_phy_n *nphy = phy->n;
28fd7daa 2921
73d07a39
RM		 2922 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2923 b43_nphy_classifier(dev, 1, 0);
2924 else
2925 b43_nphy_classifier(dev, 1, 1);
28fd7daa 2926
73d07a39
RM		 2927 if (nphy->hang_avoid)
2928 b43_nphy_stay_in_carrier_search(dev, 1);
2929
2930 b43_phy_set(dev, B43_NPHY_IQFLIP,
2931 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2932
d11d354b
RM		 2933 if (dev->phy.rev >= 7)
2934 b43_nphy_workarounds_rev7plus(dev);
2935 else if (dev->phy.rev >= 3)
73d07a39
RM		 2936 b43_nphy_workarounds_rev3plus(dev);
2937 else
2938 b43_nphy_workarounds_rev1_2(dev);
28fd7daa
RM		 2939
2940 if (nphy->hang_avoid)
2941 b43_nphy_stay_in_carrier_search(dev, 0);
2942}
2943
9dd4d9b9
RM		 2944/**************************************************
2945 * Tx/Rx common
2946 **************************************************/
2947
2948/*
2949 * Transmits a known value for LO calibration
2950 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2951 */
2952static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2953 bool iqmode, bool dac_test)
2954{
2955 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2956 if (samp == 0)
2957 return -1;
2958 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2959 return 0;
2960}
2961
2962/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2963static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2964{
2965 struct b43_phy_n *nphy = dev->phy.n;
2966
2967 bool override = false;
2968 u16 chain = 0x33;
2969
2970 if (nphy->txrx_chain == 0) {
2971 chain = 0x11;
2972 override = true;
2973 } else if (nphy->txrx_chain == 1) {
2974 chain = 0x22;
2975 override = true;
2976 }
2977
2978 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2979 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2980 chain);
2981
2982 if (override)
2983 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2984 B43_NPHY_RFSEQMODE_CAOVER);
2985 else
2986 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2987 ~B43_NPHY_RFSEQMODE_CAOVER);
2988}
2989
2990/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2991static void b43_nphy_stop_playback(struct b43_wldev *dev)
2992{
2993 struct b43_phy_n *nphy = dev->phy.n;
2994 u16 tmp;
2995
2996 if (nphy->hang_avoid)
2997 b43_nphy_stay_in_carrier_search(dev, 1);
2998
2999 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
3000 if (tmp & 0x1)
3001 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
3002 else if (tmp & 0x2)
3003 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
3004
3005 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
3006
3007 if (nphy->bb_mult_save & 0x80000000) {
3008 tmp = nphy->bb_mult_save & 0xFFFF;
3009 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
3010 nphy->bb_mult_save = 0;
3011 }
3012
3013 if (nphy->hang_avoid)
3014 b43_nphy_stay_in_carrier_search(dev, 0);
3015}
3016
3017/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
3018static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
3019 struct nphy_txgains target,
3020 struct nphy_iqcal_params *params)
3021{
3022 int i, j, indx;
3023 u16 gain;
3024
3025 if (dev->phy.rev >= 3) {
3026 params->txgm = target.txgm[core];
3027 params->pga = target.pga[core];
3028 params->pad = target.pad[core];
3029 params->ipa = target.ipa[core];
3030 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
3031 (params->pad << 4) | (params->ipa);
3032 for (j = 0; j < 5; j++)
3033 params->ncorr[j] = 0x79;
3034 } else {
3035 gain = (target.pad[core]) | (target.pga[core] << 4) |
3036 (target.txgm[core] << 8);
3037
3038 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
3039 1 : 0;
3040 for (i = 0; i < 9; i++)
3041 if (tbl_iqcal_gainparams[indx][i][0] == gain)
3042 break;
3043 i = min(i, 8);
3044
3045 params->txgm = tbl_iqcal_gainparams[indx][i][1];
3046 params->pga = tbl_iqcal_gainparams[indx][i][2];
3047 params->pad = tbl_iqcal_gainparams[indx][i][3];
3048 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
3049 (params->pad << 2);
3050 for (j = 0; j < 4; j++)
3051 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
3052 }
3053}
3054
884a5228 3055/**************************************************
104cfa88 3056 * Tx and Rx
884a5228 3057 **************************************************/
5f6393ec 3058
884a5228
RM		 3059static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
3060{//TODO
3061}
59af099b 3062
884a5228
RM		 3063static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
3064 bool ignore_tssi)
3065{//TODO
3066 return B43_TXPWR_RES_DONE;
3067}
59af099b 3068
161d540c
RM		 3069/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
3070static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3071{
3072 struct b43_phy_n *nphy = dev->phy.n;
3073 u8 i;
c9c0d9ec
RM		 3074 u16 bmask, val, tmp;
3075 enum ieee80211_band band = b43_current_band(dev->wl);
59af099b 3076
161d540c
RM		 3077 if (nphy->hang_avoid)
3078 b43_nphy_stay_in_carrier_search(dev, 1);
59af099b 3079
161d540c
RM		 3080 nphy->txpwrctrl = enable;
3081 if (!enable) {
c9c0d9ec
RM		 3082 if (dev->phy.rev >= 3 &&
3083 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
3084 (B43_NPHY_TXPCTL_CMD_COEFF |
3085 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
3086 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
3087 /* We disable enabled TX pwr ctl, save it's state */
3088 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
3089 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
3090 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
3091 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
3092 }
59af099b 3093
161d540c
RM		 3094 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
3095 for (i = 0; i < 84; i++)
3096 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3097
161d540c
RM		 3098 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
3099 for (i = 0; i < 84; i++)
3100 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
59af099b 3101
161d540c
RM		 3102 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3103 if (dev->phy.rev >= 3)
3104 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3105 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
59af099b 3106
161d540c
RM		 3107 if (dev->phy.rev >= 3) {
3108 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3109 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3110 } else {
3111 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3112 }
10a79873 3113
161d540c
RM		 3114 if (dev->phy.rev == 2)
3115 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3116 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
3117 else if (dev->phy.rev < 2)
3118 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3119 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
10a79873 3120
c9c0d9ec
RM		 3121 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3122 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
161d540c 3123 } else {
c9c0d9ec
RM		 3124 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
3125 nphy->adj_pwr_tbl);
3126 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
3127 nphy->adj_pwr_tbl);
10a79873 3128
c9c0d9ec
RM		 3129 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
3130 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3131 /* wl does useless check for "enable" param here */
3132 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
3133 if (dev->phy.rev >= 3) {
3134 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3135 if (val)
3136 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
3137 }
3138 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
10a79873 3139
c9c0d9ec
RM		 3140 if (band == IEEE80211_BAND_5GHZ) {
3141 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3142 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
3143 if (dev->phy.rev > 1)
3144 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3145 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
3146 0x64);
3147 }
10a79873 3148
c9c0d9ec
RM		 3149 if (dev->phy.rev >= 3) {
3150 if (nphy->tx_pwr_idx[0] != 128 &&
3151 nphy->tx_pwr_idx[1] != 128) {
3152 /* Recover TX pwr ctl state */
3153 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3154 ~B43_NPHY_TXPCTL_CMD_INIT,
3155 nphy->tx_pwr_idx[0]);
3156 if (dev->phy.rev > 1)
3157 b43_phy_maskset(dev,
3158 B43_NPHY_TXPCTL_INIT,
3159 ~0xff, nphy->tx_pwr_idx[1]);
3160 }
3161 }
10a79873 3162
c9c0d9ec
RM		 3163 if (dev->phy.rev >= 3) {
3164 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
3165 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
3166 } else {
3167 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
3168 }
10a79873 3169
c9c0d9ec
RM		 3170 if (dev->phy.rev == 2)
3171 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
3172 else if (dev->phy.rev < 2)
3173 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
10a79873 3174
c9c0d9ec
RM		 3175 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
3176 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
10a79873 3177
c002831a 3178 if (b43_nphy_ipa(dev)) {
c9c0d9ec
RM		 3179 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
3180 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
10a79873 3181 }
10a79873 3182 }
10a79873 3183
161d540c
RM		 3184 if (nphy->hang_avoid)
3185 b43_nphy_stay_in_carrier_search(dev, 0);
59af099b
RM		 3186}
3187
161d540c 3188/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
d1591314 3189static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
6dcd9d91
RM		 3190{
3191 struct b43_phy_n *nphy = dev->phy.n;
0581483a 3192 struct ssb_sprom *sprom = dev->dev->bus_sprom;
6dcd9d91 3193
161d540c
RM		 3194 u8 txpi[2], bbmult, i;
3195 u16 tmp, radio_gain, dac_gain;
3196 u16 freq = dev->phy.channel_freq;
3197 u32 txgain;
3198 /* u32 gaintbl; rev3+ */
6dcd9d91
RM		 3199
3200 if (nphy->hang_avoid)
161d540c 3201 b43_nphy_stay_in_carrier_search(dev, 1);
6dcd9d91 3202
dd5f13b8
RM		 3203 if (dev->phy.rev >= 7) {
3204 txpi[0] = txpi[1] = 30;
3205 } else if (dev->phy.rev >= 3) {
161d540c
RM		 3206 txpi[0] = 40;
3207 txpi[1] = 40;
3208 } else if (sprom->revision < 4) {
3209 txpi[0] = 72;
3210 txpi[1] = 72;
3211 } else {
3212 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3213 txpi[0] = sprom->txpid2g[0];
3214 txpi[1] = sprom->txpid2g[1];
3215 } else if (freq >= 4900 && freq < 5100) {
3216 txpi[0] = sprom->txpid5gl[0];
3217 txpi[1] = sprom->txpid5gl[1];
3218 } else if (freq >= 5100 && freq < 5500) {
3219 txpi[0] = sprom->txpid5g[0];
3220 txpi[1] = sprom->txpid5g[1];
3221 } else if (freq >= 5500) {
3222 txpi[0] = sprom->txpid5gh[0];
3223 txpi[1] = sprom->txpid5gh[1];
3224 } else {
3225 txpi[0] = 91;
3226 txpi[1] = 91;
6dcd9d91
RM		 3227 }
3228 }
dd5f13b8 3229 if (dev->phy.rev < 7 &&
9bd28571 3230 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
dd5f13b8 3231 txpi[0] = txpi[1] = 91;
6dcd9d91 3232
161d540c
RM		 3233 /*
3234 for (i = 0; i < 2; i++) {
3235 nphy->txpwrindex[i].index_internal = txpi[i];
3236 nphy->txpwrindex[i].index_internal_save = txpi[i];
95b66bad 3237 }
161d540c 3238 */
75377b24 3239
161d540c 3240 for (i = 0; i < 2; i++) {
aeab5751
RM		 3241 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
3242
3243 if (dev->phy.rev >= 3)
161d540c 3244 radio_gain = (txgain >> 16) & 0x1FFFF;
aeab5751 3245 else
161d540c 3246 radio_gain = (txgain >> 16) & 0x1FFF;
75377b24 3247
dd5f13b8
RM		 3248 if (dev->phy.rev >= 7)
3249 dac_gain = (txgain >> 8) & 0x7;
3250 else
3251 dac_gain = (txgain >> 8) & 0x3F;
161d540c 3252 bbmult = txgain & 0xFF;
75377b24 3253
161d540c
RM		 3254 if (dev->phy.rev >= 3) {
3255 if (i == 0)
3256 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
3257 else
3258 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
3259 } else {
3260 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
3261 }
75377b24 3262
161d540c
RM		 3263 if (i == 0)
3264 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
3265 else
3266 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
75377b24 3267
44f4008b 3268 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
75377b24 3269
44f4008b 3270 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
161d540c
RM		 3271 if (i == 0)
3272 tmp = (tmp & 0x00FF) | (bbmult << 8);
3273 else
3274 tmp = (tmp & 0xFF00) | bbmult;
44f4008b 3275 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
161d540c 3276
0eff8fcd
RM		 3277 if (b43_nphy_ipa(dev)) {
3278 u32 tmp32;
3279 u16 reg = (i == 0) ?
3280 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
dd5f13b8
RM		 3281 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
3282 576 + txpi[i]));
0eff8fcd
RM		 3283 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
3284 b43_phy_set(dev, reg, 0x4);
75377b24
RM		 3285 }
3286 }
75377b24 3287
161d540c 3288 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
67cbc3ed 3289
161d540c
RM		 3290 if (nphy->hang_avoid)
3291 b43_nphy_stay_in_carrier_search(dev, 0);
d1591314 3292}
67cbc3ed 3293
3dda07b6
RM		 3294static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
3295{
3296 struct b43_phy *phy = &dev->phy;
3297
3298 u8 core;
3299 u16 r; /* routing */
3300
3301 if (phy->rev >= 7) {
3302 for (core = 0; core < 2; core++) {
3303 r = core ? 0x190 : 0x170;
3304 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3305 b43_radio_write(dev, r + 0x5, 0x5);
3306 b43_radio_write(dev, r + 0x9, 0xE);
3307 if (phy->rev != 5)
3308 b43_radio_write(dev, r + 0xA, 0);
3309 if (phy->rev != 7)
3310 b43_radio_write(dev, r + 0xB, 1);
3311 else
3312 b43_radio_write(dev, r + 0xB, 0x31);
3313 } else {
3314 b43_radio_write(dev, r + 0x5, 0x9);
3315 b43_radio_write(dev, r + 0x9, 0xC);
3316 b43_radio_write(dev, r + 0xB, 0x0);
3317 if (phy->rev != 5)
3318 b43_radio_write(dev, r + 0xA, 1);
3319 else
3320 b43_radio_write(dev, r + 0xA, 0x31);
3321 }
3322 b43_radio_write(dev, r + 0x6, 0);
3323 b43_radio_write(dev, r + 0x7, 0);
3324 b43_radio_write(dev, r + 0x8, 3);
3325 b43_radio_write(dev, r + 0xC, 0);
3326 }
3327 } else {
3328 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3329 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
3330 else
3331 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
3332 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
3333 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
3334
3335 for (core = 0; core < 2; core++) {
3336 r = core ? B2056_TX1 : B2056_TX0;
3337
3338 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
3339 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
3340 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
3341 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
3342 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
3343 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
3344 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
3345 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3346 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3347 0x5);
3348 if (phy->rev != 5)
3349 b43_radio_write(dev, r | B2056_TX_TSSIA,
3350 0x00);
3351 if (phy->rev >= 5)
3352 b43_radio_write(dev, r | B2056_TX_TSSIG,
3353 0x31);
3354 else
3355 b43_radio_write(dev, r | B2056_TX_TSSIG,
3356 0x11);
3357 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3358 0xE);
3359 } else {
3360 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
3361 0x9);
3362 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
3363 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
3364 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
3365 0xC);
3366 }
3367 }
3368 }
3369}
3370
3371/*
3372 * Stop radio and transmit known signal. Then check received signal strength to
3373 * get TSSI (Transmit Signal Strength Indicator).
3374 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
3375 */
3376static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
3377{
3378 struct b43_phy *phy = &dev->phy;
3379 struct b43_phy_n *nphy = dev->phy.n;
3380
3381 u32 tmp;
3382 s32 rssi[4] = { };
3383
3384 /* TODO: check if we can transmit */
3385
3386 if (b43_nphy_ipa(dev))
3387 b43_nphy_ipa_internal_tssi_setup(dev);
3388
3389 if (phy->rev >= 7)
78ae7532 3390 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, false, 0);
3dda07b6 3391 else if (phy->rev >= 3)
78ae7532 3392 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false);
3dda07b6
RM		 3393
3394 b43_nphy_stop_playback(dev);
3395 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
3396 udelay(20);
a3764ef7 3397 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1);
3dda07b6 3398 b43_nphy_stop_playback(dev);
a3764ef7 3399 b43_nphy_rssi_select(dev, 0, N_RSSI_W1);
3dda07b6
RM		 3400
3401 if (phy->rev >= 7)
78ae7532 3402 b43_nphy_rf_ctl_override_rev7(dev, 0x2000, 0, 3, true, 0);
3dda07b6 3403 else if (phy->rev >= 3)
78ae7532 3404 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true);
3dda07b6
RM		 3405
3406 if (phy->rev >= 3) {
3407 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
3408 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
3409 } else {
3410 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
3411 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
3412 }
3413 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
3414 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
3415}
3416
d3fd8bf7
RM		 3417/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
3418static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3419{
3420 struct b43_phy_n *nphy = dev->phy.n;
3421
3422 u8 idx, delta;
3423 u8 i, stf_mode;
3424
55757927
RM		 3425 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of
3426 * 21 groups, each containing 4 entries.
3427 *
3428 * First group has entries for CCK modulation.
3429 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM).
3430 *
3431 * Group 0 is for CCK
3432 * Groups 1..4 use BPSK (group per coding rate)
3433 * Groups 5..8 use QPSK (group per coding rate)
3434 * Groups 9..12 use 16-QAM (group per coding rate)
3435 * Groups 13..16 use 64-QAM (group per coding rate)
3436 * Groups 17..20 are unknown
3437 */
3438
d3fd8bf7
RM		 3439 for (i = 0; i < 4; i++)
3440 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
3441
3442 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
3443 delta = 0;
3444 switch (stf_mode) {
3445 case 0:
3446 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
3447 idx = 68;
3448 } else {
3449 delta = 1;
3450 idx = dev->phy.is_40mhz ? 52 : 4;
3451 }
3452 break;
3453 case 1:
3454 idx = dev->phy.is_40mhz ? 76 : 28;
3455 break;
3456 case 2:
3457 idx = dev->phy.is_40mhz ? 84 : 36;
3458 break;
3459 case 3:
3460 idx = dev->phy.is_40mhz ? 92 : 44;
3461 break;
3462 }
3463
3464 for (i = 0; i < 20; i++) {
3465 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
3466 nphy->tx_power_offset[idx];
3467 if (i == 0)
3468 idx += delta;
3469 if (i == 14)
3470 idx += 1 - delta;
3471 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
3472 i == 13)
3473 idx += 1;
3474 }
3475 }
3476}
3477
3478/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
3479static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
3480{
3481 struct b43_phy_n *nphy = dev->phy.n;
3482 struct ssb_sprom *sprom = dev->dev->bus_sprom;
3483
3484 s16 a1[2], b0[2], b1[2];
3485 u8 idle[2];
3486 s8 target[2];
3487 s32 num, den, pwr;
3488 u32 regval[64];
3489
3490 u16 freq = dev->phy.channel_freq;
3491 u16 tmp;
3492 u16 r; /* routing */
3493 u8 i, c;
3494
3495 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3496 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3497 b43_read32(dev, B43_MMIO_MACCTL);
3498 udelay(1);
3499 }
3500
3501 if (nphy->hang_avoid)
3502 b43_nphy_stay_in_carrier_search(dev, true);
3503
3504 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
3505 if (dev->phy.rev >= 3)
3506 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
3507 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
3508 else
3509 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
3510 B43_NPHY_TXPCTL_CMD_PCTLEN);
3511
3512 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3513 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3514
3515 if (sprom->revision < 4) {
3516 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
3517 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
3518 target[0] = target[1] = 52;
3519 a1[0] = a1[1] = -424;
3520 b0[0] = b0[1] = 5612;
3521 b1[0] = b1[1] = -1393;
3522 } else {
3523 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3524 for (c = 0; c < 2; c++) {
3525 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
3526 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
3527 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
3528 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
3529 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
3530 }
3531 } else if (freq >= 4900 && freq < 5100) {
3532 for (c = 0; c < 2; c++) {
3533 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3534 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
3535 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
3536 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
3537 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
3538 }
3539 } else if (freq >= 5100 && freq < 5500) {
3540 for (c = 0; c < 2; c++) {
3541 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3542 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
3543 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
3544 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
3545 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
3546 }
3547 } else if (freq >= 5500) {
3548 for (c = 0; c < 2; c++) {
3549 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
3550 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
3551 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
3552 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
3553 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
3554 }
3555 } else {
3556 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
3557 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
3558 target[0] = target[1] = 52;
3559 a1[0] = a1[1] = -424;
3560 b0[0] = b0[1] = 5612;
3561 b1[0] = b1[1] = -1393;
3562 }
3563 }
3564 /* target[0] = target[1] = nphy->tx_power_max; */
3565
3566 if (dev->phy.rev >= 3) {
3567 if (sprom->fem.ghz2.tssipos)
3568 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
3569 if (dev->phy.rev >= 7) {
3570 for (c = 0; c < 2; c++) {
3571 r = c ? 0x190 : 0x170;
3572 if (b43_nphy_ipa(dev))
3573 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
3574 }
3575 } else {
3576 if (b43_nphy_ipa(dev)) {
3577 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
3578 b43_radio_write(dev,
3579 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
3580 b43_radio_write(dev,
3581 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
3582 } else {
3583 b43_radio_write(dev,
3584 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
3585 b43_radio_write(dev,
3586 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
3587 }
3588 }
3589 }
3590
3591 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
3592 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
3593 b43_read32(dev, B43_MMIO_MACCTL);
3594 udelay(1);
3595 }
3596
3597 if (dev->phy.rev >= 7) {
3598 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3599 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
3600 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3601 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
3602 } else {
3603 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
3604 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
3605 if (dev->phy.rev > 1)
3606 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
3607 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
3608 }
3609
3610 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
3611 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
3612
3613 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
3614 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
3615 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
3616 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
3617 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
3618 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
3619 B43_NPHY_TXPCTL_ITSSI_BINF);
3620 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
3621 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
3622 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
3623
3624 for (c = 0; c < 2; c++) {
3625 for (i = 0; i < 64; i++) {
3626 num = 8 * (16 * b0[c] + b1[c] * i);
3627 den = 32768 + a1[c] * i;
3628 pwr = max((4 * num + den / 2) / den, -8);
3629 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
3630 pwr = max(pwr, target[c] + 1);
3631 regval[i] = pwr;
3632 }
3633 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
3634 }
3635
3636 b43_nphy_tx_prepare_adjusted_power_table(dev);
d3fd8bf7
RM		 3637 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
3638 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
d3fd8bf7
RM		 3639
3640 if (nphy->hang_avoid)
3641 b43_nphy_stay_in_carrier_search(dev, false);
3642}
3643
0eff8fcd
RM		 3644static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
3645{
3646 struct b43_phy *phy = &dev->phy;
67cbc3ed 3647
0eff8fcd 3648 const u32 *table = NULL;
0eff8fcd
RM		 3649 u32 rfpwr_offset;
3650 u8 pga_gain;
3651 int i;
0eff8fcd 3652
aeab5751 3653 table = b43_nphy_get_tx_gain_table(dev);
0eff8fcd
RM		 3654 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
3655 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
3656
3657 if (phy->rev >= 3) {
3658#if 0
3659 nphy->gmval = (table[0] >> 16) & 0x7000;
34c5cf20 3660#endif
0eff8fcd
RM		 3661
3662 for (i = 0; i < 128; i++) {
3663 pga_gain = (table[i] >> 24) & 0xF;
3664 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
34c5cf20
RM		 3665 rfpwr_offset =
3666 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
0eff8fcd 3667 else
34c5cf20
RM		 3668 rfpwr_offset =
3669 0; /* FIXME */
0eff8fcd
RM		 3670 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
3671 rfpwr_offset);
3672 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
3673 rfpwr_offset);
3674 }
67cbc3ed
RM		 3675 }
3676}
3677
e50cbcf6
RM		 3678/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
3679static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
95b66bad 3680{
e50cbcf6
RM		 3681 struct b43_phy_n *nphy = dev->phy.n;
3682 enum ieee80211_band band;
3683 u16 tmp;
95b66bad 3684
e50cbcf6
RM		 3685 if (!enable) {
3686 nphy->rfctrl_intc1_save = b43_phy_read(dev,
3687 B43_NPHY_RFCTL_INTC1);
3688 nphy->rfctrl_intc2_save = b43_phy_read(dev,
3689 B43_NPHY_RFCTL_INTC2);
3690 band = b43_current_band(dev->wl);
3691 if (dev->phy.rev >= 3) {
3692 if (band == IEEE80211_BAND_5GHZ)
3693 tmp = 0x600;
3694 else
3695 tmp = 0x480;
3696 } else {
3697 if (band == IEEE80211_BAND_5GHZ)
3698 tmp = 0x180;
3699 else
3700 tmp = 0x120;
3701 }
3702 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3703 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3704 } else {
3705 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
3706 nphy->rfctrl_intc1_save);
3707 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
3708 nphy->rfctrl_intc2_save);
95b66bad 3709 }
95b66bad
MB		 3710}
3711
fe3e46e8
RM		 3712/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
3713static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
3c95627d
RM		 3714{
3715 u16 tmp;
3c95627d 3716
fe3e46e8 3717 if (dev->phy.rev >= 3) {
c002831a 3718 if (b43_nphy_ipa(dev)) {
fe3e46e8
RM		 3719 tmp = 4;
3720 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
3721 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3722 }
76b002bd 3723
fe3e46e8
RM		 3724 tmp = 1;
3725 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
3726 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
3727 }
3728}
76b002bd 3729
2faa6b83
RM		 3730/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
3731static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
3732 u16 samps, u8 time, bool wait)
3c95627d 3733{
2faa6b83
RM		 3734 int i;
3735 u16 tmp;
3c95627d 3736
2faa6b83
RM		 3737 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
3738 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
3739 if (wait)
3740 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
99b82c41 3741 else
2faa6b83 3742 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
99b82c41 3743
2faa6b83 3744 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
3c95627d 3745
2faa6b83
RM		 3746 for (i = 1000; i; i--) {
3747 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
3748 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
3749 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
3750 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
3751 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
3752 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
3753 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
3754 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
3c95627d 3755
2faa6b83
RM		 3756 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
3757 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
3758 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
3759 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
3760 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
3761 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
3762 return;
3c95627d 3763 }
2faa6b83 3764 udelay(10);
3c95627d 3765 }
2faa6b83 3766 memset(est, 0, sizeof(*est));
3c95627d
RM		 3767}
3768
a67162ab
RM		 3769/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
3770static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
3771 struct b43_phy_n_iq_comp *pcomp)
99b82c41 3772{
a67162ab
RM		 3773 if (write) {
3774 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
3775 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
3776 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
3777 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
6e3b15a9 3778 } else {
a67162ab
RM		 3779 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
3780 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
3781 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
3782 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
3783 }
3784}
6e3b15a9 3785
c7455cf9
RM		 3786#if 0
3787/* Ready but not used anywhere */
026816fc
RM		 3788/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
3789static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
3790{
3791 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3792
026816fc
RM		 3793 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
3794 if (core == 0) {
3795 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
3796 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3797 } else {
3798 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3799 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3800 }
3801 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
3802 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
3803 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
3804 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
3805 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
3806 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
3807 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3808 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3809}
6e3b15a9 3810
026816fc
RM		 3811/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
3812static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
3813{
3814 u8 rxval, txval;
3815 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
6e3b15a9 3816
026816fc
RM		 3817 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
3818 if (core == 0) {
3819 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3820 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3821 } else {
3822 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3823 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3824 }
3825 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3826 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3827 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
3828 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
3829 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
3830 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
3831 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3832 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
6e3b15a9 3833
026816fc
RM		 3834 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3835 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
6e3b15a9 3836
acd82aa8
LF		 3837 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
3838 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
026816fc
RM		 3839 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
3840 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
3841 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
3842 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3843 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
3844 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
3845 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
6e3b15a9 3846
026816fc
RM		 3847 if (core == 0) {
3848 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
3849 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
3850 } else {
3851 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
3852 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
3853 }
6e3b15a9 3854
89e43dad 3855 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3);
78ae7532 3856 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false);
67c0d6e2 3857 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
6e3b15a9 3858
026816fc
RM		 3859 if (core == 0) {
3860 rxval = 1;
3861 txval = 8;
3862 } else {
3863 rxval = 4;
3864 txval = 2;
6e3b15a9 3865 }
89e43dad
RM		 3866 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval,
3867 core + 1);
3868 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval,
3869 2 - core);
99b82c41 3870}
c7455cf9 3871#endif
99b82c41 3872
34a56f2c
RM		 3873/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3874static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
dfb4aa5d
RM		 3875{
3876 int i;
34a56f2c
RM		 3877 s32 iq;
3878 u32 ii;
3879 u32 qq;
3880 int iq_nbits, qq_nbits;
3881 int arsh, brsh;
3882 u16 tmp, a, b;
3883
3884 struct nphy_iq_est est;
3885 struct b43_phy_n_iq_comp old;
3886 struct b43_phy_n_iq_comp new = { };
3887 bool error = false;
3888
3889 if (mask == 0)
3890 return;
3891
3892 b43_nphy_rx_iq_coeffs(dev, false, &old);
3893 b43_nphy_rx_iq_coeffs(dev, true, &new);
3894 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3895 new = old;
3896
dfb4aa5d 3897 for (i = 0; i < 2; i++) {
34a56f2c
RM		 3898 if (i == 0 && (mask & 1)) {
3899 iq = est.iq0_prod;
3900 ii = est.i0_pwr;
3901 qq = est.q0_pwr;
3902 } else if (i == 1 && (mask & 2)) {
3903 iq = est.iq1_prod;
3904 ii = est.i1_pwr;
3905 qq = est.q1_pwr;
dfb4aa5d 3906 } else {
34a56f2c 3907 continue;
dfb4aa5d 3908 }
dfb4aa5d 3909
34a56f2c
RM		 3910 if (ii + qq < 2) {
3911 error = true;
3912 break;
3913 }
dfb4aa5d 3914
34a56f2c
RM		 3915 iq_nbits = fls(abs(iq));
3916 qq_nbits = fls(qq);
dfb4aa5d 3917
34a56f2c
RM		 3918 arsh = iq_nbits - 20;
3919 if (arsh >= 0) {
3920 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3921 tmp = ii >> arsh;
3922 } else {
3923 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3924 tmp = ii << -arsh;
3925 }
3926 if (tmp == 0) {
3927 error = true;
3928 break;
3929 }
3930 a /= tmp;
dfb4aa5d 3931
34a56f2c
RM		 3932 brsh = qq_nbits - 11;
3933 if (brsh >= 0) {
3934 b = (qq << (31 - qq_nbits));
3935 tmp = ii >> brsh;
dfb4aa5d 3936 } else {
34a56f2c
RM		 3937 b = (qq << (31 - qq_nbits));
3938 tmp = ii << -brsh;
3939 }
3940 if (tmp == 0) {
3941 error = true;
3942 break;
dfb4aa5d 3943 }
34a56f2c 3944 b = int_sqrt(b / tmp - a * a) - (1 << 10);
dfb4aa5d 3945
34a56f2c
RM		 3946 if (i == 0 && (mask & 0x1)) {
3947 if (dev->phy.rev >= 3) {
3948 new.a0 = a & 0x3FF;
3949 new.b0 = b & 0x3FF;
3950 } else {
3951 new.a0 = b & 0x3FF;
3952 new.b0 = a & 0x3FF;
3953 }
3954 } else if (i == 1 && (mask & 0x2)) {
3955 if (dev->phy.rev >= 3) {
3956 new.a1 = a & 0x3FF;
3957 new.b1 = b & 0x3FF;
3958 } else {
3959 new.a1 = b & 0x3FF;
3960 new.b1 = a & 0x3FF;
3961 }
3962 }
dfb4aa5d 3963 }
dfb4aa5d 3964
34a56f2c
RM		 3965 if (error)
3966 new = old;
dfb4aa5d 3967
34a56f2c
RM		 3968 b43_nphy_rx_iq_coeffs(dev, true, &new);
3969}
dfb4aa5d 3970
09146400
RM		 3971/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3972static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3973{
3974 u16 array[4];
44f4008b 3975 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
09146400
RM		 3976
3977 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3978 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3979 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3980 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
dfb4aa5d
RM		 3981}
3982
9442e5b5
RM		 3983/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3984static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3985{
3986 struct b43_phy_n *nphy = dev->phy.n;
90b9738d 3987
204a665b 3988 u8 channel = dev->phy.channel;
9442e5b5
RM		 3989 int tone[2] = { 57, 58 };
3990 u32 noise[2] = { 0x3FF, 0x3FF };
90b9738d 3991
9442e5b5 3992 B43_WARN_ON(dev->phy.rev < 3);
90b9738d 3993
9442e5b5
RM		 3994 if (nphy->hang_avoid)
3995 b43_nphy_stay_in_carrier_search(dev, 1);
90b9738d 3996
9442e5b5
RM		 3997 if (nphy->gband_spurwar_en) {
3998 /* TODO: N PHY Adjust Analog Pfbw (7) */
3999 if (channel == 11 && dev->phy.is_40mhz)
4000 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4001 else
4002 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4003 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
90b9738d
RM		 4004 }
4005
9442e5b5
RM		 4006 if (nphy->aband_spurwar_en) {
4007 if (channel == 54) {
4008 tone[0] = 0x20;
4009 noise[0] = 0x25F;
4010 } else if (channel == 38 || channel == 102 || channel == 118) {
4011 if (0 /* FIXME */) {
4012 tone[0] = 0x20;
4013 noise[0] = 0x21F;
4014 } else {
4015 tone[0] = 0;
4016 noise[0] = 0;
90b9738d 4017 }
9442e5b5
RM		 4018 } else if (channel == 134) {
4019 tone[0] = 0x20;
4020 noise[0] = 0x21F;
4021 } else if (channel == 151) {
4022 tone[0] = 0x10;
4023 noise[0] = 0x23F;
4024 } else if (channel == 153 || channel == 161) {
4025 tone[0] = 0x30;
4026 noise[0] = 0x23F;
4027 } else {
4028 tone[0] = 0;
4029 noise[0] = 0;
90b9738d 4030 }
90b9738d 4031
9442e5b5
RM		 4032 if (!tone[0] && !noise[0])
4033 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
90b9738d 4034 else
9442e5b5
RM		 4035 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
4036 }
90b9738d 4037
9442e5b5
RM		 4038 if (nphy->hang_avoid)
4039 b43_nphy_stay_in_carrier_search(dev, 0);
4040}
90b9738d 4041
5ecab603
RM		 4042/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
4043static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
4044{
4045 struct b43_phy_n *nphy = dev->phy.n;
4046 int i, j;
4047 u32 tmp;
4048 u32 cur_real, cur_imag, real_part, imag_part;
90b9738d 4049
5ecab603 4050 u16 buffer[7];
90b9738d 4051
5ecab603
RM		 4052 if (nphy->hang_avoid)
4053 b43_nphy_stay_in_carrier_search(dev, true);
90b9738d 4054
5ecab603 4055 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
90b9738d 4056
5ecab603
RM		 4057 for (i = 0; i < 2; i++) {
4058 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
4059 (buffer[i * 2 + 1] & 0x3FF);
4060 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4061 (((i + 26) << 10) | 320));
4062 for (j = 0; j < 128; j++) {
4063 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4064 ((tmp >> 16) & 0xFFFF));
4065 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4066 (tmp & 0xFFFF));
90b9738d 4067 }
90b9738d 4068 }
90b9738d 4069
5ecab603
RM		 4070 for (i = 0; i < 2; i++) {
4071 tmp = buffer[5 + i];
4072 real_part = (tmp >> 8) & 0xFF;
4073 imag_part = (tmp & 0xFF);
4074 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
4075 (((i + 26) << 10) | 448));
90b9738d 4076
5ecab603
RM		 4077 if (dev->phy.rev >= 3) {
4078 cur_real = real_part;
4079 cur_imag = imag_part;
4080 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
4081 }
4cb99775 4082
5ecab603
RM		 4083 for (j = 0; j < 128; j++) {
4084 if (dev->phy.rev < 3) {
4085 cur_real = (real_part * loscale[j] + 128) >> 8;
4086 cur_imag = (imag_part * loscale[j] + 128) >> 8;
4087 tmp = ((cur_real & 0xFF) << 8) |
4088 (cur_imag & 0xFF);
4089 }
4090 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
4091 ((tmp >> 16) & 0xFFFF));
4092 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
4093 (tmp & 0xFFFF));
4094 }
90b9738d 4095 }
4cb99775 4096
4cb99775 4097 if (dev->phy.rev >= 3) {
5ecab603
RM		 4098 b43_shm_write16(dev, B43_SHM_SHARED,
4099 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
4100 b43_shm_write16(dev, B43_SHM_SHARED,
4101 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
4cb99775 4102 }
90b9738d 4103
5ecab603
RM		 4104 if (nphy->hang_avoid)
4105 b43_nphy_stay_in_carrier_search(dev, false);
95b66bad
MB		 4106}
4107
42e1547e
RM		 4108/*
4109 * Restore RSSI Calibration
4110 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
4111 */
4112static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
4113{
4114 struct b43_phy_n *nphy = dev->phy.n;
4115
4116 u16 *rssical_radio_regs = NULL;
4117 u16 *rssical_phy_regs = NULL;
4118
4119 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4120 if (!nphy->rssical_chanspec_2G.center_freq)
42e1547e
RM		 4121 return;
4122 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
4123 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
4124 } else {
204a665b 4125 if (!nphy->rssical_chanspec_5G.center_freq)
42e1547e
RM		 4126 return;
4127 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
4128 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
4129 }
4130
9a98979e
RM		 4131 if (dev->phy.rev >= 7) {
4132 } else {
4133 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3,
4134 rssical_radio_regs[0]);
4135 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3,
4136 rssical_radio_regs[1]);
4137 }
42e1547e
RM		 4138
4139 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
4140 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
4141 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
4142 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
4143
4144 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
4145 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
4146 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
4147 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
4148
4149 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
4150 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
4151 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
4152 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
4153}
4154
c4a92003
RM		 4155/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
4156static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
4157{
4158 struct b43_phy_n *nphy = dev->phy.n;
4159 u16 *save = nphy->tx_rx_cal_radio_saveregs;
52cb5e97
RM		 4160 u16 tmp;
4161 u8 offset, i;
c4a92003
RM		 4162
4163 if (dev->phy.rev >= 3) {
52cb5e97
RM		 4164 for (i = 0; i < 2; i++) {
4165 tmp = (i == 0) ? 0x2000 : 0x3000;
4166 offset = i * 11;
4167
0c201cfb
RM		 4168 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
4169 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
4170 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
4171 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
4172 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
4173 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
4174 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
4175 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
4176 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
4177 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
4178 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
52cb5e97
RM		 4179
4180 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
0c201cfb
RM		 4181 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
4182 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4183 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4184 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4185 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
52cb5e97 4186 if (nphy->ipa5g_on) {
0c201cfb
RM		 4187 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
4188 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
52cb5e97 4189 } else {
0c201cfb
RM		 4190 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4191 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
52cb5e97 4192 }
0c201cfb 4193 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97 4194 } else {
0c201cfb
RM		 4195 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
4196 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
4197 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
4198 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
4199 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
4200 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
52cb5e97 4201 if (nphy->ipa2g_on) {
0c201cfb
RM		 4202 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
4203 b43_radio_write(dev, tmp | B2055_XOCTL2,
52cb5e97
RM		 4204 (dev->phy.rev < 5) ? 0x11 : 0x01);
4205 } else {
0c201cfb
RM		 4206 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
4207 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
52cb5e97
RM		 4208 }
4209 }
0c201cfb
RM		 4210 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
4211 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
4212 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
52cb5e97 4213 }
c4a92003 4214 } else {
0c201cfb
RM		 4215 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
4216 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
c4a92003 4217
0c201cfb
RM		 4218 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
4219 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
c4a92003 4220
0c201cfb
RM		 4221 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
4222 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
c4a92003 4223
0c201cfb
RM		 4224 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4225 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
c4a92003 4226
0c201cfb
RM		 4227 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4228 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
c4a92003
RM		 4229
4230 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4231 B43_NPHY_BANDCTL_5GHZ)) {
0c201cfb
RM		 4232 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4233 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
c4a92003 4234 } else {
0c201cfb
RM		 4235 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4236 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
c4a92003
RM		 4237 }
4238
4239 if (dev->phy.rev < 2) {
4240 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
4241 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
4242 } else {
4243 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
4244 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
4245 }
4246 }
4247}
4248
de7ed0c6
RM		 4249/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
4250static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
4251{
4252 struct b43_phy_n *nphy = dev->phy.n;
4253 int i;
4254 u16 scale, entry;
4255
4256 u16 tmp = nphy->txcal_bbmult;
4257 if (core == 0)
4258 tmp >>= 8;
4259 tmp &= 0xff;
4260
4261 for (i = 0; i < 18; i++) {
4262 scale = (ladder_lo[i].percent * tmp) / 100;
4263 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
d41a3552 4264 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
de7ed0c6
RM		 4265
4266 scale = (ladder_iq[i].percent * tmp) / 100;
4267 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
d41a3552 4268 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
de7ed0c6
RM		 4269 }
4270}
4271
45ca697e
RM		 4272/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
4273static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
4274{
4275 int i;
4276 for (i = 0; i < 15; i++)
4277 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
4278 tbl_tx_filter_coef_rev4[2][i]);
4279}
4280
4281/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
4282static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4283{
4284 int i, j;
4285 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
20407ed8 4286 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
45ca697e
RM		 4287
4288 for (i = 0; i < 3; i++)
4289 for (j = 0; j < 15; j++)
4290 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4291 tbl_tx_filter_coef_rev4[i][j]);
4292
4293 if (dev->phy.is_40mhz) {
4294 for (j = 0; j < 15; j++)
4295 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4296 tbl_tx_filter_coef_rev4[3][j]);
4297 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
4298 for (j = 0; j < 15; j++)
4299 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4300 tbl_tx_filter_coef_rev4[5][j]);
4301 }
4302
4303 if (dev->phy.channel == 14)
4304 for (j = 0; j < 15; j++)
4305 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4306 tbl_tx_filter_coef_rev4[6][j]);
4307}
4308
b0022e15
RM		 4309/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
4310static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
4311{
4312 struct b43_phy_n *nphy = dev->phy.n;
4313
4314 u16 curr_gain[2];
4315 struct nphy_txgains target;
4316 const u32 *table = NULL;
4317
161d540c 4318 if (!nphy->txpwrctrl) {
b0022e15
RM		 4319 int i;
4320
4321 if (nphy->hang_avoid)
4322 b43_nphy_stay_in_carrier_search(dev, true);
9145834e 4323 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
b0022e15
RM		 4324 if (nphy->hang_avoid)
4325 b43_nphy_stay_in_carrier_search(dev, false);
4326
4327 for (i = 0; i < 2; ++i) {
4328 if (dev->phy.rev >= 3) {
4329 target.ipa[i] = curr_gain[i] & 0x000F;
4330 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
4331 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
4332 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
4333 } else {
4334 target.ipa[i] = curr_gain[i] & 0x0003;
4335 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
4336 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
4337 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
4338 }
4339 }
4340 } else {
4341 int i;
4342 u16 index[2];
4343 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
4344 B43_NPHY_TXPCTL_STAT_BIDX) >>
4345 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4346 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
4347 B43_NPHY_TXPCTL_STAT_BIDX) >>
4348 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
4349
4350 for (i = 0; i < 2; ++i) {
aeab5751 4351 table = b43_nphy_get_tx_gain_table(dev);
b0022e15 4352 if (dev->phy.rev >= 3) {
b0022e15
RM		 4353 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
4354 target.pad[i] = (table[index[i]] >> 20) & 0xF;
4355 target.pga[i] = (table[index[i]] >> 24) & 0xF;
4356 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
4357 } else {
b0022e15
RM		 4358 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
4359 target.pad[i] = (table[index[i]] >> 18) & 0x3;
4360 target.pga[i] = (table[index[i]] >> 20) & 0x7;
4361 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
4362 }
4363 }
4364 }
4365
4366 return target;
4367}
4368
e53de674
RM		 4369/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
4370static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
4371{
4372 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4373
4374 if (dev->phy.rev >= 3) {
4375 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
4376 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
4377 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
4378 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
4379 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
d41a3552
RM		 4380 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
4381 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
e53de674
RM		 4382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
4383 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
4384 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
4385 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
4386 b43_nphy_reset_cca(dev);
4387 } else {
4388 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
4389 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
4390 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
d41a3552
RM		 4391 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
4392 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
e53de674
RM		 4393 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
4394 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
4395 }
4396}
4397
4398/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
4399static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
4400{
4401 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
4402 u16 tmp;
4403
4404 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
4405 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
4406 if (dev->phy.rev >= 3) {
4407 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
4408 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
4409
4410 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
4411 regs[2] = tmp;
4412 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
4413
4414 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4415 regs[3] = tmp;
4416 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
4417
4418 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
acd82aa8
LF		 4419 b43_phy_mask(dev, B43_NPHY_BBCFG,
4420 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
e53de674 4421
c643a66e 4422 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
e53de674 4423 regs[5] = tmp;
d41a3552 4424 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
c643a66e
RM		 4425
4426 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
e53de674 4427 regs[6] = tmp;
d41a3552 4428 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
e53de674
RM		 4429 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4430 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4431
89e43dad
RM		 4432 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 1, 3);
4433 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1);
4434 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2);
e53de674
RM		 4435
4436 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
4437 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
4438 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
4439 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
4440 } else {
4441 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
4442 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
4443 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4444 regs[2] = tmp;
4445 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
c643a66e 4446 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
e53de674
RM		 4447 regs[3] = tmp;
4448 tmp |= 0x2000;
d41a3552 4449 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
c643a66e 4450 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
e53de674
RM		 4451 regs[4] = tmp;
4452 tmp |= 0x2000;
d41a3552 4453 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
e53de674
RM		 4454 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
4455 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
4456 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
4457 tmp = 0x0180;
4458 else
4459 tmp = 0x0120;
4460 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
4461 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
4462 }
4463}
4464
bbc6dc12
RM		 4465/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
4466static void b43_nphy_save_cal(struct b43_wldev *dev)
4467{
4468 struct b43_phy_n *nphy = dev->phy.n;
4469
4470 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4471 u16 *txcal_radio_regs = NULL;
902db91d 4472 struct b43_chanspec *iqcal_chanspec;
bbc6dc12
RM		 4473 u16 *table = NULL;
4474
4475 if (nphy->hang_avoid)
4476 b43_nphy_stay_in_carrier_search(dev, 1);
4477
4478 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4479 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4480 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4481 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
4482 table = nphy->cal_cache.txcal_coeffs_2G;
4483 } else {
4484 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4485 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4486 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
4487 table = nphy->cal_cache.txcal_coeffs_5G;
4488 }
4489
4490 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
4491 /* TODO use some definitions */
4492 if (dev->phy.rev >= 3) {
4493 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
4494 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
4495 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
4496 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
4497 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
4498 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
4499 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
4500 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
4501 } else {
4502 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
4503 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
4504 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
4505 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
4506 }
204a665b
RM		 4507 iqcal_chanspec->center_freq = dev->phy.channel_freq;
4508 iqcal_chanspec->channel_type = dev->phy.channel_type;
5818e989 4509 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
bbc6dc12
RM		 4510
4511 if (nphy->hang_avoid)
4512 b43_nphy_stay_in_carrier_search(dev, 0);
4513}
4514
2f258b74
RM		 4515/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
4516static void b43_nphy_restore_cal(struct b43_wldev *dev)
4517{
4518 struct b43_phy_n *nphy = dev->phy.n;
4519
4520 u16 coef[4];
4521 u16 *loft = NULL;
4522 u16 *table = NULL;
4523
4524 int i;
4525 u16 *txcal_radio_regs = NULL;
4526 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
4527
4528 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
204a665b 4529 if (!nphy->iqcal_chanspec_2G.center_freq)
2f258b74
RM		 4530 return;
4531 table = nphy->cal_cache.txcal_coeffs_2G;
4532 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
4533 } else {
204a665b 4534 if (!nphy->iqcal_chanspec_5G.center_freq)
2f258b74
RM		 4535 return;
4536 table = nphy->cal_cache.txcal_coeffs_5G;
4537 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
4538 }
4539
2581b143 4540 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2f258b74
RM		 4541
4542 for (i = 0; i < 4; i++) {
4543 if (dev->phy.rev >= 3)
4544 table[i] = coef[i];
4545 else
4546 coef[i] = 0;
4547 }
4548
2581b143
RM		 4549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
4550 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
4551 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2f258b74
RM		 4552
4553 if (dev->phy.rev < 2)
4554 b43_nphy_tx_iq_workaround(dev);
4555
4556 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4557 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
4558 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
4559 } else {
4560 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
4561 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
4562 }
4563
4564 /* TODO use some definitions */
4565 if (dev->phy.rev >= 3) {
4566 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
4567 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
4568 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
4569 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
4570 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
4571 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
4572 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
4573 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
4574 } else {
4575 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
4576 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
4577 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
4578 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
4579 }
4580 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
4581}
4582
fb43b8e2
RM		 4583/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
4584static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4585 struct nphy_txgains target,
4586 bool full, bool mphase)
4587{
4588 struct b43_phy_n *nphy = dev->phy.n;
4589 int i;
4590 int error = 0;
4591 int freq;
4592 bool avoid = false;
4593 u8 length;
fb23d863 4594 u16 tmp, core, type, count, max, numb, last = 0, cmd;
fb43b8e2
RM		 4595 const u16 *table;
4596 bool phy6or5x;
4597
4598 u16 buffer[11];
4599 u16 diq_start = 0;
4600 u16 save[2];
4601 u16 gain[2];
4602 struct nphy_iqcal_params params[2];
4603 bool updated[2] = { };
4604
4605 b43_nphy_stay_in_carrier_search(dev, true);
4606
4607 if (dev->phy.rev >= 4) {
4608 avoid = nphy->hang_avoid;
3db1cd5c 4609 nphy->hang_avoid = false;
fb43b8e2
RM		 4610 }
4611
9145834e 4612 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4613
4614 for (i = 0; i < 2; i++) {
4615 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
4616 gain[i] = params[i].cal_gain;
4617 }
2581b143
RM		 4618
4619 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
fb43b8e2
RM		 4620
4621 b43_nphy_tx_cal_radio_setup(dev);
e53de674 4622 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 4623
4624 phy6or5x = dev->phy.rev >= 6 ||
4625 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4626 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4627 if (phy6or5x) {
38bb9029
RM		 4628 if (dev->phy.is_40mhz) {
4629 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4630 tbl_tx_iqlo_cal_loft_ladder_40);
4631 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4632 tbl_tx_iqlo_cal_iqimb_ladder_40);
4633 } else {
4634 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4635 tbl_tx_iqlo_cal_loft_ladder_20);
4636 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
4637 tbl_tx_iqlo_cal_iqimb_ladder_20);
4638 }
fb43b8e2
RM		 4639 }
4640
4641 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4642
aa4c7b2a 4643 if (!dev->phy.is_40mhz)
fb43b8e2
RM		 4644 freq = 2500;
4645 else
4646 freq = 5000;
4647
4648 if (nphy->mphase_cal_phase_id > 2)
10a79873
RM		 4649 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
4650 0xFFFF, 0, true, false);
fb43b8e2 4651 else
59af099b 4652 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
fb43b8e2
RM		 4653
4654 if (error == 0) {
4655 if (nphy->mphase_cal_phase_id > 2) {
4656 table = nphy->mphase_txcal_bestcoeffs;
4657 length = 11;
4658 if (dev->phy.rev < 3)
4659 length -= 2;
4660 } else {
4661 if (!full && nphy->txiqlocal_coeffsvalid) {
4662 table = nphy->txiqlocal_bestc;
4663 length = 11;
4664 if (dev->phy.rev < 3)
4665 length -= 2;
4666 } else {
4667 full = true;
4668 if (dev->phy.rev >= 3) {
4669 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
4670 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
4671 } else {
4672 table = tbl_tx_iqlo_cal_startcoefs;
4673 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
4674 }
4675 }
4676 }
4677
2581b143 4678 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
fb43b8e2
RM		 4679
4680 if (full) {
4681 if (dev->phy.rev >= 3)
4682 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
4683 else
4684 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
4685 } else {
4686 if (dev->phy.rev >= 3)
4687 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
4688 else
4689 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
4690 }
4691
4692 if (mphase) {
4693 count = nphy->mphase_txcal_cmdidx;
4694 numb = min(max,
4695 (u16)(count + nphy->mphase_txcal_numcmds));
4696 } else {
4697 count = 0;
4698 numb = max;
4699 }
4700
4701 for (; count < numb; count++) {
4702 if (full) {
4703 if (dev->phy.rev >= 3)
4704 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
4705 else
4706 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
4707 } else {
4708 if (dev->phy.rev >= 3)
4709 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
4710 else
4711 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
4712 }
4713
4714 core = (cmd & 0x3000) >> 12;
4715 type = (cmd & 0x0F00) >> 8;
4716
4717 if (phy6or5x && updated[core] == 0) {
4718 b43_nphy_update_tx_cal_ladder(dev, core);
3db1cd5c 4719 updated[core] = true;
fb43b8e2
RM		 4720 }
4721
4722 tmp = (params[core].ncorr[type] << 8) | 0x66;
4723 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
4724
4725 if (type == 1 || type == 3 || type == 4) {
c643a66e
RM		 4726 buffer[0] = b43_ntab_read(dev,
4727 B43_NTAB16(15, 69 + core));
fb43b8e2
RM		 4728 diq_start = buffer[0];
4729 buffer[0] = 0;
d41a3552
RM		 4730 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
4731 0);
fb43b8e2
RM		 4732 }
4733
4734 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
4735 for (i = 0; i < 2000; i++) {
4736 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
4737 if (tmp & 0xC000)
4738 break;
4739 udelay(10);
4740 }
4741
9145834e
RM		 4742 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4743 buffer);
2581b143
RM		 4744 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
4745 buffer);
fb43b8e2
RM		 4746
4747 if (type == 1 || type == 3 || type == 4)
4748 buffer[0] = diq_start;
4749 }
4750
4751 if (mphase)
4752 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
4753
4754 last = (dev->phy.rev < 3) ? 6 : 7;
4755
4756 if (!mphase || nphy->mphase_cal_phase_id == last) {
2581b143 4757 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
9145834e 4758 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
fb43b8e2
RM		 4759 if (dev->phy.rev < 3) {
4760 buffer[0] = 0;
4761 buffer[1] = 0;
4762 buffer[2] = 0;
4763 buffer[3] = 0;
4764 }
2581b143
RM		 4765 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4766 buffer);
bc53e512 4767 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2581b143
RM		 4768 buffer);
4769 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4770 buffer);
4771 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4772 buffer);
fb43b8e2
RM		 4773 length = 11;
4774 if (dev->phy.rev < 3)
4775 length -= 2;
9145834e
RM		 4776 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4777 nphy->txiqlocal_bestc);
fb43b8e2 4778 nphy->txiqlocal_coeffsvalid = true;
204a665b
RM		 4779 nphy->txiqlocal_chanspec.center_freq =
4780 dev->phy.channel_freq;
4781 nphy->txiqlocal_chanspec.channel_type =
4782 dev->phy.channel_type;
fb43b8e2
RM		 4783 } else {
4784 length = 11;
4785 if (dev->phy.rev < 3)
4786 length -= 2;
9145834e
RM		 4787 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
4788 nphy->mphase_txcal_bestcoeffs);
fb43b8e2
RM		 4789 }
4790
53ae8e8c 4791 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 4792 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
4793 }
4794
e53de674 4795 b43_nphy_tx_cal_phy_cleanup(dev);
2581b143 4796 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
fb43b8e2
RM		 4797
4798 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
4799 b43_nphy_tx_iq_workaround(dev);
4800
4801 if (dev->phy.rev >= 4)
4802 nphy->hang_avoid = avoid;
4803
4804 b43_nphy_stay_in_carrier_search(dev, false);
4805
4806 return error;
4807}
4808
984ff4ff
RM		 4809/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
4810static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
4811{
4812 struct b43_phy_n *nphy = dev->phy.n;
4813 u8 i;
4814 u16 buffer[7];
4815 bool equal = true;
4816
902db91d 4817 if (!nphy->txiqlocal_coeffsvalid ||
204a665b
RM		 4818 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
4819 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
984ff4ff
RM		 4820 return;
4821
4822 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
4823 for (i = 0; i < 4; i++) {
4824 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
4825 equal = false;
4826 break;
4827 }
4828 }
4829
4830 if (!equal) {
4831 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
4832 nphy->txiqlocal_bestc);
4833 for (i = 0; i < 4; i++)
4834 buffer[i] = 0;
4835 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
4836 buffer);
4837 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
4838 &nphy->txiqlocal_bestc[5]);
4839 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
4840 &nphy->txiqlocal_bestc[5]);
4841 }
4842}
4843
15931e31
RM		 4844/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
4845static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
4846 struct nphy_txgains target, u8 type, bool debug)
4847{
4848 struct b43_phy_n *nphy = dev->phy.n;
4849 int i, j, index;
4850 u8 rfctl[2];
4851 u8 afectl_core;
4852 u16 tmp[6];
c7455cf9 4853 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
15931e31
RM		 4854 u32 real, imag;
4855 enum ieee80211_band band;
4856
4857 u8 use;
4858 u16 cur_hpf;
4859 u16 lna[3] = { 3, 3, 1 };
4860 u16 hpf1[3] = { 7, 2, 0 };
4861 u16 hpf2[3] = { 2, 0, 0 };
de9a47f9 4862 u32 power[3] = { };
15931e31
RM		 4863 u16 gain_save[2];
4864 u16 cal_gain[2];
4865 struct nphy_iqcal_params cal_params[2];
4866 struct nphy_iq_est est;
4867 int ret = 0;
4868 bool playtone = true;
4869 int desired = 13;
4870
4871 b43_nphy_stay_in_carrier_search(dev, 1);
4872
4873 if (dev->phy.rev < 2)
984ff4ff 4874 b43_nphy_reapply_tx_cal_coeffs(dev);
9145834e 4875 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 4876 for (i = 0; i < 2; i++) {
4877 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4878 cal_gain[i] = cal_params[i].cal_gain;
4879 }
2581b143 4880 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
15931e31
RM		 4881
4882 for (i = 0; i < 2; i++) {
4883 if (i == 0) {
4884 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4885 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4886 afectl_core = B43_NPHY_AFECTL_C1;
4887 } else {
4888 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4889 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4890 afectl_core = B43_NPHY_AFECTL_C2;
4891 }
4892
4893 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4894 tmp[2] = b43_phy_read(dev, afectl_core);
4895 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4896 tmp[4] = b43_phy_read(dev, rfctl[0]);
4897 tmp[5] = b43_phy_read(dev, rfctl[1]);
4898
4899 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
acd82aa8 4900 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
15931e31
RM		 4901 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4902 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4903 (1 - i));
4904 b43_phy_set(dev, afectl_core, 0x0006);
4905 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4906
4907 band = b43_current_band(dev->wl);
4908
4909 if (nphy->rxcalparams & 0xFF000000) {
4910 if (band == IEEE80211_BAND_5GHZ)
4911 b43_phy_write(dev, rfctl[0], 0x140);
4912 else
4913 b43_phy_write(dev, rfctl[0], 0x110);
4914 } else {
4915 if (band == IEEE80211_BAND_5GHZ)
4916 b43_phy_write(dev, rfctl[0], 0x180);
4917 else
4918 b43_phy_write(dev, rfctl[0], 0x120);
4919 }
4920
4921 if (band == IEEE80211_BAND_5GHZ)
4922 b43_phy_write(dev, rfctl[1], 0x148);
4923 else
4924 b43_phy_write(dev, rfctl[1], 0x114);
4925
4926 if (nphy->rxcalparams & 0x10000) {
4927 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4928 (i + 1));
4929 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4930 (2 - i));
4931 }
4932
30115c22 4933 for (j = 0; j < 4; j++) {
15931e31
RM		 4934 if (j < 3) {
4935 cur_lna = lna[j];
4936 cur_hpf1 = hpf1[j];
4937 cur_hpf2 = hpf2[j];
4938 } else {
4939 if (power[1] > 10000) {
4940 use = 1;
4941 cur_hpf = cur_hpf1;
4942 index = 2;
4943 } else {
4944 if (power[0] > 10000) {
4945 use = 1;
4946 cur_hpf = cur_hpf1;
4947 index = 1;
4948 } else {
4949 index = 0;
4950 use = 2;
4951 cur_hpf = cur_hpf2;
4952 }
4953 }
4954 cur_lna = lna[index];
4955 cur_hpf1 = hpf1[index];
4956 cur_hpf2 = hpf2[index];
4957 cur_hpf += desired - hweight32(power[index]);
4958 cur_hpf = clamp_val(cur_hpf, 0, 10);
4959 if (use == 1)
4960 cur_hpf1 = cur_hpf;
4961 else
4962 cur_hpf2 = cur_hpf;
4963 }
4964
4965 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4966 (cur_lna << 2));
78ae7532 4967 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3,
75377b24 4968 false);
de9a47f9 4969 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
53ae8e8c 4970 b43_nphy_stop_playback(dev);
15931e31
RM		 4971
4972 if (playtone) {
59af099b
RM		 4973 ret = b43_nphy_tx_tone(dev, 4000,
4974 (nphy->rxcalparams & 0xFFFF),
4975 false, false);
15931e31
RM		 4976 playtone = false;
4977 } else {
10a79873
RM		 4978 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4979 false, false);
15931e31
RM		 4980 }
4981
4982 if (ret == 0) {
4983 if (j < 3) {
4984 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4985 false);
4986 if (i == 0) {
4987 real = est.i0_pwr;
4988 imag = est.q0_pwr;
4989 } else {
4990 real = est.i1_pwr;
4991 imag = est.q1_pwr;
4992 }
4993 power[i] = ((real + imag) / 1024) + 1;
4994 } else {
4995 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4996 }
53ae8e8c 4997 b43_nphy_stop_playback(dev);
15931e31
RM		 4998 }
4999
5000 if (ret != 0)
5001 break;
5002 }
5003
5004 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
5005 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
5006 b43_phy_write(dev, rfctl[1], tmp[5]);
5007 b43_phy_write(dev, rfctl[0], tmp[4]);
5008 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
5009 b43_phy_write(dev, afectl_core, tmp[2]);
5010 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
5011
5012 if (ret != 0)
5013 break;
5014 }
5015
78ae7532 5016 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true);
67c0d6e2 5017 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2581b143 5018 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
15931e31
RM		 5019
5020 b43_nphy_stay_in_carrier_search(dev, 0);
5021
5022 return ret;
5023}
5024
5025static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
5026 struct nphy_txgains target, u8 type, bool debug)
5027{
5028 return -1;
5029}
5030
5031/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
5032static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
5033 struct nphy_txgains target, u8 type, bool debug)
5034{
5035 if (dev->phy.rev >= 3)
5036 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
5037 else
5038 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
5039}
5040
4e687b22
GS		 5041/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
5042static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
5043{
5044 struct b43_phy *phy = &dev->phy;
5045 struct b43_phy_n *nphy = phy->n;
0b81c23d 5046 /* u16 buf[16]; it's rev3+ */
4e687b22 5047
049fbfee
RM		 5048 nphy->phyrxchain = mask;
5049
4e687b22
GS		 5050 if (0 /* FIXME clk */)
5051 return;
5052
5053 b43_mac_suspend(dev);
5054
5055 if (nphy->hang_avoid)
5056 b43_nphy_stay_in_carrier_search(dev, true);
5057
5058 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
5059 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
5060
049fbfee 5061 if ((mask & 0x3) != 0x3) {
4e687b22
GS		 5062 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
5063 if (dev->phy.rev >= 3) {
5064 /* TODO */
5065 }
5066 } else {
5067 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
5068 if (dev->phy.rev >= 3) {
5069 /* TODO */
5070 }
5071 }
5072
5073 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
5074
5075 if (nphy->hang_avoid)
5076 b43_nphy_stay_in_carrier_search(dev, false);
5077
5078 b43_mac_enable(dev);
5079}
5080
104cfa88
RM		 5081/**************************************************
5082 * N-PHY init
5083 **************************************************/
5084
104cfa88
RM		 5085/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
5086static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
5087{
5088 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
5089
5090 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
5091 if (preamble == 1)
5092 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
5093 else
5094 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
5095
5096 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
5097}
5098
5099/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
5100static void b43_nphy_bphy_init(struct b43_wldev *dev)
5101{
5102 unsigned int i;
5103 u16 val;
5104
5105 val = 0x1E1F;
5106 for (i = 0; i < 16; i++) {
5107 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
5108 val -= 0x202;
5109 }
5110 val = 0x3E3F;
5111 for (i = 0; i < 16; i++) {
5112 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
5113 val -= 0x202;
5114 }
5115 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
5116}
5117
5118/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
5119static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
5120{
5121 if (dev->phy.rev >= 3) {
5122 if (!init)
5123 return;
5124 if (0 /* FIXME */) {
5125 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
5126 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
5127 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
5128 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
5129 }
5130 } else {
5131 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
5132 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
5133
5134 switch (dev->dev->bus_type) {
5135#ifdef CONFIG_B43_BCMA
5136 case B43_BUS_BCMA:
5137 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
5138 0xFC00, 0xFC00);
5139 break;
5140#endif
5141#ifdef CONFIG_B43_SSB
5142 case B43_BUS_SSB:
5143 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
5144 0xFC00, 0xFC00);
5145 break;
5146#endif
5147 }
5148
5056635c
RM		 5149 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
5150 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
5151 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
5152 0);
104cfa88
RM		 5153
5154 if (init) {
5155 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
5156 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
5157 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
5158 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
5159 }
5160 }
5161}
5162
5163/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
2d9d2385 5164static int b43_phy_initn(struct b43_wldev *dev)
424047e6 5165{
0581483a 5166 struct ssb_sprom *sprom = dev->dev->bus_sprom;
95b66bad 5167 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 5168 struct b43_phy_n *nphy = phy->n;
5169 u8 tx_pwr_state;
5170 struct nphy_txgains target;
95b66bad 5171 u16 tmp;
0988a7a1
RM		 5172 enum ieee80211_band tmp2;
5173 bool do_rssi_cal;
5174
5175 u16 clip[2];
5176 bool do_cal = false;
95b66bad 5177
0988a7a1 5178 if ((dev->phy.rev >= 3) &&
0581483a 5179 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
0988a7a1 5180 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
6cbab0d9 5181 switch (dev->dev->bus_type) {
42c9a458
RM		 5182#ifdef CONFIG_B43_BCMA
5183 case B43_BUS_BCMA:
5184 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
5185 BCMA_CC_CHIPCTL, 0x40);
5186 break;
5187#endif
6cbab0d9
RM		 5188#ifdef CONFIG_B43_SSB
5189 case B43_BUS_SSB:
5190 chipco_set32(&dev->dev->sdev->bus->chipco,
5191 SSB_CHIPCO_CHIPCTL, 0x40);
5192 break;
5193#endif
5194 }
0988a7a1
RM		 5195 }
5196 nphy->deaf_count = 0;
95b66bad 5197 b43_nphy_tables_init(dev);
0988a7a1
RM		 5198 nphy->crsminpwr_adjusted = false;
5199 nphy->noisevars_adjusted = false;
95b66bad
MB		 5200
5201 /* Clear all overrides */
0988a7a1
RM		 5202 if (dev->phy.rev >= 3) {
5203 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
5204 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5205 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
5206 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
5207 } else {
5208 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
5209 }
95b66bad
MB		 5210 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
5211 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 5212 if (dev->phy.rev < 6) {
5213 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
5214 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
5215 }
95b66bad
MB		 5216 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
5217 ~(B43_NPHY_RFSEQMODE_CAOVER |
5218 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 5219 if (dev->phy.rev >= 3)
5220 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 5221 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
5222
0988a7a1
RM		 5223 if (dev->phy.rev <= 2) {
5224 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
5225 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
5226 ~B43_NPHY_BPHY_CTL3_SCALE,
5227 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
5228 }
95b66bad
MB		 5229 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
5230 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
5231
0eff8fcd 5232 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
79d2232f 5233 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
fb3bc67e 5234 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93))
0988a7a1
RM		 5235 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
5236 else
5237 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
5238 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
5239 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
5240 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 5241
ad9716e8 5242 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 5243 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 5244
5245 if (phy->rev < 2) {
5246 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
5247 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
5248 }
0988a7a1
RM		 5249
5250 tmp2 = b43_current_band(dev->wl);
c002831a 5251 if (b43_nphy_ipa(dev)) {
0988a7a1
RM		 5252 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
5253 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
5254 nphy->papd_epsilon_offset[0] << 7);
5255 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
5256 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
5257 nphy->papd_epsilon_offset[1] << 7);
45ca697e 5258 b43_nphy_int_pa_set_tx_dig_filters(dev);
0988a7a1 5259 } else if (phy->rev >= 5) {
45ca697e 5260 b43_nphy_ext_pa_set_tx_dig_filters(dev);
0988a7a1
RM		 5261 }
5262
95b66bad 5263 b43_nphy_workarounds(dev);
95b66bad 5264
0988a7a1 5265 /* Reset CCA, in init code it differs a little from standard way */
f6a3e99d 5266 b43_phy_force_clock(dev, 1);
0988a7a1
RM		 5267 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
5268 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
5269 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
f6a3e99d 5270 b43_phy_force_clock(dev, 0);
0988a7a1 5271
858a1652 5272 b43_mac_phy_clock_set(dev, true);
0988a7a1 5273
e50cbcf6 5274 b43_nphy_pa_override(dev, false);
95b66bad
MB		 5275 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
5276 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 5277 b43_nphy_pa_override(dev, true);
0988a7a1 5278
bbec398c
RM		 5279 b43_nphy_classifier(dev, 0, 0);
5280 b43_nphy_read_clip_detection(dev, clip);
bec18645
RM		 5281 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5282 b43_nphy_bphy_init(dev);
5283
0988a7a1 5284 tx_pwr_state = nphy->txpwrctrl;
161d540c
RM		 5285 b43_nphy_tx_power_ctrl(dev, false);
5286 b43_nphy_tx_power_fix(dev);
3dda07b6 5287 b43_nphy_tx_power_ctl_idle_tssi(dev);
d3fd8bf7 5288 b43_nphy_tx_power_ctl_setup(dev);
0eff8fcd 5289 b43_nphy_tx_gain_table_upload(dev);
95b66bad 5290
0988a7a1 5291 if (nphy->phyrxchain != 3)
4e687b22 5292 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
0988a7a1
RM		 5293 if (nphy->mphase_cal_phase_id > 0)
5294 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
5295
5296 do_rssi_cal = false;
5297 if (phy->rev >= 3) {
5298 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5299 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
0988a7a1 5300 else
204a665b 5301 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
0988a7a1
RM		 5302
5303 if (do_rssi_cal)
4cb99775 5304 b43_nphy_rssi_cal(dev);
0988a7a1 5305 else
42e1547e 5306 b43_nphy_restore_rssi_cal(dev);
0988a7a1 5307 } else {
4cb99775 5308 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5309 }
5310
5311 if (!((nphy->measure_hold & 0x6) != 0)) {
5312 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
204a665b 5313 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
0988a7a1 5314 else
204a665b 5315 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
0988a7a1
RM		 5316
5317 if (nphy->mute)
5318 do_cal = false;
5319
5320 if (do_cal) {
b0022e15 5321 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 5322
5323 if (nphy->antsel_type == 2)
8987a9e9 5324 b43_nphy_superswitch_init(dev, true);
0988a7a1 5325 if (nphy->perical != 2) {
90b9738d 5326 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 5327 if (phy->rev >= 3) {
5328 nphy->cal_orig_pwr_idx[0] =
5329 nphy->txpwrindex[0].index_internal;
5330 nphy->cal_orig_pwr_idx[1] =
5331 nphy->txpwrindex[1].index_internal;
5332 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 5333 target = b43_nphy_get_tx_gains(dev);
0988a7a1 5334 }
e7797bf2
RM		 5335 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
5336 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
5337 b43_nphy_save_cal(dev);
5338 } else if (nphy->mphase_cal_phase_id == 0)
5339 ;/* N PHY Periodic Calibration with arg 3 */
5340 } else {
5341 b43_nphy_restore_cal(dev);
0988a7a1
RM		 5342 }
5343 }
5344
6dcd9d91 5345 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
161d540c 5346 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
0988a7a1
RM		 5347 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
5348 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
5349 if (phy->rev >= 3 && phy->rev <= 6)
bc36e994 5350 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032);
fe3e46e8 5351 b43_nphy_tx_lp_fbw(dev);
9442e5b5
RM		 5352 if (phy->rev >= 3)
5353 b43_nphy_spur_workaround(dev);
95b66bad 5354
53a6e234 5355 return 0;
424047e6 5356}
ef1a628d 5357
104cfa88
RM		 5358/**************************************************
5359 * Channel switching ops.
5360 **************************************************/
5361
5362static void b43_chantab_phy_upload(struct b43_wldev *dev,
5363 const struct b43_phy_n_sfo_cfg *e)
5364{
5365 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
5366 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
5367 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
5368 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
5369 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
5370 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
5371}
5372
49d55cef
RM		 5373/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
5374static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
5375{
d66be829
RM		 5376 switch (dev->dev->bus_type) {
5377#ifdef CONFIG_B43_BCMA
5378 case B43_BUS_BCMA:
9b383672
HM		 5379 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc,
5380 avoid);
d66be829 5381 break;
8b1fdb53 5382#endif
d66be829
RM		 5383#ifdef CONFIG_B43_SSB
5384 case B43_BUS_SSB:
46fc4c90
RM		 5385 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
5386 avoid);
d66be829
RM		 5387 break;
5388#endif
5389 }
49d55cef
RM		 5390}
5391
1b69ec7b 5392/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
a656b6a9 5393static void b43_nphy_channel_setup(struct b43_wldev *dev,
b15b3039 5394 const struct b43_phy_n_sfo_cfg *e,
a656b6a9 5395 struct ieee80211_channel *new_channel)
1b69ec7b
RM		 5396{
5397 struct b43_phy *phy = &dev->phy;
5398 struct b43_phy_n *nphy = dev->phy.n;
49d55cef 5399 int ch = new_channel->hw_value;
1b69ec7b 5400
087de74a 5401 u16 old_band_5ghz;
12cd43c6 5402 u16 tmp16;
1b69ec7b 5403
087de74a
RM		 5404 old_band_5ghz =
5405 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
5406 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
12cd43c6
RM		 5407 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5408 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
1b69ec7b 5409 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
12cd43c6 5410 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b 5411 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
087de74a 5412 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
1b69ec7b 5413 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
12cd43c6
RM		 5414 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR);
5415 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4);
acd82aa8 5416 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
12cd43c6 5417 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16);
1b69ec7b
RM		 5418 }
5419
5420 b43_chantab_phy_upload(dev, e);
5421
a656b6a9 5422 if (new_channel->hw_value == 14) {
1b69ec7b
RM		 5423 b43_nphy_classifier(dev, 2, 0);
5424 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
5425 } else {
5426 b43_nphy_classifier(dev, 2, 2);
a656b6a9 5427 if (new_channel->band == IEEE80211_BAND_2GHZ)
1b69ec7b
RM		 5428 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
5429 }
5430
161d540c 5431 if (!nphy->txpwrctrl)
1b69ec7b
RM		 5432 b43_nphy_tx_power_fix(dev);
5433
5434 if (dev->phy.rev < 3)
5435 b43_nphy_adjust_lna_gain_table(dev);
5436
5437 b43_nphy_tx_lp_fbw(dev);
5438
49d55cef
RM		 5439 if (dev->phy.rev >= 3 &&
5440 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
5441 bool avoid = false;
5442 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
5443 avoid = true;
5444 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
5445 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
5446 avoid = true;
5447 } else { /* 40MHz */
5448 if (nphy->aband_spurwar_en &&
5449 (ch == 38 || ch == 102 || ch == 118))
5450 avoid = dev->dev->chip_id == 0x4716;
5451 }
5452
5453 b43_nphy_pmu_spur_avoid(dev, avoid);
5454
5455 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
5456 dev->dev->chip_id == 43225) {
5457 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
5458 avoid ? 0x5341 : 0x8889);
5459 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
5460 }
5461
5462 if (dev->phy.rev == 3 || dev->phy.rev == 4)
5463 ; /* TODO: reset PLL */
5464
5465 if (avoid)
5466 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
5467 else
5468 b43_phy_mask(dev, B43_NPHY_BBCFG,
5469 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
5470
5471 b43_nphy_reset_cca(dev);
5472
5473 /* wl sets useless phy_isspuravoid here */
1b69ec7b
RM		 5474 }
5475
5476 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
5477
5478 if (phy->rev >= 3)
5479 b43_nphy_spur_workaround(dev);
5480}
5481
eff66c51 5482/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
a656b6a9
RM		 5483static int b43_nphy_set_channel(struct b43_wldev *dev,
5484 struct ieee80211_channel *channel,
5485 enum nl80211_channel_type channel_type)
eff66c51 5486{
a656b6a9 5487 struct b43_phy *phy = &dev->phy;
eff66c51 5488
2eeb6fd0
JL		 5489 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
5490 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
eff66c51
RM		 5491
5492 u8 tmp;
eff66c51
RM		 5493
5494 if (dev->phy.rev >= 3) {
f2a6d6a0
RM		 5495 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
5496 channel->center_freq);
f19ebe7d
RM		 5497 if (!tabent_r3)
5498 return -ESRCH;
ffd2d9bd 5499 } else {
a656b6a9
RM		 5500 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
5501 channel->hw_value);
f19ebe7d 5502 if (!tabent_r2)
ffd2d9bd 5503 return -ESRCH;
eff66c51
RM		 5504 }
5505
204a665b
RM		 5506 /* Channel is set later in common code, but we need to set it on our
5507 own to let this function's subcalls work properly. */
5508 phy->channel = channel->hw_value;
5509 phy->channel_freq = channel->center_freq;
eff66c51 5510
e5c407f9
RM		 5511 if (b43_channel_type_is_40mhz(phy->channel_type) !=
5512 b43_channel_type_is_40mhz(channel_type))
5513 ; /* TODO: BMAC BW Set (channel_type) */
eff66c51 5514
a656b6a9
RM		 5515 if (channel_type == NL80211_CHAN_HT40PLUS)
5516 b43_phy_set(dev, B43_NPHY_RXCTL,
5517 B43_NPHY_RXCTL_BSELU20);
5518 else if (channel_type == NL80211_CHAN_HT40MINUS)
5519 b43_phy_mask(dev, B43_NPHY_RXCTL,
5520 ~B43_NPHY_RXCTL_BSELU20);
eff66c51
RM		 5521
5522 if (dev->phy.rev >= 3) {
a656b6a9 5523 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
eff66c51 5524 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
d4814e69 5525 b43_radio_2056_setup(dev, tabent_r3);
a656b6a9 5526 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
eff66c51 5527 } else {
a656b6a9 5528 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
eff66c51 5529 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
f19ebe7d 5530 b43_radio_2055_setup(dev, tabent_r2);
a656b6a9 5531 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
eff66c51
RM		 5532 }
5533
5534 return 0;
5535}
5536
104cfa88
RM		 5537/**************************************************
5538 * Basic PHY ops.
5539 **************************************************/
5540
ef1a628d
MB		 5541static int b43_nphy_op_allocate(struct b43_wldev *dev)
5542{
5543 struct b43_phy_n *nphy;
5544
5545 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
5546 if (!nphy)
5547 return -ENOMEM;
5548 dev->phy.n = nphy;
5549
ef1a628d
MB		 5550 return 0;
5551}
5552
fb11137a 5553static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 5554{
fb11137a
MB		 5555 struct b43_phy *phy = &dev->phy;
5556 struct b43_phy_n *nphy = phy->n;
c7d64310 5557 struct ssb_sprom *sprom = dev->dev->bus_sprom;
ef1a628d 5558
fb11137a 5559 memset(nphy, 0, sizeof(*nphy));
ef1a628d 5560
aca434d3 5561 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
c7d64310
RM		 5562 nphy->spur_avoid = (phy->rev >= 3) ?
5563 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
d3d178f0 5564 nphy->init_por = true;
0b81c23d
RM		 5565 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
5566 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
5567 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
8c1d5a7a 5568 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
c9c0d9ec
RM		 5569 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
5570 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
5571 nphy->tx_pwr_idx[0] = 128;
5572 nphy->tx_pwr_idx[1] = 128;
c7d64310
RM		 5573
5574 /* Hardware TX power control and 5GHz power gain */
5575 nphy->txpwrctrl = false;
5576 nphy->pwg_gain_5ghz = false;
5577 if (dev->phy.rev >= 3 ||
5578 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
5579 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
5580 nphy->txpwrctrl = true;
5581 nphy->pwg_gain_5ghz = true;
5582 } else if (sprom->revision >= 4) {
5583 if (dev->phy.rev >= 2 &&
5584 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
5585 nphy->txpwrctrl = true;
5586#ifdef CONFIG_B43_SSB
5587 if (dev->dev->bus_type == B43_BUS_SSB &&
5588 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
5589 struct pci_dev *pdev =
5590 dev->dev->sdev->bus->host_pci;
5591 if (pdev->device == 0x4328 ||
5592 pdev->device == 0x432a)
5593 nphy->pwg_gain_5ghz = true;
5594 }
5595#endif
5596 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
5597 nphy->pwg_gain_5ghz = true;
5598 }
5599 }
5600
5601 if (dev->phy.rev >= 3) {
5602 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
5603 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
5604 }
572d37a4
RM		 5605
5606 nphy->init_por = true;
ef1a628d
MB		 5607}
5608
fb11137a 5609static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 5610{
fb11137a
MB		 5611 struct b43_phy *phy = &dev->phy;
5612 struct b43_phy_n *nphy = phy->n;
ef1a628d 5613
ef1a628d 5614 kfree(nphy);
fb11137a
MB		 5615 phy->n = NULL;
5616}
5617
5618static int b43_nphy_op_init(struct b43_wldev *dev)
5619{
5620 return b43_phy_initn(dev);
ef1a628d
MB		 5621}
5622
5623static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
5624{
5625#if B43_DEBUG
5626 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
5627 /* OFDM registers are onnly available on A/G-PHYs */
5628 b43err(dev->wl, "Invalid OFDM PHY access at "
5629 "0x%04X on N-PHY\n", offset);
5630 dump_stack();
5631 }
5632 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
5633 /* Ext-G registers are only available on G-PHYs */
5634 b43err(dev->wl, "Invalid EXT-G PHY access at "
5635 "0x%04X on N-PHY\n", offset);
5636 dump_stack();
5637 }
5638#endif /* B43_DEBUG */
5639}
5640
5641static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
5642{
5643 check_phyreg(dev, reg);
5644 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5645 return b43_read16(dev, B43_MMIO_PHY_DATA);
5646}
5647
5648static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
5649{
5650 check_phyreg(dev, reg);
5651 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5652 b43_write16(dev, B43_MMIO_PHY_DATA, value);
5653}
5654
755fd183
RM		 5655static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
5656 u16 set)
5657{
5658 check_phyreg(dev, reg);
5659 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
5056635c 5660 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
755fd183
RM		 5661}
5662
ef1a628d
MB		 5663static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
5664{
5665 /* Register 1 is a 32-bit register. */
5666 B43_WARN_ON(reg == 1);
a6aa05d6
RM		 5667
5668 if (dev->phy.rev >= 7)
5669 reg |= 0x200; /* Radio 0x2057 */
5670 else
5671 reg |= 0x100;
ef1a628d
MB		 5672
5673 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5674 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
5675}
5676
5677static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
5678{
5679 /* Register 1 is a 32-bit register. */
5680 B43_WARN_ON(reg == 1);
5681
5682 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
5683 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
5684}
5685
c2b7aefd 5686/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
ef1a628d 5687static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 5688 bool blocked)
c2b7aefd
RM		 5689{
5690 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
5691 b43err(dev->wl, "MAC not suspended\n");
5692
5693 if (blocked) {
5694 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
5695 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
572d37a4
RM		 5696 if (dev->phy.rev >= 7) {
5697 /* TODO */
5698 } else if (dev->phy.rev >= 3) {
c2b7aefd
RM		 5699 b43_radio_mask(dev, 0x09, ~0x2);
5700
5701 b43_radio_write(dev, 0x204D, 0);
5702 b43_radio_write(dev, 0x2053, 0);
5703 b43_radio_write(dev, 0x2058, 0);
5704 b43_radio_write(dev, 0x205E, 0);
5705 b43_radio_mask(dev, 0x2062, ~0xF0);
5706 b43_radio_write(dev, 0x2064, 0);
5707
5708 b43_radio_write(dev, 0x304D, 0);
5709 b43_radio_write(dev, 0x3053, 0);
5710 b43_radio_write(dev, 0x3058, 0);
5711 b43_radio_write(dev, 0x305E, 0);
5712 b43_radio_mask(dev, 0x3062, ~0xF0);
5713 b43_radio_write(dev, 0x3064, 0);
5714 }
5715 } else {
572d37a4
RM		 5716 if (dev->phy.rev >= 7) {
5717 b43_radio_2057_init(dev);
5718 b43_switch_channel(dev, dev->phy.channel);
5719 } else if (dev->phy.rev >= 3) {
d817f4e1 5720 b43_radio_init2056(dev);
78159788 5721 b43_switch_channel(dev, dev->phy.channel);
c2b7aefd
RM		 5722 } else {
5723 b43_radio_init2055(dev);
5724 }
5725 }
ef1a628d
MB		 5726}
5727
0f4091b9 5728/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
cb24f57f
MB		 5729static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
5730{
2a870831
RM		 5731 u16 override = on ? 0x0 : 0x7FFF;
5732 u16 core = on ? 0xD : 0x00FD;
0f4091b9 5733
2a870831
RM		 5734 if (dev->phy.rev >= 3) {
5735 if (on) {
5736 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5737 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5738 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5739 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5740 } else {
5741 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
5742 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
5743 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5744 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
5745 }
5746 } else {
5747 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
5748 }
cb24f57f
MB		 5749}
5750
ef1a628d
MB		 5751static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
5752 unsigned int new_channel)
5753{
675a0b04
KB		 5754 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
5755 enum nl80211_channel_type channel_type =
5756 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef);
5e7ee098 5757
ef1a628d
MB		 5758 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
5759 if ((new_channel < 1) || (new_channel > 14))
5760 return -EINVAL;
5761 } else {
5762 if (new_channel > 200)
5763 return -EINVAL;
5764 }
5765
a656b6a9 5766 return b43_nphy_set_channel(dev, channel, channel_type);
ef1a628d
MB		 5767}
5768
5769static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
5770{
5771 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
5772 return 1;
5773 return 36;
5774}
5775
ef1a628d
MB		 5776const struct b43_phy_operations b43_phyops_n = {
5777 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 5778 .free = b43_nphy_op_free,
5779 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 5780 .init = b43_nphy_op_init,
ef1a628d
MB		 5781 .phy_read = b43_nphy_op_read,
5782 .phy_write = b43_nphy_op_write,
755fd183 5783 .phy_maskset = b43_nphy_op_maskset,
ef1a628d
MB		 5784 .radio_read = b43_nphy_op_radio_read,
5785 .radio_write = b43_nphy_op_radio_write,
5786 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 5787 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 5788 .switch_channel = b43_nphy_op_switch_channel,
5789 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 5790 .recalc_txpower = b43_nphy_op_recalc_txpower,
5791 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 5792};
Linux 6.x block layer and io_uring tree(s)