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d7520b1d RM |
1 | #ifndef B43_PHY_HT_H_ |
2 | #define B43_PHY_HT_H_ | |
3 | ||
4 | #include "phy_common.h" | |
5 | ||
6 | ||
19240f36 RM |
7 | #define B43_PHY_HT_BBCFG 0x001 /* BB config */ |
8 | #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */ | |
9 | #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */ | |
bdb2dfb2 | 10 | #define B43_PHY_HT_BANDCTL 0x009 /* Band control */ |
19240f36 | 11 | #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */ |
d7520b1d RM |
12 | #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */ |
13 | #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */ | |
14 | #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */ | |
b372afae RM |
15 | #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */ |
16 | #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */ | |
17 | #define B43_PHY_HT_CLASS_CTL_OFDM_EN 0x0002 /* OFDM enable */ | |
18 | #define B43_PHY_HT_CLASS_CTL_WAITED_EN 0x0004 /* Waited enable */ | |
371ec465 RM |
19 | #define B43_PHY_HT_IQLOCAL_CMDGCTL 0x0C2 /* I/Q LO cal command G control */ |
20 | #define B43_PHY_HT_SAMP_CMD 0x0C3 /* Sample command */ | |
21 | #define B43_PHY_HT_SAMP_CMD_STOP 0x0002 /* Stop */ | |
396535e1 RM |
22 | #define B43_PHY_HT_SAMP_LOOP_CNT 0x0C4 /* Sample loop count */ |
23 | #define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ | |
24 | #define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ | |
371ec465 | 25 | #define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ |
fc6ab1e0 RM |
26 | #define B43_PHY_HT_EST_PWR_C1 0x118 |
27 | #define B43_PHY_HT_EST_PWR_C2 0x119 | |
28 | #define B43_PHY_HT_EST_PWR_C3 0x11A | |
5949e040 RM |
29 | #define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ |
30 | #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ | |
31 | #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ | |
bdb2dfb2 RM |
32 | #define B43_PHY_HT_BW1 0x1CE |
33 | #define B43_PHY_HT_BW2 0x1CF | |
34 | #define B43_PHY_HT_BW3 0x1D0 | |
35 | #define B43_PHY_HT_BW4 0x1D1 | |
36 | #define B43_PHY_HT_BW5 0x1D2 | |
37 | #define B43_PHY_HT_BW6 0x1D3 | |
60e8fb92 RM |
38 | #define B43_PHY_HT_TXPCTL_CMD_C1 0x1E7 /* TX power control command */ |
39 | #define B43_PHY_HT_TXPCTL_CMD_C1_INIT 0x007F /* Init */ | |
40 | #define B43_PHY_HT_TXPCTL_CMD_C1_COEFF 0x2000 /* Power control coefficients */ | |
41 | #define B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN 0x4000 /* Hardware TX power control enable */ | |
42 | #define B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN 0x8000 /* TX power control enable */ | |
5949e040 RM |
43 | #define B43_PHY_HT_TXPCTL_N 0x1E8 /* TX power control N num */ |
44 | #define B43_PHY_HT_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */ | |
45 | #define B43_PHY_HT_TXPCTL_N_TSSID_SHIFT 0 | |
46 | #define B43_PHY_HT_TXPCTL_N_NPTIL2 0x0700 /* N PT integer log2 */ | |
47 | #define B43_PHY_HT_TXPCTL_N_NPTIL2_SHIFT 8 | |
48 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI 0x1E9 /* TX power control idle TSSI */ | |
49 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1 0x003F | |
50 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C1_SHIFT 0 | |
51 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2 0x3F00 | |
52 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_C2_SHIFT 8 | |
53 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI_BINF 0x8000 /* Raw TSSI offset bin format */ | |
54 | #define B43_PHY_HT_TXPCTL_TARG_PWR 0x1EA /* TX power control target power */ | |
55 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C1 0x00FF /* Power 0 */ | |
56 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 | |
57 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ | |
58 | #define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 | |
fc6ab1e0 RM |
59 | #define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED |
60 | #define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE | |
60e8fb92 RM |
61 | #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 |
62 | #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F | |
4409a23f RM |
63 | #define B43_PHY_HT_RSSI_C1 0x219 |
64 | #define B43_PHY_HT_RSSI_C2 0x21A | |
65 | #define B43_PHY_HT_RSSI_C3 0x21B | |
d7520b1d | 66 | |
ea5a08cf RM |
67 | #define B43_PHY_HT_C1_CLIP1THRES B43_PHY_OFDM(0x00E) |
68 | #define B43_PHY_HT_C2_CLIP1THRES B43_PHY_OFDM(0x04E) | |
69 | #define B43_PHY_HT_C3_CLIP1THRES B43_PHY_OFDM(0x08E) | |
70 | ||
c750f795 | 71 | #define B43_PHY_HT_RF_SEQ_MODE B43_PHY_EXTG(0x000) |
396535e1 RM |
72 | #define B43_PHY_HT_RF_SEQ_MODE_CA_OVER 0x0001 /* Core active override */ |
73 | #define B43_PHY_HT_RF_SEQ_MODE_TR_OVER 0x0002 /* Trigger override */ | |
c750f795 RM |
74 | #define B43_PHY_HT_RF_SEQ_TRIG B43_PHY_EXTG(0x003) |
75 | #define B43_PHY_HT_RF_SEQ_TRIG_RX2TX 0x0001 /* RX2TX */ | |
76 | #define B43_PHY_HT_RF_SEQ_TRIG_TX2RX 0x0002 /* TX2RX */ | |
77 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGH 0x0004 /* Update gain H */ | |
78 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGL 0x0008 /* Update gain L */ | |
79 | #define B43_PHY_HT_RF_SEQ_TRIG_UPGU 0x0010 /* Update gain U */ | |
80 | #define B43_PHY_HT_RF_SEQ_TRIG_RST2RX 0x0020 /* Reset to RX */ | |
81 | #define B43_PHY_HT_RF_SEQ_STATUS B43_PHY_EXTG(0x004) | |
82 | /* Values for the status are the same as for the trigger */ | |
83 | ||
85e6c26f RM |
84 | #define B43_PHY_HT_RF_CTL_CMD 0x810 |
85 | #define B43_PHY_HT_RF_CTL_CMD_FORCE 0x0001 | |
86 | #define B43_PHY_HT_RF_CTL_CMD_CHIP0_PU 0x0002 | |
e7c62552 | 87 | |
a51ab258 RM |
88 | #define B43_PHY_HT_RF_CTL_INT_C1 B43_PHY_EXTG(0x04c) |
89 | #define B43_PHY_HT_RF_CTL_INT_C2 B43_PHY_EXTG(0x06c) | |
90 | #define B43_PHY_HT_RF_CTL_INT_C3 B43_PHY_EXTG(0x08c) | |
91 | ||
47606922 RM |
92 | #define B43_PHY_HT_AFE_C1_OVER B43_PHY_EXTG(0x110) |
93 | #define B43_PHY_HT_AFE_C1 B43_PHY_EXTG(0x111) | |
94 | #define B43_PHY_HT_AFE_C2_OVER B43_PHY_EXTG(0x114) | |
95 | #define B43_PHY_HT_AFE_C2 B43_PHY_EXTG(0x115) | |
96 | #define B43_PHY_HT_AFE_C3_OVER B43_PHY_EXTG(0x118) | |
97 | #define B43_PHY_HT_AFE_C3 B43_PHY_EXTG(0x119) | |
a8e82749 | 98 | |
60e8fb92 RM |
99 | #define B43_PHY_HT_TXPCTL_CMD_C3 B43_PHY_EXTG(0x164) |
100 | #define B43_PHY_HT_TXPCTL_CMD_C3_INIT 0x007F | |
5949e040 RM |
101 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2 B43_PHY_EXTG(0x165) /* TX power control idle TSSI */ |
102 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3 0x003F | |
103 | #define B43_PHY_HT_TXPCTL_IDLE_TSSI2_C3_SHIFT 0 | |
104 | #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ | |
105 | #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF | |
106 | #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 | |
fc6ab1e0 | 107 | #define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169) |
60e8fb92 | 108 | |
1f21de53 RM |
109 | #define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) |
110 | #define B43_PHY_B_BBCFG_RSTCCA 0x4000 /* Reset CCA */ | |
111 | #define B43_PHY_B_BBCFG_RSTRX 0x8000 /* Reset RX */ | |
b372afae RM |
112 | #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A) |
113 | ||
d7520b1d | 114 | |
5192bf56 RM |
115 | /* Values for PHY registers used on channel switching */ |
116 | struct b43_phy_ht_channeltab_e_phy { | |
bdb2dfb2 RM |
117 | u16 bw1; |
118 | u16 bw2; | |
119 | u16 bw3; | |
120 | u16 bw4; | |
121 | u16 bw5; | |
122 | u16 bw6; | |
5192bf56 RM |
123 | }; |
124 | ||
125 | ||
d7520b1d | 126 | struct b43_phy_ht { |
a51ab258 | 127 | u16 rf_ctl_int_save[3]; |
60e8fb92 RM |
128 | |
129 | bool tx_pwr_ctl; | |
130 | u8 tx_pwr_idx[3]; | |
371ec465 RM |
131 | |
132 | s32 bb_mult_save[3]; | |
4409a23f RM |
133 | |
134 | u8 idle_tssi[3]; | |
d7520b1d RM |
135 | }; |
136 | ||
137 | ||
138 | struct b43_phy_operations; | |
139 | extern const struct b43_phy_operations b43_phyops_ht; | |
140 | ||
141 | #endif /* B43_PHY_HT_H_ */ |