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b43: HT-PHY: move TX fix to the separated function
[linux-2.6-block.git] / drivers / net / wireless / b43 / phy_ht.c
CommitLineData
d7520b1d
RM		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY support
5
108f4f3c
RM		 6 Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
7
d7520b1d
RM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include <linux/slab.h>
26
27#include "b43.h"
28#include "phy_ht.h"
e5b61007 29#include "tables_phy_ht.h"
5192bf56 30#include "radio_2059.h"
d7520b1d
RM		 31#include "main.h"
32
3e644ab4
RM		 33/**************************************************
34 * Radio 2059.
35 **************************************************/
36
39ca554c
RM		 37static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e)
39{
a6b7da5d
RM		 40 u8 i;
41 u16 routing;
42
43 b43_radio_write(dev, 0x16, e->radio_syn16);
44 b43_radio_write(dev, 0x17, e->radio_syn17);
45 b43_radio_write(dev, 0x22, e->radio_syn22);
46 b43_radio_write(dev, 0x25, e->radio_syn25);
47 b43_radio_write(dev, 0x27, e->radio_syn27);
48 b43_radio_write(dev, 0x28, e->radio_syn28);
49 b43_radio_write(dev, 0x29, e->radio_syn29);
50 b43_radio_write(dev, 0x2c, e->radio_syn2c);
51 b43_radio_write(dev, 0x2d, e->radio_syn2d);
52 b43_radio_write(dev, 0x37, e->radio_syn37);
53 b43_radio_write(dev, 0x41, e->radio_syn41);
54 b43_radio_write(dev, 0x43, e->radio_syn43);
55 b43_radio_write(dev, 0x47, e->radio_syn47);
56 b43_radio_write(dev, 0x4a, e->radio_syn4a);
57 b43_radio_write(dev, 0x58, e->radio_syn58);
58 b43_radio_write(dev, 0x5a, e->radio_syn5a);
59 b43_radio_write(dev, 0x6a, e->radio_syn6a);
60 b43_radio_write(dev, 0x6d, e->radio_syn6d);
61 b43_radio_write(dev, 0x6e, e->radio_syn6e);
62 b43_radio_write(dev, 0x92, e->radio_syn92);
63 b43_radio_write(dev, 0x98, e->radio_syn98);
64
65 for (i = 0; i < 2; i++) {
e8dec1e9 66 routing = i ? R2059_RXRX1 : R2059_TXRX0;
a6b7da5d
RM		 67 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
68 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
69 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
70 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
71 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
72 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
73 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
74 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
75 }
76
77 udelay(50);
78
c1c3daee
RM		 79 /* Calibration */
80 b43_radio_mask(dev, 0x2b, ~0x1);
81 b43_radio_mask(dev, 0x2e, ~0x4);
82 b43_radio_set(dev, 0x2e, 0x4);
83 b43_radio_set(dev, 0x2b, 0x1);
84
85 udelay(300);
39ca554c
RM		 86}
87
3e644ab4
RM		 88static void b43_radio_2059_init(struct b43_wldev *dev)
89{
90 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
a5f377fb
RM		 91 const u16 radio_values[3][2] = {
92 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
93 };
94 u16 i, j;
3e644ab4
RM		 95
96 b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
97 b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
98
99 for (i = 0; i < ARRAY_SIZE(routing); i++)
100 b43_radio_set(dev, routing[i] | 0x146, 0x3);
101
102 b43_radio_set(dev, 0x2e, 0x0078);
103 b43_radio_set(dev, 0xc0, 0x0080);
104 msleep(2);
105 b43_radio_mask(dev, 0x2e, ~0x0078);
106 b43_radio_mask(dev, 0xc0, ~0x0080);
107
a5f377fb
RM		 108 if (1) { /* FIXME */
109 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
110 udelay(10);
111 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
112 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
113
114 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
115 udelay(100);
116 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
117
118 for (i = 0; i < 10000; i++) {
119 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
120 i = 0;
121 break;
122 }
123 udelay(100);
124 }
125 if (i)
126 b43err(dev->wl, "radio 0x945 timeout\n");
127
128 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
129 b43_radio_set(dev, 0xa, 0x60);
130
131 for (i = 0; i < 3; i++) {
132 b43_radio_write(dev, 0x17F, radio_values[i][0]);
133 b43_radio_write(dev, 0x13D, 0x6E);
134 b43_radio_write(dev, 0x13E, radio_values[i][1]);
135 b43_radio_write(dev, 0x13C, 0x55);
136
137 for (j = 0; j < 10000; j++) {
138 if (b43_radio_read(dev, 0x140) & 2) {
139 j = 0;
140 break;
141 }
142 udelay(500);
143 }
144 if (j)
145 b43err(dev->wl, "radio 0x140 timeout\n");
146
147 b43_radio_write(dev, 0x13C, 0x15);
148 }
149
150 b43_radio_mask(dev, 0x17F, ~0x1);
151 }
152
b473bc17 153 b43_radio_mask(dev, 0x11, ~0x0008);
3e644ab4
RM		 154}
155
15222b58
RM		 156/**************************************************
157 * Various PHY ops
158 **************************************************/
159
b372afae
RM		 160static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
161{
162 u16 tmp;
163 u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
164 B43_PHY_HT_CLASS_CTL_OFDM_EN |
165 B43_PHY_HT_CLASS_CTL_WAITED_EN;
166
167 tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
168 tmp &= allowed;
169 tmp &= ~mask;
170 tmp |= (val & mask);
171 b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
172
173 return tmp;
174}
175
15222b58
RM		 176static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
177{
178 u8 i, j;
179 u16 base[] = { 0x40, 0x60, 0x80 };
180
181 for (i = 0; i < ARRAY_SIZE(base); i++) {
182 for (j = 0; j < 4; j++)
183 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
184 }
185
186 for (i = 0; i < ARRAY_SIZE(base); i++)
187 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
188}
189
a4042bb0
RM		 190/* Some unknown AFE (Analog Frondned) op */
191static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
192{
193 u8 i;
194
47606922
RM		 195 static const u16 ctl_regs[3][2] = {
196 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
197 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
198 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
a4042bb0
RM		 199 };
200
201 for (i = 0; i < 3; i++) {
202 /* TODO: verify masks&sets */
203 b43_phy_set(dev, ctl_regs[i][1], 0x4);
204 b43_phy_set(dev, ctl_regs[i][0], 0x4);
205 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
206 b43_phy_set(dev, ctl_regs[i][0], 0x1);
207 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
208 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
209 }
210}
211
c750f795
RM		 212static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
213{
214 u8 i;
215
216 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
217 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
218
219 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
220 for (i = 0; i < 200; i++) {
221 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
222 i = 0;
223 break;
224 }
225 msleep(1);
226 }
227 if (i)
228 b43err(dev->wl, "Forcing RF sequence timeout\n");
229
230 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
231}
232
ea5a08cf
RM		 233static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
234{
235 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
236 clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
237 clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
238}
239
b5058348
RM		 240static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
241{
242 unsigned int i;
243 u16 val;
244
245 val = 0x1E1F;
246 for (i = 0; i < 16; i++) {
247 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
248 val -= 0x202;
249 }
250 val = 0x3E3F;
251 for (i = 0; i < 16; i++) {
252 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
253 val -= 0x202;
254 }
255 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
256}
257
f6099f89
RM		 258/**************************************************
259 * Tx/Rx
260 **************************************************/
261
262static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
263{
264 int i;
265
266 for (i = 0; i < 3; i++) {
267 u16 mask;
268 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
269
270 if (0) /* FIXME */
271 mask = 0x2 << (i * 4);
272 else
273 mask = 0;
274 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
275
276 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
277 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
278 tmp & 0xFF);
279 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
280 tmp & 0xFF);
281 }
282}
283
3e644ab4
RM		 284/**************************************************
285 * Channel switching ops.
286 **************************************************/
287
39ca554c
RM		 288static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
289 const struct b43_phy_ht_channeltab_e_phy *e,
290 struct ieee80211_channel *new_channel)
291{
bdb2dfb2
RM		 292 bool old_band_5ghz;
293
294 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
295 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
296 /* TODO */
297 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
298 /* TODO */
299 }
300
301 b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
302 b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
303 b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
304 b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
305 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
306 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
e5b61007 307
b372afae
RM		 308 if (new_channel->hw_value == 14) {
309 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
310 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
311 } else {
312 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
313 B43_PHY_HT_CLASS_CTL_OFDM_EN);
314 if (new_channel->band == IEEE80211_BAND_2GHZ)
315 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
316 }
e5b61007 317
f6099f89
RM		 318 if (1) /* TODO: On N it's for early devices only, what about HT? */
319 b43_phy_ht_tx_power_fix(dev);
e5b61007
RM		 320
321 b43_phy_write(dev, 0x017e, 0x3830);
39ca554c
RM		 322}
323
324static int b43_phy_ht_set_channel(struct b43_wldev *dev,
325 struct ieee80211_channel *channel,
326 enum nl80211_channel_type channel_type)
327{
328 struct b43_phy *phy = &dev->phy;
329
330 const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
331
332 if (phy->radio_ver == 0x2059) {
333 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
334 channel->center_freq);
335 if (!chent_r2059)
336 return -ESRCH;
337 } else {
338 return -ESRCH;
339 }
340
341 /* TODO: In case of N-PHY some bandwidth switching goes here */
342
343 if (phy->radio_ver == 0x2059) {
344 b43_radio_2059_channel_setup(dev, chent_r2059);
345 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
346 channel);
347 } else {
348 return -ESRCH;
349 }
350
351 return 0;
352}
353
d7520b1d
RM		 354/**************************************************
355 * Basic PHY ops.
356 **************************************************/
357
358static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
359{
360 struct b43_phy_ht *phy_ht;
361
362 phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
363 if (!phy_ht)
364 return -ENOMEM;
365 dev->phy.ht = phy_ht;
366
367 return 0;
368}
369
370static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
371{
372 struct b43_phy *phy = &dev->phy;
373 struct b43_phy_ht *phy_ht = phy->ht;
374
375 memset(phy_ht, 0, sizeof(*phy_ht));
376}
377
2d02c86b
RM		 378static int b43_phy_ht_op_init(struct b43_wldev *dev)
379{
19240f36 380 u16 tmp;
ea5a08cf 381 u16 clip_state[3];
19240f36 382
7c2332b8
RM		 383 if (dev->dev->bus_type != B43_BUS_BCMA) {
384 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
385 return -EOPNOTSUPP;
386 }
387
2d02c86b
RM		 388 b43_phy_ht_tables_init(dev);
389
357e24d2
RM		 390 b43_phy_mask(dev, 0x0be, ~0x2);
391 b43_phy_set(dev, 0x23f, 0x7ff);
392 b43_phy_set(dev, 0x240, 0x7ff);
393 b43_phy_set(dev, 0x241, 0x7ff);
15222b58
RM		 394
395 b43_phy_ht_zero_extg(dev);
396
357e24d2 397 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
f457f184 398
47606922
RM		 399 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
400 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
401 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
f457f184
RM		 402
403 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
404 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
405 b43_phy_write(dev, 0x20d, 0xb8);
406 b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
407 b43_phy_write(dev, 0x70, 0x50);
408 b43_phy_write(dev, 0x1ff, 0x30);
409
410 if (0) /* TODO: condition */
411 ; /* TODO: PHY op on reg 0x217 */
412
b372afae
RM		 413 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
414 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
415 else
416 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
417 B43_PHY_HT_CLASS_CTL_CCK_EN);
f457f184 418
357e24d2
RM		 419 b43_phy_set(dev, 0xb1, 0x91);
420 b43_phy_write(dev, 0x32f, 0x0003);
421 b43_phy_write(dev, 0x077, 0x0010);
422 b43_phy_write(dev, 0x0b4, 0x0258);
423 b43_phy_mask(dev, 0x17e, ~0x4000);
f457f184
RM		 424
425 b43_phy_write(dev, 0x0b9, 0x0072);
426
98f8dc72
RM		 427 b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
428 b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
429 b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
19240f36 430
a4042bb0
RM		 431 b43_phy_ht_afe_unk1(dev);
432
98f8dc72
RM		 433 b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
434 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
435
436 b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
437 b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
438
439 b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
440 b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
441 b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
442
443 b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
444 0x8e, 0x96, 0x96, 0x96);
445 b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
446 0x8f, 0x9f, 0x9f, 0x9f);
447 b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
448 0x8f, 0x9f, 0x9f, 0x9f);
449
450 b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
451 b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
452 b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
a4042bb0 453
357e24d2
RM		 454 b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
455 b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
456 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
457 b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
458
98f8dc72
RM		 459 b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
460 0x09, 0x0e, 0x13, 0x18);
461 b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
462 0x09, 0x0e, 0x13, 0x18);
463 /* TODO: Did wl mean 2 instead of 40? */
464 b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
465 0x09, 0x0e, 0x13, 0x18);
357e24d2
RM		 466
467 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
468 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
469 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
470
471 b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
472 b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
473 b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
474 b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
475
19240f36
RM		 476 /* Copy some tables entries */
477 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
478 b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
479 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
480 b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
481 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
482 b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
483
484 /* Reset CCA */
485 b43_phy_force_clock(dev, true);
486 tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
487 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
488 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
489 b43_phy_force_clock(dev, false);
490
491 b43_mac_phy_clock_set(dev, true);
492
c750f795
RM		 493 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
494 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
357e24d2 495
ea5a08cf 496 /* TODO: Should we restore it? Or store it in global PHY info? */
b372afae 497 b43_phy_ht_classifier(dev, 0, 0);
ea5a08cf 498 b43_phy_ht_read_clip_detection(dev, clip_state);
b5058348
RM		 499
500 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
501 b43_phy_ht_bphy_init(dev);
502
503 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
504 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
505
2d02c86b
RM		 506 return 0;
507}
508
d7520b1d
RM		 509static void b43_phy_ht_op_free(struct b43_wldev *dev)
510{
511 struct b43_phy *phy = &dev->phy;
512 struct b43_phy_ht *phy_ht = phy->ht;
513
514 kfree(phy_ht);
515 phy->ht = NULL;
516}
517
e7c62552
RM		 518/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
519static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
520 bool blocked)
521{
522 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
523 b43err(dev->wl, "MAC not suspended\n");
524
0b5dd734
RM		 525 /* In the following PHY ops we copy wl's dummy behaviour.
526 * TODO: Find out if reads (currently hidden in masks/masksets) are
527 * needed and replace following ops with just writes or w&r.
528 * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
529 * cause delayed (!) machine lock up. */
e7c62552 530 if (blocked) {
0b5dd734 531 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
e7c62552 532 } else {
0b5dd734
RM		 533 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
534 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
535 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
536 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
3e644ab4
RM		 537
538 if (dev->phy.radio_ver == 0x2059)
539 b43_radio_2059_init(dev);
540 else
541 B43_WARN_ON(1);
315a685f
RM		 542
543 b43_switch_channel(dev, dev->phy.channel);
e7c62552
RM		 544 }
545}
546
a8e82749
RM		 547static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
548{
549 if (on) {
47606922
RM		 550 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
551 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
552 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
553 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
554 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
555 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
a8e82749 556 } else {
47606922
RM		 557 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
558 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
559 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
560 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
561 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
562 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
a8e82749
RM		 563 }
564}
565
39ca554c
RM		 566static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
567 unsigned int new_channel)
568{
569 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
570 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
571
572 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
573 if ((new_channel < 1) || (new_channel > 14))
574 return -EINVAL;
575 } else {
576 return -EINVAL;
577 }
578
579 return b43_phy_ht_set_channel(dev, channel, channel_type);
580}
581
d7520b1d
RM		 582static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
583{
584 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
315a685f 585 return 11;
d7520b1d
RM		 586 return 36;
587}
588
589/**************************************************
590 * R/W ops.
591 **************************************************/
592
593static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
594{
595 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
596 return b43_read16(dev, B43_MMIO_PHY_DATA);
597}
598
599static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
600{
601 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
602 b43_write16(dev, B43_MMIO_PHY_DATA, value);
603}
604
605static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
606 u16 set)
607{
608 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
609 b43_write16(dev, B43_MMIO_PHY_DATA,
610 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
611}
612
4cabd425
RM		 613static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
614{
615 /* HT-PHY needs 0x200 for read access */
616 reg |= 0x200;
617
618 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
619 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
620}
621
622static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
623 u16 value)
624{
625 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
626 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
627}
628
21a18f28
RM		 629static enum b43_txpwr_result
630b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
631{
632 return B43_TXPWR_RES_DONE;
633}
634
635static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
636{
637}
638
d7520b1d
RM		 639/**************************************************
640 * PHY ops struct.
641 **************************************************/
642
643const struct b43_phy_operations b43_phyops_ht = {
644 .allocate = b43_phy_ht_op_allocate,
645 .free = b43_phy_ht_op_free,
646 .prepare_structs = b43_phy_ht_op_prepare_structs,
d7520b1d 647 .init = b43_phy_ht_op_init,
d7520b1d
RM		 648 .phy_read = b43_phy_ht_op_read,
649 .phy_write = b43_phy_ht_op_write,
650 .phy_maskset = b43_phy_ht_op_maskset,
d7520b1d
RM		 651 .radio_read = b43_phy_ht_op_radio_read,
652 .radio_write = b43_phy_ht_op_radio_write,
653 .software_rfkill = b43_phy_ht_op_software_rfkill,
654 .switch_analog = b43_phy_ht_op_switch_analog,
655 .switch_channel = b43_phy_ht_op_switch_channel,
d7520b1d 656 .get_default_chan = b43_phy_ht_op_get_default_chan,
d7520b1d
RM		 657 .recalc_txpower = b43_phy_ht_op_recalc_txpower,
658 .adjust_txpower = b43_phy_ht_op_adjust_txpower,
d7520b1d 659};
Linux 6.x block layer and io_uring tree(s)