projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
b43: HT-PHY: implement controlling TX power control
[linux-2.6-block.git] / drivers / net / wireless / b43 / phy_ht.c
CommitLineData
d7520b1d
RM		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n HT-PHY support
5
108f4f3c
RM		 6 Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
7
d7520b1d
RM		 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
25#include <linux/slab.h>
26
27#include "b43.h"
28#include "phy_ht.h"
e5b61007 29#include "tables_phy_ht.h"
5192bf56 30#include "radio_2059.h"
d7520b1d
RM		 31#include "main.h"
32
3e644ab4
RM		 33/**************************************************
34 * Radio 2059.
35 **************************************************/
36
39ca554c
RM		 37static void b43_radio_2059_channel_setup(struct b43_wldev *dev,
38 const struct b43_phy_ht_channeltab_e_radio2059 *e)
39{
a6b7da5d
RM		 40 u8 i;
41 u16 routing;
42
43 b43_radio_write(dev, 0x16, e->radio_syn16);
44 b43_radio_write(dev, 0x17, e->radio_syn17);
45 b43_radio_write(dev, 0x22, e->radio_syn22);
46 b43_radio_write(dev, 0x25, e->radio_syn25);
47 b43_radio_write(dev, 0x27, e->radio_syn27);
48 b43_radio_write(dev, 0x28, e->radio_syn28);
49 b43_radio_write(dev, 0x29, e->radio_syn29);
50 b43_radio_write(dev, 0x2c, e->radio_syn2c);
51 b43_radio_write(dev, 0x2d, e->radio_syn2d);
52 b43_radio_write(dev, 0x37, e->radio_syn37);
53 b43_radio_write(dev, 0x41, e->radio_syn41);
54 b43_radio_write(dev, 0x43, e->radio_syn43);
55 b43_radio_write(dev, 0x47, e->radio_syn47);
56 b43_radio_write(dev, 0x4a, e->radio_syn4a);
57 b43_radio_write(dev, 0x58, e->radio_syn58);
58 b43_radio_write(dev, 0x5a, e->radio_syn5a);
59 b43_radio_write(dev, 0x6a, e->radio_syn6a);
60 b43_radio_write(dev, 0x6d, e->radio_syn6d);
61 b43_radio_write(dev, 0x6e, e->radio_syn6e);
62 b43_radio_write(dev, 0x92, e->radio_syn92);
63 b43_radio_write(dev, 0x98, e->radio_syn98);
64
65 for (i = 0; i < 2; i++) {
e8dec1e9 66 routing = i ? R2059_RXRX1 : R2059_TXRX0;
a6b7da5d
RM		 67 b43_radio_write(dev, routing | 0x4a, e->radio_rxtx4a);
68 b43_radio_write(dev, routing | 0x58, e->radio_rxtx58);
69 b43_radio_write(dev, routing | 0x5a, e->radio_rxtx5a);
70 b43_radio_write(dev, routing | 0x6a, e->radio_rxtx6a);
71 b43_radio_write(dev, routing | 0x6d, e->radio_rxtx6d);
72 b43_radio_write(dev, routing | 0x6e, e->radio_rxtx6e);
73 b43_radio_write(dev, routing | 0x92, e->radio_rxtx92);
74 b43_radio_write(dev, routing | 0x98, e->radio_rxtx98);
75 }
76
77 udelay(50);
78
c1c3daee
RM		 79 /* Calibration */
80 b43_radio_mask(dev, 0x2b, ~0x1);
81 b43_radio_mask(dev, 0x2e, ~0x4);
82 b43_radio_set(dev, 0x2e, 0x4);
83 b43_radio_set(dev, 0x2b, 0x1);
84
85 udelay(300);
39ca554c
RM		 86}
87
3e644ab4
RM		 88static void b43_radio_2059_init(struct b43_wldev *dev)
89{
90 const u16 routing[] = { R2059_SYN, R2059_TXRX0, R2059_RXRX1 };
a5f377fb
RM		 91 const u16 radio_values[3][2] = {
92 { 0x61, 0xE9 }, { 0x69, 0xD5 }, { 0x73, 0x99 },
93 };
94 u16 i, j;
3e644ab4
RM		 95
96 b43_radio_write(dev, R2059_ALL | 0x51, 0x0070);
97 b43_radio_write(dev, R2059_ALL | 0x5a, 0x0003);
98
99 for (i = 0; i < ARRAY_SIZE(routing); i++)
100 b43_radio_set(dev, routing[i] | 0x146, 0x3);
101
102 b43_radio_set(dev, 0x2e, 0x0078);
103 b43_radio_set(dev, 0xc0, 0x0080);
104 msleep(2);
105 b43_radio_mask(dev, 0x2e, ~0x0078);
106 b43_radio_mask(dev, 0xc0, ~0x0080);
107
a5f377fb
RM		 108 if (1) { /* FIXME */
109 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x1);
110 udelay(10);
111 b43_radio_set(dev, R2059_RXRX1 | 0x0BF, 0x1);
112 b43_radio_maskset(dev, R2059_RXRX1 | 0x19B, 0x3, 0x2);
113
114 b43_radio_set(dev, R2059_RXRX1 | 0x4, 0x2);
115 udelay(100);
116 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x2);
117
118 for (i = 0; i < 10000; i++) {
119 if (b43_radio_read(dev, R2059_RXRX1 | 0x145) & 1) {
120 i = 0;
121 break;
122 }
123 udelay(100);
124 }
125 if (i)
126 b43err(dev->wl, "radio 0x945 timeout\n");
127
128 b43_radio_mask(dev, R2059_RXRX1 | 0x4, ~0x1);
129 b43_radio_set(dev, 0xa, 0x60);
130
131 for (i = 0; i < 3; i++) {
132 b43_radio_write(dev, 0x17F, radio_values[i][0]);
133 b43_radio_write(dev, 0x13D, 0x6E);
134 b43_radio_write(dev, 0x13E, radio_values[i][1]);
135 b43_radio_write(dev, 0x13C, 0x55);
136
137 for (j = 0; j < 10000; j++) {
138 if (b43_radio_read(dev, 0x140) & 2) {
139 j = 0;
140 break;
141 }
142 udelay(500);
143 }
144 if (j)
145 b43err(dev->wl, "radio 0x140 timeout\n");
146
147 b43_radio_write(dev, 0x13C, 0x15);
148 }
149
150 b43_radio_mask(dev, 0x17F, ~0x1);
151 }
152
b473bc17 153 b43_radio_mask(dev, 0x11, ~0x0008);
3e644ab4
RM		 154}
155
4cce0956
RM		 156/**************************************************
157 * RF
158 **************************************************/
159
160static void b43_phy_ht_force_rf_sequence(struct b43_wldev *dev, u16 rf_seq)
161{
162 u8 i;
163
164 u16 save_seq_mode = b43_phy_read(dev, B43_PHY_HT_RF_SEQ_MODE);
165 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_MODE, 0x3);
166
167 b43_phy_set(dev, B43_PHY_HT_RF_SEQ_TRIG, rf_seq);
168 for (i = 0; i < 200; i++) {
169 if (!(b43_phy_read(dev, B43_PHY_HT_RF_SEQ_STATUS) & rf_seq)) {
170 i = 0;
171 break;
172 }
173 msleep(1);
174 }
175 if (i)
176 b43err(dev->wl, "Forcing RF sequence timeout\n");
177
178 b43_phy_write(dev, B43_PHY_HT_RF_SEQ_MODE, save_seq_mode);
179}
180
a51ab258
RM		 181static void b43_phy_ht_pa_override(struct b43_wldev *dev, bool enable)
182{
183 struct b43_phy_ht *htphy = dev->phy.ht;
184 static const u16 regs[3] = { B43_PHY_HT_RF_CTL_INT_C1,
185 B43_PHY_HT_RF_CTL_INT_C2,
186 B43_PHY_HT_RF_CTL_INT_C3 };
187 int i;
188
189 if (enable) {
190 for (i = 0; i < 3; i++)
191 b43_phy_write(dev, regs[i], htphy->rf_ctl_int_save[i]);
192 } else {
193 for (i = 0; i < 3; i++)
194 htphy->rf_ctl_int_save[i] = b43_phy_read(dev, regs[i]);
195 /* TODO: Does 5GHz band use different value (not 0x0400)? */
196 for (i = 0; i < 3; i++)
197 b43_phy_write(dev, regs[i], 0x0400);
198 }
199}
200
15222b58
RM		 201/**************************************************
202 * Various PHY ops
203 **************************************************/
204
b372afae
RM		 205static u16 b43_phy_ht_classifier(struct b43_wldev *dev, u16 mask, u16 val)
206{
207 u16 tmp;
208 u16 allowed = B43_PHY_HT_CLASS_CTL_CCK_EN |
209 B43_PHY_HT_CLASS_CTL_OFDM_EN |
210 B43_PHY_HT_CLASS_CTL_WAITED_EN;
211
212 tmp = b43_phy_read(dev, B43_PHY_HT_CLASS_CTL);
213 tmp &= allowed;
214 tmp &= ~mask;
215 tmp |= (val & mask);
216 b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);
217
218 return tmp;
219}
220
4cce0956
RM		 221static void b43_phy_ht_reset_cca(struct b43_wldev *dev)
222{
223 u16 bbcfg;
224
225 b43_phy_force_clock(dev, true);
226 bbcfg = b43_phy_read(dev, B43_PHY_HT_BBCFG);
227 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg | B43_PHY_HT_BBCFG_RSTCCA);
228 udelay(1);
229 b43_phy_write(dev, B43_PHY_HT_BBCFG, bbcfg & ~B43_PHY_HT_BBCFG_RSTCCA);
230 b43_phy_force_clock(dev, false);
231
232 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
233}
234
15222b58
RM		 235static void b43_phy_ht_zero_extg(struct b43_wldev *dev)
236{
237 u8 i, j;
238 u16 base[] = { 0x40, 0x60, 0x80 };
239
240 for (i = 0; i < ARRAY_SIZE(base); i++) {
241 for (j = 0; j < 4; j++)
242 b43_phy_write(dev, B43_PHY_EXTG(base[i] + j), 0);
243 }
244
245 for (i = 0; i < ARRAY_SIZE(base); i++)
246 b43_phy_write(dev, B43_PHY_EXTG(base[i] + 0xc), 0);
247}
248
a4042bb0
RM		 249/* Some unknown AFE (Analog Frondned) op */
250static void b43_phy_ht_afe_unk1(struct b43_wldev *dev)
251{
252 u8 i;
253
47606922
RM		 254 static const u16 ctl_regs[3][2] = {
255 { B43_PHY_HT_AFE_C1_OVER, B43_PHY_HT_AFE_C1 },
256 { B43_PHY_HT_AFE_C2_OVER, B43_PHY_HT_AFE_C2 },
257 { B43_PHY_HT_AFE_C3_OVER, B43_PHY_HT_AFE_C3},
a4042bb0
RM		 258 };
259
260 for (i = 0; i < 3; i++) {
261 /* TODO: verify masks&sets */
262 b43_phy_set(dev, ctl_regs[i][1], 0x4);
263 b43_phy_set(dev, ctl_regs[i][0], 0x4);
264 b43_phy_mask(dev, ctl_regs[i][1], ~0x1);
265 b43_phy_set(dev, ctl_regs[i][0], 0x1);
266 b43_httab_write(dev, B43_HTTAB16(8, 5 + (i * 0x10)), 0);
267 b43_phy_mask(dev, ctl_regs[i][0], ~0x4);
268 }
269}
270
ea5a08cf
RM		 271static void b43_phy_ht_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
272{
273 clip_st[0] = b43_phy_read(dev, B43_PHY_HT_C1_CLIP1THRES);
274 clip_st[1] = b43_phy_read(dev, B43_PHY_HT_C2_CLIP1THRES);
275 clip_st[2] = b43_phy_read(dev, B43_PHY_HT_C3_CLIP1THRES);
276}
277
b5058348
RM		 278static void b43_phy_ht_bphy_init(struct b43_wldev *dev)
279{
280 unsigned int i;
281 u16 val;
282
283 val = 0x1E1F;
284 for (i = 0; i < 16; i++) {
285 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
286 val -= 0x202;
287 }
288 val = 0x3E3F;
289 for (i = 0; i < 16; i++) {
290 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
291 val -= 0x202;
292 }
293 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
294}
295
f6099f89
RM		 296/**************************************************
297 * Tx/Rx
298 **************************************************/
299
300static void b43_phy_ht_tx_power_fix(struct b43_wldev *dev)
301{
302 int i;
303
304 for (i = 0; i < 3; i++) {
305 u16 mask;
306 u32 tmp = b43_httab_read(dev, B43_HTTAB32(26, 0xE8));
307
308 if (0) /* FIXME */
309 mask = 0x2 << (i * 4);
310 else
311 mask = 0;
312 b43_phy_mask(dev, B43_PHY_EXTG(0x108), mask);
313
314 b43_httab_write(dev, B43_HTTAB16(7, 0x110 + i), tmp >> 16);
315 b43_httab_write(dev, B43_HTTAB8(13, 0x63 + (i * 4)),
316 tmp & 0xFF);
317 b43_httab_write(dev, B43_HTTAB8(13, 0x73 + (i * 4)),
318 tmp & 0xFF);
319 }
320}
321
60e8fb92
RM		 322#if 0
323static void b43_phy_ht_tx_power_ctl(struct b43_wldev *dev, bool enable)
324{
325 struct b43_phy_ht *phy_ht = dev->phy.ht;
326 u16 en_bits = B43_PHY_HT_TXPCTL_CMD_C1_COEFF |
327 B43_PHY_HT_TXPCTL_CMD_C1_HWPCTLEN |
328 B43_PHY_HT_TXPCTL_CMD_C1_PCTLEN;
329 static const u16 cmd_regs[3] = { B43_PHY_HT_TXPCTL_CMD_C1,
330 B43_PHY_HT_TXPCTL_CMD_C2,
331 B43_PHY_HT_TXPCTL_CMD_C3 };
332 int i;
333
334 if (!enable) {
335 if (b43_phy_read(dev, B43_PHY_HT_TXPCTL_CMD_C1) & en_bits) {
336 /* We disable enabled TX pwr ctl, save it's state */
337 /*
338 * TODO: find the registers. On N-PHY they were 0x1ed
339 * and 0x1ee, we need 3 such a registers for HT-PHY
340 */
341 }
342 b43_phy_mask(dev, B43_PHY_HT_TXPCTL_CMD_C1, ~en_bits);
343 } else {
344 b43_phy_set(dev, B43_PHY_HT_TXPCTL_CMD_C1, en_bits);
345
346 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
347 for (i = 0; i < 3; i++)
348 b43_phy_write(dev, cmd_regs[i], 0x32);
349 }
350
351 for (i = 0; i < 3; i++)
352 if (phy_ht->tx_pwr_idx[i] <=
353 B43_PHY_HT_TXPCTL_CMD_C1_INIT)
354 b43_phy_write(dev, cmd_regs[i],
355 phy_ht->tx_pwr_idx[i]);
356 }
357
358 phy_ht->tx_pwr_ctl = enable;
359}
360#endif
361
3e644ab4
RM		 362/**************************************************
363 * Channel switching ops.
364 **************************************************/
365
2dacfe7c
RM		 366static void b43_phy_ht_spur_avoid(struct b43_wldev *dev,
367 struct ieee80211_channel *new_channel)
368{
369 struct bcma_device *core = dev->dev->bdev;
370 int spuravoid = 0;
d7bb7ca8 371 u16 tmp;
2dacfe7c
RM		 372
373 /* Check for 13 and 14 is just a guess, we don't have enough logs. */
374 if (new_channel->hw_value == 13 || new_channel->hw_value == 14)
375 spuravoid = 1;
376 bcma_core_pll_ctl(core, B43_BCMA_CLKCTLST_PHY_PLL_REQ, 0, false);
377 bcma_pmu_spuravoid_pllupdate(&core->bus->drv_cc, spuravoid);
378 bcma_core_pll_ctl(core,
379 B43_BCMA_CLKCTLST_80211_PLL_REQ |
380 B43_BCMA_CLKCTLST_PHY_PLL_REQ,
381 B43_BCMA_CLKCTLST_80211_PLL_ST |
382 B43_BCMA_CLKCTLST_PHY_PLL_ST, false);
d7bb7ca8
RM		 383
384 /* Values has been taken from wlc_bmac_switch_macfreq comments */
385 switch (spuravoid) {
386 case 2: /* 126MHz */
387 tmp = 0x2082;
388 break;
389 case 1: /* 123MHz */
390 tmp = 0x5341;
391 break;
392 default: /* 120MHz */
393 tmp = 0x8889;
394 }
395
396 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW, tmp);
397 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
398
399 /* TODO: reset PLL */
4cce0956
RM		 400
401 if (spuravoid)
402 b43_phy_set(dev, B43_PHY_HT_BBCFG, B43_PHY_HT_BBCFG_RSTRX);
403 else
404 b43_phy_mask(dev, B43_PHY_HT_BBCFG,
405 ~B43_PHY_HT_BBCFG_RSTRX & 0xFFFF);
406
407 b43_phy_ht_reset_cca(dev);
2dacfe7c
RM		 408}
409
39ca554c
RM		 410static void b43_phy_ht_channel_setup(struct b43_wldev *dev,
411 const struct b43_phy_ht_channeltab_e_phy *e,
412 struct ieee80211_channel *new_channel)
413{
bdb2dfb2
RM		 414 bool old_band_5ghz;
415
416 old_band_5ghz = b43_phy_read(dev, B43_PHY_HT_BANDCTL) & 0; /* FIXME */
417 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
418 /* TODO */
419 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
420 /* TODO */
421 }
422
423 b43_phy_write(dev, B43_PHY_HT_BW1, e->bw1);
424 b43_phy_write(dev, B43_PHY_HT_BW2, e->bw2);
425 b43_phy_write(dev, B43_PHY_HT_BW3, e->bw3);
426 b43_phy_write(dev, B43_PHY_HT_BW4, e->bw4);
427 b43_phy_write(dev, B43_PHY_HT_BW5, e->bw5);
428 b43_phy_write(dev, B43_PHY_HT_BW6, e->bw6);
e5b61007 429
b372afae
RM		 430 if (new_channel->hw_value == 14) {
431 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN, 0);
432 b43_phy_set(dev, B43_PHY_HT_TEST, 0x0800);
433 } else {
434 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_OFDM_EN,
435 B43_PHY_HT_CLASS_CTL_OFDM_EN);
436 if (new_channel->band == IEEE80211_BAND_2GHZ)
437 b43_phy_mask(dev, B43_PHY_HT_TEST, ~0x840);
438 }
e5b61007 439
f6099f89
RM		 440 if (1) /* TODO: On N it's for early devices only, what about HT? */
441 b43_phy_ht_tx_power_fix(dev);
e5b61007 442
2dacfe7c
RM		 443 b43_phy_ht_spur_avoid(dev, new_channel);
444
e5b61007 445 b43_phy_write(dev, 0x017e, 0x3830);
39ca554c
RM		 446}
447
448static int b43_phy_ht_set_channel(struct b43_wldev *dev,
449 struct ieee80211_channel *channel,
450 enum nl80211_channel_type channel_type)
451{
452 struct b43_phy *phy = &dev->phy;
453
454 const struct b43_phy_ht_channeltab_e_radio2059 *chent_r2059 = NULL;
455
456 if (phy->radio_ver == 0x2059) {
457 chent_r2059 = b43_phy_ht_get_channeltab_e_r2059(dev,
458 channel->center_freq);
459 if (!chent_r2059)
460 return -ESRCH;
461 } else {
462 return -ESRCH;
463 }
464
465 /* TODO: In case of N-PHY some bandwidth switching goes here */
466
467 if (phy->radio_ver == 0x2059) {
468 b43_radio_2059_channel_setup(dev, chent_r2059);
469 b43_phy_ht_channel_setup(dev, &(chent_r2059->phy_regs),
470 channel);
471 } else {
472 return -ESRCH;
473 }
474
475 return 0;
476}
477
d7520b1d
RM		 478/**************************************************
479 * Basic PHY ops.
480 **************************************************/
481
482static int b43_phy_ht_op_allocate(struct b43_wldev *dev)
483{
484 struct b43_phy_ht *phy_ht;
485
486 phy_ht = kzalloc(sizeof(*phy_ht), GFP_KERNEL);
487 if (!phy_ht)
488 return -ENOMEM;
489 dev->phy.ht = phy_ht;
490
491 return 0;
492}
493
494static void b43_phy_ht_op_prepare_structs(struct b43_wldev *dev)
495{
496 struct b43_phy *phy = &dev->phy;
497 struct b43_phy_ht *phy_ht = phy->ht;
60e8fb92 498 int i;
d7520b1d
RM		 499
500 memset(phy_ht, 0, sizeof(*phy_ht));
60e8fb92
RM		 501
502 phy_ht->tx_pwr_ctl = true;
503 for (i = 0; i < 3; i++)
504 phy_ht->tx_pwr_idx[i] = B43_PHY_HT_TXPCTL_CMD_C1_INIT + 1;
d7520b1d
RM		 505}
506
2d02c86b
RM		 507static int b43_phy_ht_op_init(struct b43_wldev *dev)
508{
60e8fb92 509 struct b43_phy_ht *phy_ht = dev->phy.ht;
19240f36 510 u16 tmp;
ea5a08cf 511 u16 clip_state[3];
60e8fb92 512 bool saved_tx_pwr_ctl;
19240f36 513
7c2332b8
RM		 514 if (dev->dev->bus_type != B43_BUS_BCMA) {
515 b43err(dev->wl, "HT-PHY is supported only on BCMA bus!\n");
516 return -EOPNOTSUPP;
517 }
518
2d02c86b
RM		 519 b43_phy_ht_tables_init(dev);
520
357e24d2
RM		 521 b43_phy_mask(dev, 0x0be, ~0x2);
522 b43_phy_set(dev, 0x23f, 0x7ff);
523 b43_phy_set(dev, 0x240, 0x7ff);
524 b43_phy_set(dev, 0x241, 0x7ff);
15222b58
RM		 525
526 b43_phy_ht_zero_extg(dev);
527
357e24d2 528 b43_phy_mask(dev, B43_PHY_EXTG(0), ~0x3);
f457f184 529
47606922
RM		 530 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0);
531 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0);
532 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0);
f457f184
RM		 533
534 b43_phy_write(dev, B43_PHY_EXTG(0x103), 0x20);
535 b43_phy_write(dev, B43_PHY_EXTG(0x101), 0x20);
536 b43_phy_write(dev, 0x20d, 0xb8);
537 b43_phy_write(dev, B43_PHY_EXTG(0x14f), 0xc8);
538 b43_phy_write(dev, 0x70, 0x50);
539 b43_phy_write(dev, 0x1ff, 0x30);
540
541 if (0) /* TODO: condition */
542 ; /* TODO: PHY op on reg 0x217 */
543
b372afae
RM		 544 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
545 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN, 0);
546 else
547 b43_phy_ht_classifier(dev, B43_PHY_HT_CLASS_CTL_CCK_EN,
548 B43_PHY_HT_CLASS_CTL_CCK_EN);
f457f184 549
357e24d2
RM		 550 b43_phy_set(dev, 0xb1, 0x91);
551 b43_phy_write(dev, 0x32f, 0x0003);
552 b43_phy_write(dev, 0x077, 0x0010);
553 b43_phy_write(dev, 0x0b4, 0x0258);
554 b43_phy_mask(dev, 0x17e, ~0x4000);
f457f184
RM		 555
556 b43_phy_write(dev, 0x0b9, 0x0072);
557
98f8dc72
RM		 558 b43_httab_write_few(dev, B43_HTTAB16(7, 0x14e), 2, 0x010f, 0x010f);
559 b43_httab_write_few(dev, B43_HTTAB16(7, 0x15e), 2, 0x010f, 0x010f);
560 b43_httab_write_few(dev, B43_HTTAB16(7, 0x16e), 2, 0x010f, 0x010f);
19240f36 561
a4042bb0
RM		 562 b43_phy_ht_afe_unk1(dev);
563
98f8dc72
RM		 564 b43_httab_write_few(dev, B43_HTTAB16(7, 0x130), 9, 0x777, 0x111, 0x111,
565 0x777, 0x111, 0x111, 0x777, 0x111, 0x111);
566
567 b43_httab_write(dev, B43_HTTAB16(7, 0x120), 0x0777);
568 b43_httab_write(dev, B43_HTTAB16(7, 0x124), 0x0777);
569
570 b43_httab_write(dev, B43_HTTAB16(8, 0x00), 0x02);
571 b43_httab_write(dev, B43_HTTAB16(8, 0x10), 0x02);
572 b43_httab_write(dev, B43_HTTAB16(8, 0x20), 0x02);
573
574 b43_httab_write_few(dev, B43_HTTAB16(8, 0x08), 4,
575 0x8e, 0x96, 0x96, 0x96);
576 b43_httab_write_few(dev, B43_HTTAB16(8, 0x18), 4,
577 0x8f, 0x9f, 0x9f, 0x9f);
578 b43_httab_write_few(dev, B43_HTTAB16(8, 0x28), 4,
579 0x8f, 0x9f, 0x9f, 0x9f);
580
581 b43_httab_write_few(dev, B43_HTTAB16(8, 0x0c), 4, 0x2, 0x2, 0x2, 0x2);
582 b43_httab_write_few(dev, B43_HTTAB16(8, 0x1c), 4, 0x2, 0x2, 0x2, 0x2);
583 b43_httab_write_few(dev, B43_HTTAB16(8, 0x2c), 4, 0x2, 0x2, 0x2, 0x2);
a4042bb0 584
357e24d2
RM		 585 b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);
586 b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);
587 b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);
588 b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);
589
98f8dc72
RM		 590 b43_httab_write_few(dev, B43_HTTAB16(00, 0x8), 4,
591 0x09, 0x0e, 0x13, 0x18);
592 b43_httab_write_few(dev, B43_HTTAB16(01, 0x8), 4,
593 0x09, 0x0e, 0x13, 0x18);
594 /* TODO: Did wl mean 2 instead of 40? */
595 b43_httab_write_few(dev, B43_HTTAB16(40, 0x8), 4,
596 0x09, 0x0e, 0x13, 0x18);
357e24d2
RM		 597
598 b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);
599 b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);
600 b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);
601
602 b43_phy_set(dev, B43_PHY_EXTG(0x060), 0x1);
603 b43_phy_set(dev, B43_PHY_EXTG(0x064), 0x1);
604 b43_phy_set(dev, B43_PHY_EXTG(0x080), 0x1);
605 b43_phy_set(dev, B43_PHY_EXTG(0x084), 0x1);
606
19240f36
RM		 607 /* Copy some tables entries */
608 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x144));
609 b43_httab_write(dev, B43_HTTAB16(7, 0x14a), tmp);
610 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x154));
611 b43_httab_write(dev, B43_HTTAB16(7, 0x15a), tmp);
612 tmp = b43_httab_read(dev, B43_HTTAB16(7, 0x164));
613 b43_httab_write(dev, B43_HTTAB16(7, 0x16a), tmp);
614
615 /* Reset CCA */
616 b43_phy_force_clock(dev, true);
617 tmp = b43_phy_read(dev, B43_PHY_HT_BBCFG);
618 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp | B43_PHY_HT_BBCFG_RSTCCA);
619 b43_phy_write(dev, B43_PHY_HT_BBCFG, tmp & ~B43_PHY_HT_BBCFG_RSTCCA);
620 b43_phy_force_clock(dev, false);
621
622 b43_mac_phy_clock_set(dev, true);
623
a51ab258 624 b43_phy_ht_pa_override(dev, false);
c750f795
RM		 625 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RX2TX);
626 b43_phy_ht_force_rf_sequence(dev, B43_PHY_HT_RF_SEQ_TRIG_RST2RX);
a51ab258 627 b43_phy_ht_pa_override(dev, true);
357e24d2 628
ea5a08cf 629 /* TODO: Should we restore it? Or store it in global PHY info? */
b372afae 630 b43_phy_ht_classifier(dev, 0, 0);
ea5a08cf 631 b43_phy_ht_read_clip_detection(dev, clip_state);
b5058348
RM		 632
633 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
634 b43_phy_ht_bphy_init(dev);
635
636 b43_httab_write_bulk(dev, B43_HTTAB32(0x1a, 0xc0),
637 B43_HTTAB_1A_C0_LATE_SIZE, b43_httab_0x1a_0xc0_late);
638
60e8fb92
RM		 639 saved_tx_pwr_ctl = phy_ht->tx_pwr_ctl;
640 b43_phy_ht_tx_power_fix(dev);
641#if 0
642 b43_phy_ht_tx_power_ctl(dev, false);
643 /* TODO */
644 b43_phy_ht_tx_power_ctl(dev, saved_tx_pwr_ctl);
645#endif
646
2d02c86b
RM		 647 return 0;
648}
649
d7520b1d
RM		 650static void b43_phy_ht_op_free(struct b43_wldev *dev)
651{
652 struct b43_phy *phy = &dev->phy;
653 struct b43_phy_ht *phy_ht = phy->ht;
654
655 kfree(phy_ht);
656 phy->ht = NULL;
657}
658
e7c62552
RM		 659/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
660static void b43_phy_ht_op_software_rfkill(struct b43_wldev *dev,
661 bool blocked)
662{
663 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
664 b43err(dev->wl, "MAC not suspended\n");
665
0b5dd734
RM		 666 /* In the following PHY ops we copy wl's dummy behaviour.
667 * TODO: Find out if reads (currently hidden in masks/masksets) are
668 * needed and replace following ops with just writes or w&r.
669 * Note: B43_PHY_HT_RF_CTL1 register is tricky, wrong operation can
670 * cause delayed (!) machine lock up. */
e7c62552 671 if (blocked) {
0b5dd734 672 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
e7c62552 673 } else {
0b5dd734
RM		 674 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
675 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x1);
676 b43_phy_mask(dev, B43_PHY_HT_RF_CTL1, 0);
677 b43_phy_maskset(dev, B43_PHY_HT_RF_CTL1, 0, 0x2);
3e644ab4
RM		 678
679 if (dev->phy.radio_ver == 0x2059)
680 b43_radio_2059_init(dev);
681 else
682 B43_WARN_ON(1);
315a685f
RM		 683
684 b43_switch_channel(dev, dev->phy.channel);
e7c62552
RM		 685 }
686}
687
a8e82749
RM		 688static void b43_phy_ht_op_switch_analog(struct b43_wldev *dev, bool on)
689{
690 if (on) {
47606922
RM		 691 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00cd);
692 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x0000);
693 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00cd);
694 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x0000);
695 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00cd);
696 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x0000);
a8e82749 697 } else {
47606922
RM		 698 b43_phy_write(dev, B43_PHY_HT_AFE_C1_OVER, 0x07ff);
699 b43_phy_write(dev, B43_PHY_HT_AFE_C1, 0x00fd);
700 b43_phy_write(dev, B43_PHY_HT_AFE_C2_OVER, 0x07ff);
701 b43_phy_write(dev, B43_PHY_HT_AFE_C2, 0x00fd);
702 b43_phy_write(dev, B43_PHY_HT_AFE_C3_OVER, 0x07ff);
703 b43_phy_write(dev, B43_PHY_HT_AFE_C3, 0x00fd);
a8e82749
RM		 704 }
705}
706
39ca554c
RM		 707static int b43_phy_ht_op_switch_channel(struct b43_wldev *dev,
708 unsigned int new_channel)
709{
710 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
711 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
712
713 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
714 if ((new_channel < 1) || (new_channel > 14))
715 return -EINVAL;
716 } else {
717 return -EINVAL;
718 }
719
720 return b43_phy_ht_set_channel(dev, channel, channel_type);
721}
722
d7520b1d
RM		 723static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
724{
725 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
315a685f 726 return 11;
d7520b1d
RM		 727 return 36;
728}
729
730/**************************************************
731 * R/W ops.
732 **************************************************/
733
734static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
735{
736 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
737 return b43_read16(dev, B43_MMIO_PHY_DATA);
738}
739
740static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
741{
742 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
743 b43_write16(dev, B43_MMIO_PHY_DATA, value);
744}
745
746static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
747 u16 set)
748{
749 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
750 b43_write16(dev, B43_MMIO_PHY_DATA,
751 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
752}
753
4cabd425
RM		 754static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
755{
756 /* HT-PHY needs 0x200 for read access */
757 reg |= 0x200;
758
759 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
760 return b43_read16(dev, B43_MMIO_RADIO24_DATA);
761}
762
763static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
764 u16 value)
765{
766 b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
767 b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
768}
769
21a18f28
RM		 770static enum b43_txpwr_result
771b43_phy_ht_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
772{
773 return B43_TXPWR_RES_DONE;
774}
775
776static void b43_phy_ht_op_adjust_txpower(struct b43_wldev *dev)
777{
778}
779
d7520b1d
RM		 780/**************************************************
781 * PHY ops struct.
782 **************************************************/
783
784const struct b43_phy_operations b43_phyops_ht = {
785 .allocate = b43_phy_ht_op_allocate,
786 .free = b43_phy_ht_op_free,
787 .prepare_structs = b43_phy_ht_op_prepare_structs,
d7520b1d 788 .init = b43_phy_ht_op_init,
d7520b1d
RM		 789 .phy_read = b43_phy_ht_op_read,
790 .phy_write = b43_phy_ht_op_write,
791 .phy_maskset = b43_phy_ht_op_maskset,
d7520b1d
RM		 792 .radio_read = b43_phy_ht_op_radio_read,
793 .radio_write = b43_phy_ht_op_radio_write,
794 .software_rfkill = b43_phy_ht_op_software_rfkill,
795 .switch_analog = b43_phy_ht_op_switch_analog,
796 .switch_channel = b43_phy_ht_op_switch_channel,
d7520b1d 797 .get_default_chan = b43_phy_ht_op_get_default_chan,
d7520b1d
RM		 798 .recalc_txpower = b43_phy_ht_op_recalc_txpower,
799 .adjust_txpower = b43_phy_ht_op_adjust_txpower,
d7520b1d 800};
Linux 6.x block layer and io_uring tree(s)