Commit | Line | Data |
---|---|---|
ef1a628d MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | Common PHY routines | |
5 | ||
6 | Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>, | |
7 | Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it> | |
eb032b98 | 8 | Copyright (c) 2005-2008 Michael Buesch <m@bues.ch> |
ef1a628d MB |
9 | Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org> |
10 | Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch> | |
11 | ||
12 | This program is free software; you can redistribute it and/or modify | |
13 | it under the terms of the GNU General Public License as published by | |
14 | the Free Software Foundation; either version 2 of the License, or | |
15 | (at your option) any later version. | |
16 | ||
17 | This program is distributed in the hope that it will be useful, | |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
23 | along with this program; see the file COPYING. If not, write to | |
24 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
25 | Boston, MA 02110-1301, USA. | |
26 | ||
27 | */ | |
28 | ||
29 | #include "phy_common.h" | |
30 | #include "phy_g.h" | |
31 | #include "phy_a.h" | |
3d0da751 | 32 | #include "phy_n.h" |
e63e4363 | 33 | #include "phy_lp.h" |
d7520b1d | 34 | #include "phy_ht.h" |
58eb7ff3 | 35 | #include "phy_lcn.h" |
3f7bb3f3 | 36 | #include "phy_ac.h" |
ef1a628d MB |
37 | #include "b43.h" |
38 | #include "main.h" | |
39 | ||
40 | ||
fb11137a | 41 | int b43_phy_allocate(struct b43_wldev *dev) |
ef1a628d MB |
42 | { |
43 | struct b43_phy *phy = &(dev->phy); | |
44 | int err; | |
45 | ||
46 | phy->ops = NULL; | |
47 | ||
48 | switch (phy->type) { | |
ef1a628d | 49 | case B43_PHYTYPE_G: |
418378fe | 50 | #ifdef CONFIG_B43_PHY_G |
ef1a628d | 51 | phy->ops = &b43_phyops_g; |
418378fe | 52 | #endif |
ef1a628d MB |
53 | break; |
54 | case B43_PHYTYPE_N: | |
692d2c0f | 55 | #ifdef CONFIG_B43_PHY_N |
ef1a628d MB |
56 | phy->ops = &b43_phyops_n; |
57 | #endif | |
58 | break; | |
59 | case B43_PHYTYPE_LP: | |
e63e4363 MB |
60 | #ifdef CONFIG_B43_PHY_LP |
61 | phy->ops = &b43_phyops_lp; | |
d7520b1d RM |
62 | #endif |
63 | break; | |
64 | case B43_PHYTYPE_HT: | |
65 | #ifdef CONFIG_B43_PHY_HT | |
66 | phy->ops = &b43_phyops_ht; | |
58eb7ff3 RM |
67 | #endif |
68 | break; | |
69 | case B43_PHYTYPE_LCN: | |
70 | #ifdef CONFIG_B43_PHY_LCN | |
71 | phy->ops = &b43_phyops_lcn; | |
3f7bb3f3 RM |
72 | #endif |
73 | break; | |
74 | case B43_PHYTYPE_AC: | |
75 | #ifdef CONFIG_B43_PHY_AC | |
76 | phy->ops = &b43_phyops_ac; | |
e63e4363 | 77 | #endif |
ef1a628d MB |
78 | break; |
79 | } | |
80 | if (B43_WARN_ON(!phy->ops)) | |
81 | return -ENODEV; | |
82 | ||
83 | err = phy->ops->allocate(dev); | |
84 | if (err) | |
85 | phy->ops = NULL; | |
86 | ||
87 | return err; | |
88 | } | |
89 | ||
fb11137a MB |
90 | void b43_phy_free(struct b43_wldev *dev) |
91 | { | |
92 | dev->phy.ops->free(dev); | |
93 | dev->phy.ops = NULL; | |
94 | } | |
95 | ||
ef1a628d MB |
96 | int b43_phy_init(struct b43_wldev *dev) |
97 | { | |
98 | struct b43_phy *phy = &dev->phy; | |
99 | const struct b43_phy_operations *ops = phy->ops; | |
100 | int err; | |
101 | ||
ea42e71c RM |
102 | /* During PHY init we need to use some channel. On the first init this |
103 | * function is called *before* b43_op_config, so our pointer is NULL. | |
104 | */ | |
105 | if (!phy->chandef) { | |
106 | phy->chandef = &dev->wl->hw->conf.chandef; | |
107 | phy->channel = phy->chandef->chan->hw_value; | |
108 | } | |
ef1a628d | 109 | |
7a8af8cf | 110 | phy->ops->switch_analog(dev, true); |
a6316e28 | 111 | b43_software_rfkill(dev, false); |
09951ad4 | 112 | |
ef1a628d MB |
113 | err = ops->init(dev); |
114 | if (err) { | |
115 | b43err(dev->wl, "PHY init failed\n"); | |
116 | goto err_block_rf; | |
117 | } | |
09951ad4 RM |
118 | phy->do_full_init = false; |
119 | ||
eb530b0f | 120 | err = b43_switch_channel(dev, phy->channel); |
ef1a628d MB |
121 | if (err) { |
122 | b43err(dev->wl, "PHY init: Channel switch to default failed\n"); | |
123 | goto err_phy_exit; | |
124 | } | |
125 | ||
126 | return 0; | |
127 | ||
128 | err_phy_exit: | |
09951ad4 | 129 | phy->do_full_init = true; |
ef1a628d MB |
130 | if (ops->exit) |
131 | ops->exit(dev); | |
132 | err_block_rf: | |
a6316e28 | 133 | b43_software_rfkill(dev, true); |
ef1a628d MB |
134 | |
135 | return err; | |
136 | } | |
137 | ||
138 | void b43_phy_exit(struct b43_wldev *dev) | |
139 | { | |
140 | const struct b43_phy_operations *ops = dev->phy.ops; | |
141 | ||
a6316e28 | 142 | b43_software_rfkill(dev, true); |
09951ad4 | 143 | dev->phy.do_full_init = true; |
ef1a628d MB |
144 | if (ops->exit) |
145 | ops->exit(dev); | |
146 | } | |
147 | ||
148 | bool b43_has_hardware_pctl(struct b43_wldev *dev) | |
149 | { | |
150 | if (!dev->phy.hardware_power_control) | |
1a2b250b | 151 | return false; |
ef1a628d | 152 | if (!dev->phy.ops->supports_hwpctl) |
1a2b250b | 153 | return false; |
ef1a628d MB |
154 | return dev->phy.ops->supports_hwpctl(dev); |
155 | } | |
156 | ||
157 | void b43_radio_lock(struct b43_wldev *dev) | |
158 | { | |
159 | u32 macctl; | |
160 | ||
591f3dc2 MB |
161 | #if B43_DEBUG |
162 | B43_WARN_ON(dev->phy.radio_locked); | |
3db1cd5c | 163 | dev->phy.radio_locked = true; |
591f3dc2 MB |
164 | #endif |
165 | ||
ef1a628d | 166 | macctl = b43_read32(dev, B43_MMIO_MACCTL); |
ef1a628d MB |
167 | macctl |= B43_MACCTL_RADIOLOCK; |
168 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
591f3dc2 MB |
169 | /* Commit the write and wait for the firmware |
170 | * to finish any radio register access. */ | |
ef1a628d MB |
171 | b43_read32(dev, B43_MMIO_MACCTL); |
172 | udelay(10); | |
173 | } | |
174 | ||
175 | void b43_radio_unlock(struct b43_wldev *dev) | |
176 | { | |
177 | u32 macctl; | |
178 | ||
591f3dc2 MB |
179 | #if B43_DEBUG |
180 | B43_WARN_ON(!dev->phy.radio_locked); | |
3db1cd5c | 181 | dev->phy.radio_locked = false; |
591f3dc2 MB |
182 | #endif |
183 | ||
ef1a628d MB |
184 | /* Commit any write */ |
185 | b43_read16(dev, B43_MMIO_PHY_VER); | |
186 | /* unlock */ | |
187 | macctl = b43_read32(dev, B43_MMIO_MACCTL); | |
ef1a628d MB |
188 | macctl &= ~B43_MACCTL_RADIOLOCK; |
189 | b43_write32(dev, B43_MMIO_MACCTL, macctl); | |
190 | } | |
191 | ||
192 | void b43_phy_lock(struct b43_wldev *dev) | |
193 | { | |
194 | #if B43_DEBUG | |
195 | B43_WARN_ON(dev->phy.phy_locked); | |
3db1cd5c | 196 | dev->phy.phy_locked = true; |
ef1a628d | 197 | #endif |
21d889d4 | 198 | B43_WARN_ON(dev->dev->core_rev < 3); |
ef1a628d | 199 | |
05c914fe | 200 | if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) |
ef1a628d MB |
201 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); |
202 | } | |
203 | ||
204 | void b43_phy_unlock(struct b43_wldev *dev) | |
205 | { | |
206 | #if B43_DEBUG | |
207 | B43_WARN_ON(!dev->phy.phy_locked); | |
3db1cd5c | 208 | dev->phy.phy_locked = false; |
ef1a628d | 209 | #endif |
21d889d4 | 210 | B43_WARN_ON(dev->dev->core_rev < 3); |
ef1a628d | 211 | |
05c914fe | 212 | if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) |
ef1a628d MB |
213 | b43_power_saving_ctl_bits(dev, 0); |
214 | } | |
215 | ||
d10d0e57 MB |
216 | static inline void assert_mac_suspended(struct b43_wldev *dev) |
217 | { | |
218 | if (!B43_DEBUG) | |
219 | return; | |
220 | if ((b43_status(dev) >= B43_STAT_INITIALIZED) && | |
221 | (dev->mac_suspended <= 0)) { | |
222 | b43dbg(dev->wl, "PHY/RADIO register access with " | |
223 | "enabled MAC.\n"); | |
224 | dump_stack(); | |
225 | } | |
226 | } | |
227 | ||
ef1a628d MB |
228 | u16 b43_radio_read(struct b43_wldev *dev, u16 reg) |
229 | { | |
d10d0e57 | 230 | assert_mac_suspended(dev); |
6247d2aa | 231 | dev->phy.writes_counter = 0; |
ef1a628d MB |
232 | return dev->phy.ops->radio_read(dev, reg); |
233 | } | |
234 | ||
235 | void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value) | |
236 | { | |
d10d0e57 | 237 | assert_mac_suspended(dev); |
6247d2aa RM |
238 | if (b43_bus_host_is_pci(dev->dev) && |
239 | ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { | |
240 | b43_read32(dev, B43_MMIO_MACCTL); | |
241 | dev->phy.writes_counter = 1; | |
242 | } | |
ef1a628d MB |
243 | dev->phy.ops->radio_write(dev, reg, value); |
244 | } | |
245 | ||
246 | void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask) | |
247 | { | |
248 | b43_radio_write16(dev, offset, | |
249 | b43_radio_read16(dev, offset) & mask); | |
250 | } | |
251 | ||
252 | void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set) | |
253 | { | |
254 | b43_radio_write16(dev, offset, | |
255 | b43_radio_read16(dev, offset) | set); | |
256 | } | |
257 | ||
258 | void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) | |
259 | { | |
260 | b43_radio_write16(dev, offset, | |
261 | (b43_radio_read16(dev, offset) & mask) | set); | |
262 | } | |
263 | ||
0f941777 RM |
264 | bool b43_radio_wait_value(struct b43_wldev *dev, u16 offset, u16 mask, |
265 | u16 value, int delay, int timeout) | |
266 | { | |
267 | u16 val; | |
268 | int i; | |
269 | ||
270 | for (i = 0; i < timeout; i += delay) { | |
271 | val = b43_radio_read(dev, offset); | |
272 | if ((val & mask) == value) | |
273 | return true; | |
274 | udelay(delay); | |
275 | } | |
276 | return false; | |
277 | } | |
278 | ||
ef1a628d MB |
279 | u16 b43_phy_read(struct b43_wldev *dev, u16 reg) |
280 | { | |
d10d0e57 | 281 | assert_mac_suspended(dev); |
15518080 | 282 | dev->phy.writes_counter = 0; |
d342b95d RM |
283 | |
284 | if (dev->phy.ops->phy_read) | |
285 | return dev->phy.ops->phy_read(dev, reg); | |
286 | ||
25c15566 | 287 | b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); |
d342b95d | 288 | return b43_read16(dev, B43_MMIO_PHY_DATA); |
ef1a628d MB |
289 | } |
290 | ||
291 | void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value) | |
292 | { | |
d10d0e57 | 293 | assert_mac_suspended(dev); |
6247d2aa RM |
294 | if (b43_bus_host_is_pci(dev->dev) && |
295 | ++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) { | |
15518080 | 296 | b43_read16(dev, B43_MMIO_PHY_VER); |
6247d2aa | 297 | dev->phy.writes_counter = 1; |
15518080 | 298 | } |
d342b95d RM |
299 | |
300 | if (dev->phy.ops->phy_write) | |
301 | return dev->phy.ops->phy_write(dev, reg, value); | |
302 | ||
25c15566 | 303 | b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); |
d342b95d | 304 | b43_write16(dev, B43_MMIO_PHY_DATA, value); |
ef1a628d MB |
305 | } |
306 | ||
738f0f43 GS |
307 | void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg) |
308 | { | |
9c3a6670 | 309 | b43_phy_write(dev, destreg, b43_phy_read(dev, srcreg)); |
738f0f43 GS |
310 | } |
311 | ||
ef1a628d MB |
312 | void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask) |
313 | { | |
68ec5329 GS |
314 | if (dev->phy.ops->phy_maskset) { |
315 | assert_mac_suspended(dev); | |
316 | dev->phy.ops->phy_maskset(dev, offset, mask, 0); | |
317 | } else { | |
318 | b43_phy_write(dev, offset, | |
319 | b43_phy_read(dev, offset) & mask); | |
320 | } | |
ef1a628d MB |
321 | } |
322 | ||
323 | void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set) | |
324 | { | |
68ec5329 GS |
325 | if (dev->phy.ops->phy_maskset) { |
326 | assert_mac_suspended(dev); | |
327 | dev->phy.ops->phy_maskset(dev, offset, 0xFFFF, set); | |
328 | } else { | |
329 | b43_phy_write(dev, offset, | |
330 | b43_phy_read(dev, offset) | set); | |
331 | } | |
ef1a628d MB |
332 | } |
333 | ||
334 | void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set) | |
335 | { | |
68ec5329 GS |
336 | if (dev->phy.ops->phy_maskset) { |
337 | assert_mac_suspended(dev); | |
338 | dev->phy.ops->phy_maskset(dev, offset, mask, set); | |
339 | } else { | |
340 | b43_phy_write(dev, offset, | |
341 | (b43_phy_read(dev, offset) & mask) | set); | |
342 | } | |
ef1a628d MB |
343 | } |
344 | ||
b60c3c2f RM |
345 | void b43_phy_put_into_reset(struct b43_wldev *dev) |
346 | { | |
b60c3c2f | 347 | u32 tmp; |
b60c3c2f RM |
348 | |
349 | switch (dev->dev->bus_type) { | |
350 | #ifdef CONFIG_B43_BCMA | |
351 | case B43_BUS_BCMA: | |
50c1b59e RM |
352 | tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); |
353 | tmp &= ~B43_BCMA_IOCTL_GMODE; | |
354 | tmp |= B43_BCMA_IOCTL_PHY_RESET; | |
355 | tmp |= BCMA_IOCTL_FGC; | |
356 | bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); | |
357 | udelay(1); | |
358 | ||
359 | tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); | |
360 | tmp &= ~BCMA_IOCTL_FGC; | |
361 | bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); | |
362 | udelay(1); | |
b60c3c2f RM |
363 | break; |
364 | #endif | |
365 | #ifdef CONFIG_B43_SSB | |
366 | case B43_BUS_SSB: | |
367 | tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); | |
368 | tmp &= ~B43_TMSLOW_GMODE; | |
369 | tmp |= B43_TMSLOW_PHYRESET; | |
370 | tmp |= SSB_TMSLOW_FGC; | |
371 | ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); | |
50c1b59e | 372 | usleep_range(1000, 2000); |
b60c3c2f RM |
373 | |
374 | tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); | |
375 | tmp &= ~SSB_TMSLOW_FGC; | |
b60c3c2f | 376 | ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); |
50c1b59e | 377 | usleep_range(1000, 2000); |
b60c3c2f RM |
378 | |
379 | break; | |
380 | #endif | |
381 | } | |
382 | } | |
383 | ||
50c1b59e RM |
384 | void b43_phy_take_out_of_reset(struct b43_wldev *dev) |
385 | { | |
386 | u32 tmp; | |
387 | ||
388 | switch (dev->dev->bus_type) { | |
389 | #ifdef CONFIG_B43_BCMA | |
390 | case B43_BUS_BCMA: | |
391 | /* Unset reset bit (with forcing clock) */ | |
392 | tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); | |
393 | tmp &= ~B43_BCMA_IOCTL_PHY_RESET; | |
394 | tmp &= ~B43_BCMA_IOCTL_PHY_CLKEN; | |
395 | tmp |= BCMA_IOCTL_FGC; | |
396 | bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); | |
397 | udelay(1); | |
398 | ||
399 | /* Do not force clock anymore */ | |
400 | tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); | |
401 | tmp &= ~BCMA_IOCTL_FGC; | |
402 | tmp |= B43_BCMA_IOCTL_PHY_CLKEN; | |
403 | bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); | |
404 | udelay(1); | |
405 | break; | |
406 | #endif | |
407 | #ifdef CONFIG_B43_SSB | |
408 | case B43_BUS_SSB: | |
409 | /* Unset reset bit (with forcing clock) */ | |
410 | tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); | |
411 | tmp &= ~B43_TMSLOW_PHYRESET; | |
412 | tmp &= ~B43_TMSLOW_PHYCLKEN; | |
413 | tmp |= SSB_TMSLOW_FGC; | |
414 | ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); | |
415 | ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ | |
416 | usleep_range(1000, 2000); | |
417 | ||
418 | tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); | |
419 | tmp &= ~SSB_TMSLOW_FGC; | |
420 | tmp |= B43_TMSLOW_PHYCLKEN; | |
421 | ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); | |
422 | ssb_read32(dev->dev->sdev, SSB_TMSLOW); /* flush */ | |
423 | usleep_range(1000, 2000); | |
424 | break; | |
425 | #endif | |
426 | } | |
427 | } | |
428 | ||
ef1a628d MB |
429 | int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel) |
430 | { | |
431 | struct b43_phy *phy = &(dev->phy); | |
432 | u16 channelcookie, savedcookie; | |
433 | int err; | |
434 | ||
ef1a628d MB |
435 | /* First we set the channel radio code to prevent the |
436 | * firmware from sending ghost packets. | |
437 | */ | |
438 | channelcookie = new_channel; | |
439 | if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) | |
106cb09a RM |
440 | channelcookie |= B43_SHM_SH_CHAN_5GHZ; |
441 | /* FIXME: set 40Mhz flag if required */ | |
442 | if (0) | |
443 | channelcookie |= B43_SHM_SH_CHAN_40MHZ; | |
ef1a628d MB |
444 | savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN); |
445 | b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie); | |
446 | ||
447 | /* Now try to switch the PHY hardware channel. */ | |
448 | err = phy->ops->switch_channel(dev, new_channel); | |
449 | if (err) | |
450 | goto err_restore_cookie; | |
451 | ||
ef1a628d MB |
452 | /* Wait for the radio to tune to the channel and stabilize. */ |
453 | msleep(8); | |
454 | ||
455 | return 0; | |
456 | ||
457 | err_restore_cookie: | |
458 | b43_shm_write16(dev, B43_SHM_SHARED, | |
459 | B43_SHM_SH_CHAN, savedcookie); | |
460 | ||
461 | return err; | |
462 | } | |
463 | ||
19d337df | 464 | void b43_software_rfkill(struct b43_wldev *dev, bool blocked) |
ef1a628d MB |
465 | { |
466 | struct b43_phy *phy = &dev->phy; | |
467 | ||
b929ecf7 | 468 | b43_mac_suspend(dev); |
19d337df JB |
469 | phy->ops->software_rfkill(dev, blocked); |
470 | phy->radio_on = !blocked; | |
b929ecf7 | 471 | b43_mac_enable(dev); |
ef1a628d | 472 | } |
18c8adeb MB |
473 | |
474 | /** | |
475 | * b43_phy_txpower_adjust_work - TX power workqueue. | |
476 | * | |
477 | * Workqueue for updating the TX power parameters in hardware. | |
478 | */ | |
479 | void b43_phy_txpower_adjust_work(struct work_struct *work) | |
480 | { | |
481 | struct b43_wl *wl = container_of(work, struct b43_wl, | |
482 | txpower_adjust_work); | |
483 | struct b43_wldev *dev; | |
484 | ||
485 | mutex_lock(&wl->mutex); | |
486 | dev = wl->current_dev; | |
487 | ||
488 | if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED))) | |
489 | dev->phy.ops->adjust_txpower(dev); | |
490 | ||
491 | mutex_unlock(&wl->mutex); | |
492 | } | |
493 | ||
18c8adeb MB |
494 | void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags) |
495 | { | |
496 | struct b43_phy *phy = &dev->phy; | |
497 | unsigned long now = jiffies; | |
498 | enum b43_txpwr_result result; | |
499 | ||
500 | if (!(flags & B43_TXPWR_IGNORE_TIME)) { | |
501 | /* Check if it's time for a TXpower check. */ | |
502 | if (time_before(now, phy->next_txpwr_check_time)) | |
503 | return; /* Not yet */ | |
504 | } | |
505 | /* The next check will be needed in two seconds, or later. */ | |
506 | phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2)); | |
507 | ||
79d2232f RM |
508 | if ((dev->dev->board_vendor == SSB_BOARDVENDOR_BCM) && |
509 | (dev->dev->board_type == SSB_BOARD_BU4306)) | |
18c8adeb MB |
510 | return; /* No software txpower adjustment needed */ |
511 | ||
512 | result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI)); | |
513 | if (result == B43_TXPWR_RES_DONE) | |
514 | return; /* We are done. */ | |
515 | B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST); | |
516 | B43_WARN_ON(phy->ops->adjust_txpower == NULL); | |
517 | ||
518 | /* We must adjust the transmission power in hardware. | |
519 | * Schedule b43_phy_txpower_adjust_work(). */ | |
42935eca | 520 | ieee80211_queue_work(dev->wl->hw, &dev->wl->txpower_adjust_work); |
18c8adeb MB |
521 | } |
522 | ||
523 | int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset) | |
524 | { | |
525 | const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK); | |
526 | unsigned int a, b, c, d; | |
527 | unsigned int average; | |
528 | u32 tmp; | |
529 | ||
530 | tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset); | |
531 | a = tmp & 0xFF; | |
532 | b = (tmp >> 8) & 0xFF; | |
533 | c = (tmp >> 16) & 0xFF; | |
534 | d = (tmp >> 24) & 0xFF; | |
535 | if (a == 0 || a == B43_TSSI_MAX || | |
536 | b == 0 || b == B43_TSSI_MAX || | |
537 | c == 0 || c == B43_TSSI_MAX || | |
538 | d == 0 || d == B43_TSSI_MAX) | |
539 | return -ENOENT; | |
540 | /* The values are OK. Clear them. */ | |
541 | tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) | | |
542 | (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24); | |
543 | b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp); | |
544 | ||
545 | if (is_ofdm) { | |
546 | a = (a + 32) & 0x3F; | |
547 | b = (b + 32) & 0x3F; | |
548 | c = (c + 32) & 0x3F; | |
549 | d = (d + 32) & 0x3F; | |
550 | } | |
551 | ||
552 | /* Get the average of the values with 0.5 added to each value. */ | |
553 | average = (a + b + c + d + 2) / 4; | |
554 | if (is_ofdm) { | |
555 | /* Adjust for CCK-boost */ | |
6e6a2cd5 | 556 | if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1) |
18c8adeb MB |
557 | & B43_HF_CCKBOOST) |
558 | average = (average >= 13) ? (average - 13) : 0; | |
559 | } | |
560 | ||
561 | return average; | |
562 | } | |
cb24f57f MB |
563 | |
564 | void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on) | |
565 | { | |
566 | b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4); | |
567 | } | |
98650454 | 568 | |
abc1f7cd | 569 | |
bee6d4b2 RM |
570 | bool b43_is_40mhz(struct b43_wldev *dev) |
571 | { | |
572 | return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40; | |
573 | } | |
574 | ||
f6a3e99d RM |
575 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ |
576 | void b43_phy_force_clock(struct b43_wldev *dev, bool force) | |
577 | { | |
578 | u32 tmp; | |
579 | ||
580 | WARN_ON(dev->phy.type != B43_PHYTYPE_N && | |
3f7bb3f3 RM |
581 | dev->phy.type != B43_PHYTYPE_HT && |
582 | dev->phy.type != B43_PHYTYPE_AC); | |
f6a3e99d RM |
583 | |
584 | switch (dev->dev->bus_type) { | |
585 | #ifdef CONFIG_B43_BCMA | |
586 | case B43_BUS_BCMA: | |
587 | tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL); | |
588 | if (force) | |
589 | tmp |= BCMA_IOCTL_FGC; | |
590 | else | |
591 | tmp &= ~BCMA_IOCTL_FGC; | |
592 | bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp); | |
593 | break; | |
594 | #endif | |
595 | #ifdef CONFIG_B43_SSB | |
596 | case B43_BUS_SSB: | |
597 | tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW); | |
598 | if (force) | |
599 | tmp |= SSB_TMSLOW_FGC; | |
600 | else | |
601 | tmp &= ~SSB_TMSLOW_FGC; | |
602 | ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp); | |
603 | break; | |
604 | #endif | |
605 | } | |
606 | } | |
607 | ||
6f98e62a | 608 | /* http://bcm-v4.sipsolutions.net/802.11/PHY/Cordic */ |
98650454 RM |
609 | struct b43_c32 b43_cordic(int theta) |
610 | { | |
5b4bc649 JP |
611 | static const u32 arctg[] = { |
612 | 2949120, 1740967, 919879, 466945, 234379, 117304, | |
613 | 58666, 29335, 14668, 7334, 3667, 1833, | |
614 | 917, 458, 229, 115, 57, 29, | |
615 | }; | |
6f98e62a RM |
616 | u8 i; |
617 | s32 tmp; | |
618 | s8 signx = 1; | |
619 | u32 angle = 0; | |
98650454 RM |
620 | struct b43_c32 ret = { .i = 39797, .q = 0, }; |
621 | ||
6f98e62a RM |
622 | while (theta > (180 << 16)) |
623 | theta -= (360 << 16); | |
624 | while (theta < -(180 << 16)) | |
625 | theta += (360 << 16); | |
98650454 | 626 | |
6f98e62a RM |
627 | if (theta > (90 << 16)) { |
628 | theta -= (180 << 16); | |
98650454 | 629 | signx = -1; |
6f98e62a RM |
630 | } else if (theta < -(90 << 16)) { |
631 | theta += (180 << 16); | |
98650454 RM |
632 | signx = -1; |
633 | } | |
634 | ||
635 | for (i = 0; i <= 17; i++) { | |
636 | if (theta > angle) { | |
637 | tmp = ret.i - (ret.q >> i); | |
638 | ret.q += ret.i >> i; | |
639 | ret.i = tmp; | |
640 | angle += arctg[i]; | |
641 | } else { | |
642 | tmp = ret.i + (ret.q >> i); | |
643 | ret.q -= ret.i >> i; | |
644 | ret.i = tmp; | |
645 | angle -= arctg[i]; | |
646 | } | |
647 | } | |
648 | ||
649 | ret.i *= signx; | |
650 | ret.q *= signx; | |
651 | ||
652 | return ret; | |
653 | } |