projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
b43: Accessing the TSF via mac80211
[linux-2.6-block.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
e4d6b795
MB		 7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29*/
30
31#include <linux/delay.h>
32#include <linux/init.h>
33#include <linux/moduleparam.h>
34#include <linux/if_arp.h>
35#include <linux/etherdevice.h>
e4d6b795
MB		 36#include <linux/firmware.h>
37#include <linux/wireless.h>
38#include <linux/workqueue.h>
39#include <linux/skbuff.h>
96cf49a2 40#include <linux/io.h>
e4d6b795
MB		 41#include <linux/dma-mapping.h>
42#include <asm/unaligned.h>
43
44#include "b43.h"
45#include "main.h"
46#include "debugfs.h"
ef1a628d
MB		 47#include "phy_common.h"
48#include "phy_g.h"
3d0da751 49#include "phy_n.h"
e4d6b795 50#include "dma.h"
5100d5ac 51#include "pio.h"
e4d6b795
MB		 52#include "sysfs.h"
53#include "xmit.h"
e4d6b795
MB		 54#include "lo.h"
55#include "pcmcia.h"
56
57MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58MODULE_AUTHOR("Martin Langer");
59MODULE_AUTHOR("Stefano Brivio");
60MODULE_AUTHOR("Michael Buesch");
61MODULE_LICENSE("GPL");
62
9c7d99d6
MB		 63MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
64
e4d6b795
MB		 65
66static int modparam_bad_frames_preempt;
67module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
70
e4d6b795
MB		 71static char modparam_fwpostfix[16];
72module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
74
e4d6b795
MB		 75static int modparam_hwpctl;
76module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
78
79static int modparam_nohwcrypt;
80module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
82
e6f5b934
MB		 83int b43_modparam_qos = 1;
84module_param_named(qos, b43_modparam_qos, int, 0444);
85MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
86
1855ba78
MB		 87static int modparam_btcoex = 1;
88module_param_named(btcoex, modparam_btcoex, int, 0444);
89MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
90
e6f5b934 91
e4d6b795
MB		 92static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
013978b6 99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 100 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 101 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 102 SSB_DEVTABLE_END
103};
104
105MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
106
107/* Channel and ratetables are shared for all devices.
108 * They can't be const, because ieee80211 puts some precalculated
109 * data in there. This data is the same for all devices, so we don't
110 * get concurrency issues */
111#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 112 { \
113 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
114 .hw_value = (_rateid), \
115 .flags = (_flags), \
e4d6b795 116 }
8318d78a
JB		 117
118/*
119 * NOTE: When changing this, sync with xmit.c's
120 * b43_plcp_get_bitrate_idx_* functions!
121 */
e4d6b795 122static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 123 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
124 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
126 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
127 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
133 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
134 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 135};
136
137#define b43_a_ratetable (__b43_ratetable + 4)
138#define b43_a_ratetable_size 8
139#define b43_b_ratetable (__b43_ratetable + 0)
140#define b43_b_ratetable_size 4
141#define b43_g_ratetable (__b43_ratetable + 0)
142#define b43_g_ratetable_size 12
143
bb1eeff1
MB		 144#define CHAN4G(_channel, _freq, _flags) { \
145 .band = IEEE80211_BAND_2GHZ, \
146 .center_freq = (_freq), \
147 .hw_value = (_channel), \
148 .flags = (_flags), \
149 .max_antenna_gain = 0, \
150 .max_power = 30, \
151}
96c755a3 152static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 153 CHAN4G(1, 2412, 0),
154 CHAN4G(2, 2417, 0),
155 CHAN4G(3, 2422, 0),
156 CHAN4G(4, 2427, 0),
157 CHAN4G(5, 2432, 0),
158 CHAN4G(6, 2437, 0),
159 CHAN4G(7, 2442, 0),
160 CHAN4G(8, 2447, 0),
161 CHAN4G(9, 2452, 0),
162 CHAN4G(10, 2457, 0),
163 CHAN4G(11, 2462, 0),
164 CHAN4G(12, 2467, 0),
165 CHAN4G(13, 2472, 0),
166 CHAN4G(14, 2484, 0),
167};
168#undef CHAN4G
169
170#define CHAN5G(_channel, _flags) { \
171 .band = IEEE80211_BAND_5GHZ, \
172 .center_freq = 5000 + (5 * (_channel)), \
173 .hw_value = (_channel), \
174 .flags = (_flags), \
175 .max_antenna_gain = 0, \
176 .max_power = 30, \
177}
178static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
179 CHAN5G(32, 0), CHAN5G(34, 0),
180 CHAN5G(36, 0), CHAN5G(38, 0),
181 CHAN5G(40, 0), CHAN5G(42, 0),
182 CHAN5G(44, 0), CHAN5G(46, 0),
183 CHAN5G(48, 0), CHAN5G(50, 0),
184 CHAN5G(52, 0), CHAN5G(54, 0),
185 CHAN5G(56, 0), CHAN5G(58, 0),
186 CHAN5G(60, 0), CHAN5G(62, 0),
187 CHAN5G(64, 0), CHAN5G(66, 0),
188 CHAN5G(68, 0), CHAN5G(70, 0),
189 CHAN5G(72, 0), CHAN5G(74, 0),
190 CHAN5G(76, 0), CHAN5G(78, 0),
191 CHAN5G(80, 0), CHAN5G(82, 0),
192 CHAN5G(84, 0), CHAN5G(86, 0),
193 CHAN5G(88, 0), CHAN5G(90, 0),
194 CHAN5G(92, 0), CHAN5G(94, 0),
195 CHAN5G(96, 0), CHAN5G(98, 0),
196 CHAN5G(100, 0), CHAN5G(102, 0),
197 CHAN5G(104, 0), CHAN5G(106, 0),
198 CHAN5G(108, 0), CHAN5G(110, 0),
199 CHAN5G(112, 0), CHAN5G(114, 0),
200 CHAN5G(116, 0), CHAN5G(118, 0),
201 CHAN5G(120, 0), CHAN5G(122, 0),
202 CHAN5G(124, 0), CHAN5G(126, 0),
203 CHAN5G(128, 0), CHAN5G(130, 0),
204 CHAN5G(132, 0), CHAN5G(134, 0),
205 CHAN5G(136, 0), CHAN5G(138, 0),
206 CHAN5G(140, 0), CHAN5G(142, 0),
207 CHAN5G(144, 0), CHAN5G(145, 0),
208 CHAN5G(146, 0), CHAN5G(147, 0),
209 CHAN5G(148, 0), CHAN5G(149, 0),
210 CHAN5G(150, 0), CHAN5G(151, 0),
211 CHAN5G(152, 0), CHAN5G(153, 0),
212 CHAN5G(154, 0), CHAN5G(155, 0),
213 CHAN5G(156, 0), CHAN5G(157, 0),
214 CHAN5G(158, 0), CHAN5G(159, 0),
215 CHAN5G(160, 0), CHAN5G(161, 0),
216 CHAN5G(162, 0), CHAN5G(163, 0),
217 CHAN5G(164, 0), CHAN5G(165, 0),
218 CHAN5G(166, 0), CHAN5G(168, 0),
219 CHAN5G(170, 0), CHAN5G(172, 0),
220 CHAN5G(174, 0), CHAN5G(176, 0),
221 CHAN5G(178, 0), CHAN5G(180, 0),
222 CHAN5G(182, 0), CHAN5G(184, 0),
223 CHAN5G(186, 0), CHAN5G(188, 0),
224 CHAN5G(190, 0), CHAN5G(192, 0),
225 CHAN5G(194, 0), CHAN5G(196, 0),
226 CHAN5G(198, 0), CHAN5G(200, 0),
227 CHAN5G(202, 0), CHAN5G(204, 0),
228 CHAN5G(206, 0), CHAN5G(208, 0),
229 CHAN5G(210, 0), CHAN5G(212, 0),
230 CHAN5G(214, 0), CHAN5G(216, 0),
231 CHAN5G(218, 0), CHAN5G(220, 0),
232 CHAN5G(222, 0), CHAN5G(224, 0),
233 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 234};
235
bb1eeff1
MB		 236static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
237 CHAN5G(34, 0), CHAN5G(36, 0),
238 CHAN5G(38, 0), CHAN5G(40, 0),
239 CHAN5G(42, 0), CHAN5G(44, 0),
240 CHAN5G(46, 0), CHAN5G(48, 0),
241 CHAN5G(52, 0), CHAN5G(56, 0),
242 CHAN5G(60, 0), CHAN5G(64, 0),
243 CHAN5G(100, 0), CHAN5G(104, 0),
244 CHAN5G(108, 0), CHAN5G(112, 0),
245 CHAN5G(116, 0), CHAN5G(120, 0),
246 CHAN5G(124, 0), CHAN5G(128, 0),
247 CHAN5G(132, 0), CHAN5G(136, 0),
248 CHAN5G(140, 0), CHAN5G(149, 0),
249 CHAN5G(153, 0), CHAN5G(157, 0),
250 CHAN5G(161, 0), CHAN5G(165, 0),
251 CHAN5G(184, 0), CHAN5G(188, 0),
252 CHAN5G(192, 0), CHAN5G(196, 0),
253 CHAN5G(200, 0), CHAN5G(204, 0),
254 CHAN5G(208, 0), CHAN5G(212, 0),
255 CHAN5G(216, 0),
256};
257#undef CHAN5G
258
259static struct ieee80211_supported_band b43_band_5GHz_nphy = {
260 .band = IEEE80211_BAND_5GHZ,
261 .channels = b43_5ghz_nphy_chantable,
262 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
263 .bitrates = b43_a_ratetable,
264 .n_bitrates = b43_a_ratetable_size,
e4d6b795 265};
8318d78a 266
bb1eeff1
MB		 267static struct ieee80211_supported_band b43_band_5GHz_aphy = {
268 .band = IEEE80211_BAND_5GHZ,
269 .channels = b43_5ghz_aphy_chantable,
270 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
271 .bitrates = b43_a_ratetable,
272 .n_bitrates = b43_a_ratetable_size,
8318d78a 273};
e4d6b795 274
8318d78a 275static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 276 .band = IEEE80211_BAND_2GHZ,
277 .channels = b43_2ghz_chantable,
278 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
279 .bitrates = b43_g_ratetable,
280 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 281};
282
e4d6b795
MB		 283static void b43_wireless_core_exit(struct b43_wldev *dev);
284static int b43_wireless_core_init(struct b43_wldev *dev);
285static void b43_wireless_core_stop(struct b43_wldev *dev);
286static int b43_wireless_core_start(struct b43_wldev *dev);
287
288static int b43_ratelimit(struct b43_wl *wl)
289{
290 if (!wl || !wl->current_dev)
291 return 1;
292 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
293 return 1;
294 /* We are up and running.
295 * Ratelimit the messages to avoid DoS over the net. */
296 return net_ratelimit();
297}
298
299void b43info(struct b43_wl *wl, const char *fmt, ...)
300{
301 va_list args;
302
303 if (!b43_ratelimit(wl))
304 return;
305 va_start(args, fmt);
306 printk(KERN_INFO "b43-%s: ",
307 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
308 vprintk(fmt, args);
309 va_end(args);
310}
311
312void b43err(struct b43_wl *wl, const char *fmt, ...)
313{
314 va_list args;
315
316 if (!b43_ratelimit(wl))
317 return;
318 va_start(args, fmt);
319 printk(KERN_ERR "b43-%s ERROR: ",
320 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
321 vprintk(fmt, args);
322 va_end(args);
323}
324
325void b43warn(struct b43_wl *wl, const char *fmt, ...)
326{
327 va_list args;
328
329 if (!b43_ratelimit(wl))
330 return;
331 va_start(args, fmt);
332 printk(KERN_WARNING "b43-%s warning: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
334 vprintk(fmt, args);
335 va_end(args);
336}
337
338#if B43_DEBUG
339void b43dbg(struct b43_wl *wl, const char *fmt, ...)
340{
341 va_list args;
342
343 va_start(args, fmt);
344 printk(KERN_DEBUG "b43-%s debug: ",
345 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
346 vprintk(fmt, args);
347 va_end(args);
348}
349#endif /* DEBUG */
350
351static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
352{
353 u32 macctl;
354
355 B43_WARN_ON(offset % 4 != 0);
356
357 macctl = b43_read32(dev, B43_MMIO_MACCTL);
358 if (macctl & B43_MACCTL_BE)
359 val = swab32(val);
360
361 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
362 mmiowb();
363 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364}
365
280d0e16
MB		 366static inline void b43_shm_control_word(struct b43_wldev *dev,
367 u16 routing, u16 offset)
e4d6b795
MB		 368{
369 u32 control;
370
371 /* "offset" is the WORD offset. */
e4d6b795
MB		 372 control = routing;
373 control <<= 16;
374 control |= offset;
375 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376}
377
6bbc321a 378u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 379{
380 u32 ret;
381
382 if (routing == B43_SHM_SHARED) {
383 B43_WARN_ON(offset & 0x0001);
384 if (offset & 0x0003) {
385 /* Unaligned access */
386 b43_shm_control_word(dev, routing, offset >> 2);
387 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
388 ret <<= 16;
389 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
390 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
391
280d0e16 392 goto out;
e4d6b795
MB		 393 }
394 offset >>= 2;
395 }
396 b43_shm_control_word(dev, routing, offset);
397 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 398out:
e4d6b795
MB		 399 return ret;
400}
401
6bbc321a 402u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 403{
280d0e16
MB		 404 struct b43_wl *wl = dev->wl;
405 unsigned long flags;
6bbc321a 406 u32 ret;
e4d6b795 407
280d0e16 408 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 409 ret = __b43_shm_read32(dev, routing, offset);
410 spin_unlock_irqrestore(&wl->shm_lock, flags);
411
412 return ret;
413}
414
415u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
416{
417 u16 ret;
418
e4d6b795
MB		 419 if (routing == B43_SHM_SHARED) {
420 B43_WARN_ON(offset & 0x0001);
421 if (offset & 0x0003) {
422 /* Unaligned access */
423 b43_shm_control_word(dev, routing, offset >> 2);
424 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
425
280d0e16 426 goto out;
e4d6b795
MB		 427 }
428 offset >>= 2;
429 }
430 b43_shm_control_word(dev, routing, offset);
431 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 432out:
e4d6b795
MB		 433 return ret;
434}
435
6bbc321a 436u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795 437{
280d0e16
MB		 438 struct b43_wl *wl = dev->wl;
439 unsigned long flags;
6bbc321a 440 u16 ret;
280d0e16
MB		 441
442 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 443 ret = __b43_shm_read16(dev, routing, offset);
444 spin_unlock_irqrestore(&wl->shm_lock, flags);
445
446 return ret;
447}
448
449void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
450{
e4d6b795
MB		 451 if (routing == B43_SHM_SHARED) {
452 B43_WARN_ON(offset & 0x0001);
453 if (offset & 0x0003) {
454 /* Unaligned access */
455 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795
MB		 456 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
457 (value >> 16) & 0xffff);
e4d6b795 458 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
e4d6b795 459 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
6bbc321a 460 return;
e4d6b795
MB		 461 }
462 offset >>= 2;
463 }
464 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 465 b43_write32(dev, B43_MMIO_SHM_DATA, value);
466}
467
6bbc321a 468void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
e4d6b795 469{
280d0e16
MB		 470 struct b43_wl *wl = dev->wl;
471 unsigned long flags;
472
473 spin_lock_irqsave(&wl->shm_lock, flags);
6bbc321a
MB		 474 __b43_shm_write32(dev, routing, offset, value);
475 spin_unlock_irqrestore(&wl->shm_lock, flags);
476}
477
478void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
479{
e4d6b795
MB		 480 if (routing == B43_SHM_SHARED) {
481 B43_WARN_ON(offset & 0x0001);
482 if (offset & 0x0003) {
483 /* Unaligned access */
484 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 485 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 486 return;
e4d6b795
MB		 487 }
488 offset >>= 2;
489 }
490 b43_shm_control_word(dev, routing, offset);
e4d6b795 491 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 492}
493
494void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
495{
496 struct b43_wl *wl = dev->wl;
497 unsigned long flags;
498
499 spin_lock_irqsave(&wl->shm_lock, flags);
500 __b43_shm_write16(dev, routing, offset, value);
280d0e16 501 spin_unlock_irqrestore(&wl->shm_lock, flags);
e4d6b795
MB		 502}
503
504/* Read HostFlags */
35f0d354 505u64 b43_hf_read(struct b43_wldev * dev)
e4d6b795 506{
35f0d354 507 u64 ret;
e4d6b795
MB		 508
509 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
510 ret <<= 16;
35f0d354
MB		 511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
512 ret <<= 16;
e4d6b795
MB		 513 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
514
515 return ret;
516}
517
518/* Write HostFlags */
35f0d354 519void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 520{
35f0d354
MB		 521 u16 lo, mi, hi;
522
523 lo = (value & 0x00000000FFFFULL);
524 mi = (value & 0x0000FFFF0000ULL) >> 16;
525 hi = (value & 0xFFFF00000000ULL) >> 32;
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
527 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
528 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 529}
530
3ebbbb56 531void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 532{
3ebbbb56
MB		 533 u32 low, high;
534
535 B43_WARN_ON(dev->dev->id.revision < 3);
536
537 /* The hardware guarantees us an atomic read, if we
538 * read the low register first. */
539 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
540 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
541
542 *tsf = high;
543 *tsf <<= 32;
544 *tsf |= low;
e4d6b795
MB		 545}
546
547static void b43_time_lock(struct b43_wldev *dev)
548{
549 u32 macctl;
550
551 macctl = b43_read32(dev, B43_MMIO_MACCTL);
552 macctl |= B43_MACCTL_TBTTHOLD;
553 b43_write32(dev, B43_MMIO_MACCTL, macctl);
554 /* Commit the write */
555 b43_read32(dev, B43_MMIO_MACCTL);
556}
557
558static void b43_time_unlock(struct b43_wldev *dev)
559{
560 u32 macctl;
561
562 macctl = b43_read32(dev, B43_MMIO_MACCTL);
563 macctl &= ~B43_MACCTL_TBTTHOLD;
564 b43_write32(dev, B43_MMIO_MACCTL, macctl);
565 /* Commit the write */
566 b43_read32(dev, B43_MMIO_MACCTL);
567}
568
569static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
570{
3ebbbb56
MB		 571 u32 low, high;
572
573 B43_WARN_ON(dev->dev->id.revision < 3);
574
575 low = tsf;
576 high = (tsf >> 32);
577 /* The hardware guarantees us an atomic write, if we
578 * write the low register first. */
579 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
580 mmiowb();
581 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
582 mmiowb();
e4d6b795
MB		 583}
584
585void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
586{
587 b43_time_lock(dev);
588 b43_tsf_write_locked(dev, tsf);
589 b43_time_unlock(dev);
590}
591
592static
593void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
594{
595 static const u8 zero_addr[ETH_ALEN] = { 0 };
596 u16 data;
597
598 if (!mac)
599 mac = zero_addr;
600
601 offset |= 0x0020;
602 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
603
604 data = mac[0];
605 data |= mac[1] << 8;
606 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
607 data = mac[2];
608 data |= mac[3] << 8;
609 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
610 data = mac[4];
611 data |= mac[5] << 8;
612 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
613}
614
615static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
616{
617 const u8 *mac;
618 const u8 *bssid;
619 u8 mac_bssid[ETH_ALEN * 2];
620 int i;
621 u32 tmp;
622
623 bssid = dev->wl->bssid;
624 mac = dev->wl->mac_addr;
625
626 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
627
628 memcpy(mac_bssid, mac, ETH_ALEN);
629 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
630
631 /* Write our MAC address and BSSID to template ram */
632 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
633 tmp = (u32) (mac_bssid[i + 0]);
634 tmp |= (u32) (mac_bssid[i + 1]) << 8;
635 tmp |= (u32) (mac_bssid[i + 2]) << 16;
636 tmp |= (u32) (mac_bssid[i + 3]) << 24;
637 b43_ram_write(dev, 0x20 + i, tmp);
638 }
639}
640
4150c572 641static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 642{
e4d6b795 643 b43_write_mac_bssid_templates(dev);
4150c572 644 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 645}
646
647static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
648{
649 /* slot_time is in usec. */
650 if (dev->phy.type != B43_PHYTYPE_G)
651 return;
652 b43_write16(dev, 0x684, 510 + slot_time);
653 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
654}
655
656static void b43_short_slot_timing_enable(struct b43_wldev *dev)
657{
658 b43_set_slot_time(dev, 9);
e4d6b795
MB		 659}
660
661static void b43_short_slot_timing_disable(struct b43_wldev *dev)
662{
663 b43_set_slot_time(dev, 20);
e4d6b795
MB		 664}
665
666/* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
667 * Returns the _previously_ enabled IRQ mask.
668 */
669static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
670{
671 u32 old_mask;
672
673 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
674 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
675
676 return old_mask;
677}
678
679/* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
680 * Returns the _previously_ enabled IRQ mask.
681 */
682static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
683{
684 u32 old_mask;
685
686 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
687 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
688
689 return old_mask;
690}
691
692/* Synchronize IRQ top- and bottom-half.
693 * IRQs must be masked before calling this.
694 * This must not be called with the irq_lock held.
695 */
696static void b43_synchronize_irq(struct b43_wldev *dev)
697{
698 synchronize_irq(dev->dev->irq);
699 tasklet_kill(&dev->isr_tasklet);
700}
701
702/* DummyTransmission function, as documented on
703 * http://bcm-specs.sipsolutions.net/DummyTransmission
704 */
705void b43_dummy_transmission(struct b43_wldev *dev)
706{
21a75d77 707 struct b43_wl *wl = dev->wl;
e4d6b795
MB		 708 struct b43_phy *phy = &dev->phy;
709 unsigned int i, max_loop;
710 u16 value;
711 u32 buffer[5] = {
712 0x00000000,
713 0x00D40000,
714 0x00000000,
715 0x01000000,
716 0x00000000,
717 };
718
719 switch (phy->type) {
720 case B43_PHYTYPE_A:
721 max_loop = 0x1E;
722 buffer[0] = 0x000201CC;
723 break;
724 case B43_PHYTYPE_B:
725 case B43_PHYTYPE_G:
726 max_loop = 0xFA;
727 buffer[0] = 0x000B846E;
728 break;
729 default:
730 B43_WARN_ON(1);
731 return;
732 }
733
21a75d77
MB		 734 spin_lock_irq(&wl->irq_lock);
735 write_lock(&wl->tx_lock);
736
e4d6b795
MB		 737 for (i = 0; i < 5; i++)
738 b43_ram_write(dev, i * 4, buffer[i]);
739
740 /* Commit writes */
741 b43_read32(dev, B43_MMIO_MACCTL);
742
743 b43_write16(dev, 0x0568, 0x0000);
744 b43_write16(dev, 0x07C0, 0x0000);
745 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
746 b43_write16(dev, 0x050C, value);
747 b43_write16(dev, 0x0508, 0x0000);
748 b43_write16(dev, 0x050A, 0x0000);
749 b43_write16(dev, 0x054C, 0x0000);
750 b43_write16(dev, 0x056A, 0x0014);
751 b43_write16(dev, 0x0568, 0x0826);
752 b43_write16(dev, 0x0500, 0x0000);
753 b43_write16(dev, 0x0502, 0x0030);
754
755 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
756 b43_radio_write16(dev, 0x0051, 0x0017);
757 for (i = 0x00; i < max_loop; i++) {
758 value = b43_read16(dev, 0x050E);
759 if (value & 0x0080)
760 break;
761 udelay(10);
762 }
763 for (i = 0x00; i < 0x0A; i++) {
764 value = b43_read16(dev, 0x050E);
765 if (value & 0x0400)
766 break;
767 udelay(10);
768 }
1d280ddc 769 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 770 value = b43_read16(dev, 0x0690);
771 if (!(value & 0x0100))
772 break;
773 udelay(10);
774 }
775 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
776 b43_radio_write16(dev, 0x0051, 0x0037);
21a75d77
MB		 777
778 write_unlock(&wl->tx_lock);
779 spin_unlock_irq(&wl->irq_lock);
e4d6b795
MB		 780}
781
782static void key_write(struct b43_wldev *dev,
783 u8 index, u8 algorithm, const u8 * key)
784{
785 unsigned int i;
786 u32 offset;
787 u16 value;
788 u16 kidx;
789
790 /* Key index/algo block */
791 kidx = b43_kidx_to_fw(dev, index);
792 value = ((kidx << 4) | algorithm);
793 b43_shm_write16(dev, B43_SHM_SHARED,
794 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
795
796 /* Write the key to the Key Table Pointer offset */
797 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
798 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
799 value = key[i];
800 value |= (u16) (key[i + 1]) << 8;
801 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
802 }
803}
804
805static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
806{
807 u32 addrtmp[2] = { 0, 0, };
808 u8 per_sta_keys_start = 8;
809
810 if (b43_new_kidx_api(dev))
811 per_sta_keys_start = 4;
812
813 B43_WARN_ON(index < per_sta_keys_start);
814 /* We have two default TX keys and possibly two default RX keys.
815 * Physical mac 0 is mapped to physical key 4 or 8, depending
816 * on the firmware version.
817 * So we must adjust the index here.
818 */
819 index -= per_sta_keys_start;
820
821 if (addr) {
822 addrtmp[0] = addr[0];
823 addrtmp[0] |= ((u32) (addr[1]) << 8);
824 addrtmp[0] |= ((u32) (addr[2]) << 16);
825 addrtmp[0] |= ((u32) (addr[3]) << 24);
826 addrtmp[1] = addr[4];
827 addrtmp[1] |= ((u32) (addr[5]) << 8);
828 }
829
830 if (dev->dev->id.revision >= 5) {
831 /* Receive match transmitter address mechanism */
832 b43_shm_write32(dev, B43_SHM_RCMTA,
833 (index * 2) + 0, addrtmp[0]);
834 b43_shm_write16(dev, B43_SHM_RCMTA,
835 (index * 2) + 1, addrtmp[1]);
836 } else {
837 /* RXE (Receive Engine) and
838 * PSM (Programmable State Machine) mechanism
839 */
840 if (index < 8) {
841 /* TODO write to RCM 16, 19, 22 and 25 */
842 } else {
843 b43_shm_write32(dev, B43_SHM_SHARED,
844 B43_SHM_SH_PSM + (index * 6) + 0,
845 addrtmp[0]);
846 b43_shm_write16(dev, B43_SHM_SHARED,
847 B43_SHM_SH_PSM + (index * 6) + 4,
848 addrtmp[1]);
849 }
850 }
851}
852
853static void do_key_write(struct b43_wldev *dev,
854 u8 index, u8 algorithm,
855 const u8 * key, size_t key_len, const u8 * mac_addr)
856{
857 u8 buf[B43_SEC_KEYSIZE] = { 0, };
858 u8 per_sta_keys_start = 8;
859
860 if (b43_new_kidx_api(dev))
861 per_sta_keys_start = 4;
862
863 B43_WARN_ON(index >= dev->max_nr_keys);
864 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
865
866 if (index >= per_sta_keys_start)
867 keymac_write(dev, index, NULL); /* First zero out mac. */
868 if (key)
869 memcpy(buf, key, key_len);
870 key_write(dev, index, algorithm, buf);
871 if (index >= per_sta_keys_start)
872 keymac_write(dev, index, mac_addr);
873
874 dev->key[index].algorithm = algorithm;
875}
876
877static int b43_key_write(struct b43_wldev *dev,
878 int index, u8 algorithm,
879 const u8 * key, size_t key_len,
880 const u8 * mac_addr,
881 struct ieee80211_key_conf *keyconf)
882{
883 int i;
884 int sta_keys_start;
885
886 if (key_len > B43_SEC_KEYSIZE)
887 return -EINVAL;
888 for (i = 0; i < dev->max_nr_keys; i++) {
889 /* Check that we don't already have this key. */
890 B43_WARN_ON(dev->key[i].keyconf == keyconf);
891 }
892 if (index < 0) {
e808e586 893 /* Pairwise key. Get an empty slot for the key. */
e4d6b795
MB		 894 if (b43_new_kidx_api(dev))
895 sta_keys_start = 4;
896 else
897 sta_keys_start = 8;
898 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
899 if (!dev->key[i].keyconf) {
900 /* found empty */
901 index = i;
902 break;
903 }
904 }
905 if (index < 0) {
e808e586 906 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 907 return -ENOSPC;
908 }
909 } else
910 B43_WARN_ON(index > 3);
911
912 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
913 if ((index <= 3) && !b43_new_kidx_api(dev)) {
914 /* Default RX key */
915 B43_WARN_ON(mac_addr);
916 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
917 }
918 keyconf->hw_key_idx = index;
919 dev->key[index].keyconf = keyconf;
920
921 return 0;
922}
923
924static int b43_key_clear(struct b43_wldev *dev, int index)
925{
926 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
927 return -EINVAL;
928 do_key_write(dev, index, B43_SEC_ALGO_NONE,
929 NULL, B43_SEC_KEYSIZE, NULL);
930 if ((index <= 3) && !b43_new_kidx_api(dev)) {
931 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
932 NULL, B43_SEC_KEYSIZE, NULL);
933 }
934 dev->key[index].keyconf = NULL;
935
936 return 0;
937}
938
939static void b43_clear_keys(struct b43_wldev *dev)
940{
941 int i;
942
943 for (i = 0; i < dev->max_nr_keys; i++)
944 b43_key_clear(dev, i);
945}
946
9cf7f247
MB		 947static void b43_dump_keymemory(struct b43_wldev *dev)
948{
949 unsigned int i, index, offset;
950 DECLARE_MAC_BUF(macbuf);
951 u8 mac[ETH_ALEN];
952 u16 algo;
953 u32 rcmta0;
954 u16 rcmta1;
955 u64 hf;
956 struct b43_key *key;
957
958 if (!b43_debug(dev, B43_DBG_KEYS))
959 return;
960
961 hf = b43_hf_read(dev);
962 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
963 !!(hf & B43_HF_USEDEFKEYS));
964 for (index = 0; index < dev->max_nr_keys; index++) {
965 key = &(dev->key[index]);
966 printk(KERN_DEBUG "Key slot %02u: %s",
967 index, (key->keyconf == NULL) ? " " : "*");
968 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
969 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
970 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
971 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
972 }
973
974 algo = b43_shm_read16(dev, B43_SHM_SHARED,
975 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
976 printk(" Algo: %04X/%02X", algo, key->algorithm);
977
978 if (index >= 4) {
979 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
980 ((index - 4) * 2) + 0);
981 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
982 ((index - 4) * 2) + 1);
983 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
984 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
985 printk(" MAC: %s",
986 print_mac(macbuf, mac));
987 } else
988 printk(" DEFAULT KEY");
989 printk("\n");
990 }
991}
992
e4d6b795
MB		 993void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
994{
995 u32 macctl;
996 u16 ucstat;
997 bool hwps;
998 bool awake;
999 int i;
1000
1001 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1002 (ps_flags & B43_PS_DISABLED));
1003 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1004
1005 if (ps_flags & B43_PS_ENABLED) {
1006 hwps = 1;
1007 } else if (ps_flags & B43_PS_DISABLED) {
1008 hwps = 0;
1009 } else {
1010 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1011 // and thus is not an AP and we are associated, set bit 25
1012 }
1013 if (ps_flags & B43_PS_AWAKE) {
1014 awake = 1;
1015 } else if (ps_flags & B43_PS_ASLEEP) {
1016 awake = 0;
1017 } else {
1018 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1019 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1020 // successful, set bit26
1021 }
1022
1023/* FIXME: For now we force awake-on and hwps-off */
1024 hwps = 0;
1025 awake = 1;
1026
1027 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1028 if (hwps)
1029 macctl |= B43_MACCTL_HWPS;
1030 else
1031 macctl &= ~B43_MACCTL_HWPS;
1032 if (awake)
1033 macctl |= B43_MACCTL_AWAKE;
1034 else
1035 macctl &= ~B43_MACCTL_AWAKE;
1036 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1037 /* Commit write */
1038 b43_read32(dev, B43_MMIO_MACCTL);
1039 if (awake && dev->dev->id.revision >= 5) {
1040 /* Wait for the microcode to wake up. */
1041 for (i = 0; i < 100; i++) {
1042 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1043 B43_SHM_SH_UCODESTAT);
1044 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1045 break;
1046 udelay(10);
1047 }
1048 }
1049}
1050
e4d6b795
MB		 1051void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1052{
1053 u32 tmslow;
1054 u32 macctl;
1055
1056 flags |= B43_TMSLOW_PHYCLKEN;
1057 flags |= B43_TMSLOW_PHYRESET;
1058 ssb_device_enable(dev->dev, flags);
1059 msleep(2); /* Wait for the PLL to turn on. */
1060
1061 /* Now take the PHY out of Reset again */
1062 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1063 tmslow |= SSB_TMSLOW_FGC;
1064 tmslow &= ~B43_TMSLOW_PHYRESET;
1065 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1066 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1067 msleep(1);
1068 tmslow &= ~SSB_TMSLOW_FGC;
1069 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1070 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1071 msleep(1);
1072
fb11137a
MB		 1073 /* Turn Analog ON, but only if we already know the PHY-type.
1074 * This protects against very early setup where we don't know the
1075 * PHY-type, yet. wireless_core_reset will be called once again later,
1076 * when we know the PHY-type. */
1077 if (dev->phy.ops)
cb24f57f 1078 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1079
1080 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1081 macctl &= ~B43_MACCTL_GMODE;
1082 if (flags & B43_TMSLOW_GMODE)
1083 macctl |= B43_MACCTL_GMODE;
1084 macctl |= B43_MACCTL_IHR_ENABLED;
1085 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1086}
1087
1088static void handle_irq_transmit_status(struct b43_wldev *dev)
1089{
1090 u32 v0, v1;
1091 u16 tmp;
1092 struct b43_txstatus stat;
1093
1094 while (1) {
1095 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1096 if (!(v0 & 0x00000001))
1097 break;
1098 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1099
1100 stat.cookie = (v0 >> 16);
1101 stat.seq = (v1 & 0x0000FFFF);
1102 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1103 tmp = (v0 & 0x0000FFFF);
1104 stat.frame_count = ((tmp & 0xF000) >> 12);
1105 stat.rts_count = ((tmp & 0x0F00) >> 8);
1106 stat.supp_reason = ((tmp & 0x001C) >> 2);
1107 stat.pm_indicated = !!(tmp & 0x0080);
1108 stat.intermediate = !!(tmp & 0x0040);
1109 stat.for_ampdu = !!(tmp & 0x0020);
1110 stat.acked = !!(tmp & 0x0002);
1111
1112 b43_handle_txstatus(dev, &stat);
1113 }
1114}
1115
1116static void drain_txstatus_queue(struct b43_wldev *dev)
1117{
1118 u32 dummy;
1119
1120 if (dev->dev->id.revision < 5)
1121 return;
1122 /* Read all entries from the microcode TXstatus FIFO
1123 * and throw them away.
1124 */
1125 while (1) {
1126 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1127 if (!(dummy & 0x00000001))
1128 break;
1129 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1130 }
1131}
1132
1133static u32 b43_jssi_read(struct b43_wldev *dev)
1134{
1135 u32 val = 0;
1136
1137 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1138 val <<= 16;
1139 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1140
1141 return val;
1142}
1143
1144static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1145{
1146 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1147 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1148}
1149
1150static void b43_generate_noise_sample(struct b43_wldev *dev)
1151{
1152 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1153 b43_write32(dev, B43_MMIO_MACCMD,
1154 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1155}
1156
1157static void b43_calculate_link_quality(struct b43_wldev *dev)
1158{
1159 /* Top half of Link Quality calculation. */
1160
ef1a628d
MB		 1161 if (dev->phy.type != B43_PHYTYPE_G)
1162 return;
e4d6b795
MB		 1163 if (dev->noisecalc.calculation_running)
1164 return;
e4d6b795
MB		 1165 dev->noisecalc.calculation_running = 1;
1166 dev->noisecalc.nr_samples = 0;
1167
1168 b43_generate_noise_sample(dev);
1169}
1170
1171static void handle_irq_noise(struct b43_wldev *dev)
1172{
ef1a628d 1173 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1174 u16 tmp;
1175 u8 noise[4];
1176 u8 i, j;
1177 s32 average;
1178
1179 /* Bottom half of Link Quality calculation. */
1180
ef1a628d
MB		 1181 if (dev->phy.type != B43_PHYTYPE_G)
1182 return;
1183
98a3b2fe
MB		 1184 /* Possible race condition: It might be possible that the user
1185 * changed to a different channel in the meantime since we
1186 * started the calculation. We ignore that fact, since it's
1187 * not really that much of a problem. The background noise is
1188 * an estimation only anyway. Slightly wrong results will get damped
1189 * by the averaging of the 8 sample rounds. Additionally the
1190 * value is shortlived. So it will be replaced by the next noise
1191 * calculation round soon. */
1192
e4d6b795 1193 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1194 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1195 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1196 noise[2] == 0x7F || noise[3] == 0x7F)
1197 goto generate_new;
1198
1199 /* Get the noise samples. */
1200 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1201 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1202 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1203 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1204 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1205 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1206 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1207 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1208 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1209 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1210 dev->noisecalc.nr_samples++;
1211 if (dev->noisecalc.nr_samples == 8) {
1212 /* Calculate the Link Quality by the noise samples. */
1213 average = 0;
1214 for (i = 0; i < 8; i++) {
1215 for (j = 0; j < 4; j++)
1216 average += dev->noisecalc.samples[i][j];
1217 }
1218 average /= (8 * 4);
1219 average *= 125;
1220 average += 64;
1221 average /= 128;
1222 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1223 tmp = (tmp / 128) & 0x1F;
1224 if (tmp >= 8)
1225 average += 2;
1226 else
1227 average -= 25;
1228 if (tmp == 8)
1229 average -= 72;
1230 else
1231 average -= 48;
1232
1233 dev->stats.link_noise = average;
e4d6b795
MB		 1234 dev->noisecalc.calculation_running = 0;
1235 return;
1236 }
98a3b2fe 1237generate_new:
e4d6b795
MB		 1238 b43_generate_noise_sample(dev);
1239}
1240
1241static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1242{
05c914fe 1243 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1244 ///TODO: PS TBTT
1245 } else {
1246 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1247 b43_power_saving_ctl_bits(dev, 0);
1248 }
05c914fe 1249 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1250 dev->dfq_valid = 1;
e4d6b795
MB		 1251}
1252
1253static void handle_irq_atim_end(struct b43_wldev *dev)
1254{
aa6c7ae2
MB		 1255 if (dev->dfq_valid) {
1256 b43_write32(dev, B43_MMIO_MACCMD,
1257 b43_read32(dev, B43_MMIO_MACCMD)
1258 | B43_MACCMD_DFQ_VALID);
1259 dev->dfq_valid = 0;
1260 }
e4d6b795
MB		 1261}
1262
1263static void handle_irq_pmq(struct b43_wldev *dev)
1264{
1265 u32 tmp;
1266
1267 //TODO: AP mode.
1268
1269 while (1) {
1270 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1271 if (!(tmp & 0x00000008))
1272 break;
1273 }
1274 /* 16bit write is odd, but correct. */
1275 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1276}
1277
1278static void b43_write_template_common(struct b43_wldev *dev,
1279 const u8 * data, u16 size,
1280 u16 ram_offset,
1281 u16 shm_size_offset, u8 rate)
1282{
1283 u32 i, tmp;
1284 struct b43_plcp_hdr4 plcp;
1285
1286 plcp.data = 0;
1287 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1288 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1289 ram_offset += sizeof(u32);
1290 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1291 * So leave the first two bytes of the next write blank.
1292 */
1293 tmp = (u32) (data[0]) << 16;
1294 tmp |= (u32) (data[1]) << 24;
1295 b43_ram_write(dev, ram_offset, tmp);
1296 ram_offset += sizeof(u32);
1297 for (i = 2; i < size; i += sizeof(u32)) {
1298 tmp = (u32) (data[i + 0]);
1299 if (i + 1 < size)
1300 tmp |= (u32) (data[i + 1]) << 8;
1301 if (i + 2 < size)
1302 tmp |= (u32) (data[i + 2]) << 16;
1303 if (i + 3 < size)
1304 tmp |= (u32) (data[i + 3]) << 24;
1305 b43_ram_write(dev, ram_offset + i - 2, tmp);
1306 }
1307 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1308 size + sizeof(struct b43_plcp_hdr6));
1309}
1310
5042c507
MB		 1311/* Check if the use of the antenna that ieee80211 told us to
1312 * use is possible. This will fall back to DEFAULT.
1313 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1314u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1315 u8 antenna_nr)
1316{
1317 u8 antenna_mask;
1318
1319 if (antenna_nr == 0) {
1320 /* Zero means "use default antenna". That's always OK. */
1321 return 0;
1322 }
1323
1324 /* Get the mask of available antennas. */
1325 if (dev->phy.gmode)
1326 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1327 else
1328 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1329
1330 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1331 /* This antenna is not available. Fall back to default. */
1332 return 0;
1333 }
1334
1335 return antenna_nr;
1336}
1337
5042c507
MB		 1338/* Convert a b43 antenna number value to the PHY TX control value. */
1339static u16 b43_antenna_to_phyctl(int antenna)
1340{
1341 switch (antenna) {
1342 case B43_ANTENNA0:
1343 return B43_TXH_PHY_ANT0;
1344 case B43_ANTENNA1:
1345 return B43_TXH_PHY_ANT1;
1346 case B43_ANTENNA2:
1347 return B43_TXH_PHY_ANT2;
1348 case B43_ANTENNA3:
1349 return B43_TXH_PHY_ANT3;
1350 case B43_ANTENNA_AUTO:
1351 return B43_TXH_PHY_ANT01AUTO;
1352 }
1353 B43_WARN_ON(1);
1354 return 0;
1355}
1356
e4d6b795
MB		 1357static void b43_write_beacon_template(struct b43_wldev *dev,
1358 u16 ram_offset,
5042c507 1359 u16 shm_size_offset)
e4d6b795 1360{
47f76ca3 1361 unsigned int i, len, variable_len;
e66fee6a
MB		 1362 const struct ieee80211_mgmt *bcn;
1363 const u8 *ie;
1364 bool tim_found = 0;
5042c507
MB		 1365 unsigned int rate;
1366 u16 ctl;
1367 int antenna;
e039fa4a 1368 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1369
e66fee6a
MB		 1370 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1371 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1372 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1373 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1374
1375 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1376 len, ram_offset, shm_size_offset, rate);
e66fee6a 1377
5042c507 1378 /* Write the PHY TX control parameters. */
0f4ac38b 1379 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1380 antenna = b43_antenna_to_phyctl(antenna);
1381 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1382 /* We can't send beacons with short preamble. Would get PHY errors. */
1383 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1384 ctl &= ~B43_TXH_PHY_ANT;
1385 ctl &= ~B43_TXH_PHY_ENC;
1386 ctl |= antenna;
1387 if (b43_is_cck_rate(rate))
1388 ctl |= B43_TXH_PHY_ENC_CCK;
1389 else
1390 ctl |= B43_TXH_PHY_ENC_OFDM;
1391 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1392
e66fee6a
MB		 1393 /* Find the position of the TIM and the DTIM_period value
1394 * and write them to SHM. */
1395 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1396 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1397 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1398 uint8_t ie_id, ie_len;
1399
1400 ie_id = ie[i];
1401 ie_len = ie[i + 1];
1402 if (ie_id == 5) {
1403 u16 tim_position;
1404 u16 dtim_period;
1405 /* This is the TIM Information Element */
1406
1407 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1408 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1409 break;
1410 /* A valid TIM is at least 4 bytes long. */
1411 if (ie_len < 4)
1412 break;
1413 tim_found = 1;
1414
1415 tim_position = sizeof(struct b43_plcp_hdr6);
1416 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1417 tim_position += i;
1418
1419 dtim_period = ie[i + 3];
1420
1421 b43_shm_write16(dev, B43_SHM_SHARED,
1422 B43_SHM_SH_TIMBPOS, tim_position);
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1424 B43_SHM_SH_DTIMPER, dtim_period);
1425 break;
1426 }
1427 i += ie_len + 2;
1428 }
1429 if (!tim_found) {
04dea136
JB		 1430 /*
1431 * If ucode wants to modify TIM do it behind the beacon, this
1432 * will happen, for example, when doing mesh networking.
1433 */
1434 b43_shm_write16(dev, B43_SHM_SHARED,
1435 B43_SHM_SH_TIMBPOS,
1436 len + sizeof(struct b43_plcp_hdr6));
1437 b43_shm_write16(dev, B43_SHM_SHARED,
1438 B43_SHM_SH_DTIMPER, 0);
1439 }
1440 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1441}
1442
1443static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
8318d78a
JB		 1444 u16 shm_offset, u16 size,
1445 struct ieee80211_rate *rate)
e4d6b795
MB		 1446{
1447 struct b43_plcp_hdr4 plcp;
1448 u32 tmp;
1449 __le16 dur;
1450
1451 plcp.data = 0;
8318d78a 1452 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
e4d6b795 1453 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1454 dev->wl->vif, size,
8318d78a 1455 rate);
e4d6b795
MB		 1456 /* Write PLCP in two parts and timing for packet transfer */
1457 tmp = le32_to_cpu(plcp.data);
1458 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1459 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1461}
1462
1463/* Instead of using custom probe response template, this function
1464 * just patches custom beacon template by:
1465 * 1) Changing packet type
1466 * 2) Patching duration field
1467 * 3) Stripping TIM
1468 */
e66fee6a 1469static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
8318d78a
JB		 1470 u16 *dest_size,
1471 struct ieee80211_rate *rate)
e4d6b795
MB		 1472{
1473 const u8 *src_data;
1474 u8 *dest_data;
1475 u16 src_size, elem_size, src_pos, dest_pos;
1476 __le16 dur;
1477 struct ieee80211_hdr *hdr;
e66fee6a
MB		 1478 size_t ie_start;
1479
1480 src_size = dev->wl->current_beacon->len;
1481 src_data = (const u8 *)dev->wl->current_beacon->data;
e4d6b795 1482
e66fee6a
MB		 1483 /* Get the start offset of the variable IEs in the packet. */
1484 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1485 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
e4d6b795 1486
e66fee6a 1487 if (B43_WARN_ON(src_size < ie_start))
e4d6b795 1488 return NULL;
e4d6b795
MB		 1489
1490 dest_data = kmalloc(src_size, GFP_ATOMIC);
1491 if (unlikely(!dest_data))
1492 return NULL;
1493
e66fee6a
MB		 1494 /* Copy the static data and all Information Elements, except the TIM. */
1495 memcpy(dest_data, src_data, ie_start);
1496 src_pos = ie_start;
1497 dest_pos = ie_start;
1498 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
e4d6b795 1499 elem_size = src_data[src_pos + 1] + 2;
e66fee6a
MB		 1500 if (src_data[src_pos] == 5) {
1501 /* This is the TIM. */
1502 continue;
e4d6b795 1503 }
e66fee6a
MB		 1504 memcpy(dest_data + dest_pos, src_data + src_pos,
1505 elem_size);
1506 dest_pos += elem_size;
e4d6b795
MB		 1507 }
1508 *dest_size = dest_pos;
1509 hdr = (struct ieee80211_hdr *)dest_data;
1510
1511 /* Set the frame control. */
1512 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1513 IEEE80211_STYPE_PROBE_RESP);
1514 dur = ieee80211_generic_frame_duration(dev->wl->hw,
32bfd35d 1515 dev->wl->vif, *dest_size,
8318d78a 1516 rate);
e4d6b795
MB		 1517 hdr->duration_id = dur;
1518
1519 return dest_data;
1520}
1521
1522static void b43_write_probe_resp_template(struct b43_wldev *dev,
1523 u16 ram_offset,
8318d78a
JB		 1524 u16 shm_size_offset,
1525 struct ieee80211_rate *rate)
e4d6b795 1526{
e66fee6a 1527 const u8 *probe_resp_data;
e4d6b795
MB		 1528 u16 size;
1529
e66fee6a 1530 size = dev->wl->current_beacon->len;
e4d6b795
MB		 1531 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1532 if (unlikely(!probe_resp_data))
1533 return;
1534
1535 /* Looks like PLCP headers plus packet timings are stored for
1536 * all possible basic rates
1537 */
8318d78a
JB		 1538 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1539 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1540 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1541 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
e4d6b795
MB		 1542
1543 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1544 b43_write_template_common(dev, probe_resp_data,
8318d78a
JB		 1545 size, ram_offset, shm_size_offset,
1546 rate->hw_value);
e4d6b795
MB		 1547 kfree(probe_resp_data);
1548}
1549
6b4bec01
MB		 1550static void b43_upload_beacon0(struct b43_wldev *dev)
1551{
1552 struct b43_wl *wl = dev->wl;
1553
1554 if (wl->beacon0_uploaded)
1555 return;
1556 b43_write_beacon_template(dev, 0x68, 0x18);
1557 /* FIXME: Probe resp upload doesn't really belong here,
1558 * but we don't use that feature anyway. */
1559 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1560 &__b43_ratetable[3]);
1561 wl->beacon0_uploaded = 1;
1562}
1563
1564static void b43_upload_beacon1(struct b43_wldev *dev)
1565{
1566 struct b43_wl *wl = dev->wl;
1567
1568 if (wl->beacon1_uploaded)
1569 return;
1570 b43_write_beacon_template(dev, 0x468, 0x1A);
1571 wl->beacon1_uploaded = 1;
1572}
1573
c97a4ccc
MB		 1574static void handle_irq_beacon(struct b43_wldev *dev)
1575{
1576 struct b43_wl *wl = dev->wl;
1577 u32 cmd, beacon0_valid, beacon1_valid;
1578
05c914fe
JB		 1579 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1580 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1581 return;
1582
1583 /* This is the bottom half of the asynchronous beacon update. */
1584
1585 /* Ignore interrupt in the future. */
1586 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1587
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1590 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1591
1592 /* Schedule interrupt manually, if busy. */
1593 if (beacon0_valid && beacon1_valid) {
1594 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1595 dev->irq_savedstate |= B43_IRQ_BEACON;
1596 return;
1597 }
1598
6b4bec01
MB		 1599 if (unlikely(wl->beacon_templates_virgin)) {
1600 /* We never uploaded a beacon before.
1601 * Upload both templates now, but only mark one valid. */
1602 wl->beacon_templates_virgin = 0;
1603 b43_upload_beacon0(dev);
1604 b43_upload_beacon1(dev);
c97a4ccc
MB		 1605 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1606 cmd |= B43_MACCMD_BEACON0_VALID;
1607 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1608 } else {
1609 if (!beacon0_valid) {
1610 b43_upload_beacon0(dev);
1611 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1612 cmd |= B43_MACCMD_BEACON0_VALID;
1613 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1614 } else if (!beacon1_valid) {
1615 b43_upload_beacon1(dev);
1616 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1617 cmd |= B43_MACCMD_BEACON1_VALID;
1618 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1619 }
c97a4ccc
MB		 1620 }
1621}
1622
a82d9922
MB		 1623static void b43_beacon_update_trigger_work(struct work_struct *work)
1624{
1625 struct b43_wl *wl = container_of(work, struct b43_wl,
1626 beacon_update_trigger);
1627 struct b43_wldev *dev;
1628
1629 mutex_lock(&wl->mutex);
1630 dev = wl->current_dev;
1631 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
a82d9922 1632 spin_lock_irq(&wl->irq_lock);
c97a4ccc
MB		 1633 /* update beacon right away or defer to irq */
1634 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1635 handle_irq_beacon(dev);
1636 /* The handler might have updated the IRQ mask. */
1637 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1638 dev->irq_savedstate);
1639 mmiowb();
a82d9922
MB		 1640 spin_unlock_irq(&wl->irq_lock);
1641 }
1642 mutex_unlock(&wl->mutex);
1643}
1644
d4df6f1a
MB		 1645/* Asynchronously update the packet templates in template RAM.
1646 * Locking: Requires wl->irq_lock to be locked. */
9d139c81 1647static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1648{
9d139c81
JB		 1649 struct sk_buff *beacon;
1650
e66fee6a
MB		 1651 /* This is the top half of the ansynchronous beacon update.
1652 * The bottom half is the beacon IRQ.
1653 * Beacon update must be asynchronous to avoid sending an
1654 * invalid beacon. This can happen for example, if the firmware
1655 * transmits a beacon while we are updating it. */
e4d6b795 1656
9d139c81
JB		 1657 /* We could modify the existing beacon and set the aid bit in
1658 * the TIM field, but that would probably require resizing and
1659 * moving of data within the beacon template.
1660 * Simply request a new beacon and let mac80211 do the hard work. */
1661 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1662 if (unlikely(!beacon))
1663 return;
1664
e66fee6a
MB		 1665 if (wl->current_beacon)
1666 dev_kfree_skb_any(wl->current_beacon);
1667 wl->current_beacon = beacon;
1668 wl->beacon0_uploaded = 0;
1669 wl->beacon1_uploaded = 0;
a82d9922 1670 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
e4d6b795
MB		 1671}
1672
e4d6b795
MB		 1673static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1674{
1675 b43_time_lock(dev);
1676 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1677 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1678 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1679 } else {
1680 b43_write16(dev, 0x606, (beacon_int >> 6));
1681 b43_write16(dev, 0x610, beacon_int);
1682 }
1683 b43_time_unlock(dev);
a82d9922 1684 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1685}
1686
afa83e23
MB		 1687static void b43_handle_firmware_panic(struct b43_wldev *dev)
1688{
1689 u16 reason;
1690
1691 /* Read the register that contains the reason code for the panic. */
1692 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1693 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1694
1695 switch (reason) {
1696 default:
1697 b43dbg(dev->wl, "The panic reason is unknown.\n");
1698 /* fallthrough */
1699 case B43_FWPANIC_DIE:
1700 /* Do not restart the controller or firmware.
1701 * The device is nonfunctional from now on.
1702 * Restarting would result in this panic to trigger again,
1703 * so we avoid that recursion. */
1704 break;
1705 case B43_FWPANIC_RESTART:
1706 b43_controller_restart(dev, "Microcode panic");
1707 break;
1708 }
1709}
1710
e4d6b795
MB		 1711static void handle_irq_ucode_debug(struct b43_wldev *dev)
1712{
e48b0eeb 1713 unsigned int i, cnt;
53c06856 1714 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1715 __le16 *buf;
1716
1717 /* The proprietary firmware doesn't have this IRQ. */
1718 if (!dev->fw.opensource)
1719 return;
1720
afa83e23
MB		 1721 /* Read the register that contains the reason code for this IRQ. */
1722 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1723
e48b0eeb
MB		 1724 switch (reason) {
1725 case B43_DEBUGIRQ_PANIC:
afa83e23 1726 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1727 break;
1728 case B43_DEBUGIRQ_DUMP_SHM:
1729 if (!B43_DEBUG)
1730 break; /* Only with driver debugging enabled. */
1731 buf = kmalloc(4096, GFP_ATOMIC);
1732 if (!buf) {
1733 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1734 goto out;
1735 }
1736 for (i = 0; i < 4096; i += 2) {
1737 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1738 buf[i / 2] = cpu_to_le16(tmp);
1739 }
1740 b43info(dev->wl, "Shared memory dump:\n");
1741 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1742 16, 2, buf, 4096, 1);
1743 kfree(buf);
1744 break;
1745 case B43_DEBUGIRQ_DUMP_REGS:
1746 if (!B43_DEBUG)
1747 break; /* Only with driver debugging enabled. */
1748 b43info(dev->wl, "Microcode register dump:\n");
1749 for (i = 0, cnt = 0; i < 64; i++) {
1750 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1751 if (cnt == 0)
1752 printk(KERN_INFO);
1753 printk("r%02u: 0x%04X ", i, tmp);
1754 cnt++;
1755 if (cnt == 6) {
1756 printk("\n");
1757 cnt = 0;
1758 }
1759 }
1760 printk("\n");
1761 break;
53c06856
MB		 1762 case B43_DEBUGIRQ_MARKER:
1763 if (!B43_DEBUG)
1764 break; /* Only with driver debugging enabled. */
1765 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1766 B43_MARKER_ID_REG);
1767 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1768 B43_MARKER_LINE_REG);
1769 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1770 "at line number %u\n",
1771 marker_id, marker_line);
1772 break;
e48b0eeb
MB		 1773 default:
1774 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1775 reason);
1776 }
1777out:
afa83e23
MB		 1778 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1779 b43_shm_write16(dev, B43_SHM_SCRATCH,
1780 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1781}
1782
1783/* Interrupt handler bottom-half */
1784static void b43_interrupt_tasklet(struct b43_wldev *dev)
1785{
1786 u32 reason;
1787 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1788 u32 merged_dma_reason = 0;
21954c36 1789 int i;
e4d6b795
MB		 1790 unsigned long flags;
1791
1792 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1793
1794 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1795
1796 reason = dev->irq_reason;
1797 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1798 dma_reason[i] = dev->dma_reason[i];
1799 merged_dma_reason |= dma_reason[i];
1800 }
1801
1802 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1803 b43err(dev->wl, "MAC transmission error\n");
1804
00e0b8cb 1805 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1806 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1807 rmb();
1808 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1809 atomic_set(&dev->phy.txerr_cnt,
1810 B43_PHY_TX_BADNESS_LIMIT);
1811 b43err(dev->wl, "Too many PHY TX errors, "
1812 "restarting the controller\n");
1813 b43_controller_restart(dev, "PHY TX errors");
1814 }
1815 }
e4d6b795
MB		 1816
1817 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1818 B43_DMAIRQ_NONFATALMASK))) {
1819 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1820 b43err(dev->wl, "Fatal DMA error: "
1821 "0x%08X, 0x%08X, 0x%08X, "
1822 "0x%08X, 0x%08X, 0x%08X\n",
1823 dma_reason[0], dma_reason[1],
1824 dma_reason[2], dma_reason[3],
1825 dma_reason[4], dma_reason[5]);
1826 b43_controller_restart(dev, "DMA error");
1827 mmiowb();
1828 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1829 return;
1830 }
1831 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1832 b43err(dev->wl, "DMA error: "
1833 "0x%08X, 0x%08X, 0x%08X, "
1834 "0x%08X, 0x%08X, 0x%08X\n",
1835 dma_reason[0], dma_reason[1],
1836 dma_reason[2], dma_reason[3],
1837 dma_reason[4], dma_reason[5]);
1838 }
1839 }
1840
1841 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1842 handle_irq_ucode_debug(dev);
1843 if (reason & B43_IRQ_TBTT_INDI)
1844 handle_irq_tbtt_indication(dev);
1845 if (reason & B43_IRQ_ATIM_END)
1846 handle_irq_atim_end(dev);
1847 if (reason & B43_IRQ_BEACON)
1848 handle_irq_beacon(dev);
1849 if (reason & B43_IRQ_PMQ)
1850 handle_irq_pmq(dev);
21954c36
MB		 1851 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1852 ;/* TODO */
1853 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1854 handle_irq_noise(dev);
1855
1856 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1857 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1858 if (b43_using_pio_transfers(dev))
1859 b43_pio_rx(dev->pio.rx_queue);
1860 else
1861 b43_dma_rx(dev->dma.rx_ring);
1862 }
e4d6b795
MB		 1863 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1864 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1865 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1866 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1867 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1868
21954c36 1869 if (reason & B43_IRQ_TX_OK)
e4d6b795 1870 handle_irq_transmit_status(dev);
e4d6b795 1871
e4d6b795
MB		 1872 b43_interrupt_enable(dev, dev->irq_savedstate);
1873 mmiowb();
1874 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1875}
1876
e4d6b795
MB		 1877static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1878{
e4d6b795
MB		 1879 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1880
1881 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1882 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1883 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1884 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1885 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1886 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1887}
1888
1889/* Interrupt handler top-half */
1890static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1891{
1892 irqreturn_t ret = IRQ_NONE;
1893 struct b43_wldev *dev = dev_id;
1894 u32 reason;
1895
1896 if (!dev)
1897 return IRQ_NONE;
1898
1899 spin_lock(&dev->wl->irq_lock);
1900
1901 if (b43_status(dev) < B43_STAT_STARTED)
1902 goto out;
1903 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1904 if (reason == 0xffffffff) /* shared IRQ */
1905 goto out;
1906 ret = IRQ_HANDLED;
1907 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1908 if (!reason)
1909 goto out;
1910
1911 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1912 & 0x0001DC00;
1913 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1914 & 0x0000DC00;
1915 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1916 & 0x0000DC00;
1917 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1918 & 0x0001DC00;
1919 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1920 & 0x0000DC00;
1921 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1922 & 0x0000DC00;
1923
1924 b43_interrupt_ack(dev, reason);
1925 /* disable all IRQs. They are enabled again in the bottom half. */
1926 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1927 /* save the reason code and call our bottom half. */
1928 dev->irq_reason = reason;
1929 tasklet_schedule(&dev->isr_tasklet);
1930 out:
1931 mmiowb();
1932 spin_unlock(&dev->wl->irq_lock);
1933
1934 return ret;
1935}
1936
1a9f5093 1937void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1938{
1939 release_firmware(fw->data);
1940 fw->data = NULL;
1941 fw->filename = NULL;
1942}
1943
e4d6b795
MB		 1944static void b43_release_firmware(struct b43_wldev *dev)
1945{
1a9f5093
MB		 1946 b43_do_release_fw(&dev->fw.ucode);
1947 b43_do_release_fw(&dev->fw.pcm);
1948 b43_do_release_fw(&dev->fw.initvals);
1949 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1950}
1951
eb189d8b 1952static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1953{
eb189d8b
MB		 1954 const char *text;
1955
1956 text = "You must go to "
c557289c
MB		 1957 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware "
1958 "and download the correct firmware for this driver version. "
1959 "Please carefully read all instructions on this website.\n";
eb189d8b
MB		 1960 if (error)
1961 b43err(wl, text);
1962 else
1963 b43warn(wl, text);
e4d6b795
MB		 1964}
1965
1a9f5093
MB		 1966int b43_do_request_fw(struct b43_request_fw_context *ctx,
1967 const char *name,
1968 struct b43_firmware_file *fw)
e4d6b795 1969{
61cb5dd6 1970 const struct firmware *blob;
e4d6b795
MB		 1971 struct b43_fw_header *hdr;
1972 u32 size;
1973 int err;
1974
61cb5dd6
MB		 1975 if (!name) {
1976 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1977 /* FIXME: We should probably keep it anyway, to save some headache
1978 * on suspend/resume with multiband devices. */
1979 b43_do_release_fw(fw);
e4d6b795 1980 return 0;
61cb5dd6
MB		 1981 }
1982 if (fw->filename) {
1a9f5093
MB		 1983 if ((fw->type == ctx->req_type) &&
1984 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 1985 return 0; /* Already have this fw. */
1986 /* Free the cached firmware first. */
1a9f5093
MB		 1987 /* FIXME: We should probably do this later after we successfully
1988 * got the new fw. This could reduce headache with multiband devices.
1989 * We could also redesign this to cache the firmware for all possible
1990 * bands all the time. */
1991 b43_do_release_fw(fw);
61cb5dd6 1992 }
e4d6b795 1993
1a9f5093
MB		 1994 switch (ctx->req_type) {
1995 case B43_FWTYPE_PROPRIETARY:
1996 snprintf(ctx->fwname, sizeof(ctx->fwname),
1997 "b43%s/%s.fw",
1998 modparam_fwpostfix, name);
1999 break;
2000 case B43_FWTYPE_OPENSOURCE:
2001 snprintf(ctx->fwname, sizeof(ctx->fwname),
2002 "b43-open%s/%s.fw",
2003 modparam_fwpostfix, name);
2004 break;
2005 default:
2006 B43_WARN_ON(1);
2007 return -ENOSYS;
2008 }
2009 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2010 if (err == -ENOENT) {
1a9f5093
MB		 2011 snprintf(ctx->errors[ctx->req_type],
2012 sizeof(ctx->errors[ctx->req_type]),
2013 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2014 return err;
2015 } else if (err) {
1a9f5093
MB		 2016 snprintf(ctx->errors[ctx->req_type],
2017 sizeof(ctx->errors[ctx->req_type]),
2018 "Firmware file \"%s\" request failed (err=%d)\n",
2019 ctx->fwname, err);
e4d6b795
MB		 2020 return err;
2021 }
61cb5dd6 2022 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2023 goto err_format;
61cb5dd6 2024 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2025 switch (hdr->type) {
2026 case B43_FW_TYPE_UCODE:
2027 case B43_FW_TYPE_PCM:
2028 size = be32_to_cpu(hdr->size);
61cb5dd6 2029 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2030 goto err_format;
2031 /* fallthrough */
2032 case B43_FW_TYPE_IV:
2033 if (hdr->ver != 1)
2034 goto err_format;
2035 break;
2036 default:
2037 goto err_format;
2038 }
2039
61cb5dd6
MB		 2040 fw->data = blob;
2041 fw->filename = name;
1a9f5093 2042 fw->type = ctx->req_type;
61cb5dd6
MB		 2043
2044 return 0;
e4d6b795
MB		 2045
2046err_format:
1a9f5093
MB		 2047 snprintf(ctx->errors[ctx->req_type],
2048 sizeof(ctx->errors[ctx->req_type]),
2049 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2050 release_firmware(blob);
2051
e4d6b795
MB		 2052 return -EPROTO;
2053}
2054
1a9f5093 2055static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2056{
1a9f5093
MB		 2057 struct b43_wldev *dev = ctx->dev;
2058 struct b43_firmware *fw = &ctx->dev->fw;
2059 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2060 const char *filename;
2061 u32 tmshigh;
2062 int err;
2063
61cb5dd6 2064 /* Get microcode */
e4d6b795 2065 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2066 if ((rev >= 5) && (rev <= 10))
2067 filename = "ucode5";
2068 else if ((rev >= 11) && (rev <= 12))
2069 filename = "ucode11";
2070 else if (rev >= 13)
2071 filename = "ucode13";
2072 else
2073 goto err_no_ucode;
1a9f5093 2074 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2075 if (err)
2076 goto err_load;
2077
2078 /* Get PCM code */
2079 if ((rev >= 5) && (rev <= 10))
2080 filename = "pcm5";
2081 else if (rev >= 11)
2082 filename = NULL;
2083 else
2084 goto err_no_pcm;
68217832 2085 fw->pcm_request_failed = 0;
1a9f5093 2086 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2087 if (err == -ENOENT) {
2088 /* We did not find a PCM file? Not fatal, but
2089 * core rev <= 10 must do without hwcrypto then. */
2090 fw->pcm_request_failed = 1;
2091 } else if (err)
61cb5dd6
MB		 2092 goto err_load;
2093
2094 /* Get initvals */
2095 switch (dev->phy.type) {
2096 case B43_PHYTYPE_A:
2097 if ((rev >= 5) && (rev <= 10)) {
2098 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2099 filename = "a0g1initvals5";
2100 else
2101 filename = "a0g0initvals5";
2102 } else
2103 goto err_no_initvals;
2104 break;
2105 case B43_PHYTYPE_G:
e4d6b795 2106 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2107 filename = "b0g0initvals5";
e4d6b795 2108 else if (rev >= 13)
e9304882 2109 filename = "b0g0initvals13";
e4d6b795 2110 else
61cb5dd6
MB		 2111 goto err_no_initvals;
2112 break;
2113 case B43_PHYTYPE_N:
2114 if ((rev >= 11) && (rev <= 12))
2115 filename = "n0initvals11";
2116 else
2117 goto err_no_initvals;
2118 break;
2119 default:
2120 goto err_no_initvals;
e4d6b795 2121 }
1a9f5093 2122 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2123 if (err)
2124 goto err_load;
2125
2126 /* Get bandswitch initvals */
2127 switch (dev->phy.type) {
2128 case B43_PHYTYPE_A:
2129 if ((rev >= 5) && (rev <= 10)) {
2130 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2131 filename = "a0g1bsinitvals5";
2132 else
2133 filename = "a0g0bsinitvals5";
2134 } else if (rev >= 11)
2135 filename = NULL;
2136 else
2137 goto err_no_initvals;
2138 break;
2139 case B43_PHYTYPE_G:
e4d6b795 2140 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2141 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2142 else if (rev >= 11)
2143 filename = NULL;
2144 else
e4d6b795 2145 goto err_no_initvals;
61cb5dd6
MB		 2146 break;
2147 case B43_PHYTYPE_N:
2148 if ((rev >= 11) && (rev <= 12))
2149 filename = "n0bsinitvals11";
2150 else
e4d6b795 2151 goto err_no_initvals;
61cb5dd6
MB		 2152 break;
2153 default:
2154 goto err_no_initvals;
e4d6b795 2155 }
1a9f5093 2156 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2157 if (err)
2158 goto err_load;
e4d6b795
MB		 2159
2160 return 0;
2161
e4d6b795 2162err_no_ucode:
1a9f5093
MB		 2163 err = ctx->fatal_failure = -EOPNOTSUPP;
2164 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2165 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2166 goto error;
2167
2168err_no_pcm:
1a9f5093
MB		 2169 err = ctx->fatal_failure = -EOPNOTSUPP;
2170 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2171 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2172 goto error;
2173
2174err_no_initvals:
1a9f5093
MB		 2175 err = ctx->fatal_failure = -EOPNOTSUPP;
2176 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2177 "is required for your device (wl-core rev %u)\n", rev);
2178 goto error;
2179
2180err_load:
2181 /* We failed to load this firmware image. The error message
2182 * already is in ctx->errors. Return and let our caller decide
2183 * what to do. */
e4d6b795
MB		 2184 goto error;
2185
2186error:
2187 b43_release_firmware(dev);
2188 return err;
2189}
2190
1a9f5093
MB		 2191static int b43_request_firmware(struct b43_wldev *dev)
2192{
2193 struct b43_request_fw_context *ctx;
2194 unsigned int i;
2195 int err;
2196 const char *errmsg;
2197
2198 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2199 if (!ctx)
2200 return -ENOMEM;
2201 ctx->dev = dev;
2202
2203 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2204 err = b43_try_request_fw(ctx);
2205 if (!err)
2206 goto out; /* Successfully loaded it. */
2207 err = ctx->fatal_failure;
2208 if (err)
2209 goto out;
2210
2211 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2212 err = b43_try_request_fw(ctx);
2213 if (!err)
2214 goto out; /* Successfully loaded it. */
2215 err = ctx->fatal_failure;
2216 if (err)
2217 goto out;
2218
2219 /* Could not find a usable firmware. Print the errors. */
2220 for (i = 0; i < B43_NR_FWTYPES; i++) {
2221 errmsg = ctx->errors[i];
2222 if (strlen(errmsg))
2223 b43err(dev->wl, errmsg);
2224 }
2225 b43_print_fw_helptext(dev->wl, 1);
2226 err = -ENOENT;
2227
2228out:
2229 kfree(ctx);
2230 return err;
2231}
2232
e4d6b795
MB		 2233static int b43_upload_microcode(struct b43_wldev *dev)
2234{
2235 const size_t hdr_len = sizeof(struct b43_fw_header);
2236 const __be32 *data;
2237 unsigned int i, len;
2238 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2239 u32 tmp, macctl;
e4d6b795
MB		 2240 int err = 0;
2241
1f7d87b0
MB		 2242 /* Jump the microcode PSM to offset 0 */
2243 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2244 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2245 macctl |= B43_MACCTL_PSM_JMP0;
2246 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2247 /* Zero out all microcode PSM registers and shared memory. */
2248 for (i = 0; i < 64; i++)
2249 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2250 for (i = 0; i < 4096; i += 2)
2251 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2252
e4d6b795 2253 /* Upload Microcode. */
61cb5dd6
MB		 2254 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2255 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2256 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2257 for (i = 0; i < len; i++) {
2258 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2259 udelay(10);
2260 }
2261
61cb5dd6 2262 if (dev->fw.pcm.data) {
e4d6b795 2263 /* Upload PCM data. */
61cb5dd6
MB		 2264 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2265 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2266 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2267 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2268 /* No need for autoinc bit in SHM_HW */
2269 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2270 for (i = 0; i < len; i++) {
2271 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2272 udelay(10);
2273 }
2274 }
2275
2276 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2277
2278 /* Start the microcode PSM */
2279 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2280 macctl &= ~B43_MACCTL_PSM_JMP0;
2281 macctl |= B43_MACCTL_PSM_RUN;
2282 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2283
2284 /* Wait for the microcode to load and respond */
2285 i = 0;
2286 while (1) {
2287 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2288 if (tmp == B43_IRQ_MAC_SUSPENDED)
2289 break;
2290 i++;
1f7d87b0 2291 if (i >= 20) {
e4d6b795 2292 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2293 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2294 err = -ENODEV;
1f7d87b0
MB		 2295 goto error;
2296 }
2297 msleep_interruptible(50);
2298 if (signal_pending(current)) {
2299 err = -EINTR;
2300 goto error;
e4d6b795 2301 }
e4d6b795
MB		 2302 }
2303 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2304
2305 /* Get and check the revisions. */
2306 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2307 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2308 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2309 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2310
2311 if (fwrev <= 0x128) {
2312 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2313 "binary drivers older than version 4.x is unsupported. "
2314 "You must upgrade your firmware files.\n");
eb189d8b 2315 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2316 err = -EOPNOTSUPP;
1f7d87b0 2317 goto error;
e4d6b795 2318 }
e4d6b795
MB		 2319 dev->fw.rev = fwrev;
2320 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2321 dev->fw.opensource = (fwdate == 0xFFFF);
2322
2323 if (dev->fw.opensource) {
2324 /* Patchlevel info is encoded in the "time" field. */
2325 dev->fw.patch = fwtime;
68217832
MB		 2326 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2327 dev->fw.rev, dev->fw.patch,
2328 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
e48b0eeb
MB		 2329 } else {
2330 b43info(dev->wl, "Loading firmware version %u.%u "
2331 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2332 fwrev, fwpatch,
2333 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2334 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2335 if (dev->fw.pcm_request_failed) {
2336 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2337 "Hardware accelerated cryptography is disabled.\n");
2338 b43_print_fw_helptext(dev->wl, 0);
2339 }
e48b0eeb 2340 }
e4d6b795 2341
eb189d8b 2342 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2343 /* We're over the deadline, but we keep support for old fw
2344 * until it turns out to be in major conflict with something new. */
eb189d8b 2345 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2346 "Support for old firmware will be removed soon "
2347 "(official deadline was July 2008).\n");
eb189d8b
MB		 2348 b43_print_fw_helptext(dev->wl, 0);
2349 }
2350
1f7d87b0
MB		 2351 return 0;
2352
2353error:
2354 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2355 macctl &= ~B43_MACCTL_PSM_RUN;
2356 macctl |= B43_MACCTL_PSM_JMP0;
2357 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2358
e4d6b795
MB		 2359 return err;
2360}
2361
2362static int b43_write_initvals(struct b43_wldev *dev,
2363 const struct b43_iv *ivals,
2364 size_t count,
2365 size_t array_size)
2366{
2367 const struct b43_iv *iv;
2368 u16 offset;
2369 size_t i;
2370 bool bit32;
2371
2372 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2373 iv = ivals;
2374 for (i = 0; i < count; i++) {
2375 if (array_size < sizeof(iv->offset_size))
2376 goto err_format;
2377 array_size -= sizeof(iv->offset_size);
2378 offset = be16_to_cpu(iv->offset_size);
2379 bit32 = !!(offset & B43_IV_32BIT);
2380 offset &= B43_IV_OFFSET_MASK;
2381 if (offset >= 0x1000)
2382 goto err_format;
2383 if (bit32) {
2384 u32 value;
2385
2386 if (array_size < sizeof(iv->data.d32))
2387 goto err_format;
2388 array_size -= sizeof(iv->data.d32);
2389
533dd1b0 2390 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2391 b43_write32(dev, offset, value);
2392
2393 iv = (const struct b43_iv *)((const uint8_t *)iv +
2394 sizeof(__be16) +
2395 sizeof(__be32));
2396 } else {
2397 u16 value;
2398
2399 if (array_size < sizeof(iv->data.d16))
2400 goto err_format;
2401 array_size -= sizeof(iv->data.d16);
2402
2403 value = be16_to_cpu(iv->data.d16);
2404 b43_write16(dev, offset, value);
2405
2406 iv = (const struct b43_iv *)((const uint8_t *)iv +
2407 sizeof(__be16) +
2408 sizeof(__be16));
2409 }
2410 }
2411 if (array_size)
2412 goto err_format;
2413
2414 return 0;
2415
2416err_format:
2417 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2418 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2419
2420 return -EPROTO;
2421}
2422
2423static int b43_upload_initvals(struct b43_wldev *dev)
2424{
2425 const size_t hdr_len = sizeof(struct b43_fw_header);
2426 const struct b43_fw_header *hdr;
2427 struct b43_firmware *fw = &dev->fw;
2428 const struct b43_iv *ivals;
2429 size_t count;
2430 int err;
2431
61cb5dd6
MB		 2432 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2433 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2434 count = be32_to_cpu(hdr->size);
2435 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2436 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2437 if (err)
2438 goto out;
61cb5dd6
MB		 2439 if (fw->initvals_band.data) {
2440 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2441 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2442 count = be32_to_cpu(hdr->size);
2443 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2444 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2445 if (err)
2446 goto out;
2447 }
2448out:
2449
2450 return err;
2451}
2452
2453/* Initialize the GPIOs
2454 * http://bcm-specs.sipsolutions.net/GPIO
2455 */
2456static int b43_gpio_init(struct b43_wldev *dev)
2457{
2458 struct ssb_bus *bus = dev->dev->bus;
2459 struct ssb_device *gpiodev, *pcidev = NULL;
2460 u32 mask, set;
2461
2462 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2463 & ~B43_MACCTL_GPOUTSMSK);
2464
e4d6b795
MB		 2465 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2466 | 0x000F);
2467
2468 mask = 0x0000001F;
2469 set = 0x0000000F;
2470 if (dev->dev->bus->chip_id == 0x4301) {
2471 mask |= 0x0060;
2472 set |= 0x0060;
2473 }
2474 if (0 /* FIXME: conditional unknown */ ) {
2475 b43_write16(dev, B43_MMIO_GPIO_MASK,
2476 b43_read16(dev, B43_MMIO_GPIO_MASK)
2477 | 0x0100);
2478 mask |= 0x0180;
2479 set |= 0x0180;
2480 }
95de2841 2481 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2482 b43_write16(dev, B43_MMIO_GPIO_MASK,
2483 b43_read16(dev, B43_MMIO_GPIO_MASK)
2484 | 0x0200);
2485 mask |= 0x0200;
2486 set |= 0x0200;
2487 }
2488 if (dev->dev->id.revision >= 2)
2489 mask |= 0x0010; /* FIXME: This is redundant. */
2490
2491#ifdef CONFIG_SSB_DRIVER_PCICORE
2492 pcidev = bus->pcicore.dev;
2493#endif
2494 gpiodev = bus->chipco.dev ? : pcidev;
2495 if (!gpiodev)
2496 return 0;
2497 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2498 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2499 & mask) | set);
2500
2501 return 0;
2502}
2503
2504/* Turn off all GPIO stuff. Call this on module unload, for example. */
2505static void b43_gpio_cleanup(struct b43_wldev *dev)
2506{
2507 struct ssb_bus *bus = dev->dev->bus;
2508 struct ssb_device *gpiodev, *pcidev = NULL;
2509
2510#ifdef CONFIG_SSB_DRIVER_PCICORE
2511 pcidev = bus->pcicore.dev;
2512#endif
2513 gpiodev = bus->chipco.dev ? : pcidev;
2514 if (!gpiodev)
2515 return;
2516 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2517}
2518
2519/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2520void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2521{
923fd703
MB		 2522 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2523 u16 fwstate;
2524
2525 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2526 B43_SHM_SH_UCODESTAT);
2527 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2528 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2529 b43err(dev->wl, "b43_mac_enable(): The firmware "
2530 "should be suspended, but current state is %u\n",
2531 fwstate);
2532 }
2533 }
2534
e4d6b795
MB		 2535 dev->mac_suspended--;
2536 B43_WARN_ON(dev->mac_suspended < 0);
2537 if (dev->mac_suspended == 0) {
2538 b43_write32(dev, B43_MMIO_MACCTL,
2539 b43_read32(dev, B43_MMIO_MACCTL)
2540 | B43_MACCTL_ENABLED);
2541 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2542 B43_IRQ_MAC_SUSPENDED);
2543 /* Commit writes */
2544 b43_read32(dev, B43_MMIO_MACCTL);
2545 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2546 b43_power_saving_ctl_bits(dev, 0);
2547 }
2548}
2549
2550/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2551void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2552{
2553 int i;
2554 u32 tmp;
2555
05b64b36 2556 might_sleep();
e4d6b795 2557 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2558
e4d6b795
MB		 2559 if (dev->mac_suspended == 0) {
2560 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2561 b43_write32(dev, B43_MMIO_MACCTL,
2562 b43_read32(dev, B43_MMIO_MACCTL)
2563 & ~B43_MACCTL_ENABLED);
2564 /* force pci to flush the write */
2565 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2566 for (i = 35; i; i--) {
2567 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2568 if (tmp & B43_IRQ_MAC_SUSPENDED)
2569 goto out;
2570 udelay(10);
2571 }
2572 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2573 for (i = 40; i; i--) {
e4d6b795
MB		 2574 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2575 if (tmp & B43_IRQ_MAC_SUSPENDED)
2576 goto out;
05b64b36 2577 msleep(1);
e4d6b795
MB		 2578 }
2579 b43err(dev->wl, "MAC suspend failed\n");
2580 }
05b64b36 2581out:
e4d6b795
MB		 2582 dev->mac_suspended++;
2583}
2584
2585static void b43_adjust_opmode(struct b43_wldev *dev)
2586{
2587 struct b43_wl *wl = dev->wl;
2588 u32 ctl;
2589 u16 cfp_pretbtt;
2590
2591 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2592 /* Reset status to STA infrastructure mode. */
2593 ctl &= ~B43_MACCTL_AP;
2594 ctl &= ~B43_MACCTL_KEEP_CTL;
2595 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2596 ctl &= ~B43_MACCTL_KEEP_BAD;
2597 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2598 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2599 ctl |= B43_MACCTL_INFRA;
2600
05c914fe
JB		 2601 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2602 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2603 ctl |= B43_MACCTL_AP;
05c914fe 2604 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2605 ctl &= ~B43_MACCTL_INFRA;
2606
2607 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2608 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2609 if (wl->filter_flags & FIF_FCSFAIL)
2610 ctl |= B43_MACCTL_KEEP_BAD;
2611 if (wl->filter_flags & FIF_PLCPFAIL)
2612 ctl |= B43_MACCTL_KEEP_BADPLCP;
2613 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2614 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2615 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2616 ctl |= B43_MACCTL_BEACPROMISC;
2617
e4d6b795
MB		 2618 /* Workaround: On old hardware the HW-MAC-address-filter
2619 * doesn't work properly, so always run promisc in filter
2620 * it in software. */
2621 if (dev->dev->id.revision <= 4)
2622 ctl |= B43_MACCTL_PROMISC;
2623
2624 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2625
2626 cfp_pretbtt = 2;
2627 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2628 if (dev->dev->bus->chip_id == 0x4306 &&
2629 dev->dev->bus->chip_rev == 3)
2630 cfp_pretbtt = 100;
2631 else
2632 cfp_pretbtt = 50;
2633 }
2634 b43_write16(dev, 0x612, cfp_pretbtt);
2635}
2636
2637static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2638{
2639 u16 offset;
2640
2641 if (is_ofdm) {
2642 offset = 0x480;
2643 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2644 } else {
2645 offset = 0x4C0;
2646 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2647 }
2648 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2649 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2650}
2651
2652static void b43_rate_memory_init(struct b43_wldev *dev)
2653{
2654 switch (dev->phy.type) {
2655 case B43_PHYTYPE_A:
2656 case B43_PHYTYPE_G:
53a6e234 2657 case B43_PHYTYPE_N:
e4d6b795
MB		 2658 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2659 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2660 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2661 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2662 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2663 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2664 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2665 if (dev->phy.type == B43_PHYTYPE_A)
2666 break;
2667 /* fallthrough */
2668 case B43_PHYTYPE_B:
2669 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2670 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2671 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2672 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2673 break;
2674 default:
2675 B43_WARN_ON(1);
2676 }
2677}
2678
5042c507
MB		 2679/* Set the default values for the PHY TX Control Words. */
2680static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2681{
2682 u16 ctl = 0;
2683
2684 ctl |= B43_TXH_PHY_ENC_CCK;
2685 ctl |= B43_TXH_PHY_ANT01AUTO;
2686 ctl |= B43_TXH_PHY_TXPWR;
2687
2688 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2689 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2690 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2691}
2692
e4d6b795
MB		 2693/* Set the TX-Antenna for management frames sent by firmware. */
2694static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2695{
5042c507 2696 u16 ant;
e4d6b795
MB		 2697 u16 tmp;
2698
5042c507 2699 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2700
e4d6b795
MB		 2701 /* For ACK/CTS */
2702 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2703 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2704 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2705 /* For Probe Resposes */
2706 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2707 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2708 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2709}
2710
2711/* This is the opposite of b43_chip_init() */
2712static void b43_chip_exit(struct b43_wldev *dev)
2713{
fb11137a 2714 b43_phy_exit(dev);
e4d6b795
MB		 2715 b43_gpio_cleanup(dev);
2716 /* firmware is released later */
2717}
2718
2719/* Initialize the chip
2720 * http://bcm-specs.sipsolutions.net/ChipInit
2721 */
2722static int b43_chip_init(struct b43_wldev *dev)
2723{
2724 struct b43_phy *phy = &dev->phy;
ef1a628d 2725 int err;
1f7d87b0 2726 u32 value32, macctl;
e4d6b795
MB		 2727 u16 value16;
2728
1f7d87b0
MB		 2729 /* Initialize the MAC control */
2730 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2731 if (dev->phy.gmode)
2732 macctl |= B43_MACCTL_GMODE;
2733 macctl |= B43_MACCTL_INFRA;
2734 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2735
2736 err = b43_request_firmware(dev);
2737 if (err)
2738 goto out;
2739 err = b43_upload_microcode(dev);
2740 if (err)
2741 goto out; /* firmware is released later */
2742
2743 err = b43_gpio_init(dev);
2744 if (err)
2745 goto out; /* firmware is released later */
21954c36 2746
e4d6b795
MB		 2747 err = b43_upload_initvals(dev);
2748 if (err)
1a8d1227 2749 goto err_gpio_clean;
e4d6b795 2750
0b7dcd96
MB		 2751 /* Turn the Analog on and initialize the PHY. */
2752 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2753 err = b43_phy_init(dev);
2754 if (err)
ef1a628d 2755 goto err_gpio_clean;
e4d6b795 2756
ef1a628d
MB		 2757 /* Disable Interference Mitigation. */
2758 if (phy->ops->interf_mitigation)
2759 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2760
ef1a628d
MB		 2761 /* Select the antennae */
2762 if (phy->ops->set_rx_antenna)
2763 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2764 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2765
2766 if (phy->type == B43_PHYTYPE_B) {
2767 value16 = b43_read16(dev, 0x005E);
2768 value16 |= 0x0004;
2769 b43_write16(dev, 0x005E, value16);
2770 }
2771 b43_write32(dev, 0x0100, 0x01000000);
2772 if (dev->dev->id.revision < 5)
2773 b43_write32(dev, 0x010C, 0x01000000);
2774
2775 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2776 & ~B43_MACCTL_INFRA);
2777 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2778 | B43_MACCTL_INFRA);
e4d6b795 2779
e4d6b795
MB		 2780 /* Probe Response Timeout value */
2781 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2782 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2783
2784 /* Initially set the wireless operation mode. */
2785 b43_adjust_opmode(dev);
2786
2787 if (dev->dev->id.revision < 3) {
2788 b43_write16(dev, 0x060E, 0x0000);
2789 b43_write16(dev, 0x0610, 0x8000);
2790 b43_write16(dev, 0x0604, 0x0000);
2791 b43_write16(dev, 0x0606, 0x0200);
2792 } else {
2793 b43_write32(dev, 0x0188, 0x80000000);
2794 b43_write32(dev, 0x018C, 0x02000000);
2795 }
2796 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2797 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2798 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2799 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2800 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2801 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2802 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2803
2804 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2805 value32 |= 0x00100000;
2806 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2807
2808 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2809 dev->dev->bus->chipco.fast_pwrup_delay);
2810
2811 err = 0;
2812 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2813out:
e4d6b795
MB		 2814 return err;
2815
1a8d1227 2816err_gpio_clean:
e4d6b795 2817 b43_gpio_cleanup(dev);
21954c36 2818 return err;
e4d6b795
MB		 2819}
2820
e4d6b795
MB		 2821static void b43_periodic_every60sec(struct b43_wldev *dev)
2822{
ef1a628d 2823 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2824
ef1a628d
MB		 2825 if (ops->pwork_60sec)
2826 ops->pwork_60sec(dev);
18c8adeb
MB		 2827
2828 /* Force check the TX power emission now. */
2829 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2830}
2831
2832static void b43_periodic_every30sec(struct b43_wldev *dev)
2833{
2834 /* Update device statistics. */
2835 b43_calculate_link_quality(dev);
2836}
2837
2838static void b43_periodic_every15sec(struct b43_wldev *dev)
2839{
2840 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2841 u16 wdr;
2842
2843 if (dev->fw.opensource) {
2844 /* Check if the firmware is still alive.
2845 * It will reset the watchdog counter to 0 in its idle loop. */
2846 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2847 if (unlikely(wdr)) {
2848 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2849 b43_controller_restart(dev, "Firmware watchdog");
2850 return;
2851 } else {
2852 b43_shm_write16(dev, B43_SHM_SCRATCH,
2853 B43_WATCHDOG_REG, 1);
2854 }
2855 }
e4d6b795 2856
ef1a628d
MB		 2857 if (phy->ops->pwork_15sec)
2858 phy->ops->pwork_15sec(dev);
2859
00e0b8cb
SB		 2860 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2861 wmb();
e4d6b795
MB		 2862}
2863
e4d6b795
MB		 2864static void do_periodic_work(struct b43_wldev *dev)
2865{
2866 unsigned int state;
2867
2868 state = dev->periodic_state;
42bb4cd5 2869 if (state % 4 == 0)
e4d6b795 2870 b43_periodic_every60sec(dev);
42bb4cd5 2871 if (state % 2 == 0)
e4d6b795 2872 b43_periodic_every30sec(dev);
42bb4cd5 2873 b43_periodic_every15sec(dev);
e4d6b795
MB		 2874}
2875
05b64b36
MB		 2876/* Periodic work locking policy:
2877 * The whole periodic work handler is protected by
2878 * wl->mutex. If another lock is needed somewhere in the
2879 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2880 */
e4d6b795
MB		 2881static void b43_periodic_work_handler(struct work_struct *work)
2882{
05b64b36
MB		 2883 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2884 periodic_work.work);
2885 struct b43_wl *wl = dev->wl;
2886 unsigned long delay;
e4d6b795 2887
05b64b36 2888 mutex_lock(&wl->mutex);
e4d6b795
MB		 2889
2890 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2891 goto out;
2892 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2893 goto out_requeue;
2894
05b64b36 2895 do_periodic_work(dev);
e4d6b795 2896
e4d6b795 2897 dev->periodic_state++;
42bb4cd5 2898out_requeue:
e4d6b795
MB		 2899 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2900 delay = msecs_to_jiffies(50);
2901 else
82cd682d 2902 delay = round_jiffies_relative(HZ * 15);
05b64b36 2903 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
42bb4cd5 2904out:
05b64b36 2905 mutex_unlock(&wl->mutex);
e4d6b795
MB		 2906}
2907
2908static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2909{
2910 struct delayed_work *work = &dev->periodic_work;
2911
2912 dev->periodic_state = 0;
2913 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2914 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2915}
2916
f3dd3fcc 2917/* Check if communication with the device works correctly. */
e4d6b795
MB		 2918static int b43_validate_chipaccess(struct b43_wldev *dev)
2919{
f3dd3fcc 2920 u32 v, backup;
e4d6b795 2921
f3dd3fcc
MB		 2922 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2923
2924 /* Check for read/write and endianness problems. */
e4d6b795
MB		 2925 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2926 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2927 goto error;
f3dd3fcc
MB		 2928 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2929 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 2930 goto error;
2931
f3dd3fcc
MB		 2932 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2933
2934 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2935 /* The 32bit register shadows the two 16bit registers
2936 * with update sideeffects. Validate this. */
2937 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2938 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2939 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2940 goto error;
2941 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2942 goto error;
2943 }
2944 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2945
2946 v = b43_read32(dev, B43_MMIO_MACCTL);
2947 v |= B43_MACCTL_GMODE;
2948 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 2949 goto error;
2950
2951 return 0;
f3dd3fcc 2952error:
e4d6b795
MB		 2953 b43err(dev->wl, "Failed to validate the chipaccess\n");
2954 return -ENODEV;
2955}
2956
2957static void b43_security_init(struct b43_wldev *dev)
2958{
2959 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2960 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2961 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2962 /* KTP is a word address, but we address SHM bytewise.
2963 * So multiply by two.
2964 */
2965 dev->ktp *= 2;
2966 if (dev->dev->id.revision >= 5) {
2967 /* Number of RCMTA address slots */
2968 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2969 }
2970 b43_clear_keys(dev);
2971}
2972
2973static int b43_rng_read(struct hwrng *rng, u32 * data)
2974{
2975 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2976 unsigned long flags;
2977
2978 /* Don't take wl->mutex here, as it could deadlock with
2979 * hwrng internal locking. It's not needed to take
2980 * wl->mutex here, anyway. */
2981
2982 spin_lock_irqsave(&wl->irq_lock, flags);
2983 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2984 spin_unlock_irqrestore(&wl->irq_lock, flags);
2985
2986 return (sizeof(u16));
2987}
2988
b844eba2 2989static void b43_rng_exit(struct b43_wl *wl)
e4d6b795
MB		 2990{
2991 if (wl->rng_initialized)
b844eba2 2992 hwrng_unregister(&wl->rng);
e4d6b795
MB		 2993}
2994
2995static int b43_rng_init(struct b43_wl *wl)
2996{
2997 int err;
2998
2999 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3000 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3001 wl->rng.name = wl->rng_name;
3002 wl->rng.data_read = b43_rng_read;
3003 wl->rng.priv = (unsigned long)wl;
3004 wl->rng_initialized = 1;
3005 err = hwrng_register(&wl->rng);
3006 if (err) {
3007 wl->rng_initialized = 0;
3008 b43err(wl, "Failed to register the random "
3009 "number generator (%d)\n", err);
3010 }
3011
3012 return err;
3013}
3014
40faacc4 3015static int b43_op_tx(struct ieee80211_hw *hw,
e039fa4a 3016 struct sk_buff *skb)
e4d6b795
MB		 3017{
3018 struct b43_wl *wl = hw_to_b43_wl(hw);
3019 struct b43_wldev *dev = wl->current_dev;
21a75d77
MB		 3020 unsigned long flags;
3021 int err;
e4d6b795 3022
5100d5ac
MB		 3023 if (unlikely(skb->len < 2 + 2 + 6)) {
3024 /* Too short, this can't be a valid frame. */
c9e8eae0 3025 goto drop_packet;
5100d5ac
MB		 3026 }
3027 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
e4d6b795 3028 if (unlikely(!dev))
c9e8eae0 3029 goto drop_packet;
21a75d77
MB		 3030
3031 /* Transmissions on seperate queues can run concurrently. */
3032 read_lock_irqsave(&wl->tx_lock, flags);
3033
3034 err = -ENODEV;
3035 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3036 if (b43_using_pio_transfers(dev))
e039fa4a 3037 err = b43_pio_tx(dev, skb);
21a75d77 3038 else
e039fa4a 3039 err = b43_dma_tx(dev, skb);
21a75d77
MB		 3040 }
3041
3042 read_unlock_irqrestore(&wl->tx_lock, flags);
3043
e4d6b795 3044 if (unlikely(err))
c9e8eae0
MB		 3045 goto drop_packet;
3046 return NETDEV_TX_OK;
3047
3048drop_packet:
3049 /* We can not transmit this packet. Drop it. */
3050 dev_kfree_skb_any(skb);
e4d6b795
MB		 3051 return NETDEV_TX_OK;
3052}
3053
e6f5b934
MB		 3054/* Locking: wl->irq_lock */
3055static void b43_qos_params_upload(struct b43_wldev *dev,
3056 const struct ieee80211_tx_queue_params *p,
3057 u16 shm_offset)
3058{
3059 u16 params[B43_NR_QOSPARAMS];
0b57664c 3060 int bslots, tmp;
e6f5b934
MB		 3061 unsigned int i;
3062
0b57664c 3063 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3064
3065 memset(&params, 0, sizeof(params));
3066
3067 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3068 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3069 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3070 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3071 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3072 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3073 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3074
3075 for (i = 0; i < ARRAY_SIZE(params); i++) {
3076 if (i == B43_QOSPARAM_STATUS) {
3077 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3078 shm_offset + (i * 2));
3079 /* Mark the parameters as updated. */
3080 tmp |= 0x100;
3081 b43_shm_write16(dev, B43_SHM_SHARED,
3082 shm_offset + (i * 2),
3083 tmp);
3084 } else {
3085 b43_shm_write16(dev, B43_SHM_SHARED,
3086 shm_offset + (i * 2),
3087 params[i]);
3088 }
3089 }
3090}
3091
c40c1129
MB		 3092/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3093static const u16 b43_qos_shm_offsets[] = {
3094 /* [mac80211-queue-nr] = SHM_OFFSET, */
3095 [0] = B43_QOS_VOICE,
3096 [1] = B43_QOS_VIDEO,
3097 [2] = B43_QOS_BESTEFFORT,
3098 [3] = B43_QOS_BACKGROUND,
3099};
3100
5a5f3b40
MB		 3101/* Update all QOS parameters in hardware. */
3102static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3103{
3104 struct b43_wl *wl = dev->wl;
3105 struct b43_qos_params *params;
e6f5b934
MB		 3106 unsigned int i;
3107
c40c1129
MB		 3108 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3109 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3110
3111 b43_mac_suspend(dev);
e6f5b934
MB		 3112 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3113 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3114 b43_qos_params_upload(dev, &(params->p),
3115 b43_qos_shm_offsets[i]);
e6f5b934 3116 }
e6f5b934
MB		 3117 b43_mac_enable(dev);
3118}
3119
3120static void b43_qos_clear(struct b43_wl *wl)
3121{
3122 struct b43_qos_params *params;
3123 unsigned int i;
3124
c40c1129
MB		 3125 /* Initialize QoS parameters to sane defaults. */
3126
3127 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3128 ARRAY_SIZE(wl->qos_params));
3129
e6f5b934
MB		 3130 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3131 params = &(wl->qos_params[i]);
3132
c40c1129
MB		 3133 switch (b43_qos_shm_offsets[i]) {
3134 case B43_QOS_VOICE:
3135 params->p.txop = 0;
3136 params->p.aifs = 2;
3137 params->p.cw_min = 0x0001;
3138 params->p.cw_max = 0x0001;
3139 break;
3140 case B43_QOS_VIDEO:
3141 params->p.txop = 0;
3142 params->p.aifs = 2;
3143 params->p.cw_min = 0x0001;
3144 params->p.cw_max = 0x0001;
3145 break;
3146 case B43_QOS_BESTEFFORT:
3147 params->p.txop = 0;
3148 params->p.aifs = 3;
3149 params->p.cw_min = 0x0001;
3150 params->p.cw_max = 0x03FF;
3151 break;
3152 case B43_QOS_BACKGROUND:
3153 params->p.txop = 0;
3154 params->p.aifs = 7;
3155 params->p.cw_min = 0x0001;
3156 params->p.cw_max = 0x03FF;
3157 break;
3158 default:
3159 B43_WARN_ON(1);
3160 }
e6f5b934
MB		 3161 }
3162}
3163
3164/* Initialize the core's QOS capabilities */
3165static void b43_qos_init(struct b43_wldev *dev)
3166{
e6f5b934 3167 /* Upload the current QOS parameters. */
5a5f3b40 3168 b43_qos_upload_all(dev);
e6f5b934
MB		 3169
3170 /* Enable QOS support. */
3171 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3172 b43_write16(dev, B43_MMIO_IFSCTL,
3173 b43_read16(dev, B43_MMIO_IFSCTL)
3174 | B43_MMIO_IFSCTL_USE_EDCF);
3175}
3176
e100bb64 3177static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3178 const struct ieee80211_tx_queue_params *params)
e4d6b795 3179{
e6f5b934 3180 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3181 struct b43_wldev *dev;
e6f5b934 3182 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3183 int err = -ENODEV;
e6f5b934
MB		 3184
3185 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3186 /* Queue not available or don't support setting
3187 * params on this queue. Return success to not
3188 * confuse mac80211. */
3189 return 0;
3190 }
5a5f3b40
MB		 3191 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3192 ARRAY_SIZE(wl->qos_params));
e6f5b934 3193
5a5f3b40
MB		 3194 mutex_lock(&wl->mutex);
3195 dev = wl->current_dev;
3196 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3197 goto out_unlock;
e6f5b934 3198
5a5f3b40
MB		 3199 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3200 b43_mac_suspend(dev);
3201 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3202 b43_qos_shm_offsets[queue]);
3203 b43_mac_enable(dev);
3204 err = 0;
e6f5b934 3205
5a5f3b40
MB		 3206out_unlock:
3207 mutex_unlock(&wl->mutex);
3208
3209 return err;
e4d6b795
MB		 3210}
3211
40faacc4
MB		 3212static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3213 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3214{
3215 struct b43_wl *wl = hw_to_b43_wl(hw);
3216 struct b43_wldev *dev = wl->current_dev;
3217 unsigned long flags;
3218 int err = -ENODEV;
3219
3220 if (!dev)
3221 goto out;
3222 spin_lock_irqsave(&wl->irq_lock, flags);
3223 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
5100d5ac
MB		 3224 if (b43_using_pio_transfers(dev))
3225 b43_pio_get_tx_stats(dev, stats);
3226 else
3227 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3228 err = 0;
3229 }
3230 spin_unlock_irqrestore(&wl->irq_lock, flags);
40faacc4 3231out:
e4d6b795
MB		 3232 return err;
3233}
3234
40faacc4
MB		 3235static int b43_op_get_stats(struct ieee80211_hw *hw,
3236 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3237{
3238 struct b43_wl *wl = hw_to_b43_wl(hw);
3239 unsigned long flags;
3240
3241 spin_lock_irqsave(&wl->irq_lock, flags);
3242 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3243 spin_unlock_irqrestore(&wl->irq_lock, flags);
3244
3245 return 0;
3246}
3247
08e87a83
AF		 3248static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3249{
3250 struct b43_wl *wl = hw_to_b43_wl(hw);
3251 struct b43_wldev *dev;
3252 u64 tsf;
3253
3254 mutex_lock(&wl->mutex);
3255 spin_lock_irq(&wl->irq_lock);
3256 dev = wl->current_dev;
3257
3258 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3259 b43_tsf_read(dev, &tsf);
3260 else
3261 tsf = 0;
3262
3263 spin_unlock_irq(&wl->irq_lock);
3264 mutex_unlock(&wl->mutex);
3265
3266 return tsf;
3267}
3268
3269static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3270{
3271 struct b43_wl *wl = hw_to_b43_wl(hw);
3272 struct b43_wldev *dev;
3273
3274 mutex_lock(&wl->mutex);
3275 spin_lock_irq(&wl->irq_lock);
3276 dev = wl->current_dev;
3277
3278 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3279 b43_tsf_write(dev, tsf);
3280
3281 spin_unlock_irq(&wl->irq_lock);
3282 mutex_unlock(&wl->mutex);
3283}
3284
e4d6b795
MB		 3285static void b43_put_phy_into_reset(struct b43_wldev *dev)
3286{
3287 struct ssb_device *sdev = dev->dev;
3288 u32 tmslow;
3289
3290 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3291 tmslow &= ~B43_TMSLOW_GMODE;
3292 tmslow |= B43_TMSLOW_PHYRESET;
3293 tmslow |= SSB_TMSLOW_FGC;
3294 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3295 msleep(1);
3296
3297 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3298 tmslow &= ~SSB_TMSLOW_FGC;
3299 tmslow |= B43_TMSLOW_PHYRESET;
3300 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3301 msleep(1);
3302}
3303
bb1eeff1
MB		 3304static const char * band_to_string(enum ieee80211_band band)
3305{
3306 switch (band) {
3307 case IEEE80211_BAND_5GHZ:
3308 return "5";
3309 case IEEE80211_BAND_2GHZ:
3310 return "2.4";
3311 default:
3312 break;
3313 }
3314 B43_WARN_ON(1);
3315 return "";
3316}
3317
e4d6b795 3318/* Expects wl->mutex locked */
bb1eeff1 3319static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3320{
bb1eeff1 3321 struct b43_wldev *up_dev = NULL;
e4d6b795 3322 struct b43_wldev *down_dev;
bb1eeff1 3323 struct b43_wldev *d;
e4d6b795 3324 int err;
922d8a0b 3325 bool uninitialized_var(gmode);
e4d6b795
MB		 3326 int prev_status;
3327
bb1eeff1
MB		 3328 /* Find a device and PHY which supports the band. */
3329 list_for_each_entry(d, &wl->devlist, list) {
3330 switch (chan->band) {
3331 case IEEE80211_BAND_5GHZ:
3332 if (d->phy.supports_5ghz) {
3333 up_dev = d;
3334 gmode = 0;
3335 }
3336 break;
3337 case IEEE80211_BAND_2GHZ:
3338 if (d->phy.supports_2ghz) {
3339 up_dev = d;
3340 gmode = 1;
3341 }
3342 break;
3343 default:
3344 B43_WARN_ON(1);
3345 return -EINVAL;
3346 }
3347 if (up_dev)
3348 break;
3349 }
3350 if (!up_dev) {
3351 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3352 band_to_string(chan->band));
3353 return -ENODEV;
e4d6b795
MB		 3354 }
3355 if ((up_dev == wl->current_dev) &&
3356 (!!wl->current_dev->phy.gmode == !!gmode)) {
3357 /* This device is already running. */
3358 return 0;
3359 }
bb1eeff1
MB		 3360 b43dbg(wl, "Switching to %s-GHz band\n",
3361 band_to_string(chan->band));
e4d6b795
MB		 3362 down_dev = wl->current_dev;
3363
3364 prev_status = b43_status(down_dev);
3365 /* Shutdown the currently running core. */
3366 if (prev_status >= B43_STAT_STARTED)
3367 b43_wireless_core_stop(down_dev);
3368 if (prev_status >= B43_STAT_INITIALIZED)
3369 b43_wireless_core_exit(down_dev);
3370
3371 if (down_dev != up_dev) {
3372 /* We switch to a different core, so we put PHY into
3373 * RESET on the old core. */
3374 b43_put_phy_into_reset(down_dev);
3375 }
3376
3377 /* Now start the new core. */
3378 up_dev->phy.gmode = gmode;
3379 if (prev_status >= B43_STAT_INITIALIZED) {
3380 err = b43_wireless_core_init(up_dev);
3381 if (err) {
3382 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3383 "selected %s-GHz band\n",
3384 band_to_string(chan->band));
e4d6b795
MB		 3385 goto init_failure;
3386 }
3387 }
3388 if (prev_status >= B43_STAT_STARTED) {
3389 err = b43_wireless_core_start(up_dev);
3390 if (err) {
3391 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3392 "selected %s-GHz band\n",
3393 band_to_string(chan->band));
e4d6b795
MB		 3394 b43_wireless_core_exit(up_dev);
3395 goto init_failure;
3396 }
3397 }
3398 B43_WARN_ON(b43_status(up_dev) != prev_status);
3399
3400 wl->current_dev = up_dev;
3401
3402 return 0;
bb1eeff1 3403init_failure:
e4d6b795
MB		 3404 /* Whoops, failed to init the new core. No core is operating now. */
3405 wl->current_dev = NULL;
3406 return err;
3407}
3408
9124b077
JB		 3409/* Write the short and long frame retry limit values. */
3410static void b43_set_retry_limits(struct b43_wldev *dev,
3411 unsigned int short_retry,
3412 unsigned int long_retry)
3413{
3414 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3415 * the chip-internal counter. */
3416 short_retry = min(short_retry, (unsigned int)0xF);
3417 long_retry = min(long_retry, (unsigned int)0xF);
3418
3419 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3420 short_retry);
3421 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3422 long_retry);
3423}
3424
e8975581 3425static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3426{
3427 struct b43_wl *wl = hw_to_b43_wl(hw);
3428 struct b43_wldev *dev;
3429 struct b43_phy *phy;
e8975581 3430 struct ieee80211_conf *conf = &hw->conf;
e4d6b795 3431 unsigned long flags;
9db1f6d7 3432 int antenna;
e4d6b795 3433 int err = 0;
e4d6b795 3434
e4d6b795
MB		 3435 mutex_lock(&wl->mutex);
3436
bb1eeff1
MB		 3437 /* Switch the band (if necessary). This might change the active core. */
3438 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3439 if (err)
3440 goto out_unlock_mutex;
3441 dev = wl->current_dev;
3442 phy = &dev->phy;
3443
d10d0e57
MB		 3444 b43_mac_suspend(dev);
3445
9124b077
JB		 3446 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3447 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3448 conf->long_frame_max_tx_count);
3449 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3450 if (!changed)
d10d0e57 3451 goto out_mac_enable;
e4d6b795
MB		 3452
3453 /* Switch to the requested channel.
3454 * The firmware takes care of races with the TX handler. */
8318d78a 3455 if (conf->channel->hw_value != phy->channel)
ef1a628d 3456 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3457
d42ce84a
JB		 3458 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3459
e4d6b795
MB		 3460 /* Adjust the desired TX power level. */
3461 if (conf->power_level != 0) {
18c8adeb
MB		 3462 spin_lock_irqsave(&wl->irq_lock, flags);
3463 if (conf->power_level != phy->desired_txpower) {
3464 phy->desired_txpower = conf->power_level;
3465 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3466 B43_TXPWR_IGNORE_TSSI);
e4d6b795 3467 }
18c8adeb 3468 spin_unlock_irqrestore(&wl->irq_lock, flags);
e4d6b795
MB		 3469 }
3470
3471 /* Antennas for RX and management frame TX. */
0f4ac38b 3472 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3473 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3474 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3475 if (phy->ops->set_rx_antenna)
3476 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3477
04dea136 3478 /* Update templates for AP/mesh mode. */
05c914fe
JB		 3479 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3480 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
e4d6b795
MB		 3481 b43_set_beacon_int(dev, conf->beacon_int);
3482
fda9abcf
MB		 3483 if (!!conf->radio_enabled != phy->radio_on) {
3484 if (conf->radio_enabled) {
ef1a628d 3485 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
fda9abcf
MB		 3486 b43info(dev->wl, "Radio turned on by software\n");
3487 if (!dev->radio_hw_enable) {
3488 b43info(dev->wl, "The hardware RF-kill button "
3489 "still turns the radio physically off. "
3490 "Press the button to turn it on.\n");
3491 }
3492 } else {
ef1a628d 3493 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
fda9abcf
MB		 3494 b43info(dev->wl, "Radio turned off by software\n");
3495 }
3496 }
3497
d10d0e57
MB		 3498out_mac_enable:
3499 b43_mac_enable(dev);
3500out_unlock_mutex:
e4d6b795
MB		 3501 mutex_unlock(&wl->mutex);
3502
3503 return err;
3504}
3505
881d948c 3506static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3507{
3508 struct ieee80211_supported_band *sband =
3509 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3510 struct ieee80211_rate *rate;
3511 int i;
3512 u16 basic, direct, offset, basic_offset, rateptr;
3513
3514 for (i = 0; i < sband->n_bitrates; i++) {
3515 rate = &sband->bitrates[i];
3516
3517 if (b43_is_cck_rate(rate->hw_value)) {
3518 direct = B43_SHM_SH_CCKDIRECT;
3519 basic = B43_SHM_SH_CCKBASIC;
3520 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3521 offset &= 0xF;
3522 } else {
3523 direct = B43_SHM_SH_OFDMDIRECT;
3524 basic = B43_SHM_SH_OFDMBASIC;
3525 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3526 offset &= 0xF;
3527 }
3528
3529 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3530
3531 if (b43_is_cck_rate(rate->hw_value)) {
3532 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3533 basic_offset &= 0xF;
3534 } else {
3535 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3536 basic_offset &= 0xF;
3537 }
3538
3539 /*
3540 * Get the pointer that we need to point to
3541 * from the direct map
3542 */
3543 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3544 direct + 2 * basic_offset);
3545 /* and write it to the basic map */
3546 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3547 rateptr);
3548 }
3549}
3550
3551static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3552 struct ieee80211_vif *vif,
3553 struct ieee80211_bss_conf *conf,
3554 u32 changed)
3555{
3556 struct b43_wl *wl = hw_to_b43_wl(hw);
3557 struct b43_wldev *dev;
c7ab5ef9
JB		 3558
3559 mutex_lock(&wl->mutex);
3560
3561 dev = wl->current_dev;
d10d0e57 3562 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3563 goto out_unlock_mutex;
c7ab5ef9
JB		 3564 b43_mac_suspend(dev);
3565
3566 if (changed & BSS_CHANGED_BASIC_RATES)
3567 b43_update_basic_rates(dev, conf->basic_rates);
3568
3569 if (changed & BSS_CHANGED_ERP_SLOT) {
3570 if (conf->use_short_slot)
3571 b43_short_slot_timing_enable(dev);
3572 else
3573 b43_short_slot_timing_disable(dev);
3574 }
3575
3576 b43_mac_enable(dev);
d10d0e57 3577out_unlock_mutex:
c7ab5ef9
JB		 3578 mutex_unlock(&wl->mutex);
3579
3580 return;
3581}
3582
40faacc4 3583static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3584 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3585 struct ieee80211_key_conf *key)
e4d6b795
MB		 3586{
3587 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3588 struct b43_wldev *dev;
e4d6b795
MB		 3589 u8 algorithm;
3590 u8 index;
c6dfc9a8 3591 int err;
a1d88210
LF		 3592#if B43_DEBUG
3593 static const u8 bcast_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
3594#endif
e4d6b795
MB		 3595
3596 if (modparam_nohwcrypt)
3597 return -ENOSPC; /* User disabled HW-crypto */
3598
c6dfc9a8 3599 mutex_lock(&wl->mutex);
e808e586
MB		 3600 spin_lock_irq(&wl->irq_lock);
3601 write_lock(&wl->tx_lock);
3602 /* Why do we need all this locking here?
3603 * mutex -> Every config operation must take it.
3604 * irq_lock -> We modify the dev->key array, which is accessed
3605 * in the IRQ handlers.
3606 * tx_lock -> We modify the dev->key array, which is accessed
3607 * in the TX handler.
3608 */
c6dfc9a8
MB		 3609
3610 dev = wl->current_dev;
3611 err = -ENODEV;
3612 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3613 goto out_unlock;
3614
68217832
MB		 3615 if (dev->fw.pcm_request_failed) {
3616 /* We don't have firmware for the crypto engine.
3617 * Must use software-crypto. */
3618 err = -EOPNOTSUPP;
3619 goto out_unlock;
3620 }
3621
c6dfc9a8 3622 err = -EINVAL;
e4d6b795 3623 switch (key->alg) {
e4d6b795 3624 case ALG_WEP:
e808e586 3625 if (key->keylen == LEN_WEP40)
e4d6b795
MB		 3626 algorithm = B43_SEC_ALGO_WEP40;
3627 else
3628 algorithm = B43_SEC_ALGO_WEP104;
3629 break;
3630 case ALG_TKIP:
3631 algorithm = B43_SEC_ALGO_TKIP;
3632 break;
3633 case ALG_CCMP:
3634 algorithm = B43_SEC_ALGO_AES;
3635 break;
3636 default:
3637 B43_WARN_ON(1);
c6dfc9a8 3638 goto out_unlock;
e4d6b795 3639 }
e4d6b795
MB		 3640 index = (u8) (key->keyidx);
3641 if (index > 3)
e4d6b795 3642 goto out_unlock;
e4d6b795
MB		 3643
3644 switch (cmd) {
3645 case SET_KEY:
3646 if (algorithm == B43_SEC_ALGO_TKIP) {
3647 /* FIXME: No TKIP hardware encryption for now. */
3648 err = -EOPNOTSUPP;
3649 goto out_unlock;
3650 }
3651
e808e586 3652 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3653 if (WARN_ON(!sta)) {
3654 err = -EOPNOTSUPP;
3655 goto out_unlock;
3656 }
e808e586 3657 /* Pairwise key with an assigned MAC address. */
e4d6b795 3658 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3659 key->key, key->keylen,
3660 sta->addr, key);
e808e586
MB		 3661 } else {
3662 /* Group key */
3663 err = b43_key_write(dev, index, algorithm,
3664 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3665 }
3666 if (err)
3667 goto out_unlock;
3668
3669 if (algorithm == B43_SEC_ALGO_WEP40 ||
3670 algorithm == B43_SEC_ALGO_WEP104) {
3671 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3672 } else {
3673 b43_hf_write(dev,
3674 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3675 }
3676 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3677 break;
3678 case DISABLE_KEY: {
3679 err = b43_key_clear(dev, key->hw_key_idx);
3680 if (err)
3681 goto out_unlock;
3682 break;
3683 }
3684 default:
3685 B43_WARN_ON(1);
3686 }
9cf7f247 3687
e4d6b795 3688out_unlock:
e4d6b795
MB		 3689 if (!err) {
3690 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3691 "mac: %pM\n",
e4d6b795 3692 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3693 sta ? sta->addr : bcast_addr);
9cf7f247 3694 b43_dump_keymemory(dev);
e4d6b795 3695 }
e808e586
MB		 3696 write_unlock(&wl->tx_lock);
3697 spin_unlock_irq(&wl->irq_lock);
9cf7f247
MB		 3698 mutex_unlock(&wl->mutex);
3699
e4d6b795
MB		 3700 return err;
3701}
3702
40faacc4
MB		 3703static void b43_op_configure_filter(struct ieee80211_hw *hw,
3704 unsigned int changed, unsigned int *fflags,
3705 int mc_count, struct dev_addr_list *mc_list)
e4d6b795
MB		 3706{
3707 struct b43_wl *wl = hw_to_b43_wl(hw);
3708 struct b43_wldev *dev = wl->current_dev;
3709 unsigned long flags;
3710
4150c572
JB		 3711 if (!dev) {
3712 *fflags = 0;
e4d6b795 3713 return;
e4d6b795 3714 }
4150c572
JB		 3715
3716 spin_lock_irqsave(&wl->irq_lock, flags);
3717 *fflags &= FIF_PROMISC_IN_BSS |
3718 FIF_ALLMULTI |
3719 FIF_FCSFAIL |
3720 FIF_PLCPFAIL |
3721 FIF_CONTROL |
3722 FIF_OTHER_BSS |
3723 FIF_BCN_PRBRESP_PROMISC;
3724
3725 changed &= FIF_PROMISC_IN_BSS |
3726 FIF_ALLMULTI |
3727 FIF_FCSFAIL |
3728 FIF_PLCPFAIL |
3729 FIF_CONTROL |
3730 FIF_OTHER_BSS |
3731 FIF_BCN_PRBRESP_PROMISC;
3732
3733 wl->filter_flags = *fflags;
3734
3735 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3736 b43_adjust_opmode(dev);
e4d6b795
MB		 3737 spin_unlock_irqrestore(&wl->irq_lock, flags);
3738}
3739
40faacc4 3740static int b43_op_config_interface(struct ieee80211_hw *hw,
32bfd35d 3741 struct ieee80211_vif *vif,
40faacc4 3742 struct ieee80211_if_conf *conf)
e4d6b795
MB		 3743{
3744 struct b43_wl *wl = hw_to_b43_wl(hw);
3745 struct b43_wldev *dev = wl->current_dev;
3746 unsigned long flags;
3747
3748 if (!dev)
3749 return -ENODEV;
3750 mutex_lock(&wl->mutex);
3751 spin_lock_irqsave(&wl->irq_lock, flags);
32bfd35d 3752 B43_WARN_ON(wl->vif != vif);
4150c572
JB		 3753 if (conf->bssid)
3754 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3755 else
3756 memset(wl->bssid, 0, ETH_ALEN);
3757 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
05c914fe
JB		 3758 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3759 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
9d139c81 3760 B43_WARN_ON(vif->type != wl->if_type);
9d139c81
JB		 3761 if (conf->changed & IEEE80211_IFCC_BEACON)
3762 b43_update_templates(wl);
05c914fe 3763 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
9d139c81
JB		 3764 if (conf->changed & IEEE80211_IFCC_BEACON)
3765 b43_update_templates(wl);
e4d6b795 3766 }
4150c572 3767 b43_write_mac_bssid_templates(dev);
e4d6b795
MB		 3768 }
3769 spin_unlock_irqrestore(&wl->irq_lock, flags);
3770 mutex_unlock(&wl->mutex);
3771
3772 return 0;
3773}
3774
3775/* Locking: wl->mutex */
3776static void b43_wireless_core_stop(struct b43_wldev *dev)
3777{
3778 struct b43_wl *wl = dev->wl;
3779 unsigned long flags;
3780
3781 if (b43_status(dev) < B43_STAT_STARTED)
3782 return;
a19d12d7
SB		 3783
3784 /* Disable and sync interrupts. We must do this before than
3785 * setting the status to INITIALIZED, as the interrupt handler
3786 * won't care about IRQs then. */
3787 spin_lock_irqsave(&wl->irq_lock, flags);
3788 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3789 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3790 spin_unlock_irqrestore(&wl->irq_lock, flags);
3791 b43_synchronize_irq(dev);
3792
21a75d77 3793 write_lock_irqsave(&wl->tx_lock, flags);
e4d6b795 3794 b43_set_status(dev, B43_STAT_INITIALIZED);
21a75d77 3795 write_unlock_irqrestore(&wl->tx_lock, flags);
e4d6b795 3796
5100d5ac 3797 b43_pio_stop(dev);
e4d6b795
MB		 3798 mutex_unlock(&wl->mutex);
3799 /* Must unlock as it would otherwise deadlock. No races here.
3800 * Cancel the possibly running self-rearming periodic work. */
3801 cancel_delayed_work_sync(&dev->periodic_work);
3802 mutex_lock(&wl->mutex);
3803
e4d6b795
MB		 3804 b43_mac_suspend(dev);
3805 free_irq(dev->dev->irq, dev);
3806 b43dbg(wl, "Wireless interface stopped\n");
3807}
3808
3809/* Locking: wl->mutex */
3810static int b43_wireless_core_start(struct b43_wldev *dev)
3811{
3812 int err;
3813
3814 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3815
3816 drain_txstatus_queue(dev);
3817 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3818 IRQF_SHARED, KBUILD_MODNAME, dev);
3819 if (err) {
3820 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3821 goto out;
3822 }
3823
3824 /* We are ready to run. */
3825 b43_set_status(dev, B43_STAT_STARTED);
3826
3827 /* Start data flow (TX/RX). */
3828 b43_mac_enable(dev);
3829 b43_interrupt_enable(dev, dev->irq_savedstate);
e4d6b795
MB		 3830
3831 /* Start maintainance work */
3832 b43_periodic_tasks_setup(dev);
3833
3834 b43dbg(dev->wl, "Wireless interface started\n");
3835 out:
3836 return err;
3837}
3838
3839/* Get PHY and RADIO versioning numbers */
3840static int b43_phy_versioning(struct b43_wldev *dev)
3841{
3842 struct b43_phy *phy = &dev->phy;
3843 u32 tmp;
3844 u8 analog_type;
3845 u8 phy_type;
3846 u8 phy_rev;
3847 u16 radio_manuf;
3848 u16 radio_ver;
3849 u16 radio_rev;
3850 int unsupported = 0;
3851
3852 /* Get PHY versioning */
3853 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3854 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3855 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3856 phy_rev = (tmp & B43_PHYVER_VERSION);
3857 switch (phy_type) {
3858 case B43_PHYTYPE_A:
3859 if (phy_rev >= 4)
3860 unsupported = 1;
3861 break;
3862 case B43_PHYTYPE_B:
3863 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3864 && phy_rev != 7)
3865 unsupported = 1;
3866 break;
3867 case B43_PHYTYPE_G:
013978b6 3868 if (phy_rev > 9)
e4d6b795
MB		 3869 unsupported = 1;
3870 break;
d5c71e46
MB		 3871#ifdef CONFIG_B43_NPHY
3872 case B43_PHYTYPE_N:
bb519bee 3873 if (phy_rev > 4)
d5c71e46
MB		 3874 unsupported = 1;
3875 break;
6b1c7c67
MB		 3876#endif
3877#ifdef CONFIG_B43_PHY_LP
3878 case B43_PHYTYPE_LP:
3879 if (phy_rev > 1)
3880 unsupported = 1;
3881 break;
d5c71e46 3882#endif
e4d6b795
MB		 3883 default:
3884 unsupported = 1;
3885 };
3886 if (unsupported) {
3887 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3888 "(Analog %u, Type %u, Revision %u)\n",
3889 analog_type, phy_type, phy_rev);
3890 return -EOPNOTSUPP;
3891 }
3892 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3893 analog_type, phy_type, phy_rev);
3894
3895 /* Get RADIO versioning */
3896 if (dev->dev->bus->chip_id == 0x4317) {
3897 if (dev->dev->bus->chip_rev == 0)
3898 tmp = 0x3205017F;
3899 else if (dev->dev->bus->chip_rev == 1)
3900 tmp = 0x4205017F;
3901 else
3902 tmp = 0x5205017F;
3903 } else {
3904 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3905 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 3906 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 3907 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 3908 }
3909 radio_manuf = (tmp & 0x00000FFF);
3910 radio_ver = (tmp & 0x0FFFF000) >> 12;
3911 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 3912 if (radio_manuf != 0x17F /* Broadcom */)
3913 unsupported = 1;
e4d6b795
MB		 3914 switch (phy_type) {
3915 case B43_PHYTYPE_A:
3916 if (radio_ver != 0x2060)
3917 unsupported = 1;
3918 if (radio_rev != 1)
3919 unsupported = 1;
3920 if (radio_manuf != 0x17F)
3921 unsupported = 1;
3922 break;
3923 case B43_PHYTYPE_B:
3924 if ((radio_ver & 0xFFF0) != 0x2050)
3925 unsupported = 1;
3926 break;
3927 case B43_PHYTYPE_G:
3928 if (radio_ver != 0x2050)
3929 unsupported = 1;
3930 break;
96c755a3 3931 case B43_PHYTYPE_N:
bb519bee 3932 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 3933 unsupported = 1;
3934 break;
6b1c7c67
MB		 3935 case B43_PHYTYPE_LP:
3936 if (radio_ver != 0x2062)
3937 unsupported = 1;
3938 break;
e4d6b795
MB		 3939 default:
3940 B43_WARN_ON(1);
3941 }
3942 if (unsupported) {
3943 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3944 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3945 radio_manuf, radio_ver, radio_rev);
3946 return -EOPNOTSUPP;
3947 }
3948 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3949 radio_manuf, radio_ver, radio_rev);
3950
3951 phy->radio_manuf = radio_manuf;
3952 phy->radio_ver = radio_ver;
3953 phy->radio_rev = radio_rev;
3954
3955 phy->analog = analog_type;
3956 phy->type = phy_type;
3957 phy->rev = phy_rev;
3958
3959 return 0;
3960}
3961
3962static void setup_struct_phy_for_init(struct b43_wldev *dev,
3963 struct b43_phy *phy)
3964{
e4d6b795 3965 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 3966 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 3967 /* PHY TX errors counter. */
3968 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
e4d6b795
MB		 3969}
3970
3971static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3972{
aa6c7ae2
MB		 3973 dev->dfq_valid = 0;
3974
6a724d68
MB		 3975 /* Assume the radio is enabled. If it's not enabled, the state will
3976 * immediately get fixed on the first periodic work run. */
3977 dev->radio_hw_enable = 1;
e4d6b795
MB		 3978
3979 /* Stats */
3980 memset(&dev->stats, 0, sizeof(dev->stats));
3981
3982 setup_struct_phy_for_init(dev, &dev->phy);
3983
3984 /* IRQ related flags */
3985 dev->irq_reason = 0;
3986 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3987 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3988
3989 dev->mac_suspended = 1;
3990
3991 /* Noise calculation context */
3992 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3993}
3994
3995static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3996{
3997 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 3998 u64 hf;
e4d6b795 3999
1855ba78
MB		 4000 if (!modparam_btcoex)
4001 return;
95de2841 4002 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4003 return;
4004 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4005 return;
4006
4007 hf = b43_hf_read(dev);
95de2841 4008 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4009 hf |= B43_HF_BTCOEXALT;
4010 else
4011 hf |= B43_HF_BTCOEX;
4012 b43_hf_write(dev, hf);
e4d6b795
MB		 4013}
4014
4015static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4016{
4017 if (!modparam_btcoex)
4018 return;
4019 //TODO
e4d6b795
MB		 4020}
4021
4022static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4023{
4024#ifdef CONFIG_SSB_DRIVER_PCICORE
4025 struct ssb_bus *bus = dev->dev->bus;
4026 u32 tmp;
4027
4028 if (bus->pcicore.dev &&
4029 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4030 bus->pcicore.dev->id.revision <= 5) {
4031 /* IMCFGLO timeouts workaround. */
4032 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4033 tmp &= ~SSB_IMCFGLO_REQTO;
4034 tmp &= ~SSB_IMCFGLO_SERTO;
4035 switch (bus->bustype) {
4036 case SSB_BUSTYPE_PCI:
4037 case SSB_BUSTYPE_PCMCIA:
4038 tmp |= 0x32;
4039 break;
4040 case SSB_BUSTYPE_SSB:
4041 tmp |= 0x53;
4042 break;
4043 }
4044 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4045 }
4046#endif /* CONFIG_SSB_DRIVER_PCICORE */
4047}
4048
d59f720d
MB		 4049static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4050{
4051 u16 pu_delay;
4052
4053 /* The time value is in microseconds. */
4054 if (dev->phy.type == B43_PHYTYPE_A)
4055 pu_delay = 3700;
4056 else
4057 pu_delay = 1050;
05c914fe 4058 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4059 pu_delay = 500;
4060 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4061 pu_delay = max(pu_delay, (u16)2400);
4062
4063 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4064}
4065
4066/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4067static void b43_set_pretbtt(struct b43_wldev *dev)
4068{
4069 u16 pretbtt;
4070
4071 /* The time value is in microseconds. */
05c914fe 4072 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4073 pretbtt = 2;
4074 } else {
4075 if (dev->phy.type == B43_PHYTYPE_A)
4076 pretbtt = 120;
4077 else
4078 pretbtt = 250;
4079 }
4080 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4081 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4082}
4083
e4d6b795
MB		 4084/* Shutdown a wireless core */
4085/* Locking: wl->mutex */
4086static void b43_wireless_core_exit(struct b43_wldev *dev)
4087{
1f7d87b0 4088 u32 macctl;
e4d6b795
MB		 4089
4090 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
4091 if (b43_status(dev) != B43_STAT_INITIALIZED)
4092 return;
4093 b43_set_status(dev, B43_STAT_UNINIT);
4094
1f7d87b0
MB		 4095 /* Stop the microcode PSM. */
4096 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4097 macctl &= ~B43_MACCTL_PSM_RUN;
4098 macctl |= B43_MACCTL_PSM_JMP0;
4099 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4100
3506e0c4
RW		 4101 if (!dev->suspend_in_progress) {
4102 b43_leds_exit(dev);
b844eba2 4103 b43_rng_exit(dev->wl);
3506e0c4 4104 }
e4d6b795 4105 b43_dma_free(dev);
5100d5ac 4106 b43_pio_free(dev);
e4d6b795 4107 b43_chip_exit(dev);
cb24f57f 4108 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4109 if (dev->wl->current_beacon) {
4110 dev_kfree_skb_any(dev->wl->current_beacon);
4111 dev->wl->current_beacon = NULL;
4112 }
4113
e4d6b795
MB		 4114 ssb_device_disable(dev->dev, 0);
4115 ssb_bus_may_powerdown(dev->dev->bus);
4116}
4117
4118/* Initialize a wireless core */
4119static int b43_wireless_core_init(struct b43_wldev *dev)
4120{
4121 struct b43_wl *wl = dev->wl;
4122 struct ssb_bus *bus = dev->dev->bus;
4123 struct ssb_sprom *sprom = &bus->sprom;
4124 struct b43_phy *phy = &dev->phy;
4125 int err;
a259d6a4
MB		 4126 u64 hf;
4127 u32 tmp;
e4d6b795
MB		 4128
4129 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4130
4131 err = ssb_bus_powerup(bus, 0);
4132 if (err)
4133 goto out;
4134 if (!ssb_device_is_enabled(dev->dev)) {
4135 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4136 b43_wireless_core_reset(dev, tmp);
4137 }
4138
fb11137a 4139 /* Reset all data structures. */
e4d6b795 4140 setup_struct_wldev_for_init(dev);
fb11137a 4141 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4142
4143 /* Enable IRQ routing to this device. */
4144 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4145
4146 b43_imcfglo_timeouts_workaround(dev);
4147 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4148 if (phy->ops->prepare_hardware) {
4149 err = phy->ops->prepare_hardware(dev);
ef1a628d 4150 if (err)
fb11137a 4151 goto err_busdown;
ef1a628d 4152 }
e4d6b795
MB		 4153 err = b43_chip_init(dev);
4154 if (err)
fb11137a 4155 goto err_busdown;
e4d6b795
MB		 4156 b43_shm_write16(dev, B43_SHM_SHARED,
4157 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4158 hf = b43_hf_read(dev);
4159 if (phy->type == B43_PHYTYPE_G) {
4160 hf |= B43_HF_SYMW;
4161 if (phy->rev == 1)
4162 hf |= B43_HF_GDCW;
95de2841 4163 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795
MB		 4164 hf |= B43_HF_OFDMPABOOST;
4165 } else if (phy->type == B43_PHYTYPE_B) {
4166 hf |= B43_HF_SYMW;
4167 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4168 hf &= ~B43_HF_GDCW;
4169 }
4170 b43_hf_write(dev, hf);
4171
74cfdba7
MB		 4172 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4173 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4174 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4175 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4176
4177 /* Disable sending probe responses from firmware.
4178 * Setting the MaxTime to one usec will always trigger
4179 * a timeout, so we never send any probe resp.
4180 * A timeout of zero is infinite. */
4181 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4182
4183 b43_rate_memory_init(dev);
5042c507 4184 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4185
4186 /* Minimum Contention Window */
4187 if (phy->type == B43_PHYTYPE_B) {
4188 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4189 } else {
4190 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4191 }
4192 /* Maximum Contention Window */
4193 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4194
5100d5ac
MB		 4195 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4196 dev->__using_pio_transfers = 1;
4197 err = b43_pio_init(dev);
4198 } else {
4199 dev->__using_pio_transfers = 0;
4200 err = b43_dma_init(dev);
4201 }
e4d6b795
MB		 4202 if (err)
4203 goto err_chip_exit;
03b29773 4204 b43_qos_init(dev);
d59f720d 4205 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4206 b43_bluetooth_coext_enable(dev);
4207
4208 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4150c572 4209 b43_upload_card_macaddress(dev);
e4d6b795 4210 b43_security_init(dev);
3506e0c4
RW		 4211 if (!dev->suspend_in_progress)
4212 b43_rng_init(wl);
e4d6b795
MB		 4213
4214 b43_set_status(dev, B43_STAT_INITIALIZED);
4215
3506e0c4
RW		 4216 if (!dev->suspend_in_progress)
4217 b43_leds_init(dev);
1a8d1227 4218out:
e4d6b795
MB		 4219 return err;
4220
ef1a628d 4221err_chip_exit:
e4d6b795 4222 b43_chip_exit(dev);
ef1a628d 4223err_busdown:
e4d6b795
MB		 4224 ssb_bus_may_powerdown(bus);
4225 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4226 return err;
4227}
4228
40faacc4
MB		 4229static int b43_op_add_interface(struct ieee80211_hw *hw,
4230 struct ieee80211_if_init_conf *conf)
e4d6b795
MB		 4231{
4232 struct b43_wl *wl = hw_to_b43_wl(hw);
4233 struct b43_wldev *dev;
4234 unsigned long flags;
4235 int err = -EOPNOTSUPP;
4150c572
JB		 4236
4237 /* TODO: allow WDS/AP devices to coexist */
4238
05c914fe
JB		 4239 if (conf->type != NL80211_IFTYPE_AP &&
4240 conf->type != NL80211_IFTYPE_MESH_POINT &&
4241 conf->type != NL80211_IFTYPE_STATION &&
4242 conf->type != NL80211_IFTYPE_WDS &&
4243 conf->type != NL80211_IFTYPE_ADHOC)
4150c572 4244 return -EOPNOTSUPP;
e4d6b795
MB		 4245
4246 mutex_lock(&wl->mutex);
4150c572 4247 if (wl->operating)
e4d6b795
MB		 4248 goto out_mutex_unlock;
4249
4250 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4251
4252 dev = wl->current_dev;
4150c572 4253 wl->operating = 1;
32bfd35d 4254 wl->vif = conf->vif;
4150c572
JB		 4255 wl->if_type = conf->type;
4256 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4257
4258 spin_lock_irqsave(&wl->irq_lock, flags);
4259 b43_adjust_opmode(dev);
d59f720d
MB		 4260 b43_set_pretbtt(dev);
4261 b43_set_synth_pu_delay(dev, 0);
4150c572
JB		 4262 b43_upload_card_macaddress(dev);
4263 spin_unlock_irqrestore(&wl->irq_lock, flags);
4264
4265 err = 0;
4266 out_mutex_unlock:
4267 mutex_unlock(&wl->mutex);
4268
4269 return err;
4270}
4271
40faacc4
MB		 4272static void b43_op_remove_interface(struct ieee80211_hw *hw,
4273 struct ieee80211_if_init_conf *conf)
4150c572
JB		 4274{
4275 struct b43_wl *wl = hw_to_b43_wl(hw);
4276 struct b43_wldev *dev = wl->current_dev;
4277 unsigned long flags;
4278
4279 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4280
4281 mutex_lock(&wl->mutex);
4282
4283 B43_WARN_ON(!wl->operating);
32bfd35d
JB		 4284 B43_WARN_ON(wl->vif != conf->vif);
4285 wl->vif = NULL;
4150c572
JB		 4286
4287 wl->operating = 0;
4288
4289 spin_lock_irqsave(&wl->irq_lock, flags);
4290 b43_adjust_opmode(dev);
4291 memset(wl->mac_addr, 0, ETH_ALEN);
4292 b43_upload_card_macaddress(dev);
4293 spin_unlock_irqrestore(&wl->irq_lock, flags);
4294
4295 mutex_unlock(&wl->mutex);
4296}
4297
40faacc4 4298static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4299{
4300 struct b43_wl *wl = hw_to_b43_wl(hw);
4301 struct b43_wldev *dev = wl->current_dev;
4302 int did_init = 0;
923403b8 4303 int err = 0;
1946a2c3 4304 bool do_rfkill_exit = 0;
4150c572 4305
7be1bb6b
MB		 4306 /* Kill all old instance specific information to make sure
4307 * the card won't use it in the short timeframe between start
4308 * and mac80211 reconfiguring it. */
4309 memset(wl->bssid, 0, ETH_ALEN);
4310 memset(wl->mac_addr, 0, ETH_ALEN);
4311 wl->filter_flags = 0;
4312 wl->radiotap_enabled = 0;
e6f5b934 4313 b43_qos_clear(wl);
6b4bec01
MB		 4314 wl->beacon0_uploaded = 0;
4315 wl->beacon1_uploaded = 0;
4316 wl->beacon_templates_virgin = 1;
7be1bb6b 4317
1a8d1227
LF		 4318 /* First register RFkill.
4319 * LEDs that are registered later depend on it. */
4320 b43_rfkill_init(dev);
4321
4150c572
JB		 4322 mutex_lock(&wl->mutex);
4323
e4d6b795
MB		 4324 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4325 err = b43_wireless_core_init(dev);
1946a2c3
MB		 4326 if (err) {
4327 do_rfkill_exit = 1;
e4d6b795 4328 goto out_mutex_unlock;
1946a2c3 4329 }
e4d6b795
MB		 4330 did_init = 1;
4331 }
4150c572 4332
e4d6b795
MB		 4333 if (b43_status(dev) < B43_STAT_STARTED) {
4334 err = b43_wireless_core_start(dev);
4335 if (err) {
4336 if (did_init)
4337 b43_wireless_core_exit(dev);
1946a2c3 4338 do_rfkill_exit = 1;
e4d6b795
MB		 4339 goto out_mutex_unlock;
4340 }
4341 }
4342
4150c572 4343 out_mutex_unlock:
e4d6b795
MB		 4344 mutex_unlock(&wl->mutex);
4345
1946a2c3
MB		 4346 if (do_rfkill_exit)
4347 b43_rfkill_exit(dev);
4348
e4d6b795
MB		 4349 return err;
4350}
4351
40faacc4 4352static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4353{
4354 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4355 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4356
1a8d1227 4357 b43_rfkill_exit(dev);
a82d9922 4358 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4359
e4d6b795 4360 mutex_lock(&wl->mutex);
4150c572
JB		 4361 if (b43_status(dev) >= B43_STAT_STARTED)
4362 b43_wireless_core_stop(dev);
4363 b43_wireless_core_exit(dev);
e4d6b795 4364 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4365
4366 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4367}
4368
17741cdc
JB		 4369static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4370 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4371{
4372 struct b43_wl *wl = hw_to_b43_wl(hw);
d4df6f1a 4373 unsigned long flags;
e66fee6a 4374
d4df6f1a 4375 spin_lock_irqsave(&wl->irq_lock, flags);
9d139c81 4376 b43_update_templates(wl);
d4df6f1a 4377 spin_unlock_irqrestore(&wl->irq_lock, flags);
e66fee6a
MB		 4378
4379 return 0;
4380}
4381
38968d09
JB		 4382static void b43_op_sta_notify(struct ieee80211_hw *hw,
4383 struct ieee80211_vif *vif,
4384 enum sta_notify_cmd notify_cmd,
17741cdc 4385 struct ieee80211_sta *sta)
38968d09
JB		 4386{
4387 struct b43_wl *wl = hw_to_b43_wl(hw);
4388
4389 B43_WARN_ON(!vif || wl->vif != vif);
4390}
4391
e4d6b795 4392static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4393 .tx = b43_op_tx,
4394 .conf_tx = b43_op_conf_tx,
4395 .add_interface = b43_op_add_interface,
4396 .remove_interface = b43_op_remove_interface,
4397 .config = b43_op_config,
c7ab5ef9 4398 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4399 .config_interface = b43_op_config_interface,
4400 .configure_filter = b43_op_configure_filter,
4401 .set_key = b43_op_set_key,
4402 .get_stats = b43_op_get_stats,
4403 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4404 .get_tsf = b43_op_get_tsf,
4405 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4406 .start = b43_op_start,
4407 .stop = b43_op_stop,
e66fee6a 4408 .set_tim = b43_op_beacon_set_tim,
38968d09 4409 .sta_notify = b43_op_sta_notify,
e4d6b795
MB		 4410};
4411
4412/* Hard-reset the chip. Do not call this directly.
4413 * Use b43_controller_restart()
4414 */
4415static void b43_chip_reset(struct work_struct *work)
4416{
4417 struct b43_wldev *dev =
4418 container_of(work, struct b43_wldev, restart_work);
4419 struct b43_wl *wl = dev->wl;
4420 int err = 0;
4421 int prev_status;
4422
4423 mutex_lock(&wl->mutex);
4424
4425 prev_status = b43_status(dev);
4426 /* Bring the device down... */
4427 if (prev_status >= B43_STAT_STARTED)
4428 b43_wireless_core_stop(dev);
4429 if (prev_status >= B43_STAT_INITIALIZED)
4430 b43_wireless_core_exit(dev);
4431
4432 /* ...and up again. */
4433 if (prev_status >= B43_STAT_INITIALIZED) {
4434 err = b43_wireless_core_init(dev);
4435 if (err)
4436 goto out;
4437 }
4438 if (prev_status >= B43_STAT_STARTED) {
4439 err = b43_wireless_core_start(dev);
4440 if (err) {
4441 b43_wireless_core_exit(dev);
4442 goto out;
4443 }
4444 }
3bf0a32e
MB		 4445out:
4446 if (err)
4447 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4448 mutex_unlock(&wl->mutex);
4449 if (err)
4450 b43err(wl, "Controller restart FAILED\n");
4451 else
4452 b43info(wl, "Controller restarted\n");
4453}
4454
bb1eeff1 4455static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4456 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4457{
4458 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4459
bb1eeff1
MB		 4460 if (have_2ghz_phy)
4461 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4462 if (dev->phy.type == B43_PHYTYPE_N) {
4463 if (have_5ghz_phy)
4464 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4465 } else {
4466 if (have_5ghz_phy)
4467 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4468 }
96c755a3 4469
bb1eeff1
MB		 4470 dev->phy.supports_2ghz = have_2ghz_phy;
4471 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4472
4473 return 0;
4474}
4475
4476static void b43_wireless_core_detach(struct b43_wldev *dev)
4477{
4478 /* We release firmware that late to not be required to re-request
4479 * is all the time when we reinit the core. */
4480 b43_release_firmware(dev);
fb11137a 4481 b43_phy_free(dev);
e4d6b795
MB		 4482}
4483
4484static int b43_wireless_core_attach(struct b43_wldev *dev)
4485{
4486 struct b43_wl *wl = dev->wl;
4487 struct ssb_bus *bus = dev->dev->bus;
4488 struct pci_dev *pdev = bus->host_pci;
4489 int err;
96c755a3 4490 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4491 u32 tmp;
4492
4493 /* Do NOT do any device initialization here.
4494 * Do it in wireless_core_init() instead.
4495 * This function is for gathering basic information about the HW, only.
4496 * Also some structs may be set up here. But most likely you want to have
4497 * that in core_init(), too.
4498 */
4499
4500 err = ssb_bus_powerup(bus, 0);
4501 if (err) {
4502 b43err(wl, "Bus powerup failed\n");
4503 goto out;
4504 }
4505 /* Get the PHY type. */
4506 if (dev->dev->id.revision >= 5) {
4507 u32 tmshigh;
4508
4509 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4510 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4511 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4512 } else
96c755a3 4513 B43_WARN_ON(1);
e4d6b795 4514
96c755a3 4515 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4516 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4517 b43_wireless_core_reset(dev, tmp);
4518
4519 err = b43_phy_versioning(dev);
4520 if (err)
21954c36 4521 goto err_powerdown;
e4d6b795
MB		 4522 /* Check if this device supports multiband. */
4523 if (!pdev ||
4524 (pdev->device != 0x4312 &&
4525 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4526 /* No multiband support. */
96c755a3
MB		 4527 have_2ghz_phy = 0;
4528 have_5ghz_phy = 0;
e4d6b795
MB		 4529 switch (dev->phy.type) {
4530 case B43_PHYTYPE_A:
96c755a3 4531 have_5ghz_phy = 1;
e4d6b795
MB		 4532 break;
4533 case B43_PHYTYPE_G:
96c755a3 4534 case B43_PHYTYPE_N:
6b1c7c67 4535 case B43_PHYTYPE_LP:
96c755a3 4536 have_2ghz_phy = 1;
e4d6b795
MB		 4537 break;
4538 default:
4539 B43_WARN_ON(1);
4540 }
4541 }
96c755a3
MB		 4542 if (dev->phy.type == B43_PHYTYPE_A) {
4543 /* FIXME */
4544 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4545 err = -EOPNOTSUPP;
4546 goto err_powerdown;
4547 }
2e35af14
MB		 4548 if (1 /* disable A-PHY */) {
4549 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4550 if (dev->phy.type != B43_PHYTYPE_N) {
4551 have_2ghz_phy = 1;
4552 have_5ghz_phy = 0;
4553 }
4554 }
4555
fb11137a
MB		 4556 err = b43_phy_allocate(dev);
4557 if (err)
4558 goto err_powerdown;
4559
96c755a3 4560 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4561 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4562 b43_wireless_core_reset(dev, tmp);
4563
4564 err = b43_validate_chipaccess(dev);
4565 if (err)
fb11137a 4566 goto err_phy_free;
bb1eeff1 4567 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4568 if (err)
fb11137a 4569 goto err_phy_free;
e4d6b795
MB		 4570
4571 /* Now set some default "current_dev" */
4572 if (!wl->current_dev)
4573 wl->current_dev = dev;
4574 INIT_WORK(&dev->restart_work, b43_chip_reset);
4575
cb24f57f 4576 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4577 ssb_device_disable(dev->dev, 0);
4578 ssb_bus_may_powerdown(bus);
4579
4580out:
4581 return err;
4582
fb11137a
MB		 4583err_phy_free:
4584 b43_phy_free(dev);
e4d6b795
MB		 4585err_powerdown:
4586 ssb_bus_may_powerdown(bus);
4587 return err;
4588}
4589
4590static void b43_one_core_detach(struct ssb_device *dev)
4591{
4592 struct b43_wldev *wldev;
4593 struct b43_wl *wl;
4594
3bf0a32e
MB		 4595 /* Do not cancel ieee80211-workqueue based work here.
4596 * See comment in b43_remove(). */
4597
e4d6b795
MB		 4598 wldev = ssb_get_drvdata(dev);
4599 wl = wldev->wl;
e4d6b795
MB		 4600 b43_debugfs_remove_device(wldev);
4601 b43_wireless_core_detach(wldev);
4602 list_del(&wldev->list);
4603 wl->nr_devs--;
4604 ssb_set_drvdata(dev, NULL);
4605 kfree(wldev);
4606}
4607
4608static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4609{
4610 struct b43_wldev *wldev;
4611 struct pci_dev *pdev;
4612 int err = -ENOMEM;
4613
4614 if (!list_empty(&wl->devlist)) {
4615 /* We are not the first core on this chip. */
4616 pdev = dev->bus->host_pci;
4617 /* Only special chips support more than one wireless
4618 * core, although some of the other chips have more than
4619 * one wireless core as well. Check for this and
4620 * bail out early.
4621 */
4622 if (!pdev ||
4623 ((pdev->device != 0x4321) &&
4624 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4625 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4626 return -ENODEV;
4627 }
4628 }
4629
4630 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4631 if (!wldev)
4632 goto out;
4633
4634 wldev->dev = dev;
4635 wldev->wl = wl;
4636 b43_set_status(wldev, B43_STAT_UNINIT);
4637 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4638 tasklet_init(&wldev->isr_tasklet,
4639 (void (*)(unsigned long))b43_interrupt_tasklet,
4640 (unsigned long)wldev);
e4d6b795
MB		 4641 INIT_LIST_HEAD(&wldev->list);
4642
4643 err = b43_wireless_core_attach(wldev);
4644 if (err)
4645 goto err_kfree_wldev;
4646
4647 list_add(&wldev->list, &wl->devlist);
4648 wl->nr_devs++;
4649 ssb_set_drvdata(dev, wldev);
4650 b43_debugfs_add_device(wldev);
4651
4652 out:
4653 return err;
4654
4655 err_kfree_wldev:
4656 kfree(wldev);
4657 return err;
4658}
4659
9fc38458
MB		 4660#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4661 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4662 (pdev->device == _device) && \
4663 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4664 (pdev->subsystem_device == _subdevice) )
4665
e4d6b795
MB		 4666static void b43_sprom_fixup(struct ssb_bus *bus)
4667{
1855ba78
MB		 4668 struct pci_dev *pdev;
4669
e4d6b795
MB		 4670 /* boardflags workarounds */
4671 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4672 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4673 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4674 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4675 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4676 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4677 if (bus->bustype == SSB_BUSTYPE_PCI) {
4678 pdev = bus->host_pci;
9fc38458 4679 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4680 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4681 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4682 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4683 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4684 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4685 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4686 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4687 }
e4d6b795
MB		 4688}
4689
4690static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4691{
4692 struct ieee80211_hw *hw = wl->hw;
4693
4694 ssb_set_devtypedata(dev, NULL);
4695 ieee80211_free_hw(hw);
4696}
4697
4698static int b43_wireless_init(struct ssb_device *dev)
4699{
4700 struct ssb_sprom *sprom = &dev->bus->sprom;
4701 struct ieee80211_hw *hw;
4702 struct b43_wl *wl;
4703 int err = -ENOMEM;
4704
4705 b43_sprom_fixup(dev->bus);
4706
4707 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4708 if (!hw) {
4709 b43err(NULL, "Could not allocate ieee80211 device\n");
4710 goto out;
4711 }
4712
4713 /* fill hw info */
605a0bd6 4714 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4715 IEEE80211_HW_SIGNAL_DBM |
4716 IEEE80211_HW_NOISE_DBM;
4717
f59ac048
LR		 4718 hw->wiphy->interface_modes =
4719 BIT(NL80211_IFTYPE_AP) |
4720 BIT(NL80211_IFTYPE_MESH_POINT) |
4721 BIT(NL80211_IFTYPE_STATION) |
4722 BIT(NL80211_IFTYPE_WDS) |
4723 BIT(NL80211_IFTYPE_ADHOC);
4724
e6f5b934 4725 hw->queues = b43_modparam_qos ? 4 : 1;
e6a9854b 4726 hw->max_rates = 2;
e4d6b795 4727 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4728 if (is_valid_ether_addr(sprom->et1mac))
4729 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4730 else
95de2841 4731 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795
MB		 4732
4733 /* Get and initialize struct b43_wl */
4734 wl = hw_to_b43_wl(hw);
4735 memset(wl, 0, sizeof(*wl));
4736 wl->hw = hw;
4737 spin_lock_init(&wl->irq_lock);
21a75d77 4738 rwlock_init(&wl->tx_lock);
e4d6b795 4739 spin_lock_init(&wl->leds_lock);
280d0e16 4740 spin_lock_init(&wl->shm_lock);
e4d6b795
MB		 4741 mutex_init(&wl->mutex);
4742 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4743 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4744 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
e4d6b795
MB		 4745
4746 ssb_set_devtypedata(dev, wl);
4747 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4748 err = 0;
4749 out:
4750 return err;
4751}
4752
4753static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4754{
4755 struct b43_wl *wl;
4756 int err;
4757 int first = 0;
4758
4759 wl = ssb_get_devtypedata(dev);
4760 if (!wl) {
4761 /* Probing the first core. Must setup common struct b43_wl */
4762 first = 1;
4763 err = b43_wireless_init(dev);
4764 if (err)
4765 goto out;
4766 wl = ssb_get_devtypedata(dev);
4767 B43_WARN_ON(!wl);
4768 }
4769 err = b43_one_core_attach(dev, wl);
4770 if (err)
4771 goto err_wireless_exit;
4772
4773 if (first) {
4774 err = ieee80211_register_hw(wl->hw);
4775 if (err)
4776 goto err_one_core_detach;
4777 }
4778
4779 out:
4780 return err;
4781
4782 err_one_core_detach:
4783 b43_one_core_detach(dev);
4784 err_wireless_exit:
4785 if (first)
4786 b43_wireless_exit(dev, wl);
4787 return err;
4788}
4789
4790static void b43_remove(struct ssb_device *dev)
4791{
4792 struct b43_wl *wl = ssb_get_devtypedata(dev);
4793 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4794
3bf0a32e
MB		 4795 /* We must cancel any work here before unregistering from ieee80211,
4796 * as the ieee80211 unreg will destroy the workqueue. */
4797 cancel_work_sync(&wldev->restart_work);
4798
e4d6b795
MB		 4799 B43_WARN_ON(!wl);
4800 if (wl->current_dev == wldev)
4801 ieee80211_unregister_hw(wl->hw);
4802
4803 b43_one_core_detach(dev);
4804
4805 if (list_empty(&wl->devlist)) {
4806 /* Last core on the chip unregistered.
4807 * We can destroy common struct b43_wl.
4808 */
4809 b43_wireless_exit(dev, wl);
4810 }
4811}
4812
4813/* Perform a hardware reset. This can be called from any context. */
4814void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4815{
4816 /* Must avoid requeueing, if we are in shutdown. */
4817 if (b43_status(dev) < B43_STAT_INITIALIZED)
4818 return;
4819 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4820 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4821}
4822
4823#ifdef CONFIG_PM
4824
4825static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4826{
4827 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4828 struct b43_wl *wl = wldev->wl;
4829
4830 b43dbg(wl, "Suspending...\n");
4831
4832 mutex_lock(&wl->mutex);
3506e0c4 4833 wldev->suspend_in_progress = true;
e4d6b795
MB		 4834 wldev->suspend_init_status = b43_status(wldev);
4835 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4836 b43_wireless_core_stop(wldev);
4837 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4838 b43_wireless_core_exit(wldev);
4839 mutex_unlock(&wl->mutex);
4840
4841 b43dbg(wl, "Device suspended.\n");
4842
4843 return 0;
4844}
4845
4846static int b43_resume(struct ssb_device *dev)
4847{
4848 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4849 struct b43_wl *wl = wldev->wl;
4850 int err = 0;
4851
4852 b43dbg(wl, "Resuming...\n");
4853
4854 mutex_lock(&wl->mutex);
4855 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4856 err = b43_wireless_core_init(wldev);
4857 if (err) {
4858 b43err(wl, "Resume failed at core init\n");
4859 goto out;
4860 }
4861 }
4862 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4863 err = b43_wireless_core_start(wldev);
4864 if (err) {
3506e0c4 4865 b43_leds_exit(wldev);
b844eba2 4866 b43_rng_exit(wldev->wl);
e4d6b795
MB		 4867 b43_wireless_core_exit(wldev);
4868 b43err(wl, "Resume failed at core start\n");
4869 goto out;
4870 }
4871 }
e4d6b795 4872 b43dbg(wl, "Device resumed.\n");
3506e0c4
RW		 4873 out:
4874 wldev->suspend_in_progress = false;
4875 mutex_unlock(&wl->mutex);
e4d6b795
MB		 4876 return err;
4877}
4878
4879#else /* CONFIG_PM */
4880# define b43_suspend NULL
4881# define b43_resume NULL
4882#endif /* CONFIG_PM */
4883
4884static struct ssb_driver b43_ssb_driver = {
4885 .name = KBUILD_MODNAME,
4886 .id_table = b43_ssb_tbl,
4887 .probe = b43_probe,
4888 .remove = b43_remove,
4889 .suspend = b43_suspend,
4890 .resume = b43_resume,
4891};
4892
26bc783f
MB		 4893static void b43_print_driverinfo(void)
4894{
4895 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4896 *feat_leds = "", *feat_rfkill = "";
4897
4898#ifdef CONFIG_B43_PCI_AUTOSELECT
4899 feat_pci = "P";
4900#endif
4901#ifdef CONFIG_B43_PCMCIA
4902 feat_pcmcia = "M";
4903#endif
4904#ifdef CONFIG_B43_NPHY
4905 feat_nphy = "N";
4906#endif
4907#ifdef CONFIG_B43_LEDS
4908 feat_leds = "L";
4909#endif
4910#ifdef CONFIG_B43_RFKILL
4911 feat_rfkill = "R";
4912#endif
4913 printk(KERN_INFO "Broadcom 43xx driver loaded "
4914 "[ Features: %s%s%s%s%s, Firmware-ID: "
4915 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4916 feat_pci, feat_pcmcia, feat_nphy,
4917 feat_leds, feat_rfkill);
4918}
4919
e4d6b795
MB		 4920static int __init b43_init(void)
4921{
4922 int err;
4923
4924 b43_debugfs_init();
4925 err = b43_pcmcia_init();
4926 if (err)
4927 goto err_dfs_exit;
4928 err = ssb_driver_register(&b43_ssb_driver);
4929 if (err)
4930 goto err_pcmcia_exit;
26bc783f 4931 b43_print_driverinfo();
e4d6b795
MB		 4932
4933 return err;
4934
4935err_pcmcia_exit:
4936 b43_pcmcia_exit();
4937err_dfs_exit:
4938 b43_debugfs_exit();
4939 return err;
4940}
4941
4942static void __exit b43_exit(void)
4943{
4944 ssb_driver_unregister(&b43_ssb_driver);
4945 b43_pcmcia_exit();
4946 b43_debugfs_exit();
4947}
4948
4949module_init(b43_init)
4950module_exit(b43_exit)
Linux 6.x block layer and io_uring tree(s)