Commit | Line | Data |
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e4d6b795 MB |
1 | /* |
2 | ||
3 | Broadcom B43 wireless driver | |
4 | ||
5 | DMA ringbuffer and descriptor allocation/management | |
6 | ||
7 | Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> | |
8 | ||
9 | Some code in this file is derived from the b44.c driver | |
10 | Copyright (C) 2002 David S. Miller | |
11 | Copyright (C) Pekka Pietikainen | |
12 | ||
13 | This program is free software; you can redistribute it and/or modify | |
14 | it under the terms of the GNU General Public License as published by | |
15 | the Free Software Foundation; either version 2 of the License, or | |
16 | (at your option) any later version. | |
17 | ||
18 | This program is distributed in the hope that it will be useful, | |
19 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | GNU General Public License for more details. | |
22 | ||
23 | You should have received a copy of the GNU General Public License | |
24 | along with this program; see the file COPYING. If not, write to | |
25 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, | |
26 | Boston, MA 02110-1301, USA. | |
27 | ||
28 | */ | |
29 | ||
30 | #include "b43.h" | |
31 | #include "dma.h" | |
32 | #include "main.h" | |
33 | #include "debugfs.h" | |
34 | #include "xmit.h" | |
35 | ||
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/skbuff.h> | |
280d0e16 | 40 | #include <linux/etherdevice.h> |
57df40d2 | 41 | #include <asm/div64.h> |
280d0e16 | 42 | |
e4d6b795 MB |
43 | |
44 | /* 32bit DMA ops. */ | |
45 | static | |
46 | struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring, | |
47 | int slot, | |
48 | struct b43_dmadesc_meta **meta) | |
49 | { | |
50 | struct b43_dmadesc32 *desc; | |
51 | ||
52 | *meta = &(ring->meta[slot]); | |
53 | desc = ring->descbase; | |
54 | desc = &(desc[slot]); | |
55 | ||
56 | return (struct b43_dmadesc_generic *)desc; | |
57 | } | |
58 | ||
59 | static void op32_fill_descriptor(struct b43_dmaring *ring, | |
60 | struct b43_dmadesc_generic *desc, | |
61 | dma_addr_t dmaaddr, u16 bufsize, | |
62 | int start, int end, int irq) | |
63 | { | |
64 | struct b43_dmadesc32 *descbase = ring->descbase; | |
65 | int slot; | |
66 | u32 ctl; | |
67 | u32 addr; | |
68 | u32 addrext; | |
69 | ||
70 | slot = (int)(&(desc->dma32) - descbase); | |
71 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
72 | ||
73 | addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK); | |
74 | addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK) | |
75 | >> SSB_DMA_TRANSLATION_SHIFT; | |
76 | addr |= ssb_dma_translation(ring->dev->dev); | |
77 | ctl = (bufsize - ring->frameoffset) | |
78 | & B43_DMA32_DCTL_BYTECNT; | |
79 | if (slot == ring->nr_slots - 1) | |
80 | ctl |= B43_DMA32_DCTL_DTABLEEND; | |
81 | if (start) | |
82 | ctl |= B43_DMA32_DCTL_FRAMESTART; | |
83 | if (end) | |
84 | ctl |= B43_DMA32_DCTL_FRAMEEND; | |
85 | if (irq) | |
86 | ctl |= B43_DMA32_DCTL_IRQ; | |
87 | ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT) | |
88 | & B43_DMA32_DCTL_ADDREXT_MASK; | |
89 | ||
90 | desc->dma32.control = cpu_to_le32(ctl); | |
91 | desc->dma32.address = cpu_to_le32(addr); | |
92 | } | |
93 | ||
94 | static void op32_poke_tx(struct b43_dmaring *ring, int slot) | |
95 | { | |
96 | b43_dma_write(ring, B43_DMA32_TXINDEX, | |
97 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
98 | } | |
99 | ||
100 | static void op32_tx_suspend(struct b43_dmaring *ring) | |
101 | { | |
102 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
103 | | B43_DMA32_TXSUSPEND); | |
104 | } | |
105 | ||
106 | static void op32_tx_resume(struct b43_dmaring *ring) | |
107 | { | |
108 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) | |
109 | & ~B43_DMA32_TXSUSPEND); | |
110 | } | |
111 | ||
112 | static int op32_get_current_rxslot(struct b43_dmaring *ring) | |
113 | { | |
114 | u32 val; | |
115 | ||
116 | val = b43_dma_read(ring, B43_DMA32_RXSTATUS); | |
117 | val &= B43_DMA32_RXDPTR; | |
118 | ||
119 | return (val / sizeof(struct b43_dmadesc32)); | |
120 | } | |
121 | ||
122 | static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
123 | { | |
124 | b43_dma_write(ring, B43_DMA32_RXINDEX, | |
125 | (u32) (slot * sizeof(struct b43_dmadesc32))); | |
126 | } | |
127 | ||
128 | static const struct b43_dma_ops dma32_ops = { | |
129 | .idx2desc = op32_idx2desc, | |
130 | .fill_descriptor = op32_fill_descriptor, | |
131 | .poke_tx = op32_poke_tx, | |
132 | .tx_suspend = op32_tx_suspend, | |
133 | .tx_resume = op32_tx_resume, | |
134 | .get_current_rxslot = op32_get_current_rxslot, | |
135 | .set_current_rxslot = op32_set_current_rxslot, | |
136 | }; | |
137 | ||
138 | /* 64bit DMA ops. */ | |
139 | static | |
140 | struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring, | |
141 | int slot, | |
142 | struct b43_dmadesc_meta **meta) | |
143 | { | |
144 | struct b43_dmadesc64 *desc; | |
145 | ||
146 | *meta = &(ring->meta[slot]); | |
147 | desc = ring->descbase; | |
148 | desc = &(desc[slot]); | |
149 | ||
150 | return (struct b43_dmadesc_generic *)desc; | |
151 | } | |
152 | ||
153 | static void op64_fill_descriptor(struct b43_dmaring *ring, | |
154 | struct b43_dmadesc_generic *desc, | |
155 | dma_addr_t dmaaddr, u16 bufsize, | |
156 | int start, int end, int irq) | |
157 | { | |
158 | struct b43_dmadesc64 *descbase = ring->descbase; | |
159 | int slot; | |
160 | u32 ctl0 = 0, ctl1 = 0; | |
161 | u32 addrlo, addrhi; | |
162 | u32 addrext; | |
163 | ||
164 | slot = (int)(&(desc->dma64) - descbase); | |
165 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
166 | ||
167 | addrlo = (u32) (dmaaddr & 0xFFFFFFFF); | |
168 | addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); | |
169 | addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) | |
170 | >> SSB_DMA_TRANSLATION_SHIFT; | |
013978b6 | 171 | addrhi |= (ssb_dma_translation(ring->dev->dev) << 1); |
e4d6b795 MB |
172 | if (slot == ring->nr_slots - 1) |
173 | ctl0 |= B43_DMA64_DCTL0_DTABLEEND; | |
174 | if (start) | |
175 | ctl0 |= B43_DMA64_DCTL0_FRAMESTART; | |
176 | if (end) | |
177 | ctl0 |= B43_DMA64_DCTL0_FRAMEEND; | |
178 | if (irq) | |
179 | ctl0 |= B43_DMA64_DCTL0_IRQ; | |
180 | ctl1 |= (bufsize - ring->frameoffset) | |
181 | & B43_DMA64_DCTL1_BYTECNT; | |
182 | ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) | |
183 | & B43_DMA64_DCTL1_ADDREXT_MASK; | |
184 | ||
185 | desc->dma64.control0 = cpu_to_le32(ctl0); | |
186 | desc->dma64.control1 = cpu_to_le32(ctl1); | |
187 | desc->dma64.address_low = cpu_to_le32(addrlo); | |
188 | desc->dma64.address_high = cpu_to_le32(addrhi); | |
189 | } | |
190 | ||
191 | static void op64_poke_tx(struct b43_dmaring *ring, int slot) | |
192 | { | |
193 | b43_dma_write(ring, B43_DMA64_TXINDEX, | |
194 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
195 | } | |
196 | ||
197 | static void op64_tx_suspend(struct b43_dmaring *ring) | |
198 | { | |
199 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
200 | | B43_DMA64_TXSUSPEND); | |
201 | } | |
202 | ||
203 | static void op64_tx_resume(struct b43_dmaring *ring) | |
204 | { | |
205 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) | |
206 | & ~B43_DMA64_TXSUSPEND); | |
207 | } | |
208 | ||
209 | static int op64_get_current_rxslot(struct b43_dmaring *ring) | |
210 | { | |
211 | u32 val; | |
212 | ||
213 | val = b43_dma_read(ring, B43_DMA64_RXSTATUS); | |
214 | val &= B43_DMA64_RXSTATDPTR; | |
215 | ||
216 | return (val / sizeof(struct b43_dmadesc64)); | |
217 | } | |
218 | ||
219 | static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot) | |
220 | { | |
221 | b43_dma_write(ring, B43_DMA64_RXINDEX, | |
222 | (u32) (slot * sizeof(struct b43_dmadesc64))); | |
223 | } | |
224 | ||
225 | static const struct b43_dma_ops dma64_ops = { | |
226 | .idx2desc = op64_idx2desc, | |
227 | .fill_descriptor = op64_fill_descriptor, | |
228 | .poke_tx = op64_poke_tx, | |
229 | .tx_suspend = op64_tx_suspend, | |
230 | .tx_resume = op64_tx_resume, | |
231 | .get_current_rxslot = op64_get_current_rxslot, | |
232 | .set_current_rxslot = op64_set_current_rxslot, | |
233 | }; | |
234 | ||
235 | static inline int free_slots(struct b43_dmaring *ring) | |
236 | { | |
237 | return (ring->nr_slots - ring->used_slots); | |
238 | } | |
239 | ||
240 | static inline int next_slot(struct b43_dmaring *ring, int slot) | |
241 | { | |
242 | B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); | |
243 | if (slot == ring->nr_slots - 1) | |
244 | return 0; | |
245 | return slot + 1; | |
246 | } | |
247 | ||
248 | static inline int prev_slot(struct b43_dmaring *ring, int slot) | |
249 | { | |
250 | B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); | |
251 | if (slot == 0) | |
252 | return ring->nr_slots - 1; | |
253 | return slot - 1; | |
254 | } | |
255 | ||
256 | #ifdef CONFIG_B43_DEBUG | |
257 | static void update_max_used_slots(struct b43_dmaring *ring, | |
258 | int current_used_slots) | |
259 | { | |
260 | if (current_used_slots <= ring->max_used_slots) | |
261 | return; | |
262 | ring->max_used_slots = current_used_slots; | |
263 | if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) { | |
264 | b43dbg(ring->dev->wl, | |
265 | "max_used_slots increased to %d on %s ring %d\n", | |
266 | ring->max_used_slots, | |
267 | ring->tx ? "TX" : "RX", ring->index); | |
268 | } | |
269 | } | |
270 | #else | |
271 | static inline | |
272 | void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots) | |
273 | { | |
274 | } | |
275 | #endif /* DEBUG */ | |
276 | ||
277 | /* Request a slot for usage. */ | |
278 | static inline int request_slot(struct b43_dmaring *ring) | |
279 | { | |
280 | int slot; | |
281 | ||
282 | B43_WARN_ON(!ring->tx); | |
283 | B43_WARN_ON(ring->stopped); | |
284 | B43_WARN_ON(free_slots(ring) == 0); | |
285 | ||
286 | slot = next_slot(ring, ring->current_slot); | |
287 | ring->current_slot = slot; | |
288 | ring->used_slots++; | |
289 | ||
290 | update_max_used_slots(ring, ring->used_slots); | |
291 | ||
292 | return slot; | |
293 | } | |
294 | ||
b79caa68 | 295 | static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx) |
e4d6b795 MB |
296 | { |
297 | static const u16 map64[] = { | |
298 | B43_MMIO_DMA64_BASE0, | |
299 | B43_MMIO_DMA64_BASE1, | |
300 | B43_MMIO_DMA64_BASE2, | |
301 | B43_MMIO_DMA64_BASE3, | |
302 | B43_MMIO_DMA64_BASE4, | |
303 | B43_MMIO_DMA64_BASE5, | |
304 | }; | |
305 | static const u16 map32[] = { | |
306 | B43_MMIO_DMA32_BASE0, | |
307 | B43_MMIO_DMA32_BASE1, | |
308 | B43_MMIO_DMA32_BASE2, | |
309 | B43_MMIO_DMA32_BASE3, | |
310 | B43_MMIO_DMA32_BASE4, | |
311 | B43_MMIO_DMA32_BASE5, | |
312 | }; | |
313 | ||
b79caa68 | 314 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
315 | B43_WARN_ON(!(controller_idx >= 0 && |
316 | controller_idx < ARRAY_SIZE(map64))); | |
317 | return map64[controller_idx]; | |
318 | } | |
319 | B43_WARN_ON(!(controller_idx >= 0 && | |
320 | controller_idx < ARRAY_SIZE(map32))); | |
321 | return map32[controller_idx]; | |
322 | } | |
323 | ||
324 | static inline | |
325 | dma_addr_t map_descbuffer(struct b43_dmaring *ring, | |
326 | unsigned char *buf, size_t len, int tx) | |
327 | { | |
328 | dma_addr_t dmaaddr; | |
329 | ||
330 | if (tx) { | |
331 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
332 | buf, len, DMA_TO_DEVICE); | |
333 | } else { | |
334 | dmaaddr = dma_map_single(ring->dev->dev->dev, | |
335 | buf, len, DMA_FROM_DEVICE); | |
336 | } | |
337 | ||
338 | return dmaaddr; | |
339 | } | |
340 | ||
341 | static inline | |
342 | void unmap_descbuffer(struct b43_dmaring *ring, | |
343 | dma_addr_t addr, size_t len, int tx) | |
344 | { | |
345 | if (tx) { | |
346 | dma_unmap_single(ring->dev->dev->dev, addr, len, DMA_TO_DEVICE); | |
347 | } else { | |
348 | dma_unmap_single(ring->dev->dev->dev, | |
349 | addr, len, DMA_FROM_DEVICE); | |
350 | } | |
351 | } | |
352 | ||
353 | static inline | |
354 | void sync_descbuffer_for_cpu(struct b43_dmaring *ring, | |
355 | dma_addr_t addr, size_t len) | |
356 | { | |
357 | B43_WARN_ON(ring->tx); | |
358 | dma_sync_single_for_cpu(ring->dev->dev->dev, | |
359 | addr, len, DMA_FROM_DEVICE); | |
360 | } | |
361 | ||
362 | static inline | |
363 | void sync_descbuffer_for_device(struct b43_dmaring *ring, | |
364 | dma_addr_t addr, size_t len) | |
365 | { | |
366 | B43_WARN_ON(ring->tx); | |
367 | dma_sync_single_for_device(ring->dev->dev->dev, | |
368 | addr, len, DMA_FROM_DEVICE); | |
369 | } | |
370 | ||
371 | static inline | |
372 | void free_descriptor_buffer(struct b43_dmaring *ring, | |
373 | struct b43_dmadesc_meta *meta) | |
374 | { | |
375 | if (meta->skb) { | |
376 | dev_kfree_skb_any(meta->skb); | |
377 | meta->skb = NULL; | |
378 | } | |
379 | } | |
380 | ||
381 | static int alloc_ringmemory(struct b43_dmaring *ring) | |
382 | { | |
383 | struct device *dev = ring->dev->dev->dev; | |
013978b6 LF |
384 | gfp_t flags = GFP_KERNEL; |
385 | ||
386 | /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K | |
387 | * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing | |
388 | * has shown that 4K is sufficient for the latter as long as the buffer | |
389 | * does not cross an 8K boundary. | |
390 | * | |
391 | * For unknown reasons - possibly a hardware error - the BCM4311 rev | |
392 | * 02, which uses 64-bit DMA, needs the ring buffer in very low memory, | |
393 | * which accounts for the GFP_DMA flag below. | |
394 | */ | |
b79caa68 | 395 | if (ring->type == B43_DMA_64BIT) |
013978b6 | 396 | flags |= GFP_DMA; |
e4d6b795 | 397 | ring->descbase = dma_alloc_coherent(dev, B43_DMA_RINGMEMSIZE, |
013978b6 | 398 | &(ring->dmabase), flags); |
e4d6b795 MB |
399 | if (!ring->descbase) { |
400 | b43err(ring->dev->wl, "DMA ringmemory allocation failed\n"); | |
401 | return -ENOMEM; | |
402 | } | |
403 | memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE); | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static void free_ringmemory(struct b43_dmaring *ring) | |
409 | { | |
410 | struct device *dev = ring->dev->dev->dev; | |
411 | ||
412 | dma_free_coherent(dev, B43_DMA_RINGMEMSIZE, | |
413 | ring->descbase, ring->dmabase); | |
414 | } | |
415 | ||
416 | /* Reset the RX DMA channel */ | |
b79caa68 MB |
417 | static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, |
418 | enum b43_dmatype type) | |
e4d6b795 MB |
419 | { |
420 | int i; | |
421 | u32 value; | |
422 | u16 offset; | |
423 | ||
424 | might_sleep(); | |
425 | ||
b79caa68 | 426 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL; |
e4d6b795 MB |
427 | b43_write32(dev, mmio_base + offset, 0); |
428 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
429 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS : |
430 | B43_DMA32_RXSTATUS; | |
e4d6b795 | 431 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 432 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
433 | value &= B43_DMA64_RXSTAT; |
434 | if (value == B43_DMA64_RXSTAT_DISABLED) { | |
435 | i = -1; | |
436 | break; | |
437 | } | |
438 | } else { | |
439 | value &= B43_DMA32_RXSTATE; | |
440 | if (value == B43_DMA32_RXSTAT_DISABLED) { | |
441 | i = -1; | |
442 | break; | |
443 | } | |
444 | } | |
445 | msleep(1); | |
446 | } | |
447 | if (i != -1) { | |
448 | b43err(dev->wl, "DMA RX reset timed out\n"); | |
449 | return -ENODEV; | |
450 | } | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
013978b6 | 455 | /* Reset the TX DMA channel */ |
b79caa68 MB |
456 | static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, |
457 | enum b43_dmatype type) | |
e4d6b795 MB |
458 | { |
459 | int i; | |
460 | u32 value; | |
461 | u16 offset; | |
462 | ||
463 | might_sleep(); | |
464 | ||
465 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
466 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
467 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 468 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 469 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
470 | value &= B43_DMA64_TXSTAT; |
471 | if (value == B43_DMA64_TXSTAT_DISABLED || | |
472 | value == B43_DMA64_TXSTAT_IDLEWAIT || | |
473 | value == B43_DMA64_TXSTAT_STOPPED) | |
474 | break; | |
475 | } else { | |
476 | value &= B43_DMA32_TXSTATE; | |
477 | if (value == B43_DMA32_TXSTAT_DISABLED || | |
478 | value == B43_DMA32_TXSTAT_IDLEWAIT || | |
479 | value == B43_DMA32_TXSTAT_STOPPED) | |
480 | break; | |
481 | } | |
482 | msleep(1); | |
483 | } | |
b79caa68 | 484 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL; |
e4d6b795 MB |
485 | b43_write32(dev, mmio_base + offset, 0); |
486 | for (i = 0; i < 10; i++) { | |
b79caa68 MB |
487 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
488 | B43_DMA32_TXSTATUS; | |
e4d6b795 | 489 | value = b43_read32(dev, mmio_base + offset); |
b79caa68 | 490 | if (type == B43_DMA_64BIT) { |
e4d6b795 MB |
491 | value &= B43_DMA64_TXSTAT; |
492 | if (value == B43_DMA64_TXSTAT_DISABLED) { | |
493 | i = -1; | |
494 | break; | |
495 | } | |
496 | } else { | |
497 | value &= B43_DMA32_TXSTATE; | |
498 | if (value == B43_DMA32_TXSTAT_DISABLED) { | |
499 | i = -1; | |
500 | break; | |
501 | } | |
502 | } | |
503 | msleep(1); | |
504 | } | |
505 | if (i != -1) { | |
506 | b43err(dev->wl, "DMA TX reset timed out\n"); | |
507 | return -ENODEV; | |
508 | } | |
509 | /* ensure the reset is completed. */ | |
510 | msleep(1); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
b79caa68 MB |
515 | /* Check if a DMA mapping address is invalid. */ |
516 | static bool b43_dma_mapping_error(struct b43_dmaring *ring, | |
517 | dma_addr_t addr, | |
518 | size_t buffersize) | |
519 | { | |
520 | if (unlikely(dma_mapping_error(addr))) | |
521 | return 1; | |
522 | ||
523 | switch (ring->type) { | |
524 | case B43_DMA_30BIT: | |
525 | if ((u64)addr + buffersize > (1ULL << 30)) | |
526 | return 1; | |
527 | break; | |
528 | case B43_DMA_32BIT: | |
529 | if ((u64)addr + buffersize > (1ULL << 32)) | |
530 | return 1; | |
531 | break; | |
532 | case B43_DMA_64BIT: | |
533 | /* Currently we can't have addresses beyond | |
534 | * 64bit in the kernel. */ | |
535 | break; | |
536 | } | |
537 | ||
538 | /* The address is OK. */ | |
539 | return 0; | |
540 | } | |
541 | ||
e4d6b795 MB |
542 | static int setup_rx_descbuffer(struct b43_dmaring *ring, |
543 | struct b43_dmadesc_generic *desc, | |
544 | struct b43_dmadesc_meta *meta, gfp_t gfp_flags) | |
545 | { | |
546 | struct b43_rxhdr_fw4 *rxhdr; | |
547 | struct b43_hwtxstatus *txstat; | |
548 | dma_addr_t dmaaddr; | |
549 | struct sk_buff *skb; | |
550 | ||
551 | B43_WARN_ON(ring->tx); | |
552 | ||
553 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
554 | if (unlikely(!skb)) | |
555 | return -ENOMEM; | |
556 | dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0); | |
b79caa68 | 557 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) { |
e4d6b795 MB |
558 | /* ugh. try to realloc in zone_dma */ |
559 | gfp_flags |= GFP_DMA; | |
560 | ||
561 | dev_kfree_skb_any(skb); | |
562 | ||
563 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); | |
564 | if (unlikely(!skb)) | |
565 | return -ENOMEM; | |
566 | dmaaddr = map_descbuffer(ring, skb->data, | |
567 | ring->rx_buffersize, 0); | |
568 | } | |
569 | ||
b79caa68 | 570 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize)) { |
e4d6b795 MB |
571 | dev_kfree_skb_any(skb); |
572 | return -EIO; | |
573 | } | |
574 | ||
575 | meta->skb = skb; | |
576 | meta->dmaaddr = dmaaddr; | |
577 | ring->ops->fill_descriptor(ring, desc, dmaaddr, | |
578 | ring->rx_buffersize, 0, 0, 0); | |
579 | ||
580 | rxhdr = (struct b43_rxhdr_fw4 *)(skb->data); | |
581 | rxhdr->frame_len = 0; | |
582 | txstat = (struct b43_hwtxstatus *)(skb->data); | |
583 | txstat->cookie = 0; | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
588 | /* Allocate the initial descbuffers. | |
589 | * This is used for an RX ring only. | |
590 | */ | |
591 | static int alloc_initial_descbuffers(struct b43_dmaring *ring) | |
592 | { | |
593 | int i, err = -ENOMEM; | |
594 | struct b43_dmadesc_generic *desc; | |
595 | struct b43_dmadesc_meta *meta; | |
596 | ||
597 | for (i = 0; i < ring->nr_slots; i++) { | |
598 | desc = ring->ops->idx2desc(ring, i, &meta); | |
599 | ||
600 | err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); | |
601 | if (err) { | |
602 | b43err(ring->dev->wl, | |
603 | "Failed to allocate initial descbuffers\n"); | |
604 | goto err_unwind; | |
605 | } | |
606 | } | |
607 | mb(); | |
608 | ring->used_slots = ring->nr_slots; | |
609 | err = 0; | |
610 | out: | |
611 | return err; | |
612 | ||
613 | err_unwind: | |
614 | for (i--; i >= 0; i--) { | |
615 | desc = ring->ops->idx2desc(ring, i, &meta); | |
616 | ||
617 | unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); | |
618 | dev_kfree_skb(meta->skb); | |
619 | } | |
620 | goto out; | |
621 | } | |
622 | ||
623 | /* Do initial setup of the DMA controller. | |
624 | * Reset the controller, write the ring busaddress | |
625 | * and switch the "enable" bit on. | |
626 | */ | |
627 | static int dmacontroller_setup(struct b43_dmaring *ring) | |
628 | { | |
629 | int err = 0; | |
630 | u32 value; | |
631 | u32 addrext; | |
632 | u32 trans = ssb_dma_translation(ring->dev->dev); | |
633 | ||
634 | if (ring->tx) { | |
b79caa68 | 635 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
636 | u64 ringbase = (u64) (ring->dmabase); |
637 | ||
638 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
639 | >> SSB_DMA_TRANSLATION_SHIFT; | |
640 | value = B43_DMA64_TXENABLE; | |
641 | value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) | |
642 | & B43_DMA64_TXADDREXT_MASK; | |
643 | b43_dma_write(ring, B43_DMA64_TXCTL, value); | |
644 | b43_dma_write(ring, B43_DMA64_TXRINGLO, | |
645 | (ringbase & 0xFFFFFFFF)); | |
646 | b43_dma_write(ring, B43_DMA64_TXRINGHI, | |
647 | ((ringbase >> 32) & | |
648 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 | 649 | | (trans << 1)); |
e4d6b795 MB |
650 | } else { |
651 | u32 ringbase = (u32) (ring->dmabase); | |
652 | ||
653 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
654 | >> SSB_DMA_TRANSLATION_SHIFT; | |
655 | value = B43_DMA32_TXENABLE; | |
656 | value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) | |
657 | & B43_DMA32_TXADDREXT_MASK; | |
658 | b43_dma_write(ring, B43_DMA32_TXCTL, value); | |
659 | b43_dma_write(ring, B43_DMA32_TXRING, | |
660 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
661 | | trans); | |
662 | } | |
663 | } else { | |
664 | err = alloc_initial_descbuffers(ring); | |
665 | if (err) | |
666 | goto out; | |
b79caa68 | 667 | if (ring->type == B43_DMA_64BIT) { |
e4d6b795 MB |
668 | u64 ringbase = (u64) (ring->dmabase); |
669 | ||
670 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) | |
671 | >> SSB_DMA_TRANSLATION_SHIFT; | |
672 | value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT); | |
673 | value |= B43_DMA64_RXENABLE; | |
674 | value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) | |
675 | & B43_DMA64_RXADDREXT_MASK; | |
676 | b43_dma_write(ring, B43_DMA64_RXCTL, value); | |
677 | b43_dma_write(ring, B43_DMA64_RXRINGLO, | |
678 | (ringbase & 0xFFFFFFFF)); | |
679 | b43_dma_write(ring, B43_DMA64_RXRINGHI, | |
680 | ((ringbase >> 32) & | |
681 | ~SSB_DMA_TRANSLATION_MASK) | |
013978b6 LF |
682 | | (trans << 1)); |
683 | b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * | |
684 | sizeof(struct b43_dmadesc64)); | |
e4d6b795 MB |
685 | } else { |
686 | u32 ringbase = (u32) (ring->dmabase); | |
687 | ||
688 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) | |
689 | >> SSB_DMA_TRANSLATION_SHIFT; | |
690 | value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT); | |
691 | value |= B43_DMA32_RXENABLE; | |
692 | value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) | |
693 | & B43_DMA32_RXADDREXT_MASK; | |
694 | b43_dma_write(ring, B43_DMA32_RXCTL, value); | |
695 | b43_dma_write(ring, B43_DMA32_RXRING, | |
696 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) | |
697 | | trans); | |
013978b6 LF |
698 | b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots * |
699 | sizeof(struct b43_dmadesc32)); | |
e4d6b795 MB |
700 | } |
701 | } | |
702 | ||
013978b6 | 703 | out: |
e4d6b795 MB |
704 | return err; |
705 | } | |
706 | ||
707 | /* Shutdown the DMA controller. */ | |
708 | static void dmacontroller_cleanup(struct b43_dmaring *ring) | |
709 | { | |
710 | if (ring->tx) { | |
711 | b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
712 | ring->type); |
713 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
714 | b43_dma_write(ring, B43_DMA64_TXRINGLO, 0); |
715 | b43_dma_write(ring, B43_DMA64_TXRINGHI, 0); | |
716 | } else | |
717 | b43_dma_write(ring, B43_DMA32_TXRING, 0); | |
718 | } else { | |
719 | b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base, | |
b79caa68 MB |
720 | ring->type); |
721 | if (ring->type == B43_DMA_64BIT) { | |
e4d6b795 MB |
722 | b43_dma_write(ring, B43_DMA64_RXRINGLO, 0); |
723 | b43_dma_write(ring, B43_DMA64_RXRINGHI, 0); | |
724 | } else | |
725 | b43_dma_write(ring, B43_DMA32_RXRING, 0); | |
726 | } | |
727 | } | |
728 | ||
729 | static void free_all_descbuffers(struct b43_dmaring *ring) | |
730 | { | |
731 | struct b43_dmadesc_generic *desc; | |
732 | struct b43_dmadesc_meta *meta; | |
733 | int i; | |
734 | ||
735 | if (!ring->used_slots) | |
736 | return; | |
737 | for (i = 0; i < ring->nr_slots; i++) { | |
738 | desc = ring->ops->idx2desc(ring, i, &meta); | |
739 | ||
740 | if (!meta->skb) { | |
741 | B43_WARN_ON(!ring->tx); | |
742 | continue; | |
743 | } | |
744 | if (ring->tx) { | |
745 | unmap_descbuffer(ring, meta->dmaaddr, | |
746 | meta->skb->len, 1); | |
747 | } else { | |
748 | unmap_descbuffer(ring, meta->dmaaddr, | |
749 | ring->rx_buffersize, 0); | |
750 | } | |
751 | free_descriptor_buffer(ring, meta); | |
752 | } | |
753 | } | |
754 | ||
755 | static u64 supported_dma_mask(struct b43_wldev *dev) | |
756 | { | |
757 | u32 tmp; | |
758 | u16 mmio_base; | |
759 | ||
760 | tmp = b43_read32(dev, SSB_TMSHIGH); | |
761 | if (tmp & SSB_TMSHIGH_DMA64) | |
762 | return DMA_64BIT_MASK; | |
763 | mmio_base = b43_dmacontroller_base(0, 0); | |
764 | b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK); | |
765 | tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL); | |
766 | if (tmp & B43_DMA32_TXADDREXT_MASK) | |
767 | return DMA_32BIT_MASK; | |
768 | ||
769 | return DMA_30BIT_MASK; | |
770 | } | |
771 | ||
772 | /* Main initialization function. */ | |
773 | static | |
774 | struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev, | |
775 | int controller_index, | |
b79caa68 MB |
776 | int for_tx, |
777 | enum b43_dmatype type) | |
e4d6b795 MB |
778 | { |
779 | struct b43_dmaring *ring; | |
780 | int err; | |
781 | int nr_slots; | |
782 | dma_addr_t dma_test; | |
783 | ||
784 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); | |
785 | if (!ring) | |
786 | goto out; | |
b79caa68 | 787 | ring->type = type; |
e4d6b795 MB |
788 | |
789 | nr_slots = B43_RXRING_SLOTS; | |
790 | if (for_tx) | |
791 | nr_slots = B43_TXRING_SLOTS; | |
792 | ||
793 | ring->meta = kcalloc(nr_slots, sizeof(struct b43_dmadesc_meta), | |
794 | GFP_KERNEL); | |
795 | if (!ring->meta) | |
796 | goto err_kfree_ring; | |
797 | if (for_tx) { | |
798 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 799 | b43_txhdr_size(dev), |
e4d6b795 MB |
800 | GFP_KERNEL); |
801 | if (!ring->txhdr_cache) | |
802 | goto err_kfree_meta; | |
803 | ||
804 | /* test for ability to dma to txhdr_cache */ | |
805 | dma_test = dma_map_single(dev->dev->dev, | |
806 | ring->txhdr_cache, | |
eb189d8b | 807 | b43_txhdr_size(dev), |
e4d6b795 MB |
808 | DMA_TO_DEVICE); |
809 | ||
b79caa68 | 810 | if (b43_dma_mapping_error(ring, dma_test, b43_txhdr_size(dev))) { |
e4d6b795 MB |
811 | /* ugh realloc */ |
812 | kfree(ring->txhdr_cache); | |
813 | ring->txhdr_cache = kcalloc(nr_slots, | |
eb189d8b | 814 | b43_txhdr_size(dev), |
e4d6b795 MB |
815 | GFP_KERNEL | GFP_DMA); |
816 | if (!ring->txhdr_cache) | |
817 | goto err_kfree_meta; | |
818 | ||
819 | dma_test = dma_map_single(dev->dev->dev, | |
820 | ring->txhdr_cache, | |
eb189d8b | 821 | b43_txhdr_size(dev), |
e4d6b795 MB |
822 | DMA_TO_DEVICE); |
823 | ||
b79caa68 MB |
824 | if (b43_dma_mapping_error(ring, dma_test, |
825 | b43_txhdr_size(dev))) | |
e4d6b795 MB |
826 | goto err_kfree_txhdr_cache; |
827 | } | |
828 | ||
829 | dma_unmap_single(dev->dev->dev, | |
eb189d8b | 830 | dma_test, b43_txhdr_size(dev), |
e4d6b795 MB |
831 | DMA_TO_DEVICE); |
832 | } | |
833 | ||
834 | ring->dev = dev; | |
835 | ring->nr_slots = nr_slots; | |
b79caa68 | 836 | ring->mmio_base = b43_dmacontroller_base(type, controller_index); |
e4d6b795 | 837 | ring->index = controller_index; |
b79caa68 | 838 | if (type == B43_DMA_64BIT) |
e4d6b795 MB |
839 | ring->ops = &dma64_ops; |
840 | else | |
841 | ring->ops = &dma32_ops; | |
842 | if (for_tx) { | |
843 | ring->tx = 1; | |
844 | ring->current_slot = -1; | |
845 | } else { | |
846 | if (ring->index == 0) { | |
847 | ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE; | |
848 | ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET; | |
849 | } else if (ring->index == 3) { | |
850 | ring->rx_buffersize = B43_DMA3_RX_BUFFERSIZE; | |
851 | ring->frameoffset = B43_DMA3_RX_FRAMEOFFSET; | |
852 | } else | |
853 | B43_WARN_ON(1); | |
854 | } | |
855 | spin_lock_init(&ring->lock); | |
856 | #ifdef CONFIG_B43_DEBUG | |
857 | ring->last_injected_overflow = jiffies; | |
858 | #endif | |
859 | ||
860 | err = alloc_ringmemory(ring); | |
861 | if (err) | |
862 | goto err_kfree_txhdr_cache; | |
863 | err = dmacontroller_setup(ring); | |
864 | if (err) | |
865 | goto err_free_ringmemory; | |
866 | ||
867 | out: | |
868 | return ring; | |
869 | ||
870 | err_free_ringmemory: | |
871 | free_ringmemory(ring); | |
872 | err_kfree_txhdr_cache: | |
873 | kfree(ring->txhdr_cache); | |
874 | err_kfree_meta: | |
875 | kfree(ring->meta); | |
876 | err_kfree_ring: | |
877 | kfree(ring); | |
878 | ring = NULL; | |
879 | goto out; | |
880 | } | |
881 | ||
57df40d2 MB |
882 | #define divide(a, b) ({ \ |
883 | typeof(a) __a = a; \ | |
884 | do_div(__a, b); \ | |
885 | __a; \ | |
886 | }) | |
887 | ||
888 | #define modulo(a, b) ({ \ | |
889 | typeof(a) __a = a; \ | |
890 | do_div(__a, b); \ | |
891 | }) | |
892 | ||
e4d6b795 | 893 | /* Main cleanup function. */ |
b27faf8e MB |
894 | static void b43_destroy_dmaring(struct b43_dmaring *ring, |
895 | const char *ringname) | |
e4d6b795 MB |
896 | { |
897 | if (!ring) | |
898 | return; | |
899 | ||
57df40d2 MB |
900 | #ifdef CONFIG_B43_DEBUG |
901 | { | |
902 | /* Print some statistics. */ | |
903 | u64 failed_packets = ring->nr_failed_tx_packets; | |
904 | u64 succeed_packets = ring->nr_succeed_tx_packets; | |
905 | u64 nr_packets = failed_packets + succeed_packets; | |
906 | u64 permille_failed = 0, average_tries = 0; | |
907 | ||
908 | if (nr_packets) | |
909 | permille_failed = divide(failed_packets * 1000, nr_packets); | |
910 | if (nr_packets) | |
911 | average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets); | |
912 | ||
913 | b43dbg(ring->dev->wl, "DMA-%u %s: " | |
914 | "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, " | |
915 | "Average tries %llu.%02llu\n", | |
916 | (unsigned int)(ring->type), ringname, | |
917 | ring->max_used_slots, | |
918 | ring->nr_slots, | |
919 | (unsigned long long)failed_packets, | |
920 | (unsigned long long)succeed_packets, | |
921 | (unsigned long long)divide(permille_failed, 10), | |
922 | (unsigned long long)modulo(permille_failed, 10), | |
923 | (unsigned long long)divide(average_tries, 100), | |
924 | (unsigned long long)modulo(average_tries, 100)); | |
925 | } | |
926 | #endif /* DEBUG */ | |
927 | ||
e4d6b795 MB |
928 | /* Device IRQs are disabled prior entering this function, |
929 | * so no need to take care of concurrency with rx handler stuff. | |
930 | */ | |
931 | dmacontroller_cleanup(ring); | |
932 | free_all_descbuffers(ring); | |
933 | free_ringmemory(ring); | |
934 | ||
935 | kfree(ring->txhdr_cache); | |
936 | kfree(ring->meta); | |
937 | kfree(ring); | |
938 | } | |
939 | ||
b27faf8e MB |
940 | #define destroy_ring(dma, ring) do { \ |
941 | b43_destroy_dmaring((dma)->ring, __stringify(ring)); \ | |
942 | (dma)->ring = NULL; \ | |
943 | } while (0) | |
944 | ||
e4d6b795 MB |
945 | void b43_dma_free(struct b43_wldev *dev) |
946 | { | |
03b29773 | 947 | struct b43_dma *dma = &dev->dma; |
e4d6b795 | 948 | |
b27faf8e MB |
949 | destroy_ring(dma, rx_ring); |
950 | destroy_ring(dma, tx_ring_AC_BK); | |
951 | destroy_ring(dma, tx_ring_AC_BE); | |
952 | destroy_ring(dma, tx_ring_AC_VI); | |
953 | destroy_ring(dma, tx_ring_AC_VO); | |
954 | destroy_ring(dma, tx_ring_mcast); | |
e4d6b795 MB |
955 | } |
956 | ||
957 | int b43_dma_init(struct b43_wldev *dev) | |
958 | { | |
959 | struct b43_dma *dma = &dev->dma; | |
e4d6b795 MB |
960 | int err; |
961 | u64 dmamask; | |
b79caa68 | 962 | enum b43_dmatype type; |
e4d6b795 MB |
963 | |
964 | dmamask = supported_dma_mask(dev); | |
b79caa68 MB |
965 | switch (dmamask) { |
966 | default: | |
967 | B43_WARN_ON(1); | |
968 | case DMA_30BIT_MASK: | |
969 | type = B43_DMA_30BIT; | |
970 | break; | |
971 | case DMA_32BIT_MASK: | |
972 | type = B43_DMA_32BIT; | |
973 | break; | |
974 | case DMA_64BIT_MASK: | |
975 | type = B43_DMA_64BIT; | |
976 | break; | |
977 | } | |
e4d6b795 MB |
978 | err = ssb_dma_set_mask(dev->dev, dmamask); |
979 | if (err) { | |
03b29773 MB |
980 | b43err(dev->wl, "The machine/kernel does not support " |
981 | "the required DMA mask (0x%08X%08X)\n", | |
982 | (unsigned int)((dmamask & 0xFFFFFFFF00000000ULL) >> 32), | |
983 | (unsigned int)(dmamask & 0x00000000FFFFFFFFULL)); | |
e4d6b795 | 984 | return -EOPNOTSUPP; |
e4d6b795 MB |
985 | } |
986 | ||
987 | err = -ENOMEM; | |
988 | /* setup TX DMA channels. */ | |
b27faf8e MB |
989 | dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type); |
990 | if (!dma->tx_ring_AC_BK) | |
e4d6b795 | 991 | goto out; |
e4d6b795 | 992 | |
b27faf8e MB |
993 | dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type); |
994 | if (!dma->tx_ring_AC_BE) | |
995 | goto err_destroy_bk; | |
e4d6b795 | 996 | |
b27faf8e MB |
997 | dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type); |
998 | if (!dma->tx_ring_AC_VI) | |
999 | goto err_destroy_be; | |
e4d6b795 | 1000 | |
b27faf8e MB |
1001 | dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type); |
1002 | if (!dma->tx_ring_AC_VO) | |
1003 | goto err_destroy_vi; | |
e4d6b795 | 1004 | |
b27faf8e MB |
1005 | dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type); |
1006 | if (!dma->tx_ring_mcast) | |
1007 | goto err_destroy_vo; | |
e4d6b795 | 1008 | |
b27faf8e MB |
1009 | /* setup RX DMA channel. */ |
1010 | dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type); | |
1011 | if (!dma->rx_ring) | |
1012 | goto err_destroy_mcast; | |
e4d6b795 | 1013 | |
b27faf8e MB |
1014 | /* No support for the TX status DMA ring. */ |
1015 | B43_WARN_ON(dev->dev->id.revision < 5); | |
e4d6b795 | 1016 | |
b79caa68 MB |
1017 | b43dbg(dev->wl, "%u-bit DMA initialized\n", |
1018 | (unsigned int)type); | |
e4d6b795 | 1019 | err = 0; |
b27faf8e | 1020 | out: |
e4d6b795 MB |
1021 | return err; |
1022 | ||
b27faf8e MB |
1023 | err_destroy_mcast: |
1024 | destroy_ring(dma, tx_ring_mcast); | |
1025 | err_destroy_vo: | |
1026 | destroy_ring(dma, tx_ring_AC_VO); | |
1027 | err_destroy_vi: | |
1028 | destroy_ring(dma, tx_ring_AC_VI); | |
1029 | err_destroy_be: | |
1030 | destroy_ring(dma, tx_ring_AC_BE); | |
1031 | err_destroy_bk: | |
1032 | destroy_ring(dma, tx_ring_AC_BK); | |
1033 | return err; | |
e4d6b795 MB |
1034 | } |
1035 | ||
1036 | /* Generate a cookie for the TX header. */ | |
1037 | static u16 generate_cookie(struct b43_dmaring *ring, int slot) | |
1038 | { | |
b27faf8e | 1039 | u16 cookie; |
e4d6b795 MB |
1040 | |
1041 | /* Use the upper 4 bits of the cookie as | |
1042 | * DMA controller ID and store the slot number | |
1043 | * in the lower 12 bits. | |
1044 | * Note that the cookie must never be 0, as this | |
1045 | * is a special value used in RX path. | |
280d0e16 MB |
1046 | * It can also not be 0xFFFF because that is special |
1047 | * for multicast frames. | |
e4d6b795 | 1048 | */ |
b27faf8e | 1049 | cookie = (((u16)ring->index + 1) << 12); |
e4d6b795 | 1050 | B43_WARN_ON(slot & ~0x0FFF); |
b27faf8e | 1051 | cookie |= (u16)slot; |
e4d6b795 MB |
1052 | |
1053 | return cookie; | |
1054 | } | |
1055 | ||
1056 | /* Inspect a cookie and find out to which controller/slot it belongs. */ | |
1057 | static | |
1058 | struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot) | |
1059 | { | |
1060 | struct b43_dma *dma = &dev->dma; | |
1061 | struct b43_dmaring *ring = NULL; | |
1062 | ||
1063 | switch (cookie & 0xF000) { | |
280d0e16 | 1064 | case 0x1000: |
b27faf8e | 1065 | ring = dma->tx_ring_AC_BK; |
e4d6b795 | 1066 | break; |
280d0e16 | 1067 | case 0x2000: |
b27faf8e | 1068 | ring = dma->tx_ring_AC_BE; |
e4d6b795 | 1069 | break; |
280d0e16 | 1070 | case 0x3000: |
b27faf8e | 1071 | ring = dma->tx_ring_AC_VI; |
e4d6b795 | 1072 | break; |
280d0e16 | 1073 | case 0x4000: |
b27faf8e | 1074 | ring = dma->tx_ring_AC_VO; |
e4d6b795 | 1075 | break; |
280d0e16 | 1076 | case 0x5000: |
b27faf8e | 1077 | ring = dma->tx_ring_mcast; |
e4d6b795 MB |
1078 | break; |
1079 | default: | |
1080 | B43_WARN_ON(1); | |
1081 | } | |
1082 | *slot = (cookie & 0x0FFF); | |
1083 | B43_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots)); | |
1084 | ||
1085 | return ring; | |
1086 | } | |
1087 | ||
1088 | static int dma_tx_fragment(struct b43_dmaring *ring, | |
1089 | struct sk_buff *skb, | |
1090 | struct ieee80211_tx_control *ctl) | |
1091 | { | |
1092 | const struct b43_dma_ops *ops = ring->ops; | |
1093 | u8 *header; | |
09552ccd | 1094 | int slot, old_top_slot, old_used_slots; |
e4d6b795 MB |
1095 | int err; |
1096 | struct b43_dmadesc_generic *desc; | |
1097 | struct b43_dmadesc_meta *meta; | |
1098 | struct b43_dmadesc_meta *meta_hdr; | |
1099 | struct sk_buff *bounce_skb; | |
280d0e16 | 1100 | u16 cookie; |
eb189d8b | 1101 | size_t hdrsize = b43_txhdr_size(ring->dev); |
e4d6b795 MB |
1102 | |
1103 | #define SLOTS_PER_PACKET 2 | |
1104 | B43_WARN_ON(skb_shinfo(skb)->nr_frags); | |
1105 | ||
09552ccd MB |
1106 | old_top_slot = ring->current_slot; |
1107 | old_used_slots = ring->used_slots; | |
1108 | ||
e4d6b795 MB |
1109 | /* Get a slot for the header. */ |
1110 | slot = request_slot(ring); | |
1111 | desc = ops->idx2desc(ring, slot, &meta_hdr); | |
1112 | memset(meta_hdr, 0, sizeof(*meta_hdr)); | |
1113 | ||
eb189d8b | 1114 | header = &(ring->txhdr_cache[slot * hdrsize]); |
280d0e16 | 1115 | cookie = generate_cookie(ring, slot); |
09552ccd MB |
1116 | err = b43_generate_txhdr(ring->dev, header, |
1117 | skb->data, skb->len, ctl, cookie); | |
1118 | if (unlikely(err)) { | |
1119 | ring->current_slot = old_top_slot; | |
1120 | ring->used_slots = old_used_slots; | |
1121 | return err; | |
1122 | } | |
e4d6b795 MB |
1123 | |
1124 | meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, | |
eb189d8b | 1125 | hdrsize, 1); |
b79caa68 | 1126 | if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize)) { |
09552ccd MB |
1127 | ring->current_slot = old_top_slot; |
1128 | ring->used_slots = old_used_slots; | |
e4d6b795 | 1129 | return -EIO; |
09552ccd | 1130 | } |
e4d6b795 | 1131 | ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr, |
eb189d8b | 1132 | hdrsize, 1, 0, 0); |
e4d6b795 MB |
1133 | |
1134 | /* Get a slot for the payload. */ | |
1135 | slot = request_slot(ring); | |
1136 | desc = ops->idx2desc(ring, slot, &meta); | |
1137 | memset(meta, 0, sizeof(*meta)); | |
1138 | ||
1139 | memcpy(&meta->txstat.control, ctl, sizeof(*ctl)); | |
1140 | meta->skb = skb; | |
1141 | meta->is_last_fragment = 1; | |
1142 | ||
1143 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
1144 | /* create a bounce buffer in zone_dma on mapping failure. */ | |
b79caa68 | 1145 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) { |
e4d6b795 MB |
1146 | bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA); |
1147 | if (!bounce_skb) { | |
09552ccd MB |
1148 | ring->current_slot = old_top_slot; |
1149 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1150 | err = -ENOMEM; |
1151 | goto out_unmap_hdr; | |
1152 | } | |
1153 | ||
1154 | memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len); | |
1155 | dev_kfree_skb_any(skb); | |
1156 | skb = bounce_skb; | |
1157 | meta->skb = skb; | |
1158 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); | |
b79caa68 | 1159 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len)) { |
09552ccd MB |
1160 | ring->current_slot = old_top_slot; |
1161 | ring->used_slots = old_used_slots; | |
e4d6b795 MB |
1162 | err = -EIO; |
1163 | goto out_free_bounce; | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); | |
1168 | ||
280d0e16 MB |
1169 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { |
1170 | /* Tell the firmware about the cookie of the last | |
1171 | * mcast frame, so it can clear the more-data bit in it. */ | |
1172 | b43_shm_write16(ring->dev, B43_SHM_SHARED, | |
1173 | B43_SHM_SH_MCASTCOOKIE, cookie); | |
1174 | } | |
e4d6b795 MB |
1175 | /* Now transfer the whole frame. */ |
1176 | wmb(); | |
1177 | ops->poke_tx(ring, next_slot(ring, slot)); | |
1178 | return 0; | |
1179 | ||
280d0e16 | 1180 | out_free_bounce: |
e4d6b795 | 1181 | dev_kfree_skb_any(skb); |
280d0e16 | 1182 | out_unmap_hdr: |
e4d6b795 | 1183 | unmap_descbuffer(ring, meta_hdr->dmaaddr, |
eb189d8b | 1184 | hdrsize, 1); |
e4d6b795 MB |
1185 | return err; |
1186 | } | |
1187 | ||
1188 | static inline int should_inject_overflow(struct b43_dmaring *ring) | |
1189 | { | |
1190 | #ifdef CONFIG_B43_DEBUG | |
1191 | if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) { | |
1192 | /* Check if we should inject another ringbuffer overflow | |
1193 | * to test handling of this situation in the stack. */ | |
1194 | unsigned long next_overflow; | |
1195 | ||
1196 | next_overflow = ring->last_injected_overflow + HZ; | |
1197 | if (time_after(jiffies, next_overflow)) { | |
1198 | ring->last_injected_overflow = jiffies; | |
1199 | b43dbg(ring->dev->wl, | |
1200 | "Injecting TX ring overflow on " | |
1201 | "DMA controller %d\n", ring->index); | |
1202 | return 1; | |
1203 | } | |
1204 | } | |
1205 | #endif /* CONFIG_B43_DEBUG */ | |
1206 | return 0; | |
1207 | } | |
1208 | ||
e6f5b934 MB |
1209 | /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */ |
1210 | static struct b43_dmaring * select_ring_by_priority(struct b43_wldev *dev, | |
1211 | u8 queue_prio) | |
1212 | { | |
1213 | struct b43_dmaring *ring; | |
1214 | ||
1215 | if (b43_modparam_qos) { | |
1216 | /* 0 = highest priority */ | |
1217 | switch (queue_prio) { | |
1218 | default: | |
1219 | B43_WARN_ON(1); | |
1220 | /* fallthrough */ | |
1221 | case 0: | |
b27faf8e | 1222 | ring = dev->dma.tx_ring_AC_VO; |
e6f5b934 MB |
1223 | break; |
1224 | case 1: | |
b27faf8e | 1225 | ring = dev->dma.tx_ring_AC_VI; |
e6f5b934 MB |
1226 | break; |
1227 | case 2: | |
b27faf8e | 1228 | ring = dev->dma.tx_ring_AC_BE; |
e6f5b934 MB |
1229 | break; |
1230 | case 3: | |
b27faf8e | 1231 | ring = dev->dma.tx_ring_AC_BK; |
e6f5b934 MB |
1232 | break; |
1233 | } | |
1234 | } else | |
b27faf8e | 1235 | ring = dev->dma.tx_ring_AC_BE; |
e6f5b934 MB |
1236 | |
1237 | return ring; | |
1238 | } | |
1239 | ||
e4d6b795 MB |
1240 | int b43_dma_tx(struct b43_wldev *dev, |
1241 | struct sk_buff *skb, struct ieee80211_tx_control *ctl) | |
1242 | { | |
1243 | struct b43_dmaring *ring; | |
280d0e16 | 1244 | struct ieee80211_hdr *hdr; |
e4d6b795 MB |
1245 | int err = 0; |
1246 | unsigned long flags; | |
1247 | ||
280d0e16 MB |
1248 | if (unlikely(skb->len < 2 + 2 + 6)) { |
1249 | /* Too short, this can't be a valid frame. */ | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | ||
1253 | hdr = (struct ieee80211_hdr *)skb->data; | |
1254 | if (ctl->flags & IEEE80211_TXCTL_SEND_AFTER_DTIM) { | |
1255 | /* The multicast ring will be sent after the DTIM */ | |
b27faf8e | 1256 | ring = dev->dma.tx_ring_mcast; |
280d0e16 MB |
1257 | /* Set the more-data bit. Ucode will clear it on |
1258 | * the last frame for us. */ | |
1259 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); | |
1260 | } else { | |
1261 | /* Decide by priority where to put this frame. */ | |
e6f5b934 | 1262 | ring = select_ring_by_priority(dev, ctl->queue); |
280d0e16 MB |
1263 | } |
1264 | ||
e4d6b795 MB |
1265 | spin_lock_irqsave(&ring->lock, flags); |
1266 | B43_WARN_ON(!ring->tx); | |
1267 | if (unlikely(free_slots(ring) < SLOTS_PER_PACKET)) { | |
1268 | b43warn(dev->wl, "DMA queue overflow\n"); | |
1269 | err = -ENOSPC; | |
1270 | goto out_unlock; | |
1271 | } | |
1272 | /* Check if the queue was stopped in mac80211, | |
1273 | * but we got called nevertheless. | |
1274 | * That would be a mac80211 bug. */ | |
1275 | B43_WARN_ON(ring->stopped); | |
1276 | ||
e6f5b934 MB |
1277 | /* Assign the queue number to the ring (if not already done before) |
1278 | * so TX status handling can use it. The queue to ring mapping is | |
1279 | * static, so we don't need to store it per frame. */ | |
1280 | ring->queue_prio = ctl->queue; | |
1281 | ||
e4d6b795 | 1282 | err = dma_tx_fragment(ring, skb, ctl); |
09552ccd MB |
1283 | if (unlikely(err == -ENOKEY)) { |
1284 | /* Drop this packet, as we don't have the encryption key | |
1285 | * anymore and must not transmit it unencrypted. */ | |
1286 | dev_kfree_skb_any(skb); | |
1287 | err = 0; | |
1288 | goto out_unlock; | |
1289 | } | |
e4d6b795 MB |
1290 | if (unlikely(err)) { |
1291 | b43err(dev->wl, "DMA tx mapping failure\n"); | |
1292 | goto out_unlock; | |
1293 | } | |
1294 | ring->nr_tx_packets++; | |
1295 | if ((free_slots(ring) < SLOTS_PER_PACKET) || | |
1296 | should_inject_overflow(ring)) { | |
1297 | /* This TX ring is full. */ | |
e6f5b934 | 1298 | ieee80211_stop_queue(dev->wl->hw, ctl->queue); |
e4d6b795 MB |
1299 | ring->stopped = 1; |
1300 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1301 | b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); | |
1302 | } | |
1303 | } | |
280d0e16 | 1304 | out_unlock: |
e4d6b795 MB |
1305 | spin_unlock_irqrestore(&ring->lock, flags); |
1306 | ||
1307 | return err; | |
1308 | } | |
1309 | ||
57df40d2 MB |
1310 | static void b43_fill_txstatus_report(struct b43_dmaring *ring, |
1311 | struct ieee80211_tx_status *report, | |
1312 | const struct b43_txstatus *status) | |
1313 | { | |
1314 | bool frame_failed = 0; | |
1315 | ||
1316 | if (status->acked) { | |
1317 | /* The frame was ACKed. */ | |
1318 | report->flags |= IEEE80211_TX_STATUS_ACK; | |
1319 | } else { | |
1320 | /* The frame was not ACKed... */ | |
1321 | if (!(report->control.flags & IEEE80211_TXCTL_NO_ACK)) { | |
1322 | /* ...but we expected an ACK. */ | |
1323 | frame_failed = 1; | |
1324 | report->excessive_retries = 1; | |
1325 | } | |
1326 | } | |
1327 | if (status->frame_count == 0) { | |
1328 | /* The frame was not transmitted at all. */ | |
1329 | report->retry_count = 0; | |
1330 | } else { | |
1331 | report->retry_count = status->frame_count - 1; | |
1332 | #ifdef CONFIG_B43_DEBUG | |
1333 | if (frame_failed) | |
1334 | ring->nr_failed_tx_packets++; | |
1335 | else | |
1336 | ring->nr_succeed_tx_packets++; | |
1337 | ring->nr_total_packet_tries += status->frame_count; | |
1338 | #endif /* DEBUG */ | |
1339 | } | |
1340 | } | |
1341 | ||
e4d6b795 MB |
1342 | void b43_dma_handle_txstatus(struct b43_wldev *dev, |
1343 | const struct b43_txstatus *status) | |
1344 | { | |
1345 | const struct b43_dma_ops *ops; | |
1346 | struct b43_dmaring *ring; | |
1347 | struct b43_dmadesc_generic *desc; | |
1348 | struct b43_dmadesc_meta *meta; | |
1349 | int slot; | |
1350 | ||
1351 | ring = parse_cookie(dev, status->cookie, &slot); | |
1352 | if (unlikely(!ring)) | |
1353 | return; | |
1354 | B43_WARN_ON(!irqs_disabled()); | |
1355 | spin_lock(&ring->lock); | |
1356 | ||
1357 | B43_WARN_ON(!ring->tx); | |
1358 | ops = ring->ops; | |
1359 | while (1) { | |
1360 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); | |
1361 | desc = ops->idx2desc(ring, slot, &meta); | |
1362 | ||
1363 | if (meta->skb) | |
1364 | unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, | |
1365 | 1); | |
1366 | else | |
1367 | unmap_descbuffer(ring, meta->dmaaddr, | |
eb189d8b | 1368 | b43_txhdr_size(dev), 1); |
e4d6b795 MB |
1369 | |
1370 | if (meta->is_last_fragment) { | |
1371 | B43_WARN_ON(!meta->skb); | |
1372 | /* Call back to inform the ieee80211 subsystem about the | |
1373 | * status of the transmission. | |
1374 | * Some fields of txstat are already filled in dma_tx(). | |
1375 | */ | |
57df40d2 | 1376 | b43_fill_txstatus_report(ring, &(meta->txstat), status); |
e4d6b795 MB |
1377 | ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb, |
1378 | &(meta->txstat)); | |
1379 | /* skb is freed by ieee80211_tx_status_irqsafe() */ | |
1380 | meta->skb = NULL; | |
1381 | } else { | |
1382 | /* No need to call free_descriptor_buffer here, as | |
1383 | * this is only the txhdr, which is not allocated. | |
1384 | */ | |
1385 | B43_WARN_ON(meta->skb); | |
1386 | } | |
1387 | ||
1388 | /* Everything unmapped and free'd. So it's not used anymore. */ | |
1389 | ring->used_slots--; | |
1390 | ||
1391 | if (meta->is_last_fragment) | |
1392 | break; | |
1393 | slot = next_slot(ring, slot); | |
1394 | } | |
1395 | dev->stats.last_tx = jiffies; | |
1396 | if (ring->stopped) { | |
1397 | B43_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET); | |
e6f5b934 | 1398 | ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); |
e4d6b795 MB |
1399 | ring->stopped = 0; |
1400 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { | |
1401 | b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index); | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | spin_unlock(&ring->lock); | |
1406 | } | |
1407 | ||
1408 | void b43_dma_get_tx_stats(struct b43_wldev *dev, | |
1409 | struct ieee80211_tx_queue_stats *stats) | |
1410 | { | |
1411 | const int nr_queues = dev->wl->hw->queues; | |
1412 | struct b43_dmaring *ring; | |
1413 | struct ieee80211_tx_queue_stats_data *data; | |
1414 | unsigned long flags; | |
1415 | int i; | |
1416 | ||
1417 | for (i = 0; i < nr_queues; i++) { | |
1418 | data = &(stats->data[i]); | |
e6f5b934 | 1419 | ring = select_ring_by_priority(dev, i); |
e4d6b795 MB |
1420 | |
1421 | spin_lock_irqsave(&ring->lock, flags); | |
1422 | data->len = ring->used_slots / SLOTS_PER_PACKET; | |
1423 | data->limit = ring->nr_slots / SLOTS_PER_PACKET; | |
1424 | data->count = ring->nr_tx_packets; | |
1425 | spin_unlock_irqrestore(&ring->lock, flags); | |
1426 | } | |
1427 | } | |
1428 | ||
1429 | static void dma_rx(struct b43_dmaring *ring, int *slot) | |
1430 | { | |
1431 | const struct b43_dma_ops *ops = ring->ops; | |
1432 | struct b43_dmadesc_generic *desc; | |
1433 | struct b43_dmadesc_meta *meta; | |
1434 | struct b43_rxhdr_fw4 *rxhdr; | |
1435 | struct sk_buff *skb; | |
1436 | u16 len; | |
1437 | int err; | |
1438 | dma_addr_t dmaaddr; | |
1439 | ||
1440 | desc = ops->idx2desc(ring, *slot, &meta); | |
1441 | ||
1442 | sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); | |
1443 | skb = meta->skb; | |
1444 | ||
e4d6b795 MB |
1445 | rxhdr = (struct b43_rxhdr_fw4 *)skb->data; |
1446 | len = le16_to_cpu(rxhdr->frame_len); | |
1447 | if (len == 0) { | |
1448 | int i = 0; | |
1449 | ||
1450 | do { | |
1451 | udelay(2); | |
1452 | barrier(); | |
1453 | len = le16_to_cpu(rxhdr->frame_len); | |
1454 | } while (len == 0 && i++ < 5); | |
1455 | if (unlikely(len == 0)) { | |
1456 | /* recycle the descriptor buffer. */ | |
1457 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1458 | ring->rx_buffersize); | |
1459 | goto drop; | |
1460 | } | |
1461 | } | |
1462 | if (unlikely(len > ring->rx_buffersize)) { | |
1463 | /* The data did not fit into one descriptor buffer | |
1464 | * and is split over multiple buffers. | |
1465 | * This should never happen, as we try to allocate buffers | |
1466 | * big enough. So simply ignore this packet. | |
1467 | */ | |
1468 | int cnt = 0; | |
1469 | s32 tmp = len; | |
1470 | ||
1471 | while (1) { | |
1472 | desc = ops->idx2desc(ring, *slot, &meta); | |
1473 | /* recycle the descriptor buffer. */ | |
1474 | sync_descbuffer_for_device(ring, meta->dmaaddr, | |
1475 | ring->rx_buffersize); | |
1476 | *slot = next_slot(ring, *slot); | |
1477 | cnt++; | |
1478 | tmp -= ring->rx_buffersize; | |
1479 | if (tmp <= 0) | |
1480 | break; | |
1481 | } | |
1482 | b43err(ring->dev->wl, "DMA RX buffer too small " | |
1483 | "(len: %u, buffer: %u, nr-dropped: %d)\n", | |
1484 | len, ring->rx_buffersize, cnt); | |
1485 | goto drop; | |
1486 | } | |
1487 | ||
1488 | dmaaddr = meta->dmaaddr; | |
1489 | err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); | |
1490 | if (unlikely(err)) { | |
1491 | b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n"); | |
1492 | sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize); | |
1493 | goto drop; | |
1494 | } | |
1495 | ||
1496 | unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); | |
1497 | skb_put(skb, len + ring->frameoffset); | |
1498 | skb_pull(skb, ring->frameoffset); | |
1499 | ||
1500 | b43_rx(ring->dev, skb, rxhdr); | |
b27faf8e | 1501 | drop: |
e4d6b795 MB |
1502 | return; |
1503 | } | |
1504 | ||
1505 | void b43_dma_rx(struct b43_dmaring *ring) | |
1506 | { | |
1507 | const struct b43_dma_ops *ops = ring->ops; | |
1508 | int slot, current_slot; | |
1509 | int used_slots = 0; | |
1510 | ||
1511 | B43_WARN_ON(ring->tx); | |
1512 | current_slot = ops->get_current_rxslot(ring); | |
1513 | B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots)); | |
1514 | ||
1515 | slot = ring->current_slot; | |
1516 | for (; slot != current_slot; slot = next_slot(ring, slot)) { | |
1517 | dma_rx(ring, &slot); | |
1518 | update_max_used_slots(ring, ++used_slots); | |
1519 | } | |
1520 | ops->set_current_rxslot(ring, slot); | |
1521 | ring->current_slot = slot; | |
1522 | } | |
1523 | ||
1524 | static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring) | |
1525 | { | |
1526 | unsigned long flags; | |
1527 | ||
1528 | spin_lock_irqsave(&ring->lock, flags); | |
1529 | B43_WARN_ON(!ring->tx); | |
1530 | ring->ops->tx_suspend(ring); | |
1531 | spin_unlock_irqrestore(&ring->lock, flags); | |
1532 | } | |
1533 | ||
1534 | static void b43_dma_tx_resume_ring(struct b43_dmaring *ring) | |
1535 | { | |
1536 | unsigned long flags; | |
1537 | ||
1538 | spin_lock_irqsave(&ring->lock, flags); | |
1539 | B43_WARN_ON(!ring->tx); | |
1540 | ring->ops->tx_resume(ring); | |
1541 | spin_unlock_irqrestore(&ring->lock, flags); | |
1542 | } | |
1543 | ||
1544 | void b43_dma_tx_suspend(struct b43_wldev *dev) | |
1545 | { | |
1546 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); | |
b27faf8e MB |
1547 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK); |
1548 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE); | |
1549 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI); | |
1550 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO); | |
1551 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast); | |
e4d6b795 MB |
1552 | } |
1553 | ||
1554 | void b43_dma_tx_resume(struct b43_wldev *dev) | |
1555 | { | |
b27faf8e MB |
1556 | b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast); |
1557 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO); | |
1558 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI); | |
1559 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE); | |
1560 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK); | |
e4d6b795 MB |
1561 | b43_power_saving_ctl_bits(dev, 0); |
1562 | } |