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ath9k: Miscellaneous fixes
[linux-block.git] / drivers / net / wireless / ath9k / xmit.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/*
18 * Implementation of transmit path.
19 */
20
21#include "core.h"
22
23#define BITS_PER_BYTE 8
24#define OFDM_PLCP_BITS 22
25#define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
26#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
27#define L_STF 8
28#define L_LTF 8
29#define L_SIG 4
30#define HT_SIG 8
31#define HT_STF 4
32#define HT_LTF(_ns) (4 * (_ns))
33#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
34#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
35#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
36#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
37
38#define OFDM_SIFS_TIME 16
39
40static u32 bits_per_symbol[][2] = {
41 /* 20MHz 40MHz */
42 { 26, 54 }, /* 0: BPSK */
43 { 52, 108 }, /* 1: QPSK 1/2 */
44 { 78, 162 }, /* 2: QPSK 3/4 */
45 { 104, 216 }, /* 3: 16-QAM 1/2 */
46 { 156, 324 }, /* 4: 16-QAM 3/4 */
47 { 208, 432 }, /* 5: 64-QAM 2/3 */
48 { 234, 486 }, /* 6: 64-QAM 3/4 */
49 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 { 52, 108 }, /* 8: BPSK */
51 { 104, 216 }, /* 9: QPSK 1/2 */
52 { 156, 324 }, /* 10: QPSK 3/4 */
53 { 208, 432 }, /* 11: 16-QAM 1/2 */
54 { 312, 648 }, /* 12: 16-QAM 3/4 */
55 { 416, 864 }, /* 13: 64-QAM 2/3 */
56 { 468, 972 }, /* 14: 64-QAM 3/4 */
57 { 520, 1080 }, /* 15: 64-QAM 5/6 */
58};
59
60#define IS_HT_RATE(_rate) ((_rate) & 0x80)
61
62/*
63 * Insert a chain of ath_buf (descriptors) on a multicast txq
64 * but do NOT start tx DMA on this queue.
65 * NB: must be called with txq lock held
66 */
67
68static void ath_tx_mcastqaddbuf(struct ath_softc *sc,
69 struct ath_txq *txq,
70 struct list_head *head)
71{
72 struct ath_hal *ah = sc->sc_ah;
73 struct ath_buf *bf;
74
75 if (list_empty(head))
76 return;
77
78 /*
79 * Insert the frame on the outbound list and
80 * pass it on to the hardware.
81 */
82 bf = list_first_entry(head, struct ath_buf, list);
83
84 /*
85 * The CAB queue is started from the SWBA handler since
86 * frames only go out on DTIM and to avoid possible races.
87 */
88 ath9k_hw_set_interrupts(ah, 0);
89
90 /*
91 * If there is anything in the mcastq, we want to set
92 * the "more data" bit in the last item in the queue to
93 * indicate that there is "more data". It makes sense to add
94 * it here since you are *always* going to have
95 * more data when adding to this queue, no matter where
96 * you call from.
97 */
98
99 if (txq->axq_depth) {
100 struct ath_buf *lbf;
101 struct ieee80211_hdr *hdr;
102
103 /*
104 * Add the "more data flag" to the last frame
105 */
106
107 lbf = list_entry(txq->axq_q.prev, struct ath_buf, list);
108 hdr = (struct ieee80211_hdr *)
109 ((struct sk_buff *)(lbf->bf_mpdu))->data;
110 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA);
111 }
112
113 /*
114 * Now, concat the frame onto the queue
115 */
116 list_splice_tail_init(head, &txq->axq_q);
117 txq->axq_depth++;
118 txq->axq_totalqueued++;
119 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
120
121 DPRINTF(sc, ATH_DBG_QUEUE,
122 "%s: txq depth = %d\n", __func__, txq->axq_depth);
123 if (txq->axq_link != NULL) {
124 *txq->axq_link = bf->bf_daddr;
125 DPRINTF(sc, ATH_DBG_XMIT,
126 "%s: link[%u](%p)=%llx (%p)\n",
127 __func__,
128 txq->axq_qnum, txq->axq_link,
129 ito64(bf->bf_daddr), bf->bf_desc);
130 }
131 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
132 ath9k_hw_set_interrupts(ah, sc->sc_imask);
133}
134
135/*
136 * Insert a chain of ath_buf (descriptors) on a txq and
137 * assume the descriptors are already chained together by caller.
138 * NB: must be called with txq lock held
139 */
140
141static void ath_tx_txqaddbuf(struct ath_softc *sc,
142 struct ath_txq *txq, struct list_head *head)
143{
144 struct ath_hal *ah = sc->sc_ah;
145 struct ath_buf *bf;
146 /*
147 * Insert the frame on the outbound list and
148 * pass it on to the hardware.
149 */
150
151 if (list_empty(head))
152 return;
153
154 bf = list_first_entry(head, struct ath_buf, list);
155
156 list_splice_tail_init(head, &txq->axq_q);
157 txq->axq_depth++;
158 txq->axq_totalqueued++;
159 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
160
161 DPRINTF(sc, ATH_DBG_QUEUE,
162 "%s: txq depth = %d\n", __func__, txq->axq_depth);
163
164 if (txq->axq_link == NULL) {
165 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
166 DPRINTF(sc, ATH_DBG_XMIT,
167 "%s: TXDP[%u] = %llx (%p)\n",
168 __func__, txq->axq_qnum,
169 ito64(bf->bf_daddr), bf->bf_desc);
170 } else {
171 *txq->axq_link = bf->bf_daddr;
172 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
173 __func__,
174 txq->axq_qnum, txq->axq_link,
175 ito64(bf->bf_daddr), bf->bf_desc);
176 }
177 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
178 ath9k_hw_txstart(ah, txq->axq_qnum);
179}
180
181/* Get transmit rate index using rate in Kbps */
182
183static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate)
184{
185 int i;
186 int ndx = 0;
187
188 for (i = 0; i < rt->rateCount; i++) {
189 if (rt->info[i].rateKbps == rate) {
190 ndx = i;
191 break;
192 }
193 }
194
195 return ndx;
196}
197
198/* Check if it's okay to send out aggregates */
199
200static int ath_aggr_query(struct ath_softc *sc,
201 struct ath_node *an, u8 tidno)
202{
203 struct ath_atx_tid *tid;
204 tid = ATH_AN_2_TID(an, tidno);
205
206 if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress)
207 return 1;
208 else
209 return 0;
210}
211
212static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr)
213{
214 enum ath9k_pkt_type htype;
215 __le16 fc;
216
217 fc = hdr->frame_control;
218
219 /* Calculate Atheros packet type from IEEE80211 packet header */
220
221 if (ieee80211_is_beacon(fc))
222 htype = ATH9K_PKT_TYPE_BEACON;
223 else if (ieee80211_is_probe_resp(fc))
224 htype = ATH9K_PKT_TYPE_PROBE_RESP;
225 else if (ieee80211_is_atim(fc))
226 htype = ATH9K_PKT_TYPE_ATIM;
227 else if (ieee80211_is_pspoll(fc))
228 htype = ATH9K_PKT_TYPE_PSPOLL;
229 else
230 htype = ATH9K_PKT_TYPE_NORMAL;
231
232 return htype;
233}
234
235static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl)
236{
237 struct ieee80211_hdr *hdr;
238 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
239 struct ath_tx_info_priv *tx_info_priv;
240 __le16 fc;
241
242 hdr = (struct ieee80211_hdr *)skb->data;
243 fc = hdr->frame_control;
244 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
245
246 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) {
247 txctl->use_minrate = 1;
248 txctl->min_rate = tx_info_priv->min_rate;
249 } else if (ieee80211_is_data(fc)) {
250 if (ieee80211_is_nullfunc(fc) ||
251 /* Port Access Entity (IEEE 802.1X) */
252 (skb->protocol == cpu_to_be16(0x888E))) {
253 txctl->use_minrate = 1;
254 txctl->min_rate = tx_info_priv->min_rate;
255 }
256 if (is_multicast_ether_addr(hdr->addr1))
257 txctl->mcast_rate = tx_info_priv->min_rate;
258 }
259
260}
261
262/* This function will setup additional txctl information, mostly rate stuff */
263/* FIXME: seqno, ps */
264static int ath_tx_prepare(struct ath_softc *sc,
265 struct sk_buff *skb,
266 struct ath_tx_control *txctl)
267{
268 struct ieee80211_hw *hw = sc->hw;
269 struct ieee80211_hdr *hdr;
270 struct ath_rc_series *rcs;
271 struct ath_txq *txq = NULL;
272 const struct ath9k_rate_table *rt;
273 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
274 struct ath_tx_info_priv *tx_info_priv;
275 int hdrlen;
276 u8 rix, antenna;
277 __le16 fc;
278 u8 *qc;
279
280 memset(txctl, 0, sizeof(struct ath_tx_control));
281
282 txctl->dev = sc;
283 hdr = (struct ieee80211_hdr *)skb->data;
284 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
285 fc = hdr->frame_control;
286
287 rt = sc->sc_currates;
288 BUG_ON(!rt);
289
290 /* Fill misc fields */
291
292 spin_lock_bh(&sc->node_lock);
293 txctl->an = ath_node_get(sc, hdr->addr1);
294 /* create a temp node, if the node is not there already */
295 if (!txctl->an)
296 txctl->an = ath_node_attach(sc, hdr->addr1, 0);
297 spin_unlock_bh(&sc->node_lock);
298
299 if (ieee80211_is_data_qos(fc)) {
300 qc = ieee80211_get_qos_ctl(hdr);
301 txctl->tidno = qc[0] & 0xf;
302 }
303
304 txctl->if_id = 0;
305 txctl->nextfraglen = 0;
306 txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3);
307 txctl->txpower = MAX_RATE_POWER; /* FIXME */
308
309 /* Fill Key related fields */
310
311 txctl->keytype = ATH9K_KEY_TYPE_CLEAR;
312 txctl->keyix = ATH9K_TXKEYIX_INVALID;
313
314 if (tx_info->control.hw_key) {
315 txctl->keyix = tx_info->control.hw_key->hw_key_idx;
316 txctl->frmlen += tx_info->control.icv_len;
317
318 if (sc->sc_keytype == ATH9K_CIPHER_WEP)
319 txctl->keytype = ATH9K_KEY_TYPE_WEP;
320 else if (sc->sc_keytype == ATH9K_CIPHER_TKIP)
321 txctl->keytype = ATH9K_KEY_TYPE_TKIP;
322 else if (sc->sc_keytype == ATH9K_CIPHER_AES_CCM)
323 txctl->keytype = ATH9K_KEY_TYPE_AES;
324 }
325
326 /* Fill packet type */
327
328 txctl->atype = get_hal_packet_type(hdr);
329
330 /* Fill qnum */
331
332 txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
333 txq = &sc->sc_txq[txctl->qnum];
334 spin_lock_bh(&txq->axq_lock);
335
336 /* Try to avoid running out of descriptors */
337 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
338 DPRINTF(sc, ATH_DBG_FATAL,
339 "%s: TX queue: %d is full, depth: %d\n",
340 __func__,
341 txctl->qnum,
342 txq->axq_depth);
343 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
344 txq->stopped = 1;
345 spin_unlock_bh(&txq->axq_lock);
346 return -1;
347 }
348
349 spin_unlock_bh(&txq->axq_lock);
350
351 /* Fill rate */
352
353 fill_min_rates(skb, txctl);
354
355 /* Fill flags */
356
357 txctl->flags = ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
358
359 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
b14ecdd0 360 txctl->flags |= ATH9K_TXDESC_NOACK;
f078f209 361 if (tx_info->flags & IEEE80211_TX_CTL_USE_RTS_CTS)
b14ecdd0 362 txctl->flags |= ATH9K_TXDESC_RTSENA;
f078f209
LR		 363
364 /*
365 * Setup for rate calculations.
366 */
367 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
368 rcs = tx_info_priv->rcs;
369
370 if (ieee80211_is_data(fc) && !txctl->use_minrate) {
371
372 /* Enable HT only for DATA frames and not for EAPOL */
373 txctl->ht = (hw->conf.ht_conf.ht_supported &&
374 (tx_info->flags & IEEE80211_TX_CTL_AMPDU));
375
376 if (is_multicast_ether_addr(hdr->addr1)) {
377 rcs[0].rix = (u8)
378 ath_tx_findindex(rt, txctl->mcast_rate);
379
380 /*
381 * mcast packets are not re-tried.
382 */
383 rcs[0].tries = 1;
384 }
385 /* For HT capable stations, we save tidno for later use.
386 * We also override seqno set by upper layer with the one
387 * in tx aggregation state.
388 *
389 * First, the fragmentation stat is determined.
390 * If fragmentation is on, the sequence number is
391 * not overridden, since it has been
392 * incremented by the fragmentation routine.
393 */
394 if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) &&
672840ac 395 txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 396 struct ath_atx_tid *tid;
397
398 tid = ATH_AN_2_TID(txctl->an, txctl->tidno);
399
400 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
401 IEEE80211_SEQ_SEQ_SHIFT);
402 txctl->seqno = tid->seq_next;
403 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
404 }
405 } else {
406 /* for management and control frames,
407 * or for NULL and EAPOL frames */
408 if (txctl->min_rate)
409 rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate);
410 else
86b89eed 411 rcs[0].rix = 0;
f078f209
LR		 412 rcs[0].tries = ATH_MGT_TXMAXTRY;
413 }
414 rix = rcs[0].rix;
415
416 /*
417 * Calculate duration. This logically belongs in the 802.11
418 * layer but it lacks sufficient information to calculate it.
419 */
420 if ((txctl->flags & ATH9K_TXDESC_NOACK) == 0 && !ieee80211_is_ctl(fc)) {
421 u16 dur;
422 /*
423 * XXX not right with fragmentation.
424 */
672840ac 425 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
f078f209
LR		 426 dur = rt->info[rix].spAckDuration;
427 else
428 dur = rt->info[rix].lpAckDuration;
429
430 if (le16_to_cpu(hdr->frame_control) &
431 IEEE80211_FCTL_MOREFRAGS) {
432 dur += dur; /* Add additional 'SIFS + ACK' */
433
434 /*
435 ** Compute size of next fragment in order to compute
436 ** durations needed to update NAV.
437 ** The last fragment uses the ACK duration only.
438 ** Add time for next fragment.
439 */
440 dur += ath9k_hw_computetxtime(sc->sc_ah, rt,
672840ac
S		 441 txctl->nextfraglen,
442 rix,
443 (sc->sc_flags & SC_OP_PREAMBLE_SHORT));
f078f209
LR		 444 }
445
446 if (ieee80211_has_morefrags(fc) ||
447 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
448 /*
449 ** Force hardware to use computed duration for next
450 ** fragment by disabling multi-rate retry, which
451 ** updates duration based on the multi-rate
452 ** duration table.
453 */
454 rcs[1].tries = rcs[2].tries = rcs[3].tries = 0;
455 rcs[1].rix = rcs[2].rix = rcs[3].rix = 0;
456 /* reset tries but keep rate index */
457 rcs[0].tries = ATH_TXMAXTRY;
458 }
459
460 hdr->duration_id = cpu_to_le16(dur);
461 }
462
463 /*
464 * Determine if a tx interrupt should be generated for
465 * this descriptor. We take a tx interrupt to reap
466 * descriptors when the h/w hits an EOL condition or
467 * when the descriptor is specifically marked to generate
468 * an interrupt. We periodically mark descriptors in this
469 * way to insure timely replenishing of the supply needed
470 * for sending frames. Defering interrupts reduces system
471 * load and potentially allows more concurrent work to be
472 * done but if done to aggressively can cause senders to
473 * backup.
474 *
475 * NB: use >= to deal with sc_txintrperiod changing
476 * dynamically through sysctl.
477 */
478 spin_lock_bh(&txq->axq_lock);
479 if ((++txq->axq_intrcnt >= sc->sc_txintrperiod)) {
480 txctl->flags |= ATH9K_TXDESC_INTREQ;
481 txq->axq_intrcnt = 0;
482 }
483 spin_unlock_bh(&txq->axq_lock);
484
485 if (is_multicast_ether_addr(hdr->addr1)) {
486 antenna = sc->sc_mcastantenna + 1;
487 sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1;
98deeea0 488 }
f078f209 489
f078f209
LR		 490 return 0;
491}
492
493/* To complete a chain of buffers associated a frame */
494
495static void ath_tx_complete_buf(struct ath_softc *sc,
496 struct ath_buf *bf,
497 struct list_head *bf_q,
498 int txok, int sendbar)
499{
500 struct sk_buff *skb = bf->bf_mpdu;
501 struct ath_xmit_status tx_status;
f078f209
LR		 502
503 /*
504 * Set retry information.
505 * NB: Don't use the information in the descriptor, because the frame
506 * could be software retried.
507 */
508 tx_status.retries = bf->bf_retries;
509 tx_status.flags = 0;
510
511 if (sendbar)
512 tx_status.flags = ATH_TX_BAR;
513
514 if (!txok) {
515 tx_status.flags |= ATH_TX_ERROR;
516
cd3d39a6 517 if (bf_isxretried(bf))
f078f209
LR		 518 tx_status.flags |= ATH_TX_XRETRY;
519 }
520 /* Unmap this frame */
f078f209 521 pci_unmap_single(sc->pdev,
ff9b662d 522 bf->bf_dmacontext,
f078f209
LR		 523 skb->len,
524 PCI_DMA_TODEVICE);
525 /* complete this frame */
526 ath_tx_complete(sc, skb, &tx_status, bf->bf_node);
527
528 /*
529 * Return the list of ath_buf of this mpdu to free queue
530 */
531 spin_lock_bh(&sc->sc_txbuflock);
532 list_splice_tail_init(bf_q, &sc->sc_txbuf);
533 spin_unlock_bh(&sc->sc_txbuflock);
534}
535
536/*
537 * queue up a dest/ac pair for tx scheduling
538 * NB: must be called with txq lock held
539 */
540
541static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
542{
543 struct ath_atx_ac *ac = tid->ac;
544
545 /*
546 * if tid is paused, hold off
547 */
548 if (tid->paused)
549 return;
550
551 /*
552 * add tid to ac atmost once
553 */
554 if (tid->sched)
555 return;
556
557 tid->sched = true;
558 list_add_tail(&tid->list, &ac->tid_q);
559
560 /*
561 * add node ac to txq atmost once
562 */
563 if (ac->sched)
564 return;
565
566 ac->sched = true;
567 list_add_tail(&ac->list, &txq->axq_acq);
568}
569
570/* pause a tid */
571
572static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
573{
574 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
575
576 spin_lock_bh(&txq->axq_lock);
577
578 tid->paused++;
579
580 spin_unlock_bh(&txq->axq_lock);
581}
582
583/* resume a tid and schedule aggregate */
584
585void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
586{
587 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
588
589 ASSERT(tid->paused > 0);
590 spin_lock_bh(&txq->axq_lock);
591
592 tid->paused--;
593
594 if (tid->paused > 0)
595 goto unlock;
596
597 if (list_empty(&tid->buf_q))
598 goto unlock;
599
600 /*
601 * Add this TID to scheduler and try to send out aggregates
602 */
603 ath_tx_queue_tid(txq, tid);
604 ath_txq_schedule(sc, txq);
605unlock:
606 spin_unlock_bh(&txq->axq_lock);
607}
608
609/* Compute the number of bad frames */
610
611static int ath_tx_num_badfrms(struct ath_softc *sc,
612 struct ath_buf *bf, int txok)
613{
614 struct ath_node *an = bf->bf_node;
615 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
616 struct ath_buf *bf_last = bf->bf_lastbf;
617 struct ath_desc *ds = bf_last->bf_desc;
618 u16 seq_st = 0;
619 u32 ba[WME_BA_BMP_SIZE >> 5];
620 int ba_index;
621 int nbad = 0;
622 int isaggr = 0;
623
624 if (isnodegone || ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
625 return 0;
626
cd3d39a6 627 isaggr = bf_isaggr(bf);
f078f209
LR		 628 if (isaggr) {
629 seq_st = ATH_DS_BA_SEQ(ds);
630 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
631 }
632
633 while (bf) {
634 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
635 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
636 nbad++;
637
638 bf = bf->bf_next;
639 }
640
641 return nbad;
642}
643
644static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
645{
646 struct sk_buff *skb;
647 struct ieee80211_hdr *hdr;
648
cd3d39a6 649 bf->bf_state.bf_type |= BUF_RETRY;
f078f209
LR		 650 bf->bf_retries++;
651
652 skb = bf->bf_mpdu;
653 hdr = (struct ieee80211_hdr *)skb->data;
654 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
655}
656
657/* Update block ack window */
658
659static void ath_tx_update_baw(struct ath_softc *sc,
660 struct ath_atx_tid *tid, int seqno)
661{
662 int index, cindex;
663
664 index = ATH_BA_INDEX(tid->seq_start, seqno);
665 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
666
667 tid->tx_buf[cindex] = NULL;
668
669 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
670 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
671 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
672 }
673}
674
675/*
676 * ath_pkt_dur - compute packet duration (NB: not NAV)
677 *
678 * rix - rate index
679 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
680 * width - 0 for 20 MHz, 1 for 40 MHz
681 * half_gi - to use 4us v/s 3.6 us for symbol time
682 */
683
684static u32 ath_pkt_duration(struct ath_softc *sc,
685 u8 rix,
686 struct ath_buf *bf,
687 int width,
688 int half_gi,
689 bool shortPreamble)
690{
691 const struct ath9k_rate_table *rt = sc->sc_currates;
692 u32 nbits, nsymbits, duration, nsymbols;
693 u8 rc;
694 int streams, pktlen;
695
cd3d39a6 696 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
f078f209
LR		 697 rc = rt->info[rix].rateCode;
698
699 /*
700 * for legacy rates, use old function to compute packet duration
701 */
702 if (!IS_HT_RATE(rc))
703 return ath9k_hw_computetxtime(sc->sc_ah,
704 rt,
705 pktlen,
706 rix,
707 shortPreamble);
708 /*
709 * find number of symbols: PLCP + data
710 */
711 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
712 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
713 nsymbols = (nbits + nsymbits - 1) / nsymbits;
714
715 if (!half_gi)
716 duration = SYMBOL_TIME(nsymbols);
717 else
718 duration = SYMBOL_TIME_HALFGI(nsymbols);
719
720 /*
721 * addup duration for legacy/ht training and signal fields
722 */
723 streams = HT_RC_2_STREAMS(rc);
724 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
725 return duration;
726}
727
728/* Rate module function to set rate related fields in tx descriptor */
729
730static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
731{
732 struct ath_hal *ah = sc->sc_ah;
733 const struct ath9k_rate_table *rt;
734 struct ath_desc *ds = bf->bf_desc;
735 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
736 struct ath9k_11n_rate_series series[4];
737 int i, flags, rtsctsena = 0, dynamic_mimops = 0;
738 u32 ctsduration = 0;
739 u8 rix = 0, cix, ctsrate = 0;
98deeea0 740 u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit;
f078f209
LR		 741 struct ath_node *an = (struct ath_node *) bf->bf_node;
742
743 /*
744 * get the cix for the lowest valid rix.
745 */
746 rt = sc->sc_currates;
747 for (i = 4; i--;) {
748 if (bf->bf_rcs[i].tries) {
749 rix = bf->bf_rcs[i].rix;
750 break;
751 }
752 }
753 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
754 cix = rt->info[rix].controlRate;
755
756 /*
757 * If 802.11g protection is enabled, determine whether
758 * to use RTS/CTS or just CTS. Note that this is only
759 * done for OFDM/HT unicast frames.
760 */
761 if (sc->sc_protmode != PROT_M_NONE &&
762 (rt->info[rix].phy == PHY_OFDM ||
763 rt->info[rix].phy == PHY_HT) &&
764 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
765 if (sc->sc_protmode == PROT_M_RTSCTS)
766 flags = ATH9K_TXDESC_RTSENA;
767 else if (sc->sc_protmode == PROT_M_CTSONLY)
768 flags = ATH9K_TXDESC_CTSENA;
769
770 cix = rt->info[sc->sc_protrix].controlRate;
771 rtsctsena = 1;
772 }
773
774 /* For 11n, the default behavior is to enable RTS for
775 * hw retried frames. We enable the global flag here and
776 * let rate series flags determine which rates will actually
777 * use RTS.
778 */
cd3d39a6 779 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
f078f209
LR		 780 BUG_ON(!an);
781 /*
782 * 802.11g protection not needed, use our default behavior
783 */
784 if (!rtsctsena)
785 flags = ATH9K_TXDESC_RTSENA;
786 /*
787 * For dynamic MIMO PS, RTS needs to precede the first aggregate
788 * and the second aggregate should have any protection at all.
789 */
790 if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) {
cd3d39a6 791 if (!bf_isaggrburst(bf)) {
f078f209
LR		 792 flags = ATH9K_TXDESC_RTSENA;
793 dynamic_mimops = 1;
794 } else {
795 flags = 0;
796 }
797 }
798 }
799
800 /*
801 * Set protection if aggregate protection on
802 */
803 if (sc->sc_config.ath_aggr_prot &&
cd3d39a6 804 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
f078f209
LR		 805 flags = ATH9K_TXDESC_RTSENA;
806 cix = rt->info[sc->sc_protrix].controlRate;
807 rtsctsena = 1;
808 }
809
810 /*
811 * For AR5416 - RTS cannot be followed by a frame larger than 8K.
812 */
cd3d39a6 813 if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) {
f078f209
LR		 814 /*
815 * Ensure that in the case of SM Dynamic power save
816 * while we are bursting the second aggregate the
817 * RTS is cleared.
818 */
819 flags &= ~(ATH9K_TXDESC_RTSENA);
820 }
821
822 /*
823 * CTS transmit rate is derived from the transmit rate
824 * by looking in the h/w rate table. We must also factor
825 * in whether or not a short preamble is to be used.
826 */
827 /* NB: cix is set above where RTS/CTS is enabled */
828 BUG_ON(cix == 0xff);
829 ctsrate = rt->info[cix].rateCode |
cd3d39a6 830 (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0);
f078f209
LR		 831
832 /*
833 * Setup HAL rate series
834 */
835 memzero(series, sizeof(struct ath9k_11n_rate_series) * 4);
836
837 for (i = 0; i < 4; i++) {
838 if (!bf->bf_rcs[i].tries)
839 continue;
840
841 rix = bf->bf_rcs[i].rix;
842
843 series[i].Rate = rt->info[rix].rateCode |
cd3d39a6 844 (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0);
f078f209
LR		 845
846 series[i].Tries = bf->bf_rcs[i].tries;
847
848 series[i].RateFlags = (
849 (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
850 ATH9K_RATESERIES_RTS_CTS : 0) |
851 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
852 ATH9K_RATESERIES_2040 : 0) |
853 ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ?
854 ATH9K_RATESERIES_HALFGI : 0);
855
856 series[i].PktDuration = ath_pkt_duration(
857 sc, rix, bf,
858 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
859 (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG),
cd3d39a6 860 bf_isshpreamble(bf));
f078f209
LR		 861
862 if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) &&
863 (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) {
864 /*
865 * When sending to an HT node that has enabled static
866 * SM/MIMO power save, send at single stream rates but
867 * use maximum allowed transmit chains per user,
868 * hardware, regulatory, or country limits for
869 * better range.
870 */
871 series[i].ChSel = sc->sc_tx_chainmask;
872 } else {
cd3d39a6 873 if (bf_isht(bf))
f078f209
LR		 874 series[i].ChSel =
875 ath_chainmask_sel_logic(sc, an);
876 else
877 series[i].ChSel = sc->sc_tx_chainmask;
878 }
879
880 if (rtsctsena)
881 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
882
883 /*
884 * Set RTS for all rates if node is in dynamic powersave
885 * mode and we are using dual stream rates.
886 */
887 if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG))
888 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
889 }
890
891 /*
892 * For non-HT devices, calculate RTS/CTS duration in software
893 * and disable multi-rate retry.
894 */
60b67f51 895 if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) {
f078f209
LR		 896 /*
897 * Compute the transmit duration based on the frame
898 * size and the size of an ACK frame. We call into the
899 * HAL to do the computation since it depends on the
900 * characteristics of the actual PHY being used.
901 *
902 * NB: CTS is assumed the same size as an ACK so we can
903 * use the precalculated ACK durations.
904 */
905 if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */
cd3d39a6 906 ctsduration += bf_isshpreamble(bf) ?
f078f209
LR		 907 rt->info[cix].spAckDuration :
908 rt->info[cix].lpAckDuration;
909 }
910
911 ctsduration += series[0].PktDuration;
912
913 if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */
cd3d39a6 914 ctsduration += bf_isshpreamble(bf) ?
f078f209
LR		 915 rt->info[rix].spAckDuration :
916 rt->info[rix].lpAckDuration;
917 }
918
919 /*
920 * Disable multi-rate retry when using RTS/CTS by clearing
921 * series 1, 2 and 3.
922 */
923 memzero(&series[1], sizeof(struct ath9k_11n_rate_series) * 3);
924 }
925
926 /*
927 * set dur_update_en for l-sig computation except for PS-Poll frames
928 */
929 ath9k_hw_set11n_ratescenario(ah, ds, lastds,
cd3d39a6
S		 930 !bf_ispspoll(bf),
931 ctsrate,
932 ctsduration,
933 series, 4, flags);
f078f209
LR		 934 if (sc->sc_config.ath_aggr_prot && flags)
935 ath9k_hw_set11n_burstduration(ah, ds, 8192);
936}
937
938/*
939 * Function to send a normal HT (non-AMPDU) frame
940 * NB: must be called with txq lock held
941 */
942
943static int ath_tx_send_normal(struct ath_softc *sc,
944 struct ath_txq *txq,
945 struct ath_atx_tid *tid,
946 struct list_head *bf_head)
947{
948 struct ath_buf *bf;
949 struct sk_buff *skb;
950 struct ieee80211_tx_info *tx_info;
951 struct ath_tx_info_priv *tx_info_priv;
952
953 BUG_ON(list_empty(bf_head));
954
955 bf = list_first_entry(bf_head, struct ath_buf, list);
cd3d39a6 956 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
f078f209
LR		 957
958 skb = (struct sk_buff *)bf->bf_mpdu;
959 tx_info = IEEE80211_SKB_CB(skb);
960 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
961 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
962
963 /* update starting sequence number for subsequent ADDBA request */
964 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
965
966 /* Queue to h/w without aggregation */
967 bf->bf_nframes = 1;
968 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
969 ath_buf_set_rate(sc, bf);
970 ath_tx_txqaddbuf(sc, txq, bf_head);
971
972 return 0;
973}
974
975/* flush tid's software queue and send frames as non-ampdu's */
976
977static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
978{
979 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
980 struct ath_buf *bf;
981 struct list_head bf_head;
982 INIT_LIST_HEAD(&bf_head);
983
984 ASSERT(tid->paused > 0);
985 spin_lock_bh(&txq->axq_lock);
986
987 tid->paused--;
988
989 if (tid->paused > 0) {
990 spin_unlock_bh(&txq->axq_lock);
991 return;
992 }
993
994 while (!list_empty(&tid->buf_q)) {
995 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
cd3d39a6 996 ASSERT(!bf_isretried(bf));
f078f209
LR		 997 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
998 ath_tx_send_normal(sc, txq, tid, &bf_head);
999 }
1000
1001 spin_unlock_bh(&txq->axq_lock);
1002}
1003
1004/* Completion routine of an aggregate */
1005
1006static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
1007 struct ath_txq *txq,
1008 struct ath_buf *bf,
1009 struct list_head *bf_q,
1010 int txok)
1011{
1012 struct ath_node *an = bf->bf_node;
1013 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1014 struct ath_buf *bf_last = bf->bf_lastbf;
1015 struct ath_desc *ds = bf_last->bf_desc;
1016 struct ath_buf *bf_next, *bf_lastq = NULL;
1017 struct list_head bf_head, bf_pending;
1018 u16 seq_st = 0;
1019 u32 ba[WME_BA_BMP_SIZE >> 5];
1020 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
1021 int isnodegone = (an->an_flags & ATH_NODE_CLEAN);
1022
cd3d39a6 1023 isaggr = bf_isaggr(bf);
f078f209
LR		 1024 if (isaggr) {
1025 if (txok) {
1026 if (ATH_DS_TX_BA(ds)) {
1027 /*
1028 * extract starting sequence and
1029 * block-ack bitmap
1030 */
1031 seq_st = ATH_DS_BA_SEQ(ds);
1032 memcpy(ba,
1033 ATH_DS_BA_BITMAP(ds),
1034 WME_BA_BMP_SIZE >> 3);
1035 } else {
1036 memzero(ba, WME_BA_BMP_SIZE >> 3);
1037
1038 /*
1039 * AR5416 can become deaf/mute when BA
1040 * issue happens. Chip needs to be reset.
1041 * But AP code may have sychronization issues
1042 * when perform internal reset in this routine.
1043 * Only enable reset in STA mode for now.
1044 */
b4696c8b 1045 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
f078f209
LR		 1046 needreset = 1;
1047 }
1048 } else {
1049 memzero(ba, WME_BA_BMP_SIZE >> 3);
1050 }
1051 }
1052
1053 INIT_LIST_HEAD(&bf_pending);
1054 INIT_LIST_HEAD(&bf_head);
1055
1056 while (bf) {
1057 txfail = txpending = 0;
1058 bf_next = bf->bf_next;
1059
1060 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
1061 /* transmit completion, subframe is
1062 * acked by block ack */
1063 } else if (!isaggr && txok) {
1064 /* transmit completion */
1065 } else {
1066
1067 if (!tid->cleanup_inprogress && !isnodegone &&
1068 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
1069 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
1070 ath_tx_set_retry(sc, bf);
1071 txpending = 1;
1072 } else {
cd3d39a6 1073 bf->bf_state.bf_type |= BUF_XRETRY;
f078f209
LR		 1074 txfail = 1;
1075 sendbar = 1;
1076 }
1077 } else {
1078 /*
1079 * cleanup in progress, just fail
1080 * the un-acked sub-frames
1081 */
1082 txfail = 1;
1083 }
1084 }
1085 /*
1086 * Remove ath_buf's of this sub-frame from aggregate queue.
1087 */
1088 if (bf_next == NULL) { /* last subframe in the aggregate */
1089 ASSERT(bf->bf_lastfrm == bf_last);
1090
1091 /*
1092 * The last descriptor of the last sub frame could be
1093 * a holding descriptor for h/w. If that's the case,
1094 * bf->bf_lastfrm won't be in the bf_q.
1095 * Make sure we handle bf_q properly here.
1096 */
1097
1098 if (!list_empty(bf_q)) {
1099 bf_lastq = list_entry(bf_q->prev,
1100 struct ath_buf, list);
1101 list_cut_position(&bf_head,
1102 bf_q, &bf_lastq->list);
1103 } else {
1104 /*
1105 * XXX: if the last subframe only has one
1106 * descriptor which is also being used as
1107 * a holding descriptor. Then the ath_buf
1108 * is not in the bf_q at all.
1109 */
1110 INIT_LIST_HEAD(&bf_head);
1111 }
1112 } else {
1113 ASSERT(!list_empty(bf_q));
1114 list_cut_position(&bf_head,
1115 bf_q, &bf->bf_lastfrm->list);
1116 }
1117
1118 if (!txpending) {
1119 /*
1120 * complete the acked-ones/xretried ones; update
1121 * block-ack window
1122 */
1123 spin_lock_bh(&txq->axq_lock);
1124 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1125 spin_unlock_bh(&txq->axq_lock);
1126
1127 /* complete this sub-frame */
1128 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
1129 } else {
1130 /*
1131 * retry the un-acked ones
1132 */
1133 /*
1134 * XXX: if the last descriptor is holding descriptor,
1135 * in order to requeue the frame to software queue, we
1136 * need to allocate a new descriptor and
1137 * copy the content of holding descriptor to it.
1138 */
1139 if (bf->bf_next == NULL &&
1140 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
1141 struct ath_buf *tbf;
1142
1143 /* allocate new descriptor */
1144 spin_lock_bh(&sc->sc_txbuflock);
1145 ASSERT(!list_empty((&sc->sc_txbuf)));
1146 tbf = list_first_entry(&sc->sc_txbuf,
1147 struct ath_buf, list);
1148 list_del(&tbf->list);
1149 spin_unlock_bh(&sc->sc_txbuflock);
1150
1151 ATH_TXBUF_RESET(tbf);
1152
1153 /* copy descriptor content */
1154 tbf->bf_mpdu = bf_last->bf_mpdu;
1155 tbf->bf_node = bf_last->bf_node;
1156 tbf->bf_buf_addr = bf_last->bf_buf_addr;
1157 *(tbf->bf_desc) = *(bf_last->bf_desc);
1158
1159 /* link it to the frame */
1160 if (bf_lastq) {
1161 bf_lastq->bf_desc->ds_link =
1162 tbf->bf_daddr;
1163 bf->bf_lastfrm = tbf;
1164 ath9k_hw_cleartxdesc(sc->sc_ah,
1165 bf->bf_lastfrm->bf_desc);
1166 } else {
1167 tbf->bf_state = bf_last->bf_state;
1168 tbf->bf_lastfrm = tbf;
1169 ath9k_hw_cleartxdesc(sc->sc_ah,
1170 tbf->bf_lastfrm->bf_desc);
1171
1172 /* copy the DMA context */
ff9b662d
S		 1173 tbf->bf_dmacontext =
1174 bf_last->bf_dmacontext;
f078f209
LR		 1175 }
1176 list_add_tail(&tbf->list, &bf_head);
1177 } else {
1178 /*
1179 * Clear descriptor status words for
1180 * software retry
1181 */
1182 ath9k_hw_cleartxdesc(sc->sc_ah,
ff9b662d 1183 bf->bf_lastfrm->bf_desc);
f078f209
LR		 1184 }
1185
1186 /*
1187 * Put this buffer to the temporary pending
1188 * queue to retain ordering
1189 */
1190 list_splice_tail_init(&bf_head, &bf_pending);
1191 }
1192
1193 bf = bf_next;
1194 }
1195
1196 /*
1197 * node is already gone. no more assocication
1198 * with the node. the node might have been freed
1199 * any node acces can result in panic.note tid
1200 * is part of the node.
1201 */
1202 if (isnodegone)
1203 return;
1204
1205 if (tid->cleanup_inprogress) {
1206 /* check to see if we're done with cleaning the h/w queue */
1207 spin_lock_bh(&txq->axq_lock);
1208
1209 if (tid->baw_head == tid->baw_tail) {
1210 tid->addba_exchangecomplete = 0;
1211 tid->addba_exchangeattempts = 0;
1212 spin_unlock_bh(&txq->axq_lock);
1213
1214 tid->cleanup_inprogress = false;
1215
1216 /* send buffered frames as singles */
1217 ath_tx_flush_tid(sc, tid);
1218 } else
1219 spin_unlock_bh(&txq->axq_lock);
1220
1221 return;
1222 }
1223
1224 /*
1225 * prepend un-acked frames to the beginning of the pending frame queue
1226 */
1227 if (!list_empty(&bf_pending)) {
1228 spin_lock_bh(&txq->axq_lock);
1229 /* Note: we _prepend_, we _do_not_ at to
1230 * the end of the queue ! */
1231 list_splice(&bf_pending, &tid->buf_q);
1232 ath_tx_queue_tid(txq, tid);
1233 spin_unlock_bh(&txq->axq_lock);
1234 }
1235
1236 if (needreset)
f45144ef 1237 ath_reset(sc, false);
f078f209
LR		 1238
1239 return;
1240}
1241
1242/* Process completed xmit descriptors from the specified queue */
1243
1244static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1245{
1246 struct ath_hal *ah = sc->sc_ah;
1247 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1248 struct list_head bf_head;
1249 struct ath_desc *ds, *tmp_ds;
1250 struct sk_buff *skb;
1251 struct ieee80211_tx_info *tx_info;
1252 struct ath_tx_info_priv *tx_info_priv;
1253 int nacked, txok, nbad = 0, isrifs = 0;
1254 int status;
1255
1256 DPRINTF(sc, ATH_DBG_QUEUE,
1257 "%s: tx queue %d (%x), link %p\n", __func__,
1258 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1259 txq->axq_link);
1260
1261 nacked = 0;
1262 for (;;) {
1263 spin_lock_bh(&txq->axq_lock);
1264 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
1265 if (list_empty(&txq->axq_q)) {
1266 txq->axq_link = NULL;
1267 txq->axq_linkbuf = NULL;
1268 spin_unlock_bh(&txq->axq_lock);
1269 break;
1270 }
1271 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1272
1273 /*
1274 * There is a race condition that a BH gets scheduled
1275 * after sw writes TxE and before hw re-load the last
1276 * descriptor to get the newly chained one.
1277 * Software must keep the last DONE descriptor as a
1278 * holding descriptor - software does so by marking
1279 * it with the STALE flag.
1280 */
1281 bf_held = NULL;
1282 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1283 bf_held = bf;
1284 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1285 /* FIXME:
1286 * The holding descriptor is the last
1287 * descriptor in queue. It's safe to remove
1288 * the last holding descriptor in BH context.
1289 */
1290 spin_unlock_bh(&txq->axq_lock);
1291 break;
1292 } else {
1293 /* Lets work with the next buffer now */
1294 bf = list_entry(bf_held->list.next,
1295 struct ath_buf, list);
1296 }
1297 }
1298
1299 lastbf = bf->bf_lastbf;
1300 ds = lastbf->bf_desc; /* NB: last decriptor */
1301
1302 status = ath9k_hw_txprocdesc(ah, ds);
1303 if (status == -EINPROGRESS) {
1304 spin_unlock_bh(&txq->axq_lock);
1305 break;
1306 }
1307 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1308 txq->axq_lastdsWithCTS = NULL;
1309 if (ds == txq->axq_gatingds)
1310 txq->axq_gatingds = NULL;
1311
1312 /*
1313 * Remove ath_buf's of the same transmit unit from txq,
1314 * however leave the last descriptor back as the holding
1315 * descriptor for hw.
1316 */
1317 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1318 INIT_LIST_HEAD(&bf_head);
1319
1320 if (!list_is_singular(&lastbf->list))
1321 list_cut_position(&bf_head,
1322 &txq->axq_q, lastbf->list.prev);
1323
1324 txq->axq_depth--;
1325
cd3d39a6 1326 if (bf_isaggr(bf))
f078f209
LR		 1327 txq->axq_aggr_depth--;
1328
1329 txok = (ds->ds_txstat.ts_status == 0);
1330
1331 spin_unlock_bh(&txq->axq_lock);
1332
1333 if (bf_held) {
1334 list_del(&bf_held->list);
1335 spin_lock_bh(&sc->sc_txbuflock);
1336 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1337 spin_unlock_bh(&sc->sc_txbuflock);
1338 }
1339
cd3d39a6 1340 if (!bf_isampdu(bf)) {
f078f209
LR		 1341 /*
1342 * This frame is sent out as a single frame.
1343 * Use hardware retry status for this frame.
1344 */
1345 bf->bf_retries = ds->ds_txstat.ts_longretry;
1346 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
cd3d39a6 1347 bf->bf_state.bf_type |= BUF_XRETRY;
f078f209
LR		 1348 nbad = 0;
1349 } else {
1350 nbad = ath_tx_num_badfrms(sc, bf, txok);
1351 }
1352 skb = bf->bf_mpdu;
1353 tx_info = IEEE80211_SKB_CB(skb);
1354 tx_info_priv = (struct ath_tx_info_priv *)
1355 tx_info->driver_data[0];
1356 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1357 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1358 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1359 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1360 if (ds->ds_txstat.ts_status == 0)
1361 nacked++;
1362
cd3d39a6 1363 if (bf_isdata(bf)) {
f078f209
LR		 1364 if (isrifs)
1365 tmp_ds = bf->bf_rifslast->bf_desc;
1366 else
1367 tmp_ds = ds;
1368 memcpy(&tx_info_priv->tx,
1369 &tmp_ds->ds_txstat,
1370 sizeof(tx_info_priv->tx));
1371 tx_info_priv->n_frames = bf->bf_nframes;
1372 tx_info_priv->n_bad_frames = nbad;
1373 }
1374 }
1375
1376 /*
1377 * Complete this transmit unit
1378 */
cd3d39a6 1379 if (bf_isampdu(bf))
f078f209
LR		 1380 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1381 else
1382 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1383
1384 /* Wake up mac80211 queue */
1385
1386 spin_lock_bh(&txq->axq_lock);
1387 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1388 (ATH_TXBUF - 20)) {
1389 int qnum;
1390 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1391 if (qnum != -1) {
1392 ieee80211_wake_queue(sc->hw, qnum);
1393 txq->stopped = 0;
1394 }
1395
1396 }
1397
1398 /*
1399 * schedule any pending packets if aggregation is enabled
1400 */
672840ac 1401 if (sc->sc_flags & SC_OP_TXAGGR)
f078f209
LR		 1402 ath_txq_schedule(sc, txq);
1403 spin_unlock_bh(&txq->axq_lock);
1404 }
1405 return nacked;
1406}
1407
1408static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1409{
1410 struct ath_hal *ah = sc->sc_ah;
1411
1412 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1413 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1414 __func__, txq->axq_qnum,
1415 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1416}
1417
1418/* Drain only the data queues */
1419
1420static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1421{
1422 struct ath_hal *ah = sc->sc_ah;
1423 int i;
1424 int npend = 0;
f078f209
LR		 1425
1426 /* XXX return value */
672840ac 1427 if (!(sc->sc_flags & SC_OP_INVALID)) {
f078f209
LR		 1428 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1429 if (ATH_TXQ_SETUP(sc, i)) {
1430 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1431
1432 /* The TxDMA may not really be stopped.
1433 * Double check the hal tx pending count */
1434 npend += ath9k_hw_numtxpending(ah,
1435 sc->sc_txq[i].axq_qnum);
1436 }
1437 }
1438 }
1439
1440 if (npend) {
1441 int status;
1442
1443 /* TxDMA not stopped, reset the hal */
1444 DPRINTF(sc, ATH_DBG_XMIT,
1445 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1446
1447 spin_lock_bh(&sc->sc_resetlock);
b4696c8b 1448 if (!ath9k_hw_reset(ah,
927e70e9
S		 1449 sc->sc_ah->ah_curchan,
1450 sc->sc_ht_info.tx_chan_width,
1451 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1452 sc->sc_ht_extprotspacing, true, &status)) {
f078f209
LR		 1453
1454 DPRINTF(sc, ATH_DBG_FATAL,
1455 "%s: unable to reset hardware; hal status %u\n",
1456 __func__,
1457 status);
1458 }
1459 spin_unlock_bh(&sc->sc_resetlock);
1460 }
1461
1462 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1463 if (ATH_TXQ_SETUP(sc, i))
1464 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1465 }
1466}
1467
1468/* Add a sub-frame to block ack window */
1469
1470static void ath_tx_addto_baw(struct ath_softc *sc,
1471 struct ath_atx_tid *tid,
1472 struct ath_buf *bf)
1473{
1474 int index, cindex;
1475
cd3d39a6 1476 if (bf_isretried(bf))
f078f209
LR		 1477 return;
1478
1479 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1480 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1481
1482 ASSERT(tid->tx_buf[cindex] == NULL);
1483 tid->tx_buf[cindex] = bf;
1484
1485 if (index >= ((tid->baw_tail - tid->baw_head) &
1486 (ATH_TID_MAX_BUFS - 1))) {
1487 tid->baw_tail = cindex;
1488 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1489 }
1490}
1491
1492/*
1493 * Function to send an A-MPDU
1494 * NB: must be called with txq lock held
1495 */
1496
1497static int ath_tx_send_ampdu(struct ath_softc *sc,
1498 struct ath_txq *txq,
1499 struct ath_atx_tid *tid,
1500 struct list_head *bf_head,
1501 struct ath_tx_control *txctl)
1502{
1503 struct ath_buf *bf;
1504 struct sk_buff *skb;
1505 struct ieee80211_tx_info *tx_info;
1506 struct ath_tx_info_priv *tx_info_priv;
1507
1508 BUG_ON(list_empty(bf_head));
1509
1510 bf = list_first_entry(bf_head, struct ath_buf, list);
cd3d39a6 1511 bf->bf_state.bf_type |= BUF_AMPDU;
f078f209
LR		 1512 bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */
1513 bf->bf_tidno = txctl->tidno;
1514
1515 /*
1516 * Do not queue to h/w when any of the following conditions is true:
1517 * - there are pending frames in software queue
1518 * - the TID is currently paused for ADDBA/BAR request
1519 * - seqno is not within block-ack window
1520 * - h/w queue depth exceeds low water mark
1521 */
1522 if (!list_empty(&tid->buf_q) || tid->paused ||
1523 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1524 txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1525 /*
1526 * Add this frame to software queue for scheduling later
1527 * for aggregation.
1528 */
1529 list_splice_tail_init(bf_head, &tid->buf_q);
1530 ath_tx_queue_tid(txq, tid);
1531 return 0;
1532 }
1533
1534 skb = (struct sk_buff *)bf->bf_mpdu;
1535 tx_info = IEEE80211_SKB_CB(skb);
1536 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
1537 memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1538
1539 /* Add sub-frame to BAW */
1540 ath_tx_addto_baw(sc, tid, bf);
1541
1542 /* Queue to h/w without aggregation */
1543 bf->bf_nframes = 1;
1544 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1545 ath_buf_set_rate(sc, bf);
1546 ath_tx_txqaddbuf(sc, txq, bf_head);
1547 return 0;
1548}
1549
1550/*
1551 * looks up the rate
1552 * returns aggr limit based on lowest of the rates
1553 */
1554
1555static u32 ath_lookup_rate(struct ath_softc *sc,
1556 struct ath_buf *bf)
1557{
1558 const struct ath9k_rate_table *rt = sc->sc_currates;
1559 struct sk_buff *skb;
1560 struct ieee80211_tx_info *tx_info;
1561 struct ath_tx_info_priv *tx_info_priv;
1562 u32 max_4ms_framelen, frame_length;
1563 u16 aggr_limit, legacy = 0, maxampdu;
1564 int i;
1565
1566
1567 skb = (struct sk_buff *)bf->bf_mpdu;
1568 tx_info = IEEE80211_SKB_CB(skb);
1569 tx_info_priv = (struct ath_tx_info_priv *)
1570 tx_info->driver_data[0];
1571 memcpy(bf->bf_rcs,
1572 tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0]));
1573
1574 /*
1575 * Find the lowest frame length among the rate series that will have a
1576 * 4ms transmit duration.
1577 * TODO - TXOP limit needs to be considered.
1578 */
1579 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1580
1581 for (i = 0; i < 4; i++) {
1582 if (bf->bf_rcs[i].tries) {
1583 frame_length = bf->bf_rcs[i].max_4ms_framelen;
1584
1585 if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) {
1586 legacy = 1;
1587 break;
1588 }
1589
1590 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1591 }
1592 }
1593
1594 /*
1595 * limit aggregate size by the minimum rate if rate selected is
1596 * not a probe rate, if rate selected is a probe rate then
1597 * avoid aggregation of this packet.
1598 */
1599 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1600 return 0;
1601
1602 aggr_limit = min(max_4ms_framelen,
1603 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1604
1605 /*
1606 * h/w can accept aggregates upto 16 bit lengths (65535).
1607 * The IE, however can hold upto 65536, which shows up here
1608 * as zero. Ignore 65536 since we are constrained by hw.
1609 */
1610 maxampdu = sc->sc_ht_info.maxampdu;
1611 if (maxampdu)
1612 aggr_limit = min(aggr_limit, maxampdu);
1613
1614 return aggr_limit;
1615}
1616
1617/*
1618 * returns the number of delimiters to be added to
1619 * meet the minimum required mpdudensity.
1620 * caller should make sure that the rate is HT rate .
1621 */
1622
1623static int ath_compute_num_delims(struct ath_softc *sc,
1624 struct ath_buf *bf,
1625 u16 frmlen)
1626{
1627 const struct ath9k_rate_table *rt = sc->sc_currates;
1628 u32 nsymbits, nsymbols, mpdudensity;
1629 u16 minlen;
1630 u8 rc, flags, rix;
1631 int width, half_gi, ndelim, mindelim;
1632
1633 /* Select standard number of delimiters based on frame length alone */
1634 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1635
1636 /*
1637 * If encryption enabled, hardware requires some more padding between
1638 * subframes.
1639 * TODO - this could be improved to be dependent on the rate.
1640 * The hardware can keep up at lower rates, but not higher rates
1641 */
1642 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1643 ndelim += ATH_AGGR_ENCRYPTDELIM;
1644
1645 /*
1646 * Convert desired mpdu density from microeconds to bytes based
1647 * on highest rate in rate series (i.e. first rate) to determine
1648 * required minimum length for subframe. Take into account
1649 * whether high rate is 20 or 40Mhz and half or full GI.
1650 */
1651 mpdudensity = sc->sc_ht_info.mpdudensity;
1652
1653 /*
1654 * If there is no mpdu density restriction, no further calculation
1655 * is needed.
1656 */
1657 if (mpdudensity == 0)
1658 return ndelim;
1659
1660 rix = bf->bf_rcs[0].rix;
1661 flags = bf->bf_rcs[0].flags;
1662 rc = rt->info[rix].rateCode;
1663 width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0;
1664 half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0;
1665
1666 if (half_gi)
1667 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1668 else
1669 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1670
1671 if (nsymbols == 0)
1672 nsymbols = 1;
1673
1674 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1675 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1676
1677 /* Is frame shorter than required minimum length? */
1678 if (frmlen < minlen) {
1679 /* Get the minimum number of delimiters required. */
1680 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1681 ndelim = max(mindelim, ndelim);
1682 }
1683
1684 return ndelim;
1685}
1686
1687/*
1688 * For aggregation from software buffer queue.
1689 * NB: must be called with txq lock held
1690 */
1691
1692static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1693 struct ath_atx_tid *tid,
1694 struct list_head *bf_q,
1695 struct ath_buf **bf_last,
1696 struct aggr_rifs_param *param,
1697 int *prev_frames)
1698{
1699#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1700 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1701 struct list_head bf_head;
1702 int rl = 0, nframes = 0, ndelim;
1703 u16 aggr_limit = 0, al = 0, bpad = 0,
1704 al_delta, h_baw = tid->baw_size / 2;
1705 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1706 int prev_al = 0, is_ds_rate = 0;
1707 INIT_LIST_HEAD(&bf_head);
1708
1709 BUG_ON(list_empty(&tid->buf_q));
1710
1711 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1712
1713 do {
1714 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1715
1716 /*
1717 * do not step over block-ack window
1718 */
1719 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1720 status = ATH_AGGR_BAW_CLOSED;
1721 break;
1722 }
1723
1724 if (!rl) {
1725 aggr_limit = ath_lookup_rate(sc, bf);
1726 rl = 1;
1727 /*
1728 * Is rate dual stream
1729 */
1730 is_ds_rate =
1731 (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0;
1732 }
1733
1734 /*
1735 * do not exceed aggregation limit
1736 */
1737 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1738
1739 if (nframes && (aggr_limit <
1740 (al + bpad + al_delta + prev_al))) {
1741 status = ATH_AGGR_LIMITED;
1742 break;
1743 }
1744
1745 /*
1746 * do not exceed subframe limit
1747 */
1748 if ((nframes + *prev_frames) >=
1749 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1750 status = ATH_AGGR_LIMITED;
1751 break;
1752 }
1753
1754 /*
1755 * add padding for previous frame to aggregation length
1756 */
1757 al += bpad + al_delta;
1758
1759 /*
1760 * Get the delimiters needed to meet the MPDU
1761 * density for this node.
1762 */
1763 ndelim = ath_compute_num_delims(sc, bf_first, bf->bf_frmlen);
1764
1765 bpad = PADBYTES(al_delta) + (ndelim << 2);
1766
1767 bf->bf_next = NULL;
1768 bf->bf_lastfrm->bf_desc->ds_link = 0;
1769
1770 /*
1771 * this packet is part of an aggregate
1772 * - remove all descriptors belonging to this frame from
1773 * software queue
1774 * - add it to block ack window
1775 * - set up descriptors for aggregation
1776 */
1777 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1778 ath_tx_addto_baw(sc, tid, bf);
1779
1780 list_for_each_entry(tbf, &bf_head, list) {
1781 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1782 tbf->bf_desc, ndelim);
1783 }
1784
1785 /*
1786 * link buffers of this frame to the aggregate
1787 */
1788 list_splice_tail_init(&bf_head, bf_q);
1789 nframes++;
1790
1791 if (bf_prev) {
1792 bf_prev->bf_next = bf;
1793 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1794 }
1795 bf_prev = bf;
1796
1797#ifdef AGGR_NOSHORT
1798 /*
1799 * terminate aggregation on a small packet boundary
1800 */
1801 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1802 status = ATH_AGGR_SHORTPKT;
1803 break;
1804 }
1805#endif
1806 } while (!list_empty(&tid->buf_q));
1807
1808 bf_first->bf_al = al;
1809 bf_first->bf_nframes = nframes;
1810 *bf_last = bf_prev;
1811 return status;
1812#undef PADBYTES
1813}
1814
1815/*
1816 * process pending frames possibly doing a-mpdu aggregation
1817 * NB: must be called with txq lock held
1818 */
1819
1820static void ath_tx_sched_aggr(struct ath_softc *sc,
1821 struct ath_txq *txq, struct ath_atx_tid *tid)
1822{
1823 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1824 enum ATH_AGGR_STATUS status;
1825 struct list_head bf_q;
1826 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1827 int prev_frames = 0;
1828
1829 do {
1830 if (list_empty(&tid->buf_q))
1831 return;
1832
1833 INIT_LIST_HEAD(&bf_q);
1834
1835 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1836 &prev_frames);
1837
1838 /*
1839 * no frames picked up to be aggregated; block-ack
1840 * window is not open
1841 */
1842 if (list_empty(&bf_q))
1843 break;
1844
1845 bf = list_first_entry(&bf_q, struct ath_buf, list);
1846 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1847 bf->bf_lastbf = bf_last;
1848
1849 /*
1850 * if only one frame, send as non-aggregate
1851 */
1852 if (bf->bf_nframes == 1) {
1853 ASSERT(bf->bf_lastfrm == bf_last);
1854
cd3d39a6 1855 bf->bf_state.bf_type &= ~BUF_AGGR;
f078f209
LR		 1856 /*
1857 * clear aggr bits for every descriptor
1858 * XXX TODO: is there a way to optimize it?
1859 */
1860 list_for_each_entry(tbf, &bf_q, list) {
1861 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1862 }
1863
1864 ath_buf_set_rate(sc, bf);
1865 ath_tx_txqaddbuf(sc, txq, &bf_q);
1866 continue;
1867 }
1868
1869 /*
1870 * setup first desc with rate and aggr info
1871 */
cd3d39a6 1872 bf->bf_state.bf_type |= BUF_AGGR;
f078f209
LR		 1873 ath_buf_set_rate(sc, bf);
1874 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1875
1876 /*
1877 * anchor last frame of aggregate correctly
1878 */
1879 ASSERT(bf_lastaggr);
1880 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1881 tbf = bf_lastaggr;
1882 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1883
1884 /* XXX: We don't enter into this loop, consider removing this */
1885 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1886 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1887 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1888 }
1889
1890 txq->axq_aggr_depth++;
1891
1892 /*
1893 * Normal aggregate, queue to hardware
1894 */
1895 ath_tx_txqaddbuf(sc, txq, &bf_q);
1896
1897 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1898 status != ATH_AGGR_BAW_CLOSED);
1899}
1900
1901/* Called with txq lock held */
1902
1903static void ath_tid_drain(struct ath_softc *sc,
1904 struct ath_txq *txq,
1905 struct ath_atx_tid *tid,
1906 bool bh_flag)
1907{
1908 struct ath_buf *bf;
1909 struct list_head bf_head;
1910 INIT_LIST_HEAD(&bf_head);
1911
1912 for (;;) {
1913 if (list_empty(&tid->buf_q))
1914 break;
1915 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1916
1917 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1918
1919 /* update baw for software retried frame */
cd3d39a6 1920 if (bf_isretried(bf))
f078f209
LR		 1921 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1922
1923 /*
1924 * do not indicate packets while holding txq spinlock.
1925 * unlock is intentional here
1926 */
1927 if (likely(bh_flag))
1928 spin_unlock_bh(&txq->axq_lock);
1929 else
1930 spin_unlock(&txq->axq_lock);
1931
1932 /* complete this sub-frame */
1933 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1934
1935 if (likely(bh_flag))
1936 spin_lock_bh(&txq->axq_lock);
1937 else
1938 spin_lock(&txq->axq_lock);
1939 }
1940
1941 /*
1942 * TODO: For frame(s) that are in the retry state, we will reuse the
1943 * sequence number(s) without setting the retry bit. The
1944 * alternative is to give up on these and BAR the receiver's window
1945 * forward.
1946 */
1947 tid->seq_next = tid->seq_start;
1948 tid->baw_tail = tid->baw_head;
1949}
1950
1951/*
1952 * Drain all pending buffers
1953 * NB: must be called with txq lock held
1954 */
1955
1956static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1957 struct ath_txq *txq,
1958 bool bh_flag)
1959{
1960 struct ath_atx_ac *ac, *ac_tmp;
1961 struct ath_atx_tid *tid, *tid_tmp;
1962
1963 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1964 list_del(&ac->list);
1965 ac->sched = false;
1966 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1967 list_del(&tid->list);
1968 tid->sched = false;
1969 ath_tid_drain(sc, txq, tid, bh_flag);
1970 }
1971 }
1972}
1973
1974static int ath_tx_start_dma(struct ath_softc *sc,
1975 struct sk_buff *skb,
1976 struct scatterlist *sg,
1977 u32 n_sg,
1978 struct ath_tx_control *txctl)
1979{
1980 struct ath_node *an = txctl->an;
1981 struct ath_buf *bf = NULL;
1982 struct list_head bf_head;
1983 struct ath_desc *ds;
1984 struct ath_hal *ah = sc->sc_ah;
1985 struct ath_txq *txq = &sc->sc_txq[txctl->qnum];
1986 struct ath_tx_info_priv *tx_info_priv;
1987 struct ath_rc_series *rcs;
1988 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1989 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1990 __le16 fc = hdr->frame_control;
1991
1992 /* For each sglist entry, allocate an ath_buf for DMA */
1993 INIT_LIST_HEAD(&bf_head);
1994 spin_lock_bh(&sc->sc_txbuflock);
1995 if (unlikely(list_empty(&sc->sc_txbuf))) {
1996 spin_unlock_bh(&sc->sc_txbuflock);
1997 return -ENOMEM;
1998 }
1999
2000 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
2001 list_del(&bf->list);
2002 spin_unlock_bh(&sc->sc_txbuflock);
2003
2004 list_add_tail(&bf->list, &bf_head);
2005
2006 /* set up this buffer */
2007 ATH_TXBUF_RESET(bf);
2008 bf->bf_frmlen = txctl->frmlen;
cd3d39a6
S		 2009
2010 ieee80211_is_data(fc) ?
2011 (bf->bf_state.bf_type |= BUF_DATA) :
2012 (bf->bf_state.bf_type &= ~BUF_DATA);
2013 ieee80211_is_back_req(fc) ?
2014 (bf->bf_state.bf_type |= BUF_BAR) :
2015 (bf->bf_state.bf_type &= ~BUF_BAR);
2016 ieee80211_is_pspoll(fc) ?
2017 (bf->bf_state.bf_type |= BUF_PSPOLL) :
2018 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
672840ac 2019 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
cd3d39a6
S		 2020 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
2021 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
2022
f078f209 2023 bf->bf_flags = txctl->flags;
f078f209
LR		 2024 bf->bf_keytype = txctl->keytype;
2025 tx_info_priv = (struct ath_tx_info_priv *)tx_info->driver_data[0];
2026 rcs = tx_info_priv->rcs;
2027 bf->bf_rcs[0] = rcs[0];
2028 bf->bf_rcs[1] = rcs[1];
2029 bf->bf_rcs[2] = rcs[2];
2030 bf->bf_rcs[3] = rcs[3];
2031 bf->bf_node = an;
2032 bf->bf_mpdu = skb;
2033 bf->bf_buf_addr = sg_dma_address(sg);
2034
2035 /* setup descriptor */
2036 ds = bf->bf_desc;
2037 ds->ds_link = 0;
2038 ds->ds_data = bf->bf_buf_addr;
2039
2040 /*
2041 * Save the DMA context in the first ath_buf
2042 */
ff9b662d 2043 bf->bf_dmacontext = txctl->dmacontext;
f078f209
LR		 2044
2045 /*
2046 * Formulate first tx descriptor with tx controls.
2047 */
2048 ath9k_hw_set11n_txdesc(ah,
2049 ds,
2050 bf->bf_frmlen, /* frame length */
2051 txctl->atype, /* Atheros packet type */
2052 min(txctl->txpower, (u16)60), /* txpower */
2053 txctl->keyix, /* key cache index */
2054 txctl->keytype, /* key type */
2055 txctl->flags); /* flags */
2056 ath9k_hw_filltxdesc(ah,
2057 ds,
2058 sg_dma_len(sg), /* segment length */
2059 true, /* first segment */
2060 (n_sg == 1) ? true : false, /* last segment */
2061 ds); /* first descriptor */
2062
2063 bf->bf_lastfrm = bf;
cd3d39a6
S		 2064 (txctl->ht) ?
2065 (bf->bf_state.bf_type |= BUF_HT) :
2066 (bf->bf_state.bf_type &= ~BUF_HT);
f078f209
LR		 2067
2068 spin_lock_bh(&txq->axq_lock);
2069
672840ac 2070 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 2071 struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno);
2072 if (ath_aggr_query(sc, an, txctl->tidno)) {
2073 /*
2074 * Try aggregation if it's a unicast data frame
2075 * and the destination is HT capable.
2076 */
2077 ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl);
2078 } else {
2079 /*
2080 * Send this frame as regular when ADDBA exchange
2081 * is neither complete nor pending.
2082 */
2083 ath_tx_send_normal(sc, txq, tid, &bf_head);
2084 }
2085 } else {
2086 bf->bf_lastbf = bf;
2087 bf->bf_nframes = 1;
2088 ath_buf_set_rate(sc, bf);
2089
2090 if (ieee80211_is_back_req(fc)) {
2091 /* This is required for resuming tid
2092 * during BAR completion */
2093 bf->bf_tidno = txctl->tidno;
2094 }
2095
2096 if (is_multicast_ether_addr(hdr->addr1)) {
2097 struct ath_vap *avp = sc->sc_vaps[txctl->if_id];
2098
2099 /*
2100 * When servicing one or more stations in power-save
2101 * mode (or) if there is some mcast data waiting on
2102 * mcast queue (to prevent out of order delivery of
2103 * mcast,bcast packets) multicast frames must be
2104 * buffered until after the beacon. We use the private
2105 * mcast queue for that.
2106 */
2107 /* XXX? more bit in 802.11 frame header */
2108 spin_lock_bh(&avp->av_mcastq.axq_lock);
2109 if (txctl->ps || avp->av_mcastq.axq_depth)
2110 ath_tx_mcastqaddbuf(sc,
2111 &avp->av_mcastq, &bf_head);
2112 else
2113 ath_tx_txqaddbuf(sc, txq, &bf_head);
2114 spin_unlock_bh(&avp->av_mcastq.axq_lock);
2115 } else
2116 ath_tx_txqaddbuf(sc, txq, &bf_head);
2117 }
2118 spin_unlock_bh(&txq->axq_lock);
2119 return 0;
2120}
2121
2122static void xmit_map_sg(struct ath_softc *sc,
2123 struct sk_buff *skb,
f078f209
LR		 2124 struct ath_tx_control *txctl)
2125{
2126 struct ath_xmit_status tx_status;
2127 struct ath_atx_tid *tid;
2128 struct scatterlist sg;
2129
ff9b662d
S		 2130 txctl->dmacontext = pci_map_single(sc->pdev, skb->data,
2131 skb->len, PCI_DMA_TODEVICE);
f078f209
LR		 2132
2133 /* setup S/G list */
2134 memset(&sg, 0, sizeof(struct scatterlist));
ff9b662d 2135 sg_dma_address(&sg) = txctl->dmacontext;
f078f209
LR		 2136 sg_dma_len(&sg) = skb->len;
2137
2138 if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) {
2139 /*
2140 * We have to do drop frame here.
2141 */
ff9b662d
S		 2142 pci_unmap_single(sc->pdev, txctl->dmacontext,
2143 skb->len, PCI_DMA_TODEVICE);
f078f209
LR		 2144
2145 tx_status.retries = 0;
2146 tx_status.flags = ATH_TX_ERROR;
2147
672840ac 2148 if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) {
f078f209
LR		 2149 /* Reclaim the seqno. */
2150 tid = ATH_AN_2_TID((struct ath_node *)
2151 txctl->an, txctl->tidno);
2152 DECR(tid->seq_next, IEEE80211_SEQ_MAX);
2153 }
2154 ath_tx_complete(sc, skb, &tx_status, txctl->an);
2155 }
2156}
2157
2158/* Initialize TX queue and h/w */
2159
2160int ath_tx_init(struct ath_softc *sc, int nbufs)
2161{
2162 int error = 0;
2163
2164 do {
2165 spin_lock_init(&sc->sc_txbuflock);
2166
2167 /* Setup tx descriptors */
2168 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
556bb8f1 2169 "tx", nbufs, 1);
f078f209
LR		 2170 if (error != 0) {
2171 DPRINTF(sc, ATH_DBG_FATAL,
2172 "%s: failed to allocate tx descriptors: %d\n",
2173 __func__, error);
2174 break;
2175 }
2176
2177 /* XXX allocate beacon state together with vap */
2178 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2179 "beacon", ATH_BCBUF, 1);
2180 if (error != 0) {
2181 DPRINTF(sc, ATH_DBG_FATAL,
2182 "%s: failed to allocate "
2183 "beacon descripotrs: %d\n",
2184 __func__, error);
2185 break;
2186 }
2187
2188 } while (0);
2189
2190 if (error != 0)
2191 ath_tx_cleanup(sc);
2192
2193 return error;
2194}
2195
2196/* Reclaim all tx queue resources */
2197
2198int ath_tx_cleanup(struct ath_softc *sc)
2199{
2200 /* cleanup beacon descriptors */
2201 if (sc->sc_bdma.dd_desc_len != 0)
2202 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2203
2204 /* cleanup tx descriptors */
2205 if (sc->sc_txdma.dd_desc_len != 0)
2206 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2207
2208 return 0;
2209}
2210
2211/* Setup a h/w transmit queue */
2212
2213struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2214{
2215 struct ath_hal *ah = sc->sc_ah;
ea9880fb 2216 struct ath9k_tx_queue_info qi;
f078f209
LR		 2217 int qnum;
2218
2219 memzero(&qi, sizeof(qi));
2220 qi.tqi_subtype = subtype;
2221 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
2222 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
2223 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
ea9880fb 2224 qi.tqi_physCompBuf = 0;
f078f209
LR		 2225
2226 /*
2227 * Enable interrupts only for EOL and DESC conditions.
2228 * We mark tx descriptors to receive a DESC interrupt
2229 * when a tx queue gets deep; otherwise waiting for the
2230 * EOL to reap descriptors. Note that this is done to
2231 * reduce interrupt load and this only defers reaping
2232 * descriptors, never transmitting frames. Aside from
2233 * reducing interrupts this also permits more concurrency.
2234 * The only potential downside is if the tx queue backs
2235 * up in which case the top half of the kernel may backup
2236 * due to a lack of tx descriptors.
2237 *
2238 * The UAPSD queue is an exception, since we take a desc-
2239 * based intr on the EOSP frames.
2240 */
2241 if (qtype == ATH9K_TX_QUEUE_UAPSD)
2242 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
2243 else
2244 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
2245 TXQ_FLAG_TXDESCINT_ENABLE;
2246 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
2247 if (qnum == -1) {
2248 /*
2249 * NB: don't print a message, this happens
2250 * normally on parts with too few tx queues
2251 */
2252 return NULL;
2253 }
2254 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
2255 DPRINTF(sc, ATH_DBG_FATAL,
2256 "%s: hal qnum %u out of range, max %u!\n",
2257 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
2258 ath9k_hw_releasetxqueue(ah, qnum);
2259 return NULL;
2260 }
2261 if (!ATH_TXQ_SETUP(sc, qnum)) {
2262 struct ath_txq *txq = &sc->sc_txq[qnum];
2263
2264 txq->axq_qnum = qnum;
2265 txq->axq_link = NULL;
2266 INIT_LIST_HEAD(&txq->axq_q);
2267 INIT_LIST_HEAD(&txq->axq_acq);
2268 spin_lock_init(&txq->axq_lock);
2269 txq->axq_depth = 0;
2270 txq->axq_aggr_depth = 0;
2271 txq->axq_totalqueued = 0;
2272 txq->axq_intrcnt = 0;
2273 txq->axq_linkbuf = NULL;
2274 sc->sc_txqsetup |= 1<<qnum;
2275 }
2276 return &sc->sc_txq[qnum];
2277}
2278
2279/* Reclaim resources for a setup queue */
2280
2281void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
2282{
2283 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
2284 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
2285}
2286
2287/*
2288 * Setup a hardware data transmit queue for the specified
2289 * access control. The hal may not support all requested
2290 * queues in which case it will return a reference to a
2291 * previously setup queue. We record the mapping from ac's
2292 * to h/w queues for use by ath_tx_start and also track
2293 * the set of h/w queues being used to optimize work in the
2294 * transmit interrupt handler and related routines.
2295 */
2296
2297int ath_tx_setup(struct ath_softc *sc, int haltype)
2298{
2299 struct ath_txq *txq;
2300
2301 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2302 DPRINTF(sc, ATH_DBG_FATAL,
2303 "%s: HAL AC %u out of range, max %zu!\n",
2304 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
2305 return 0;
2306 }
2307 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
2308 if (txq != NULL) {
2309 sc->sc_haltype2q[haltype] = txq->axq_qnum;
2310 return 1;
2311 } else
2312 return 0;
2313}
2314
2315int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
2316{
2317 int qnum;
2318
2319 switch (qtype) {
2320 case ATH9K_TX_QUEUE_DATA:
2321 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
2322 DPRINTF(sc, ATH_DBG_FATAL,
2323 "%s: HAL AC %u out of range, max %zu!\n",
2324 __func__,
2325 haltype, ARRAY_SIZE(sc->sc_haltype2q));
2326 return -1;
2327 }
2328 qnum = sc->sc_haltype2q[haltype];
2329 break;
2330 case ATH9K_TX_QUEUE_BEACON:
2331 qnum = sc->sc_bhalq;
2332 break;
2333 case ATH9K_TX_QUEUE_CAB:
2334 qnum = sc->sc_cabq->axq_qnum;
2335 break;
2336 default:
2337 qnum = -1;
2338 }
2339 return qnum;
2340}
2341
2342/* Update parameters for a transmit queue */
2343
ea9880fb
S		 2344int ath_txq_update(struct ath_softc *sc, int qnum,
2345 struct ath9k_tx_queue_info *qinfo)
f078f209
LR		 2346{
2347 struct ath_hal *ah = sc->sc_ah;
2348 int error = 0;
ea9880fb 2349 struct ath9k_tx_queue_info qi;
f078f209
LR		 2350
2351 if (qnum == sc->sc_bhalq) {
2352 /*
2353 * XXX: for beacon queue, we just save the parameter.
2354 * It will be picked up by ath_beaconq_config when
2355 * it's necessary.
2356 */
ea9880fb 2357 sc->sc_beacon_qi = *qinfo;
f078f209
LR		 2358 return 0;
2359 }
2360
2361 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2362
ea9880fb
S		 2363 ath9k_hw_get_txq_props(ah, qnum, &qi);
2364 qi.tqi_aifs = qinfo->tqi_aifs;
2365 qi.tqi_cwmin = qinfo->tqi_cwmin;
2366 qi.tqi_cwmax = qinfo->tqi_cwmax;
2367 qi.tqi_burstTime = qinfo->tqi_burstTime;
2368 qi.tqi_readyTime = qinfo->tqi_readyTime;
f078f209 2369
ea9880fb 2370 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
f078f209
LR		 2371 DPRINTF(sc, ATH_DBG_FATAL,
2372 "%s: unable to update hardware queue %u!\n",
2373 __func__, qnum);
2374 error = -EIO;
2375 } else {
2376 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2377 }
2378
2379 return error;
2380}
2381
2382int ath_cabq_update(struct ath_softc *sc)
2383{
ea9880fb 2384 struct ath9k_tx_queue_info qi;
f078f209
LR		 2385 int qnum = sc->sc_cabq->axq_qnum;
2386 struct ath_beacon_config conf;
2387
ea9880fb 2388 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
f078f209
LR		 2389 /*
2390 * Ensure the readytime % is within the bounds.
2391 */
2392 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2393 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2394 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2395 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2396
2397 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2398 qi.tqi_readyTime =
2399 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2400 ath_txq_update(sc, qnum, &qi);
2401
2402 return 0;
2403}
2404
2405int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb)
2406{
2407 struct ath_tx_control txctl;
2408 int error = 0;
2409
2410 error = ath_tx_prepare(sc, skb, &txctl);
2411 if (error == 0)
2412 /*
2413 * Start DMA mapping.
2414 * ath_tx_start_dma() will be called either synchronously
2415 * or asynchrounsly once DMA is complete.
2416 */
ff9b662d 2417 xmit_map_sg(sc, skb, &txctl);
f078f209
LR		 2418 else
2419 ath_node_put(sc, txctl.an, ATH9K_BH_STATUS_CHANGE);
2420
2421 /* failed packets will be dropped by the caller */
2422 return error;
2423}
2424
2425/* Deferred processing of transmit interrupt */
2426
2427void ath_tx_tasklet(struct ath_softc *sc)
2428{
2429 u64 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2430 int i, nacked = 0;
2431 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2432
2433 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2434
2435 /*
2436 * Process each active queue.
2437 */
2438 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2439 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2440 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
2441 }
2442 if (nacked)
2443 sc->sc_lastrx = tsf;
2444}
2445
2446void ath_tx_draintxq(struct ath_softc *sc,
2447 struct ath_txq *txq, bool retry_tx)
2448{
2449 struct ath_buf *bf, *lastbf;
2450 struct list_head bf_head;
2451
2452 INIT_LIST_HEAD(&bf_head);
2453
2454 /*
2455 * NB: this assumes output has been stopped and
2456 * we do not need to block ath_tx_tasklet
2457 */
2458 for (;;) {
2459 spin_lock_bh(&txq->axq_lock);
2460
2461 if (list_empty(&txq->axq_q)) {
2462 txq->axq_link = NULL;
2463 txq->axq_linkbuf = NULL;
2464 spin_unlock_bh(&txq->axq_lock);
2465 break;
2466 }
2467
2468 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2469
2470 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2471 list_del(&bf->list);
2472 spin_unlock_bh(&txq->axq_lock);
2473
2474 spin_lock_bh(&sc->sc_txbuflock);
2475 list_add_tail(&bf->list, &sc->sc_txbuf);
2476 spin_unlock_bh(&sc->sc_txbuflock);
2477 continue;
2478 }
2479
2480 lastbf = bf->bf_lastbf;
2481 if (!retry_tx)
2482 lastbf->bf_desc->ds_txstat.ts_flags =
2483 ATH9K_TX_SW_ABORTED;
2484
2485 /* remove ath_buf's of the same mpdu from txq */
2486 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2487 txq->axq_depth--;
2488
2489 spin_unlock_bh(&txq->axq_lock);
2490
cd3d39a6 2491 if (bf_isampdu(bf))
f078f209
LR		 2492 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2493 else
2494 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2495 }
2496
2497 /* flush any pending frames if aggregation is enabled */
672840ac 2498 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2499 if (!retry_tx) {
2500 spin_lock_bh(&txq->axq_lock);
2501 ath_txq_drain_pending_buffers(sc, txq,
2502 ATH9K_BH_STATUS_CHANGE);
2503 spin_unlock_bh(&txq->axq_lock);
2504 }
2505 }
2506}
2507
2508/* Drain the transmit queues and reclaim resources */
2509
2510void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2511{
2512 /* stop beacon queue. The beacon will be freed when
2513 * we go to INIT state */
672840ac 2514 if (!(sc->sc_flags & SC_OP_INVALID)) {
f078f209
LR		 2515 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2516 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2517 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2518 }
2519
2520 ath_drain_txdataq(sc, retry_tx);
2521}
2522
2523u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2524{
2525 return sc->sc_txq[qnum].axq_depth;
2526}
2527
2528u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2529{
2530 return sc->sc_txq[qnum].axq_aggr_depth;
2531}
2532
2533/* Check if an ADDBA is required. A valid node must be passed. */
2534enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc,
2535 struct ath_node *an,
2536 u8 tidno)
2537{
2538 struct ath_atx_tid *txtid;
2539 DECLARE_MAC_BUF(mac);
2540
672840ac 2541 if (!(sc->sc_flags & SC_OP_TXAGGR))
f078f209
LR		 2542 return AGGR_NOT_REQUIRED;
2543
2544 /* ADDBA exchange must be completed before sending aggregates */
2545 txtid = ATH_AN_2_TID(an, tidno);
2546
2547 if (txtid->addba_exchangecomplete)
2548 return AGGR_EXCHANGE_DONE;
2549
2550 if (txtid->cleanup_inprogress)
2551 return AGGR_CLEANUP_PROGRESS;
2552
2553 if (txtid->addba_exchangeinprogress)
2554 return AGGR_EXCHANGE_PROGRESS;
2555
2556 if (!txtid->addba_exchangecomplete) {
2557 if (!txtid->addba_exchangeinprogress &&
2558 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2559 txtid->addba_exchangeattempts++;
2560 return AGGR_REQUIRED;
2561 }
2562 }
2563
2564 return AGGR_NOT_REQUIRED;
2565}
2566
2567/* Start TX aggregation */
2568
2569int ath_tx_aggr_start(struct ath_softc *sc,
2570 const u8 *addr,
2571 u16 tid,
2572 u16 *ssn)
2573{
2574 struct ath_atx_tid *txtid;
2575 struct ath_node *an;
2576
2577 spin_lock_bh(&sc->node_lock);
2578 an = ath_node_find(sc, (u8 *) addr);
2579 spin_unlock_bh(&sc->node_lock);
2580
2581 if (!an) {
2582 DPRINTF(sc, ATH_DBG_AGGR,
2583 "%s: Node not found to initialize "
2584 "TX aggregation\n", __func__);
2585 return -1;
2586 }
2587
672840ac 2588 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2589 txtid = ATH_AN_2_TID(an, tid);
2590 txtid->addba_exchangeinprogress = 1;
2591 ath_tx_pause_tid(sc, txtid);
2592 }
2593
2594 return 0;
2595}
2596
2597/* Stop tx aggregation */
2598
2599int ath_tx_aggr_stop(struct ath_softc *sc,
2600 const u8 *addr,
2601 u16 tid)
2602{
2603 struct ath_node *an;
2604
2605 spin_lock_bh(&sc->node_lock);
2606 an = ath_node_find(sc, (u8 *) addr);
2607 spin_unlock_bh(&sc->node_lock);
2608
2609 if (!an) {
2610 DPRINTF(sc, ATH_DBG_AGGR,
2611 "%s: TX aggr stop for non-existent node\n", __func__);
2612 return -1;
2613 }
2614
2615 ath_tx_aggr_teardown(sc, an, tid);
2616 return 0;
2617}
2618
2619/*
2620 * Performs transmit side cleanup when TID changes from aggregated to
2621 * unaggregated.
2622 * - Pause the TID and mark cleanup in progress
2623 * - Discard all retry frames from the s/w queue.
2624 */
2625
2626void ath_tx_aggr_teardown(struct ath_softc *sc,
2627 struct ath_node *an, u8 tid)
2628{
2629 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2630 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2631 struct ath_buf *bf;
2632 struct list_head bf_head;
2633 INIT_LIST_HEAD(&bf_head);
2634
2635 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2636
2637 if (txtid->cleanup_inprogress) /* cleanup is in progress */
2638 return;
2639
2640 if (!txtid->addba_exchangecomplete) {
2641 txtid->addba_exchangeattempts = 0;
2642 return;
2643 }
2644
2645 /* TID must be paused first */
2646 ath_tx_pause_tid(sc, txtid);
2647
2648 /* drop all software retried frames and mark this TID */
2649 spin_lock_bh(&txq->axq_lock);
2650 while (!list_empty(&txtid->buf_q)) {
2651 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
cd3d39a6 2652 if (!bf_isretried(bf)) {
f078f209
LR		 2653 /*
2654 * NB: it's based on the assumption that
2655 * software retried frame will always stay
2656 * at the head of software queue.
2657 */
2658 break;
2659 }
2660 list_cut_position(&bf_head,
2661 &txtid->buf_q, &bf->bf_lastfrm->list);
2662 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2663
2664 /* complete this sub-frame */
2665 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2666 }
2667
2668 if (txtid->baw_head != txtid->baw_tail) {
2669 spin_unlock_bh(&txq->axq_lock);
2670 txtid->cleanup_inprogress = true;
2671 } else {
2672 txtid->addba_exchangecomplete = 0;
2673 txtid->addba_exchangeattempts = 0;
2674 spin_unlock_bh(&txq->axq_lock);
2675 ath_tx_flush_tid(sc, txtid);
2676 }
2677}
2678
2679/*
2680 * Tx scheduling logic
2681 * NB: must be called with txq lock held
2682 */
2683
2684void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2685{
2686 struct ath_atx_ac *ac;
2687 struct ath_atx_tid *tid;
2688
2689 /* nothing to schedule */
2690 if (list_empty(&txq->axq_acq))
2691 return;
2692 /*
2693 * get the first node/ac pair on the queue
2694 */
2695 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2696 list_del(&ac->list);
2697 ac->sched = false;
2698
2699 /*
2700 * process a single tid per destination
2701 */
2702 do {
2703 /* nothing to schedule */
2704 if (list_empty(&ac->tid_q))
2705 return;
2706
2707 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2708 list_del(&tid->list);
2709 tid->sched = false;
2710
2711 if (tid->paused) /* check next tid to keep h/w busy */
2712 continue;
2713
2714 if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) ||
2715 ((txq->axq_depth % 2) == 0)) {
2716 ath_tx_sched_aggr(sc, txq, tid);
2717 }
2718
2719 /*
2720 * add tid to round-robin queue if more frames
2721 * are pending for the tid
2722 */
2723 if (!list_empty(&tid->buf_q))
2724 ath_tx_queue_tid(txq, tid);
2725
2726 /* only schedule one TID at a time */
2727 break;
2728 } while (!list_empty(&ac->tid_q));
2729
2730 /*
2731 * schedule AC if more TIDs need processing
2732 */
2733 if (!list_empty(&ac->tid_q)) {
2734 /*
2735 * add dest ac to txq if not already added
2736 */
2737 if (!ac->sched) {
2738 ac->sched = true;
2739 list_add_tail(&ac->list, &txq->axq_acq);
2740 }
2741 }
2742}
2743
2744/* Initialize per-node transmit state */
2745
2746void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2747{
672840ac 2748 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2749 struct ath_atx_tid *tid;
2750 struct ath_atx_ac *ac;
2751 int tidno, acno;
2752
2753 sc->sc_ht_info.maxampdu = ATH_AMPDU_LIMIT_DEFAULT;
2754
2755 /*
2756 * Init per tid tx state
2757 */
2758 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2759 tidno < WME_NUM_TID;
2760 tidno++, tid++) {
2761 tid->an = an;
2762 tid->tidno = tidno;
2763 tid->seq_start = tid->seq_next = 0;
2764 tid->baw_size = WME_MAX_BA;
2765 tid->baw_head = tid->baw_tail = 0;
2766 tid->sched = false;
2767 tid->paused = false;
2768 tid->cleanup_inprogress = false;
2769 INIT_LIST_HEAD(&tid->buf_q);
2770
2771 acno = TID_TO_WME_AC(tidno);
2772 tid->ac = &an->an_aggr.tx.ac[acno];
2773
2774 /* ADDBA state */
2775 tid->addba_exchangecomplete = 0;
2776 tid->addba_exchangeinprogress = 0;
2777 tid->addba_exchangeattempts = 0;
2778 }
2779
2780 /*
2781 * Init per ac tx state
2782 */
2783 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2784 acno < WME_NUM_AC; acno++, ac++) {
2785 ac->sched = false;
2786 INIT_LIST_HEAD(&ac->tid_q);
2787
2788 switch (acno) {
2789 case WME_AC_BE:
2790 ac->qnum = ath_tx_get_qnum(sc,
2791 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2792 break;
2793 case WME_AC_BK:
2794 ac->qnum = ath_tx_get_qnum(sc,
2795 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2796 break;
2797 case WME_AC_VI:
2798 ac->qnum = ath_tx_get_qnum(sc,
2799 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2800 break;
2801 case WME_AC_VO:
2802 ac->qnum = ath_tx_get_qnum(sc,
2803 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2804 break;
2805 }
2806 }
2807 }
2808}
2809
2810/* Cleanupthe pending buffers for the node. */
2811
2812void ath_tx_node_cleanup(struct ath_softc *sc,
2813 struct ath_node *an, bool bh_flag)
2814{
2815 int i;
2816 struct ath_atx_ac *ac, *ac_tmp;
2817 struct ath_atx_tid *tid, *tid_tmp;
2818 struct ath_txq *txq;
2819 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2820 if (ATH_TXQ_SETUP(sc, i)) {
2821 txq = &sc->sc_txq[i];
2822
2823 if (likely(bh_flag))
2824 spin_lock_bh(&txq->axq_lock);
2825 else
2826 spin_lock(&txq->axq_lock);
2827
2828 list_for_each_entry_safe(ac,
2829 ac_tmp, &txq->axq_acq, list) {
2830 tid = list_first_entry(&ac->tid_q,
2831 struct ath_atx_tid, list);
2832 if (tid && tid->an != an)
2833 continue;
2834 list_del(&ac->list);
2835 ac->sched = false;
2836
2837 list_for_each_entry_safe(tid,
2838 tid_tmp, &ac->tid_q, list) {
2839 list_del(&tid->list);
2840 tid->sched = false;
2841 ath_tid_drain(sc, txq, tid, bh_flag);
2842 tid->addba_exchangecomplete = 0;
2843 tid->addba_exchangeattempts = 0;
2844 tid->cleanup_inprogress = false;
2845 }
2846 }
2847
2848 if (likely(bh_flag))
2849 spin_unlock_bh(&txq->axq_lock);
2850 else
2851 spin_unlock(&txq->axq_lock);
2852 }
2853 }
2854}
2855
2856/* Cleanup per node transmit state */
2857
2858void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an)
2859{
672840ac 2860 if (sc->sc_flags & SC_OP_TXAGGR) {
f078f209
LR		 2861 struct ath_atx_tid *tid;
2862 int tidno, i;
2863
2864 /* Init per tid rx state */
2865 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2866 tidno < WME_NUM_TID;
2867 tidno++, tid++) {
2868
2869 for (i = 0; i < ATH_TID_MAX_BUFS; i++)
2870 ASSERT(tid->tx_buf[i] == NULL);
2871 }
2872 }
2873}
Linux 6.x block layer and io_uring tree(s)