Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Implementation of transmit path. | |
19 | */ | |
20 | ||
21 | #include "core.h" | |
22 | ||
23 | #define BITS_PER_BYTE 8 | |
24 | #define OFDM_PLCP_BITS 22 | |
25 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
26 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
27 | #define L_STF 8 | |
28 | #define L_LTF 8 | |
29 | #define L_SIG 4 | |
30 | #define HT_SIG 8 | |
31 | #define HT_STF 4 | |
32 | #define HT_LTF(_ns) (4 * (_ns)) | |
33 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
34 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
35 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
36 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
37 | ||
38 | #define OFDM_SIFS_TIME 16 | |
39 | ||
40 | static u32 bits_per_symbol[][2] = { | |
41 | /* 20MHz 40MHz */ | |
42 | { 26, 54 }, /* 0: BPSK */ | |
43 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
44 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
45 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
46 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
47 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
48 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
49 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
50 | { 52, 108 }, /* 8: BPSK */ | |
51 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
52 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
53 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
54 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
55 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
56 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
57 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
58 | }; | |
59 | ||
60 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
61 | ||
f078f209 LR |
62 | /* |
63 | * Insert a chain of ath_buf (descriptors) on a txq and | |
64 | * assume the descriptors are already chained together by caller. | |
65 | * NB: must be called with txq lock held | |
66 | */ | |
67 | ||
68 | static void ath_tx_txqaddbuf(struct ath_softc *sc, | |
69 | struct ath_txq *txq, struct list_head *head) | |
70 | { | |
71 | struct ath_hal *ah = sc->sc_ah; | |
72 | struct ath_buf *bf; | |
73 | /* | |
74 | * Insert the frame on the outbound list and | |
75 | * pass it on to the hardware. | |
76 | */ | |
77 | ||
78 | if (list_empty(head)) | |
79 | return; | |
80 | ||
81 | bf = list_first_entry(head, struct ath_buf, list); | |
82 | ||
83 | list_splice_tail_init(head, &txq->axq_q); | |
84 | txq->axq_depth++; | |
85 | txq->axq_totalqueued++; | |
86 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
87 | ||
88 | DPRINTF(sc, ATH_DBG_QUEUE, | |
89 | "%s: txq depth = %d\n", __func__, txq->axq_depth); | |
90 | ||
91 | if (txq->axq_link == NULL) { | |
92 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
93 | DPRINTF(sc, ATH_DBG_XMIT, | |
94 | "%s: TXDP[%u] = %llx (%p)\n", | |
95 | __func__, txq->axq_qnum, | |
96 | ito64(bf->bf_daddr), bf->bf_desc); | |
97 | } else { | |
98 | *txq->axq_link = bf->bf_daddr; | |
99 | DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n", | |
100 | __func__, | |
101 | txq->axq_qnum, txq->axq_link, | |
102 | ito64(bf->bf_daddr), bf->bf_desc); | |
103 | } | |
104 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
105 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
106 | } | |
107 | ||
108 | /* Get transmit rate index using rate in Kbps */ | |
109 | ||
110 | static int ath_tx_findindex(const struct ath9k_rate_table *rt, int rate) | |
111 | { | |
112 | int i; | |
113 | int ndx = 0; | |
114 | ||
115 | for (i = 0; i < rt->rateCount; i++) { | |
116 | if (rt->info[i].rateKbps == rate) { | |
117 | ndx = i; | |
118 | break; | |
119 | } | |
120 | } | |
121 | ||
122 | return ndx; | |
123 | } | |
124 | ||
125 | /* Check if it's okay to send out aggregates */ | |
126 | ||
127 | static int ath_aggr_query(struct ath_softc *sc, | |
128 | struct ath_node *an, u8 tidno) | |
129 | { | |
130 | struct ath_atx_tid *tid; | |
131 | tid = ATH_AN_2_TID(an, tidno); | |
132 | ||
133 | if (tid->addba_exchangecomplete || tid->addba_exchangeinprogress) | |
134 | return 1; | |
135 | else | |
136 | return 0; | |
137 | } | |
138 | ||
139 | static enum ath9k_pkt_type get_hal_packet_type(struct ieee80211_hdr *hdr) | |
140 | { | |
141 | enum ath9k_pkt_type htype; | |
142 | __le16 fc; | |
143 | ||
144 | fc = hdr->frame_control; | |
145 | ||
146 | /* Calculate Atheros packet type from IEEE80211 packet header */ | |
147 | ||
148 | if (ieee80211_is_beacon(fc)) | |
149 | htype = ATH9K_PKT_TYPE_BEACON; | |
150 | else if (ieee80211_is_probe_resp(fc)) | |
151 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
152 | else if (ieee80211_is_atim(fc)) | |
153 | htype = ATH9K_PKT_TYPE_ATIM; | |
154 | else if (ieee80211_is_pspoll(fc)) | |
155 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
156 | else | |
157 | htype = ATH9K_PKT_TYPE_NORMAL; | |
158 | ||
159 | return htype; | |
160 | } | |
161 | ||
162 | static void fill_min_rates(struct sk_buff *skb, struct ath_tx_control *txctl) | |
163 | { | |
164 | struct ieee80211_hdr *hdr; | |
165 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
166 | struct ath_tx_info_priv *tx_info_priv; | |
167 | __le16 fc; | |
168 | ||
169 | hdr = (struct ieee80211_hdr *)skb->data; | |
170 | fc = hdr->frame_control; | |
e6a9854b JB |
171 | |
172 | /* XXX: HACK! */ | |
173 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; | |
f078f209 LR |
174 | |
175 | if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc)) { | |
176 | txctl->use_minrate = 1; | |
177 | txctl->min_rate = tx_info_priv->min_rate; | |
178 | } else if (ieee80211_is_data(fc)) { | |
179 | if (ieee80211_is_nullfunc(fc) || | |
4c244298 LR |
180 | /* Port Access Entity (IEEE 802.1X) */ |
181 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
f078f209 LR |
182 | txctl->use_minrate = 1; |
183 | txctl->min_rate = tx_info_priv->min_rate; | |
184 | } | |
185 | if (is_multicast_ether_addr(hdr->addr1)) | |
186 | txctl->mcast_rate = tx_info_priv->min_rate; | |
187 | } | |
188 | ||
189 | } | |
190 | ||
191 | /* This function will setup additional txctl information, mostly rate stuff */ | |
192 | /* FIXME: seqno, ps */ | |
193 | static int ath_tx_prepare(struct ath_softc *sc, | |
194 | struct sk_buff *skb, | |
195 | struct ath_tx_control *txctl) | |
196 | { | |
197 | struct ieee80211_hw *hw = sc->hw; | |
198 | struct ieee80211_hdr *hdr; | |
199 | struct ath_rc_series *rcs; | |
200 | struct ath_txq *txq = NULL; | |
201 | const struct ath9k_rate_table *rt; | |
202 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
203 | struct ath_tx_info_priv *tx_info_priv; | |
204 | int hdrlen; | |
205 | u8 rix, antenna; | |
206 | __le16 fc; | |
207 | u8 *qc; | |
208 | ||
f078f209 LR |
209 | txctl->dev = sc; |
210 | hdr = (struct ieee80211_hdr *)skb->data; | |
211 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
212 | fc = hdr->frame_control; | |
213 | ||
214 | rt = sc->sc_currates; | |
215 | BUG_ON(!rt); | |
216 | ||
f078f209 LR |
217 | if (ieee80211_is_data_qos(fc)) { |
218 | qc = ieee80211_get_qos_ctl(hdr); | |
219 | txctl->tidno = qc[0] & 0xf; | |
220 | } | |
221 | ||
222 | txctl->if_id = 0; | |
f078f209 | 223 | txctl->frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
5c020dc6 LR |
224 | |
225 | /* Always try at highest power possible unless the the device | |
226 | * was configured by the user to use another power. */ | |
227 | if (likely(sc->sc_config.txpowlimit == ATH_TXPOWER_MAX)) | |
228 | txctl->txpower = ATH_TXPOWER_MAX; | |
229 | else | |
230 | txctl->txpower = sc->sc_config.txpowlimit; | |
f078f209 LR |
231 | |
232 | /* Fill Key related fields */ | |
233 | ||
234 | txctl->keytype = ATH9K_KEY_TYPE_CLEAR; | |
235 | txctl->keyix = ATH9K_TXKEYIX_INVALID; | |
236 | ||
237 | if (tx_info->control.hw_key) { | |
238 | txctl->keyix = tx_info->control.hw_key->hw_key_idx; | |
76708dee | 239 | txctl->frmlen += tx_info->control.hw_key->icv_len; |
f078f209 | 240 | |
d0be7cc7 | 241 | if (tx_info->control.hw_key->alg == ALG_WEP) |
f078f209 | 242 | txctl->keytype = ATH9K_KEY_TYPE_WEP; |
d0be7cc7 | 243 | else if (tx_info->control.hw_key->alg == ALG_TKIP) |
f078f209 | 244 | txctl->keytype = ATH9K_KEY_TYPE_TKIP; |
d0be7cc7 | 245 | else if (tx_info->control.hw_key->alg == ALG_CCMP) |
f078f209 LR |
246 | txctl->keytype = ATH9K_KEY_TYPE_AES; |
247 | } | |
248 | ||
249 | /* Fill packet type */ | |
250 | ||
251 | txctl->atype = get_hal_packet_type(hdr); | |
252 | ||
253 | /* Fill qnum */ | |
254 | ||
e022edbd JM |
255 | if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) { |
256 | txctl->qnum = 0; | |
257 | txq = sc->sc_cabq; | |
258 | } else { | |
259 | txctl->qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); | |
260 | txq = &sc->sc_txq[txctl->qnum]; | |
261 | } | |
f078f209 LR |
262 | spin_lock_bh(&txq->axq_lock); |
263 | ||
264 | /* Try to avoid running out of descriptors */ | |
e022edbd JM |
265 | if (txq->axq_depth >= (ATH_TXBUF - 20) && |
266 | !(txctl->flags & ATH9K_TXDESC_CAB)) { | |
f078f209 LR |
267 | DPRINTF(sc, ATH_DBG_FATAL, |
268 | "%s: TX queue: %d is full, depth: %d\n", | |
269 | __func__, | |
270 | txctl->qnum, | |
271 | txq->axq_depth); | |
272 | ieee80211_stop_queue(hw, skb_get_queue_mapping(skb)); | |
273 | txq->stopped = 1; | |
274 | spin_unlock_bh(&txq->axq_lock); | |
275 | return -1; | |
276 | } | |
277 | ||
278 | spin_unlock_bh(&txq->axq_lock); | |
279 | ||
280 | /* Fill rate */ | |
281 | ||
282 | fill_min_rates(skb, txctl); | |
283 | ||
284 | /* Fill flags */ | |
285 | ||
b139a10a LR |
286 | txctl->flags |= ATH9K_TXDESC_CLRDMASK /* needed for crypto errors */ |
287 | | ATH9K_TXDESC_INTREQ; /* Generate an interrupt */ | |
f078f209 LR |
288 | |
289 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
b14ecdd0 | 290 | txctl->flags |= ATH9K_TXDESC_NOACK; |
e6a9854b JB |
291 | |
292 | if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
b14ecdd0 | 293 | txctl->flags |= ATH9K_TXDESC_RTSENA; |
f078f209 LR |
294 | |
295 | /* | |
296 | * Setup for rate calculations. | |
297 | */ | |
e6a9854b JB |
298 | |
299 | /* XXX: HACK! */ | |
300 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; | |
f078f209 LR |
301 | rcs = tx_info_priv->rcs; |
302 | ||
303 | if (ieee80211_is_data(fc) && !txctl->use_minrate) { | |
304 | ||
305 | /* Enable HT only for DATA frames and not for EAPOL */ | |
ae5eb026 JB |
306 | /* XXX why AMPDU only?? */ |
307 | txctl->ht = (hw->conf.ht.enabled && | |
f078f209 LR |
308 | (tx_info->flags & IEEE80211_TX_CTL_AMPDU)); |
309 | ||
310 | if (is_multicast_ether_addr(hdr->addr1)) { | |
311 | rcs[0].rix = (u8) | |
312 | ath_tx_findindex(rt, txctl->mcast_rate); | |
313 | ||
314 | /* | |
315 | * mcast packets are not re-tried. | |
316 | */ | |
317 | rcs[0].tries = 1; | |
318 | } | |
319 | /* For HT capable stations, we save tidno for later use. | |
320 | * We also override seqno set by upper layer with the one | |
321 | * in tx aggregation state. | |
322 | * | |
323 | * First, the fragmentation stat is determined. | |
324 | * If fragmentation is on, the sequence number is | |
325 | * not overridden, since it has been | |
326 | * incremented by the fragmentation routine. | |
327 | */ | |
328 | if (likely(!(txctl->flags & ATH9K_TXDESC_FRAG_IS_ON)) && | |
672840ac | 329 | txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) { |
f078f209 LR |
330 | struct ath_atx_tid *tid; |
331 | ||
332 | tid = ATH_AN_2_TID(txctl->an, txctl->tidno); | |
333 | ||
334 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
335 | IEEE80211_SEQ_SEQ_SHIFT); | |
336 | txctl->seqno = tid->seq_next; | |
337 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
338 | } | |
339 | } else { | |
340 | /* for management and control frames, | |
341 | * or for NULL and EAPOL frames */ | |
342 | if (txctl->min_rate) | |
343 | rcs[0].rix = ath_rate_findrateix(sc, txctl->min_rate); | |
344 | else | |
86b89eed | 345 | rcs[0].rix = 0; |
f078f209 LR |
346 | rcs[0].tries = ATH_MGT_TXMAXTRY; |
347 | } | |
348 | rix = rcs[0].rix; | |
349 | ||
14cc709f S |
350 | if (ieee80211_has_morefrags(fc) || |
351 | (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) { | |
f078f209 | 352 | /* |
14cc709f S |
353 | ** Force hardware to use computed duration for next |
354 | ** fragment by disabling multi-rate retry, which | |
355 | ** updates duration based on the multi-rate | |
356 | ** duration table. | |
357 | */ | |
358 | rcs[1].tries = rcs[2].tries = rcs[3].tries = 0; | |
359 | rcs[1].rix = rcs[2].rix = rcs[3].rix = 0; | |
360 | /* reset tries but keep rate index */ | |
361 | rcs[0].tries = ATH_TXMAXTRY; | |
f078f209 LR |
362 | } |
363 | ||
f078f209 LR |
364 | if (is_multicast_ether_addr(hdr->addr1)) { |
365 | antenna = sc->sc_mcastantenna + 1; | |
366 | sc->sc_mcastantenna = (sc->sc_mcastantenna + 1) & 0x1; | |
98deeea0 | 367 | } |
f078f209 | 368 | |
f078f209 LR |
369 | return 0; |
370 | } | |
371 | ||
372 | /* To complete a chain of buffers associated a frame */ | |
373 | ||
374 | static void ath_tx_complete_buf(struct ath_softc *sc, | |
375 | struct ath_buf *bf, | |
376 | struct list_head *bf_q, | |
377 | int txok, int sendbar) | |
378 | { | |
379 | struct sk_buff *skb = bf->bf_mpdu; | |
380 | struct ath_xmit_status tx_status; | |
f078f209 LR |
381 | |
382 | /* | |
383 | * Set retry information. | |
384 | * NB: Don't use the information in the descriptor, because the frame | |
385 | * could be software retried. | |
386 | */ | |
387 | tx_status.retries = bf->bf_retries; | |
388 | tx_status.flags = 0; | |
389 | ||
390 | if (sendbar) | |
391 | tx_status.flags = ATH_TX_BAR; | |
392 | ||
393 | if (!txok) { | |
394 | tx_status.flags |= ATH_TX_ERROR; | |
395 | ||
cd3d39a6 | 396 | if (bf_isxretried(bf)) |
f078f209 LR |
397 | tx_status.flags |= ATH_TX_XRETRY; |
398 | } | |
399 | /* Unmap this frame */ | |
f078f209 | 400 | pci_unmap_single(sc->pdev, |
ff9b662d | 401 | bf->bf_dmacontext, |
f078f209 LR |
402 | skb->len, |
403 | PCI_DMA_TODEVICE); | |
404 | /* complete this frame */ | |
405 | ath_tx_complete(sc, skb, &tx_status, bf->bf_node); | |
406 | ||
407 | /* | |
408 | * Return the list of ath_buf of this mpdu to free queue | |
409 | */ | |
410 | spin_lock_bh(&sc->sc_txbuflock); | |
411 | list_splice_tail_init(bf_q, &sc->sc_txbuf); | |
412 | spin_unlock_bh(&sc->sc_txbuflock); | |
413 | } | |
414 | ||
415 | /* | |
416 | * queue up a dest/ac pair for tx scheduling | |
417 | * NB: must be called with txq lock held | |
418 | */ | |
419 | ||
420 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) | |
421 | { | |
422 | struct ath_atx_ac *ac = tid->ac; | |
423 | ||
424 | /* | |
425 | * if tid is paused, hold off | |
426 | */ | |
427 | if (tid->paused) | |
428 | return; | |
429 | ||
430 | /* | |
431 | * add tid to ac atmost once | |
432 | */ | |
433 | if (tid->sched) | |
434 | return; | |
435 | ||
436 | tid->sched = true; | |
437 | list_add_tail(&tid->list, &ac->tid_q); | |
438 | ||
439 | /* | |
440 | * add node ac to txq atmost once | |
441 | */ | |
442 | if (ac->sched) | |
443 | return; | |
444 | ||
445 | ac->sched = true; | |
446 | list_add_tail(&ac->list, &txq->axq_acq); | |
447 | } | |
448 | ||
449 | /* pause a tid */ | |
450 | ||
451 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | |
452 | { | |
453 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | |
454 | ||
455 | spin_lock_bh(&txq->axq_lock); | |
456 | ||
457 | tid->paused++; | |
458 | ||
459 | spin_unlock_bh(&txq->axq_lock); | |
460 | } | |
461 | ||
462 | /* resume a tid and schedule aggregate */ | |
463 | ||
464 | void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | |
465 | { | |
466 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | |
467 | ||
468 | ASSERT(tid->paused > 0); | |
469 | spin_lock_bh(&txq->axq_lock); | |
470 | ||
471 | tid->paused--; | |
472 | ||
473 | if (tid->paused > 0) | |
474 | goto unlock; | |
475 | ||
476 | if (list_empty(&tid->buf_q)) | |
477 | goto unlock; | |
478 | ||
479 | /* | |
480 | * Add this TID to scheduler and try to send out aggregates | |
481 | */ | |
482 | ath_tx_queue_tid(txq, tid); | |
483 | ath_txq_schedule(sc, txq); | |
484 | unlock: | |
485 | spin_unlock_bh(&txq->axq_lock); | |
486 | } | |
487 | ||
488 | /* Compute the number of bad frames */ | |
489 | ||
b5aa9bf9 S |
490 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
491 | int txok) | |
f078f209 | 492 | { |
f078f209 LR |
493 | struct ath_buf *bf_last = bf->bf_lastbf; |
494 | struct ath_desc *ds = bf_last->bf_desc; | |
495 | u16 seq_st = 0; | |
496 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
497 | int ba_index; | |
498 | int nbad = 0; | |
499 | int isaggr = 0; | |
500 | ||
b5aa9bf9 | 501 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
f078f209 LR |
502 | return 0; |
503 | ||
cd3d39a6 | 504 | isaggr = bf_isaggr(bf); |
f078f209 LR |
505 | if (isaggr) { |
506 | seq_st = ATH_DS_BA_SEQ(ds); | |
507 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
508 | } | |
509 | ||
510 | while (bf) { | |
511 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
512 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
513 | nbad++; | |
514 | ||
515 | bf = bf->bf_next; | |
516 | } | |
517 | ||
518 | return nbad; | |
519 | } | |
520 | ||
521 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) | |
522 | { | |
523 | struct sk_buff *skb; | |
524 | struct ieee80211_hdr *hdr; | |
525 | ||
cd3d39a6 | 526 | bf->bf_state.bf_type |= BUF_RETRY; |
f078f209 LR |
527 | bf->bf_retries++; |
528 | ||
529 | skb = bf->bf_mpdu; | |
530 | hdr = (struct ieee80211_hdr *)skb->data; | |
531 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
532 | } | |
533 | ||
534 | /* Update block ack window */ | |
535 | ||
536 | static void ath_tx_update_baw(struct ath_softc *sc, | |
537 | struct ath_atx_tid *tid, int seqno) | |
538 | { | |
539 | int index, cindex; | |
540 | ||
541 | index = ATH_BA_INDEX(tid->seq_start, seqno); | |
542 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
543 | ||
544 | tid->tx_buf[cindex] = NULL; | |
545 | ||
546 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { | |
547 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
548 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
549 | } | |
550 | } | |
551 | ||
552 | /* | |
553 | * ath_pkt_dur - compute packet duration (NB: not NAV) | |
554 | * | |
555 | * rix - rate index | |
556 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
557 | * width - 0 for 20 MHz, 1 for 40 MHz | |
558 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
559 | */ | |
560 | ||
561 | static u32 ath_pkt_duration(struct ath_softc *sc, | |
562 | u8 rix, | |
563 | struct ath_buf *bf, | |
564 | int width, | |
565 | int half_gi, | |
566 | bool shortPreamble) | |
567 | { | |
568 | const struct ath9k_rate_table *rt = sc->sc_currates; | |
569 | u32 nbits, nsymbits, duration, nsymbols; | |
570 | u8 rc; | |
571 | int streams, pktlen; | |
572 | ||
cd3d39a6 | 573 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; |
f078f209 LR |
574 | rc = rt->info[rix].rateCode; |
575 | ||
576 | /* | |
577 | * for legacy rates, use old function to compute packet duration | |
578 | */ | |
579 | if (!IS_HT_RATE(rc)) | |
580 | return ath9k_hw_computetxtime(sc->sc_ah, | |
581 | rt, | |
582 | pktlen, | |
583 | rix, | |
584 | shortPreamble); | |
585 | /* | |
586 | * find number of symbols: PLCP + data | |
587 | */ | |
588 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
589 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
590 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
591 | ||
592 | if (!half_gi) | |
593 | duration = SYMBOL_TIME(nsymbols); | |
594 | else | |
595 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
596 | ||
597 | /* | |
598 | * addup duration for legacy/ht training and signal fields | |
599 | */ | |
600 | streams = HT_RC_2_STREAMS(rc); | |
601 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
602 | return duration; | |
603 | } | |
604 | ||
605 | /* Rate module function to set rate related fields in tx descriptor */ | |
606 | ||
607 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
608 | { | |
609 | struct ath_hal *ah = sc->sc_ah; | |
610 | const struct ath9k_rate_table *rt; | |
611 | struct ath_desc *ds = bf->bf_desc; | |
612 | struct ath_desc *lastds = bf->bf_lastbf->bf_desc; | |
613 | struct ath9k_11n_rate_series series[4]; | |
614 | int i, flags, rtsctsena = 0, dynamic_mimops = 0; | |
615 | u32 ctsduration = 0; | |
616 | u8 rix = 0, cix, ctsrate = 0; | |
98deeea0 | 617 | u32 aggr_limit_with_rts = ah->ah_caps.rts_aggr_limit; |
f078f209 LR |
618 | struct ath_node *an = (struct ath_node *) bf->bf_node; |
619 | ||
620 | /* | |
621 | * get the cix for the lowest valid rix. | |
622 | */ | |
623 | rt = sc->sc_currates; | |
624 | for (i = 4; i--;) { | |
625 | if (bf->bf_rcs[i].tries) { | |
626 | rix = bf->bf_rcs[i].rix; | |
627 | break; | |
628 | } | |
629 | } | |
630 | flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)); | |
631 | cix = rt->info[rix].controlRate; | |
632 | ||
633 | /* | |
634 | * If 802.11g protection is enabled, determine whether | |
635 | * to use RTS/CTS or just CTS. Note that this is only | |
636 | * done for OFDM/HT unicast frames. | |
637 | */ | |
638 | if (sc->sc_protmode != PROT_M_NONE && | |
639 | (rt->info[rix].phy == PHY_OFDM || | |
640 | rt->info[rix].phy == PHY_HT) && | |
641 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | |
642 | if (sc->sc_protmode == PROT_M_RTSCTS) | |
643 | flags = ATH9K_TXDESC_RTSENA; | |
644 | else if (sc->sc_protmode == PROT_M_CTSONLY) | |
645 | flags = ATH9K_TXDESC_CTSENA; | |
646 | ||
647 | cix = rt->info[sc->sc_protrix].controlRate; | |
648 | rtsctsena = 1; | |
649 | } | |
650 | ||
651 | /* For 11n, the default behavior is to enable RTS for | |
652 | * hw retried frames. We enable the global flag here and | |
653 | * let rate series flags determine which rates will actually | |
654 | * use RTS. | |
655 | */ | |
cd3d39a6 | 656 | if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) { |
f078f209 LR |
657 | BUG_ON(!an); |
658 | /* | |
659 | * 802.11g protection not needed, use our default behavior | |
660 | */ | |
661 | if (!rtsctsena) | |
662 | flags = ATH9K_TXDESC_RTSENA; | |
663 | /* | |
664 | * For dynamic MIMO PS, RTS needs to precede the first aggregate | |
665 | * and the second aggregate should have any protection at all. | |
666 | */ | |
667 | if (an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) { | |
cd3d39a6 | 668 | if (!bf_isaggrburst(bf)) { |
f078f209 LR |
669 | flags = ATH9K_TXDESC_RTSENA; |
670 | dynamic_mimops = 1; | |
671 | } else { | |
672 | flags = 0; | |
673 | } | |
674 | } | |
675 | } | |
676 | ||
677 | /* | |
678 | * Set protection if aggregate protection on | |
679 | */ | |
680 | if (sc->sc_config.ath_aggr_prot && | |
cd3d39a6 | 681 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
f078f209 LR |
682 | flags = ATH9K_TXDESC_RTSENA; |
683 | cix = rt->info[sc->sc_protrix].controlRate; | |
684 | rtsctsena = 1; | |
685 | } | |
686 | ||
687 | /* | |
688 | * For AR5416 - RTS cannot be followed by a frame larger than 8K. | |
689 | */ | |
cd3d39a6 | 690 | if (bf_isaggr(bf) && (bf->bf_al > aggr_limit_with_rts)) { |
f078f209 LR |
691 | /* |
692 | * Ensure that in the case of SM Dynamic power save | |
693 | * while we are bursting the second aggregate the | |
694 | * RTS is cleared. | |
695 | */ | |
696 | flags &= ~(ATH9K_TXDESC_RTSENA); | |
697 | } | |
698 | ||
699 | /* | |
700 | * CTS transmit rate is derived from the transmit rate | |
701 | * by looking in the h/w rate table. We must also factor | |
702 | * in whether or not a short preamble is to be used. | |
703 | */ | |
704 | /* NB: cix is set above where RTS/CTS is enabled */ | |
705 | BUG_ON(cix == 0xff); | |
706 | ctsrate = rt->info[cix].rateCode | | |
cd3d39a6 | 707 | (bf_isshpreamble(bf) ? rt->info[cix].shortPreamble : 0); |
f078f209 LR |
708 | |
709 | /* | |
710 | * Setup HAL rate series | |
711 | */ | |
0345f37b | 712 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); |
f078f209 LR |
713 | |
714 | for (i = 0; i < 4; i++) { | |
715 | if (!bf->bf_rcs[i].tries) | |
716 | continue; | |
717 | ||
718 | rix = bf->bf_rcs[i].rix; | |
719 | ||
720 | series[i].Rate = rt->info[rix].rateCode | | |
cd3d39a6 | 721 | (bf_isshpreamble(bf) ? rt->info[rix].shortPreamble : 0); |
f078f209 LR |
722 | |
723 | series[i].Tries = bf->bf_rcs[i].tries; | |
724 | ||
725 | series[i].RateFlags = ( | |
726 | (bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ? | |
727 | ATH9K_RATESERIES_RTS_CTS : 0) | | |
728 | ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ? | |
729 | ATH9K_RATESERIES_2040 : 0) | | |
730 | ((bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG) ? | |
731 | ATH9K_RATESERIES_HALFGI : 0); | |
732 | ||
733 | series[i].PktDuration = ath_pkt_duration( | |
734 | sc, rix, bf, | |
735 | (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0, | |
736 | (bf->bf_rcs[i].flags & ATH_RC_SGI_FLAG), | |
cd3d39a6 | 737 | bf_isshpreamble(bf)); |
f078f209 LR |
738 | |
739 | if ((an->an_smmode == ATH_SM_PWRSAV_STATIC) && | |
740 | (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG) == 0) { | |
741 | /* | |
742 | * When sending to an HT node that has enabled static | |
743 | * SM/MIMO power save, send at single stream rates but | |
744 | * use maximum allowed transmit chains per user, | |
745 | * hardware, regulatory, or country limits for | |
746 | * better range. | |
747 | */ | |
748 | series[i].ChSel = sc->sc_tx_chainmask; | |
749 | } else { | |
cd3d39a6 | 750 | if (bf_isht(bf)) |
f078f209 LR |
751 | series[i].ChSel = |
752 | ath_chainmask_sel_logic(sc, an); | |
753 | else | |
754 | series[i].ChSel = sc->sc_tx_chainmask; | |
755 | } | |
756 | ||
757 | if (rtsctsena) | |
758 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
759 | ||
760 | /* | |
761 | * Set RTS for all rates if node is in dynamic powersave | |
762 | * mode and we are using dual stream rates. | |
763 | */ | |
764 | if (dynamic_mimops && (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)) | |
765 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
766 | } | |
767 | ||
768 | /* | |
769 | * For non-HT devices, calculate RTS/CTS duration in software | |
770 | * and disable multi-rate retry. | |
771 | */ | |
60b67f51 | 772 | if (flags && !(ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)) { |
f078f209 LR |
773 | /* |
774 | * Compute the transmit duration based on the frame | |
775 | * size and the size of an ACK frame. We call into the | |
776 | * HAL to do the computation since it depends on the | |
777 | * characteristics of the actual PHY being used. | |
778 | * | |
779 | * NB: CTS is assumed the same size as an ACK so we can | |
780 | * use the precalculated ACK durations. | |
781 | */ | |
782 | if (flags & ATH9K_TXDESC_RTSENA) { /* SIFS + CTS */ | |
cd3d39a6 | 783 | ctsduration += bf_isshpreamble(bf) ? |
f078f209 LR |
784 | rt->info[cix].spAckDuration : |
785 | rt->info[cix].lpAckDuration; | |
786 | } | |
787 | ||
788 | ctsduration += series[0].PktDuration; | |
789 | ||
790 | if ((bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { /* SIFS + ACK */ | |
cd3d39a6 | 791 | ctsduration += bf_isshpreamble(bf) ? |
f078f209 LR |
792 | rt->info[rix].spAckDuration : |
793 | rt->info[rix].lpAckDuration; | |
794 | } | |
795 | ||
796 | /* | |
797 | * Disable multi-rate retry when using RTS/CTS by clearing | |
798 | * series 1, 2 and 3. | |
799 | */ | |
0345f37b | 800 | memset(&series[1], 0, sizeof(struct ath9k_11n_rate_series) * 3); |
f078f209 LR |
801 | } |
802 | ||
803 | /* | |
804 | * set dur_update_en for l-sig computation except for PS-Poll frames | |
805 | */ | |
806 | ath9k_hw_set11n_ratescenario(ah, ds, lastds, | |
cd3d39a6 S |
807 | !bf_ispspoll(bf), |
808 | ctsrate, | |
809 | ctsduration, | |
810 | series, 4, flags); | |
f078f209 LR |
811 | if (sc->sc_config.ath_aggr_prot && flags) |
812 | ath9k_hw_set11n_burstduration(ah, ds, 8192); | |
813 | } | |
814 | ||
815 | /* | |
816 | * Function to send a normal HT (non-AMPDU) frame | |
817 | * NB: must be called with txq lock held | |
818 | */ | |
819 | ||
820 | static int ath_tx_send_normal(struct ath_softc *sc, | |
821 | struct ath_txq *txq, | |
822 | struct ath_atx_tid *tid, | |
823 | struct list_head *bf_head) | |
824 | { | |
825 | struct ath_buf *bf; | |
826 | struct sk_buff *skb; | |
827 | struct ieee80211_tx_info *tx_info; | |
828 | struct ath_tx_info_priv *tx_info_priv; | |
829 | ||
830 | BUG_ON(list_empty(bf_head)); | |
831 | ||
832 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
cd3d39a6 | 833 | bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */ |
f078f209 LR |
834 | |
835 | skb = (struct sk_buff *)bf->bf_mpdu; | |
836 | tx_info = IEEE80211_SKB_CB(skb); | |
e6a9854b JB |
837 | |
838 | /* XXX: HACK! */ | |
839 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; | |
f078f209 LR |
840 | memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); |
841 | ||
842 | /* update starting sequence number for subsequent ADDBA request */ | |
843 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
844 | ||
845 | /* Queue to h/w without aggregation */ | |
846 | bf->bf_nframes = 1; | |
847 | bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */ | |
848 | ath_buf_set_rate(sc, bf); | |
849 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
854 | /* flush tid's software queue and send frames as non-ampdu's */ | |
855 | ||
856 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) | |
857 | { | |
858 | struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum]; | |
859 | struct ath_buf *bf; | |
860 | struct list_head bf_head; | |
861 | INIT_LIST_HEAD(&bf_head); | |
862 | ||
863 | ASSERT(tid->paused > 0); | |
864 | spin_lock_bh(&txq->axq_lock); | |
865 | ||
866 | tid->paused--; | |
867 | ||
868 | if (tid->paused > 0) { | |
869 | spin_unlock_bh(&txq->axq_lock); | |
870 | return; | |
871 | } | |
872 | ||
873 | while (!list_empty(&tid->buf_q)) { | |
874 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
cd3d39a6 | 875 | ASSERT(!bf_isretried(bf)); |
f078f209 LR |
876 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); |
877 | ath_tx_send_normal(sc, txq, tid, &bf_head); | |
878 | } | |
879 | ||
880 | spin_unlock_bh(&txq->axq_lock); | |
881 | } | |
882 | ||
883 | /* Completion routine of an aggregate */ | |
884 | ||
885 | static void ath_tx_complete_aggr_rifs(struct ath_softc *sc, | |
886 | struct ath_txq *txq, | |
887 | struct ath_buf *bf, | |
888 | struct list_head *bf_q, | |
889 | int txok) | |
890 | { | |
891 | struct ath_node *an = bf->bf_node; | |
892 | struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
893 | struct ath_buf *bf_last = bf->bf_lastbf; | |
894 | struct ath_desc *ds = bf_last->bf_desc; | |
895 | struct ath_buf *bf_next, *bf_lastq = NULL; | |
896 | struct list_head bf_head, bf_pending; | |
897 | u16 seq_st = 0; | |
898 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
899 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0; | |
f078f209 | 900 | |
cd3d39a6 | 901 | isaggr = bf_isaggr(bf); |
f078f209 LR |
902 | if (isaggr) { |
903 | if (txok) { | |
904 | if (ATH_DS_TX_BA(ds)) { | |
905 | /* | |
906 | * extract starting sequence and | |
907 | * block-ack bitmap | |
908 | */ | |
909 | seq_st = ATH_DS_BA_SEQ(ds); | |
910 | memcpy(ba, | |
911 | ATH_DS_BA_BITMAP(ds), | |
912 | WME_BA_BMP_SIZE >> 3); | |
913 | } else { | |
0345f37b | 914 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 LR |
915 | |
916 | /* | |
917 | * AR5416 can become deaf/mute when BA | |
918 | * issue happens. Chip needs to be reset. | |
919 | * But AP code may have sychronization issues | |
920 | * when perform internal reset in this routine. | |
921 | * Only enable reset in STA mode for now. | |
922 | */ | |
b4696c8b | 923 | if (sc->sc_ah->ah_opmode == ATH9K_M_STA) |
f078f209 LR |
924 | needreset = 1; |
925 | } | |
926 | } else { | |
0345f37b | 927 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 LR |
928 | } |
929 | } | |
930 | ||
931 | INIT_LIST_HEAD(&bf_pending); | |
932 | INIT_LIST_HEAD(&bf_head); | |
933 | ||
934 | while (bf) { | |
935 | txfail = txpending = 0; | |
936 | bf_next = bf->bf_next; | |
937 | ||
938 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { | |
939 | /* transmit completion, subframe is | |
940 | * acked by block ack */ | |
941 | } else if (!isaggr && txok) { | |
942 | /* transmit completion */ | |
943 | } else { | |
944 | ||
b5aa9bf9 | 945 | if (!tid->cleanup_inprogress && |
f078f209 LR |
946 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { |
947 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
948 | ath_tx_set_retry(sc, bf); | |
949 | txpending = 1; | |
950 | } else { | |
cd3d39a6 | 951 | bf->bf_state.bf_type |= BUF_XRETRY; |
f078f209 LR |
952 | txfail = 1; |
953 | sendbar = 1; | |
954 | } | |
955 | } else { | |
956 | /* | |
957 | * cleanup in progress, just fail | |
958 | * the un-acked sub-frames | |
959 | */ | |
960 | txfail = 1; | |
961 | } | |
962 | } | |
963 | /* | |
964 | * Remove ath_buf's of this sub-frame from aggregate queue. | |
965 | */ | |
966 | if (bf_next == NULL) { /* last subframe in the aggregate */ | |
967 | ASSERT(bf->bf_lastfrm == bf_last); | |
968 | ||
969 | /* | |
970 | * The last descriptor of the last sub frame could be | |
971 | * a holding descriptor for h/w. If that's the case, | |
972 | * bf->bf_lastfrm won't be in the bf_q. | |
973 | * Make sure we handle bf_q properly here. | |
974 | */ | |
975 | ||
976 | if (!list_empty(bf_q)) { | |
977 | bf_lastq = list_entry(bf_q->prev, | |
978 | struct ath_buf, list); | |
979 | list_cut_position(&bf_head, | |
980 | bf_q, &bf_lastq->list); | |
981 | } else { | |
982 | /* | |
983 | * XXX: if the last subframe only has one | |
984 | * descriptor which is also being used as | |
985 | * a holding descriptor. Then the ath_buf | |
986 | * is not in the bf_q at all. | |
987 | */ | |
988 | INIT_LIST_HEAD(&bf_head); | |
989 | } | |
990 | } else { | |
991 | ASSERT(!list_empty(bf_q)); | |
992 | list_cut_position(&bf_head, | |
993 | bf_q, &bf->bf_lastfrm->list); | |
994 | } | |
995 | ||
996 | if (!txpending) { | |
997 | /* | |
998 | * complete the acked-ones/xretried ones; update | |
999 | * block-ack window | |
1000 | */ | |
1001 | spin_lock_bh(&txq->axq_lock); | |
1002 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
1003 | spin_unlock_bh(&txq->axq_lock); | |
1004 | ||
1005 | /* complete this sub-frame */ | |
1006 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); | |
1007 | } else { | |
1008 | /* | |
1009 | * retry the un-acked ones | |
1010 | */ | |
1011 | /* | |
1012 | * XXX: if the last descriptor is holding descriptor, | |
1013 | * in order to requeue the frame to software queue, we | |
1014 | * need to allocate a new descriptor and | |
1015 | * copy the content of holding descriptor to it. | |
1016 | */ | |
1017 | if (bf->bf_next == NULL && | |
1018 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | |
1019 | struct ath_buf *tbf; | |
1020 | ||
1021 | /* allocate new descriptor */ | |
1022 | spin_lock_bh(&sc->sc_txbuflock); | |
1023 | ASSERT(!list_empty((&sc->sc_txbuf))); | |
1024 | tbf = list_first_entry(&sc->sc_txbuf, | |
1025 | struct ath_buf, list); | |
1026 | list_del(&tbf->list); | |
1027 | spin_unlock_bh(&sc->sc_txbuflock); | |
1028 | ||
1029 | ATH_TXBUF_RESET(tbf); | |
1030 | ||
1031 | /* copy descriptor content */ | |
1032 | tbf->bf_mpdu = bf_last->bf_mpdu; | |
1033 | tbf->bf_node = bf_last->bf_node; | |
1034 | tbf->bf_buf_addr = bf_last->bf_buf_addr; | |
1035 | *(tbf->bf_desc) = *(bf_last->bf_desc); | |
1036 | ||
1037 | /* link it to the frame */ | |
1038 | if (bf_lastq) { | |
1039 | bf_lastq->bf_desc->ds_link = | |
1040 | tbf->bf_daddr; | |
1041 | bf->bf_lastfrm = tbf; | |
1042 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
1043 | bf->bf_lastfrm->bf_desc); | |
1044 | } else { | |
1045 | tbf->bf_state = bf_last->bf_state; | |
1046 | tbf->bf_lastfrm = tbf; | |
1047 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
1048 | tbf->bf_lastfrm->bf_desc); | |
1049 | ||
1050 | /* copy the DMA context */ | |
ff9b662d S |
1051 | tbf->bf_dmacontext = |
1052 | bf_last->bf_dmacontext; | |
f078f209 LR |
1053 | } |
1054 | list_add_tail(&tbf->list, &bf_head); | |
1055 | } else { | |
1056 | /* | |
1057 | * Clear descriptor status words for | |
1058 | * software retry | |
1059 | */ | |
1060 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
ff9b662d | 1061 | bf->bf_lastfrm->bf_desc); |
f078f209 LR |
1062 | } |
1063 | ||
1064 | /* | |
1065 | * Put this buffer to the temporary pending | |
1066 | * queue to retain ordering | |
1067 | */ | |
1068 | list_splice_tail_init(&bf_head, &bf_pending); | |
1069 | } | |
1070 | ||
1071 | bf = bf_next; | |
1072 | } | |
1073 | ||
f078f209 LR |
1074 | if (tid->cleanup_inprogress) { |
1075 | /* check to see if we're done with cleaning the h/w queue */ | |
1076 | spin_lock_bh(&txq->axq_lock); | |
1077 | ||
1078 | if (tid->baw_head == tid->baw_tail) { | |
1079 | tid->addba_exchangecomplete = 0; | |
1080 | tid->addba_exchangeattempts = 0; | |
1081 | spin_unlock_bh(&txq->axq_lock); | |
1082 | ||
1083 | tid->cleanup_inprogress = false; | |
1084 | ||
1085 | /* send buffered frames as singles */ | |
1086 | ath_tx_flush_tid(sc, tid); | |
1087 | } else | |
1088 | spin_unlock_bh(&txq->axq_lock); | |
1089 | ||
1090 | return; | |
1091 | } | |
1092 | ||
1093 | /* | |
1094 | * prepend un-acked frames to the beginning of the pending frame queue | |
1095 | */ | |
1096 | if (!list_empty(&bf_pending)) { | |
1097 | spin_lock_bh(&txq->axq_lock); | |
1098 | /* Note: we _prepend_, we _do_not_ at to | |
1099 | * the end of the queue ! */ | |
1100 | list_splice(&bf_pending, &tid->buf_q); | |
1101 | ath_tx_queue_tid(txq, tid); | |
1102 | spin_unlock_bh(&txq->axq_lock); | |
1103 | } | |
1104 | ||
1105 | if (needreset) | |
f45144ef | 1106 | ath_reset(sc, false); |
f078f209 LR |
1107 | |
1108 | return; | |
1109 | } | |
1110 | ||
1111 | /* Process completed xmit descriptors from the specified queue */ | |
1112 | ||
1113 | static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) | |
1114 | { | |
1115 | struct ath_hal *ah = sc->sc_ah; | |
1116 | struct ath_buf *bf, *lastbf, *bf_held = NULL; | |
1117 | struct list_head bf_head; | |
1118 | struct ath_desc *ds, *tmp_ds; | |
1119 | struct sk_buff *skb; | |
1120 | struct ieee80211_tx_info *tx_info; | |
1121 | struct ath_tx_info_priv *tx_info_priv; | |
1122 | int nacked, txok, nbad = 0, isrifs = 0; | |
1123 | int status; | |
1124 | ||
1125 | DPRINTF(sc, ATH_DBG_QUEUE, | |
1126 | "%s: tx queue %d (%x), link %p\n", __func__, | |
1127 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1128 | txq->axq_link); | |
1129 | ||
1130 | nacked = 0; | |
1131 | for (;;) { | |
1132 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1133 | if (list_empty(&txq->axq_q)) { |
1134 | txq->axq_link = NULL; | |
1135 | txq->axq_linkbuf = NULL; | |
1136 | spin_unlock_bh(&txq->axq_lock); | |
1137 | break; | |
1138 | } | |
1139 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); | |
1140 | ||
1141 | /* | |
1142 | * There is a race condition that a BH gets scheduled | |
1143 | * after sw writes TxE and before hw re-load the last | |
1144 | * descriptor to get the newly chained one. | |
1145 | * Software must keep the last DONE descriptor as a | |
1146 | * holding descriptor - software does so by marking | |
1147 | * it with the STALE flag. | |
1148 | */ | |
1149 | bf_held = NULL; | |
1150 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | |
1151 | bf_held = bf; | |
1152 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
1153 | /* FIXME: | |
1154 | * The holding descriptor is the last | |
1155 | * descriptor in queue. It's safe to remove | |
1156 | * the last holding descriptor in BH context. | |
1157 | */ | |
1158 | spin_unlock_bh(&txq->axq_lock); | |
1159 | break; | |
1160 | } else { | |
1161 | /* Lets work with the next buffer now */ | |
1162 | bf = list_entry(bf_held->list.next, | |
1163 | struct ath_buf, list); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | lastbf = bf->bf_lastbf; | |
1168 | ds = lastbf->bf_desc; /* NB: last decriptor */ | |
1169 | ||
1170 | status = ath9k_hw_txprocdesc(ah, ds); | |
1171 | if (status == -EINPROGRESS) { | |
1172 | spin_unlock_bh(&txq->axq_lock); | |
1173 | break; | |
1174 | } | |
1175 | if (bf->bf_desc == txq->axq_lastdsWithCTS) | |
1176 | txq->axq_lastdsWithCTS = NULL; | |
1177 | if (ds == txq->axq_gatingds) | |
1178 | txq->axq_gatingds = NULL; | |
1179 | ||
1180 | /* | |
1181 | * Remove ath_buf's of the same transmit unit from txq, | |
1182 | * however leave the last descriptor back as the holding | |
1183 | * descriptor for hw. | |
1184 | */ | |
1185 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | |
1186 | INIT_LIST_HEAD(&bf_head); | |
1187 | ||
1188 | if (!list_is_singular(&lastbf->list)) | |
1189 | list_cut_position(&bf_head, | |
1190 | &txq->axq_q, lastbf->list.prev); | |
1191 | ||
1192 | txq->axq_depth--; | |
1193 | ||
cd3d39a6 | 1194 | if (bf_isaggr(bf)) |
f078f209 LR |
1195 | txq->axq_aggr_depth--; |
1196 | ||
1197 | txok = (ds->ds_txstat.ts_status == 0); | |
1198 | ||
1199 | spin_unlock_bh(&txq->axq_lock); | |
1200 | ||
1201 | if (bf_held) { | |
1202 | list_del(&bf_held->list); | |
1203 | spin_lock_bh(&sc->sc_txbuflock); | |
1204 | list_add_tail(&bf_held->list, &sc->sc_txbuf); | |
1205 | spin_unlock_bh(&sc->sc_txbuflock); | |
1206 | } | |
1207 | ||
cd3d39a6 | 1208 | if (!bf_isampdu(bf)) { |
f078f209 LR |
1209 | /* |
1210 | * This frame is sent out as a single frame. | |
1211 | * Use hardware retry status for this frame. | |
1212 | */ | |
1213 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
1214 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
cd3d39a6 | 1215 | bf->bf_state.bf_type |= BUF_XRETRY; |
f078f209 LR |
1216 | nbad = 0; |
1217 | } else { | |
1218 | nbad = ath_tx_num_badfrms(sc, bf, txok); | |
1219 | } | |
1220 | skb = bf->bf_mpdu; | |
1221 | tx_info = IEEE80211_SKB_CB(skb); | |
e6a9854b JB |
1222 | |
1223 | /* XXX: HACK! */ | |
1224 | tx_info_priv = (struct ath_tx_info_priv *) tx_info->control.vif; | |
f078f209 LR |
1225 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1226 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
1227 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && | |
1228 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | |
1229 | if (ds->ds_txstat.ts_status == 0) | |
1230 | nacked++; | |
1231 | ||
cd3d39a6 | 1232 | if (bf_isdata(bf)) { |
f078f209 LR |
1233 | if (isrifs) |
1234 | tmp_ds = bf->bf_rifslast->bf_desc; | |
1235 | else | |
1236 | tmp_ds = ds; | |
1237 | memcpy(&tx_info_priv->tx, | |
1238 | &tmp_ds->ds_txstat, | |
1239 | sizeof(tx_info_priv->tx)); | |
1240 | tx_info_priv->n_frames = bf->bf_nframes; | |
1241 | tx_info_priv->n_bad_frames = nbad; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | /* | |
1246 | * Complete this transmit unit | |
1247 | */ | |
cd3d39a6 | 1248 | if (bf_isampdu(bf)) |
f078f209 LR |
1249 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok); |
1250 | else | |
1251 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
1252 | ||
1253 | /* Wake up mac80211 queue */ | |
1254 | ||
1255 | spin_lock_bh(&txq->axq_lock); | |
1256 | if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <= | |
1257 | (ATH_TXBUF - 20)) { | |
1258 | int qnum; | |
1259 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); | |
1260 | if (qnum != -1) { | |
1261 | ieee80211_wake_queue(sc->hw, qnum); | |
1262 | txq->stopped = 0; | |
1263 | } | |
1264 | ||
1265 | } | |
1266 | ||
1267 | /* | |
1268 | * schedule any pending packets if aggregation is enabled | |
1269 | */ | |
672840ac | 1270 | if (sc->sc_flags & SC_OP_TXAGGR) |
f078f209 LR |
1271 | ath_txq_schedule(sc, txq); |
1272 | spin_unlock_bh(&txq->axq_lock); | |
1273 | } | |
1274 | return nacked; | |
1275 | } | |
1276 | ||
1277 | static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) | |
1278 | { | |
1279 | struct ath_hal *ah = sc->sc_ah; | |
1280 | ||
1281 | (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1282 | DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n", | |
1283 | __func__, txq->axq_qnum, | |
1284 | ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link); | |
1285 | } | |
1286 | ||
1287 | /* Drain only the data queues */ | |
1288 | ||
1289 | static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) | |
1290 | { | |
1291 | struct ath_hal *ah = sc->sc_ah; | |
1292 | int i; | |
1293 | int npend = 0; | |
f078f209 LR |
1294 | |
1295 | /* XXX return value */ | |
672840ac | 1296 | if (!(sc->sc_flags & SC_OP_INVALID)) { |
f078f209 LR |
1297 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
1298 | if (ATH_TXQ_SETUP(sc, i)) { | |
1299 | ath_tx_stopdma(sc, &sc->sc_txq[i]); | |
1300 | ||
1301 | /* The TxDMA may not really be stopped. | |
1302 | * Double check the hal tx pending count */ | |
1303 | npend += ath9k_hw_numtxpending(ah, | |
1304 | sc->sc_txq[i].axq_qnum); | |
1305 | } | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | if (npend) { | |
1310 | int status; | |
1311 | ||
1312 | /* TxDMA not stopped, reset the hal */ | |
1313 | DPRINTF(sc, ATH_DBG_XMIT, | |
1314 | "%s: Unable to stop TxDMA. Reset HAL!\n", __func__); | |
1315 | ||
1316 | spin_lock_bh(&sc->sc_resetlock); | |
b4696c8b | 1317 | if (!ath9k_hw_reset(ah, |
927e70e9 S |
1318 | sc->sc_ah->ah_curchan, |
1319 | sc->sc_ht_info.tx_chan_width, | |
1320 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, | |
1321 | sc->sc_ht_extprotspacing, true, &status)) { | |
f078f209 LR |
1322 | |
1323 | DPRINTF(sc, ATH_DBG_FATAL, | |
1324 | "%s: unable to reset hardware; hal status %u\n", | |
1325 | __func__, | |
1326 | status); | |
1327 | } | |
1328 | spin_unlock_bh(&sc->sc_resetlock); | |
1329 | } | |
1330 | ||
1331 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1332 | if (ATH_TXQ_SETUP(sc, i)) | |
1333 | ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx); | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | /* Add a sub-frame to block ack window */ | |
1338 | ||
1339 | static void ath_tx_addto_baw(struct ath_softc *sc, | |
1340 | struct ath_atx_tid *tid, | |
1341 | struct ath_buf *bf) | |
1342 | { | |
1343 | int index, cindex; | |
1344 | ||
cd3d39a6 | 1345 | if (bf_isretried(bf)) |
f078f209 LR |
1346 | return; |
1347 | ||
1348 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); | |
1349 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
1350 | ||
1351 | ASSERT(tid->tx_buf[cindex] == NULL); | |
1352 | tid->tx_buf[cindex] = bf; | |
1353 | ||
1354 | if (index >= ((tid->baw_tail - tid->baw_head) & | |
1355 | (ATH_TID_MAX_BUFS - 1))) { | |
1356 | tid->baw_tail = cindex; | |
1357 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
1358 | } | |
1359 | } | |
1360 | ||
1361 | /* | |
1362 | * Function to send an A-MPDU | |
1363 | * NB: must be called with txq lock held | |
1364 | */ | |
1365 | ||
1366 | static int ath_tx_send_ampdu(struct ath_softc *sc, | |
1367 | struct ath_txq *txq, | |
1368 | struct ath_atx_tid *tid, | |
1369 | struct list_head *bf_head, | |
1370 | struct ath_tx_control *txctl) | |
1371 | { | |
1372 | struct ath_buf *bf; | |
1373 | struct sk_buff *skb; | |
1374 | struct ieee80211_tx_info *tx_info; | |
1375 | struct ath_tx_info_priv *tx_info_priv; | |
1376 | ||
1377 | BUG_ON(list_empty(bf_head)); | |
1378 | ||
1379 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
cd3d39a6 | 1380 | bf->bf_state.bf_type |= BUF_AMPDU; |
f078f209 LR |
1381 | bf->bf_seqno = txctl->seqno; /* save seqno and tidno in buffer */ |
1382 | bf->bf_tidno = txctl->tidno; | |
1383 | ||
1384 | /* | |
1385 | * Do not queue to h/w when any of the following conditions is true: | |
1386 | * - there are pending frames in software queue | |
1387 | * - the TID is currently paused for ADDBA/BAR request | |
1388 | * - seqno is not within block-ack window | |
1389 | * - h/w queue depth exceeds low water mark | |
1390 | */ | |
1391 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1392 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1393 | txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
1394 | /* | |
1395 | * Add this frame to software queue for scheduling later | |
1396 | * for aggregation. | |
1397 | */ | |
1398 | list_splice_tail_init(bf_head, &tid->buf_q); | |
1399 | ath_tx_queue_tid(txq, tid); | |
1400 | return 0; | |
1401 | } | |
1402 | ||
1403 | skb = (struct sk_buff *)bf->bf_mpdu; | |
1404 | tx_info = IEEE80211_SKB_CB(skb); | |
e6a9854b JB |
1405 | /* XXX: HACK! */ |
1406 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; | |
f078f209 LR |
1407 | memcpy(bf->bf_rcs, tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); |
1408 | ||
1409 | /* Add sub-frame to BAW */ | |
1410 | ath_tx_addto_baw(sc, tid, bf); | |
1411 | ||
1412 | /* Queue to h/w without aggregation */ | |
1413 | bf->bf_nframes = 1; | |
1414 | bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */ | |
1415 | ath_buf_set_rate(sc, bf); | |
1416 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | /* | |
1421 | * looks up the rate | |
1422 | * returns aggr limit based on lowest of the rates | |
1423 | */ | |
1424 | ||
1425 | static u32 ath_lookup_rate(struct ath_softc *sc, | |
ae5eb026 JB |
1426 | struct ath_buf *bf, |
1427 | struct ath_atx_tid *tid) | |
f078f209 LR |
1428 | { |
1429 | const struct ath9k_rate_table *rt = sc->sc_currates; | |
1430 | struct sk_buff *skb; | |
1431 | struct ieee80211_tx_info *tx_info; | |
1432 | struct ath_tx_info_priv *tx_info_priv; | |
1433 | u32 max_4ms_framelen, frame_length; | |
1434 | u16 aggr_limit, legacy = 0, maxampdu; | |
1435 | int i; | |
1436 | ||
1437 | ||
1438 | skb = (struct sk_buff *)bf->bf_mpdu; | |
1439 | tx_info = IEEE80211_SKB_CB(skb); | |
1440 | tx_info_priv = (struct ath_tx_info_priv *) | |
e6a9854b | 1441 | tx_info->control.vif; /* XXX: HACK! */ |
f078f209 LR |
1442 | memcpy(bf->bf_rcs, |
1443 | tx_info_priv->rcs, 4 * sizeof(tx_info_priv->rcs[0])); | |
1444 | ||
1445 | /* | |
1446 | * Find the lowest frame length among the rate series that will have a | |
1447 | * 4ms transmit duration. | |
1448 | * TODO - TXOP limit needs to be considered. | |
1449 | */ | |
1450 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
1451 | ||
1452 | for (i = 0; i < 4; i++) { | |
1453 | if (bf->bf_rcs[i].tries) { | |
1454 | frame_length = bf->bf_rcs[i].max_4ms_framelen; | |
1455 | ||
1456 | if (rt->info[bf->bf_rcs[i].rix].phy != PHY_HT) { | |
1457 | legacy = 1; | |
1458 | break; | |
1459 | } | |
1460 | ||
1461 | max_4ms_framelen = min(max_4ms_framelen, frame_length); | |
1462 | } | |
1463 | } | |
1464 | ||
1465 | /* | |
1466 | * limit aggregate size by the minimum rate if rate selected is | |
1467 | * not a probe rate, if rate selected is a probe rate then | |
1468 | * avoid aggregation of this packet. | |
1469 | */ | |
1470 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) | |
1471 | return 0; | |
1472 | ||
1473 | aggr_limit = min(max_4ms_framelen, | |
1474 | (u32)ATH_AMPDU_LIMIT_DEFAULT); | |
1475 | ||
1476 | /* | |
1477 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
1478 | * The IE, however can hold upto 65536, which shows up here | |
1479 | * as zero. Ignore 65536 since we are constrained by hw. | |
1480 | */ | |
ae5eb026 | 1481 | maxampdu = tid->an->maxampdu; |
f078f209 LR |
1482 | if (maxampdu) |
1483 | aggr_limit = min(aggr_limit, maxampdu); | |
1484 | ||
1485 | return aggr_limit; | |
1486 | } | |
1487 | ||
1488 | /* | |
1489 | * returns the number of delimiters to be added to | |
1490 | * meet the minimum required mpdudensity. | |
1491 | * caller should make sure that the rate is HT rate . | |
1492 | */ | |
1493 | ||
1494 | static int ath_compute_num_delims(struct ath_softc *sc, | |
ae5eb026 | 1495 | struct ath_atx_tid *tid, |
f078f209 LR |
1496 | struct ath_buf *bf, |
1497 | u16 frmlen) | |
1498 | { | |
1499 | const struct ath9k_rate_table *rt = sc->sc_currates; | |
1500 | u32 nsymbits, nsymbols, mpdudensity; | |
1501 | u16 minlen; | |
1502 | u8 rc, flags, rix; | |
1503 | int width, half_gi, ndelim, mindelim; | |
1504 | ||
1505 | /* Select standard number of delimiters based on frame length alone */ | |
1506 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
1507 | ||
1508 | /* | |
1509 | * If encryption enabled, hardware requires some more padding between | |
1510 | * subframes. | |
1511 | * TODO - this could be improved to be dependent on the rate. | |
1512 | * The hardware can keep up at lower rates, but not higher rates | |
1513 | */ | |
1514 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) | |
1515 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
1516 | ||
1517 | /* | |
1518 | * Convert desired mpdu density from microeconds to bytes based | |
1519 | * on highest rate in rate series (i.e. first rate) to determine | |
1520 | * required minimum length for subframe. Take into account | |
1521 | * whether high rate is 20 or 40Mhz and half or full GI. | |
1522 | */ | |
ae5eb026 | 1523 | mpdudensity = tid->an->mpdudensity; |
f078f209 LR |
1524 | |
1525 | /* | |
1526 | * If there is no mpdu density restriction, no further calculation | |
1527 | * is needed. | |
1528 | */ | |
1529 | if (mpdudensity == 0) | |
1530 | return ndelim; | |
1531 | ||
1532 | rix = bf->bf_rcs[0].rix; | |
1533 | flags = bf->bf_rcs[0].flags; | |
1534 | rc = rt->info[rix].rateCode; | |
1535 | width = (flags & ATH_RC_CW40_FLAG) ? 1 : 0; | |
1536 | half_gi = (flags & ATH_RC_SGI_FLAG) ? 1 : 0; | |
1537 | ||
1538 | if (half_gi) | |
1539 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
1540 | else | |
1541 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
1542 | ||
1543 | if (nsymbols == 0) | |
1544 | nsymbols = 1; | |
1545 | ||
1546 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1547 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
1548 | ||
1549 | /* Is frame shorter than required minimum length? */ | |
1550 | if (frmlen < minlen) { | |
1551 | /* Get the minimum number of delimiters required. */ | |
1552 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; | |
1553 | ndelim = max(mindelim, ndelim); | |
1554 | } | |
1555 | ||
1556 | return ndelim; | |
1557 | } | |
1558 | ||
1559 | /* | |
1560 | * For aggregation from software buffer queue. | |
1561 | * NB: must be called with txq lock held | |
1562 | */ | |
1563 | ||
1564 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, | |
1565 | struct ath_atx_tid *tid, | |
1566 | struct list_head *bf_q, | |
1567 | struct ath_buf **bf_last, | |
1568 | struct aggr_rifs_param *param, | |
1569 | int *prev_frames) | |
1570 | { | |
1571 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) | |
1572 | struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL; | |
1573 | struct list_head bf_head; | |
1574 | int rl = 0, nframes = 0, ndelim; | |
1575 | u16 aggr_limit = 0, al = 0, bpad = 0, | |
1576 | al_delta, h_baw = tid->baw_size / 2; | |
1577 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
1578 | int prev_al = 0, is_ds_rate = 0; | |
1579 | INIT_LIST_HEAD(&bf_head); | |
1580 | ||
1581 | BUG_ON(list_empty(&tid->buf_q)); | |
1582 | ||
1583 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
1584 | ||
1585 | do { | |
1586 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
1587 | ||
1588 | /* | |
1589 | * do not step over block-ack window | |
1590 | */ | |
1591 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { | |
1592 | status = ATH_AGGR_BAW_CLOSED; | |
1593 | break; | |
1594 | } | |
1595 | ||
1596 | if (!rl) { | |
ae5eb026 | 1597 | aggr_limit = ath_lookup_rate(sc, bf, tid); |
f078f209 LR |
1598 | rl = 1; |
1599 | /* | |
1600 | * Is rate dual stream | |
1601 | */ | |
1602 | is_ds_rate = | |
1603 | (bf->bf_rcs[0].flags & ATH_RC_DS_FLAG) ? 1 : 0; | |
1604 | } | |
1605 | ||
1606 | /* | |
1607 | * do not exceed aggregation limit | |
1608 | */ | |
1609 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; | |
1610 | ||
1611 | if (nframes && (aggr_limit < | |
1612 | (al + bpad + al_delta + prev_al))) { | |
1613 | status = ATH_AGGR_LIMITED; | |
1614 | break; | |
1615 | } | |
1616 | ||
1617 | /* | |
1618 | * do not exceed subframe limit | |
1619 | */ | |
1620 | if ((nframes + *prev_frames) >= | |
1621 | min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
1622 | status = ATH_AGGR_LIMITED; | |
1623 | break; | |
1624 | } | |
1625 | ||
1626 | /* | |
1627 | * add padding for previous frame to aggregation length | |
1628 | */ | |
1629 | al += bpad + al_delta; | |
1630 | ||
1631 | /* | |
1632 | * Get the delimiters needed to meet the MPDU | |
1633 | * density for this node. | |
1634 | */ | |
ae5eb026 | 1635 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); |
f078f209 LR |
1636 | |
1637 | bpad = PADBYTES(al_delta) + (ndelim << 2); | |
1638 | ||
1639 | bf->bf_next = NULL; | |
1640 | bf->bf_lastfrm->bf_desc->ds_link = 0; | |
1641 | ||
1642 | /* | |
1643 | * this packet is part of an aggregate | |
1644 | * - remove all descriptors belonging to this frame from | |
1645 | * software queue | |
1646 | * - add it to block ack window | |
1647 | * - set up descriptors for aggregation | |
1648 | */ | |
1649 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | |
1650 | ath_tx_addto_baw(sc, tid, bf); | |
1651 | ||
1652 | list_for_each_entry(tbf, &bf_head, list) { | |
1653 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, | |
1654 | tbf->bf_desc, ndelim); | |
1655 | } | |
1656 | ||
1657 | /* | |
1658 | * link buffers of this frame to the aggregate | |
1659 | */ | |
1660 | list_splice_tail_init(&bf_head, bf_q); | |
1661 | nframes++; | |
1662 | ||
1663 | if (bf_prev) { | |
1664 | bf_prev->bf_next = bf; | |
1665 | bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr; | |
1666 | } | |
1667 | bf_prev = bf; | |
1668 | ||
1669 | #ifdef AGGR_NOSHORT | |
1670 | /* | |
1671 | * terminate aggregation on a small packet boundary | |
1672 | */ | |
1673 | if (bf->bf_frmlen < ATH_AGGR_MINPLEN) { | |
1674 | status = ATH_AGGR_SHORTPKT; | |
1675 | break; | |
1676 | } | |
1677 | #endif | |
1678 | } while (!list_empty(&tid->buf_q)); | |
1679 | ||
1680 | bf_first->bf_al = al; | |
1681 | bf_first->bf_nframes = nframes; | |
1682 | *bf_last = bf_prev; | |
1683 | return status; | |
1684 | #undef PADBYTES | |
1685 | } | |
1686 | ||
1687 | /* | |
1688 | * process pending frames possibly doing a-mpdu aggregation | |
1689 | * NB: must be called with txq lock held | |
1690 | */ | |
1691 | ||
1692 | static void ath_tx_sched_aggr(struct ath_softc *sc, | |
1693 | struct ath_txq *txq, struct ath_atx_tid *tid) | |
1694 | { | |
1695 | struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL; | |
1696 | enum ATH_AGGR_STATUS status; | |
1697 | struct list_head bf_q; | |
1698 | struct aggr_rifs_param param = {0, 0, 0, 0, NULL}; | |
1699 | int prev_frames = 0; | |
1700 | ||
1701 | do { | |
1702 | if (list_empty(&tid->buf_q)) | |
1703 | return; | |
1704 | ||
1705 | INIT_LIST_HEAD(&bf_q); | |
1706 | ||
1707 | status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m, | |
1708 | &prev_frames); | |
1709 | ||
1710 | /* | |
1711 | * no frames picked up to be aggregated; block-ack | |
1712 | * window is not open | |
1713 | */ | |
1714 | if (list_empty(&bf_q)) | |
1715 | break; | |
1716 | ||
1717 | bf = list_first_entry(&bf_q, struct ath_buf, list); | |
1718 | bf_last = list_entry(bf_q.prev, struct ath_buf, list); | |
1719 | bf->bf_lastbf = bf_last; | |
1720 | ||
1721 | /* | |
1722 | * if only one frame, send as non-aggregate | |
1723 | */ | |
1724 | if (bf->bf_nframes == 1) { | |
1725 | ASSERT(bf->bf_lastfrm == bf_last); | |
1726 | ||
cd3d39a6 | 1727 | bf->bf_state.bf_type &= ~BUF_AGGR; |
f078f209 LR |
1728 | /* |
1729 | * clear aggr bits for every descriptor | |
1730 | * XXX TODO: is there a way to optimize it? | |
1731 | */ | |
1732 | list_for_each_entry(tbf, &bf_q, list) { | |
1733 | ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc); | |
1734 | } | |
1735 | ||
1736 | ath_buf_set_rate(sc, bf); | |
1737 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
1738 | continue; | |
1739 | } | |
1740 | ||
1741 | /* | |
1742 | * setup first desc with rate and aggr info | |
1743 | */ | |
cd3d39a6 | 1744 | bf->bf_state.bf_type |= BUF_AGGR; |
f078f209 LR |
1745 | ath_buf_set_rate(sc, bf); |
1746 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
1747 | ||
1748 | /* | |
1749 | * anchor last frame of aggregate correctly | |
1750 | */ | |
1751 | ASSERT(bf_lastaggr); | |
1752 | ASSERT(bf_lastaggr->bf_lastfrm == bf_last); | |
1753 | tbf = bf_lastaggr; | |
1754 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | |
1755 | ||
1756 | /* XXX: We don't enter into this loop, consider removing this */ | |
1757 | while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) { | |
1758 | tbf = list_entry(tbf->list.next, struct ath_buf, list); | |
1759 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | |
1760 | } | |
1761 | ||
1762 | txq->axq_aggr_depth++; | |
1763 | ||
1764 | /* | |
1765 | * Normal aggregate, queue to hardware | |
1766 | */ | |
1767 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
1768 | ||
1769 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && | |
1770 | status != ATH_AGGR_BAW_CLOSED); | |
1771 | } | |
1772 | ||
1773 | /* Called with txq lock held */ | |
1774 | ||
1775 | static void ath_tid_drain(struct ath_softc *sc, | |
1776 | struct ath_txq *txq, | |
b5aa9bf9 S |
1777 | struct ath_atx_tid *tid) |
1778 | ||
f078f209 LR |
1779 | { |
1780 | struct ath_buf *bf; | |
1781 | struct list_head bf_head; | |
1782 | INIT_LIST_HEAD(&bf_head); | |
1783 | ||
1784 | for (;;) { | |
1785 | if (list_empty(&tid->buf_q)) | |
1786 | break; | |
1787 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
1788 | ||
1789 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | |
1790 | ||
1791 | /* update baw for software retried frame */ | |
cd3d39a6 | 1792 | if (bf_isretried(bf)) |
f078f209 LR |
1793 | ath_tx_update_baw(sc, tid, bf->bf_seqno); |
1794 | ||
1795 | /* | |
1796 | * do not indicate packets while holding txq spinlock. | |
1797 | * unlock is intentional here | |
1798 | */ | |
b5aa9bf9 | 1799 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
1800 | |
1801 | /* complete this sub-frame */ | |
1802 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
1803 | ||
b5aa9bf9 | 1804 | spin_lock(&txq->axq_lock); |
f078f209 LR |
1805 | } |
1806 | ||
1807 | /* | |
1808 | * TODO: For frame(s) that are in the retry state, we will reuse the | |
1809 | * sequence number(s) without setting the retry bit. The | |
1810 | * alternative is to give up on these and BAR the receiver's window | |
1811 | * forward. | |
1812 | */ | |
1813 | tid->seq_next = tid->seq_start; | |
1814 | tid->baw_tail = tid->baw_head; | |
1815 | } | |
1816 | ||
1817 | /* | |
1818 | * Drain all pending buffers | |
1819 | * NB: must be called with txq lock held | |
1820 | */ | |
1821 | ||
1822 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, | |
b5aa9bf9 | 1823 | struct ath_txq *txq) |
f078f209 LR |
1824 | { |
1825 | struct ath_atx_ac *ac, *ac_tmp; | |
1826 | struct ath_atx_tid *tid, *tid_tmp; | |
1827 | ||
1828 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { | |
1829 | list_del(&ac->list); | |
1830 | ac->sched = false; | |
1831 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
1832 | list_del(&tid->list); | |
1833 | tid->sched = false; | |
b5aa9bf9 | 1834 | ath_tid_drain(sc, txq, tid); |
f078f209 LR |
1835 | } |
1836 | } | |
1837 | } | |
1838 | ||
1839 | static int ath_tx_start_dma(struct ath_softc *sc, | |
1840 | struct sk_buff *skb, | |
1841 | struct scatterlist *sg, | |
1842 | u32 n_sg, | |
1843 | struct ath_tx_control *txctl) | |
1844 | { | |
1845 | struct ath_node *an = txctl->an; | |
1846 | struct ath_buf *bf = NULL; | |
1847 | struct list_head bf_head; | |
1848 | struct ath_desc *ds; | |
1849 | struct ath_hal *ah = sc->sc_ah; | |
e022edbd | 1850 | struct ath_txq *txq; |
f078f209 LR |
1851 | struct ath_tx_info_priv *tx_info_priv; |
1852 | struct ath_rc_series *rcs; | |
1853 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
1854 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1855 | __le16 fc = hdr->frame_control; | |
1856 | ||
e022edbd JM |
1857 | if (unlikely(txctl->flags & ATH9K_TXDESC_CAB)) |
1858 | txq = sc->sc_cabq; | |
1859 | else | |
1860 | txq = &sc->sc_txq[txctl->qnum]; | |
1861 | ||
f078f209 LR |
1862 | /* For each sglist entry, allocate an ath_buf for DMA */ |
1863 | INIT_LIST_HEAD(&bf_head); | |
1864 | spin_lock_bh(&sc->sc_txbuflock); | |
1865 | if (unlikely(list_empty(&sc->sc_txbuf))) { | |
1866 | spin_unlock_bh(&sc->sc_txbuflock); | |
1867 | return -ENOMEM; | |
1868 | } | |
1869 | ||
1870 | bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list); | |
1871 | list_del(&bf->list); | |
1872 | spin_unlock_bh(&sc->sc_txbuflock); | |
1873 | ||
1874 | list_add_tail(&bf->list, &bf_head); | |
1875 | ||
1876 | /* set up this buffer */ | |
1877 | ATH_TXBUF_RESET(bf); | |
1878 | bf->bf_frmlen = txctl->frmlen; | |
cd3d39a6 S |
1879 | |
1880 | ieee80211_is_data(fc) ? | |
1881 | (bf->bf_state.bf_type |= BUF_DATA) : | |
1882 | (bf->bf_state.bf_type &= ~BUF_DATA); | |
1883 | ieee80211_is_back_req(fc) ? | |
1884 | (bf->bf_state.bf_type |= BUF_BAR) : | |
1885 | (bf->bf_state.bf_type &= ~BUF_BAR); | |
1886 | ieee80211_is_pspoll(fc) ? | |
1887 | (bf->bf_state.bf_type |= BUF_PSPOLL) : | |
1888 | (bf->bf_state.bf_type &= ~BUF_PSPOLL); | |
672840ac | 1889 | (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ? |
cd3d39a6 S |
1890 | (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) : |
1891 | (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE); | |
1892 | ||
f078f209 | 1893 | bf->bf_flags = txctl->flags; |
f078f209 | 1894 | bf->bf_keytype = txctl->keytype; |
e6a9854b JB |
1895 | /* XXX: HACK! */ |
1896 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->control.vif; | |
f078f209 LR |
1897 | rcs = tx_info_priv->rcs; |
1898 | bf->bf_rcs[0] = rcs[0]; | |
1899 | bf->bf_rcs[1] = rcs[1]; | |
1900 | bf->bf_rcs[2] = rcs[2]; | |
1901 | bf->bf_rcs[3] = rcs[3]; | |
1902 | bf->bf_node = an; | |
1903 | bf->bf_mpdu = skb; | |
1904 | bf->bf_buf_addr = sg_dma_address(sg); | |
1905 | ||
1906 | /* setup descriptor */ | |
1907 | ds = bf->bf_desc; | |
1908 | ds->ds_link = 0; | |
1909 | ds->ds_data = bf->bf_buf_addr; | |
1910 | ||
1911 | /* | |
1912 | * Save the DMA context in the first ath_buf | |
1913 | */ | |
ff9b662d | 1914 | bf->bf_dmacontext = txctl->dmacontext; |
f078f209 LR |
1915 | |
1916 | /* | |
1917 | * Formulate first tx descriptor with tx controls. | |
1918 | */ | |
1919 | ath9k_hw_set11n_txdesc(ah, | |
1920 | ds, | |
1921 | bf->bf_frmlen, /* frame length */ | |
1922 | txctl->atype, /* Atheros packet type */ | |
1923 | min(txctl->txpower, (u16)60), /* txpower */ | |
1924 | txctl->keyix, /* key cache index */ | |
1925 | txctl->keytype, /* key type */ | |
1926 | txctl->flags); /* flags */ | |
1927 | ath9k_hw_filltxdesc(ah, | |
1928 | ds, | |
1929 | sg_dma_len(sg), /* segment length */ | |
1930 | true, /* first segment */ | |
1931 | (n_sg == 1) ? true : false, /* last segment */ | |
1932 | ds); /* first descriptor */ | |
1933 | ||
1934 | bf->bf_lastfrm = bf; | |
cd3d39a6 S |
1935 | (txctl->ht) ? |
1936 | (bf->bf_state.bf_type |= BUF_HT) : | |
1937 | (bf->bf_state.bf_type &= ~BUF_HT); | |
f078f209 LR |
1938 | |
1939 | spin_lock_bh(&txq->axq_lock); | |
1940 | ||
672840ac | 1941 | if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) { |
f078f209 LR |
1942 | struct ath_atx_tid *tid = ATH_AN_2_TID(an, txctl->tidno); |
1943 | if (ath_aggr_query(sc, an, txctl->tidno)) { | |
1944 | /* | |
1945 | * Try aggregation if it's a unicast data frame | |
1946 | * and the destination is HT capable. | |
1947 | */ | |
1948 | ath_tx_send_ampdu(sc, txq, tid, &bf_head, txctl); | |
1949 | } else { | |
1950 | /* | |
1951 | * Send this frame as regular when ADDBA exchange | |
1952 | * is neither complete nor pending. | |
1953 | */ | |
1954 | ath_tx_send_normal(sc, txq, tid, &bf_head); | |
1955 | } | |
1956 | } else { | |
1957 | bf->bf_lastbf = bf; | |
1958 | bf->bf_nframes = 1; | |
1959 | ath_buf_set_rate(sc, bf); | |
1960 | ||
1961 | if (ieee80211_is_back_req(fc)) { | |
1962 | /* This is required for resuming tid | |
1963 | * during BAR completion */ | |
1964 | bf->bf_tidno = txctl->tidno; | |
1965 | } | |
1966 | ||
e022edbd | 1967 | ath_tx_txqaddbuf(sc, txq, &bf_head); |
f078f209 LR |
1968 | } |
1969 | spin_unlock_bh(&txq->axq_lock); | |
1970 | return 0; | |
1971 | } | |
1972 | ||
1973 | static void xmit_map_sg(struct ath_softc *sc, | |
1974 | struct sk_buff *skb, | |
f078f209 LR |
1975 | struct ath_tx_control *txctl) |
1976 | { | |
1977 | struct ath_xmit_status tx_status; | |
1978 | struct ath_atx_tid *tid; | |
1979 | struct scatterlist sg; | |
1980 | ||
ff9b662d S |
1981 | txctl->dmacontext = pci_map_single(sc->pdev, skb->data, |
1982 | skb->len, PCI_DMA_TODEVICE); | |
f078f209 LR |
1983 | |
1984 | /* setup S/G list */ | |
1985 | memset(&sg, 0, sizeof(struct scatterlist)); | |
ff9b662d | 1986 | sg_dma_address(&sg) = txctl->dmacontext; |
f078f209 LR |
1987 | sg_dma_len(&sg) = skb->len; |
1988 | ||
1989 | if (ath_tx_start_dma(sc, skb, &sg, 1, txctl) != 0) { | |
1990 | /* | |
1991 | * We have to do drop frame here. | |
1992 | */ | |
ff9b662d S |
1993 | pci_unmap_single(sc->pdev, txctl->dmacontext, |
1994 | skb->len, PCI_DMA_TODEVICE); | |
f078f209 LR |
1995 | |
1996 | tx_status.retries = 0; | |
1997 | tx_status.flags = ATH_TX_ERROR; | |
1998 | ||
672840ac | 1999 | if (txctl->ht && (sc->sc_flags & SC_OP_TXAGGR)) { |
f078f209 LR |
2000 | /* Reclaim the seqno. */ |
2001 | tid = ATH_AN_2_TID((struct ath_node *) | |
2002 | txctl->an, txctl->tidno); | |
2003 | DECR(tid->seq_next, IEEE80211_SEQ_MAX); | |
2004 | } | |
2005 | ath_tx_complete(sc, skb, &tx_status, txctl->an); | |
2006 | } | |
2007 | } | |
2008 | ||
2009 | /* Initialize TX queue and h/w */ | |
2010 | ||
2011 | int ath_tx_init(struct ath_softc *sc, int nbufs) | |
2012 | { | |
2013 | int error = 0; | |
2014 | ||
2015 | do { | |
2016 | spin_lock_init(&sc->sc_txbuflock); | |
2017 | ||
2018 | /* Setup tx descriptors */ | |
2019 | error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, | |
556bb8f1 | 2020 | "tx", nbufs, 1); |
f078f209 LR |
2021 | if (error != 0) { |
2022 | DPRINTF(sc, ATH_DBG_FATAL, | |
2023 | "%s: failed to allocate tx descriptors: %d\n", | |
2024 | __func__, error); | |
2025 | break; | |
2026 | } | |
2027 | ||
2028 | /* XXX allocate beacon state together with vap */ | |
2029 | error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, | |
2030 | "beacon", ATH_BCBUF, 1); | |
2031 | if (error != 0) { | |
2032 | DPRINTF(sc, ATH_DBG_FATAL, | |
2033 | "%s: failed to allocate " | |
2034 | "beacon descripotrs: %d\n", | |
2035 | __func__, error); | |
2036 | break; | |
2037 | } | |
2038 | ||
2039 | } while (0); | |
2040 | ||
2041 | if (error != 0) | |
2042 | ath_tx_cleanup(sc); | |
2043 | ||
2044 | return error; | |
2045 | } | |
2046 | ||
2047 | /* Reclaim all tx queue resources */ | |
2048 | ||
2049 | int ath_tx_cleanup(struct ath_softc *sc) | |
2050 | { | |
2051 | /* cleanup beacon descriptors */ | |
2052 | if (sc->sc_bdma.dd_desc_len != 0) | |
2053 | ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); | |
2054 | ||
2055 | /* cleanup tx descriptors */ | |
2056 | if (sc->sc_txdma.dd_desc_len != 0) | |
2057 | ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); | |
2058 | ||
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | /* Setup a h/w transmit queue */ | |
2063 | ||
2064 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) | |
2065 | { | |
2066 | struct ath_hal *ah = sc->sc_ah; | |
ea9880fb | 2067 | struct ath9k_tx_queue_info qi; |
f078f209 LR |
2068 | int qnum; |
2069 | ||
0345f37b | 2070 | memset(&qi, 0, sizeof(qi)); |
f078f209 LR |
2071 | qi.tqi_subtype = subtype; |
2072 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
2073 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
2074 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
ea9880fb | 2075 | qi.tqi_physCompBuf = 0; |
f078f209 LR |
2076 | |
2077 | /* | |
2078 | * Enable interrupts only for EOL and DESC conditions. | |
2079 | * We mark tx descriptors to receive a DESC interrupt | |
2080 | * when a tx queue gets deep; otherwise waiting for the | |
2081 | * EOL to reap descriptors. Note that this is done to | |
2082 | * reduce interrupt load and this only defers reaping | |
2083 | * descriptors, never transmitting frames. Aside from | |
2084 | * reducing interrupts this also permits more concurrency. | |
2085 | * The only potential downside is if the tx queue backs | |
2086 | * up in which case the top half of the kernel may backup | |
2087 | * due to a lack of tx descriptors. | |
2088 | * | |
2089 | * The UAPSD queue is an exception, since we take a desc- | |
2090 | * based intr on the EOSP frames. | |
2091 | */ | |
2092 | if (qtype == ATH9K_TX_QUEUE_UAPSD) | |
2093 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
2094 | else | |
2095 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
2096 | TXQ_FLAG_TXDESCINT_ENABLE; | |
2097 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
2098 | if (qnum == -1) { | |
2099 | /* | |
2100 | * NB: don't print a message, this happens | |
2101 | * normally on parts with too few tx queues | |
2102 | */ | |
2103 | return NULL; | |
2104 | } | |
2105 | if (qnum >= ARRAY_SIZE(sc->sc_txq)) { | |
2106 | DPRINTF(sc, ATH_DBG_FATAL, | |
2107 | "%s: hal qnum %u out of range, max %u!\n", | |
2108 | __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq)); | |
2109 | ath9k_hw_releasetxqueue(ah, qnum); | |
2110 | return NULL; | |
2111 | } | |
2112 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
2113 | struct ath_txq *txq = &sc->sc_txq[qnum]; | |
2114 | ||
2115 | txq->axq_qnum = qnum; | |
2116 | txq->axq_link = NULL; | |
2117 | INIT_LIST_HEAD(&txq->axq_q); | |
2118 | INIT_LIST_HEAD(&txq->axq_acq); | |
2119 | spin_lock_init(&txq->axq_lock); | |
2120 | txq->axq_depth = 0; | |
2121 | txq->axq_aggr_depth = 0; | |
2122 | txq->axq_totalqueued = 0; | |
f078f209 LR |
2123 | txq->axq_linkbuf = NULL; |
2124 | sc->sc_txqsetup |= 1<<qnum; | |
2125 | } | |
2126 | return &sc->sc_txq[qnum]; | |
2127 | } | |
2128 | ||
2129 | /* Reclaim resources for a setup queue */ | |
2130 | ||
2131 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) | |
2132 | { | |
2133 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); | |
2134 | sc->sc_txqsetup &= ~(1<<txq->axq_qnum); | |
2135 | } | |
2136 | ||
2137 | /* | |
2138 | * Setup a hardware data transmit queue for the specified | |
2139 | * access control. The hal may not support all requested | |
2140 | * queues in which case it will return a reference to a | |
2141 | * previously setup queue. We record the mapping from ac's | |
2142 | * to h/w queues for use by ath_tx_start and also track | |
2143 | * the set of h/w queues being used to optimize work in the | |
2144 | * transmit interrupt handler and related routines. | |
2145 | */ | |
2146 | ||
2147 | int ath_tx_setup(struct ath_softc *sc, int haltype) | |
2148 | { | |
2149 | struct ath_txq *txq; | |
2150 | ||
2151 | if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { | |
2152 | DPRINTF(sc, ATH_DBG_FATAL, | |
2153 | "%s: HAL AC %u out of range, max %zu!\n", | |
2154 | __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q)); | |
2155 | return 0; | |
2156 | } | |
2157 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
2158 | if (txq != NULL) { | |
2159 | sc->sc_haltype2q[haltype] = txq->axq_qnum; | |
2160 | return 1; | |
2161 | } else | |
2162 | return 0; | |
2163 | } | |
2164 | ||
2165 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) | |
2166 | { | |
2167 | int qnum; | |
2168 | ||
2169 | switch (qtype) { | |
2170 | case ATH9K_TX_QUEUE_DATA: | |
2171 | if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) { | |
2172 | DPRINTF(sc, ATH_DBG_FATAL, | |
2173 | "%s: HAL AC %u out of range, max %zu!\n", | |
2174 | __func__, | |
2175 | haltype, ARRAY_SIZE(sc->sc_haltype2q)); | |
2176 | return -1; | |
2177 | } | |
2178 | qnum = sc->sc_haltype2q[haltype]; | |
2179 | break; | |
2180 | case ATH9K_TX_QUEUE_BEACON: | |
2181 | qnum = sc->sc_bhalq; | |
2182 | break; | |
2183 | case ATH9K_TX_QUEUE_CAB: | |
2184 | qnum = sc->sc_cabq->axq_qnum; | |
2185 | break; | |
2186 | default: | |
2187 | qnum = -1; | |
2188 | } | |
2189 | return qnum; | |
2190 | } | |
2191 | ||
2192 | /* Update parameters for a transmit queue */ | |
2193 | ||
ea9880fb S |
2194 | int ath_txq_update(struct ath_softc *sc, int qnum, |
2195 | struct ath9k_tx_queue_info *qinfo) | |
f078f209 LR |
2196 | { |
2197 | struct ath_hal *ah = sc->sc_ah; | |
2198 | int error = 0; | |
ea9880fb | 2199 | struct ath9k_tx_queue_info qi; |
f078f209 LR |
2200 | |
2201 | if (qnum == sc->sc_bhalq) { | |
2202 | /* | |
2203 | * XXX: for beacon queue, we just save the parameter. | |
2204 | * It will be picked up by ath_beaconq_config when | |
2205 | * it's necessary. | |
2206 | */ | |
ea9880fb | 2207 | sc->sc_beacon_qi = *qinfo; |
f078f209 LR |
2208 | return 0; |
2209 | } | |
2210 | ||
2211 | ASSERT(sc->sc_txq[qnum].axq_qnum == qnum); | |
2212 | ||
ea9880fb S |
2213 | ath9k_hw_get_txq_props(ah, qnum, &qi); |
2214 | qi.tqi_aifs = qinfo->tqi_aifs; | |
2215 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
2216 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
2217 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
2218 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
f078f209 | 2219 | |
ea9880fb | 2220 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { |
f078f209 LR |
2221 | DPRINTF(sc, ATH_DBG_FATAL, |
2222 | "%s: unable to update hardware queue %u!\n", | |
2223 | __func__, qnum); | |
2224 | error = -EIO; | |
2225 | } else { | |
2226 | ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */ | |
2227 | } | |
2228 | ||
2229 | return error; | |
2230 | } | |
2231 | ||
2232 | int ath_cabq_update(struct ath_softc *sc) | |
2233 | { | |
ea9880fb | 2234 | struct ath9k_tx_queue_info qi; |
f078f209 LR |
2235 | int qnum = sc->sc_cabq->axq_qnum; |
2236 | struct ath_beacon_config conf; | |
2237 | ||
ea9880fb | 2238 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 LR |
2239 | /* |
2240 | * Ensure the readytime % is within the bounds. | |
2241 | */ | |
2242 | if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) | |
2243 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
2244 | else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
2245 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
2246 | ||
2247 | ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf); | |
2248 | qi.tqi_readyTime = | |
2249 | (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100; | |
2250 | ath_txq_update(sc, qnum, &qi); | |
2251 | ||
2252 | return 0; | |
2253 | } | |
2254 | ||
2255 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb) | |
2256 | { | |
2257 | struct ath_tx_control txctl; | |
2258 | int error = 0; | |
2259 | ||
e022edbd | 2260 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
2261 | error = ath_tx_prepare(sc, skb, &txctl); |
2262 | if (error == 0) | |
2263 | /* | |
2264 | * Start DMA mapping. | |
2265 | * ath_tx_start_dma() will be called either synchronously | |
2266 | * or asynchrounsly once DMA is complete. | |
2267 | */ | |
ff9b662d | 2268 | xmit_map_sg(sc, skb, &txctl); |
f078f209 LR |
2269 | |
2270 | /* failed packets will be dropped by the caller */ | |
2271 | return error; | |
2272 | } | |
2273 | ||
2274 | /* Deferred processing of transmit interrupt */ | |
2275 | ||
2276 | void ath_tx_tasklet(struct ath_softc *sc) | |
2277 | { | |
1fe1132b | 2278 | int i; |
f078f209 LR |
2279 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); |
2280 | ||
2281 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); | |
2282 | ||
2283 | /* | |
2284 | * Process each active queue. | |
2285 | */ | |
2286 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2287 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
1fe1132b | 2288 | ath_tx_processq(sc, &sc->sc_txq[i]); |
f078f209 | 2289 | } |
f078f209 LR |
2290 | } |
2291 | ||
2292 | void ath_tx_draintxq(struct ath_softc *sc, | |
2293 | struct ath_txq *txq, bool retry_tx) | |
2294 | { | |
2295 | struct ath_buf *bf, *lastbf; | |
2296 | struct list_head bf_head; | |
2297 | ||
2298 | INIT_LIST_HEAD(&bf_head); | |
2299 | ||
2300 | /* | |
2301 | * NB: this assumes output has been stopped and | |
2302 | * we do not need to block ath_tx_tasklet | |
2303 | */ | |
2304 | for (;;) { | |
2305 | spin_lock_bh(&txq->axq_lock); | |
2306 | ||
2307 | if (list_empty(&txq->axq_q)) { | |
2308 | txq->axq_link = NULL; | |
2309 | txq->axq_linkbuf = NULL; | |
2310 | spin_unlock_bh(&txq->axq_lock); | |
2311 | break; | |
2312 | } | |
2313 | ||
2314 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); | |
2315 | ||
2316 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { | |
2317 | list_del(&bf->list); | |
2318 | spin_unlock_bh(&txq->axq_lock); | |
2319 | ||
2320 | spin_lock_bh(&sc->sc_txbuflock); | |
2321 | list_add_tail(&bf->list, &sc->sc_txbuf); | |
2322 | spin_unlock_bh(&sc->sc_txbuflock); | |
2323 | continue; | |
2324 | } | |
2325 | ||
2326 | lastbf = bf->bf_lastbf; | |
2327 | if (!retry_tx) | |
2328 | lastbf->bf_desc->ds_txstat.ts_flags = | |
2329 | ATH9K_TX_SW_ABORTED; | |
2330 | ||
2331 | /* remove ath_buf's of the same mpdu from txq */ | |
2332 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
2333 | txq->axq_depth--; | |
2334 | ||
2335 | spin_unlock_bh(&txq->axq_lock); | |
2336 | ||
cd3d39a6 | 2337 | if (bf_isampdu(bf)) |
f078f209 LR |
2338 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0); |
2339 | else | |
2340 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
2341 | } | |
2342 | ||
2343 | /* flush any pending frames if aggregation is enabled */ | |
672840ac | 2344 | if (sc->sc_flags & SC_OP_TXAGGR) { |
f078f209 LR |
2345 | if (!retry_tx) { |
2346 | spin_lock_bh(&txq->axq_lock); | |
b5aa9bf9 | 2347 | ath_txq_drain_pending_buffers(sc, txq); |
f078f209 LR |
2348 | spin_unlock_bh(&txq->axq_lock); |
2349 | } | |
2350 | } | |
2351 | } | |
2352 | ||
2353 | /* Drain the transmit queues and reclaim resources */ | |
2354 | ||
2355 | void ath_draintxq(struct ath_softc *sc, bool retry_tx) | |
2356 | { | |
2357 | /* stop beacon queue. The beacon will be freed when | |
2358 | * we go to INIT state */ | |
672840ac | 2359 | if (!(sc->sc_flags & SC_OP_INVALID)) { |
f078f209 LR |
2360 | (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); |
2361 | DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__, | |
2362 | ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq)); | |
2363 | } | |
2364 | ||
2365 | ath_drain_txdataq(sc, retry_tx); | |
2366 | } | |
2367 | ||
2368 | u32 ath_txq_depth(struct ath_softc *sc, int qnum) | |
2369 | { | |
2370 | return sc->sc_txq[qnum].axq_depth; | |
2371 | } | |
2372 | ||
2373 | u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum) | |
2374 | { | |
2375 | return sc->sc_txq[qnum].axq_aggr_depth; | |
2376 | } | |
2377 | ||
2378 | /* Check if an ADDBA is required. A valid node must be passed. */ | |
2379 | enum ATH_AGGR_CHECK ath_tx_aggr_check(struct ath_softc *sc, | |
2380 | struct ath_node *an, | |
2381 | u8 tidno) | |
2382 | { | |
2383 | struct ath_atx_tid *txtid; | |
f078f209 | 2384 | |
672840ac | 2385 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
f078f209 LR |
2386 | return AGGR_NOT_REQUIRED; |
2387 | ||
2388 | /* ADDBA exchange must be completed before sending aggregates */ | |
2389 | txtid = ATH_AN_2_TID(an, tidno); | |
2390 | ||
2391 | if (txtid->addba_exchangecomplete) | |
2392 | return AGGR_EXCHANGE_DONE; | |
2393 | ||
2394 | if (txtid->cleanup_inprogress) | |
2395 | return AGGR_CLEANUP_PROGRESS; | |
2396 | ||
2397 | if (txtid->addba_exchangeinprogress) | |
2398 | return AGGR_EXCHANGE_PROGRESS; | |
2399 | ||
2400 | if (!txtid->addba_exchangecomplete) { | |
2401 | if (!txtid->addba_exchangeinprogress && | |
2402 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
2403 | txtid->addba_exchangeattempts++; | |
2404 | return AGGR_REQUIRED; | |
2405 | } | |
2406 | } | |
2407 | ||
2408 | return AGGR_NOT_REQUIRED; | |
2409 | } | |
2410 | ||
2411 | /* Start TX aggregation */ | |
2412 | ||
b5aa9bf9 S |
2413 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
2414 | u16 tid, u16 *ssn) | |
f078f209 LR |
2415 | { |
2416 | struct ath_atx_tid *txtid; | |
2417 | struct ath_node *an; | |
2418 | ||
b5aa9bf9 | 2419 | an = (struct ath_node *)sta->drv_priv; |
f078f209 | 2420 | |
672840ac | 2421 | if (sc->sc_flags & SC_OP_TXAGGR) { |
f078f209 LR |
2422 | txtid = ATH_AN_2_TID(an, tid); |
2423 | txtid->addba_exchangeinprogress = 1; | |
2424 | ath_tx_pause_tid(sc, txtid); | |
2425 | } | |
2426 | ||
2427 | return 0; | |
2428 | } | |
2429 | ||
2430 | /* Stop tx aggregation */ | |
2431 | ||
b5aa9bf9 | 2432 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
f078f209 | 2433 | { |
b5aa9bf9 | 2434 | struct ath_node *an = (struct ath_node *)sta->drv_priv; |
f078f209 LR |
2435 | |
2436 | ath_tx_aggr_teardown(sc, an, tid); | |
2437 | return 0; | |
2438 | } | |
2439 | ||
2440 | /* | |
2441 | * Performs transmit side cleanup when TID changes from aggregated to | |
2442 | * unaggregated. | |
2443 | * - Pause the TID and mark cleanup in progress | |
2444 | * - Discard all retry frames from the s/w queue. | |
2445 | */ | |
2446 | ||
b5aa9bf9 | 2447 | void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid) |
f078f209 LR |
2448 | { |
2449 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
2450 | struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum]; | |
2451 | struct ath_buf *bf; | |
2452 | struct list_head bf_head; | |
2453 | INIT_LIST_HEAD(&bf_head); | |
2454 | ||
2455 | DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__); | |
2456 | ||
2457 | if (txtid->cleanup_inprogress) /* cleanup is in progress */ | |
2458 | return; | |
2459 | ||
2460 | if (!txtid->addba_exchangecomplete) { | |
2461 | txtid->addba_exchangeattempts = 0; | |
2462 | return; | |
2463 | } | |
2464 | ||
2465 | /* TID must be paused first */ | |
2466 | ath_tx_pause_tid(sc, txtid); | |
2467 | ||
2468 | /* drop all software retried frames and mark this TID */ | |
2469 | spin_lock_bh(&txq->axq_lock); | |
2470 | while (!list_empty(&txtid->buf_q)) { | |
2471 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
cd3d39a6 | 2472 | if (!bf_isretried(bf)) { |
f078f209 LR |
2473 | /* |
2474 | * NB: it's based on the assumption that | |
2475 | * software retried frame will always stay | |
2476 | * at the head of software queue. | |
2477 | */ | |
2478 | break; | |
2479 | } | |
2480 | list_cut_position(&bf_head, | |
2481 | &txtid->buf_q, &bf->bf_lastfrm->list); | |
2482 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); | |
2483 | ||
2484 | /* complete this sub-frame */ | |
2485 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
2486 | } | |
2487 | ||
2488 | if (txtid->baw_head != txtid->baw_tail) { | |
2489 | spin_unlock_bh(&txq->axq_lock); | |
2490 | txtid->cleanup_inprogress = true; | |
2491 | } else { | |
2492 | txtid->addba_exchangecomplete = 0; | |
2493 | txtid->addba_exchangeattempts = 0; | |
2494 | spin_unlock_bh(&txq->axq_lock); | |
2495 | ath_tx_flush_tid(sc, txtid); | |
2496 | } | |
2497 | } | |
2498 | ||
2499 | /* | |
2500 | * Tx scheduling logic | |
2501 | * NB: must be called with txq lock held | |
2502 | */ | |
2503 | ||
2504 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) | |
2505 | { | |
2506 | struct ath_atx_ac *ac; | |
2507 | struct ath_atx_tid *tid; | |
2508 | ||
2509 | /* nothing to schedule */ | |
2510 | if (list_empty(&txq->axq_acq)) | |
2511 | return; | |
2512 | /* | |
2513 | * get the first node/ac pair on the queue | |
2514 | */ | |
2515 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); | |
2516 | list_del(&ac->list); | |
2517 | ac->sched = false; | |
2518 | ||
2519 | /* | |
2520 | * process a single tid per destination | |
2521 | */ | |
2522 | do { | |
2523 | /* nothing to schedule */ | |
2524 | if (list_empty(&ac->tid_q)) | |
2525 | return; | |
2526 | ||
2527 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); | |
2528 | list_del(&tid->list); | |
2529 | tid->sched = false; | |
2530 | ||
2531 | if (tid->paused) /* check next tid to keep h/w busy */ | |
2532 | continue; | |
2533 | ||
2534 | if (!(tid->an->an_smmode == ATH_SM_PWRSAV_DYNAMIC) || | |
2535 | ((txq->axq_depth % 2) == 0)) { | |
2536 | ath_tx_sched_aggr(sc, txq, tid); | |
2537 | } | |
2538 | ||
2539 | /* | |
2540 | * add tid to round-robin queue if more frames | |
2541 | * are pending for the tid | |
2542 | */ | |
2543 | if (!list_empty(&tid->buf_q)) | |
2544 | ath_tx_queue_tid(txq, tid); | |
2545 | ||
2546 | /* only schedule one TID at a time */ | |
2547 | break; | |
2548 | } while (!list_empty(&ac->tid_q)); | |
2549 | ||
2550 | /* | |
2551 | * schedule AC if more TIDs need processing | |
2552 | */ | |
2553 | if (!list_empty(&ac->tid_q)) { | |
2554 | /* | |
2555 | * add dest ac to txq if not already added | |
2556 | */ | |
2557 | if (!ac->sched) { | |
2558 | ac->sched = true; | |
2559 | list_add_tail(&ac->list, &txq->axq_acq); | |
2560 | } | |
2561 | } | |
2562 | } | |
2563 | ||
2564 | /* Initialize per-node transmit state */ | |
2565 | ||
2566 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2567 | { | |
672840ac | 2568 | if (sc->sc_flags & SC_OP_TXAGGR) { |
f078f209 LR |
2569 | struct ath_atx_tid *tid; |
2570 | struct ath_atx_ac *ac; | |
2571 | int tidno, acno; | |
2572 | ||
f078f209 LR |
2573 | /* |
2574 | * Init per tid tx state | |
2575 | */ | |
2576 | for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno]; | |
2577 | tidno < WME_NUM_TID; | |
2578 | tidno++, tid++) { | |
2579 | tid->an = an; | |
2580 | tid->tidno = tidno; | |
2581 | tid->seq_start = tid->seq_next = 0; | |
2582 | tid->baw_size = WME_MAX_BA; | |
2583 | tid->baw_head = tid->baw_tail = 0; | |
2584 | tid->sched = false; | |
2585 | tid->paused = false; | |
2586 | tid->cleanup_inprogress = false; | |
2587 | INIT_LIST_HEAD(&tid->buf_q); | |
2588 | ||
2589 | acno = TID_TO_WME_AC(tidno); | |
2590 | tid->ac = &an->an_aggr.tx.ac[acno]; | |
2591 | ||
2592 | /* ADDBA state */ | |
2593 | tid->addba_exchangecomplete = 0; | |
2594 | tid->addba_exchangeinprogress = 0; | |
2595 | tid->addba_exchangeattempts = 0; | |
2596 | } | |
2597 | ||
2598 | /* | |
2599 | * Init per ac tx state | |
2600 | */ | |
2601 | for (acno = 0, ac = &an->an_aggr.tx.ac[acno]; | |
2602 | acno < WME_NUM_AC; acno++, ac++) { | |
2603 | ac->sched = false; | |
2604 | INIT_LIST_HEAD(&ac->tid_q); | |
2605 | ||
2606 | switch (acno) { | |
2607 | case WME_AC_BE: | |
2608 | ac->qnum = ath_tx_get_qnum(sc, | |
2609 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2610 | break; | |
2611 | case WME_AC_BK: | |
2612 | ac->qnum = ath_tx_get_qnum(sc, | |
2613 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2614 | break; | |
2615 | case WME_AC_VI: | |
2616 | ac->qnum = ath_tx_get_qnum(sc, | |
2617 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2618 | break; | |
2619 | case WME_AC_VO: | |
2620 | ac->qnum = ath_tx_get_qnum(sc, | |
2621 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2622 | break; | |
2623 | } | |
2624 | } | |
2625 | } | |
2626 | } | |
2627 | ||
2628 | /* Cleanupthe pending buffers for the node. */ | |
2629 | ||
b5aa9bf9 | 2630 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2631 | { |
2632 | int i; | |
2633 | struct ath_atx_ac *ac, *ac_tmp; | |
2634 | struct ath_atx_tid *tid, *tid_tmp; | |
2635 | struct ath_txq *txq; | |
2636 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
2637 | if (ATH_TXQ_SETUP(sc, i)) { | |
2638 | txq = &sc->sc_txq[i]; | |
2639 | ||
b5aa9bf9 | 2640 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2641 | |
2642 | list_for_each_entry_safe(ac, | |
2643 | ac_tmp, &txq->axq_acq, list) { | |
2644 | tid = list_first_entry(&ac->tid_q, | |
2645 | struct ath_atx_tid, list); | |
2646 | if (tid && tid->an != an) | |
2647 | continue; | |
2648 | list_del(&ac->list); | |
2649 | ac->sched = false; | |
2650 | ||
2651 | list_for_each_entry_safe(tid, | |
2652 | tid_tmp, &ac->tid_q, list) { | |
2653 | list_del(&tid->list); | |
2654 | tid->sched = false; | |
b5aa9bf9 | 2655 | ath_tid_drain(sc, txq, tid); |
f078f209 LR |
2656 | tid->addba_exchangecomplete = 0; |
2657 | tid->addba_exchangeattempts = 0; | |
2658 | tid->cleanup_inprogress = false; | |
2659 | } | |
2660 | } | |
2661 | ||
b5aa9bf9 | 2662 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2663 | } |
2664 | } | |
2665 | } | |
2666 | ||
2667 | /* Cleanup per node transmit state */ | |
2668 | ||
2669 | void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an) | |
2670 | { | |
672840ac | 2671 | if (sc->sc_flags & SC_OP_TXAGGR) { |
f078f209 LR |
2672 | struct ath_atx_tid *tid; |
2673 | int tidno, i; | |
2674 | ||
2675 | /* Init per tid rx state */ | |
2676 | for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno]; | |
2677 | tidno < WME_NUM_TID; | |
2678 | tidno++, tid++) { | |
2679 | ||
2680 | for (i = 0; i < ATH_TID_MAX_BUFS; i++) | |
2681 | ASSERT(tid->tx_buf[i] == NULL); | |
2682 | } | |
2683 | } | |
2684 | } | |
e022edbd JM |
2685 | |
2686 | void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb) | |
2687 | { | |
2688 | int hdrlen, padsize; | |
2689 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
2690 | struct ath_tx_control txctl; | |
2691 | ||
2692 | /* | |
2693 | * As a temporary workaround, assign seq# here; this will likely need | |
2694 | * to be cleaned up to work better with Beacon transmission and virtual | |
2695 | * BSSes. | |
2696 | */ | |
2697 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
2698 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
2699 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
2700 | sc->seq_no += 0x10; | |
2701 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
2702 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
2703 | } | |
2704 | ||
2705 | /* Add the padding after the header if this is not already done */ | |
2706 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2707 | if (hdrlen & 3) { | |
2708 | padsize = hdrlen % 4; | |
2709 | if (skb_headroom(skb) < padsize) { | |
2710 | DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding " | |
2711 | "failed\n", __func__); | |
2712 | dev_kfree_skb_any(skb); | |
2713 | return; | |
2714 | } | |
2715 | skb_push(skb, padsize); | |
2716 | memmove(skb->data, skb->data + padsize, hdrlen); | |
2717 | } | |
2718 | ||
2719 | DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n", | |
2720 | __func__, | |
2721 | skb); | |
2722 | ||
2723 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | |
2724 | txctl.flags = ATH9K_TXDESC_CAB; | |
2725 | if (ath_tx_prepare(sc, skb, &txctl) == 0) { | |
2726 | /* | |
2727 | * Start DMA mapping. | |
2728 | * ath_tx_start_dma() will be called either synchronously | |
2729 | * or asynchrounsly once DMA is complete. | |
2730 | */ | |
2731 | xmit_map_sg(sc, skb, &txctl); | |
2732 | } else { | |
e022edbd JM |
2733 | DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ failed\n", __func__); |
2734 | dev_kfree_skb_any(skb); | |
2735 | } | |
2736 | } | |
2737 |