Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include "core.h" |
18 | ||
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
e8324357 S |
58 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, | |
62 | struct list_head *bf_q, | |
63 | int txok, int sendbar); | |
102e0572 | 64 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
65 | struct list_head *head); |
66 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
c4288390 | 67 | |
e8324357 S |
68 | /*********************/ |
69 | /* Aggregation logic */ | |
70 | /*********************/ | |
f078f209 | 71 | |
a37c2c79 | 72 | static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
f078f209 LR |
73 | { |
74 | struct ath_atx_tid *tid; | |
75 | tid = ATH_AN_2_TID(an, tidno); | |
76 | ||
a37c2c79 S |
77 | if (tid->state & AGGR_ADDBA_COMPLETE || |
78 | tid->state & AGGR_ADDBA_PROGRESS) | |
f078f209 LR |
79 | return 1; |
80 | else | |
81 | return 0; | |
82 | } | |
83 | ||
e8324357 | 84 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 85 | { |
e8324357 | 86 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 87 | |
e8324357 S |
88 | if (tid->paused) |
89 | return; | |
ff37e337 | 90 | |
e8324357 S |
91 | if (tid->sched) |
92 | return; | |
ff37e337 | 93 | |
e8324357 S |
94 | tid->sched = true; |
95 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 96 | |
e8324357 S |
97 | if (ac->sched) |
98 | return; | |
f078f209 | 99 | |
e8324357 S |
100 | ac->sched = true; |
101 | list_add_tail(&ac->list, &txq->axq_acq); | |
102 | } | |
f078f209 | 103 | |
e8324357 S |
104 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
105 | { | |
106 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 107 | |
e8324357 S |
108 | spin_lock_bh(&txq->axq_lock); |
109 | tid->paused++; | |
110 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
111 | } |
112 | ||
e8324357 | 113 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 114 | { |
e8324357 | 115 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 116 | |
e8324357 S |
117 | ASSERT(tid->paused > 0); |
118 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 119 | |
e8324357 | 120 | tid->paused--; |
f078f209 | 121 | |
e8324357 S |
122 | if (tid->paused > 0) |
123 | goto unlock; | |
f078f209 | 124 | |
e8324357 S |
125 | if (list_empty(&tid->buf_q)) |
126 | goto unlock; | |
f078f209 | 127 | |
e8324357 S |
128 | ath_tx_queue_tid(txq, tid); |
129 | ath_txq_schedule(sc, txq); | |
130 | unlock: | |
131 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 132 | } |
f078f209 | 133 | |
e8324357 | 134 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 135 | { |
e8324357 S |
136 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
137 | struct ath_buf *bf; | |
138 | struct list_head bf_head; | |
139 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 140 | |
e8324357 S |
141 | ASSERT(tid->paused > 0); |
142 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 143 | |
e8324357 | 144 | tid->paused--; |
f078f209 | 145 | |
e8324357 S |
146 | if (tid->paused > 0) { |
147 | spin_unlock_bh(&txq->axq_lock); | |
148 | return; | |
149 | } | |
f078f209 | 150 | |
e8324357 S |
151 | while (!list_empty(&tid->buf_q)) { |
152 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
153 | ASSERT(!bf_isretried(bf)); | |
154 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | |
155 | ath_tx_send_normal(sc, txq, tid, &bf_head); | |
528f0c6b | 156 | } |
f078f209 | 157 | |
e8324357 | 158 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 159 | } |
f078f209 | 160 | |
e8324357 S |
161 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
162 | int seqno) | |
528f0c6b | 163 | { |
e8324357 | 164 | int index, cindex; |
f078f209 | 165 | |
e8324357 S |
166 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
167 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 168 | |
e8324357 | 169 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 170 | |
e8324357 S |
171 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
172 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
173 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
174 | } | |
528f0c6b | 175 | } |
f078f209 | 176 | |
e8324357 S |
177 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
178 | struct ath_buf *bf) | |
528f0c6b | 179 | { |
e8324357 | 180 | int index, cindex; |
528f0c6b | 181 | |
e8324357 S |
182 | if (bf_isretried(bf)) |
183 | return; | |
528f0c6b | 184 | |
e8324357 S |
185 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
186 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 187 | |
e8324357 S |
188 | ASSERT(tid->tx_buf[cindex] == NULL); |
189 | tid->tx_buf[cindex] = bf; | |
f078f209 | 190 | |
e8324357 S |
191 | if (index >= ((tid->baw_tail - tid->baw_head) & |
192 | (ATH_TID_MAX_BUFS - 1))) { | |
193 | tid->baw_tail = cindex; | |
194 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 195 | } |
f078f209 LR |
196 | } |
197 | ||
198 | /* | |
e8324357 S |
199 | * TODO: For frame(s) that are in the retry state, we will reuse the |
200 | * sequence number(s) without setting the retry bit. The | |
201 | * alternative is to give up on these and BAR the receiver's window | |
202 | * forward. | |
f078f209 | 203 | */ |
e8324357 S |
204 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
205 | struct ath_atx_tid *tid) | |
f078f209 | 206 | |
f078f209 | 207 | { |
e8324357 S |
208 | struct ath_buf *bf; |
209 | struct list_head bf_head; | |
210 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 211 | |
e8324357 S |
212 | for (;;) { |
213 | if (list_empty(&tid->buf_q)) | |
214 | break; | |
215 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 216 | |
e8324357 | 217 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); |
f078f209 | 218 | |
e8324357 S |
219 | if (bf_isretried(bf)) |
220 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 221 | |
e8324357 S |
222 | spin_unlock(&txq->axq_lock); |
223 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
224 | spin_lock(&txq->axq_lock); | |
225 | } | |
f078f209 | 226 | |
e8324357 S |
227 | tid->seq_next = tid->seq_start; |
228 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
229 | } |
230 | ||
e8324357 | 231 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf) |
f078f209 | 232 | { |
e8324357 S |
233 | struct sk_buff *skb; |
234 | struct ieee80211_hdr *hdr; | |
f078f209 | 235 | |
e8324357 S |
236 | bf->bf_state.bf_type |= BUF_RETRY; |
237 | bf->bf_retries++; | |
f078f209 | 238 | |
e8324357 S |
239 | skb = bf->bf_mpdu; |
240 | hdr = (struct ieee80211_hdr *)skb->data; | |
241 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
242 | } |
243 | ||
e8324357 S |
244 | static void ath_tx_complete_aggr_rifs(struct ath_softc *sc, struct ath_txq *txq, |
245 | struct ath_buf *bf, struct list_head *bf_q, | |
246 | int txok) | |
f078f209 | 247 | { |
e8324357 S |
248 | struct ath_node *an = NULL; |
249 | struct sk_buff *skb; | |
250 | struct ieee80211_tx_info *tx_info; | |
251 | struct ath_atx_tid *tid = NULL; | |
f078f209 LR |
252 | struct ath_buf *bf_last = bf->bf_lastbf; |
253 | struct ath_desc *ds = bf_last->bf_desc; | |
e8324357 S |
254 | struct ath_buf *bf_next, *bf_lastq = NULL; |
255 | struct list_head bf_head, bf_pending; | |
f078f209 LR |
256 | u16 seq_st = 0; |
257 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
e8324357 | 258 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0; |
f078f209 | 259 | |
e8324357 S |
260 | skb = (struct sk_buff *)bf->bf_mpdu; |
261 | tx_info = IEEE80211_SKB_CB(skb); | |
f078f209 | 262 | |
e8324357 S |
263 | if (tx_info->control.sta) { |
264 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
265 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
f078f209 LR |
266 | } |
267 | ||
e8324357 S |
268 | isaggr = bf_isaggr(bf); |
269 | if (isaggr) { | |
270 | if (txok) { | |
271 | if (ATH_DS_TX_BA(ds)) { | |
272 | seq_st = ATH_DS_BA_SEQ(ds); | |
273 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
274 | WME_BA_BMP_SIZE >> 3); | |
275 | } else { | |
276 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); | |
f078f209 | 277 | |
e8324357 S |
278 | /* |
279 | * AR5416 can become deaf/mute when BA | |
280 | * issue happens. Chip needs to be reset. | |
281 | * But AP code may have sychronization issues | |
282 | * when perform internal reset in this routine. | |
283 | * Only enable reset in STA mode for now. | |
284 | */ | |
285 | if (sc->sc_ah->ah_opmode == | |
286 | NL80211_IFTYPE_STATION) | |
287 | needreset = 1; | |
288 | } | |
289 | } else { | |
290 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); | |
291 | } | |
f078f209 LR |
292 | } |
293 | ||
e8324357 S |
294 | INIT_LIST_HEAD(&bf_pending); |
295 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 296 | |
e8324357 S |
297 | while (bf) { |
298 | txfail = txpending = 0; | |
299 | bf_next = bf->bf_next; | |
f078f209 | 300 | |
e8324357 S |
301 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
302 | /* transmit completion, subframe is | |
303 | * acked by block ack */ | |
304 | } else if (!isaggr && txok) { | |
305 | /* transmit completion */ | |
306 | } else { | |
f078f209 | 307 | |
e8324357 S |
308 | if (!(tid->state & AGGR_CLEANUP) && |
309 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
310 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
311 | ath_tx_set_retry(sc, bf); | |
312 | txpending = 1; | |
313 | } else { | |
314 | bf->bf_state.bf_type |= BUF_XRETRY; | |
315 | txfail = 1; | |
316 | sendbar = 1; | |
317 | } | |
318 | } else { | |
319 | /* | |
320 | * cleanup in progress, just fail | |
321 | * the un-acked sub-frames | |
322 | */ | |
323 | txfail = 1; | |
324 | } | |
325 | } | |
f078f209 | 326 | |
e8324357 S |
327 | if (bf_next == NULL) { |
328 | ASSERT(bf->bf_lastfrm == bf_last); | |
329 | if (!list_empty(bf_q)) { | |
330 | bf_lastq = list_entry(bf_q->prev, | |
331 | struct ath_buf, list); | |
332 | list_cut_position(&bf_head, | |
333 | bf_q, &bf_lastq->list); | |
334 | } else { | |
335 | INIT_LIST_HEAD(&bf_head); | |
336 | } | |
337 | } else { | |
338 | ASSERT(!list_empty(bf_q)); | |
339 | list_cut_position(&bf_head, | |
340 | bf_q, &bf->bf_lastfrm->list); | |
341 | } | |
f078f209 | 342 | |
e8324357 S |
343 | if (!txpending) { |
344 | /* | |
345 | * complete the acked-ones/xretried ones; update | |
346 | * block-ack window | |
347 | */ | |
348 | spin_lock_bh(&txq->axq_lock); | |
349 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
350 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 351 | |
e8324357 S |
352 | ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar); |
353 | } else { | |
354 | /* | |
355 | * retry the un-acked ones | |
356 | */ | |
357 | if (bf->bf_next == NULL && | |
358 | bf_last->bf_status & ATH_BUFSTATUS_STALE) { | |
359 | struct ath_buf *tbf; | |
f078f209 | 360 | |
e8324357 S |
361 | /* allocate new descriptor */ |
362 | spin_lock_bh(&sc->tx.txbuflock); | |
363 | ASSERT(!list_empty((&sc->tx.txbuf))); | |
364 | tbf = list_first_entry(&sc->tx.txbuf, | |
365 | struct ath_buf, list); | |
366 | list_del(&tbf->list); | |
367 | spin_unlock_bh(&sc->tx.txbuflock); | |
f078f209 | 368 | |
e8324357 S |
369 | ATH_TXBUF_RESET(tbf); |
370 | ||
371 | /* copy descriptor content */ | |
372 | tbf->bf_mpdu = bf_last->bf_mpdu; | |
373 | tbf->bf_buf_addr = bf_last->bf_buf_addr; | |
374 | *(tbf->bf_desc) = *(bf_last->bf_desc); | |
375 | ||
376 | /* link it to the frame */ | |
377 | if (bf_lastq) { | |
378 | bf_lastq->bf_desc->ds_link = | |
379 | tbf->bf_daddr; | |
380 | bf->bf_lastfrm = tbf; | |
381 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
382 | bf->bf_lastfrm->bf_desc); | |
383 | } else { | |
384 | tbf->bf_state = bf_last->bf_state; | |
385 | tbf->bf_lastfrm = tbf; | |
386 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
387 | tbf->bf_lastfrm->bf_desc); | |
388 | ||
389 | /* copy the DMA context */ | |
390 | tbf->bf_dmacontext = | |
391 | bf_last->bf_dmacontext; | |
392 | } | |
393 | list_add_tail(&tbf->list, &bf_head); | |
394 | } else { | |
395 | /* | |
396 | * Clear descriptor status words for | |
397 | * software retry | |
398 | */ | |
399 | ath9k_hw_cleartxdesc(sc->sc_ah, | |
400 | bf->bf_lastfrm->bf_desc); | |
401 | } | |
402 | ||
403 | /* | |
404 | * Put this buffer to the temporary pending | |
405 | * queue to retain ordering | |
406 | */ | |
407 | list_splice_tail_init(&bf_head, &bf_pending); | |
408 | } | |
409 | ||
410 | bf = bf_next; | |
f078f209 | 411 | } |
f078f209 | 412 | |
e8324357 S |
413 | if (tid->state & AGGR_CLEANUP) { |
414 | /* check to see if we're done with cleaning the h/w queue */ | |
415 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 416 | |
e8324357 S |
417 | if (tid->baw_head == tid->baw_tail) { |
418 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
419 | tid->addba_exchangeattempts = 0; | |
420 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 421 | |
e8324357 | 422 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 423 | |
e8324357 S |
424 | /* send buffered frames as singles */ |
425 | ath_tx_flush_tid(sc, tid); | |
426 | } else | |
427 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 428 | |
e8324357 S |
429 | return; |
430 | } | |
f078f209 | 431 | |
e8324357 S |
432 | /* |
433 | * prepend un-acked frames to the beginning of the pending frame queue | |
434 | */ | |
435 | if (!list_empty(&bf_pending)) { | |
436 | spin_lock_bh(&txq->axq_lock); | |
437 | list_splice(&bf_pending, &tid->buf_q); | |
438 | ath_tx_queue_tid(txq, tid); | |
439 | spin_unlock_bh(&txq->axq_lock); | |
440 | } | |
102e0572 | 441 | |
e8324357 S |
442 | if (needreset) |
443 | ath_reset(sc, false); | |
f078f209 | 444 | |
e8324357 S |
445 | return; |
446 | } | |
f078f209 | 447 | |
e8324357 S |
448 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
449 | struct ath_atx_tid *tid) | |
f078f209 | 450 | { |
e8324357 | 451 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
452 | struct sk_buff *skb; |
453 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 454 | struct ieee80211_tx_rate *rates; |
e8324357 S |
455 | struct ath_tx_info_priv *tx_info_priv; |
456 | u32 max_4ms_framelen, frame_length; | |
457 | u16 aggr_limit, legacy = 0, maxampdu; | |
458 | int i; | |
528f0c6b S |
459 | |
460 | skb = (struct sk_buff *)bf->bf_mpdu; | |
461 | tx_info = IEEE80211_SKB_CB(skb); | |
e63835b0 | 462 | rates = tx_info->control.rates; |
e8324357 S |
463 | tx_info_priv = |
464 | (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; | |
528f0c6b | 465 | |
e8324357 S |
466 | /* |
467 | * Find the lowest frame length among the rate series that will have a | |
468 | * 4ms transmit duration. | |
469 | * TODO - TXOP limit needs to be considered. | |
470 | */ | |
471 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 472 | |
e8324357 S |
473 | for (i = 0; i < 4; i++) { |
474 | if (rates[i].count) { | |
475 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
476 | legacy = 1; | |
477 | break; | |
478 | } | |
479 | ||
480 | frame_length = | |
481 | rate_table->info[rates[i].idx].max_4ms_framelen; | |
482 | max_4ms_framelen = min(max_4ms_framelen, frame_length); | |
f078f209 LR |
483 | } |
484 | } | |
e63835b0 | 485 | |
f078f209 | 486 | /* |
e8324357 S |
487 | * limit aggregate size by the minimum rate if rate selected is |
488 | * not a probe rate, if rate selected is a probe rate then | |
489 | * avoid aggregation of this packet. | |
f078f209 | 490 | */ |
e8324357 S |
491 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
492 | return 0; | |
f078f209 | 493 | |
e8324357 S |
494 | aggr_limit = min(max_4ms_framelen, |
495 | (u32)ATH_AMPDU_LIMIT_DEFAULT); | |
f078f209 | 496 | |
e8324357 S |
497 | /* |
498 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
499 | * The IE, however can hold upto 65536, which shows up here | |
500 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 501 | */ |
e8324357 S |
502 | maxampdu = tid->an->maxampdu; |
503 | if (maxampdu) | |
504 | aggr_limit = min(aggr_limit, maxampdu); | |
f078f209 | 505 | |
e8324357 S |
506 | return aggr_limit; |
507 | } | |
f078f209 | 508 | |
e8324357 S |
509 | /* |
510 | * returns the number of delimiters to be added to | |
511 | * meet the minimum required mpdudensity. | |
512 | * caller should make sure that the rate is HT rate . | |
513 | */ | |
514 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
515 | struct ath_buf *bf, u16 frmlen) | |
516 | { | |
517 | struct ath_rate_table *rt = sc->cur_rate_table; | |
518 | struct sk_buff *skb = bf->bf_mpdu; | |
519 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
520 | u32 nsymbits, nsymbols, mpdudensity; | |
521 | u16 minlen; | |
522 | u8 rc, flags, rix; | |
523 | int width, half_gi, ndelim, mindelim; | |
524 | ||
525 | /* Select standard number of delimiters based on frame length alone */ | |
526 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
527 | |
528 | /* | |
e8324357 S |
529 | * If encryption enabled, hardware requires some more padding between |
530 | * subframes. | |
531 | * TODO - this could be improved to be dependent on the rate. | |
532 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 533 | */ |
e8324357 S |
534 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
535 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 536 | |
e8324357 S |
537 | /* |
538 | * Convert desired mpdu density from microeconds to bytes based | |
539 | * on highest rate in rate series (i.e. first rate) to determine | |
540 | * required minimum length for subframe. Take into account | |
541 | * whether high rate is 20 or 40Mhz and half or full GI. | |
542 | */ | |
543 | mpdudensity = tid->an->mpdudensity; | |
f078f209 | 544 | |
e8324357 S |
545 | /* |
546 | * If there is no mpdu density restriction, no further calculation | |
547 | * is needed. | |
548 | */ | |
549 | if (mpdudensity == 0) | |
550 | return ndelim; | |
f078f209 | 551 | |
e8324357 S |
552 | rix = tx_info->control.rates[0].idx; |
553 | flags = tx_info->control.rates[0].flags; | |
554 | rc = rt->info[rix].ratecode; | |
555 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
556 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 557 | |
e8324357 S |
558 | if (half_gi) |
559 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity); | |
560 | else | |
561 | nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity); | |
f078f209 | 562 | |
e8324357 S |
563 | if (nsymbols == 0) |
564 | nsymbols = 1; | |
f078f209 | 565 | |
e8324357 S |
566 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
567 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 568 | |
e8324357 S |
569 | /* Is frame shorter than required minimum length? */ |
570 | if (frmlen < minlen) { | |
571 | /* Get the minimum number of delimiters required. */ | |
572 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; | |
573 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
574 | } |
575 | ||
e8324357 | 576 | return ndelim; |
f078f209 LR |
577 | } |
578 | ||
e8324357 S |
579 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
580 | struct ath_atx_tid *tid, struct list_head *bf_q, | |
581 | struct ath_buf **bf_last, struct aggr_rifs_param *param, | |
582 | int *prev_frames) | |
f078f209 | 583 | { |
e8324357 S |
584 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
585 | struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL; | |
586 | struct list_head bf_head; | |
587 | int rl = 0, nframes = 0, ndelim; | |
588 | u16 aggr_limit = 0, al = 0, bpad = 0, | |
589 | al_delta, h_baw = tid->baw_size / 2; | |
590 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
591 | int prev_al = 0; | |
592 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 593 | |
e8324357 | 594 | BUG_ON(list_empty(&tid->buf_q)); |
f078f209 | 595 | |
e8324357 | 596 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 597 | |
e8324357 S |
598 | do { |
599 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 600 | |
e8324357 S |
601 | /* |
602 | * do not step over block-ack window | |
603 | */ | |
604 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { | |
605 | status = ATH_AGGR_BAW_CLOSED; | |
606 | break; | |
607 | } | |
f078f209 | 608 | |
e8324357 S |
609 | if (!rl) { |
610 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
611 | rl = 1; | |
612 | } | |
f078f209 | 613 | |
e8324357 S |
614 | /* |
615 | * do not exceed aggregation limit | |
616 | */ | |
617 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; | |
f078f209 | 618 | |
e8324357 S |
619 | if (nframes && (aggr_limit < |
620 | (al + bpad + al_delta + prev_al))) { | |
621 | status = ATH_AGGR_LIMITED; | |
622 | break; | |
623 | } | |
f078f209 | 624 | |
e8324357 S |
625 | /* |
626 | * do not exceed subframe limit | |
627 | */ | |
628 | if ((nframes + *prev_frames) >= | |
629 | min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
630 | status = ATH_AGGR_LIMITED; | |
631 | break; | |
632 | } | |
f078f209 | 633 | |
e8324357 S |
634 | /* |
635 | * add padding for previous frame to aggregation length | |
636 | */ | |
637 | al += bpad + al_delta; | |
f078f209 | 638 | |
e8324357 S |
639 | /* |
640 | * Get the delimiters needed to meet the MPDU | |
641 | * density for this node. | |
642 | */ | |
643 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
f078f209 | 644 | |
e8324357 | 645 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 646 | |
e8324357 S |
647 | bf->bf_next = NULL; |
648 | bf->bf_lastfrm->bf_desc->ds_link = 0; | |
f078f209 | 649 | |
e8324357 S |
650 | /* |
651 | * this packet is part of an aggregate | |
652 | * - remove all descriptors belonging to this frame from | |
653 | * software queue | |
654 | * - add it to block ack window | |
655 | * - set up descriptors for aggregation | |
656 | */ | |
657 | list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list); | |
658 | ath_tx_addto_baw(sc, tid, bf); | |
f078f209 | 659 | |
e8324357 S |
660 | list_for_each_entry(tbf, &bf_head, list) { |
661 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, | |
662 | tbf->bf_desc, ndelim); | |
663 | } | |
f078f209 | 664 | |
e8324357 S |
665 | /* |
666 | * link buffers of this frame to the aggregate | |
667 | */ | |
668 | list_splice_tail_init(&bf_head, bf_q); | |
669 | nframes++; | |
528f0c6b | 670 | |
e8324357 S |
671 | if (bf_prev) { |
672 | bf_prev->bf_next = bf; | |
673 | bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr; | |
674 | } | |
675 | bf_prev = bf; | |
528f0c6b | 676 | |
e8324357 | 677 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 678 | |
e8324357 S |
679 | bf_first->bf_al = al; |
680 | bf_first->bf_nframes = nframes; | |
681 | *bf_last = bf_prev; | |
682 | return status; | |
683 | #undef PADBYTES | |
684 | } | |
f078f209 | 685 | |
e8324357 S |
686 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
687 | struct ath_atx_tid *tid) | |
688 | { | |
689 | struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL; | |
690 | enum ATH_AGGR_STATUS status; | |
691 | struct list_head bf_q; | |
692 | struct aggr_rifs_param param = {0, 0, 0, 0, NULL}; | |
693 | int prev_frames = 0; | |
f078f209 | 694 | |
e8324357 S |
695 | do { |
696 | if (list_empty(&tid->buf_q)) | |
697 | return; | |
f078f209 | 698 | |
e8324357 S |
699 | INIT_LIST_HEAD(&bf_q); |
700 | ||
701 | status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m, | |
702 | &prev_frames); | |
f078f209 | 703 | |
f078f209 | 704 | /* |
e8324357 S |
705 | * no frames picked up to be aggregated; block-ack |
706 | * window is not open | |
f078f209 | 707 | */ |
e8324357 S |
708 | if (list_empty(&bf_q)) |
709 | break; | |
f078f209 | 710 | |
e8324357 S |
711 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
712 | bf_last = list_entry(bf_q.prev, struct ath_buf, list); | |
713 | bf->bf_lastbf = bf_last; | |
f078f209 | 714 | |
e8324357 S |
715 | /* |
716 | * if only one frame, send as non-aggregate | |
717 | */ | |
718 | if (bf->bf_nframes == 1) { | |
719 | ASSERT(bf->bf_lastfrm == bf_last); | |
f078f209 | 720 | |
e8324357 | 721 | bf->bf_state.bf_type &= ~BUF_AGGR; |
f078f209 | 722 | /* |
e8324357 S |
723 | * clear aggr bits for every descriptor |
724 | * XXX TODO: is there a way to optimize it? | |
f078f209 | 725 | */ |
e8324357 S |
726 | list_for_each_entry(tbf, &bf_q, list) { |
727 | ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc); | |
728 | } | |
f078f209 | 729 | |
e8324357 S |
730 | ath_buf_set_rate(sc, bf); |
731 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
732 | continue; | |
733 | } | |
f078f209 | 734 | |
e8324357 S |
735 | /* |
736 | * setup first desc with rate and aggr info | |
737 | */ | |
738 | bf->bf_state.bf_type |= BUF_AGGR; | |
739 | ath_buf_set_rate(sc, bf); | |
740 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 741 | |
e8324357 S |
742 | /* |
743 | * anchor last frame of aggregate correctly | |
744 | */ | |
745 | ASSERT(bf_lastaggr); | |
746 | ASSERT(bf_lastaggr->bf_lastfrm == bf_last); | |
747 | tbf = bf_lastaggr; | |
748 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | |
f078f209 | 749 | |
e8324357 S |
750 | /* XXX: We don't enter into this loop, consider removing this */ |
751 | while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) { | |
752 | tbf = list_entry(tbf->list.next, struct ath_buf, list); | |
753 | ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc); | |
754 | } | |
f078f209 | 755 | |
e8324357 | 756 | txq->axq_aggr_depth++; |
f078f209 | 757 | |
e8324357 S |
758 | /* |
759 | * Normal aggregate, queue to hardware | |
760 | */ | |
761 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
f078f209 | 762 | |
e8324357 S |
763 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
764 | status != ATH_AGGR_BAW_CLOSED); | |
765 | } | |
766 | ||
767 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, | |
768 | u16 tid, u16 *ssn) | |
769 | { | |
770 | struct ath_atx_tid *txtid; | |
771 | struct ath_node *an; | |
772 | ||
773 | an = (struct ath_node *)sta->drv_priv; | |
774 | ||
775 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
776 | txtid = ATH_AN_2_TID(an, tid); | |
777 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
778 | ath_tx_pause_tid(sc, txtid); | |
f078f209 LR |
779 | } |
780 | ||
e8324357 S |
781 | return 0; |
782 | } | |
f078f209 | 783 | |
e8324357 S |
784 | int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
785 | { | |
786 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
787 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
788 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
789 | struct ath_buf *bf; | |
790 | struct list_head bf_head; | |
791 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 792 | |
e8324357 S |
793 | if (txtid->state & AGGR_CLEANUP) |
794 | return 0; | |
f078f209 | 795 | |
e8324357 S |
796 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
797 | txtid->addba_exchangeattempts = 0; | |
798 | return 0; | |
799 | } | |
f078f209 | 800 | |
e8324357 S |
801 | ath_tx_pause_tid(sc, txtid); |
802 | ||
803 | /* drop all software retried frames and mark this TID */ | |
804 | spin_lock_bh(&txq->axq_lock); | |
805 | while (!list_empty(&txtid->buf_q)) { | |
806 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
807 | if (!bf_isretried(bf)) { | |
808 | /* | |
809 | * NB: it's based on the assumption that | |
810 | * software retried frame will always stay | |
811 | * at the head of software queue. | |
812 | */ | |
813 | break; | |
814 | } | |
815 | list_cut_position(&bf_head, | |
816 | &txtid->buf_q, &bf->bf_lastfrm->list); | |
817 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); | |
818 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
819 | } |
820 | ||
e8324357 S |
821 | if (txtid->baw_head != txtid->baw_tail) { |
822 | spin_unlock_bh(&txq->axq_lock); | |
823 | txtid->state |= AGGR_CLEANUP; | |
824 | } else { | |
825 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
826 | txtid->addba_exchangeattempts = 0; | |
f078f209 | 827 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 828 | ath_tx_flush_tid(sc, txtid); |
f078f209 LR |
829 | } |
830 | ||
e8324357 S |
831 | return 0; |
832 | } | |
f078f209 | 833 | |
e8324357 S |
834 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
835 | { | |
836 | struct ath_atx_tid *txtid; | |
837 | struct ath_node *an; | |
838 | ||
839 | an = (struct ath_node *)sta->drv_priv; | |
840 | ||
841 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
842 | txtid = ATH_AN_2_TID(an, tid); | |
843 | txtid->baw_size = | |
844 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
845 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
846 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
847 | ath_tx_resume_tid(sc, txtid); | |
848 | } | |
f078f209 LR |
849 | } |
850 | ||
e8324357 | 851 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 852 | { |
e8324357 | 853 | struct ath_atx_tid *txtid; |
c4288390 | 854 | |
e8324357 S |
855 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
856 | return false; | |
c4288390 | 857 | |
e8324357 S |
858 | txtid = ATH_AN_2_TID(an, tidno); |
859 | ||
860 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { | |
861 | if (!(txtid->state & AGGR_ADDBA_PROGRESS) && | |
862 | (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) { | |
863 | txtid->addba_exchangeattempts++; | |
864 | return true; | |
c4288390 S |
865 | } |
866 | } | |
e8324357 S |
867 | |
868 | return false; | |
c4288390 S |
869 | } |
870 | ||
e8324357 S |
871 | /********************/ |
872 | /* Queue Management */ | |
873 | /********************/ | |
f078f209 | 874 | |
e8324357 S |
875 | static u32 ath_txq_depth(struct ath_softc *sc, int qnum) |
876 | { | |
877 | return sc->tx.txq[qnum].axq_depth; | |
878 | } | |
879 | ||
e8324357 S |
880 | static void ath_get_beaconconfig(struct ath_softc *sc, int if_id, |
881 | struct ath_beacon_config *conf) | |
f078f209 | 882 | { |
e8324357 | 883 | struct ieee80211_hw *hw = sc->hw; |
f078f209 | 884 | |
e8324357 | 885 | /* fill in beacon config data */ |
f078f209 | 886 | |
e8324357 S |
887 | conf->beacon_interval = hw->conf.beacon_int; |
888 | conf->listen_interval = 100; | |
889 | conf->dtim_count = 1; | |
890 | conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval; | |
891 | } | |
f078f209 LR |
892 | |
893 | static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx) | |
894 | { | |
895 | struct ath_hal *ah = sc->sc_ah; | |
55f5e4a9 | 896 | struct ath_txq *txq; |
ae8d2858 | 897 | int i, npend = 0; |
f078f209 | 898 | |
55f5e4a9 S |
899 | if (sc->sc_flags & SC_OP_INVALID) |
900 | return; | |
901 | ||
902 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
903 | if (ATH_TXQ_SETUP(sc, i)) { | |
904 | txq = &sc->tx.txq[i]; | |
905 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
906 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
f078f209 LR |
907 | } |
908 | } | |
909 | ||
910 | if (npend) { | |
ae8d2858 | 911 | int r; |
e8324357 | 912 | |
04bd4638 | 913 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); |
f078f209 LR |
914 | |
915 | spin_lock_bh(&sc->sc_resetlock); | |
ae8d2858 LR |
916 | r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, true); |
917 | if (r) | |
f078f209 | 918 | DPRINTF(sc, ATH_DBG_FATAL, |
ae8d2858 LR |
919 | "Unable to reset hardware; reset status %u\n", |
920 | r); | |
f078f209 LR |
921 | spin_unlock_bh(&sc->sc_resetlock); |
922 | } | |
923 | ||
924 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
925 | if (ATH_TXQ_SETUP(sc, i)) | |
b77f483f | 926 | ath_tx_draintxq(sc, &sc->tx.txq[i], retry_tx); |
f078f209 LR |
927 | } |
928 | } | |
929 | ||
e8324357 S |
930 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
931 | struct ath_txq *txq) | |
f078f209 | 932 | { |
e8324357 S |
933 | struct ath_atx_ac *ac, *ac_tmp; |
934 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 935 | |
e8324357 S |
936 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
937 | list_del(&ac->list); | |
938 | ac->sched = false; | |
939 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
940 | list_del(&tid->list); | |
941 | tid->sched = false; | |
942 | ath_tid_drain(sc, txq, tid); | |
943 | } | |
f078f209 LR |
944 | } |
945 | } | |
946 | ||
e8324357 | 947 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 948 | { |
e8324357 S |
949 | struct ath_hal *ah = sc->sc_ah; |
950 | struct ath9k_tx_queue_info qi; | |
951 | int qnum; | |
f078f209 | 952 | |
e8324357 S |
953 | memset(&qi, 0, sizeof(qi)); |
954 | qi.tqi_subtype = subtype; | |
955 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
956 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
957 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
958 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
959 | |
960 | /* | |
e8324357 S |
961 | * Enable interrupts only for EOL and DESC conditions. |
962 | * We mark tx descriptors to receive a DESC interrupt | |
963 | * when a tx queue gets deep; otherwise waiting for the | |
964 | * EOL to reap descriptors. Note that this is done to | |
965 | * reduce interrupt load and this only defers reaping | |
966 | * descriptors, never transmitting frames. Aside from | |
967 | * reducing interrupts this also permits more concurrency. | |
968 | * The only potential downside is if the tx queue backs | |
969 | * up in which case the top half of the kernel may backup | |
970 | * due to a lack of tx descriptors. | |
971 | * | |
972 | * The UAPSD queue is an exception, since we take a desc- | |
973 | * based intr on the EOSP frames. | |
f078f209 | 974 | */ |
e8324357 S |
975 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
976 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
977 | else | |
978 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
979 | TXQ_FLAG_TXDESCINT_ENABLE; | |
980 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
981 | if (qnum == -1) { | |
f078f209 | 982 | /* |
e8324357 S |
983 | * NB: don't print a message, this happens |
984 | * normally on parts with too few tx queues | |
f078f209 | 985 | */ |
e8324357 | 986 | return NULL; |
f078f209 | 987 | } |
e8324357 S |
988 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
989 | DPRINTF(sc, ATH_DBG_FATAL, | |
990 | "qnum %u out of range, max %u!\n", | |
991 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
992 | ath9k_hw_releasetxqueue(ah, qnum); | |
993 | return NULL; | |
994 | } | |
995 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
996 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 997 | |
e8324357 S |
998 | txq->axq_qnum = qnum; |
999 | txq->axq_link = NULL; | |
1000 | INIT_LIST_HEAD(&txq->axq_q); | |
1001 | INIT_LIST_HEAD(&txq->axq_acq); | |
1002 | spin_lock_init(&txq->axq_lock); | |
1003 | txq->axq_depth = 0; | |
1004 | txq->axq_aggr_depth = 0; | |
1005 | txq->axq_totalqueued = 0; | |
1006 | txq->axq_linkbuf = NULL; | |
1007 | sc->tx.txqsetup |= 1<<qnum; | |
1008 | } | |
1009 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
1010 | } |
1011 | ||
e8324357 | 1012 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 1013 | { |
e8324357 | 1014 | int qnum; |
f078f209 | 1015 | |
e8324357 S |
1016 | switch (qtype) { |
1017 | case ATH9K_TX_QUEUE_DATA: | |
1018 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
1019 | DPRINTF(sc, ATH_DBG_FATAL, | |
1020 | "HAL AC %u out of range, max %zu!\n", | |
1021 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1022 | return -1; | |
1023 | } | |
1024 | qnum = sc->tx.hwq_map[haltype]; | |
1025 | break; | |
1026 | case ATH9K_TX_QUEUE_BEACON: | |
1027 | qnum = sc->beacon.beaconq; | |
1028 | break; | |
1029 | case ATH9K_TX_QUEUE_CAB: | |
1030 | qnum = sc->beacon.cabq->axq_qnum; | |
1031 | break; | |
1032 | default: | |
1033 | qnum = -1; | |
1034 | } | |
1035 | return qnum; | |
1036 | } | |
f078f209 | 1037 | |
e8324357 S |
1038 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
1039 | { | |
1040 | struct ath_txq *txq = NULL; | |
1041 | int qnum; | |
f078f209 | 1042 | |
e8324357 S |
1043 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
1044 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 1045 | |
e8324357 S |
1046 | spin_lock_bh(&txq->axq_lock); |
1047 | ||
1048 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
1049 | DPRINTF(sc, ATH_DBG_FATAL, | |
1050 | "TX queue: %d is full, depth: %d\n", | |
1051 | qnum, txq->axq_depth); | |
1052 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
1053 | txq->stopped = 1; | |
1054 | spin_unlock_bh(&txq->axq_lock); | |
1055 | return NULL; | |
f078f209 LR |
1056 | } |
1057 | ||
e8324357 S |
1058 | spin_unlock_bh(&txq->axq_lock); |
1059 | ||
1060 | return txq; | |
1061 | } | |
1062 | ||
1063 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
1064 | struct ath9k_tx_queue_info *qinfo) | |
1065 | { | |
1066 | struct ath_hal *ah = sc->sc_ah; | |
1067 | int error = 0; | |
1068 | struct ath9k_tx_queue_info qi; | |
1069 | ||
1070 | if (qnum == sc->beacon.beaconq) { | |
1071 | /* | |
1072 | * XXX: for beacon queue, we just save the parameter. | |
1073 | * It will be picked up by ath_beaconq_config when | |
1074 | * it's necessary. | |
1075 | */ | |
1076 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 1077 | return 0; |
e8324357 | 1078 | } |
f078f209 | 1079 | |
e8324357 S |
1080 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
1081 | ||
1082 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
1083 | qi.tqi_aifs = qinfo->tqi_aifs; | |
1084 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
1085 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
1086 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
1087 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
1088 | ||
1089 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
1090 | DPRINTF(sc, ATH_DBG_FATAL, | |
1091 | "Unable to update hardware queue %u!\n", qnum); | |
1092 | error = -EIO; | |
1093 | } else { | |
1094 | ath9k_hw_resettxqueue(ah, qnum); | |
1095 | } | |
1096 | ||
1097 | return error; | |
1098 | } | |
1099 | ||
1100 | int ath_cabq_update(struct ath_softc *sc) | |
1101 | { | |
1102 | struct ath9k_tx_queue_info qi; | |
1103 | int qnum = sc->beacon.cabq->axq_qnum; | |
1104 | struct ath_beacon_config conf; | |
f078f209 | 1105 | |
e8324357 | 1106 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1107 | /* |
e8324357 | 1108 | * Ensure the readytime % is within the bounds. |
f078f209 | 1109 | */ |
e8324357 S |
1110 | if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1111 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1112 | else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1113 | sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1114 | |
e8324357 S |
1115 | ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf); |
1116 | qi.tqi_readyTime = | |
1117 | (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100; | |
1118 | ath_txq_update(sc, qnum, &qi); | |
1119 | ||
1120 | return 0; | |
f078f209 LR |
1121 | } |
1122 | ||
e8324357 | 1123 | void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) |
f078f209 | 1124 | { |
e8324357 S |
1125 | struct ath_buf *bf, *lastbf; |
1126 | struct list_head bf_head; | |
f078f209 | 1127 | |
e8324357 | 1128 | INIT_LIST_HEAD(&bf_head); |
f078f209 LR |
1129 | |
1130 | /* | |
e8324357 S |
1131 | * NB: this assumes output has been stopped and |
1132 | * we do not need to block ath_tx_tasklet | |
f078f209 | 1133 | */ |
e8324357 S |
1134 | for (;;) { |
1135 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1136 | |
e8324357 S |
1137 | if (list_empty(&txq->axq_q)) { |
1138 | txq->axq_link = NULL; | |
1139 | txq->axq_linkbuf = NULL; | |
1140 | spin_unlock_bh(&txq->axq_lock); | |
1141 | break; | |
1142 | } | |
f078f209 | 1143 | |
e8324357 | 1144 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1145 | |
e8324357 S |
1146 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
1147 | list_del(&bf->list); | |
1148 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1149 | |
e8324357 S |
1150 | spin_lock_bh(&sc->tx.txbuflock); |
1151 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1152 | spin_unlock_bh(&sc->tx.txbuflock); | |
1153 | continue; | |
1154 | } | |
f078f209 | 1155 | |
e8324357 S |
1156 | lastbf = bf->bf_lastbf; |
1157 | if (!retry_tx) | |
1158 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1159 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1160 | |
e8324357 S |
1161 | /* remove ath_buf's of the same mpdu from txq */ |
1162 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1163 | txq->axq_depth--; | |
f078f209 | 1164 | |
e8324357 S |
1165 | spin_unlock_bh(&txq->axq_lock); |
1166 | ||
1167 | if (bf_isampdu(bf)) | |
1168 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0); | |
1169 | else | |
1170 | ath_tx_complete_buf(sc, bf, &bf_head, 0, 0); | |
f078f209 LR |
1171 | } |
1172 | ||
e8324357 S |
1173 | /* flush any pending frames if aggregation is enabled */ |
1174 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1175 | if (!retry_tx) { | |
1176 | spin_lock_bh(&txq->axq_lock); | |
1177 | ath_txq_drain_pending_buffers(sc, txq); | |
1178 | spin_unlock_bh(&txq->axq_lock); | |
1179 | } | |
1180 | } | |
f078f209 LR |
1181 | } |
1182 | ||
e8324357 | 1183 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1184 | { |
e8324357 S |
1185 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1186 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
1187 | } | |
f078f209 | 1188 | |
e8324357 S |
1189 | void ath_draintxq(struct ath_softc *sc, bool retry_tx) |
1190 | { | |
1191 | if (!(sc->sc_flags & SC_OP_INVALID)) | |
1192 | (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
f078f209 | 1193 | |
e8324357 S |
1194 | ath_drain_txdataq(sc, retry_tx); |
1195 | } | |
f078f209 | 1196 | |
e8324357 S |
1197 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1198 | { | |
1199 | struct ath_atx_ac *ac; | |
1200 | struct ath_atx_tid *tid; | |
f078f209 | 1201 | |
e8324357 S |
1202 | if (list_empty(&txq->axq_acq)) |
1203 | return; | |
f078f209 | 1204 | |
e8324357 S |
1205 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1206 | list_del(&ac->list); | |
1207 | ac->sched = false; | |
f078f209 | 1208 | |
e8324357 S |
1209 | do { |
1210 | if (list_empty(&ac->tid_q)) | |
1211 | return; | |
f078f209 | 1212 | |
e8324357 S |
1213 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1214 | list_del(&tid->list); | |
1215 | tid->sched = false; | |
f078f209 | 1216 | |
e8324357 S |
1217 | if (tid->paused) |
1218 | continue; | |
f078f209 | 1219 | |
e8324357 S |
1220 | if ((txq->axq_depth % 2) == 0) |
1221 | ath_tx_sched_aggr(sc, txq, tid); | |
f078f209 LR |
1222 | |
1223 | /* | |
e8324357 S |
1224 | * add tid to round-robin queue if more frames |
1225 | * are pending for the tid | |
f078f209 | 1226 | */ |
e8324357 S |
1227 | if (!list_empty(&tid->buf_q)) |
1228 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1229 | |
e8324357 S |
1230 | break; |
1231 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1232 | |
e8324357 S |
1233 | if (!list_empty(&ac->tid_q)) { |
1234 | if (!ac->sched) { | |
1235 | ac->sched = true; | |
1236 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1237 | } |
e8324357 S |
1238 | } |
1239 | } | |
f078f209 | 1240 | |
e8324357 S |
1241 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1242 | { | |
1243 | struct ath_txq *txq; | |
f078f209 | 1244 | |
e8324357 S |
1245 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1246 | DPRINTF(sc, ATH_DBG_FATAL, | |
1247 | "HAL AC %u out of range, max %zu!\n", | |
1248 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1249 | return 0; | |
1250 | } | |
1251 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1252 | if (txq != NULL) { | |
1253 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1254 | return 1; | |
1255 | } else | |
1256 | return 0; | |
f078f209 LR |
1257 | } |
1258 | ||
e8324357 S |
1259 | /***********/ |
1260 | /* TX, DMA */ | |
1261 | /***********/ | |
1262 | ||
f078f209 | 1263 | /* |
e8324357 S |
1264 | * Insert a chain of ath_buf (descriptors) on a txq and |
1265 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1266 | */ |
e8324357 S |
1267 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1268 | struct list_head *head) | |
f078f209 | 1269 | { |
e8324357 S |
1270 | struct ath_hal *ah = sc->sc_ah; |
1271 | struct ath_buf *bf; | |
f078f209 | 1272 | |
e8324357 S |
1273 | /* |
1274 | * Insert the frame on the outbound list and | |
1275 | * pass it on to the hardware. | |
1276 | */ | |
f078f209 | 1277 | |
e8324357 S |
1278 | if (list_empty(head)) |
1279 | return; | |
f078f209 | 1280 | |
e8324357 | 1281 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1282 | |
e8324357 S |
1283 | list_splice_tail_init(head, &txq->axq_q); |
1284 | txq->axq_depth++; | |
1285 | txq->axq_totalqueued++; | |
1286 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); | |
f078f209 | 1287 | |
e8324357 S |
1288 | DPRINTF(sc, ATH_DBG_QUEUE, |
1289 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1290 | |
e8324357 S |
1291 | if (txq->axq_link == NULL) { |
1292 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1293 | DPRINTF(sc, ATH_DBG_XMIT, | |
1294 | "TXDP[%u] = %llx (%p)\n", | |
1295 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1296 | } else { | |
1297 | *txq->axq_link = bf->bf_daddr; | |
1298 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1299 | txq->axq_qnum, txq->axq_link, | |
1300 | ito64(bf->bf_daddr), bf->bf_desc); | |
1301 | } | |
1302 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1303 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1304 | } | |
f078f209 | 1305 | |
e8324357 S |
1306 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1307 | { | |
1308 | struct ath_buf *bf = NULL; | |
f078f209 | 1309 | |
e8324357 | 1310 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1311 | |
e8324357 S |
1312 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1313 | spin_unlock_bh(&sc->tx.txbuflock); | |
1314 | return NULL; | |
1315 | } | |
f078f209 | 1316 | |
e8324357 S |
1317 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1318 | list_del(&bf->list); | |
f078f209 | 1319 | |
e8324357 | 1320 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1321 | |
e8324357 | 1322 | return bf; |
f078f209 LR |
1323 | } |
1324 | ||
e8324357 S |
1325 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1326 | struct list_head *bf_head, | |
1327 | struct ath_tx_control *txctl) | |
f078f209 LR |
1328 | { |
1329 | struct ath_buf *bf; | |
f078f209 | 1330 | |
e8324357 | 1331 | BUG_ON(list_empty(bf_head)); |
f078f209 | 1332 | |
e8324357 S |
1333 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1334 | bf->bf_state.bf_type |= BUF_AMPDU; | |
f078f209 | 1335 | |
e8324357 S |
1336 | /* |
1337 | * Do not queue to h/w when any of the following conditions is true: | |
1338 | * - there are pending frames in software queue | |
1339 | * - the TID is currently paused for ADDBA/BAR request | |
1340 | * - seqno is not within block-ack window | |
1341 | * - h/w queue depth exceeds low water mark | |
1342 | */ | |
1343 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1344 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1345 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1346 | /* |
e8324357 S |
1347 | * Add this frame to software queue for scheduling later |
1348 | * for aggregation. | |
f078f209 | 1349 | */ |
e8324357 S |
1350 | list_splice_tail_init(bf_head, &tid->buf_q); |
1351 | ath_tx_queue_tid(txctl->txq, tid); | |
1352 | return; | |
1353 | } | |
1354 | ||
1355 | /* Add sub-frame to BAW */ | |
1356 | ath_tx_addto_baw(sc, tid, bf); | |
1357 | ||
1358 | /* Queue to h/w without aggregation */ | |
1359 | bf->bf_nframes = 1; | |
1360 | bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */ | |
1361 | ath_buf_set_rate(sc, bf); | |
1362 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
1363 | ||
1364 | return; | |
1365 | } | |
1366 | ||
1367 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, | |
1368 | struct ath_atx_tid *tid, | |
1369 | struct list_head *bf_head) | |
1370 | { | |
1371 | struct ath_buf *bf; | |
1372 | ||
1373 | BUG_ON(list_empty(bf_head)); | |
1374 | ||
1375 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1376 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1377 | ||
1378 | /* update starting sequence number for subsequent ADDBA request */ | |
1379 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1380 | ||
1381 | bf->bf_nframes = 1; | |
1382 | bf->bf_lastbf = bf->bf_lastfrm; | |
1383 | ath_buf_set_rate(sc, bf); | |
1384 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
1385 | } | |
1386 | ||
1387 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) | |
1388 | { | |
1389 | struct ieee80211_hdr *hdr; | |
1390 | enum ath9k_pkt_type htype; | |
1391 | __le16 fc; | |
1392 | ||
1393 | hdr = (struct ieee80211_hdr *)skb->data; | |
1394 | fc = hdr->frame_control; | |
1395 | ||
1396 | if (ieee80211_is_beacon(fc)) | |
1397 | htype = ATH9K_PKT_TYPE_BEACON; | |
1398 | else if (ieee80211_is_probe_resp(fc)) | |
1399 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1400 | else if (ieee80211_is_atim(fc)) | |
1401 | htype = ATH9K_PKT_TYPE_ATIM; | |
1402 | else if (ieee80211_is_pspoll(fc)) | |
1403 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1404 | else | |
1405 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1406 | ||
1407 | return htype; | |
1408 | } | |
1409 | ||
1410 | static bool is_pae(struct sk_buff *skb) | |
1411 | { | |
1412 | struct ieee80211_hdr *hdr; | |
1413 | __le16 fc; | |
1414 | ||
1415 | hdr = (struct ieee80211_hdr *)skb->data; | |
1416 | fc = hdr->frame_control; | |
1417 | ||
1418 | if (ieee80211_is_data(fc)) { | |
1419 | if (ieee80211_is_nullfunc(fc) || | |
1420 | /* Port Access Entity (IEEE 802.1X) */ | |
1421 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1422 | return true; | |
1423 | } | |
1424 | } | |
1425 | ||
1426 | return false; | |
1427 | } | |
1428 | ||
1429 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1430 | { | |
1431 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1432 | ||
1433 | if (tx_info->control.hw_key) { | |
1434 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1435 | return ATH9K_KEY_TYPE_WEP; | |
1436 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1437 | return ATH9K_KEY_TYPE_TKIP; | |
1438 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1439 | return ATH9K_KEY_TYPE_AES; | |
1440 | } | |
1441 | ||
1442 | return ATH9K_KEY_TYPE_CLEAR; | |
1443 | } | |
1444 | ||
1445 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1446 | struct ath_buf *bf) | |
1447 | { | |
1448 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1449 | struct ieee80211_hdr *hdr; | |
1450 | struct ath_node *an; | |
1451 | struct ath_atx_tid *tid; | |
1452 | __le16 fc; | |
1453 | u8 *qc; | |
1454 | ||
1455 | if (!tx_info->control.sta) | |
1456 | return; | |
1457 | ||
1458 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1459 | hdr = (struct ieee80211_hdr *)skb->data; | |
1460 | fc = hdr->frame_control; | |
1461 | ||
1462 | if (ieee80211_is_data_qos(fc)) { | |
1463 | qc = ieee80211_get_qos_ctl(hdr); | |
1464 | bf->bf_tidno = qc[0] & 0xf; | |
1465 | } | |
1466 | ||
1467 | /* | |
1468 | * For HT capable stations, we save tidno for later use. | |
1469 | * We also override seqno set by upper layer with the one | |
1470 | * in tx aggregation state. | |
1471 | * | |
1472 | * If fragmentation is on, the sequence number is | |
1473 | * not overridden, since it has been | |
1474 | * incremented by the fragmentation routine. | |
1475 | * | |
1476 | * FIXME: check if the fragmentation threshold exceeds | |
1477 | * IEEE80211 max. | |
1478 | */ | |
1479 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1480 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1481 | IEEE80211_SEQ_SEQ_SHIFT); | |
1482 | bf->bf_seqno = tid->seq_next; | |
1483 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1484 | } | |
1485 | ||
1486 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1487 | struct ath_txq *txq) | |
1488 | { | |
1489 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1490 | int flags = 0; | |
1491 | ||
1492 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1493 | flags |= ATH9K_TXDESC_INTREQ; | |
1494 | ||
1495 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1496 | flags |= ATH9K_TXDESC_NOACK; | |
1497 | if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1498 | flags |= ATH9K_TXDESC_RTSENA; | |
1499 | ||
1500 | return flags; | |
1501 | } | |
1502 | ||
1503 | /* | |
1504 | * rix - rate index | |
1505 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1506 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1507 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1508 | */ | |
1509 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1510 | int width, int half_gi, bool shortPreamble) | |
1511 | { | |
1512 | struct ath_rate_table *rate_table = sc->cur_rate_table; | |
1513 | u32 nbits, nsymbits, duration, nsymbols; | |
1514 | u8 rc; | |
1515 | int streams, pktlen; | |
1516 | ||
1517 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1518 | rc = rate_table->info[rix].ratecode; | |
1519 | ||
1520 | /* for legacy rates, use old function to compute packet duration */ | |
1521 | if (!IS_HT_RATE(rc)) | |
1522 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1523 | rix, shortPreamble); | |
1524 | ||
1525 | /* find number of symbols: PLCP + data */ | |
1526 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1527 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1528 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1529 | ||
1530 | if (!half_gi) | |
1531 | duration = SYMBOL_TIME(nsymbols); | |
1532 | else | |
1533 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1534 | ||
1535 | /* addup duration for legacy/ht training and signal fields */ | |
1536 | streams = HT_RC_2_STREAMS(rc); | |
1537 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1538 | ||
1539 | return duration; | |
1540 | } | |
1541 | ||
1542 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1543 | { | |
1544 | struct ath_hal *ah = sc->sc_ah; | |
1545 | struct ath_rate_table *rt; | |
1546 | struct ath_desc *ds = bf->bf_desc; | |
1547 | struct ath_desc *lastds = bf->bf_lastbf->bf_desc; | |
1548 | struct ath9k_11n_rate_series series[4]; | |
1549 | struct sk_buff *skb; | |
1550 | struct ieee80211_tx_info *tx_info; | |
1551 | struct ieee80211_tx_rate *rates; | |
1552 | struct ieee80211_hdr *hdr; | |
1553 | struct ieee80211_hw *hw = sc->hw; | |
1554 | int i, flags, rtsctsena = 0, enable_g_protection = 0; | |
1555 | u32 ctsduration = 0; | |
1556 | u8 rix = 0, cix, ctsrate = 0; | |
1557 | __le16 fc; | |
1558 | ||
1559 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1560 | ||
1561 | skb = (struct sk_buff *)bf->bf_mpdu; | |
1562 | hdr = (struct ieee80211_hdr *)skb->data; | |
1563 | fc = hdr->frame_control; | |
1564 | tx_info = IEEE80211_SKB_CB(skb); | |
1565 | rates = tx_info->control.rates; | |
1566 | ||
1567 | if (ieee80211_has_morefrags(fc) || | |
1568 | (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) { | |
1569 | rates[1].count = rates[2].count = rates[3].count = 0; | |
1570 | rates[1].idx = rates[2].idx = rates[3].idx = 0; | |
1571 | rates[0].count = ATH_TXMAXTRY; | |
1572 | } | |
1573 | ||
1574 | /* get the cix for the lowest valid rix */ | |
1575 | rt = sc->cur_rate_table; | |
1576 | for (i = 3; i >= 0; i--) { | |
1577 | if (rates[i].count && (rates[i].idx >= 0)) { | |
1578 | rix = rates[i].idx; | |
1579 | break; | |
1580 | } | |
1581 | } | |
1582 | ||
1583 | flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA)); | |
1584 | cix = rt->info[rix].ctrl_rate; | |
1585 | ||
1586 | /* All protection frames are transmited at 2Mb/s for 802.11g, | |
1587 | * otherwise we transmit them at 1Mb/s */ | |
1588 | if (hw->conf.channel->band == IEEE80211_BAND_2GHZ && | |
1589 | !conf_is_ht(&hw->conf)) | |
1590 | enable_g_protection = 1; | |
1591 | ||
1592 | /* | |
1593 | * If 802.11g protection is enabled, determine whether to use RTS/CTS or | |
1594 | * just CTS. Note that this is only done for OFDM/HT unicast frames. | |
1595 | */ | |
1596 | if (sc->sc_protmode != PROT_M_NONE && !(bf->bf_flags & ATH9K_TXDESC_NOACK) | |
1597 | && (rt->info[rix].phy == WLAN_RC_PHY_OFDM || | |
1598 | WLAN_RC_PHY_HT(rt->info[rix].phy))) { | |
1599 | if (sc->sc_protmode == PROT_M_RTSCTS) | |
1600 | flags = ATH9K_TXDESC_RTSENA; | |
1601 | else if (sc->sc_protmode == PROT_M_CTSONLY) | |
1602 | flags = ATH9K_TXDESC_CTSENA; | |
1603 | ||
1604 | cix = rt->info[enable_g_protection].ctrl_rate; | |
1605 | rtsctsena = 1; | |
1606 | } | |
1607 | ||
1608 | /* For 11n, the default behavior is to enable RTS for hw retried frames. | |
1609 | * We enable the global flag here and let rate series flags determine | |
1610 | * which rates will actually use RTS. | |
1611 | */ | |
1612 | if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) { | |
1613 | /* 802.11g protection not needed, use our default behavior */ | |
1614 | if (!rtsctsena) | |
1615 | flags = ATH9K_TXDESC_RTSENA; | |
1616 | } | |
1617 | ||
1618 | /* Set protection if aggregate protection on */ | |
1619 | if (sc->sc_config.ath_aggr_prot && | |
1620 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { | |
1621 | flags = ATH9K_TXDESC_RTSENA; | |
1622 | cix = rt->info[enable_g_protection].ctrl_rate; | |
1623 | rtsctsena = 1; | |
1624 | } | |
1625 | ||
1626 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
1627 | if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit)) | |
1628 | flags &= ~(ATH9K_TXDESC_RTSENA); | |
1629 | ||
1630 | /* | |
1631 | * CTS transmit rate is derived from the transmit rate by looking in the | |
1632 | * h/w rate table. We must also factor in whether or not a short | |
1633 | * preamble is to be used. NB: cix is set above where RTS/CTS is enabled | |
1634 | */ | |
1635 | ctsrate = rt->info[cix].ratecode | | |
1636 | (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0); | |
1637 | ||
1638 | for (i = 0; i < 4; i++) { | |
1639 | if (!rates[i].count || (rates[i].idx < 0)) | |
1640 | continue; | |
1641 | ||
1642 | rix = rates[i].idx; | |
1643 | ||
1644 | series[i].Rate = rt->info[rix].ratecode | | |
1645 | (bf_isshpreamble(bf) ? rt->info[rix].short_preamble : 0); | |
1646 | ||
1647 | series[i].Tries = rates[i].count; | |
1648 | ||
1649 | series[i].RateFlags = ( | |
1650 | (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) ? | |
1651 | ATH9K_RATESERIES_RTS_CTS : 0) | | |
1652 | ((rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? | |
1653 | ATH9K_RATESERIES_2040 : 0) | | |
1654 | ((rates[i].flags & IEEE80211_TX_RC_SHORT_GI) ? | |
1655 | ATH9K_RATESERIES_HALFGI : 0); | |
1656 | ||
1657 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1658 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1659 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
1660 | bf_isshpreamble(bf)); | |
f078f209 | 1661 | |
e8324357 | 1662 | series[i].ChSel = sc->sc_tx_chainmask; |
f078f209 | 1663 | |
e8324357 S |
1664 | if (rtsctsena) |
1665 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
f078f209 LR |
1666 | } |
1667 | ||
e8324357 S |
1668 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
1669 | ath9k_hw_set11n_ratescenario(ah, ds, lastds, !bf_ispspoll(bf), | |
1670 | ctsrate, ctsduration, | |
1671 | series, 4, flags); | |
f078f209 | 1672 | |
e8324357 S |
1673 | if (sc->sc_config.ath_aggr_prot && flags) |
1674 | ath9k_hw_set11n_burstduration(ah, ds, 8192); | |
f078f209 LR |
1675 | } |
1676 | ||
f8316df1 | 1677 | static int ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf, |
8f93b8b3 | 1678 | struct sk_buff *skb, |
528f0c6b | 1679 | struct ath_tx_control *txctl) |
f078f209 | 1680 | { |
528f0c6b S |
1681 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1682 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1683 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1684 | int hdrlen; |
1685 | __le16 fc; | |
e022edbd | 1686 | |
c112d0c5 LR |
1687 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1688 | if (unlikely(!tx_info_priv)) | |
1689 | return -ENOMEM; | |
a8efee4f | 1690 | tx_info->rate_driver_data[0] = tx_info_priv; |
528f0c6b S |
1691 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1692 | fc = hdr->frame_control; | |
f078f209 | 1693 | |
528f0c6b | 1694 | ATH_TXBUF_RESET(bf); |
f078f209 | 1695 | |
528f0c6b | 1696 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 S |
1697 | |
1698 | ieee80211_is_data(fc) ? | |
1699 | (bf->bf_state.bf_type |= BUF_DATA) : | |
1700 | (bf->bf_state.bf_type &= ~BUF_DATA); | |
1701 | ieee80211_is_back_req(fc) ? | |
1702 | (bf->bf_state.bf_type |= BUF_BAR) : | |
1703 | (bf->bf_state.bf_type &= ~BUF_BAR); | |
1704 | ieee80211_is_pspoll(fc) ? | |
1705 | (bf->bf_state.bf_type |= BUF_PSPOLL) : | |
1706 | (bf->bf_state.bf_type &= ~BUF_PSPOLL); | |
672840ac | 1707 | (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ? |
cd3d39a6 S |
1708 | (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) : |
1709 | (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE); | |
ecf70441 | 1710 | (conf_is_ht(&sc->hw->conf) && !is_pae(skb) && |
528f0c6b S |
1711 | (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ? |
1712 | (bf->bf_state.bf_type |= BUF_HT) : | |
1713 | (bf->bf_state.bf_type &= ~BUF_HT); | |
1714 | ||
1715 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1716 | ||
528f0c6b S |
1717 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
1718 | ||
1719 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { | |
1720 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1721 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1722 | } else { | |
1723 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1724 | } | |
1725 | ||
d3a1db1c | 1726 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1727 | assign_aggr_tid_seqno(skb, bf); |
1728 | ||
f078f209 | 1729 | bf->bf_mpdu = skb; |
f8316df1 | 1730 | |
7da3c55c GJ |
1731 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1732 | skb->len, DMA_TO_DEVICE); | |
1733 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 LR |
1734 | bf->bf_mpdu = NULL; |
1735 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 1736 | "dma_mapping_error() on TX\n"); |
f8316df1 LR |
1737 | return -ENOMEM; |
1738 | } | |
1739 | ||
528f0c6b | 1740 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1741 | return 0; |
528f0c6b S |
1742 | } |
1743 | ||
1744 | /* FIXME: tx power */ | |
1745 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1746 | struct ath_tx_control *txctl) |
1747 | { | |
1748 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; | |
1749 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1750 | struct ath_node *an = NULL; | |
1751 | struct list_head bf_head; | |
1752 | struct ath_desc *ds; | |
1753 | struct ath_atx_tid *tid; | |
1754 | struct ath_hal *ah = sc->sc_ah; | |
1755 | int frm_type; | |
1756 | ||
528f0c6b S |
1757 | frm_type = get_hw_packet_type(skb); |
1758 | ||
1759 | INIT_LIST_HEAD(&bf_head); | |
1760 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1761 | |
f078f209 LR |
1762 | ds = bf->bf_desc; |
1763 | ds->ds_link = 0; | |
1764 | ds->ds_data = bf->bf_buf_addr; | |
1765 | ||
528f0c6b S |
1766 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1767 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1768 | ||
1769 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1770 | skb->len, /* segment length */ |
1771 | true, /* first segment */ | |
1772 | true, /* last segment */ | |
1773 | ds); /* first descriptor */ | |
f078f209 LR |
1774 | |
1775 | bf->bf_lastfrm = bf; | |
f078f209 | 1776 | |
528f0c6b | 1777 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1778 | |
f1617967 JL |
1779 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1780 | tx_info->control.sta) { | |
1781 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1782 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1783 | ||
528f0c6b | 1784 | if (ath_aggr_query(sc, an, bf->bf_tidno)) { |
f078f209 LR |
1785 | /* |
1786 | * Try aggregation if it's a unicast data frame | |
1787 | * and the destination is HT capable. | |
1788 | */ | |
528f0c6b | 1789 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1790 | } else { |
1791 | /* | |
528f0c6b S |
1792 | * Send this frame as regular when ADDBA |
1793 | * exchange is neither complete nor pending. | |
f078f209 | 1794 | */ |
528f0c6b S |
1795 | ath_tx_send_normal(sc, txctl->txq, |
1796 | tid, &bf_head); | |
f078f209 LR |
1797 | } |
1798 | } else { | |
1799 | bf->bf_lastbf = bf; | |
1800 | bf->bf_nframes = 1; | |
f078f209 | 1801 | |
528f0c6b S |
1802 | ath_buf_set_rate(sc, bf); |
1803 | ath_tx_txqaddbuf(sc, txctl->txq, &bf_head); | |
f078f209 | 1804 | } |
528f0c6b S |
1805 | |
1806 | spin_unlock_bh(&txctl->txq->axq_lock); | |
f078f209 LR |
1807 | } |
1808 | ||
f8316df1 | 1809 | /* Upon failure caller should free skb */ |
528f0c6b S |
1810 | int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb, |
1811 | struct ath_tx_control *txctl) | |
f078f209 | 1812 | { |
528f0c6b | 1813 | struct ath_buf *bf; |
f8316df1 | 1814 | int r; |
f078f209 | 1815 | |
528f0c6b S |
1816 | bf = ath_tx_get_buffer(sc); |
1817 | if (!bf) { | |
04bd4638 | 1818 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1819 | return -1; |
1820 | } | |
1821 | ||
f8316df1 LR |
1822 | r = ath_tx_setup_buffer(sc, bf, skb, txctl); |
1823 | if (unlikely(r)) { | |
c112d0c5 LR |
1824 | struct ath_txq *txq = txctl->txq; |
1825 | ||
f8316df1 | 1826 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1827 | |
1828 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1829 | * guarantee this will happen by knowing beforehand that | |
1830 | * we will at least have to run TX completionon one buffer | |
1831 | * on the queue */ | |
1832 | spin_lock_bh(&txq->axq_lock); | |
1833 | if (ath_txq_depth(sc, txq->axq_qnum) > 1) { | |
1834 | ieee80211_stop_queue(sc->hw, | |
1835 | skb_get_queue_mapping(skb)); | |
1836 | txq->stopped = 1; | |
1837 | } | |
1838 | spin_unlock_bh(&txq->axq_lock); | |
1839 | ||
b77f483f S |
1840 | spin_lock_bh(&sc->tx.txbuflock); |
1841 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1842 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1843 | |
f8316df1 LR |
1844 | return r; |
1845 | } | |
1846 | ||
8f93b8b3 | 1847 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1848 | |
528f0c6b | 1849 | return 0; |
f078f209 LR |
1850 | } |
1851 | ||
e8324357 | 1852 | void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb) |
f078f209 | 1853 | { |
e8324357 S |
1854 | int hdrlen, padsize; |
1855 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1856 | struct ath_tx_control txctl; | |
f078f209 | 1857 | |
e8324357 | 1858 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1859 | |
1860 | /* | |
e8324357 S |
1861 | * As a temporary workaround, assign seq# here; this will likely need |
1862 | * to be cleaned up to work better with Beacon transmission and virtual | |
1863 | * BSSes. | |
f078f209 | 1864 | */ |
e8324357 S |
1865 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1866 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1867 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1868 | sc->tx.seq_no += 0x10; | |
1869 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1870 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1871 | } |
f078f209 | 1872 | |
e8324357 S |
1873 | /* Add the padding after the header if this is not already done */ |
1874 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1875 | if (hdrlen & 3) { | |
1876 | padsize = hdrlen % 4; | |
1877 | if (skb_headroom(skb) < padsize) { | |
1878 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1879 | dev_kfree_skb_any(skb); | |
1880 | return; | |
1881 | } | |
1882 | skb_push(skb, padsize); | |
1883 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1884 | } |
f078f209 | 1885 | |
e8324357 | 1886 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1887 | |
e8324357 | 1888 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1889 | |
e8324357 S |
1890 | if (ath_tx_start(sc, skb, &txctl) != 0) { |
1891 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); | |
1892 | goto exit; | |
f078f209 | 1893 | } |
f078f209 | 1894 | |
e8324357 S |
1895 | return; |
1896 | exit: | |
1897 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1898 | } |
1899 | ||
e8324357 S |
1900 | /*****************/ |
1901 | /* TX Completion */ | |
1902 | /*****************/ | |
528f0c6b | 1903 | |
e8324357 S |
1904 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
1905 | struct ath_xmit_status *tx_status) | |
528f0c6b | 1906 | { |
e8324357 S |
1907 | struct ieee80211_hw *hw = sc->hw; |
1908 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1909 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1910 | int hdrlen, padsize; | |
528f0c6b | 1911 | |
e8324357 | 1912 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1913 | |
e8324357 S |
1914 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1915 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1916 | kfree(tx_info_priv); | |
1917 | tx_info->rate_driver_data[0] = NULL; | |
1918 | } | |
528f0c6b | 1919 | |
e8324357 S |
1920 | if (tx_status->flags & ATH_TX_BAR) { |
1921 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
1922 | tx_status->flags &= ~ATH_TX_BAR; | |
1923 | } | |
1924 | ||
1925 | if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { | |
1926 | /* Frame was ACKed */ | |
1927 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1928 | } |
1929 | ||
e8324357 | 1930 | tx_info->status.rates[0].count = tx_status->retries + 1; |
528f0c6b | 1931 | |
e8324357 S |
1932 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1933 | padsize = hdrlen & 3; | |
1934 | if (padsize && hdrlen >= 24) { | |
1935 | /* | |
1936 | * Remove MAC header padding before giving the frame back to | |
1937 | * mac80211. | |
1938 | */ | |
1939 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1940 | skb_pull(skb, padsize); | |
1941 | } | |
528f0c6b | 1942 | |
e8324357 S |
1943 | ieee80211_tx_status(hw, skb); |
1944 | } | |
f078f209 | 1945 | |
e8324357 S |
1946 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
1947 | struct list_head *bf_q, | |
1948 | int txok, int sendbar) | |
f078f209 | 1949 | { |
e8324357 S |
1950 | struct sk_buff *skb = bf->bf_mpdu; |
1951 | struct ath_xmit_status tx_status; | |
1952 | unsigned long flags; | |
f078f209 | 1953 | |
e8324357 S |
1954 | /* |
1955 | * Set retry information. | |
1956 | * NB: Don't use the information in the descriptor, because the frame | |
1957 | * could be software retried. | |
1958 | */ | |
1959 | tx_status.retries = bf->bf_retries; | |
1960 | tx_status.flags = 0; | |
f078f209 | 1961 | |
e8324357 S |
1962 | if (sendbar) |
1963 | tx_status.flags = ATH_TX_BAR; | |
f078f209 | 1964 | |
e8324357 S |
1965 | if (!txok) { |
1966 | tx_status.flags |= ATH_TX_ERROR; | |
f078f209 | 1967 | |
e8324357 S |
1968 | if (bf_isxretried(bf)) |
1969 | tx_status.flags |= ATH_TX_XRETRY; | |
f078f209 LR |
1970 | } |
1971 | ||
e8324357 S |
1972 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
1973 | ath_tx_complete(sc, skb, &tx_status); | |
1974 | ||
1975 | /* | |
1976 | * Return the list of ath_buf of this mpdu to free queue | |
1977 | */ | |
1978 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1979 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1980 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1981 | } |
1982 | ||
e8324357 S |
1983 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1984 | int txok) | |
f078f209 | 1985 | { |
e8324357 S |
1986 | struct ath_buf *bf_last = bf->bf_lastbf; |
1987 | struct ath_desc *ds = bf_last->bf_desc; | |
1988 | u16 seq_st = 0; | |
1989 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1990 | int ba_index; | |
1991 | int nbad = 0; | |
1992 | int isaggr = 0; | |
f078f209 | 1993 | |
e8324357 S |
1994 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1995 | return 0; | |
f078f209 | 1996 | |
e8324357 S |
1997 | isaggr = bf_isaggr(bf); |
1998 | if (isaggr) { | |
1999 | seq_st = ATH_DS_BA_SEQ(ds); | |
2000 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
2001 | } | |
f078f209 | 2002 | |
e8324357 S |
2003 | while (bf) { |
2004 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
2005 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
2006 | nbad++; | |
2007 | ||
2008 | bf = bf->bf_next; | |
2009 | } | |
f078f209 | 2010 | |
e8324357 S |
2011 | return nbad; |
2012 | } | |
f078f209 | 2013 | |
e8324357 | 2014 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad) |
f078f209 | 2015 | { |
e8324357 S |
2016 | struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu; |
2017 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
2018 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
f078f209 | 2019 | |
e8324357 S |
2020 | tx_info_priv->update_rc = false; |
2021 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) | |
2022 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 2023 | |
e8324357 S |
2024 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
2025 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) { | |
2026 | if (bf_isdata(bf)) { | |
2027 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, | |
2028 | sizeof(tx_info_priv->tx)); | |
2029 | tx_info_priv->n_frames = bf->bf_nframes; | |
2030 | tx_info_priv->n_bad_frames = nbad; | |
2031 | tx_info_priv->update_rc = true; | |
2032 | } | |
f078f209 | 2033 | } |
f078f209 LR |
2034 | } |
2035 | ||
e8324357 | 2036 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 2037 | { |
e8324357 S |
2038 | struct ath_hal *ah = sc->sc_ah; |
2039 | struct ath_buf *bf, *lastbf, *bf_held = NULL; | |
f078f209 | 2040 | struct list_head bf_head; |
e8324357 S |
2041 | struct ath_desc *ds; |
2042 | int txok, nbad = 0; | |
2043 | int status; | |
f078f209 | 2044 | |
e8324357 S |
2045 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
2046 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
2047 | txq->axq_link); | |
f078f209 | 2048 | |
f078f209 LR |
2049 | for (;;) { |
2050 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
2051 | if (list_empty(&txq->axq_q)) { |
2052 | txq->axq_link = NULL; | |
2053 | txq->axq_linkbuf = NULL; | |
2054 | spin_unlock_bh(&txq->axq_lock); | |
2055 | break; | |
2056 | } | |
f078f209 LR |
2057 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2058 | ||
e8324357 S |
2059 | /* |
2060 | * There is a race condition that a BH gets scheduled | |
2061 | * after sw writes TxE and before hw re-load the last | |
2062 | * descriptor to get the newly chained one. | |
2063 | * Software must keep the last DONE descriptor as a | |
2064 | * holding descriptor - software does so by marking | |
2065 | * it with the STALE flag. | |
2066 | */ | |
2067 | bf_held = NULL; | |
f078f209 | 2068 | if (bf->bf_status & ATH_BUFSTATUS_STALE) { |
e8324357 S |
2069 | bf_held = bf; |
2070 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
2071 | /* FIXME: | |
2072 | * The holding descriptor is the last | |
2073 | * descriptor in queue. It's safe to remove | |
2074 | * the last holding descriptor in BH context. | |
2075 | */ | |
2076 | spin_unlock_bh(&txq->axq_lock); | |
2077 | break; | |
2078 | } else { | |
2079 | bf = list_entry(bf_held->list.next, | |
2080 | struct ath_buf, list); | |
2081 | } | |
f078f209 LR |
2082 | } |
2083 | ||
2084 | lastbf = bf->bf_lastbf; | |
e8324357 | 2085 | ds = lastbf->bf_desc; |
f078f209 | 2086 | |
e8324357 S |
2087 | status = ath9k_hw_txprocdesc(ah, ds); |
2088 | if (status == -EINPROGRESS) { | |
f078f209 | 2089 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2090 | break; |
f078f209 | 2091 | } |
e8324357 S |
2092 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
2093 | txq->axq_lastdsWithCTS = NULL; | |
2094 | if (ds == txq->axq_gatingds) | |
2095 | txq->axq_gatingds = NULL; | |
f078f209 | 2096 | |
e8324357 S |
2097 | /* |
2098 | * Remove ath_buf's of the same transmit unit from txq, | |
2099 | * however leave the last descriptor back as the holding | |
2100 | * descriptor for hw. | |
2101 | */ | |
2102 | lastbf->bf_status |= ATH_BUFSTATUS_STALE; | |
2103 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 2104 | |
e8324357 S |
2105 | if (!list_is_singular(&lastbf->list)) |
2106 | list_cut_position(&bf_head, | |
2107 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2108 | |
e8324357 | 2109 | txq->axq_depth--; |
f078f209 | 2110 | |
e8324357 S |
2111 | if (bf_isaggr(bf)) |
2112 | txq->axq_aggr_depth--; | |
f078f209 | 2113 | |
e8324357 | 2114 | txok = (ds->ds_txstat.ts_status == 0); |
f078f209 | 2115 | |
e8324357 | 2116 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2117 | |
e8324357 S |
2118 | if (bf_held) { |
2119 | list_del(&bf_held->list); | |
2120 | spin_lock_bh(&sc->tx.txbuflock); | |
2121 | list_add_tail(&bf_held->list, &sc->tx.txbuf); | |
2122 | spin_unlock_bh(&sc->tx.txbuflock); | |
2123 | } | |
f078f209 | 2124 | |
e8324357 S |
2125 | if (!bf_isampdu(bf)) { |
2126 | /* | |
2127 | * This frame is sent out as a single frame. | |
2128 | * Use hardware retry status for this frame. | |
2129 | */ | |
2130 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2131 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2132 | bf->bf_state.bf_type |= BUF_XRETRY; | |
2133 | nbad = 0; | |
2134 | } else { | |
2135 | nbad = ath_tx_num_badfrms(sc, bf, txok); | |
2136 | } | |
f078f209 | 2137 | |
e8324357 | 2138 | ath_tx_rc_status(bf, ds, nbad); |
f078f209 | 2139 | |
e8324357 S |
2140 | if (bf_isampdu(bf)) |
2141 | ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok); | |
2142 | else | |
2143 | ath_tx_complete_buf(sc, bf, &bf_head, txok, 0); | |
8469cdef | 2144 | |
e8324357 S |
2145 | spin_lock_bh(&txq->axq_lock); |
2146 | if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <= | |
2147 | (ATH_TXBUF - 20)) { | |
2148 | int qnum; | |
2149 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); | |
2150 | if (qnum != -1) { | |
2151 | ieee80211_wake_queue(sc->hw, qnum); | |
2152 | txq->stopped = 0; | |
2153 | } | |
8469cdef | 2154 | |
e8324357 | 2155 | } |
8469cdef | 2156 | |
e8324357 S |
2157 | if (sc->sc_flags & SC_OP_TXAGGR) |
2158 | ath_txq_schedule(sc, txq); | |
2159 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2160 | } |
2161 | } | |
2162 | ||
f078f209 | 2163 | |
e8324357 | 2164 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2165 | { |
e8324357 S |
2166 | int i; |
2167 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2168 | |
e8324357 | 2169 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2170 | |
e8324357 S |
2171 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2172 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2173 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2174 | } |
2175 | } | |
2176 | ||
e8324357 S |
2177 | /*****************/ |
2178 | /* Init, Cleanup */ | |
2179 | /*****************/ | |
f078f209 | 2180 | |
e8324357 | 2181 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2182 | { |
e8324357 | 2183 | int error = 0; |
f078f209 | 2184 | |
f078f209 | 2185 | do { |
e8324357 | 2186 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2187 | |
e8324357 S |
2188 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2189 | "tx", nbufs, 1); | |
2190 | if (error != 0) { | |
2191 | DPRINTF(sc, ATH_DBG_FATAL, | |
2192 | "Failed to allocate tx descriptors: %d\n", | |
2193 | error); | |
2194 | break; | |
2195 | } | |
f078f209 | 2196 | |
e8324357 S |
2197 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2198 | "beacon", ATH_BCBUF, 1); | |
2199 | if (error != 0) { | |
2200 | DPRINTF(sc, ATH_DBG_FATAL, | |
2201 | "Failed to allocate beacon descriptors: %d\n", | |
2202 | error); | |
2203 | break; | |
2204 | } | |
f078f209 | 2205 | |
e8324357 | 2206 | } while (0); |
f078f209 | 2207 | |
e8324357 S |
2208 | if (error != 0) |
2209 | ath_tx_cleanup(sc); | |
f078f209 | 2210 | |
e8324357 | 2211 | return error; |
f078f209 LR |
2212 | } |
2213 | ||
e8324357 S |
2214 | int ath_tx_cleanup(struct ath_softc *sc) |
2215 | { | |
2216 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2217 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2218 | ||
2219 | if (sc->tx.txdma.dd_desc_len != 0) | |
2220 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
2221 | ||
2222 | return 0; | |
2223 | } | |
f078f209 LR |
2224 | |
2225 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2226 | { | |
c5170163 S |
2227 | struct ath_atx_tid *tid; |
2228 | struct ath_atx_ac *ac; | |
2229 | int tidno, acno; | |
f078f209 | 2230 | |
8ee5afbc | 2231 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2232 | tidno < WME_NUM_TID; |
2233 | tidno++, tid++) { | |
2234 | tid->an = an; | |
2235 | tid->tidno = tidno; | |
2236 | tid->seq_start = tid->seq_next = 0; | |
2237 | tid->baw_size = WME_MAX_BA; | |
2238 | tid->baw_head = tid->baw_tail = 0; | |
2239 | tid->sched = false; | |
e8324357 | 2240 | tid->paused = false; |
a37c2c79 | 2241 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2242 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2243 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2244 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2245 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2246 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
2247 | tid->addba_exchangeattempts = 0; | |
c5170163 | 2248 | } |
f078f209 | 2249 | |
8ee5afbc | 2250 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2251 | acno < WME_NUM_AC; acno++, ac++) { |
2252 | ac->sched = false; | |
2253 | INIT_LIST_HEAD(&ac->tid_q); | |
2254 | ||
2255 | switch (acno) { | |
2256 | case WME_AC_BE: | |
2257 | ac->qnum = ath_tx_get_qnum(sc, | |
2258 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2259 | break; | |
2260 | case WME_AC_BK: | |
2261 | ac->qnum = ath_tx_get_qnum(sc, | |
2262 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2263 | break; | |
2264 | case WME_AC_VI: | |
2265 | ac->qnum = ath_tx_get_qnum(sc, | |
2266 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2267 | break; | |
2268 | case WME_AC_VO: | |
2269 | ac->qnum = ath_tx_get_qnum(sc, | |
2270 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2271 | break; | |
f078f209 LR |
2272 | } |
2273 | } | |
2274 | } | |
2275 | ||
b5aa9bf9 | 2276 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2277 | { |
2278 | int i; | |
2279 | struct ath_atx_ac *ac, *ac_tmp; | |
2280 | struct ath_atx_tid *tid, *tid_tmp; | |
2281 | struct ath_txq *txq; | |
e8324357 | 2282 | |
f078f209 LR |
2283 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2284 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2285 | txq = &sc->tx.txq[i]; |
f078f209 | 2286 | |
b5aa9bf9 | 2287 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2288 | |
2289 | list_for_each_entry_safe(ac, | |
2290 | ac_tmp, &txq->axq_acq, list) { | |
2291 | tid = list_first_entry(&ac->tid_q, | |
2292 | struct ath_atx_tid, list); | |
2293 | if (tid && tid->an != an) | |
2294 | continue; | |
2295 | list_del(&ac->list); | |
2296 | ac->sched = false; | |
2297 | ||
2298 | list_for_each_entry_safe(tid, | |
2299 | tid_tmp, &ac->tid_q, list) { | |
2300 | list_del(&tid->list); | |
2301 | tid->sched = false; | |
b5aa9bf9 | 2302 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2303 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
f078f209 | 2304 | tid->addba_exchangeattempts = 0; |
a37c2c79 | 2305 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2306 | } |
2307 | } | |
2308 | ||
b5aa9bf9 | 2309 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2310 | } |
2311 | } | |
2312 | } |