Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include "core.h" |
18 | ||
19 | /* | |
20 | * Setup and link descriptors. | |
21 | * | |
22 | * 11N: we can no longer afford to self link the last descriptor. | |
23 | * MAC acknowledges BA status as long as it copies frames to host | |
24 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
25 | * to a sender if last desc is self-linked. | |
f078f209 | 26 | */ |
f078f209 LR |
27 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
28 | { | |
29 | struct ath_hal *ah = sc->sc_ah; | |
30 | struct ath_desc *ds; | |
31 | struct sk_buff *skb; | |
32 | ||
33 | ATH_RXBUF_RESET(bf); | |
34 | ||
35 | ds = bf->bf_desc; | |
be0418ad | 36 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
37 | ds->ds_data = bf->bf_buf_addr; |
38 | ||
be0418ad | 39 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
40 | skb = bf->bf_mpdu; |
41 | ASSERT(skb != NULL); | |
42 | ds->ds_vdata = skb->data; | |
43 | ||
b77f483f | 44 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
45 | * how much data it can DMA to us and that we are prepared |
46 | * to process */ | |
b77f483f S |
47 | ath9k_hw_setuprxdesc(ah, ds, |
48 | sc->rx.bufsize, | |
f078f209 LR |
49 | 0); |
50 | ||
b77f483f | 51 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
52 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
53 | else | |
b77f483f | 54 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 55 | |
b77f483f | 56 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
57 | ath9k_hw_rxena(ah); |
58 | } | |
59 | ||
ff37e337 S |
60 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
61 | { | |
62 | /* XXX block beacon interrupts */ | |
63 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
64 | sc->rx.defant = antenna; |
65 | sc->rx.rxotherant = 0; | |
ff37e337 S |
66 | } |
67 | ||
68 | /* | |
69 | * Extend 15-bit time stamp from rx descriptor to | |
70 | * a full 64-bit TSF using the current h/w TSF. | |
71 | */ | |
72 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
73 | { | |
74 | u64 tsf; | |
75 | ||
76 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
77 | if ((tsf & 0x7fff) < rstamp) | |
78 | tsf -= 0x8000; | |
79 | return (tsf & ~0x7fff) | rstamp; | |
80 | } | |
81 | ||
be0418ad | 82 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) |
f078f209 LR |
83 | { |
84 | struct sk_buff *skb; | |
85 | u32 off; | |
86 | ||
87 | /* | |
88 | * Cache-line-align. This is important (for the | |
89 | * 5210 at least) as not doing so causes bogus data | |
90 | * in rx'd frames. | |
91 | */ | |
92 | ||
b4b6cda2 LR |
93 | /* Note: the kernel can allocate a value greater than |
94 | * what we ask it to give us. We really only need 4 KB as that | |
95 | * is this hardware supports and in fact we need at least 3849 | |
96 | * as that is the MAX AMSDU size this hardware supports. | |
97 | * Unfortunately this means we may get 8 KB here from the | |
98 | * kernel... and that is actually what is observed on some | |
99 | * systems :( */ | |
f078f209 LR |
100 | skb = dev_alloc_skb(len + sc->sc_cachelsz - 1); |
101 | if (skb != NULL) { | |
102 | off = ((unsigned long) skb->data) % sc->sc_cachelsz; | |
103 | if (off != 0) | |
104 | skb_reserve(skb, sc->sc_cachelsz - off); | |
105 | } else { | |
106 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 107 | "skbuff alloc of size %u failed\n", len); |
f078f209 LR |
108 | return NULL; |
109 | } | |
110 | ||
111 | return skb; | |
112 | } | |
113 | ||
be0418ad S |
114 | static int ath_rate2idx(struct ath_softc *sc, int rate) |
115 | { | |
116 | int i = 0, cur_band, n_rates; | |
117 | struct ieee80211_hw *hw = sc->hw; | |
118 | ||
119 | cur_band = hw->conf.channel->band; | |
120 | n_rates = sc->sbands[cur_band].n_bitrates; | |
121 | ||
122 | for (i = 0; i < n_rates; i++) { | |
123 | if (sc->sbands[cur_band].bitrates[i].bitrate == rate) | |
124 | break; | |
125 | } | |
126 | ||
127 | /* | |
128 | * NB:mac80211 validates rx rate index against the supported legacy rate | |
129 | * index only (should be done against ht rates also), return the highest | |
130 | * legacy rate index for rx rate which does not match any one of the | |
131 | * supported basic and extended rates to make mac80211 happy. | |
132 | * The following hack will be cleaned up once the issue with | |
133 | * the rx rate index validation in mac80211 is fixed. | |
134 | */ | |
135 | if (i == n_rates) | |
136 | return n_rates - 1; | |
137 | ||
138 | return i; | |
f078f209 LR |
139 | } |
140 | ||
141 | /* | |
be0418ad S |
142 | * For Decrypt or Demic errors, we only mark packet status here and always push |
143 | * up the frame up to let mac80211 handle the actual error case, be it no | |
144 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 145 | */ |
be0418ad S |
146 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
147 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
148 | struct ath_softc *sc) | |
f078f209 | 149 | { |
3706de6f | 150 | struct ath_rate_table *rate_table = sc->cur_rate_table; |
be0418ad | 151 | struct ieee80211_hdr *hdr; |
e63835b0 | 152 | int ratekbps, rix; |
be0418ad S |
153 | u8 ratecode; |
154 | __le16 fc; | |
155 | ||
156 | hdr = (struct ieee80211_hdr *)skb->data; | |
157 | fc = hdr->frame_control; | |
158 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
159 | ||
160 | if (ds->ds_rxstat.rs_more) { | |
161 | /* | |
162 | * Frame spans multiple descriptors; this cannot happen yet | |
163 | * as we don't support jumbograms. If not in monitor mode, | |
164 | * discard the frame. Enable this if you want to see | |
165 | * error frames in Monitor mode. | |
166 | */ | |
d97809db | 167 | if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_MONITOR) |
be0418ad S |
168 | goto rx_next; |
169 | } else if (ds->ds_rxstat.rs_status != 0) { | |
170 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
171 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
172 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
173 | goto rx_next; | |
f078f209 | 174 | |
be0418ad S |
175 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
176 | *decrypt_error = true; | |
177 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
178 | if (ieee80211_is_ctl(fc)) | |
179 | /* | |
180 | * Sometimes, we get invalid | |
181 | * MIC failures on valid control frames. | |
182 | * Remove these mic errors. | |
183 | */ | |
184 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
185 | else | |
186 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
187 | } | |
188 | /* | |
189 | * Reject error frames with the exception of | |
190 | * decryption and MIC failures. For monitor mode, | |
191 | * we also ignore the CRC error. | |
192 | */ | |
d97809db | 193 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR) { |
be0418ad S |
194 | if (ds->ds_rxstat.rs_status & |
195 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
196 | ATH9K_RXERR_CRC)) | |
197 | goto rx_next; | |
198 | } else { | |
199 | if (ds->ds_rxstat.rs_status & | |
200 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
201 | goto rx_next; | |
202 | } | |
203 | } | |
f078f209 LR |
204 | } |
205 | ||
be0418ad | 206 | ratecode = ds->ds_rxstat.rs_rate; |
e63835b0 S |
207 | rix = rate_table->rateCodeToIndex[ratecode]; |
208 | ratekbps = rate_table->info[rix].ratekbps; | |
be0418ad S |
209 | |
210 | /* HT rate */ | |
211 | if (ratecode & 0x80) { | |
212 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) | |
213 | ratekbps = (ratekbps * 27) / 13; | |
214 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) | |
215 | ratekbps = (ratekbps * 10) / 9; | |
216 | } | |
217 | ||
218 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
219 | rx_status->band = sc->hw->conf.channel->band; | |
220 | rx_status->freq = sc->hw->conf.channel->center_freq; | |
221 | rx_status->noise = sc->sc_ani.sc_noise_floor; | |
222 | rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; | |
223 | rx_status->rate_idx = ath_rate2idx(sc, (ratekbps / 100)); | |
224 | rx_status->antenna = ds->ds_rxstat.rs_antenna; | |
225 | ||
226 | /* at 45 you will be able to use MCS 15 reliably. A more elaborate | |
227 | * scheme can be used here but it requires tables of SNR/throughput for | |
228 | * each possible mode used. */ | |
229 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
230 | ||
231 | /* rssi can be more than 45 though, anything above that | |
232 | * should be considered at 100% */ | |
233 | if (rx_status->qual > 100) | |
234 | rx_status->qual = 100; | |
235 | ||
236 | rx_status->flag |= RX_FLAG_TSFT; | |
237 | ||
238 | return 1; | |
239 | rx_next: | |
240 | return 0; | |
f078f209 LR |
241 | } |
242 | ||
243 | static void ath_opmode_init(struct ath_softc *sc) | |
244 | { | |
245 | struct ath_hal *ah = sc->sc_ah; | |
246 | u32 rfilt, mfilt[2]; | |
247 | ||
248 | /* configure rx filter */ | |
249 | rfilt = ath_calcrxfilter(sc); | |
250 | ath9k_hw_setrxfilter(ah, rfilt); | |
251 | ||
252 | /* configure bssid mask */ | |
60b67f51 | 253 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
f078f209 LR |
254 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); |
255 | ||
256 | /* configure operational mode */ | |
257 | ath9k_hw_setopmode(ah); | |
258 | ||
259 | /* Handle any link-level address change. */ | |
260 | ath9k_hw_setmac(ah, sc->sc_myaddr); | |
261 | ||
262 | /* calculate and install multicast filter */ | |
263 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 264 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
265 | } |
266 | ||
267 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
268 | { | |
269 | struct sk_buff *skb; | |
270 | struct ath_buf *bf; | |
271 | int error = 0; | |
272 | ||
273 | do { | |
b77f483f | 274 | spin_lock_init(&sc->rx.rxflushlock); |
98deeea0 | 275 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 276 | spin_lock_init(&sc->rx.rxbuflock); |
f078f209 | 277 | |
b77f483f | 278 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
f078f209 LR |
279 | min(sc->sc_cachelsz, |
280 | (u16)64)); | |
281 | ||
04bd4638 | 282 | DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
b77f483f | 283 | sc->sc_cachelsz, sc->rx.bufsize); |
f078f209 LR |
284 | |
285 | /* Initialize rx descriptors */ | |
286 | ||
b77f483f | 287 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
f078f209 LR |
288 | "rx", nbufs, 1); |
289 | if (error != 0) { | |
290 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 291 | "failed to allocate rx descriptors: %d\n", error); |
f078f209 LR |
292 | break; |
293 | } | |
294 | ||
b77f483f S |
295 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
296 | skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); | |
f078f209 LR |
297 | if (skb == NULL) { |
298 | error = -ENOMEM; | |
299 | break; | |
300 | } | |
301 | ||
302 | bf->bf_mpdu = skb; | |
927e70e9 | 303 | bf->bf_buf_addr = pci_map_single(sc->pdev, skb->data, |
b77f483f S |
304 | sc->rx.bufsize, |
305 | PCI_DMA_FROMDEVICE); | |
f8316df1 LR |
306 | if (unlikely(pci_dma_mapping_error(sc->pdev, |
307 | bf->bf_buf_addr))) { | |
308 | dev_kfree_skb_any(skb); | |
309 | bf->bf_mpdu = NULL; | |
310 | DPRINTF(sc, ATH_DBG_CONFIG, | |
311 | "pci_dma_mapping_error() on RX init\n"); | |
312 | error = -ENOMEM; | |
313 | break; | |
314 | } | |
927e70e9 | 315 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 | 316 | } |
b77f483f | 317 | sc->rx.rxlink = NULL; |
f078f209 LR |
318 | |
319 | } while (0); | |
320 | ||
321 | if (error) | |
322 | ath_rx_cleanup(sc); | |
323 | ||
324 | return error; | |
325 | } | |
326 | ||
f078f209 LR |
327 | void ath_rx_cleanup(struct ath_softc *sc) |
328 | { | |
329 | struct sk_buff *skb; | |
330 | struct ath_buf *bf; | |
331 | ||
b77f483f | 332 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 LR |
333 | skb = bf->bf_mpdu; |
334 | if (skb) | |
335 | dev_kfree_skb(skb); | |
336 | } | |
337 | ||
b77f483f S |
338 | if (sc->rx.rxdma.dd_desc_len != 0) |
339 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
340 | } |
341 | ||
342 | /* | |
343 | * Calculate the receive filter according to the | |
344 | * operating mode and state: | |
345 | * | |
346 | * o always accept unicast, broadcast, and multicast traffic | |
347 | * o maintain current state of phy error reception (the hal | |
348 | * may enable phy error frames for noise immunity work) | |
349 | * o probe request frames are accepted only when operating in | |
350 | * hostap, adhoc, or monitor modes | |
351 | * o enable promiscuous mode according to the interface state | |
352 | * o accept beacons: | |
353 | * - when operating in adhoc mode so the 802.11 layer creates | |
354 | * node table entries for peers, | |
355 | * - when operating in station mode for collecting rssi data when | |
356 | * the station is otherwise quiet, or | |
357 | * - when operating as a repeater so we see repeater-sta beacons | |
358 | * - when scanning | |
359 | */ | |
360 | ||
361 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
362 | { | |
363 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 364 | |
f078f209 LR |
365 | u32 rfilt; |
366 | ||
367 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
368 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
369 | | ATH9K_RX_FILTER_MCAST; | |
370 | ||
371 | /* If not a STA, enable processing of Probe Requests */ | |
d97809db | 372 | if (sc->sc_ah->ah_opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
373 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
374 | ||
375 | /* Can't set HOSTAP into promiscous mode */ | |
d97809db | 376 | if (((sc->sc_ah->ah_opmode != NL80211_IFTYPE_AP) && |
b77f483f | 377 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
d97809db | 378 | (sc->sc_ah->ah_opmode == NL80211_IFTYPE_MONITOR)) { |
f078f209 LR |
379 | rfilt |= ATH9K_RX_FILTER_PROM; |
380 | /* ??? To prevent from sending ACK */ | |
381 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | |
382 | } | |
383 | ||
d97809db CM |
384 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION || |
385 | sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) | |
f078f209 LR |
386 | rfilt |= ATH9K_RX_FILTER_BEACON; |
387 | ||
388 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames | |
389 | & beacon frames */ | |
d97809db | 390 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) |
f078f209 | 391 | rfilt |= (ATH9K_RX_FILTER_BEACON | ATH9K_RX_FILTER_PSPOLL); |
be0418ad | 392 | |
f078f209 | 393 | return rfilt; |
7dcfdcd9 | 394 | |
f078f209 LR |
395 | #undef RX_FILTER_PRESERVE |
396 | } | |
397 | ||
f078f209 LR |
398 | int ath_startrecv(struct ath_softc *sc) |
399 | { | |
400 | struct ath_hal *ah = sc->sc_ah; | |
401 | struct ath_buf *bf, *tbf; | |
402 | ||
b77f483f S |
403 | spin_lock_bh(&sc->rx.rxbuflock); |
404 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
405 | goto start_recv; |
406 | ||
b77f483f S |
407 | sc->rx.rxlink = NULL; |
408 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
409 | ath_rx_buf_link(sc, bf); |
410 | } | |
411 | ||
412 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 413 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
414 | goto start_recv; |
415 | ||
b77f483f | 416 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 417 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 418 | ath9k_hw_rxena(ah); |
f078f209 LR |
419 | |
420 | start_recv: | |
b77f483f | 421 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
422 | ath_opmode_init(sc); |
423 | ath9k_hw_startpcureceive(ah); | |
424 | ||
f078f209 LR |
425 | return 0; |
426 | } | |
427 | ||
f078f209 LR |
428 | bool ath_stoprecv(struct ath_softc *sc) |
429 | { | |
430 | struct ath_hal *ah = sc->sc_ah; | |
f078f209 LR |
431 | bool stopped; |
432 | ||
be0418ad S |
433 | ath9k_hw_stoppcurecv(ah); |
434 | ath9k_hw_setrxfilter(ah, 0); | |
435 | stopped = ath9k_hw_stopdmarecv(ah); | |
436 | mdelay(3); /* 3ms is long enough for 1 frame */ | |
b77f483f | 437 | sc->rx.rxlink = NULL; |
be0418ad | 438 | |
f078f209 LR |
439 | return stopped; |
440 | } | |
441 | ||
f078f209 LR |
442 | void ath_flushrecv(struct ath_softc *sc) |
443 | { | |
b77f483f | 444 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 445 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 446 | ath_rx_tasklet(sc, 1); |
98deeea0 | 447 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 448 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
449 | } |
450 | ||
f078f209 LR |
451 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
452 | { | |
453 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
454 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
455 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 456 | |
be0418ad | 457 | struct ath_buf *bf; |
f078f209 | 458 | struct ath_desc *ds; |
cb71d9ba | 459 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 460 | struct ieee80211_rx_status rx_status; |
f078f209 | 461 | struct ath_hal *ah = sc->sc_ah; |
be0418ad S |
462 | struct ieee80211_hdr *hdr; |
463 | int hdrlen, padsize, retval; | |
464 | bool decrypt_error = false; | |
465 | u8 keyix; | |
466 | ||
b77f483f | 467 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
468 | |
469 | do { | |
470 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 471 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
472 | break; |
473 | ||
b77f483f S |
474 | if (list_empty(&sc->rx.rxbuf)) { |
475 | sc->rx.rxlink = NULL; | |
f078f209 LR |
476 | break; |
477 | } | |
478 | ||
b77f483f | 479 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 480 | ds = bf->bf_desc; |
f078f209 LR |
481 | |
482 | /* | |
483 | * Must provide the virtual address of the current | |
484 | * descriptor, the physical address, and the virtual | |
485 | * address of the next descriptor in the h/w chain. | |
486 | * This allows the HAL to look ahead to see if the | |
487 | * hardware is done with a descriptor by checking the | |
488 | * done bit in the following descriptor and the address | |
489 | * of the current descriptor the DMA engine is working | |
490 | * on. All this is necessary because of our use of | |
491 | * a self-linked list to avoid rx overruns. | |
492 | */ | |
be0418ad | 493 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
494 | bf->bf_daddr, |
495 | PA2DESC(sc, ds->ds_link), | |
496 | 0); | |
497 | if (retval == -EINPROGRESS) { | |
498 | struct ath_buf *tbf; | |
499 | struct ath_desc *tds; | |
500 | ||
b77f483f S |
501 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
502 | sc->rx.rxlink = NULL; | |
f078f209 LR |
503 | break; |
504 | } | |
505 | ||
506 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
507 | ||
508 | /* | |
509 | * On some hardware the descriptor status words could | |
510 | * get corrupted, including the done bit. Because of | |
511 | * this, check if the next descriptor's done bit is | |
512 | * set or not. | |
513 | * | |
514 | * If the next descriptor's done bit is set, the current | |
515 | * descriptor has been corrupted. Force s/w to discard | |
516 | * this descriptor and continue... | |
517 | */ | |
518 | ||
519 | tds = tbf->bf_desc; | |
be0418ad S |
520 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
521 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 522 | if (retval == -EINPROGRESS) { |
f078f209 LR |
523 | break; |
524 | } | |
525 | } | |
526 | ||
f078f209 | 527 | skb = bf->bf_mpdu; |
be0418ad | 528 | if (!skb) |
f078f209 | 529 | continue; |
f078f209 | 530 | |
f078f209 | 531 | /* |
be0418ad S |
532 | * If we're asked to flush receive queue, directly |
533 | * chain it back at the queue without processing it. | |
f078f209 | 534 | */ |
be0418ad | 535 | if (flush) |
cb71d9ba | 536 | goto requeue; |
f078f209 | 537 | |
be0418ad | 538 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 539 | goto requeue; |
f078f209 | 540 | |
be0418ad | 541 | /* The status portion of the descriptor could get corrupted. */ |
b77f483f | 542 | if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 543 | goto requeue; |
f078f209 | 544 | |
be0418ad | 545 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
546 | goto requeue; |
547 | ||
548 | /* Ensure we always have an skb to requeue once we are done | |
549 | * processing the current buffer's skb */ | |
b77f483f | 550 | requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); |
cb71d9ba LR |
551 | |
552 | /* If there is no memory we ignore the current RX'd frame, | |
553 | * tell hardware it can give us a new frame using the old | |
b77f483f | 554 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
555 | * processing. */ |
556 | if (!requeue_skb) | |
557 | goto requeue; | |
f078f209 | 558 | |
b77f483f S |
559 | /* Sync and unmap the frame */ |
560 | pci_dma_sync_single_for_cpu(sc->pdev, bf->bf_buf_addr, | |
561 | sc->rx.bufsize, | |
f078f209 | 562 | PCI_DMA_FROMDEVICE); |
be0418ad | 563 | pci_unmap_single(sc->pdev, bf->bf_buf_addr, |
b77f483f | 564 | sc->rx.bufsize, |
f078f209 LR |
565 | PCI_DMA_FROMDEVICE); |
566 | ||
be0418ad S |
567 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
568 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
569 | ||
570 | /* see if any padding is done by the hw and remove it */ | |
571 | hdr = (struct ieee80211_hdr *)skb->data; | |
572 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
573 | ||
574 | if (hdrlen & 3) { | |
575 | padsize = hdrlen % 4; | |
576 | memmove(skb->data + padsize, skb->data, hdrlen); | |
577 | skb_pull(skb, padsize); | |
f078f209 LR |
578 | } |
579 | ||
be0418ad | 580 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 581 | |
be0418ad S |
582 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
583 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
584 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | |
585 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
586 | keyix = skb->data[hdrlen + 3] >> 6; | |
587 | ||
588 | if (test_bit(keyix, sc->sc_keymap)) | |
589 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
590 | } | |
591 | ||
592 | /* Send the frame to mac80211 */ | |
593 | __ieee80211_rx(sc->hw, skb, &rx_status); | |
cb71d9ba LR |
594 | |
595 | /* We will now give hardware our shiny new allocated skb */ | |
596 | bf->bf_mpdu = requeue_skb; | |
597 | bf->bf_buf_addr = pci_map_single(sc->pdev, requeue_skb->data, | |
b77f483f | 598 | sc->rx.bufsize, |
cb71d9ba | 599 | PCI_DMA_FROMDEVICE); |
f8316df1 LR |
600 | if (unlikely(pci_dma_mapping_error(sc->pdev, |
601 | bf->bf_buf_addr))) { | |
602 | dev_kfree_skb_any(requeue_skb); | |
603 | bf->bf_mpdu = NULL; | |
604 | DPRINTF(sc, ATH_DBG_CONFIG, | |
605 | "pci_dma_mapping_error() on RX\n"); | |
606 | break; | |
607 | } | |
cb71d9ba | 608 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
609 | |
610 | /* | |
611 | * change the default rx antenna if rx diversity chooses the | |
612 | * other antenna 3 times in a row. | |
613 | */ | |
b77f483f S |
614 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
615 | if (++sc->rx.rxotherant >= 3) | |
be0418ad | 616 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 | 617 | } else { |
b77f483f | 618 | sc->rx.rxotherant = 0; |
f078f209 | 619 | } |
cb71d9ba | 620 | requeue: |
b77f483f | 621 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 622 | ath_rx_buf_link(sc, bf); |
be0418ad S |
623 | } while (1); |
624 | ||
b77f483f | 625 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
626 | |
627 | return 0; | |
628 | #undef PA2DESC | |
629 | } |