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ath9k: Add spectrum management to HW capabilities
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
17d7904d 301 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 302 ath9k_ps_restore(sc);
ff37e337
S		 303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
20977d3e
S		 315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 321 u32 cal_interval, short_cal_interval;
ff37e337 322
20977d3e
S		 323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
0c98de65 330 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 331 goto set_timer;
ff37e337
S		 332
333 /* Long calibration runs independently of short calibration. */
17d7904d 334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 335 longcal = true;
04bd4638 336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 337 sc->ani.longcal_timer = timestamp;
ff37e337
S		 338 }
339
17d7904d
S		 340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
20977d3e 342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 343 shortcal = true;
04bd4638 344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 347 }
348 } else {
17d7904d 349 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 350 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 354 }
355 }
356
357 /* Verify whether we must check ANI */
20977d3e 358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 359 aniflag = true;
17d7904d 360 sc->ani.checkani_timer = timestamp;
ff37e337
S		 361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
20977d3e 367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
2660b81a 373 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 374 sc->rx_chainmask, longcal,
ff37e337
S		 375 &iscaldone)) {
376 if (longcal)
17d7904d 377 sc->ani.noise_floor =
ff37e337 378 ath9k_hw_getchan_noise(ah,
2660b81a 379 ah->curchan);
ff37e337
S		 380
381 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 382 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 383 ah->curchan->channel,
384 ah->curchan->channelFlags,
17d7904d 385 sc->ani.noise_floor);
ff37e337
S		 386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 388 "calibrate chan %u/%x failed\n",
2660b81a
S		 389 ah->curchan->channel,
390 ah->curchan->channelFlags);
ff37e337 391 }
17d7904d 392 sc->ani.caldone = iscaldone;
ff37e337
S		 393 }
394 }
395
20977d3e 396set_timer:
ff37e337
S		 397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e 402 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 403 if (sc->sc_ah->config.enable_ani)
aac9207e 404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 405 if (!sc->ani.caldone)
20977d3e 406 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 407
17d7904d 408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337 416 */
0e2dedf9 417void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337
S		 418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 420 if (is_ht ||
2660b81a
S		 421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 424 } else {
17d7904d
S		 425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
ff37e337
S		 427 }
428
04bd4638 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 430 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 458 u32 status = sc->intrstatus;
ff37e337
S		 459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
17d7904d 478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
cbe61d8a 484 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
17d7904d 509 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
17d7904d 518 sc->intrstatus = status;
541d8dd5 519 ath9k_ps_wakeup(sc);
ff37e337
S		 520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
17d7904d
S		 566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 570 if (!(ah->caps.hw_caps &
ff37e337
S		 571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
3cbb5dd7 574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
3cbb5dd7 577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 578 }
579 }
4af9cf4f
S		 580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
ff37e337 584 }
541d8dd5 585 ath9k_ps_restore(sc);
ff37e337
S		 586 } while (0);
587
817e11de
S		 588 ath_debug_stat_interrupt(sc, status);
589
ff37e337
S		 590 if (sched) {
591 /* turn off every interrupt except SWBA */
17d7904d 592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597}
598
f078f209 599static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 600 struct ieee80211_channel *chan,
094d05dc 601 enum nl80211_channel_type channel_type)
f078f209
LR		 602{
603 u32 chanmode = 0;
f078f209
LR		 604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
094d05dc
S		 607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
f078f209 610 chanmode = CHANNEL_G_HT20;
094d05dc
S		 611 break;
612 case NL80211_CHAN_HT40PLUS:
f078f209 613 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 614 break;
615 case NL80211_CHAN_HT40MINUS:
f078f209 616 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 617 break;
618 }
f078f209
LR		 619 break;
620 case IEEE80211_BAND_5GHZ:
094d05dc
S		 621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
f078f209 624 chanmode = CHANNEL_A_HT20;
094d05dc
S		 625 break;
626 case NL80211_CHAN_HT40PLUS:
f078f209 627 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 628 break;
629 case NL80211_CHAN_HT40MINUS:
f078f209 630 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 631 break;
632 }
f078f209
LR		 633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639}
640
6ace2891 641static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
f078f209 644{
6ace2891
JM		 645 const u8 *key_rxmic;
646 const u8 *key_txmic;
f078f209 647
6ace2891
JM		 648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 650
651 if (addr == NULL) {
d216aaa6
JM		 652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
3f53dd64
JM		 657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
d216aaa6 664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 665 }
17d7904d 666 if (!sc->splitmic) {
d216aaa6 667 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 671 }
d216aaa6
JM		 672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
f078f209 676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
f078f209 679 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 680 "Setting TX MIC Key Failed\n");
f078f209
LR		 681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
d216aaa6 686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
17d7904d
S		 693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
6ace2891 696 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 719 return i;
17d7904d
S		 720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i + 32;
17d7904d
S		 725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
ea612132 729 return i + 64;
17d7904d
S		 730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
ea612132 734 return i + 64 + 32;
6ace2891
JM		 735 }
736 } else {
17d7904d
S		 737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
6ace2891 740 return i;
17d7904d
S		 741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
17d7904d 748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
17d7904d 754 if (sc->splitmic) {
be2864cf
JM		 755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
17d7904d 761 if (!test_bit(i, sc->keymap))
6ace2891
JM		 762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
f078f209
LR		 767}
768
769static int ath_key_config(struct ath_softc *sc,
3f53dd64 770 struct ieee80211_vif *vif,
dc822b5d 771 struct ieee80211_sta *sta,
f078f209
LR		 772 struct ieee80211_key_conf *key)
773{
f078f209
LR		 774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
6ace2891 777 int idx;
f078f209
LR		 778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
ca470b29 792 return -EOPNOTSUPP;
f078f209
LR		 793 }
794
6ace2891 795 hk.kv_len = key->keylen;
f078f209
LR		 796 memcpy(hk.kv_val, key->key, key->keylen);
797
6ace2891
JM		 798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
dc822b5d
JB		 803 if (WARN_ON(!sta))
804 return -EOPNOTSUPP;
805 mac = sta->addr;
806
6ace2891
JM		 807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
f078f209 813 } else {
dc822b5d
JB		 814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
6ace2891
JM		 818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
ca470b29 823 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 824 }
825
826 if (key->alg == ALG_TKIP)
3f53dd64
JM		 827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
828 vif->type == NL80211_IFTYPE_AP);
f078f209 829 else
d216aaa6 830 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 831
832 if (!ret)
833 return -EIO;
834
17d7904d 835 set_bit(idx, sc->keymap);
6ace2891 836 if (key->alg == ALG_TKIP) {
17d7904d
S		 837 set_bit(idx + 64, sc->keymap);
838 if (sc->splitmic) {
839 set_bit(idx + 32, sc->keymap);
840 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 841 }
842 }
843
844 return idx;
f078f209
LR		 845}
846
847static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
848{
6ace2891
JM		 849 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
850 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 return;
852
17d7904d 853 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 854 if (key->alg != ALG_TKIP)
855 return;
f078f209 856
17d7904d
S		 857 clear_bit(key->hw_key_idx + 64, sc->keymap);
858 if (sc->splitmic) {
859 clear_bit(key->hw_key_idx + 32, sc->keymap);
860 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 861 }
f078f209
LR		 862}
863
eb2599ca
S		 864static void setup_ht_cap(struct ath_softc *sc,
865 struct ieee80211_sta_ht_cap *ht_info)
f078f209 866{
60653678
S		 867#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
868#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 869
d9fe60de
JB		 870 ht_info->ht_supported = true;
871 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
872 IEEE80211_HT_CAP_SM_PS |
873 IEEE80211_HT_CAP_SGI_40 |
874 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 875
60653678
S		 876 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
877 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 878
d9fe60de
JB		 879 /* set up supported mcs set */
880 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 881
17d7904d 882 switch(sc->rx_chainmask) {
eb2599ca
S		 883 case 1:
884 ht_info->mcs.rx_mask[0] = 0xff;
885 break;
3c457265 886 case 3:
eb2599ca
S		 887 case 5:
888 case 7:
889 default:
890 ht_info->mcs.rx_mask[0] = 0xff;
891 ht_info->mcs.rx_mask[1] = 0xff;
892 break;
893 }
894
d9fe60de 895 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 896}
897
8feceb67 898static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 899 struct ieee80211_vif *vif,
8feceb67 900 struct ieee80211_bss_conf *bss_conf)
f078f209 901{
17d7904d 902 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 903
8feceb67 904 if (bss_conf->assoc) {
094d05dc 905 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 906 bss_conf->aid, sc->curbssid);
f078f209 907
8feceb67 908 /* New association, store aid */
d97809db 909 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 910 sc->curaid = bss_conf->aid;
ba52da58 911 ath9k_hw_write_associd(sc);
8feceb67 912 }
f078f209 913
8feceb67 914 /* Configure the beacon */
2c3db3d5 915 ath_beacon_config(sc, vif);
f078f209 916
8feceb67 917 /* Reset rssi stats */
17d7904d
S		 918 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 922
6f255425 923 /* Start ANI */
17d7904d 924 mod_timer(&sc->ani.timer,
20977d3e 925 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 926 } else {
04bd4638 927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 928 sc->curaid = 0;
f078f209 929 }
8feceb67 930}
f078f209 931
8feceb67
VT		 932/********************************/
933/* LED functions */
934/********************************/
f078f209 935
f2bffa7e
VT		 936static void ath_led_blink_work(struct work_struct *work)
937{
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
943 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
944 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
945
946 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
947 (sc->sc_flags & SC_OP_LED_ON) ?
948 msecs_to_jiffies(sc->led_off_duration) :
949 msecs_to_jiffies(sc->led_on_duration));
950
951 sc->led_on_duration =
952 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
953 sc->led_off_duration =
954 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
955 sc->led_on_cnt = sc->led_off_cnt = 0;
956 if (sc->sc_flags & SC_OP_LED_ON)
957 sc->sc_flags &= ~SC_OP_LED_ON;
958 else
959 sc->sc_flags |= SC_OP_LED_ON;
960}
961
8feceb67
VT		 962static void ath_led_brightness(struct led_classdev *led_cdev,
963 enum led_brightness brightness)
964{
965 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
966 struct ath_softc *sc = led->sc;
f078f209 967
8feceb67
VT		 968 switch (brightness) {
969 case LED_OFF:
970 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 971 led->led_type == ATH_LED_RADIO) {
972 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
973 (led->led_type == ATH_LED_RADIO));
8feceb67 974 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 975 if (led->led_type == ATH_LED_RADIO)
976 sc->sc_flags &= ~SC_OP_LED_ON;
977 } else {
978 sc->led_off_cnt++;
979 }
8feceb67
VT		 980 break;
981 case LED_FULL:
f2bffa7e 982 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 983 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 984 queue_delayed_work(sc->hw->workqueue,
985 &sc->ath_led_blink_work, 0);
986 } else if (led->led_type == ATH_LED_RADIO) {
987 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
988 sc->sc_flags |= SC_OP_LED_ON;
989 } else {
990 sc->led_on_cnt++;
991 }
8feceb67
VT		 992 break;
993 default:
994 break;
f078f209 995 }
8feceb67 996}
f078f209 997
8feceb67
VT		 998static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
999 char *trigger)
1000{
1001 int ret;
f078f209 1002
8feceb67
VT		 1003 led->sc = sc;
1004 led->led_cdev.name = led->name;
1005 led->led_cdev.default_trigger = trigger;
1006 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1007
8feceb67
VT		 1008 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009 if (ret)
1010 DPRINTF(sc, ATH_DBG_FATAL,
1011 "Failed to register led:%s", led->name);
1012 else
1013 led->registered = 1;
1014 return ret;
1015}
f078f209 1016
8feceb67
VT		 1017static void ath_unregister_led(struct ath_led *led)
1018{
1019 if (led->registered) {
1020 led_classdev_unregister(&led->led_cdev);
1021 led->registered = 0;
f078f209 1022 }
f078f209
LR		 1023}
1024
8feceb67 1025static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1026{
f2bffa7e 1027 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1028 ath_unregister_led(&sc->assoc_led);
1029 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030 ath_unregister_led(&sc->tx_led);
1031 ath_unregister_led(&sc->rx_led);
1032 ath_unregister_led(&sc->radio_led);
1033 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034}
f078f209 1035
8feceb67
VT		 1036static void ath_init_leds(struct ath_softc *sc)
1037{
1038 char *trigger;
1039 int ret;
f078f209 1040
8feceb67
VT		 1041 /* Configure gpio 1 for output */
1042 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044 /* LED off, active low */
1045 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1046
f2bffa7e
VT		 1047 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
8feceb67
VT		 1049 trigger = ieee80211_get_radio_led_name(sc->hw);
1050 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1051 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1052 ret = ath_register_led(sc, &sc->radio_led, trigger);
1053 sc->radio_led.led_type = ATH_LED_RADIO;
1054 if (ret)
1055 goto fail;
7dcfdcd9 1056
8feceb67
VT		 1057 trigger = ieee80211_get_assoc_led_name(sc->hw);
1058 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1059 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1060 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061 sc->assoc_led.led_type = ATH_LED_ASSOC;
1062 if (ret)
1063 goto fail;
f078f209 1064
8feceb67
VT		 1065 trigger = ieee80211_get_tx_led_name(sc->hw);
1066 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1067 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1068 ret = ath_register_led(sc, &sc->tx_led, trigger);
1069 sc->tx_led.led_type = ATH_LED_TX;
1070 if (ret)
1071 goto fail;
f078f209 1072
8feceb67
VT		 1073 trigger = ieee80211_get_rx_led_name(sc->hw);
1074 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1075 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1076 ret = ath_register_led(sc, &sc->rx_led, trigger);
1077 sc->rx_led.led_type = ATH_LED_RX;
1078 if (ret)
1079 goto fail;
f078f209 1080
8feceb67
VT		 1081 return;
1082
1083fail:
1084 ath_deinit_leds(sc);
f078f209
LR		 1085}
1086
7ec3e514 1087void ath_radio_enable(struct ath_softc *sc)
500c064d 1088{
cbe61d8a 1089 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1090 struct ieee80211_channel *channel = sc->hw->conf.channel;
1091 int r;
500c064d 1092
3cbb5dd7 1093 ath9k_ps_wakeup(sc);
500c064d 1094 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1095
2660b81a 1096 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1097
1098 if (r) {
500c064d 1099 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1100 "Unable to reset channel %u (%uMhz) ",
1101 "reset status %u\n",
1102 channel->center_freq, r);
500c064d
VT		 1103 }
1104 spin_unlock_bh(&sc->sc_resetlock);
1105
1106 ath_update_txpow(sc);
1107 if (ath_startrecv(sc) != 0) {
1108 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1109 "Unable to restart recv logic\n");
500c064d
VT		 1110 return;
1111 }
1112
1113 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1114 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1115
1116 /* Re-Enable interrupts */
17d7904d 1117 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1118
1119 /* Enable LED */
1120 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1121 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1122 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1123
1124 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1125 ath9k_ps_restore(sc);
500c064d
VT		 1126}
1127
7ec3e514 1128void ath_radio_disable(struct ath_softc *sc)
500c064d 1129{
cbe61d8a 1130 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1131 struct ieee80211_channel *channel = sc->hw->conf.channel;
1132 int r;
500c064d 1133
3cbb5dd7 1134 ath9k_ps_wakeup(sc);
500c064d
VT		 1135 ieee80211_stop_queues(sc->hw);
1136
1137 /* Disable LED */
1138 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1139 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1140
1141 /* Disable interrupts */
1142 ath9k_hw_set_interrupts(ah, 0);
1143
043a0405 1144 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1145 ath_stoprecv(sc); /* turn off frame recv */
1146 ath_flushrecv(sc); /* flush recv queue */
1147
1148 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1149 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1150 if (r) {
500c064d 1151 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1152 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1153 "reset status %u\n",
1154 channel->center_freq, r);
500c064d
VT		 1155 }
1156 spin_unlock_bh(&sc->sc_resetlock);
1157
1158 ath9k_hw_phy_disable(ah);
1159 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1160 ath9k_ps_restore(sc);
500c064d
VT		 1161}
1162
5077fd35
GJ		 1163#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1164
1165/*******************/
1166/* Rfkill */
1167/*******************/
1168
500c064d
VT		 1169static bool ath_is_rfkill_set(struct ath_softc *sc)
1170{
cbe61d8a 1171 struct ath_hw *ah = sc->sc_ah;
500c064d 1172
2660b81a
S		 1173 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174 ah->rfkill_polarity;
500c064d
VT		 1175}
1176
1177/* h/w rfkill poll function */
1178static void ath_rfkill_poll(struct work_struct *work)
1179{
1180 struct ath_softc *sc = container_of(work, struct ath_softc,
1181 rf_kill.rfkill_poll.work);
1182 bool radio_on;
1183
1184 if (sc->sc_flags & SC_OP_INVALID)
1185 return;
1186
1187 radio_on = !ath_is_rfkill_set(sc);
1188
1189 /*
1190 * enable/disable radio only when there is a
1191 * state change in RF switch
1192 */
1193 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194 enum rfkill_state state;
1195
1196 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198 : RFKILL_STATE_HARD_BLOCKED;
1199 } else if (radio_on) {
1200 ath_radio_enable(sc);
1201 state = RFKILL_STATE_UNBLOCKED;
1202 } else {
1203 ath_radio_disable(sc);
1204 state = RFKILL_STATE_HARD_BLOCKED;
1205 }
1206
1207 if (state == RFKILL_STATE_HARD_BLOCKED)
1208 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209 else
1210 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212 rfkill_force_state(sc->rf_kill.rfkill, state);
1213 }
1214
1215 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217}
1218
1219/* s/w rfkill handler */
1220static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221{
1222 struct ath_softc *sc = data;
1223
1224 switch (state) {
1225 case RFKILL_STATE_SOFT_BLOCKED:
1226 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227 SC_OP_RFKILL_SW_BLOCKED)))
1228 ath_radio_disable(sc);
1229 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230 return 0;
1231 case RFKILL_STATE_UNBLOCKED:
1232 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1236 "radio as it is disabled by h/w\n");
500c064d
VT		 1237 return -EPERM;
1238 }
1239 ath_radio_enable(sc);
1240 }
1241 return 0;
1242 default:
1243 return -EINVAL;
1244 }
1245}
1246
1247/* Init s/w rfkill */
1248static int ath_init_sw_rfkill(struct ath_softc *sc)
1249{
1250 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251 RFKILL_TYPE_WLAN);
1252 if (!sc->rf_kill.rfkill) {
1253 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254 return -ENOMEM;
1255 }
1256
1257 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1258 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1259 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260 sc->rf_kill.rfkill->data = sc;
1261 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265 return 0;
1266}
1267
1268/* Deinitialize rfkill */
1269static void ath_deinit_rfkill(struct ath_softc *sc)
1270{
2660b81a 1271 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1272 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275 rfkill_unregister(sc->rf_kill.rfkill);
1276 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277 sc->rf_kill.rfkill = NULL;
1278 }
1279}
9c84b797
S		 1280
1281static int ath_start_rfkill_poll(struct ath_softc *sc)
1282{
2660b81a 1283 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1284 queue_delayed_work(sc->hw->workqueue,
1285 &sc->rf_kill.rfkill_poll, 0);
1286
1287 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288 if (rfkill_register(sc->rf_kill.rfkill)) {
1289 DPRINTF(sc, ATH_DBG_FATAL,
1290 "Unable to register rfkill\n");
1291 rfkill_free(sc->rf_kill.rfkill);
1292
1293 /* Deinitialize the device */
39c3c2f2 1294 ath_cleanup(sc);
9c84b797
S		 1295 return -EIO;
1296 } else {
1297 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298 }
1299 }
1300
1301 return 0;
1302}
500c064d
VT		 1303#endif /* CONFIG_RFKILL */
1304
6baff7f9 1305void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1306{
1307 ath_detach(sc);
1308 free_irq(sc->irq, sc);
1309 ath_bus_cleanup(sc);
c52f33d0 1310 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1311 ieee80211_free_hw(sc->hw);
1312}
1313
6baff7f9 1314void ath_detach(struct ath_softc *sc)
f078f209 1315{
8feceb67 1316 struct ieee80211_hw *hw = sc->hw;
9c84b797 1317 int i = 0;
f078f209 1318
3cbb5dd7
VN		 1319 ath9k_ps_wakeup(sc);
1320
04bd4638 1321 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1322
e97275cb 1323#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1324 ath_deinit_rfkill(sc);
1325#endif
3fcdfb4b 1326 ath_deinit_leds(sc);
0e2dedf9 1327 cancel_work_sync(&sc->chan_work);
f98c3bd2 1328 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1329
c52f33d0
JM		 1330 for (i = 0; i < sc->num_sec_wiphy; i++) {
1331 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1332 if (aphy == NULL)
1333 continue;
1334 sc->sec_wiphy[i] = NULL;
1335 ieee80211_unregister_hw(aphy->hw);
1336 ieee80211_free_hw(aphy->hw);
1337 }
3fcdfb4b 1338 ieee80211_unregister_hw(hw);
8feceb67
VT		 1339 ath_rx_cleanup(sc);
1340 ath_tx_cleanup(sc);
f078f209 1341
9c84b797
S		 1342 tasklet_kill(&sc->intr_tq);
1343 tasklet_kill(&sc->bcon_tasklet);
f078f209 1344
9c84b797
S		 1345 if (!(sc->sc_flags & SC_OP_INVALID))
1346 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1347
9c84b797
S		 1348 /* cleanup tx queues */
1349 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1350 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1351 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1352
1353 ath9k_hw_detach(sc->sc_ah);
826d2680 1354 ath9k_exit_debug(sc);
3cbb5dd7 1355 ath9k_ps_restore(sc);
f078f209
LR		 1356}
1357
ff37e337
S		 1358static int ath_init(u16 devid, struct ath_softc *sc)
1359{
cbe61d8a 1360 struct ath_hw *ah = NULL;
ff37e337
S		 1361 int status;
1362 int error = 0, i;
1363 int csz = 0;
1364
1365 /* XXX: hardware will not be ready until ath_open() being called */
1366 sc->sc_flags |= SC_OP_INVALID;
88b126af 1367
826d2680
S		 1368 if (ath9k_init_debug(sc) < 0)
1369 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1370
c52f33d0 1371 spin_lock_init(&sc->wiphy_lock);
ff37e337 1372 spin_lock_init(&sc->sc_resetlock);
aa33de09 1373 mutex_init(&sc->mutex);
ff37e337 1374 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1375 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1376 (unsigned long)sc);
1377
1378 /*
1379 * Cache line size is used to size and align various
1380 * structures used to communicate with the hardware.
1381 */
88d15707 1382 ath_read_cachesize(sc, &csz);
ff37e337 1383 /* XXX assert csz is non-zero */
17d7904d 1384 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1385
cbe61d8a 1386 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1387 if (ah == NULL) {
1388 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1389 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1390 error = -ENXIO;
1391 goto bad;
1392 }
1393 sc->sc_ah = ah;
1394
1395 /* Get the hardware key cache size. */
2660b81a 1396 sc->keymax = ah->caps.keycache_size;
17d7904d 1397 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1398 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1399 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1400 ATH_KEYMAX, sc->keymax);
1401 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1402 }
1403
1404 /*
1405 * Reset the key cache since some parts do not
1406 * reset the contents on initial power up.
1407 */
17d7904d 1408 for (i = 0; i < sc->keymax; i++)
ff37e337 1409 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1410
5f8e077c 1411 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1412 goto bad;
1413
1414 /* default to MONITOR mode */
2660b81a 1415 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1416
ff37e337
S		 1417 /* Setup rate tables */
1418
1419 ath_rate_attach(sc);
1420 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1421 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1422
1423 /*
1424 * Allocate hardware transmit queues: one queue for
1425 * beacon frames and one data queue for each QoS
1426 * priority. Note that the hal handles reseting
1427 * these queues at the needed time.
1428 */
b77f483f
S		 1429 sc->beacon.beaconq = ath_beaconq_setup(ah);
1430 if (sc->beacon.beaconq == -1) {
ff37e337 1431 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1432 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1433 error = -EIO;
1434 goto bad2;
1435 }
b77f483f
S		 1436 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1437 if (sc->beacon.cabq == NULL) {
ff37e337 1438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1439 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1440 error = -EIO;
1441 goto bad2;
1442 }
1443
17d7904d 1444 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1445 ath_cabq_update(sc);
1446
b77f483f
S		 1447 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1448 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1449
1450 /* Setup data queues */
1451 /* NB: ensure BK queue is the lowest priority h/w queue */
1452 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1453 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1454 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1455 error = -EIO;
1456 goto bad2;
1457 }
1458
1459 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1460 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1461 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1462 error = -EIO;
1463 goto bad2;
1464 }
1465 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1466 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1467 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1468 error = -EIO;
1469 goto bad2;
1470 }
1471 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1472 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1473 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1474 error = -EIO;
1475 goto bad2;
1476 }
1477
1478 /* Initializes the noise floor to a reasonable default value.
1479 * Later on this will be updated during ANI processing. */
1480
17d7904d
S		 1481 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1482 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1483
1484 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1485 ATH9K_CIPHER_TKIP, NULL)) {
1486 /*
1487 * Whether we should enable h/w TKIP MIC.
1488 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1489 * report WMM capable, so it's always safe to turn on
1490 * TKIP MIC in this case.
1491 */
1492 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1493 0, 1, NULL);
1494 }
1495
1496 /*
1497 * Check whether the separate key cache entries
1498 * are required to handle both tx+rx MIC keys.
1499 * With split mic keys the number of stations is limited
1500 * to 27 otherwise 59.
1501 */
1502 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1503 ATH9K_CIPHER_TKIP, NULL)
1504 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1505 ATH9K_CIPHER_MIC, NULL)
1506 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1507 0, NULL))
17d7904d 1508 sc->splitmic = 1;
ff37e337
S		 1509
1510 /* turn on mcast key search if possible */
1511 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1512 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1513 1, NULL);
1514
17d7904d 1515 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1516
1517 /* 11n Capabilities */
2660b81a 1518 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1519 sc->sc_flags |= SC_OP_TXAGGR;
1520 sc->sc_flags |= SC_OP_RXAGGR;
1521 }
1522
2660b81a
S		 1523 sc->tx_chainmask = ah->caps.tx_chainmask;
1524 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1525
1526 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1527 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1528
8ca21f01 1529 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1530 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1531
b77f483f 1532 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1533
1534 /* initialize beacon slots */
c52f33d0 1535 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1536 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1537 sc->beacon.bslot_aphy[i] = NULL;
1538 }
ff37e337
S		 1539
1540 /* save MISC configurations */
17d7904d 1541 sc->config.swBeaconProcess = 1;
ff37e337 1542
ff37e337
S		 1543 /* setup channels and rates */
1544
5f8e077c 1545 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1546 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1547 sc->rates[IEEE80211_BAND_2GHZ];
1548 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1549 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1550 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1551
2660b81a 1552 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1553 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1554 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1555 sc->rates[IEEE80211_BAND_5GHZ];
1556 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1557 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1558 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1559 }
1560
2660b81a 1561 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1562 ath9k_hw_btcoex_enable(sc->sc_ah);
1563
ff37e337
S		 1564 return 0;
1565bad2:
1566 /* cleanup tx queues */
1567 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1568 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1569 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1570bad:
1571 if (ah)
1572 ath9k_hw_detach(ah);
40b130a9 1573 ath9k_exit_debug(sc);
ff37e337
S		 1574
1575 return error;
1576}
1577
c52f33d0 1578void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1579{
9c84b797
S		 1580 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1581 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1583 IEEE80211_HW_AMPDU_AGGREGATION |
1584 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1585 IEEE80211_HW_PS_NULLFUNC_STACK |
1586 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1587
b3bd89ce 1588 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1589 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1590
9c84b797
S		 1591 hw->wiphy->interface_modes =
1592 BIT(NL80211_IFTYPE_AP) |
1593 BIT(NL80211_IFTYPE_STATION) |
1594 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1595
5f8e077c
LR		 1596 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1597 hw->wiphy->strict_regulatory = true;
1598
8feceb67 1599 hw->queues = 4;
e63835b0 1600 hw->max_rates = 4;
171387ef 1601 hw->channel_change_time = 5000;
465ca84d 1602 hw->max_listen_interval = 10;
e63835b0 1603 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1604 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1605 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1606
8feceb67 1607 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1608
c52f33d0
JM		 1609 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1610 &sc->sbands[IEEE80211_BAND_2GHZ];
1611 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1612 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1613 &sc->sbands[IEEE80211_BAND_5GHZ];
1614}
1615
1616int ath_attach(u16 devid, struct ath_softc *sc)
1617{
1618 struct ieee80211_hw *hw = sc->hw;
1619 const struct ieee80211_regdomain *regd;
1620 int error = 0, i;
1621
1622 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1623
1624 error = ath_init(devid, sc);
1625 if (error != 0)
1626 return error;
1627
1628 /* get mac address from hardware and set in mac80211 */
1629
1630 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1631
1632 ath_set_hw_capab(sc, hw);
1633
2660b81a 1634 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1635 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1636 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1637 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1638 }
1639
db93e7b5
SB		 1640 /* initialize tx/rx engine */
1641 error = ath_tx_init(sc, ATH_TXBUF);
1642 if (error != 0)
40b130a9 1643 goto error_attach;
8feceb67 1644
db93e7b5
SB		 1645 error = ath_rx_init(sc, ATH_RXBUF);
1646 if (error != 0)
40b130a9 1647 goto error_attach;
8feceb67 1648
e97275cb 1649#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1650 /* Initialze h/w Rfkill */
2660b81a 1651 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1652 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1653
1654 /* Initialize s/w rfkill */
40b130a9
VT		 1655 error = ath_init_sw_rfkill(sc);
1656 if (error)
1657 goto error_attach;
500c064d
VT		 1658#endif
1659
5f8e077c 1660 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1661 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1662 * saved on the wiphy orig_* parameters */
191a99b7 1663 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1664 hw->wiphy->custom_regulatory = true;
1665 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1666 } else {
1667 /* This gets applied in the case of the absense of CRDA,
191a99b7 1668 * it's our own custom world regulatory domain, similar to
5f8e077c 1669 * cfg80211's but we enable passive scanning */
191a99b7 1670 regd = ath9k_default_world_regdomain();
5f8e077c 1671 }
191a99b7
BC		 1672 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1673 ath9k_reg_apply_radar_flags(hw->wiphy);
7db90f4a 1674 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
5f8e077c 1675
0e2dedf9 1676 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1677 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1678 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1679
db93e7b5 1680 error = ieee80211_register_hw(hw);
8feceb67 1681
fe33eb39
LR		 1682 if (!ath9k_is_world_regd(sc->sc_ah)) {
1683 error = regulatory_hint(hw->wiphy,
1684 sc->sc_ah->regulatory.alpha2);
1685 if (error)
1686 goto error_attach;
1687 }
5f8e077c 1688
db93e7b5
SB		 1689 /* Initialize LED control */
1690 ath_init_leds(sc);
8feceb67 1691
5f8e077c 1692
8feceb67 1693 return 0;
40b130a9
VT		 1694
1695error_attach:
1696 /* cleanup tx queues */
1697 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1698 if (ATH_TXQ_SETUP(sc, i))
1699 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1700
1701 ath9k_hw_detach(sc->sc_ah);
1702 ath9k_exit_debug(sc);
1703
8feceb67 1704 return error;
f078f209
LR		 1705}
1706
ff37e337
S		 1707int ath_reset(struct ath_softc *sc, bool retry_tx)
1708{
cbe61d8a 1709 struct ath_hw *ah = sc->sc_ah;
030bb495 1710 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1711 int r;
ff37e337
S		 1712
1713 ath9k_hw_set_interrupts(ah, 0);
043a0405 1714 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1715 ath_stoprecv(sc);
1716 ath_flushrecv(sc);
1717
1718 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1719 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1720 if (r)
ff37e337 1721 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1722 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1723 spin_unlock_bh(&sc->sc_resetlock);
1724
1725 if (ath_startrecv(sc) != 0)
04bd4638 1726 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1727
1728 /*
1729 * We may be doing a reset in response to a request
1730 * that changes the channel so update any state that
1731 * might change as a result.
1732 */
ce111bad 1733 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1734
1735 ath_update_txpow(sc);
1736
1737 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1738 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1739
17d7904d 1740 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1741
1742 if (retry_tx) {
1743 int i;
1744 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1745 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1746 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1747 ath_txq_schedule(sc, &sc->tx.txq[i]);
1748 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1749 }
1750 }
1751 }
1752
ae8d2858 1753 return r;
ff37e337
S		 1754}
1755
1756/*
1757 * This function will allocate both the DMA descriptor structure, and the
1758 * buffers it contains. These are used to contain the descriptors used
1759 * by the system.
1760*/
1761int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1762 struct list_head *head, const char *name,
1763 int nbuf, int ndesc)
1764{
1765#define DS2PHYS(_dd, _ds) \
1766 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1767#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1768#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1769
1770 struct ath_desc *ds;
1771 struct ath_buf *bf;
1772 int i, bsize, error;
1773
04bd4638
S		 1774 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1775 name, nbuf, ndesc);
ff37e337 1776
b03a9db9 1777 INIT_LIST_HEAD(head);
ff37e337
S		 1778 /* ath_desc must be a multiple of DWORDs */
1779 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1780 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1781 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1782 error = -ENOMEM;
1783 goto fail;
1784 }
1785
1786 dd->dd_name = name;
1787 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1788
1789 /*
1790 * Need additional DMA memory because we can't use
1791 * descriptors that cross the 4K page boundary. Assume
1792 * one skipped descriptor per 4K page.
1793 */
2660b81a 1794 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1795 u32 ndesc_skipped =
1796 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1797 u32 dma_len;
1798
1799 while (ndesc_skipped) {
1800 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1801 dd->dd_desc_len += dma_len;
1802
1803 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1804 };
1805 }
1806
1807 /* allocate descriptors */
7da3c55c 1808 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1809 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1810 if (dd->dd_desc == NULL) {
1811 error = -ENOMEM;
1812 goto fail;
1813 }
1814 ds = dd->dd_desc;
04bd4638
S		 1815 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1816 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1817 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1818
1819 /* allocate buffers */
1820 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1821 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1822 if (bf == NULL) {
1823 error = -ENOMEM;
1824 goto fail2;
1825 }
ff37e337
S		 1826 dd->dd_bufptr = bf;
1827
ff37e337
S		 1828 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1829 bf->bf_desc = ds;
1830 bf->bf_daddr = DS2PHYS(dd, ds);
1831
2660b81a 1832 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1833 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1834 /*
1835 * Skip descriptor addresses which can cause 4KB
1836 * boundary crossing (addr + length) with a 32 dword
1837 * descriptor fetch.
1838 */
1839 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1840 ASSERT((caddr_t) bf->bf_desc <
1841 ((caddr_t) dd->dd_desc +
1842 dd->dd_desc_len));
1843
1844 ds += ndesc;
1845 bf->bf_desc = ds;
1846 bf->bf_daddr = DS2PHYS(dd, ds);
1847 }
1848 }
1849 list_add_tail(&bf->list, head);
1850 }
1851 return 0;
1852fail2:
7da3c55c
GJ		 1853 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1854 dd->dd_desc_paddr);
ff37e337
S		 1855fail:
1856 memset(dd, 0, sizeof(*dd));
1857 return error;
1858#undef ATH_DESC_4KB_BOUND_CHECK
1859#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1860#undef DS2PHYS
1861}
1862
1863void ath_descdma_cleanup(struct ath_softc *sc,
1864 struct ath_descdma *dd,
1865 struct list_head *head)
1866{
7da3c55c
GJ		 1867 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1868 dd->dd_desc_paddr);
ff37e337
S		 1869
1870 INIT_LIST_HEAD(head);
1871 kfree(dd->dd_bufptr);
1872 memset(dd, 0, sizeof(*dd));
1873}
1874
1875int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1876{
1877 int qnum;
1878
1879 switch (queue) {
1880 case 0:
b77f483f 1881 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1882 break;
1883 case 1:
b77f483f 1884 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1885 break;
1886 case 2:
b77f483f 1887 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1888 break;
1889 case 3:
b77f483f 1890 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1891 break;
1892 default:
b77f483f 1893 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1894 break;
1895 }
1896
1897 return qnum;
1898}
1899
1900int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1901{
1902 int qnum;
1903
1904 switch (queue) {
1905 case ATH9K_WME_AC_VO:
1906 qnum = 0;
1907 break;
1908 case ATH9K_WME_AC_VI:
1909 qnum = 1;
1910 break;
1911 case ATH9K_WME_AC_BE:
1912 qnum = 2;
1913 break;
1914 case ATH9K_WME_AC_BK:
1915 qnum = 3;
1916 break;
1917 default:
1918 qnum = -1;
1919 break;
1920 }
1921
1922 return qnum;
1923}
1924
5f8e077c
LR		 1925/* XXX: Remove me once we don't depend on ath9k_channel for all
1926 * this redundant data */
0e2dedf9
JM		 1927void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1928 struct ath9k_channel *ichan)
5f8e077c 1929{
5f8e077c
LR		 1930 struct ieee80211_channel *chan = hw->conf.channel;
1931 struct ieee80211_conf *conf = &hw->conf;
1932
1933 ichan->channel = chan->center_freq;
1934 ichan->chan = chan;
1935
1936 if (chan->band == IEEE80211_BAND_2GHZ) {
1937 ichan->chanmode = CHANNEL_G;
1938 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1939 } else {
1940 ichan->chanmode = CHANNEL_A;
1941 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1942 }
1943
1944 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1945
1946 if (conf_is_ht(conf)) {
1947 if (conf_is_ht40(conf))
1948 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1949
1950 ichan->chanmode = ath_get_extchanmode(sc, chan,
1951 conf->channel_type);
1952 }
1953}
1954
ff37e337
S		 1955/**********************/
1956/* mac80211 callbacks */
1957/**********************/
1958
8feceb67 1959static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1960{
bce048d7
JM		 1961 struct ath_wiphy *aphy = hw->priv;
1962 struct ath_softc *sc = aphy->sc;
8feceb67 1963 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1964 struct ath9k_channel *init_channel;
ae8d2858 1965 int r, pos;
f078f209 1966
04bd4638
S		 1967 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1968 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1969
141b38b6
S		 1970 mutex_lock(&sc->mutex);
1971
9580a222
JM		 1972 if (ath9k_wiphy_started(sc)) {
1973 if (sc->chan_idx == curchan->hw_value) {
1974 /*
1975 * Already on the operational channel, the new wiphy
1976 * can be marked active.
1977 */
1978 aphy->state = ATH_WIPHY_ACTIVE;
1979 ieee80211_wake_queues(hw);
1980 } else {
1981 /*
1982 * Another wiphy is on another channel, start the new
1983 * wiphy in paused state.
1984 */
1985 aphy->state = ATH_WIPHY_PAUSED;
1986 ieee80211_stop_queues(hw);
1987 }
1988 mutex_unlock(&sc->mutex);
1989 return 0;
1990 }
1991 aphy->state = ATH_WIPHY_ACTIVE;
1992
8feceb67 1993 /* setup initial channel */
f078f209 1994
5f8e077c 1995 pos = curchan->hw_value;
f078f209 1996
0e2dedf9 1997 sc->chan_idx = pos;
2660b81a 1998 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 1999 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 2000
2001 /* Reset SERDES registers */
2002 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2003
2004 /*
2005 * The basic interface to setting the hardware in a good
2006 * state is ``reset''. On return the hardware is known to
2007 * be powered up and with interrupts disabled. This must
2008 * be followed by initialization of the appropriate bits
2009 * and then setup of the interrupt mask.
2010 */
2011 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 2012 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2013 if (r) {
ff37e337 2014 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 2015 "Unable to reset hardware; reset status %u "
2016 "(freq %u MHz)\n", r,
2017 curchan->center_freq);
ff37e337 2018 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2019 goto mutex_unlock;
ff37e337
S		 2020 }
2021 spin_unlock_bh(&sc->sc_resetlock);
2022
2023 /*
2024 * This is needed only to setup initial state
2025 * but it's best done after a reset.
2026 */
2027 ath_update_txpow(sc);
8feceb67 2028
ff37e337
S		 2029 /*
2030 * Setup the hardware after reset:
2031 * The receive engine is set going.
2032 * Frame transmit is handled entirely
2033 * in the frame output path; there's nothing to do
2034 * here except setup the interrupt mask.
2035 */
2036 if (ath_startrecv(sc) != 0) {
8feceb67 2037 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2038 "Unable to start recv logic\n");
141b38b6
S		 2039 r = -EIO;
2040 goto mutex_unlock;
f078f209 2041 }
8feceb67 2042
ff37e337 2043 /* Setup our intr mask. */
17d7904d 2044 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2045 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2046 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2047
2660b81a 2048 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2049 sc->imask |= ATH9K_INT_GTT;
ff37e337 2050
2660b81a 2051 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2052 sc->imask |= ATH9K_INT_CST;
ff37e337 2053
ce111bad 2054 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2055
2056 sc->sc_flags &= ~SC_OP_INVALID;
2057
2058 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2059 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2060 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2061
bce048d7 2062 ieee80211_wake_queues(hw);
ff37e337 2063
e97275cb 2064#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2065 r = ath_start_rfkill_poll(sc);
500c064d 2066#endif
141b38b6
S		 2067
2068mutex_unlock:
2069 mutex_unlock(&sc->mutex);
2070
ae8d2858 2071 return r;
f078f209
LR		 2072}
2073
8feceb67
VT		 2074static int ath9k_tx(struct ieee80211_hw *hw,
2075 struct sk_buff *skb)
f078f209 2076{
528f0c6b 2077 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2078 struct ath_wiphy *aphy = hw->priv;
2079 struct ath_softc *sc = aphy->sc;
528f0c6b 2080 struct ath_tx_control txctl;
8feceb67 2081 int hdrlen, padsize;
528f0c6b 2082
8089cc47 2083 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2084 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2085 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2086 goto exit;
2087 }
2088
528f0c6b 2089 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2090
8feceb67
VT		 2091 /*
2092 * As a temporary workaround, assign seq# here; this will likely need
2093 * to be cleaned up to work better with Beacon transmission and virtual
2094 * BSSes.
2095 */
2096 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2097 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2098 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2099 sc->tx.seq_no += 0x10;
8feceb67 2100 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2101 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2102 }
f078f209 2103
8feceb67
VT		 2104 /* Add the padding after the header if this is not already done */
2105 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2106 if (hdrlen & 3) {
2107 padsize = hdrlen % 4;
2108 if (skb_headroom(skb) < padsize)
2109 return -1;
2110 skb_push(skb, padsize);
2111 memmove(skb->data, skb->data + padsize, hdrlen);
2112 }
2113
528f0c6b
S		 2114 /* Check if a tx queue is available */
2115
2116 txctl.txq = ath_test_get_txq(sc, skb);
2117 if (!txctl.txq)
2118 goto exit;
2119
04bd4638 2120 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2121
c52f33d0 2122 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2123 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2124 goto exit;
8feceb67
VT		 2125 }
2126
528f0c6b
S		 2127 return 0;
2128exit:
2129 dev_kfree_skb_any(skb);
8feceb67 2130 return 0;
f078f209
LR		 2131}
2132
8feceb67 2133static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2134{
bce048d7
JM		 2135 struct ath_wiphy *aphy = hw->priv;
2136 struct ath_softc *sc = aphy->sc;
f078f209 2137
9580a222
JM		 2138 aphy->state = ATH_WIPHY_INACTIVE;
2139
9c84b797 2140 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2141 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2142 return;
2143 }
8feceb67 2144
141b38b6 2145 mutex_lock(&sc->mutex);
ff37e337 2146
bce048d7 2147 ieee80211_stop_queues(hw);
ff37e337 2148
9580a222
JM		 2149 if (ath9k_wiphy_started(sc)) {
2150 mutex_unlock(&sc->mutex);
2151 return; /* another wiphy still in use */
2152 }
2153
ff37e337
S		 2154 /* make sure h/w will not generate any interrupt
2155 * before setting the invalid flag. */
2156 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2157
2158 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2159 ath_drain_all_txq(sc, false);
ff37e337
S		 2160 ath_stoprecv(sc);
2161 ath9k_hw_phy_disable(sc->sc_ah);
2162 } else
b77f483f 2163 sc->rx.rxlink = NULL;
ff37e337
S		 2164
2165#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2166 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2167 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2168#endif
2169 /* disable HAL and put h/w to sleep */
2170 ath9k_hw_disable(sc->sc_ah);
2171 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2172
2173 sc->sc_flags |= SC_OP_INVALID;
500c064d 2174
141b38b6
S		 2175 mutex_unlock(&sc->mutex);
2176
04bd4638 2177 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2178}
2179
8feceb67
VT		 2180static int ath9k_add_interface(struct ieee80211_hw *hw,
2181 struct ieee80211_if_init_conf *conf)
f078f209 2182{
bce048d7
JM		 2183 struct ath_wiphy *aphy = hw->priv;
2184 struct ath_softc *sc = aphy->sc;
17d7904d 2185 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2186 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2187 int ret = 0;
8feceb67 2188
141b38b6
S		 2189 mutex_lock(&sc->mutex);
2190
8ca21f01
JM		 2191 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2192 sc->nvifs > 0) {
2193 ret = -ENOBUFS;
2194 goto out;
2195 }
2196
8feceb67 2197 switch (conf->type) {
05c914fe 2198 case NL80211_IFTYPE_STATION:
d97809db 2199 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2200 break;
05c914fe 2201 case NL80211_IFTYPE_ADHOC:
2c3db3d5
JM		 2202 if (sc->nbcnvifs >= ATH_BCBUF) {
2203 ret = -ENOBUFS;
2204 goto out;
2205 }
d97809db 2206 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2207 break;
05c914fe 2208 case NL80211_IFTYPE_AP:
2c3db3d5
JM		 2209 if (sc->nbcnvifs >= ATH_BCBUF) {
2210 ret = -ENOBUFS;
2211 goto out;
2212 }
d97809db 2213 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2214 break;
2215 default:
2216 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2217 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2218 ret = -EOPNOTSUPP;
2219 goto out;
f078f209
LR		 2220 }
2221
17d7904d 2222 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2223
17d7904d 2224 /* Set the VIF opmode */
5640b08e
S		 2225 avp->av_opmode = ic_opmode;
2226 avp->av_bslot = -1;
2227
2c3db3d5 2228 sc->nvifs++;
8ca21f01
JM		 2229
2230 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2231 ath9k_set_bssid_mask(hw);
2232
2c3db3d5
JM		 2233 if (sc->nvifs > 1)
2234 goto out; /* skip global settings for secondary vif */
2235
b238e90e 2236 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2237 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2238 sc->sc_flags |= SC_OP_TSF_RESET;
2239 }
5640b08e 2240
5640b08e 2241 /* Set the device opmode */
2660b81a 2242 sc->sc_ah->opmode = ic_opmode;
5640b08e 2243
4e30ffa2
VN		 2244 /*
2245 * Enable MIB interrupts when there are hardware phy counters.
2246 * Note we only do this (at the moment) for station mode.
2247 */
4af9cf4f
S		 2248 if ((conf->type == NL80211_IFTYPE_STATION) ||
2249 (conf->type == NL80211_IFTYPE_ADHOC)) {
2250 if (ath9k_hw_phycounters(sc->sc_ah))
2251 sc->imask |= ATH9K_INT_MIB;
2252 sc->imask |= ATH9K_INT_TSFOOR;
2253 }
2254
4e30ffa2
VN		 2255 /*
2256 * Some hardware processes the TIM IE and fires an
2257 * interrupt when the TIM bit is set. For hardware
2258 * that does, if not overridden by configuration,
2259 * enable the TIM interrupt when operating as station.
2260 */
2660b81a 2261 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2262 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2263 !sc->config.swBeaconProcess)
2264 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2265
17d7904d 2266 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2267
6f255425
LR		 2268 if (conf->type == NL80211_IFTYPE_AP) {
2269 /* TODO: is this a suitable place to start ANI for AP mode? */
2270 /* Start ANI */
17d7904d 2271 mod_timer(&sc->ani.timer,
6f255425
LR		 2272 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2273 }
2274
2c3db3d5 2275out:
141b38b6 2276 mutex_unlock(&sc->mutex);
2c3db3d5 2277 return ret;
f078f209
LR		 2278}
2279
8feceb67
VT		 2280static void ath9k_remove_interface(struct ieee80211_hw *hw,
2281 struct ieee80211_if_init_conf *conf)
f078f209 2282{
bce048d7
JM		 2283 struct ath_wiphy *aphy = hw->priv;
2284 struct ath_softc *sc = aphy->sc;
17d7904d 2285 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2286 int i;
f078f209 2287
04bd4638 2288 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2289
141b38b6
S		 2290 mutex_lock(&sc->mutex);
2291
6f255425 2292 /* Stop ANI */
17d7904d 2293 del_timer_sync(&sc->ani.timer);
580f0b8a 2294
8feceb67 2295 /* Reclaim beacon resources */
2660b81a
S		 2296 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2297 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2298 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2299 ath_beacon_return(sc, avp);
580f0b8a 2300 }
f078f209 2301
8feceb67 2302 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2303
2c3db3d5
JM		 2304 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2305 if (sc->beacon.bslot[i] == conf->vif) {
2306 printk(KERN_DEBUG "%s: vif had allocated beacon "
2307 "slot\n", __func__);
2308 sc->beacon.bslot[i] = NULL;
c52f33d0 2309 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2310 }
2311 }
2312
17d7904d 2313 sc->nvifs--;
141b38b6
S		 2314
2315 mutex_unlock(&sc->mutex);
f078f209
LR		 2316}
2317
e8975581 2318static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2319{
bce048d7
JM		 2320 struct ath_wiphy *aphy = hw->priv;
2321 struct ath_softc *sc = aphy->sc;
e8975581 2322 struct ieee80211_conf *conf = &hw->conf;
f078f209 2323
aa33de09 2324 mutex_lock(&sc->mutex);
141b38b6 2325
3cbb5dd7
VN		 2326 if (changed & IEEE80211_CONF_CHANGE_PS) {
2327 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2328 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2329 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2330 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2331 sc->imask);
3cbb5dd7
VN		 2332 }
2333 ath9k_hw_setrxabort(sc->sc_ah, 1);
2334 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2335 } else {
2336 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2337 ath9k_hw_setrxabort(sc->sc_ah, 0);
2338 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2339 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2340 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2341 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2342 sc->imask);
3cbb5dd7
VN		 2343 }
2344 }
2345 }
2346
4797938c 2347 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2348 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2349 int pos = curchan->hw_value;
ae5eb026 2350
0e2dedf9
JM		 2351 aphy->chan_idx = pos;
2352 aphy->chan_is_ht = conf_is_ht(conf);
2353
8089cc47
JM		 2354 if (aphy->state == ATH_WIPHY_SCAN ||
2355 aphy->state == ATH_WIPHY_ACTIVE)
2356 ath9k_wiphy_pause_all_forced(sc, aphy);
2357 else {
2358 /*
2359 * Do not change operational channel based on a paused
2360 * wiphy changes.
2361 */
2362 goto skip_chan_change;
2363 }
0e2dedf9 2364
04bd4638
S		 2365 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2366 curchan->center_freq);
f078f209 2367
5f8e077c 2368 /* XXX: remove me eventualy */
0e2dedf9 2369 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2370
ecf70441 2371 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2372
0e2dedf9 2373 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2374 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2375 mutex_unlock(&sc->mutex);
e11602b7
S		 2376 return -EINVAL;
2377 }
094d05dc 2378 }
f078f209 2379
8089cc47 2380skip_chan_change:
5c020dc6 2381 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2382 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2383
b238e90e
S		 2384 /*
2385 * The HW TSF has to be reset when the beacon interval changes.
2386 * We set the flag here, and ath_beacon_config_ap() would take this
2387 * into account when it gets called through the subsequent
2388 * config_interface() call - with IFCC_BEACON in the changed field.
2389 */
2390
2391 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2392 sc->sc_flags |= SC_OP_TSF_RESET;
2393
aa33de09 2394 mutex_unlock(&sc->mutex);
141b38b6 2395
f078f209
LR		 2396 return 0;
2397}
2398
8feceb67
VT		 2399static int ath9k_config_interface(struct ieee80211_hw *hw,
2400 struct ieee80211_vif *vif,
2401 struct ieee80211_if_conf *conf)
c83be688 2402{
bce048d7
JM		 2403 struct ath_wiphy *aphy = hw->priv;
2404 struct ath_softc *sc = aphy->sc;
cbe61d8a 2405 struct ath_hw *ah = sc->sc_ah;
17d7904d 2406 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2407 u32 rfilt = 0;
2408 int error, i;
c83be688 2409
2554935b
S		 2410 mutex_lock(&sc->mutex);
2411
8feceb67
VT		 2412 /* TODO: Need to decide which hw opmode to use for multi-interface
2413 * cases */
05c914fe 2414 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2415 ah->opmode != NL80211_IFTYPE_AP) {
2416 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2417 ath9k_hw_setopmode(ah);
ba52da58
S		 2418 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2419 sc->curaid = 0;
2420 ath9k_hw_write_associd(sc);
8feceb67
VT		 2421 /* Request full reset to get hw opmode changed properly */
2422 sc->sc_flags |= SC_OP_FULL_RESET;
2423 }
c83be688 2424
8feceb67
VT		 2425 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2426 !is_zero_ether_addr(conf->bssid)) {
2427 switch (vif->type) {
05c914fe
JB		 2428 case NL80211_IFTYPE_STATION:
2429 case NL80211_IFTYPE_ADHOC:
8feceb67 2430 /* Set BSSID */
17d7904d 2431 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
f0ed85c6 2432 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
17d7904d 2433 sc->curaid = 0;
ba52da58 2434 ath9k_hw_write_associd(sc);
c83be688 2435
8feceb67 2436 /* Set aggregation protection mode parameters */
17d7904d 2437 sc->config.ath_aggr_prot = 0;
c83be688 2438
8feceb67 2439 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2440 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2441 rfilt, sc->curbssid, sc->curaid);
c83be688 2442
8feceb67
VT		 2443 /* need to reconfigure the beacon */
2444 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2445
8feceb67
VT		 2446 break;
2447 default:
2448 break;
2449 }
2450 }
c83be688 2451
1f7d6cbf
S		 2452 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2453 (vif->type == NL80211_IFTYPE_AP)) {
2454 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2455 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2456 conf->enable_beacon)) {
2457 /*
2458 * Allocate and setup the beacon frame.
2459 *
2460 * Stop any previous beacon DMA. This may be
2461 * necessary, for example, when an ibss merge
2462 * causes reconfiguration; we may be called
2463 * with beacon transmission active.
2464 */
2465 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2466
c52f33d0 2467 error = ath_beacon_alloc(aphy, vif);
2554935b
S		 2468 if (error != 0) {
2469 mutex_unlock(&sc->mutex);
1f7d6cbf 2470 return error;
2554935b 2471 }
c83be688 2472
2c3db3d5 2473 ath_beacon_config(sc, vif);
1f7d6cbf 2474 }
8feceb67 2475 }
c83be688 2476
8feceb67 2477 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2478 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2479 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2480 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2481 ath9k_hw_keysetmac(sc->sc_ah,
2482 (u16)i,
17d7904d 2483 sc->curbssid);
8feceb67 2484 }
c83be688 2485
8feceb67 2486 /* Only legacy IBSS for now */
05c914fe 2487 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2488 ath_update_chainmask(sc, 0);
f078f209 2489
2554935b
S		 2490 mutex_unlock(&sc->mutex);
2491
8feceb67
VT		 2492 return 0;
2493}
f078f209 2494
8feceb67
VT		 2495#define SUPPORTED_FILTERS \
2496 (FIF_PROMISC_IN_BSS | \
2497 FIF_ALLMULTI | \
2498 FIF_CONTROL | \
2499 FIF_OTHER_BSS | \
2500 FIF_BCN_PRBRESP_PROMISC | \
2501 FIF_FCSFAIL)
c83be688 2502
8feceb67
VT		 2503/* FIXME: sc->sc_full_reset ? */
2504static void ath9k_configure_filter(struct ieee80211_hw *hw,
2505 unsigned int changed_flags,
2506 unsigned int *total_flags,
2507 int mc_count,
2508 struct dev_mc_list *mclist)
2509{
bce048d7
JM		 2510 struct ath_wiphy *aphy = hw->priv;
2511 struct ath_softc *sc = aphy->sc;
8feceb67 2512 u32 rfilt;
f078f209 2513
8feceb67
VT		 2514 changed_flags &= SUPPORTED_FILTERS;
2515 *total_flags &= SUPPORTED_FILTERS;
f078f209 2516
b77f483f 2517 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2518 rfilt = ath_calcrxfilter(sc);
2519 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2520
b77f483f 2521 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2522}
f078f209 2523
8feceb67
VT		 2524static void ath9k_sta_notify(struct ieee80211_hw *hw,
2525 struct ieee80211_vif *vif,
2526 enum sta_notify_cmd cmd,
17741cdc 2527 struct ieee80211_sta *sta)
8feceb67 2528{
bce048d7
JM		 2529 struct ath_wiphy *aphy = hw->priv;
2530 struct ath_softc *sc = aphy->sc;
f078f209 2531
8feceb67
VT		 2532 switch (cmd) {
2533 case STA_NOTIFY_ADD:
5640b08e 2534 ath_node_attach(sc, sta);
8feceb67
VT		 2535 break;
2536 case STA_NOTIFY_REMOVE:
b5aa9bf9 2537 ath_node_detach(sc, sta);
8feceb67
VT		 2538 break;
2539 default:
2540 break;
2541 }
f078f209
LR		 2542}
2543
141b38b6 2544static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2545 const struct ieee80211_tx_queue_params *params)
f078f209 2546{
bce048d7
JM		 2547 struct ath_wiphy *aphy = hw->priv;
2548 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2549 struct ath9k_tx_queue_info qi;
2550 int ret = 0, qnum;
f078f209 2551
8feceb67
VT		 2552 if (queue >= WME_NUM_AC)
2553 return 0;
f078f209 2554
141b38b6
S		 2555 mutex_lock(&sc->mutex);
2556
8feceb67
VT		 2557 qi.tqi_aifs = params->aifs;
2558 qi.tqi_cwmin = params->cw_min;
2559 qi.tqi_cwmax = params->cw_max;
2560 qi.tqi_burstTime = params->txop;
2561 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2562
8feceb67 2563 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2564 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2565 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2566 queue, qnum, params->aifs, params->cw_min,
2567 params->cw_max, params->txop);
f078f209 2568
8feceb67
VT		 2569 ret = ath_txq_update(sc, qnum, &qi);
2570 if (ret)
04bd4638 2571 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2572
141b38b6
S		 2573 mutex_unlock(&sc->mutex);
2574
8feceb67
VT		 2575 return ret;
2576}
f078f209 2577
8feceb67
VT		 2578static int ath9k_set_key(struct ieee80211_hw *hw,
2579 enum set_key_cmd cmd,
dc822b5d
JB		 2580 struct ieee80211_vif *vif,
2581 struct ieee80211_sta *sta,
8feceb67
VT		 2582 struct ieee80211_key_conf *key)
2583{
bce048d7
JM		 2584 struct ath_wiphy *aphy = hw->priv;
2585 struct ath_softc *sc = aphy->sc;
8feceb67 2586 int ret = 0;
f078f209 2587
b3bd89ce
JM		 2588 if (modparam_nohwcrypt)
2589 return -ENOSPC;
2590
141b38b6 2591 mutex_lock(&sc->mutex);
3cbb5dd7 2592 ath9k_ps_wakeup(sc);
04bd4638 2593 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2594
8feceb67
VT		 2595 switch (cmd) {
2596 case SET_KEY:
3f53dd64 2597 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2598 if (ret >= 0) {
2599 key->hw_key_idx = ret;
8feceb67
VT		 2600 /* push IV and Michael MIC generation to stack */
2601 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2602 if (key->alg == ALG_TKIP)
2603 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2604 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2605 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2606 ret = 0;
8feceb67
VT		 2607 }
2608 break;
2609 case DISABLE_KEY:
2610 ath_key_delete(sc, key);
8feceb67
VT		 2611 break;
2612 default:
2613 ret = -EINVAL;
2614 }
f078f209 2615
3cbb5dd7 2616 ath9k_ps_restore(sc);
141b38b6
S		 2617 mutex_unlock(&sc->mutex);
2618
8feceb67
VT		 2619 return ret;
2620}
f078f209 2621
8feceb67
VT		 2622static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2623 struct ieee80211_vif *vif,
2624 struct ieee80211_bss_conf *bss_conf,
2625 u32 changed)
2626{
bce048d7
JM		 2627 struct ath_wiphy *aphy = hw->priv;
2628 struct ath_softc *sc = aphy->sc;
f078f209 2629
141b38b6
S		 2630 mutex_lock(&sc->mutex);
2631
8feceb67 2632 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2633 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2634 bss_conf->use_short_preamble);
2635 if (bss_conf->use_short_preamble)
2636 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2637 else
2638 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2639 }
f078f209 2640
8feceb67 2641 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2642 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2643 bss_conf->use_cts_prot);
2644 if (bss_conf->use_cts_prot &&
2645 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2646 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2647 else
2648 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2649 }
f078f209 2650
8feceb67 2651 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2652 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2653 bss_conf->assoc);
5640b08e 2654 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2655 }
141b38b6
S		 2656
2657 mutex_unlock(&sc->mutex);
8feceb67 2658}
f078f209 2659
8feceb67
VT		 2660static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2661{
2662 u64 tsf;
bce048d7
JM		 2663 struct ath_wiphy *aphy = hw->priv;
2664 struct ath_softc *sc = aphy->sc;
f078f209 2665
141b38b6
S		 2666 mutex_lock(&sc->mutex);
2667 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2668 mutex_unlock(&sc->mutex);
f078f209 2669
8feceb67
VT		 2670 return tsf;
2671}
f078f209 2672
3b5d665b
AF		 2673static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2674{
bce048d7
JM		 2675 struct ath_wiphy *aphy = hw->priv;
2676 struct ath_softc *sc = aphy->sc;
3b5d665b 2677
141b38b6
S		 2678 mutex_lock(&sc->mutex);
2679 ath9k_hw_settsf64(sc->sc_ah, tsf);
2680 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2681}
2682
8feceb67
VT		 2683static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2684{
bce048d7
JM		 2685 struct ath_wiphy *aphy = hw->priv;
2686 struct ath_softc *sc = aphy->sc;
c83be688 2687
141b38b6
S		 2688 mutex_lock(&sc->mutex);
2689 ath9k_hw_reset_tsf(sc->sc_ah);
2690 mutex_unlock(&sc->mutex);
8feceb67 2691}
f078f209 2692
8feceb67 2693static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2694 enum ieee80211_ampdu_mlme_action action,
2695 struct ieee80211_sta *sta,
2696 u16 tid, u16 *ssn)
8feceb67 2697{
bce048d7
JM		 2698 struct ath_wiphy *aphy = hw->priv;
2699 struct ath_softc *sc = aphy->sc;
8feceb67 2700 int ret = 0;
f078f209 2701
8feceb67
VT		 2702 switch (action) {
2703 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2704 if (!(sc->sc_flags & SC_OP_RXAGGR))
2705 ret = -ENOTSUPP;
8feceb67
VT		 2706 break;
2707 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2708 break;
2709 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2710 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2711 if (ret < 0)
2712 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2713 "Unable to start TX aggregation\n");
8feceb67 2714 else
17741cdc 2715 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2716 break;
2717 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2718 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2719 if (ret < 0)
2720 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2721 "Unable to stop TX aggregation\n");
f078f209 2722
17741cdc 2723 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2724 break;
8469cdef
S		 2725 case IEEE80211_AMPDU_TX_RESUME:
2726 ath_tx_aggr_resume(sc, sta, tid);
2727 break;
8feceb67 2728 default:
04bd4638 2729 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2730 }
2731
2732 return ret;
f078f209
LR		 2733}
2734
0c98de65
S		 2735static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2736{
bce048d7
JM		 2737 struct ath_wiphy *aphy = hw->priv;
2738 struct ath_softc *sc = aphy->sc;
0c98de65 2739
8089cc47
JM		 2740 if (ath9k_wiphy_scanning(sc)) {
2741 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2742 "same time\n");
2743 /*
2744 * Do not allow the concurrent scanning state for now. This
2745 * could be improved with scanning control moved into ath9k.
2746 */
2747 return;
2748 }
2749
2750 aphy->state = ATH_WIPHY_SCAN;
2751 ath9k_wiphy_pause_all_forced(sc, aphy);
2752
0c98de65
S		 2753 mutex_lock(&sc->mutex);
2754 sc->sc_flags |= SC_OP_SCANNING;
2755 mutex_unlock(&sc->mutex);
2756}
2757
2758static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2759{
bce048d7
JM		 2760 struct ath_wiphy *aphy = hw->priv;
2761 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2762
2763 mutex_lock(&sc->mutex);
8089cc47 2764 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65
S		 2765 sc->sc_flags &= ~SC_OP_SCANNING;
2766 mutex_unlock(&sc->mutex);
2767}
2768
6baff7f9 2769struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2770 .tx = ath9k_tx,
2771 .start = ath9k_start,
2772 .stop = ath9k_stop,
2773 .add_interface = ath9k_add_interface,
2774 .remove_interface = ath9k_remove_interface,
2775 .config = ath9k_config,
2776 .config_interface = ath9k_config_interface,
2777 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2778 .sta_notify = ath9k_sta_notify,
2779 .conf_tx = ath9k_conf_tx,
8feceb67 2780 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2781 .set_key = ath9k_set_key,
8feceb67 2782 .get_tsf = ath9k_get_tsf,
3b5d665b 2783 .set_tsf = ath9k_set_tsf,
8feceb67 2784 .reset_tsf = ath9k_reset_tsf,
4233df6b 2785 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2786 .sw_scan_start = ath9k_sw_scan_start,
2787 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2788};
2789
392dff83
BP		 2790static struct {
2791 u32 version;
2792 const char * name;
2793} ath_mac_bb_names[] = {
2794 { AR_SREV_VERSION_5416_PCI, "5416" },
2795 { AR_SREV_VERSION_5416_PCIE, "5418" },
2796 { AR_SREV_VERSION_9100, "9100" },
2797 { AR_SREV_VERSION_9160, "9160" },
2798 { AR_SREV_VERSION_9280, "9280" },
2799 { AR_SREV_VERSION_9285, "9285" }
2800};
2801
2802static struct {
2803 u16 version;
2804 const char * name;
2805} ath_rf_names[] = {
2806 { 0, "5133" },
2807 { AR_RAD5133_SREV_MAJOR, "5133" },
2808 { AR_RAD5122_SREV_MAJOR, "5122" },
2809 { AR_RAD2133_SREV_MAJOR, "2133" },
2810 { AR_RAD2122_SREV_MAJOR, "2122" }
2811};
2812
2813/*
2814 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2815 */
6baff7f9 2816const char *
392dff83
BP		 2817ath_mac_bb_name(u32 mac_bb_version)
2818{
2819 int i;
2820
2821 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2822 if (ath_mac_bb_names[i].version == mac_bb_version) {
2823 return ath_mac_bb_names[i].name;
2824 }
2825 }
2826
2827 return "????";
2828}
2829
2830/*
2831 * Return the RF name. "????" is returned if the RF is unknown.
2832 */
6baff7f9 2833const char *
392dff83
BP		 2834ath_rf_name(u16 rf_version)
2835{
2836 int i;
2837
2838 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2839 if (ath_rf_names[i].version == rf_version) {
2840 return ath_rf_names[i].name;
2841 }
2842 }
2843
2844 return "????";
2845}
2846
6baff7f9 2847static int __init ath9k_init(void)
f078f209 2848{
ca8a8560
VT		 2849 int error;
2850
ca8a8560
VT		 2851 /* Register rate control algorithm */
2852 error = ath_rate_control_register();
2853 if (error != 0) {
2854 printk(KERN_ERR
b51bb3cd
LR		 2855 "ath9k: Unable to register rate control "
2856 "algorithm: %d\n",
ca8a8560 2857 error);
6baff7f9 2858 goto err_out;
ca8a8560
VT		 2859 }
2860
19d8bc22
GJ		 2861 error = ath9k_debug_create_root();
2862 if (error) {
2863 printk(KERN_ERR
2864 "ath9k: Unable to create debugfs root: %d\n",
2865 error);
2866 goto err_rate_unregister;
2867 }
2868
6baff7f9
GJ		 2869 error = ath_pci_init();
2870 if (error < 0) {
f078f209 2871 printk(KERN_ERR
b51bb3cd 2872 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2873 error = -ENODEV;
19d8bc22 2874 goto err_remove_root;
f078f209
LR		 2875 }
2876
09329d37
GJ		 2877 error = ath_ahb_init();
2878 if (error < 0) {
2879 error = -ENODEV;
2880 goto err_pci_exit;
2881 }
2882
f078f209 2883 return 0;
6baff7f9 2884
09329d37
GJ		 2885 err_pci_exit:
2886 ath_pci_exit();
2887
19d8bc22
GJ		 2888 err_remove_root:
2889 ath9k_debug_remove_root();
6baff7f9
GJ		 2890 err_rate_unregister:
2891 ath_rate_control_unregister();
2892 err_out:
2893 return error;
f078f209 2894}
6baff7f9 2895module_init(ath9k_init);
f078f209 2896
6baff7f9 2897static void __exit ath9k_exit(void)
f078f209 2898{
09329d37 2899 ath_ahb_exit();
6baff7f9 2900 ath_pci_exit();
19d8bc22 2901 ath9k_debug_remove_root();
ca8a8560 2902 ath_rate_control_unregister();
04bd4638 2903 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2904}
6baff7f9 2905module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)