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ath9k: use ieee80211_conf on ath9k_hw_iscal_supported()
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
e7594072 37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
f078f209
LR		 38 { 0 }
39};
40
9757d556
S		 41static void ath_detach(struct ath_softc *sc);
42
ff37e337
S		 43/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60}
61
ce111bad
LR		 62static void ath_cache_conf_rate(struct ath_softc *sc,
63 struct ieee80211_conf *conf)
ff37e337 64{
030bb495
LR		 65 switch (conf->channel->band) {
66 case IEEE80211_BAND_2GHZ:
67 if (conf_is_ht20(conf))
68 sc->cur_rate_table =
69 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
70 else if (conf_is_ht40_minus(conf))
71 sc->cur_rate_table =
72 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
73 else if (conf_is_ht40_plus(conf))
74 sc->cur_rate_table =
75 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 76 else
030bb495
LR		 77 sc->cur_rate_table =
78 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 79 break;
80 case IEEE80211_BAND_5GHZ:
81 if (conf_is_ht20(conf))
82 sc->cur_rate_table =
83 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
84 else if (conf_is_ht40_minus(conf))
85 sc->cur_rate_table =
86 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
87 else if (conf_is_ht40_plus(conf))
88 sc->cur_rate_table =
89 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
90 else
96742256
LR		 91 sc->cur_rate_table =
92 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 93 break;
94 default:
ce111bad 95 BUG_ON(1);
030bb495
LR		 96 break;
97 }
ff37e337
S		 98}
99
100static void ath_update_txpow(struct ath_softc *sc)
101{
102 struct ath_hal *ah = sc->sc_ah;
103 u32 txpow;
104
105 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
106 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
107 /* read back in case value is clamped */
108 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
109 sc->sc_curtxpow = txpow;
110 }
111}
112
113static u8 parse_mpdudensity(u8 mpdudensity)
114{
115 /*
116 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
117 * 0 for no restriction
118 * 1 for 1/4 us
119 * 2 for 1/2 us
120 * 3 for 1 us
121 * 4 for 2 us
122 * 5 for 4 us
123 * 6 for 8 us
124 * 7 for 16 us
125 */
126 switch (mpdudensity) {
127 case 0:
128 return 0;
129 case 1:
130 case 2:
131 case 3:
132 /* Our lower layer calculations limit our precision to
133 1 microsecond */
134 return 1;
135 case 4:
136 return 2;
137 case 5:
138 return 4;
139 case 6:
140 return 8;
141 case 7:
142 return 16;
143 default:
144 return 0;
145 }
146}
147
148static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
149{
150 struct ath_rate_table *rate_table = NULL;
151 struct ieee80211_supported_band *sband;
152 struct ieee80211_rate *rate;
153 int i, maxrates;
154
155 switch (band) {
156 case IEEE80211_BAND_2GHZ:
157 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
158 break;
159 case IEEE80211_BAND_5GHZ:
160 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
161 break;
162 default:
163 break;
164 }
165
166 if (rate_table == NULL)
167 return;
168
169 sband = &sc->sbands[band];
170 rate = sc->rates[band];
171
172 if (rate_table->rate_cnt > ATH_RATE_MAX)
173 maxrates = ATH_RATE_MAX;
174 else
175 maxrates = rate_table->rate_cnt;
176
177 for (i = 0; i < maxrates; i++) {
178 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
179 rate[i].hw_value = rate_table->info[i].ratecode;
180 sband->n_bitrates++;
04bd4638
S		 181 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
182 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 183 }
184}
185
186static int ath_setup_channels(struct ath_softc *sc)
187{
188 struct ath_hal *ah = sc->sc_ah;
189 int nchan, i, a = 0, b = 0;
190 u8 regclassids[ATH_REGCLASSIDS_MAX];
191 u32 nregclass = 0;
192 struct ieee80211_supported_band *band_2ghz;
193 struct ieee80211_supported_band *band_5ghz;
194 struct ieee80211_channel *chan_2ghz;
195 struct ieee80211_channel *chan_5ghz;
196 struct ath9k_channel *c;
197
198 /* Fill in ah->ah_channels */
199 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
200 regclassids, ATH_REGCLASSIDS_MAX,
201 &nregclass, CTRY_DEFAULT, false, 1)) {
202 u32 rd = ah->ah_currentRD;
203 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 204 "Unable to collect channel list; "
ff37e337 205 "regdomain likely %u country code %u\n",
04bd4638 206 rd, CTRY_DEFAULT);
ff37e337
S		 207 return -EINVAL;
208 }
209
210 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
211 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
212 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
213 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
214
215 for (i = 0; i < nchan; i++) {
216 c = &ah->ah_channels[i];
217 if (IS_CHAN_2GHZ(c)) {
218 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
219 chan_2ghz[a].center_freq = c->channel;
220 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 221 c->chan = &chan_2ghz[a];
ff37e337
S		 222
223 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
225 if (c->channelFlags & CHANNEL_PASSIVE)
226 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
227
228 band_2ghz->n_channels = ++a;
229
04bd4638 230 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 231 "channelFlags: 0x%x\n",
04bd4638 232 c->channel, c->channelFlags);
ff37e337
S		 233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 237 c->chan = &chan_5ghz[a];
ff37e337
S		 238
239 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
240 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
243
244 band_5ghz->n_channels = ++b;
245
04bd4638 246 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 247 "channelFlags: 0x%x\n",
04bd4638 248 c->channel, c->channelFlags);
ff37e337
S		 249 }
250 }
251
252 return 0;
253}
254
255/*
256 * Set/change channels. If the channel is really being changed, it's done
257 * by reseting the chip. To accomplish this we must first cleanup any pending
258 * DMA, then restart stuff.
259*/
260static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
261{
262 struct ath_hal *ah = sc->sc_ah;
263 bool fastcc = true, stopped;
030bb495 264 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 265 struct ieee80211_channel *channel = hw->conf.channel;
266 int r;
ff37e337
S		 267
268 if (sc->sc_flags & SC_OP_INVALID)
269 return -EIO;
270
ff37e337
S		 271 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
272 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
273 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
274 (sc->sc_flags & SC_OP_FULL_RESET)) {
ff37e337
S		 275 /*
276 * This is only performed if the channel settings have
277 * actually changed.
278 *
279 * To switch channels clear any pending DMA operations;
280 * wait long enough for the RX fifo to drain, reset the
281 * hardware at the new frequency, and then re-enable
282 * the relevant bits of the h/w.
283 */
04bd4638
S		 284 ath9k_hw_set_interrupts(ah, 0);
285 ath_draintxq(sc, false);
286 stopped = ath_stoprecv(sc);
ff37e337
S		 287
288 /* XXX: do not flush receive queue here. We don't want
289 * to flush data frames already in queue because of
290 * changing channel. */
291
292 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
293 fastcc = false;
294
99405f93 295 DPRINTF(sc, ATH_DBG_CONFIG,
ae8d2858 296 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
99405f93 297 sc->sc_ah->ah_curchan->channel,
ae8d2858 298 channel->center_freq, sc->tx_chan_width);
99405f93 299
ff37e337 300 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 301
302 r = ath9k_hw_reset(ah, hchan, fastcc);
303 if (r) {
ff37e337 304 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 305 "Unable to reset channel (%u Mhz) "
306 "reset status %u\n",
307 channel->center_freq, r);
ff37e337 308 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 309 return r;
ff37e337
S		 310 }
311 spin_unlock_bh(&sc->sc_resetlock);
312
313 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
314 sc->sc_flags &= ~SC_OP_FULL_RESET;
315
316 if (ath_startrecv(sc) != 0) {
317 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 318 "Unable to restart recv logic\n");
ff37e337
S		 319 return -EIO;
320 }
321
ce111bad 322 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 323 ath_update_txpow(sc);
324 ath9k_hw_set_interrupts(ah, sc->sc_imask);
325 }
326 return 0;
327}
328
329/*
330 * This routine performs the periodic noise floor calibration function
331 * that is used to adjust and optimize the chip performance. This
332 * takes environmental changes (location, temperature) into account.
333 * When the task is complete, it reschedules itself depending on the
334 * appropriate interval that was calculated.
335 */
336static void ath_ani_calibrate(unsigned long data)
337{
338 struct ath_softc *sc;
339 struct ath_hal *ah;
340 bool longcal = false;
341 bool shortcal = false;
342 bool aniflag = false;
343 unsigned int timestamp = jiffies_to_msecs(jiffies);
344 u32 cal_interval;
345
346 sc = (struct ath_softc *)data;
347 ah = sc->sc_ah;
348
349 /*
350 * don't calibrate when we're scanning.
351 * we are most likely not on our home channel.
352 */
b77f483f 353 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 354 return;
355
356 /* Long calibration runs independently of short calibration. */
357 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
358 longcal = true;
04bd4638 359 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 360 sc->sc_ani.sc_longcal_timer = timestamp;
361 }
362
363 /* Short calibration applies only while sc_caldone is false */
364 if (!sc->sc_ani.sc_caldone) {
365 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
366 ATH_SHORT_CALINTERVAL) {
367 shortcal = true;
04bd4638 368 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 369 sc->sc_ani.sc_shortcal_timer = timestamp;
370 sc->sc_ani.sc_resetcal_timer = timestamp;
371 }
372 } else {
373 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
374 ATH_RESTART_CALINTERVAL) {
c9e27d94 375 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 376 if (sc->sc_ani.sc_caldone)
377 sc->sc_ani.sc_resetcal_timer = timestamp;
378 }
379 }
380
381 /* Verify whether we must check ANI */
382 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
383 ATH_ANI_POLLINTERVAL) {
384 aniflag = true;
385 sc->sc_ani.sc_checkani_timer = timestamp;
386 }
387
388 /* Skip all processing if there's nothing to do. */
389 if (longcal || shortcal || aniflag) {
390 /* Call ANI routine if necessary */
391 if (aniflag)
392 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
393 ah->ah_curchan);
394
395 /* Perform calibration if necessary */
396 if (longcal || shortcal) {
397 bool iscaldone = false;
398
399 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
400 sc->sc_rx_chainmask, longcal,
401 &iscaldone)) {
402 if (longcal)
403 sc->sc_ani.sc_noise_floor =
404 ath9k_hw_getchan_noise(ah,
405 ah->ah_curchan);
406
407 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 408 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 409 ah->ah_curchan->channel,
410 ah->ah_curchan->channelFlags,
411 sc->sc_ani.sc_noise_floor);
412 } else {
413 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 414 "calibrate chan %u/%x failed\n",
ff37e337
S		 415 ah->ah_curchan->channel,
416 ah->ah_curchan->channelFlags);
417 }
418 sc->sc_ani.sc_caldone = iscaldone;
419 }
420 }
421
422 /*
423 * Set timer interval based on previous results.
424 * The interval must be the shortest necessary to satisfy ANI,
425 * short calibration and long calibration.
426 */
aac9207e
S		 427 cal_interval = ATH_LONG_CALINTERVAL;
428 if (sc->sc_ah->ah_config.enable_ani)
429 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 430 if (!sc->sc_ani.sc_caldone)
431 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
432
433 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
434}
435
436/*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
439 * the chainmask configuration.
440 */
441static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
442{
443 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
444 if (is_ht) {
445 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
446 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
447 } else {
448 sc->sc_tx_chainmask = 1;
449 sc->sc_rx_chainmask = 1;
450 }
451
04bd4638
S		 452 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
453 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 454}
455
456static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
457{
458 struct ath_node *an;
459
460 an = (struct ath_node *)sta->drv_priv;
461
462 if (sc->sc_flags & SC_OP_TXAGGR)
463 ath_tx_node_init(sc, an);
464
465 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
468}
469
470static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
471{
472 struct ath_node *an = (struct ath_node *)sta->drv_priv;
473
474 if (sc->sc_flags & SC_OP_TXAGGR)
475 ath_tx_node_cleanup(sc, an);
476}
477
478static void ath9k_tasklet(unsigned long data)
479{
480 struct ath_softc *sc = (struct ath_softc *)data;
481 u32 status = sc->sc_intrstatus;
482
483 if (status & ATH9K_INT_FATAL) {
484 /* need a chip reset */
485 ath_reset(sc, false);
486 return;
487 } else {
488
489 if (status &
490 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 491 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 492 ath_rx_tasklet(sc, 0);
b77f483f 493 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 494 }
495 /* XXX: optimize this */
496 if (status & ATH9K_INT_TX)
497 ath_tx_tasklet(sc);
498 }
499
500 /* re-enable hardware interrupt */
501 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
502}
503
504static irqreturn_t ath_isr(int irq, void *dev)
505{
506 struct ath_softc *sc = dev;
507 struct ath_hal *ah = sc->sc_ah;
508 enum ath9k_int status;
509 bool sched = false;
510
511 do {
512 if (sc->sc_flags & SC_OP_INVALID) {
513 /*
514 * The hardware is not ready/present, don't
515 * touch anything. Note this can happen early
516 * on if the IRQ is shared.
517 */
518 return IRQ_NONE;
519 }
520 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
521 return IRQ_NONE;
522 }
523
524 /*
525 * Figure out the reason(s) for the interrupt. Note
526 * that the hal returns a pseudo-ISR that may include
527 * bits we haven't explicitly enabled so we mask the
528 * value to insure we only process bits we requested.
529 */
530 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
531
532 status &= sc->sc_imask; /* discard unasked-for bits */
533
534 /*
535 * If there are no status bits set, then this interrupt was not
536 * for me (should have been caught above).
537 */
538 if (!status)
539 return IRQ_NONE;
540
541 sc->sc_intrstatus = status;
542
543 if (status & ATH9K_INT_FATAL) {
544 /* need a chip reset */
545 sched = true;
546 } else if (status & ATH9K_INT_RXORN) {
547 /* need a chip reset */
548 sched = true;
549 } else {
550 if (status & ATH9K_INT_SWBA) {
551 /* schedule a tasklet for beacon handling */
552 tasklet_schedule(&sc->bcon_tasklet);
553 }
554 if (status & ATH9K_INT_RXEOL) {
555 /*
556 * NB: the hardware should re-read the link when
557 * RXE bit is written, but it doesn't work
558 * at least on older hardware revs.
559 */
560 sched = true;
561 }
562
563 if (status & ATH9K_INT_TXURN)
564 /* bump tx trigger level */
565 ath9k_hw_updatetxtriglevel(ah, true);
566 /* XXX: optimize this */
567 if (status & ATH9K_INT_RX)
568 sched = true;
569 if (status & ATH9K_INT_TX)
570 sched = true;
571 if (status & ATH9K_INT_BMISS)
572 sched = true;
573 /* carrier sense timeout */
574 if (status & ATH9K_INT_CST)
575 sched = true;
576 if (status & ATH9K_INT_MIB) {
577 /*
578 * Disable interrupts until we service the MIB
579 * interrupt; otherwise it will continue to
580 * fire.
581 */
582 ath9k_hw_set_interrupts(ah, 0);
583 /*
584 * Let the hal handle the event. We assume
585 * it will clear whatever condition caused
586 * the interrupt.
587 */
588 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
589 ath9k_hw_set_interrupts(ah, sc->sc_imask);
590 }
591 if (status & ATH9K_INT_TIM_TIMER) {
592 if (!(ah->ah_caps.hw_caps &
593 ATH9K_HW_CAP_AUTOSLEEP)) {
594 /* Clear RxAbort bit so that we can
595 * receive frames */
596 ath9k_hw_setrxabort(ah, 0);
597 sched = true;
598 }
599 }
600 }
601 } while (0);
602
817e11de
S		 603 ath_debug_stat_interrupt(sc, status);
604
ff37e337
S		 605 if (sched) {
606 /* turn off every interrupt except SWBA */
607 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
608 tasklet_schedule(&sc->intr_tq);
609 }
610
611 return IRQ_HANDLED;
612}
613
f078f209
LR		 614static int ath_get_channel(struct ath_softc *sc,
615 struct ieee80211_channel *chan)
616{
617 int i;
618
619 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
620 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
621 return i;
622 }
623
624 return -1;
625}
626
627static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 628 struct ieee80211_channel *chan,
094d05dc 629 enum nl80211_channel_type channel_type)
f078f209
LR		 630{
631 u32 chanmode = 0;
f078f209
LR		 632
633 switch (chan->band) {
634 case IEEE80211_BAND_2GHZ:
094d05dc
S		 635 switch(channel_type) {
636 case NL80211_CHAN_NO_HT:
637 case NL80211_CHAN_HT20:
f078f209 638 chanmode = CHANNEL_G_HT20;
094d05dc
S		 639 break;
640 case NL80211_CHAN_HT40PLUS:
f078f209 641 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 642 break;
643 case NL80211_CHAN_HT40MINUS:
f078f209 644 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 645 break;
646 }
f078f209
LR		 647 break;
648 case IEEE80211_BAND_5GHZ:
094d05dc
S		 649 switch(channel_type) {
650 case NL80211_CHAN_NO_HT:
651 case NL80211_CHAN_HT20:
f078f209 652 chanmode = CHANNEL_A_HT20;
094d05dc
S		 653 break;
654 case NL80211_CHAN_HT40PLUS:
f078f209 655 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 656 break;
657 case NL80211_CHAN_HT40MINUS:
f078f209 658 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 659 break;
660 }
f078f209
LR		 661 break;
662 default:
663 break;
664 }
665
666 return chanmode;
667}
668
ff37e337
S		 669static int ath_keyset(struct ath_softc *sc, u16 keyix,
670 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
671{
672 bool status;
673
674 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
675 keyix, hk, mac, false);
676
677 return status != false;
678}
f078f209 679
6ace2891 680static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 681 struct ath9k_keyval *hk,
682 const u8 *addr)
683{
6ace2891
JM		 684 const u8 *key_rxmic;
685 const u8 *key_txmic;
f078f209 686
6ace2891
JM		 687 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
688 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 689
690 if (addr == NULL) {
691 /* Group key installation */
6ace2891
JM		 692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 694 }
695 if (!sc->sc_splitmic) {
696 /*
697 * data key goes at first index,
698 * the hal handles the MIC keys at index+64.
699 */
700 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
701 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 702 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 703 }
704 /*
705 * TX key goes at first index, RX key at +32.
706 * The hal handles the MIC keys at index+64.
707 */
708 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 709 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 710 /* Txmic entry failed. No need to proceed further */
711 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 712 "Setting TX MIC Key Failed\n");
f078f209
LR		 713 return 0;
714 }
715
716 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
717 /* XXX delete tx key on failure? */
6ace2891
JM		 718 return ath_keyset(sc, keyix + 32, hk, addr);
719}
720
721static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
722{
723 int i;
724
725 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
726 if (test_bit(i, sc->sc_keymap) ||
727 test_bit(i + 64, sc->sc_keymap))
728 continue; /* At least one part of TKIP key allocated */
729 if (sc->sc_splitmic &&
730 (test_bit(i + 32, sc->sc_keymap) ||
731 test_bit(i + 64 + 32, sc->sc_keymap)))
732 continue; /* At least one part of TKIP key allocated */
733
734 /* Found a free slot for a TKIP key */
735 return i;
736 }
737 return -1;
738}
739
740static int ath_reserve_key_cache_slot(struct ath_softc *sc)
741{
742 int i;
743
744 /* First, try to find slots that would not be available for TKIP. */
745 if (sc->sc_splitmic) {
746 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
747 if (!test_bit(i, sc->sc_keymap) &&
748 (test_bit(i + 32, sc->sc_keymap) ||
749 test_bit(i + 64, sc->sc_keymap) ||
750 test_bit(i + 64 + 32, sc->sc_keymap)))
751 return i;
752 if (!test_bit(i + 32, sc->sc_keymap) &&
753 (test_bit(i, sc->sc_keymap) ||
754 test_bit(i + 64, sc->sc_keymap) ||
755 test_bit(i + 64 + 32, sc->sc_keymap)))
756 return i + 32;
757 if (!test_bit(i + 64, sc->sc_keymap) &&
758 (test_bit(i , sc->sc_keymap) ||
759 test_bit(i + 32, sc->sc_keymap) ||
760 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 761 return i + 64;
6ace2891
JM		 762 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
763 (test_bit(i, sc->sc_keymap) ||
764 test_bit(i + 32, sc->sc_keymap) ||
765 test_bit(i + 64, sc->sc_keymap)))
ea612132 766 return i + 64 + 32;
6ace2891
JM		 767 }
768 } else {
769 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
770 if (!test_bit(i, sc->sc_keymap) &&
771 test_bit(i + 64, sc->sc_keymap))
772 return i;
773 if (test_bit(i, sc->sc_keymap) &&
774 !test_bit(i + 64, sc->sc_keymap))
775 return i + 64;
776 }
777 }
778
779 /* No partially used TKIP slots, pick any available slot */
780 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 781 /* Do not allow slots that could be needed for TKIP group keys
782 * to be used. This limitation could be removed if we know that
783 * TKIP will not be used. */
784 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
785 continue;
786 if (sc->sc_splitmic) {
787 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
788 continue;
789 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
790 continue;
791 }
792
6ace2891
JM		 793 if (!test_bit(i, sc->sc_keymap))
794 return i; /* Found a free slot for a key */
795 }
796
797 /* No free slot found */
798 return -1;
f078f209
LR		 799}
800
801static int ath_key_config(struct ath_softc *sc,
802 const u8 *addr,
803 struct ieee80211_key_conf *key)
804{
f078f209
LR		 805 struct ath9k_keyval hk;
806 const u8 *mac = NULL;
807 int ret = 0;
6ace2891 808 int idx;
f078f209
LR		 809
810 memset(&hk, 0, sizeof(hk));
811
812 switch (key->alg) {
813 case ALG_WEP:
814 hk.kv_type = ATH9K_CIPHER_WEP;
815 break;
816 case ALG_TKIP:
817 hk.kv_type = ATH9K_CIPHER_TKIP;
818 break;
819 case ALG_CCMP:
820 hk.kv_type = ATH9K_CIPHER_AES_CCM;
821 break;
822 default:
823 return -EINVAL;
824 }
825
6ace2891 826 hk.kv_len = key->keylen;
f078f209
LR		 827 memcpy(hk.kv_val, key->key, key->keylen);
828
6ace2891
JM		 829 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
830 /* For now, use the default keys for broadcast keys. This may
831 * need to change with virtual interfaces. */
832 idx = key->keyidx;
833 } else if (key->keyidx) {
834 struct ieee80211_vif *vif;
f078f209 835
6ace2891
JM		 836 mac = addr;
837 vif = sc->sc_vaps[0];
838 if (vif->type != NL80211_IFTYPE_AP) {
839 /* Only keyidx 0 should be used with unicast key, but
840 * allow this for client mode for now. */
841 idx = key->keyidx;
842 } else
843 return -EIO;
f078f209
LR		 844 } else {
845 mac = addr;
6ace2891
JM		 846 if (key->alg == ALG_TKIP)
847 idx = ath_reserve_key_cache_slot_tkip(sc);
848 else
849 idx = ath_reserve_key_cache_slot(sc);
850 if (idx < 0)
851 return -EIO; /* no free key cache entries */
f078f209
LR		 852 }
853
854 if (key->alg == ALG_TKIP)
6ace2891 855 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 856 else
6ace2891 857 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 858
859 if (!ret)
860 return -EIO;
861
6ace2891
JM		 862 set_bit(idx, sc->sc_keymap);
863 if (key->alg == ALG_TKIP) {
864 set_bit(idx + 64, sc->sc_keymap);
865 if (sc->sc_splitmic) {
866 set_bit(idx + 32, sc->sc_keymap);
867 set_bit(idx + 64 + 32, sc->sc_keymap);
868 }
869 }
870
871 return idx;
f078f209
LR		 872}
873
874static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
875{
6ace2891
JM		 876 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
877 if (key->hw_key_idx < IEEE80211_WEP_NKID)
878 return;
879
880 clear_bit(key->hw_key_idx, sc->sc_keymap);
881 if (key->alg != ALG_TKIP)
882 return;
f078f209 883
6ace2891
JM		 884 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
885 if (sc->sc_splitmic) {
886 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
887 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
888 }
f078f209
LR		 889}
890
d9fe60de 891static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 892{
60653678
S		 893#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
894#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 895
d9fe60de
JB		 896 ht_info->ht_supported = true;
897 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
898 IEEE80211_HT_CAP_SM_PS |
899 IEEE80211_HT_CAP_SGI_40 |
900 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 901
60653678
S		 902 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
903 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 904 /* set up supported mcs set */
905 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
906 ht_info->mcs.rx_mask[0] = 0xff;
907 ht_info->mcs.rx_mask[1] = 0xff;
908 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 909}
910
8feceb67 911static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 912 struct ieee80211_vif *vif,
8feceb67 913 struct ieee80211_bss_conf *bss_conf)
f078f209 914{
5640b08e 915 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 916
8feceb67 917 if (bss_conf->assoc) {
094d05dc
S		 918 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
919 bss_conf->aid, sc->sc_curbssid);
f078f209 920
8feceb67 921 /* New association, store aid */
d97809db 922 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 923 sc->sc_curaid = bss_conf->aid;
924 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
925 sc->sc_curaid);
926 }
f078f209 927
8feceb67
VT		 928 /* Configure the beacon */
929 ath_beacon_config(sc, 0);
930 sc->sc_flags |= SC_OP_BEACONS;
f078f209 931
8feceb67
VT		 932 /* Reset rssi stats */
933 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
934 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
935 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
936 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 937
6f255425
LR		 938 /* Start ANI */
939 mod_timer(&sc->sc_ani.timer,
940 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
941
8feceb67 942 } else {
04bd4638 943 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 944 sc->sc_curaid = 0;
f078f209 945 }
8feceb67 946}
f078f209 947
8feceb67
VT		 948/********************************/
949/* LED functions */
950/********************************/
f078f209 951
8feceb67
VT		 952static void ath_led_brightness(struct led_classdev *led_cdev,
953 enum led_brightness brightness)
954{
955 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
956 struct ath_softc *sc = led->sc;
f078f209 957
8feceb67
VT		 958 switch (brightness) {
959 case LED_OFF:
960 if (led->led_type == ATH_LED_ASSOC ||
961 led->led_type == ATH_LED_RADIO)
962 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
963 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
964 (led->led_type == ATH_LED_RADIO) ? 1 :
965 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
966 break;
967 case LED_FULL:
968 if (led->led_type == ATH_LED_ASSOC)
969 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
970 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
971 break;
972 default:
973 break;
f078f209 974 }
8feceb67 975}
f078f209 976
8feceb67
VT		 977static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
978 char *trigger)
979{
980 int ret;
f078f209 981
8feceb67
VT		 982 led->sc = sc;
983 led->led_cdev.name = led->name;
984 led->led_cdev.default_trigger = trigger;
985 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 986
8feceb67
VT		 987 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
988 if (ret)
989 DPRINTF(sc, ATH_DBG_FATAL,
990 "Failed to register led:%s", led->name);
991 else
992 led->registered = 1;
993 return ret;
994}
f078f209 995
8feceb67
VT		 996static void ath_unregister_led(struct ath_led *led)
997{
998 if (led->registered) {
999 led_classdev_unregister(&led->led_cdev);
1000 led->registered = 0;
f078f209 1001 }
f078f209
LR		 1002}
1003
8feceb67 1004static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1005{
8feceb67
VT		 1006 ath_unregister_led(&sc->assoc_led);
1007 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1008 ath_unregister_led(&sc->tx_led);
1009 ath_unregister_led(&sc->rx_led);
1010 ath_unregister_led(&sc->radio_led);
1011 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1012}
f078f209 1013
8feceb67
VT		 1014static void ath_init_leds(struct ath_softc *sc)
1015{
1016 char *trigger;
1017 int ret;
f078f209 1018
8feceb67
VT		 1019 /* Configure gpio 1 for output */
1020 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1021 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1022 /* LED off, active low */
1023 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1024
8feceb67
VT		 1025 trigger = ieee80211_get_radio_led_name(sc->hw);
1026 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1027 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1028 ret = ath_register_led(sc, &sc->radio_led, trigger);
1029 sc->radio_led.led_type = ATH_LED_RADIO;
1030 if (ret)
1031 goto fail;
7dcfdcd9 1032
8feceb67
VT		 1033 trigger = ieee80211_get_assoc_led_name(sc->hw);
1034 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1035 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1036 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1037 sc->assoc_led.led_type = ATH_LED_ASSOC;
1038 if (ret)
1039 goto fail;
f078f209 1040
8feceb67
VT		 1041 trigger = ieee80211_get_tx_led_name(sc->hw);
1042 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1043 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1044 ret = ath_register_led(sc, &sc->tx_led, trigger);
1045 sc->tx_led.led_type = ATH_LED_TX;
1046 if (ret)
1047 goto fail;
f078f209 1048
8feceb67
VT		 1049 trigger = ieee80211_get_rx_led_name(sc->hw);
1050 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1051 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1052 ret = ath_register_led(sc, &sc->rx_led, trigger);
1053 sc->rx_led.led_type = ATH_LED_RX;
1054 if (ret)
1055 goto fail;
f078f209 1056
8feceb67
VT		 1057 return;
1058
1059fail:
1060 ath_deinit_leds(sc);
f078f209
LR		 1061}
1062
e97275cb 1063#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1064
500c064d
VT		 1065/*******************/
1066/* Rfkill */
1067/*******************/
1068
1069static void ath_radio_enable(struct ath_softc *sc)
1070{
1071 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1072 struct ieee80211_channel *channel = sc->hw->conf.channel;
1073 int r;
500c064d
VT		 1074
1075 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1076
1077 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1078
1079 if (r) {
500c064d 1080 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1081 "Unable to reset channel %u (%uMhz) ",
1082 "reset status %u\n",
1083 channel->center_freq, r);
500c064d
VT		 1084 }
1085 spin_unlock_bh(&sc->sc_resetlock);
1086
1087 ath_update_txpow(sc);
1088 if (ath_startrecv(sc) != 0) {
1089 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1090 "Unable to restart recv logic\n");
500c064d
VT		 1091 return;
1092 }
1093
1094 if (sc->sc_flags & SC_OP_BEACONS)
1095 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1096
1097 /* Re-Enable interrupts */
1098 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1099
1100 /* Enable LED */
1101 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1102 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1103 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1104
1105 ieee80211_wake_queues(sc->hw);
1106}
1107
1108static void ath_radio_disable(struct ath_softc *sc)
1109{
1110 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1111 struct ieee80211_channel *channel = sc->hw->conf.channel;
1112 int r;
500c064d
VT		 1113
1114 ieee80211_stop_queues(sc->hw);
1115
1116 /* Disable LED */
1117 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1118 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1119
1120 /* Disable interrupts */
1121 ath9k_hw_set_interrupts(ah, 0);
1122
1123 ath_draintxq(sc, false); /* clear pending tx frames */
1124 ath_stoprecv(sc); /* turn off frame recv */
1125 ath_flushrecv(sc); /* flush recv queue */
1126
1127 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1128 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1129 if (r) {
500c064d 1130 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1131 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1132 "reset status %u\n",
1133 channel->center_freq, r);
500c064d
VT		 1134 }
1135 spin_unlock_bh(&sc->sc_resetlock);
1136
1137 ath9k_hw_phy_disable(ah);
1138 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1139}
1140
1141static bool ath_is_rfkill_set(struct ath_softc *sc)
1142{
1143 struct ath_hal *ah = sc->sc_ah;
1144
1145 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1146 ah->ah_rfkill_polarity;
1147}
1148
1149/* h/w rfkill poll function */
1150static void ath_rfkill_poll(struct work_struct *work)
1151{
1152 struct ath_softc *sc = container_of(work, struct ath_softc,
1153 rf_kill.rfkill_poll.work);
1154 bool radio_on;
1155
1156 if (sc->sc_flags & SC_OP_INVALID)
1157 return;
1158
1159 radio_on = !ath_is_rfkill_set(sc);
1160
1161 /*
1162 * enable/disable radio only when there is a
1163 * state change in RF switch
1164 */
1165 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1166 enum rfkill_state state;
1167
1168 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1169 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1170 : RFKILL_STATE_HARD_BLOCKED;
1171 } else if (radio_on) {
1172 ath_radio_enable(sc);
1173 state = RFKILL_STATE_UNBLOCKED;
1174 } else {
1175 ath_radio_disable(sc);
1176 state = RFKILL_STATE_HARD_BLOCKED;
1177 }
1178
1179 if (state == RFKILL_STATE_HARD_BLOCKED)
1180 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1181 else
1182 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1183
1184 rfkill_force_state(sc->rf_kill.rfkill, state);
1185 }
1186
1187 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1188 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1189}
1190
1191/* s/w rfkill handler */
1192static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1193{
1194 struct ath_softc *sc = data;
1195
1196 switch (state) {
1197 case RFKILL_STATE_SOFT_BLOCKED:
1198 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1199 SC_OP_RFKILL_SW_BLOCKED)))
1200 ath_radio_disable(sc);
1201 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1202 return 0;
1203 case RFKILL_STATE_UNBLOCKED:
1204 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1205 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1206 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1207 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1208 "radio as it is disabled by h/w\n");
500c064d
VT		 1209 return -EPERM;
1210 }
1211 ath_radio_enable(sc);
1212 }
1213 return 0;
1214 default:
1215 return -EINVAL;
1216 }
1217}
1218
1219/* Init s/w rfkill */
1220static int ath_init_sw_rfkill(struct ath_softc *sc)
1221{
1222 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1223 RFKILL_TYPE_WLAN);
1224 if (!sc->rf_kill.rfkill) {
1225 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1226 return -ENOMEM;
1227 }
1228
1229 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1230 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1231 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1232 sc->rf_kill.rfkill->data = sc;
1233 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1234 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1235 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1236
1237 return 0;
1238}
1239
1240/* Deinitialize rfkill */
1241static void ath_deinit_rfkill(struct ath_softc *sc)
1242{
1243 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1244 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1245
1246 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1247 rfkill_unregister(sc->rf_kill.rfkill);
1248 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1249 sc->rf_kill.rfkill = NULL;
1250 }
1251}
9c84b797
S		 1252
1253static int ath_start_rfkill_poll(struct ath_softc *sc)
1254{
1255 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1256 queue_delayed_work(sc->hw->workqueue,
1257 &sc->rf_kill.rfkill_poll, 0);
1258
1259 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1260 if (rfkill_register(sc->rf_kill.rfkill)) {
1261 DPRINTF(sc, ATH_DBG_FATAL,
1262 "Unable to register rfkill\n");
1263 rfkill_free(sc->rf_kill.rfkill);
1264
1265 /* Deinitialize the device */
306efdd1 1266 ath_detach(sc);
9c84b797
S		 1267 if (sc->pdev->irq)
1268 free_irq(sc->pdev->irq, sc);
9c84b797
S		 1269 pci_iounmap(sc->pdev, sc->mem);
1270 pci_release_region(sc->pdev, 0);
1271 pci_disable_device(sc->pdev);
9757d556 1272 ieee80211_free_hw(sc->hw);
9c84b797
S		 1273 return -EIO;
1274 } else {
1275 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1276 }
1277 }
1278
1279 return 0;
1280}
500c064d
VT		 1281#endif /* CONFIG_RFKILL */
1282
9c84b797 1283static void ath_detach(struct ath_softc *sc)
f078f209 1284{
8feceb67 1285 struct ieee80211_hw *hw = sc->hw;
9c84b797 1286 int i = 0;
f078f209 1287
04bd4638 1288 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1289
e97275cb 1290#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1291 ath_deinit_rfkill(sc);
1292#endif
3fcdfb4b
VT		 1293 ath_deinit_leds(sc);
1294
1295 ieee80211_unregister_hw(hw);
8feceb67
VT		 1296 ath_rx_cleanup(sc);
1297 ath_tx_cleanup(sc);
f078f209 1298
9c84b797
S		 1299 tasklet_kill(&sc->intr_tq);
1300 tasklet_kill(&sc->bcon_tasklet);
f078f209 1301
9c84b797
S		 1302 if (!(sc->sc_flags & SC_OP_INVALID))
1303 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1304
9c84b797
S		 1305 /* cleanup tx queues */
1306 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1307 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1308 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1309
1310 ath9k_hw_detach(sc->sc_ah);
826d2680 1311 ath9k_exit_debug(sc);
f078f209
LR		 1312}
1313
ff37e337
S		 1314static int ath_init(u16 devid, struct ath_softc *sc)
1315{
1316 struct ath_hal *ah = NULL;
1317 int status;
1318 int error = 0, i;
1319 int csz = 0;
1320
1321 /* XXX: hardware will not be ready until ath_open() being called */
1322 sc->sc_flags |= SC_OP_INVALID;
88b126af 1323
826d2680
S		 1324 if (ath9k_init_debug(sc) < 0)
1325 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1326
1327 spin_lock_init(&sc->sc_resetlock);
aa33de09 1328 mutex_init(&sc->mutex);
ff37e337
S		 1329 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1330 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1331 (unsigned long)sc);
1332
1333 /*
1334 * Cache line size is used to size and align various
1335 * structures used to communicate with the hardware.
1336 */
1337 bus_read_cachesize(sc, &csz);
1338 /* XXX assert csz is non-zero */
1339 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1340
1341 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1342 if (ah == NULL) {
1343 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1344 "Unable to attach hardware; HAL status %u\n", status);
ff37e337
S		 1345 error = -ENXIO;
1346 goto bad;
1347 }
1348 sc->sc_ah = ah;
1349
1350 /* Get the hardware key cache size. */
1351 sc->sc_keymax = ah->ah_caps.keycache_size;
1352 if (sc->sc_keymax > ATH_KEYMAX) {
1353 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1354 "Warning, using only %u entries in %u key cache\n",
1355 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1356 sc->sc_keymax = ATH_KEYMAX;
1357 }
1358
1359 /*
1360 * Reset the key cache since some parts do not
1361 * reset the contents on initial power up.
1362 */
1363 for (i = 0; i < sc->sc_keymax; i++)
1364 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1365
1366 /* Collect the channel list using the default country code */
1367
1368 error = ath_setup_channels(sc);
1369 if (error)
1370 goto bad;
1371
1372 /* default to MONITOR mode */
d97809db
CM		 1373 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1374
ff37e337
S		 1375
1376 /* Setup rate tables */
1377
1378 ath_rate_attach(sc);
1379 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1380 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1381
1382 /*
1383 * Allocate hardware transmit queues: one queue for
1384 * beacon frames and one data queue for each QoS
1385 * priority. Note that the hal handles reseting
1386 * these queues at the needed time.
1387 */
b77f483f
S		 1388 sc->beacon.beaconq = ath_beaconq_setup(ah);
1389 if (sc->beacon.beaconq == -1) {
ff37e337 1390 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1391 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1392 error = -EIO;
1393 goto bad2;
1394 }
b77f483f
S		 1395 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1396 if (sc->beacon.cabq == NULL) {
ff37e337 1397 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1398 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1399 error = -EIO;
1400 goto bad2;
1401 }
1402
1403 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1404 ath_cabq_update(sc);
1405
b77f483f
S		 1406 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1407 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1408
1409 /* Setup data queues */
1410 /* NB: ensure BK queue is the lowest priority h/w queue */
1411 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1412 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1413 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1414 error = -EIO;
1415 goto bad2;
1416 }
1417
1418 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1419 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1420 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1421 error = -EIO;
1422 goto bad2;
1423 }
1424 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1425 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1426 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1427 error = -EIO;
1428 goto bad2;
1429 }
1430 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1431 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1432 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1433 error = -EIO;
1434 goto bad2;
1435 }
1436
1437 /* Initializes the noise floor to a reasonable default value.
1438 * Later on this will be updated during ANI processing. */
1439
1440 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1441 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1442
1443 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1444 ATH9K_CIPHER_TKIP, NULL)) {
1445 /*
1446 * Whether we should enable h/w TKIP MIC.
1447 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1448 * report WMM capable, so it's always safe to turn on
1449 * TKIP MIC in this case.
1450 */
1451 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1452 0, 1, NULL);
1453 }
1454
1455 /*
1456 * Check whether the separate key cache entries
1457 * are required to handle both tx+rx MIC keys.
1458 * With split mic keys the number of stations is limited
1459 * to 27 otherwise 59.
1460 */
1461 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1462 ATH9K_CIPHER_TKIP, NULL)
1463 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1464 ATH9K_CIPHER_MIC, NULL)
1465 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1466 0, NULL))
1467 sc->sc_splitmic = 1;
1468
1469 /* turn on mcast key search if possible */
1470 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1471 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1472 1, NULL);
1473
1474 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1475 sc->sc_config.txpowlimit_override = 0;
1476
1477 /* 11n Capabilities */
1478 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1479 sc->sc_flags |= SC_OP_TXAGGR;
1480 sc->sc_flags |= SC_OP_RXAGGR;
1481 }
1482
1483 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1484 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1485
1486 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1487 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1488
1489 ath9k_hw_getmac(ah, sc->sc_myaddr);
1490 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1491 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1492 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1493 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1494 }
1495
b77f483f 1496 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1497
1498 /* initialize beacon slots */
b77f483f
S		 1499 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1500 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1501
1502 /* save MISC configurations */
1503 sc->sc_config.swBeaconProcess = 1;
1504
ff37e337
S		 1505 /* setup channels and rates */
1506
1507 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1508 sc->channels[IEEE80211_BAND_2GHZ];
1509 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1510 sc->rates[IEEE80211_BAND_2GHZ];
1511 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1512
1513 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1514 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1515 sc->channels[IEEE80211_BAND_5GHZ];
1516 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1517 sc->rates[IEEE80211_BAND_5GHZ];
1518 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1519 }
1520
1521 return 0;
1522bad2:
1523 /* cleanup tx queues */
1524 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1525 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1526 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1527bad:
1528 if (ah)
1529 ath9k_hw_detach(ah);
1530
1531 return error;
1532}
1533
9c84b797 1534static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1535{
8feceb67
VT		 1536 struct ieee80211_hw *hw = sc->hw;
1537 int error = 0;
f078f209 1538
04bd4638 1539 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1540
8feceb67
VT		 1541 error = ath_init(devid, sc);
1542 if (error != 0)
1543 return error;
f078f209 1544
8feceb67 1545 /* get mac address from hardware and set in mac80211 */
f078f209 1546
8feceb67 1547 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1548
9c84b797
S		 1549 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1550 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1551 IEEE80211_HW_SIGNAL_DBM |
1552 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1553
9c84b797
S		 1554 hw->wiphy->interface_modes =
1555 BIT(NL80211_IFTYPE_AP) |
1556 BIT(NL80211_IFTYPE_STATION) |
1557 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1558
8feceb67 1559 hw->queues = 4;
e63835b0
S		 1560 hw->max_rates = 4;
1561 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1562 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1563 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1564
8feceb67 1565 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1566
9c84b797
S		 1567 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1568 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1569 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1570 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1571 }
1572
1573 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1574 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1575 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1576 &sc->sbands[IEEE80211_BAND_5GHZ];
1577
db93e7b5
SB		 1578 /* initialize tx/rx engine */
1579 error = ath_tx_init(sc, ATH_TXBUF);
1580 if (error != 0)
1581 goto detach;
8feceb67 1582
db93e7b5
SB		 1583 error = ath_rx_init(sc, ATH_RXBUF);
1584 if (error != 0)
1585 goto detach;
8feceb67 1586
e97275cb 1587#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1588 /* Initialze h/w Rfkill */
1589 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1590 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1591
1592 /* Initialize s/w rfkill */
1593 if (ath_init_sw_rfkill(sc))
1594 goto detach;
1595#endif
1596
db93e7b5 1597 error = ieee80211_register_hw(hw);
8feceb67 1598
db93e7b5
SB		 1599 /* Initialize LED control */
1600 ath_init_leds(sc);
8feceb67
VT		 1601
1602 return 0;
1603detach:
1604 ath_detach(sc);
8feceb67 1605 return error;
f078f209
LR		 1606}
1607
ff37e337
S		 1608int ath_reset(struct ath_softc *sc, bool retry_tx)
1609{
1610 struct ath_hal *ah = sc->sc_ah;
030bb495 1611 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1612 int r;
ff37e337
S		 1613
1614 ath9k_hw_set_interrupts(ah, 0);
1615 ath_draintxq(sc, retry_tx);
1616 ath_stoprecv(sc);
1617 ath_flushrecv(sc);
1618
1619 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1620 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1621 if (r)
ff37e337 1622 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1623 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1624 spin_unlock_bh(&sc->sc_resetlock);
1625
1626 if (ath_startrecv(sc) != 0)
04bd4638 1627 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1628
1629 /*
1630 * We may be doing a reset in response to a request
1631 * that changes the channel so update any state that
1632 * might change as a result.
1633 */
ce111bad 1634 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1635
1636 ath_update_txpow(sc);
1637
1638 if (sc->sc_flags & SC_OP_BEACONS)
1639 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1640
1641 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1642
1643 if (retry_tx) {
1644 int i;
1645 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1646 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1647 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1648 ath_txq_schedule(sc, &sc->tx.txq[i]);
1649 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1650 }
1651 }
1652 }
1653
ae8d2858 1654 return r;
ff37e337
S		 1655}
1656
1657/*
1658 * This function will allocate both the DMA descriptor structure, and the
1659 * buffers it contains. These are used to contain the descriptors used
1660 * by the system.
1661*/
1662int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1663 struct list_head *head, const char *name,
1664 int nbuf, int ndesc)
1665{
1666#define DS2PHYS(_dd, _ds) \
1667 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1668#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1669#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1670
1671 struct ath_desc *ds;
1672 struct ath_buf *bf;
1673 int i, bsize, error;
1674
04bd4638
S		 1675 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1676 name, nbuf, ndesc);
ff37e337
S		 1677
1678 /* ath_desc must be a multiple of DWORDs */
1679 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1680 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1681 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1682 error = -ENOMEM;
1683 goto fail;
1684 }
1685
1686 dd->dd_name = name;
1687 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1688
1689 /*
1690 * Need additional DMA memory because we can't use
1691 * descriptors that cross the 4K page boundary. Assume
1692 * one skipped descriptor per 4K page.
1693 */
1694 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1695 u32 ndesc_skipped =
1696 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1697 u32 dma_len;
1698
1699 while (ndesc_skipped) {
1700 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1701 dd->dd_desc_len += dma_len;
1702
1703 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1704 };
1705 }
1706
1707 /* allocate descriptors */
1708 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1709 dd->dd_desc_len,
1710 &dd->dd_desc_paddr);
1711 if (dd->dd_desc == NULL) {
1712 error = -ENOMEM;
1713 goto fail;
1714 }
1715 ds = dd->dd_desc;
04bd4638
S		 1716 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1717 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1718 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1719
1720 /* allocate buffers */
1721 bsize = sizeof(struct ath_buf) * nbuf;
1722 bf = kmalloc(bsize, GFP_KERNEL);
1723 if (bf == NULL) {
1724 error = -ENOMEM;
1725 goto fail2;
1726 }
1727 memset(bf, 0, bsize);
1728 dd->dd_bufptr = bf;
1729
1730 INIT_LIST_HEAD(head);
1731 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1732 bf->bf_desc = ds;
1733 bf->bf_daddr = DS2PHYS(dd, ds);
1734
1735 if (!(sc->sc_ah->ah_caps.hw_caps &
1736 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1737 /*
1738 * Skip descriptor addresses which can cause 4KB
1739 * boundary crossing (addr + length) with a 32 dword
1740 * descriptor fetch.
1741 */
1742 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1743 ASSERT((caddr_t) bf->bf_desc <
1744 ((caddr_t) dd->dd_desc +
1745 dd->dd_desc_len));
1746
1747 ds += ndesc;
1748 bf->bf_desc = ds;
1749 bf->bf_daddr = DS2PHYS(dd, ds);
1750 }
1751 }
1752 list_add_tail(&bf->list, head);
1753 }
1754 return 0;
1755fail2:
1756 pci_free_consistent(sc->pdev,
1757 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1758fail:
1759 memset(dd, 0, sizeof(*dd));
1760 return error;
1761#undef ATH_DESC_4KB_BOUND_CHECK
1762#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1763#undef DS2PHYS
1764}
1765
1766void ath_descdma_cleanup(struct ath_softc *sc,
1767 struct ath_descdma *dd,
1768 struct list_head *head)
1769{
1770 pci_free_consistent(sc->pdev,
1771 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1772
1773 INIT_LIST_HEAD(head);
1774 kfree(dd->dd_bufptr);
1775 memset(dd, 0, sizeof(*dd));
1776}
1777
1778int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1779{
1780 int qnum;
1781
1782 switch (queue) {
1783 case 0:
b77f483f 1784 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1785 break;
1786 case 1:
b77f483f 1787 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1788 break;
1789 case 2:
b77f483f 1790 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1791 break;
1792 case 3:
b77f483f 1793 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1794 break;
1795 default:
b77f483f 1796 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1797 break;
1798 }
1799
1800 return qnum;
1801}
1802
1803int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1804{
1805 int qnum;
1806
1807 switch (queue) {
1808 case ATH9K_WME_AC_VO:
1809 qnum = 0;
1810 break;
1811 case ATH9K_WME_AC_VI:
1812 qnum = 1;
1813 break;
1814 case ATH9K_WME_AC_BE:
1815 qnum = 2;
1816 break;
1817 case ATH9K_WME_AC_BK:
1818 qnum = 3;
1819 break;
1820 default:
1821 qnum = -1;
1822 break;
1823 }
1824
1825 return qnum;
1826}
1827
1828/**********************/
1829/* mac80211 callbacks */
1830/**********************/
1831
8feceb67 1832static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1833{
1834 struct ath_softc *sc = hw->priv;
8feceb67 1835 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1836 struct ath9k_channel *init_channel;
ae8d2858 1837 int r, pos;
f078f209 1838
04bd4638
S		 1839 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1840 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1841
8feceb67 1842 /* setup initial channel */
f078f209 1843
8feceb67
VT		 1844 pos = ath_get_channel(sc, curchan);
1845 if (pos == -1) {
04bd4638 1846 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1847 return -EINVAL;
f078f209
LR		 1848 }
1849
99405f93 1850 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1851 sc->sc_ah->ah_channels[pos].chanmode =
1852 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1853 init_channel = &sc->sc_ah->ah_channels[pos];
1854
1855 /* Reset SERDES registers */
1856 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1857
1858 /*
1859 * The basic interface to setting the hardware in a good
1860 * state is ``reset''. On return the hardware is known to
1861 * be powered up and with interrupts disabled. This must
1862 * be followed by initialization of the appropriate bits
1863 * and then setup of the interrupt mask.
1864 */
1865 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1866 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1867 if (r) {
ff37e337 1868 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1869 "Unable to reset hardware; reset status %u "
1870 "(freq %u MHz)\n", r,
1871 curchan->center_freq);
ff37e337 1872 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1873 return r;
ff37e337
S		 1874 }
1875 spin_unlock_bh(&sc->sc_resetlock);
1876
1877 /*
1878 * This is needed only to setup initial state
1879 * but it's best done after a reset.
1880 */
1881 ath_update_txpow(sc);
8feceb67 1882
ff37e337
S		 1883 /*
1884 * Setup the hardware after reset:
1885 * The receive engine is set going.
1886 * Frame transmit is handled entirely
1887 * in the frame output path; there's nothing to do
1888 * here except setup the interrupt mask.
1889 */
1890 if (ath_startrecv(sc) != 0) {
8feceb67 1891 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1892 "Unable to start recv logic\n");
ae8d2858 1893 return -EIO;
f078f209 1894 }
8feceb67 1895
ff37e337
S		 1896 /* Setup our intr mask. */
1897 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1898 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1899 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1900
1901 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1902 sc->sc_imask |= ATH9K_INT_GTT;
1903
1904 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1905 sc->sc_imask |= ATH9K_INT_CST;
1906
1907 /*
1908 * Enable MIB interrupts when there are hardware phy counters.
1909 * Note we only do this (at the moment) for station mode.
1910 */
1911 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1912 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1913 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1914 sc->sc_imask |= ATH9K_INT_MIB;
1915 /*
1916 * Some hardware processes the TIM IE and fires an
1917 * interrupt when the TIM bit is set. For hardware
1918 * that does, if not overridden by configuration,
1919 * enable the TIM interrupt when operating as station.
1920 */
1921 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1922 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1923 !sc->sc_config.swBeaconProcess)
1924 sc->sc_imask |= ATH9K_INT_TIM;
1925
ce111bad 1926 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1927
1928 sc->sc_flags &= ~SC_OP_INVALID;
1929
1930 /* Disable BMISS interrupt when we're not associated */
1931 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1932 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1933
1934 ieee80211_wake_queues(sc->hw);
1935
e97275cb 1936#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1937 r = ath_start_rfkill_poll(sc);
500c064d 1938#endif
ae8d2858 1939 return r;
f078f209
LR		 1940}
1941
8feceb67
VT		 1942static int ath9k_tx(struct ieee80211_hw *hw,
1943 struct sk_buff *skb)
f078f209 1944{
528f0c6b 1945 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1946 struct ath_softc *sc = hw->priv;
528f0c6b 1947 struct ath_tx_control txctl;
8feceb67 1948 int hdrlen, padsize;
528f0c6b
S		 1949
1950 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1951
8feceb67
VT		 1952 /*
1953 * As a temporary workaround, assign seq# here; this will likely need
1954 * to be cleaned up to work better with Beacon transmission and virtual
1955 * BSSes.
1956 */
1957 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1958 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1959 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1960 sc->tx.seq_no += 0x10;
8feceb67 1961 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1962 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1963 }
f078f209 1964
8feceb67
VT		 1965 /* Add the padding after the header if this is not already done */
1966 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1967 if (hdrlen & 3) {
1968 padsize = hdrlen % 4;
1969 if (skb_headroom(skb) < padsize)
1970 return -1;
1971 skb_push(skb, padsize);
1972 memmove(skb->data, skb->data + padsize, hdrlen);
1973 }
1974
528f0c6b
S		 1975 /* Check if a tx queue is available */
1976
1977 txctl.txq = ath_test_get_txq(sc, skb);
1978 if (!txctl.txq)
1979 goto exit;
1980
04bd4638 1981 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1982
528f0c6b 1983 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1984 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1985 goto exit;
8feceb67
VT		 1986 }
1987
528f0c6b
S		 1988 return 0;
1989exit:
1990 dev_kfree_skb_any(skb);
8feceb67 1991 return 0;
f078f209
LR		 1992}
1993
8feceb67 1994static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 1995{
1996 struct ath_softc *sc = hw->priv;
f078f209 1997
9c84b797 1998 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 1999 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2000 return;
2001 }
8feceb67 2002
04bd4638 2003 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2004
2005 ieee80211_stop_queues(sc->hw);
2006
2007 /* make sure h/w will not generate any interrupt
2008 * before setting the invalid flag. */
2009 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2010
2011 if (!(sc->sc_flags & SC_OP_INVALID)) {
2012 ath_draintxq(sc, false);
2013 ath_stoprecv(sc);
2014 ath9k_hw_phy_disable(sc->sc_ah);
2015 } else
b77f483f 2016 sc->rx.rxlink = NULL;
ff37e337
S		 2017
2018#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2019 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2020 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2021#endif
2022 /* disable HAL and put h/w to sleep */
2023 ath9k_hw_disable(sc->sc_ah);
2024 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2025
2026 sc->sc_flags |= SC_OP_INVALID;
500c064d 2027
04bd4638 2028 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2029}
2030
8feceb67
VT		 2031static int ath9k_add_interface(struct ieee80211_hw *hw,
2032 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2033{
2034 struct ath_softc *sc = hw->priv;
5640b08e 2035 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2036 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2037
8feceb67
VT		 2038 /* Support only vap for now */
2039
2040 if (sc->sc_nvaps)
2041 return -ENOBUFS;
2042
2043 switch (conf->type) {
05c914fe 2044 case NL80211_IFTYPE_STATION:
d97809db 2045 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2046 break;
05c914fe 2047 case NL80211_IFTYPE_ADHOC:
d97809db 2048 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2049 break;
05c914fe 2050 case NL80211_IFTYPE_AP:
d97809db 2051 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2052 break;
2053 default:
2054 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2055 "Interface type %d not yet supported\n", conf->type);
8feceb67 2056 return -EOPNOTSUPP;
f078f209
LR		 2057 }
2058
04bd4638 2059 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2060
5640b08e
S		 2061 /* Set the VAP opmode */
2062 avp->av_opmode = ic_opmode;
2063 avp->av_bslot = -1;
2064
d97809db 2065 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2066 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2067
2068 sc->sc_vaps[0] = conf->vif;
2069 sc->sc_nvaps++;
2070
2071 /* Set the device opmode */
2072 sc->sc_ah->ah_opmode = ic_opmode;
2073
6f255425
LR		 2074 if (conf->type == NL80211_IFTYPE_AP) {
2075 /* TODO: is this a suitable place to start ANI for AP mode? */
2076 /* Start ANI */
2077 mod_timer(&sc->sc_ani.timer,
2078 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2079 }
2080
8feceb67 2081 return 0;
f078f209
LR		 2082}
2083
8feceb67
VT		 2084static void ath9k_remove_interface(struct ieee80211_hw *hw,
2085 struct ieee80211_if_init_conf *conf)
f078f209 2086{
8feceb67 2087 struct ath_softc *sc = hw->priv;
5640b08e 2088 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2089
04bd4638 2090 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2091
6f255425
LR		 2092 /* Stop ANI */
2093 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2094
8feceb67 2095 /* Reclaim beacon resources */
d97809db
CM		 2096 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2097 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2098 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2099 ath_beacon_return(sc, avp);
580f0b8a 2100 }
f078f209 2101
8feceb67 2102 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2103
5640b08e
S		 2104 sc->sc_vaps[0] = NULL;
2105 sc->sc_nvaps--;
f078f209
LR		 2106}
2107
e8975581 2108static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2109{
8feceb67 2110 struct ath_softc *sc = hw->priv;
e8975581 2111 struct ieee80211_conf *conf = &hw->conf;
f078f209 2112
aa33de09 2113 mutex_lock(&sc->mutex);
094d05dc
S		 2114 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2115 IEEE80211_CONF_CHANGE_HT)) {
99405f93
S		 2116 struct ieee80211_channel *curchan = hw->conf.channel;
2117 int pos;
ae5eb026 2118
04bd4638
S		 2119 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2120 curchan->center_freq);
f078f209 2121
99405f93
S		 2122 pos = ath_get_channel(sc, curchan);
2123 if (pos == -1) {
04bd4638
S		 2124 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2125 curchan->center_freq);
aa33de09 2126 mutex_unlock(&sc->mutex);
99405f93
S		 2127 return -EINVAL;
2128 }
f078f209 2129
99405f93 2130 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2131 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2132 (curchan->band == IEEE80211_BAND_2GHZ) ?
2133 CHANNEL_G : CHANNEL_A;
2134
094d05dc
S		 2135 if (conf->ht.enabled) {
2136 if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2137 conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2138 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2139
2140 sc->sc_ah->ah_channels[pos].chanmode =
2141 ath_get_extchanmode(sc, curchan,
094d05dc 2142 conf->ht.channel_type);
e11602b7
S		 2143 }
2144
86060f0d
S		 2145 ath_update_chainmask(sc, conf->ht.enabled);
2146
e11602b7 2147 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2148 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2149 mutex_unlock(&sc->mutex);
e11602b7
S		 2150 return -EINVAL;
2151 }
094d05dc 2152 }
f078f209 2153
5c020dc6
LR		 2154 if (changed & IEEE80211_CONF_CHANGE_POWER)
2155 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2156
aa33de09 2157 mutex_unlock(&sc->mutex);
f078f209
LR		 2158 return 0;
2159}
2160
8feceb67
VT		 2161static int ath9k_config_interface(struct ieee80211_hw *hw,
2162 struct ieee80211_vif *vif,
2163 struct ieee80211_if_conf *conf)
c83be688 2164{
8feceb67
VT		 2165 struct ath_softc *sc = hw->priv;
2166 struct ath_hal *ah = sc->sc_ah;
5640b08e 2167 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2168 u32 rfilt = 0;
2169 int error, i;
c83be688 2170
8feceb67
VT		 2171 /* TODO: Need to decide which hw opmode to use for multi-interface
2172 * cases */
05c914fe 2173 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2174 ah->ah_opmode != NL80211_IFTYPE_AP) {
2175 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2176 ath9k_hw_setopmode(ah);
2177 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2178 /* Request full reset to get hw opmode changed properly */
2179 sc->sc_flags |= SC_OP_FULL_RESET;
2180 }
c83be688 2181
8feceb67
VT		 2182 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2183 !is_zero_ether_addr(conf->bssid)) {
2184 switch (vif->type) {
05c914fe
JB		 2185 case NL80211_IFTYPE_STATION:
2186 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2187 /* Set BSSID */
2188 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2189 sc->sc_curaid = 0;
2190 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2191 sc->sc_curaid);
c83be688 2192
8feceb67
VT		 2193 /* Set aggregation protection mode parameters */
2194 sc->sc_config.ath_aggr_prot = 0;
c83be688 2195
8feceb67 2196 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2197 "RX filter 0x%x bssid %pM aid 0x%x\n",
2198 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2199
8feceb67
VT		 2200 /* need to reconfigure the beacon */
2201 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2202
8feceb67
VT		 2203 break;
2204 default:
2205 break;
2206 }
2207 }
c83be688 2208
8feceb67 2209 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2210 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2211 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2212 /*
2213 * Allocate and setup the beacon frame.
2214 *
2215 * Stop any previous beacon DMA. This may be
2216 * necessary, for example, when an ibss merge
2217 * causes reconfiguration; we may be called
2218 * with beacon transmission active.
2219 */
b77f483f 2220 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2221
8feceb67
VT		 2222 error = ath_beacon_alloc(sc, 0);
2223 if (error != 0)
2224 return error;
c83be688 2225
8feceb67
VT		 2226 ath_beacon_sync(sc, 0);
2227 }
c83be688 2228
8feceb67 2229 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2230 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2231 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2232 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2233 ath9k_hw_keysetmac(sc->sc_ah,
2234 (u16)i,
2235 sc->sc_curbssid);
2236 }
c83be688 2237
8feceb67 2238 /* Only legacy IBSS for now */
05c914fe 2239 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2240 ath_update_chainmask(sc, 0);
f078f209 2241
8feceb67
VT		 2242 return 0;
2243}
f078f209 2244
8feceb67
VT		 2245#define SUPPORTED_FILTERS \
2246 (FIF_PROMISC_IN_BSS | \
2247 FIF_ALLMULTI | \
2248 FIF_CONTROL | \
2249 FIF_OTHER_BSS | \
2250 FIF_BCN_PRBRESP_PROMISC | \
2251 FIF_FCSFAIL)
c83be688 2252
8feceb67
VT		 2253/* FIXME: sc->sc_full_reset ? */
2254static void ath9k_configure_filter(struct ieee80211_hw *hw,
2255 unsigned int changed_flags,
2256 unsigned int *total_flags,
2257 int mc_count,
2258 struct dev_mc_list *mclist)
2259{
2260 struct ath_softc *sc = hw->priv;
2261 u32 rfilt;
f078f209 2262
8feceb67
VT		 2263 changed_flags &= SUPPORTED_FILTERS;
2264 *total_flags &= SUPPORTED_FILTERS;
f078f209 2265
b77f483f 2266 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2267 rfilt = ath_calcrxfilter(sc);
2268 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2269
8feceb67
VT		 2270 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2271 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2272 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2273 }
f078f209 2274
b77f483f 2275 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2276}
f078f209 2277
8feceb67
VT		 2278static void ath9k_sta_notify(struct ieee80211_hw *hw,
2279 struct ieee80211_vif *vif,
2280 enum sta_notify_cmd cmd,
17741cdc 2281 struct ieee80211_sta *sta)
8feceb67
VT		 2282{
2283 struct ath_softc *sc = hw->priv;
f078f209 2284
8feceb67
VT		 2285 switch (cmd) {
2286 case STA_NOTIFY_ADD:
5640b08e 2287 ath_node_attach(sc, sta);
8feceb67
VT		 2288 break;
2289 case STA_NOTIFY_REMOVE:
b5aa9bf9 2290 ath_node_detach(sc, sta);
8feceb67
VT		 2291 break;
2292 default:
2293 break;
2294 }
f078f209
LR		 2295}
2296
8feceb67
VT		 2297static int ath9k_conf_tx(struct ieee80211_hw *hw,
2298 u16 queue,
2299 const struct ieee80211_tx_queue_params *params)
f078f209 2300{
8feceb67
VT		 2301 struct ath_softc *sc = hw->priv;
2302 struct ath9k_tx_queue_info qi;
2303 int ret = 0, qnum;
f078f209 2304
8feceb67
VT		 2305 if (queue >= WME_NUM_AC)
2306 return 0;
f078f209 2307
8feceb67
VT		 2308 qi.tqi_aifs = params->aifs;
2309 qi.tqi_cwmin = params->cw_min;
2310 qi.tqi_cwmax = params->cw_max;
2311 qi.tqi_burstTime = params->txop;
2312 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2313
8feceb67 2314 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2315 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2316 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2317 queue, qnum, params->aifs, params->cw_min,
2318 params->cw_max, params->txop);
f078f209 2319
8feceb67
VT		 2320 ret = ath_txq_update(sc, qnum, &qi);
2321 if (ret)
04bd4638 2322 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2323
8feceb67
VT		 2324 return ret;
2325}
f078f209 2326
8feceb67
VT		 2327static int ath9k_set_key(struct ieee80211_hw *hw,
2328 enum set_key_cmd cmd,
2329 const u8 *local_addr,
2330 const u8 *addr,
2331 struct ieee80211_key_conf *key)
2332{
2333 struct ath_softc *sc = hw->priv;
2334 int ret = 0;
f078f209 2335
04bd4638 2336 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2337
8feceb67
VT		 2338 switch (cmd) {
2339 case SET_KEY:
2340 ret = ath_key_config(sc, addr, key);
6ace2891
JM		 2341 if (ret >= 0) {
2342 key->hw_key_idx = ret;
8feceb67
VT		 2343 /* push IV and Michael MIC generation to stack */
2344 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2345 if (key->alg == ALG_TKIP)
2346 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6ace2891 2347 ret = 0;
8feceb67
VT		 2348 }
2349 break;
2350 case DISABLE_KEY:
2351 ath_key_delete(sc, key);
8feceb67
VT		 2352 break;
2353 default:
2354 ret = -EINVAL;
2355 }
f078f209 2356
8feceb67
VT		 2357 return ret;
2358}
f078f209 2359
8feceb67
VT		 2360static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2361 struct ieee80211_vif *vif,
2362 struct ieee80211_bss_conf *bss_conf,
2363 u32 changed)
2364{
2365 struct ath_softc *sc = hw->priv;
f078f209 2366
8feceb67 2367 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2368 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2369 bss_conf->use_short_preamble);
2370 if (bss_conf->use_short_preamble)
2371 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2372 else
2373 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2374 }
f078f209 2375
8feceb67 2376 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2377 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2378 bss_conf->use_cts_prot);
2379 if (bss_conf->use_cts_prot &&
2380 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2381 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2382 else
2383 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2384 }
f078f209 2385
8feceb67 2386 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2387 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2388 bss_conf->assoc);
5640b08e 2389 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2390 }
2391}
f078f209 2392
8feceb67
VT		 2393static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2394{
2395 u64 tsf;
2396 struct ath_softc *sc = hw->priv;
2397 struct ath_hal *ah = sc->sc_ah;
f078f209 2398
8feceb67 2399 tsf = ath9k_hw_gettsf64(ah);
f078f209 2400
8feceb67
VT		 2401 return tsf;
2402}
f078f209 2403
8feceb67
VT		 2404static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2405{
2406 struct ath_softc *sc = hw->priv;
2407 struct ath_hal *ah = sc->sc_ah;
c83be688 2408
8feceb67
VT		 2409 ath9k_hw_reset_tsf(ah);
2410}
f078f209 2411
8feceb67
VT		 2412static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2413 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2414 struct ieee80211_sta *sta,
2415 u16 tid, u16 *ssn)
8feceb67
VT		 2416{
2417 struct ath_softc *sc = hw->priv;
2418 int ret = 0;
f078f209 2419
8feceb67
VT		 2420 switch (action) {
2421 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2422 if (!(sc->sc_flags & SC_OP_RXAGGR))
2423 ret = -ENOTSUPP;
8feceb67
VT		 2424 break;
2425 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2426 break;
2427 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2428 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2429 if (ret < 0)
2430 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2431 "Unable to start TX aggregation\n");
8feceb67 2432 else
17741cdc 2433 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2434 break;
2435 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2436 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2437 if (ret < 0)
2438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2439 "Unable to stop TX aggregation\n");
f078f209 2440
17741cdc 2441 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2442 break;
8469cdef
S		 2443 case IEEE80211_AMPDU_TX_RESUME:
2444 ath_tx_aggr_resume(sc, sta, tid);
2445 break;
8feceb67 2446 default:
04bd4638 2447 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2448 }
2449
2450 return ret;
f078f209
LR		 2451}
2452
8feceb67
VT		 2453static struct ieee80211_ops ath9k_ops = {
2454 .tx = ath9k_tx,
2455 .start = ath9k_start,
2456 .stop = ath9k_stop,
2457 .add_interface = ath9k_add_interface,
2458 .remove_interface = ath9k_remove_interface,
2459 .config = ath9k_config,
2460 .config_interface = ath9k_config_interface,
2461 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2462 .sta_notify = ath9k_sta_notify,
2463 .conf_tx = ath9k_conf_tx,
8feceb67 2464 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2465 .set_key = ath9k_set_key,
8feceb67
VT		 2466 .get_tsf = ath9k_get_tsf,
2467 .reset_tsf = ath9k_reset_tsf,
4233df6b 2468 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2469};
2470
392dff83
BP		 2471static struct {
2472 u32 version;
2473 const char * name;
2474} ath_mac_bb_names[] = {
2475 { AR_SREV_VERSION_5416_PCI, "5416" },
2476 { AR_SREV_VERSION_5416_PCIE, "5418" },
2477 { AR_SREV_VERSION_9100, "9100" },
2478 { AR_SREV_VERSION_9160, "9160" },
2479 { AR_SREV_VERSION_9280, "9280" },
2480 { AR_SREV_VERSION_9285, "9285" }
2481};
2482
2483static struct {
2484 u16 version;
2485 const char * name;
2486} ath_rf_names[] = {
2487 { 0, "5133" },
2488 { AR_RAD5133_SREV_MAJOR, "5133" },
2489 { AR_RAD5122_SREV_MAJOR, "5122" },
2490 { AR_RAD2133_SREV_MAJOR, "2133" },
2491 { AR_RAD2122_SREV_MAJOR, "2122" }
2492};
2493
2494/*
2495 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2496 */
392dff83
BP		 2497static const char *
2498ath_mac_bb_name(u32 mac_bb_version)
2499{
2500 int i;
2501
2502 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2503 if (ath_mac_bb_names[i].version == mac_bb_version) {
2504 return ath_mac_bb_names[i].name;
2505 }
2506 }
2507
2508 return "????";
2509}
2510
2511/*
2512 * Return the RF name. "????" is returned if the RF is unknown.
2513 */
392dff83
BP		 2514static const char *
2515ath_rf_name(u16 rf_version)
2516{
2517 int i;
2518
2519 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2520 if (ath_rf_names[i].version == rf_version) {
2521 return ath_rf_names[i].name;
2522 }
2523 }
2524
2525 return "????";
2526}
2527
f078f209
LR		 2528static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2529{
2530 void __iomem *mem;
2531 struct ath_softc *sc;
2532 struct ieee80211_hw *hw;
f078f209
LR		 2533 u8 csz;
2534 u32 val;
2535 int ret = 0;
392dff83 2536 struct ath_hal *ah;
f078f209
LR		 2537
2538 if (pci_enable_device(pdev))
2539 return -EIO;
2540
97b777db
LR		 2541 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2542
2543 if (ret) {
1d450cfc 2544 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2545 goto bad;
2546 }
2547
2548 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2549
2550 if (ret) {
2551 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2552 "DMA enable failed\n");
f078f209
LR		 2553 goto bad;
2554 }
2555
2556 /*
2557 * Cache line size is used to size and align various
2558 * structures used to communicate with the hardware.
2559 */
2560 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2561 if (csz == 0) {
2562 /*
2563 * Linux 2.4.18 (at least) writes the cache line size
2564 * register as a 16-bit wide register which is wrong.
2565 * We must have this setup properly for rx buffer
2566 * DMA to work so force a reasonable value here if it
2567 * comes up zero.
2568 */
2569 csz = L1_CACHE_BYTES / sizeof(u32);
2570 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2571 }
2572 /*
2573 * The default setting of latency timer yields poor results,
2574 * set it to the value used by other systems. It may be worth
2575 * tweaking this setting more.
2576 */
2577 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2578
2579 pci_set_master(pdev);
2580
2581 /*
2582 * Disable the RETRY_TIMEOUT register (0x41) to keep
2583 * PCI Tx retries from interfering with C3 CPU state.
2584 */
2585 pci_read_config_dword(pdev, 0x40, &val);
2586 if ((val & 0x0000ff00) != 0)
2587 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2588
2589 ret = pci_request_region(pdev, 0, "ath9k");
2590 if (ret) {
2591 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2592 ret = -ENODEV;
2593 goto bad;
2594 }
2595
2596 mem = pci_iomap(pdev, 0, 0);
2597 if (!mem) {
2598 printk(KERN_ERR "PCI memory map error\n") ;
2599 ret = -EIO;
2600 goto bad1;
2601 }
2602
2603 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2604 if (hw == NULL) {
2605 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2606 goto bad2;
2607 }
2608
f078f209
LR		 2609 SET_IEEE80211_DEV(hw, &pdev->dev);
2610 pci_set_drvdata(pdev, hw);
2611
2612 sc = hw->priv;
2613 sc->hw = hw;
2614 sc->pdev = pdev;
2615 sc->mem = mem;
2616
2617 if (ath_attach(id->device, sc) != 0) {
2618 ret = -ENODEV;
2619 goto bad3;
2620 }
2621
2622 /* setup interrupt service routine */
2623
2624 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2625 printk(KERN_ERR "%s: request_irq failed\n",
2626 wiphy_name(hw->wiphy));
2627 ret = -EIO;
2628 goto bad4;
2629 }
2630
392dff83
BP		 2631 ah = sc->sc_ah;
2632 printk(KERN_INFO
2633 "%s: Atheros AR%s MAC/BB Rev:%x "
2634 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2635 wiphy_name(hw->wiphy),
392dff83
BP		 2636 ath_mac_bb_name(ah->ah_macVersion),
2637 ah->ah_macRev,
2638 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2639 ah->ah_phyRev,
f078f209
LR		 2640 (unsigned long)mem, pdev->irq);
2641
2642 return 0;
2643bad4:
2644 ath_detach(sc);
2645bad3:
2646 ieee80211_free_hw(hw);
2647bad2:
2648 pci_iounmap(pdev, mem);
2649bad1:
2650 pci_release_region(pdev, 0);
2651bad:
2652 pci_disable_device(pdev);
2653 return ret;
2654}
2655
2656static void ath_pci_remove(struct pci_dev *pdev)
2657{
2658 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2659 struct ath_softc *sc = hw->priv;
2660
f078f209 2661 ath_detach(sc);
9c84b797
S		 2662 if (pdev->irq)
2663 free_irq(pdev->irq, sc);
f078f209
LR		 2664 pci_iounmap(pdev, sc->mem);
2665 pci_release_region(pdev, 0);
2666 pci_disable_device(pdev);
2667 ieee80211_free_hw(hw);
2668}
2669
2670#ifdef CONFIG_PM
2671
2672static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2673{
c83be688
VT		 2674 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2675 struct ath_softc *sc = hw->priv;
2676
2677 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2678
e97275cb 2679#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2680 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2681 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2682#endif
2683
f078f209
LR		 2684 pci_save_state(pdev);
2685 pci_disable_device(pdev);
2686 pci_set_power_state(pdev, 3);
2687
2688 return 0;
2689}
2690
2691static int ath_pci_resume(struct pci_dev *pdev)
2692{
c83be688
VT		 2693 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2694 struct ath_softc *sc = hw->priv;
f078f209
LR		 2695 u32 val;
2696 int err;
2697
2698 err = pci_enable_device(pdev);
2699 if (err)
2700 return err;
2701 pci_restore_state(pdev);
2702 /*
2703 * Suspend/Resume resets the PCI configuration space, so we have to
2704 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2705 * PCI Tx retries from interfering with C3 CPU state
2706 */
2707 pci_read_config_dword(pdev, 0x40, &val);
2708 if ((val & 0x0000ff00) != 0)
2709 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2710
c83be688
VT		 2711 /* Enable LED */
2712 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2713 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2714 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2715
e97275cb 2716#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2717 /*
2718 * check the h/w rfkill state on resume
2719 * and start the rfkill poll timer
2720 */
2721 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2722 queue_delayed_work(sc->hw->workqueue,
2723 &sc->rf_kill.rfkill_poll, 0);
2724#endif
2725
f078f209
LR		 2726 return 0;
2727}
2728
2729#endif /* CONFIG_PM */
2730
2731MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2732
2733static struct pci_driver ath_pci_driver = {
2734 .name = "ath9k",
2735 .id_table = ath_pci_id_table,
2736 .probe = ath_pci_probe,
2737 .remove = ath_pci_remove,
2738#ifdef CONFIG_PM
2739 .suspend = ath_pci_suspend,
2740 .resume = ath_pci_resume,
2741#endif /* CONFIG_PM */
2742};
2743
2744static int __init init_ath_pci(void)
2745{
ca8a8560
VT		 2746 int error;
2747
f078f209
LR		 2748 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2749
ca8a8560
VT		 2750 /* Register rate control algorithm */
2751 error = ath_rate_control_register();
2752 if (error != 0) {
2753 printk(KERN_ERR
2754 "Unable to register rate control algorithm: %d\n",
2755 error);
2756 ath_rate_control_unregister();
2757 return error;
2758 }
2759
f078f209
LR		 2760 if (pci_register_driver(&ath_pci_driver) < 0) {
2761 printk(KERN_ERR
2762 "ath_pci: No devices found, driver not installed.\n");
ca8a8560 2763 ath_rate_control_unregister();
f078f209
LR		 2764 pci_unregister_driver(&ath_pci_driver);
2765 return -ENODEV;
2766 }
2767
2768 return 0;
2769}
2770module_init(init_ath_pci);
2771
2772static void __exit exit_ath_pci(void)
2773{
ca8a8560 2774 ath_rate_control_unregister();
f078f209 2775 pci_unregister_driver(&ath_pci_driver);
04bd4638 2776 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2777}
2778module_exit(exit_ath_pci);
Linux 6.x block layer and io_uring tree(s)