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mac80211: Creating new IBSS with fixed BSSID
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 30, \
37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 30, \
44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
142 struct ath_hal *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->sc_curtxpow = txpow;
150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
190 struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
ff37e337
S		 232/*
233 * Set/change channels. If the channel is really being changed, it's done
234 * by reseting the chip. To accomplish this we must first cleanup any pending
235 * DMA, then restart stuff.
236*/
237static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
238{
239 struct ath_hal *ah = sc->sc_ah;
240 bool fastcc = true, stopped;
030bb495 241 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 242 struct ieee80211_channel *channel = hw->conf.channel;
243 int r;
ff37e337
S		 244
245 if (sc->sc_flags & SC_OP_INVALID)
246 return -EIO;
247
3cbb5dd7
VN		 248 ath9k_ps_wakeup(sc);
249
c0d7c7af
LR		 250 /*
251 * This is only performed if the channel settings have
252 * actually changed.
253 *
254 * To switch channels clear any pending DMA operations;
255 * wait long enough for the RX fifo to drain, reset the
256 * hardware at the new frequency, and then re-enable
257 * the relevant bits of the h/w.
258 */
259 ath9k_hw_set_interrupts(ah, 0);
043a0405 260 ath_drain_all_txq(sc, false);
c0d7c7af 261 stopped = ath_stoprecv(sc);
ff37e337 262
c0d7c7af
LR		 263 /* XXX: do not flush receive queue here. We don't want
264 * to flush data frames already in queue because of
265 * changing channel. */
ff37e337 266
c0d7c7af
LR		 267 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
268 fastcc = false;
269
270 DPRINTF(sc, ATH_DBG_CONFIG,
271 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
272 sc->sc_ah->ah_curchan->channel,
273 channel->center_freq, sc->tx_chan_width);
ff37e337 274
c0d7c7af
LR		 275 spin_lock_bh(&sc->sc_resetlock);
276
277 r = ath9k_hw_reset(ah, hchan, fastcc);
278 if (r) {
279 DPRINTF(sc, ATH_DBG_FATAL,
280 "Unable to reset channel (%u Mhz) "
281 "reset status %u\n",
282 channel->center_freq, r);
283 spin_unlock_bh(&sc->sc_resetlock);
284 return r;
ff37e337 285 }
c0d7c7af
LR		 286 spin_unlock_bh(&sc->sc_resetlock);
287
288 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
289 sc->sc_flags &= ~SC_OP_FULL_RESET;
290
291 if (ath_startrecv(sc) != 0) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to restart recv logic\n");
294 return -EIO;
295 }
296
297 ath_cache_conf_rate(sc, &hw->conf);
298 ath_update_txpow(sc);
299 ath9k_hw_set_interrupts(ah, sc->sc_imask);
3cbb5dd7 300 ath9k_ps_restore(sc);
ff37e337
S		 301 return 0;
302}
303
304/*
305 * This routine performs the periodic noise floor calibration function
306 * that is used to adjust and optimize the chip performance. This
307 * takes environmental changes (location, temperature) into account.
308 * When the task is complete, it reschedules itself depending on the
309 * appropriate interval that was calculated.
310 */
311static void ath_ani_calibrate(unsigned long data)
312{
313 struct ath_softc *sc;
314 struct ath_hal *ah;
315 bool longcal = false;
316 bool shortcal = false;
317 bool aniflag = false;
318 unsigned int timestamp = jiffies_to_msecs(jiffies);
319 u32 cal_interval;
320
321 sc = (struct ath_softc *)data;
322 ah = sc->sc_ah;
323
324 /*
325 * don't calibrate when we're scanning.
326 * we are most likely not on our home channel.
327 */
b77f483f 328 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 329 return;
330
331 /* Long calibration runs independently of short calibration. */
332 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
333 longcal = true;
04bd4638 334 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 335 sc->sc_ani.sc_longcal_timer = timestamp;
336 }
337
338 /* Short calibration applies only while sc_caldone is false */
339 if (!sc->sc_ani.sc_caldone) {
340 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
341 ATH_SHORT_CALINTERVAL) {
342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 344 sc->sc_ani.sc_shortcal_timer = timestamp;
345 sc->sc_ani.sc_resetcal_timer = timestamp;
346 }
347 } else {
348 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
349 ATH_RESTART_CALINTERVAL) {
c9e27d94 350 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 351 if (sc->sc_ani.sc_caldone)
352 sc->sc_ani.sc_resetcal_timer = timestamp;
353 }
354 }
355
356 /* Verify whether we must check ANI */
357 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
358 ATH_ANI_POLLINTERVAL) {
359 aniflag = true;
360 sc->sc_ani.sc_checkani_timer = timestamp;
361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
367 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
368 ah->ah_curchan);
369
370 /* Perform calibration if necessary */
371 if (longcal || shortcal) {
372 bool iscaldone = false;
373
374 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
375 sc->sc_rx_chainmask, longcal,
376 &iscaldone)) {
377 if (longcal)
378 sc->sc_ani.sc_noise_floor =
379 ath9k_hw_getchan_noise(ah,
380 ah->ah_curchan);
381
382 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 383 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 384 ah->ah_curchan->channel,
385 ah->ah_curchan->channelFlags,
386 sc->sc_ani.sc_noise_floor);
387 } else {
388 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 389 "calibrate chan %u/%x failed\n",
ff37e337
S		 390 ah->ah_curchan->channel,
391 ah->ah_curchan->channelFlags);
392 }
393 sc->sc_ani.sc_caldone = iscaldone;
394 }
395 }
396
397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e
S		 402 cal_interval = ATH_LONG_CALINTERVAL;
403 if (sc->sc_ah->ah_config.enable_ani)
404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 405 if (!sc->sc_ani.sc_caldone)
406 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
407
408 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337
S		 416 */
417static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 420 if (is_ht ||
421 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 422 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
423 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
424 } else {
425 sc->sc_tx_chainmask = 1;
426 sc->sc_rx_chainmask = 1;
427 }
428
04bd4638
S		 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
430 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
458 u32 status = sc->sc_intrstatus;
459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
484 struct ath_hal *ah = sc->sc_ah;
485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
509 status &= sc->sc_imask; /* discard unasked-for bits */
510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
518 sc->sc_intrstatus = status;
519
520 if (status & ATH9K_INT_FATAL) {
521 /* need a chip reset */
522 sched = true;
523 } else if (status & ATH9K_INT_RXORN) {
524 /* need a chip reset */
525 sched = true;
526 } else {
527 if (status & ATH9K_INT_SWBA) {
528 /* schedule a tasklet for beacon handling */
529 tasklet_schedule(&sc->bcon_tasklet);
530 }
531 if (status & ATH9K_INT_RXEOL) {
532 /*
533 * NB: the hardware should re-read the link when
534 * RXE bit is written, but it doesn't work
535 * at least on older hardware revs.
536 */
537 sched = true;
538 }
539
540 if (status & ATH9K_INT_TXURN)
541 /* bump tx trigger level */
542 ath9k_hw_updatetxtriglevel(ah, true);
543 /* XXX: optimize this */
544 if (status & ATH9K_INT_RX)
545 sched = true;
546 if (status & ATH9K_INT_TX)
547 sched = true;
548 if (status & ATH9K_INT_BMISS)
549 sched = true;
550 /* carrier sense timeout */
551 if (status & ATH9K_INT_CST)
552 sched = true;
553 if (status & ATH9K_INT_MIB) {
554 /*
555 * Disable interrupts until we service the MIB
556 * interrupt; otherwise it will continue to
557 * fire.
558 */
559 ath9k_hw_set_interrupts(ah, 0);
560 /*
561 * Let the hal handle the event. We assume
562 * it will clear whatever condition caused
563 * the interrupt.
564 */
565 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
566 ath9k_hw_set_interrupts(ah, sc->sc_imask);
567 }
568 if (status & ATH9K_INT_TIM_TIMER) {
569 if (!(ah->ah_caps.hw_caps &
570 ATH9K_HW_CAP_AUTOSLEEP)) {
571 /* Clear RxAbort bit so that we can
572 * receive frames */
3cbb5dd7 573 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 574 ath9k_hw_setrxabort(ah, 0);
575 sched = true;
3cbb5dd7 576 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 577 }
578 }
579 }
580 } while (0);
581
817e11de
S		 582 ath_debug_stat_interrupt(sc, status);
583
ff37e337
S		 584 if (sched) {
585 /* turn off every interrupt except SWBA */
586 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
587 tasklet_schedule(&sc->intr_tq);
588 }
589
590 return IRQ_HANDLED;
591}
592
f078f209 593static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 594 struct ieee80211_channel *chan,
094d05dc 595 enum nl80211_channel_type channel_type)
f078f209
LR		 596{
597 u32 chanmode = 0;
f078f209
LR		 598
599 switch (chan->band) {
600 case IEEE80211_BAND_2GHZ:
094d05dc
S		 601 switch(channel_type) {
602 case NL80211_CHAN_NO_HT:
603 case NL80211_CHAN_HT20:
f078f209 604 chanmode = CHANNEL_G_HT20;
094d05dc
S		 605 break;
606 case NL80211_CHAN_HT40PLUS:
f078f209 607 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 608 break;
609 case NL80211_CHAN_HT40MINUS:
f078f209 610 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 611 break;
612 }
f078f209
LR		 613 break;
614 case IEEE80211_BAND_5GHZ:
094d05dc
S		 615 switch(channel_type) {
616 case NL80211_CHAN_NO_HT:
617 case NL80211_CHAN_HT20:
f078f209 618 chanmode = CHANNEL_A_HT20;
094d05dc
S		 619 break;
620 case NL80211_CHAN_HT40PLUS:
f078f209 621 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 622 break;
623 case NL80211_CHAN_HT40MINUS:
f078f209 624 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 625 break;
626 }
f078f209
LR		 627 break;
628 default:
629 break;
630 }
631
632 return chanmode;
633}
634
ff37e337
S		 635static int ath_keyset(struct ath_softc *sc, u16 keyix,
636 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
637{
638 bool status;
639
640 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
641 keyix, hk, mac, false);
642
643 return status != false;
644}
f078f209 645
6ace2891 646static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 647 struct ath9k_keyval *hk,
648 const u8 *addr)
649{
6ace2891
JM		 650 const u8 *key_rxmic;
651 const u8 *key_txmic;
f078f209 652
6ace2891
JM		 653 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
654 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 655
656 if (addr == NULL) {
657 /* Group key installation */
6ace2891
JM		 658 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
659 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 660 }
661 if (!sc->sc_splitmic) {
662 /*
663 * data key goes at first index,
664 * the hal handles the MIC keys at index+64.
665 */
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 668 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 669 }
670 /*
671 * TX key goes at first index, RX key at +32.
672 * The hal handles the MIC keys at index+64.
673 */
674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 675 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 676 /* Txmic entry failed. No need to proceed further */
677 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 678 "Setting TX MIC Key Failed\n");
f078f209
LR		 679 return 0;
680 }
681
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 /* XXX delete tx key on failure? */
6ace2891
JM		 684 return ath_keyset(sc, keyix + 32, hk, addr);
685}
686
687static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
688{
689 int i;
690
691 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
692 if (test_bit(i, sc->sc_keymap) ||
693 test_bit(i + 64, sc->sc_keymap))
694 continue; /* At least one part of TKIP key allocated */
695 if (sc->sc_splitmic &&
696 (test_bit(i + 32, sc->sc_keymap) ||
697 test_bit(i + 64 + 32, sc->sc_keymap)))
698 continue; /* At least one part of TKIP key allocated */
699
700 /* Found a free slot for a TKIP key */
701 return i;
702 }
703 return -1;
704}
705
706static int ath_reserve_key_cache_slot(struct ath_softc *sc)
707{
708 int i;
709
710 /* First, try to find slots that would not be available for TKIP. */
711 if (sc->sc_splitmic) {
712 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
713 if (!test_bit(i, sc->sc_keymap) &&
714 (test_bit(i + 32, sc->sc_keymap) ||
715 test_bit(i + 64, sc->sc_keymap) ||
716 test_bit(i + 64 + 32, sc->sc_keymap)))
717 return i;
718 if (!test_bit(i + 32, sc->sc_keymap) &&
719 (test_bit(i, sc->sc_keymap) ||
720 test_bit(i + 64, sc->sc_keymap) ||
721 test_bit(i + 64 + 32, sc->sc_keymap)))
722 return i + 32;
723 if (!test_bit(i + 64, sc->sc_keymap) &&
724 (test_bit(i , sc->sc_keymap) ||
725 test_bit(i + 32, sc->sc_keymap) ||
726 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 727 return i + 64;
6ace2891
JM		 728 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
729 (test_bit(i, sc->sc_keymap) ||
730 test_bit(i + 32, sc->sc_keymap) ||
731 test_bit(i + 64, sc->sc_keymap)))
ea612132 732 return i + 64 + 32;
6ace2891
JM		 733 }
734 } else {
735 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
736 if (!test_bit(i, sc->sc_keymap) &&
737 test_bit(i + 64, sc->sc_keymap))
738 return i;
739 if (test_bit(i, sc->sc_keymap) &&
740 !test_bit(i + 64, sc->sc_keymap))
741 return i + 64;
742 }
743 }
744
745 /* No partially used TKIP slots, pick any available slot */
746 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 747 /* Do not allow slots that could be needed for TKIP group keys
748 * to be used. This limitation could be removed if we know that
749 * TKIP will not be used. */
750 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
751 continue;
752 if (sc->sc_splitmic) {
753 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
754 continue;
755 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
756 continue;
757 }
758
6ace2891
JM		 759 if (!test_bit(i, sc->sc_keymap))
760 return i; /* Found a free slot for a key */
761 }
762
763 /* No free slot found */
764 return -1;
f078f209
LR		 765}
766
767static int ath_key_config(struct ath_softc *sc,
dc822b5d 768 struct ieee80211_sta *sta,
f078f209
LR		 769 struct ieee80211_key_conf *key)
770{
f078f209
LR		 771 struct ath9k_keyval hk;
772 const u8 *mac = NULL;
773 int ret = 0;
6ace2891 774 int idx;
f078f209
LR		 775
776 memset(&hk, 0, sizeof(hk));
777
778 switch (key->alg) {
779 case ALG_WEP:
780 hk.kv_type = ATH9K_CIPHER_WEP;
781 break;
782 case ALG_TKIP:
783 hk.kv_type = ATH9K_CIPHER_TKIP;
784 break;
785 case ALG_CCMP:
786 hk.kv_type = ATH9K_CIPHER_AES_CCM;
787 break;
788 default:
ca470b29 789 return -EOPNOTSUPP;
f078f209
LR		 790 }
791
6ace2891 792 hk.kv_len = key->keylen;
f078f209
LR		 793 memcpy(hk.kv_val, key->key, key->keylen);
794
6ace2891
JM		 795 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
796 /* For now, use the default keys for broadcast keys. This may
797 * need to change with virtual interfaces. */
798 idx = key->keyidx;
799 } else if (key->keyidx) {
800 struct ieee80211_vif *vif;
f078f209 801
dc822b5d
JB		 802 if (WARN_ON(!sta))
803 return -EOPNOTSUPP;
804 mac = sta->addr;
805
6ace2891
JM		 806 vif = sc->sc_vaps[0];
807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
f078f209 813 } else {
dc822b5d
JB		 814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
6ace2891
JM		 818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
ca470b29 823 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 824 }
825
826 if (key->alg == ALG_TKIP)
6ace2891 827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 828 else
6ace2891 829 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 830
831 if (!ret)
832 return -EIO;
833
6ace2891
JM		 834 set_bit(idx, sc->sc_keymap);
835 if (key->alg == ALG_TKIP) {
836 set_bit(idx + 64, sc->sc_keymap);
837 if (sc->sc_splitmic) {
838 set_bit(idx + 32, sc->sc_keymap);
839 set_bit(idx + 64 + 32, sc->sc_keymap);
840 }
841 }
842
843 return idx;
f078f209
LR		 844}
845
846static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
847{
6ace2891
JM		 848 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
849 if (key->hw_key_idx < IEEE80211_WEP_NKID)
850 return;
851
852 clear_bit(key->hw_key_idx, sc->sc_keymap);
853 if (key->alg != ALG_TKIP)
854 return;
f078f209 855
6ace2891
JM		 856 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
857 if (sc->sc_splitmic) {
858 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
859 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
860 }
f078f209
LR		 861}
862
eb2599ca
S		 863static void setup_ht_cap(struct ath_softc *sc,
864 struct ieee80211_sta_ht_cap *ht_info)
f078f209 865{
60653678
S		 866#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
867#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 868
d9fe60de
JB		 869 ht_info->ht_supported = true;
870 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
871 IEEE80211_HT_CAP_SM_PS |
872 IEEE80211_HT_CAP_SGI_40 |
873 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 874
60653678
S		 875 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
876 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 877
d9fe60de
JB		 878 /* set up supported mcs set */
879 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca
S		 880
881 switch(sc->sc_rx_chainmask) {
882 case 1:
883 ht_info->mcs.rx_mask[0] = 0xff;
884 break;
3c457265 885 case 3:
eb2599ca
S		 886 case 5:
887 case 7:
888 default:
889 ht_info->mcs.rx_mask[0] = 0xff;
890 ht_info->mcs.rx_mask[1] = 0xff;
891 break;
892 }
893
d9fe60de 894 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 895}
896
8feceb67 897static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 898 struct ieee80211_vif *vif,
8feceb67 899 struct ieee80211_bss_conf *bss_conf)
f078f209 900{
5640b08e 901 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 902
8feceb67 903 if (bss_conf->assoc) {
094d05dc
S		 904 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
905 bss_conf->aid, sc->sc_curbssid);
f078f209 906
8feceb67 907 /* New association, store aid */
d97809db 908 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 909 sc->sc_curaid = bss_conf->aid;
910 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
911 sc->sc_curaid);
912 }
f078f209 913
8feceb67
VT		 914 /* Configure the beacon */
915 ath_beacon_config(sc, 0);
916 sc->sc_flags |= SC_OP_BEACONS;
f078f209 917
8feceb67
VT		 918 /* Reset rssi stats */
919 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 923
6f255425
LR		 924 /* Start ANI */
925 mod_timer(&sc->sc_ani.timer,
926 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
927
8feceb67 928 } else {
04bd4638 929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 930 sc->sc_curaid = 0;
f078f209 931 }
8feceb67 932}
f078f209 933
8feceb67
VT		 934/********************************/
935/* LED functions */
936/********************************/
f078f209 937
8feceb67
VT		 938static void ath_led_brightness(struct led_classdev *led_cdev,
939 enum led_brightness brightness)
940{
941 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
942 struct ath_softc *sc = led->sc;
f078f209 943
8feceb67
VT		 944 switch (brightness) {
945 case LED_OFF:
946 if (led->led_type == ATH_LED_ASSOC ||
947 led->led_type == ATH_LED_RADIO)
948 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
949 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
950 (led->led_type == ATH_LED_RADIO) ? 1 :
951 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
952 break;
953 case LED_FULL:
954 if (led->led_type == ATH_LED_ASSOC)
955 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
956 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
957 break;
958 default:
959 break;
f078f209 960 }
8feceb67 961}
f078f209 962
8feceb67
VT		 963static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
964 char *trigger)
965{
966 int ret;
f078f209 967
8feceb67
VT		 968 led->sc = sc;
969 led->led_cdev.name = led->name;
970 led->led_cdev.default_trigger = trigger;
971 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 972
8feceb67
VT		 973 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
974 if (ret)
975 DPRINTF(sc, ATH_DBG_FATAL,
976 "Failed to register led:%s", led->name);
977 else
978 led->registered = 1;
979 return ret;
980}
f078f209 981
8feceb67
VT		 982static void ath_unregister_led(struct ath_led *led)
983{
984 if (led->registered) {
985 led_classdev_unregister(&led->led_cdev);
986 led->registered = 0;
f078f209 987 }
f078f209
LR		 988}
989
8feceb67 990static void ath_deinit_leds(struct ath_softc *sc)
f078f209 991{
8feceb67
VT		 992 ath_unregister_led(&sc->assoc_led);
993 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
994 ath_unregister_led(&sc->tx_led);
995 ath_unregister_led(&sc->rx_led);
996 ath_unregister_led(&sc->radio_led);
997 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
998}
f078f209 999
8feceb67
VT		 1000static void ath_init_leds(struct ath_softc *sc)
1001{
1002 char *trigger;
1003 int ret;
f078f209 1004
8feceb67
VT		 1005 /* Configure gpio 1 for output */
1006 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1007 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1008 /* LED off, active low */
1009 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1010
8feceb67
VT		 1011 trigger = ieee80211_get_radio_led_name(sc->hw);
1012 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1013 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1014 ret = ath_register_led(sc, &sc->radio_led, trigger);
1015 sc->radio_led.led_type = ATH_LED_RADIO;
1016 if (ret)
1017 goto fail;
7dcfdcd9 1018
8feceb67
VT		 1019 trigger = ieee80211_get_assoc_led_name(sc->hw);
1020 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1021 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1022 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1023 sc->assoc_led.led_type = ATH_LED_ASSOC;
1024 if (ret)
1025 goto fail;
f078f209 1026
8feceb67
VT		 1027 trigger = ieee80211_get_tx_led_name(sc->hw);
1028 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1029 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1030 ret = ath_register_led(sc, &sc->tx_led, trigger);
1031 sc->tx_led.led_type = ATH_LED_TX;
1032 if (ret)
1033 goto fail;
f078f209 1034
8feceb67
VT		 1035 trigger = ieee80211_get_rx_led_name(sc->hw);
1036 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1037 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1038 ret = ath_register_led(sc, &sc->rx_led, trigger);
1039 sc->rx_led.led_type = ATH_LED_RX;
1040 if (ret)
1041 goto fail;
f078f209 1042
8feceb67
VT		 1043 return;
1044
1045fail:
1046 ath_deinit_leds(sc);
f078f209
LR		 1047}
1048
e97275cb 1049#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1050
500c064d
VT		 1051/*******************/
1052/* Rfkill */
1053/*******************/
1054
1055static void ath_radio_enable(struct ath_softc *sc)
1056{
1057 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1058 struct ieee80211_channel *channel = sc->hw->conf.channel;
1059 int r;
500c064d 1060
3cbb5dd7 1061 ath9k_ps_wakeup(sc);
500c064d 1062 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1063
1064 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1065
1066 if (r) {
500c064d 1067 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1068 "Unable to reset channel %u (%uMhz) ",
1069 "reset status %u\n",
1070 channel->center_freq, r);
500c064d
VT		 1071 }
1072 spin_unlock_bh(&sc->sc_resetlock);
1073
1074 ath_update_txpow(sc);
1075 if (ath_startrecv(sc) != 0) {
1076 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1077 "Unable to restart recv logic\n");
500c064d
VT		 1078 return;
1079 }
1080
1081 if (sc->sc_flags & SC_OP_BEACONS)
1082 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1083
1084 /* Re-Enable interrupts */
1085 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1086
1087 /* Enable LED */
1088 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1089 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1090 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1091
1092 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1093 ath9k_ps_restore(sc);
500c064d
VT		 1094}
1095
1096static void ath_radio_disable(struct ath_softc *sc)
1097{
1098 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1099 struct ieee80211_channel *channel = sc->hw->conf.channel;
1100 int r;
500c064d 1101
3cbb5dd7 1102 ath9k_ps_wakeup(sc);
500c064d
VT		 1103 ieee80211_stop_queues(sc->hw);
1104
1105 /* Disable LED */
1106 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1107 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1108
1109 /* Disable interrupts */
1110 ath9k_hw_set_interrupts(ah, 0);
1111
043a0405 1112 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1113 ath_stoprecv(sc); /* turn off frame recv */
1114 ath_flushrecv(sc); /* flush recv queue */
1115
1116 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1117 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1118 if (r) {
500c064d 1119 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1120 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1121 "reset status %u\n",
1122 channel->center_freq, r);
500c064d
VT		 1123 }
1124 spin_unlock_bh(&sc->sc_resetlock);
1125
1126 ath9k_hw_phy_disable(ah);
1127 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1128 ath9k_ps_restore(sc);
500c064d
VT		 1129}
1130
1131static bool ath_is_rfkill_set(struct ath_softc *sc)
1132{
1133 struct ath_hal *ah = sc->sc_ah;
1134
1135 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1136 ah->ah_rfkill_polarity;
1137}
1138
1139/* h/w rfkill poll function */
1140static void ath_rfkill_poll(struct work_struct *work)
1141{
1142 struct ath_softc *sc = container_of(work, struct ath_softc,
1143 rf_kill.rfkill_poll.work);
1144 bool radio_on;
1145
1146 if (sc->sc_flags & SC_OP_INVALID)
1147 return;
1148
1149 radio_on = !ath_is_rfkill_set(sc);
1150
1151 /*
1152 * enable/disable radio only when there is a
1153 * state change in RF switch
1154 */
1155 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1156 enum rfkill_state state;
1157
1158 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1159 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1160 : RFKILL_STATE_HARD_BLOCKED;
1161 } else if (radio_on) {
1162 ath_radio_enable(sc);
1163 state = RFKILL_STATE_UNBLOCKED;
1164 } else {
1165 ath_radio_disable(sc);
1166 state = RFKILL_STATE_HARD_BLOCKED;
1167 }
1168
1169 if (state == RFKILL_STATE_HARD_BLOCKED)
1170 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1171 else
1172 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1173
1174 rfkill_force_state(sc->rf_kill.rfkill, state);
1175 }
1176
1177 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1178 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1179}
1180
1181/* s/w rfkill handler */
1182static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1183{
1184 struct ath_softc *sc = data;
1185
1186 switch (state) {
1187 case RFKILL_STATE_SOFT_BLOCKED:
1188 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1189 SC_OP_RFKILL_SW_BLOCKED)))
1190 ath_radio_disable(sc);
1191 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1192 return 0;
1193 case RFKILL_STATE_UNBLOCKED:
1194 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1195 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1196 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1197 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1198 "radio as it is disabled by h/w\n");
500c064d
VT		 1199 return -EPERM;
1200 }
1201 ath_radio_enable(sc);
1202 }
1203 return 0;
1204 default:
1205 return -EINVAL;
1206 }
1207}
1208
1209/* Init s/w rfkill */
1210static int ath_init_sw_rfkill(struct ath_softc *sc)
1211{
1212 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1213 RFKILL_TYPE_WLAN);
1214 if (!sc->rf_kill.rfkill) {
1215 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1216 return -ENOMEM;
1217 }
1218
1219 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1220 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1221 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1222 sc->rf_kill.rfkill->data = sc;
1223 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1224 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1225 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1226
1227 return 0;
1228}
1229
1230/* Deinitialize rfkill */
1231static void ath_deinit_rfkill(struct ath_softc *sc)
1232{
1233 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1234 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1235
1236 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1237 rfkill_unregister(sc->rf_kill.rfkill);
1238 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1239 sc->rf_kill.rfkill = NULL;
1240 }
1241}
9c84b797
S		 1242
1243static int ath_start_rfkill_poll(struct ath_softc *sc)
1244{
1245 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1246 queue_delayed_work(sc->hw->workqueue,
1247 &sc->rf_kill.rfkill_poll, 0);
1248
1249 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1250 if (rfkill_register(sc->rf_kill.rfkill)) {
1251 DPRINTF(sc, ATH_DBG_FATAL,
1252 "Unable to register rfkill\n");
1253 rfkill_free(sc->rf_kill.rfkill);
1254
1255 /* Deinitialize the device */
39c3c2f2 1256 ath_cleanup(sc);
9c84b797
S		 1257 return -EIO;
1258 } else {
1259 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1260 }
1261 }
1262
1263 return 0;
1264}
500c064d
VT		 1265#endif /* CONFIG_RFKILL */
1266
6baff7f9 1267void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1268{
1269 ath_detach(sc);
1270 free_irq(sc->irq, sc);
1271 ath_bus_cleanup(sc);
1272 ieee80211_free_hw(sc->hw);
1273}
1274
6baff7f9 1275void ath_detach(struct ath_softc *sc)
f078f209 1276{
8feceb67 1277 struct ieee80211_hw *hw = sc->hw;
9c84b797 1278 int i = 0;
f078f209 1279
3cbb5dd7
VN		 1280 ath9k_ps_wakeup(sc);
1281
04bd4638 1282 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1283
e97275cb 1284#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1285 ath_deinit_rfkill(sc);
1286#endif
3fcdfb4b
VT		 1287 ath_deinit_leds(sc);
1288
1289 ieee80211_unregister_hw(hw);
8feceb67
VT		 1290 ath_rx_cleanup(sc);
1291 ath_tx_cleanup(sc);
f078f209 1292
9c84b797
S		 1293 tasklet_kill(&sc->intr_tq);
1294 tasklet_kill(&sc->bcon_tasklet);
f078f209 1295
9c84b797
S		 1296 if (!(sc->sc_flags & SC_OP_INVALID))
1297 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1298
9c84b797
S		 1299 /* cleanup tx queues */
1300 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1301 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1302 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1303
1304 ath9k_hw_detach(sc->sc_ah);
826d2680 1305 ath9k_exit_debug(sc);
3cbb5dd7 1306 ath9k_ps_restore(sc);
f078f209
LR		 1307}
1308
ff37e337
S		 1309static int ath_init(u16 devid, struct ath_softc *sc)
1310{
1311 struct ath_hal *ah = NULL;
1312 int status;
1313 int error = 0, i;
1314 int csz = 0;
1315
1316 /* XXX: hardware will not be ready until ath_open() being called */
1317 sc->sc_flags |= SC_OP_INVALID;
88b126af 1318
826d2680
S		 1319 if (ath9k_init_debug(sc) < 0)
1320 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1321
1322 spin_lock_init(&sc->sc_resetlock);
aa33de09 1323 mutex_init(&sc->mutex);
ff37e337
S		 1324 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1325 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1326 (unsigned long)sc);
1327
1328 /*
1329 * Cache line size is used to size and align various
1330 * structures used to communicate with the hardware.
1331 */
88d15707 1332 ath_read_cachesize(sc, &csz);
ff37e337
S		 1333 /* XXX assert csz is non-zero */
1334 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1335
1336 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1337 if (ah == NULL) {
1338 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1339 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1340 error = -ENXIO;
1341 goto bad;
1342 }
1343 sc->sc_ah = ah;
1344
1345 /* Get the hardware key cache size. */
1346 sc->sc_keymax = ah->ah_caps.keycache_size;
1347 if (sc->sc_keymax > ATH_KEYMAX) {
1348 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1349 "Warning, using only %u entries in %u key cache\n",
1350 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1351 sc->sc_keymax = ATH_KEYMAX;
1352 }
1353
1354 /*
1355 * Reset the key cache since some parts do not
1356 * reset the contents on initial power up.
1357 */
1358 for (i = 0; i < sc->sc_keymax; i++)
1359 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1360
5f8e077c 1361 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1362 goto bad;
1363
1364 /* default to MONITOR mode */
d97809db
CM		 1365 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1366
ff37e337
S		 1367 /* Setup rate tables */
1368
1369 ath_rate_attach(sc);
1370 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1371 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1372
1373 /*
1374 * Allocate hardware transmit queues: one queue for
1375 * beacon frames and one data queue for each QoS
1376 * priority. Note that the hal handles reseting
1377 * these queues at the needed time.
1378 */
b77f483f
S		 1379 sc->beacon.beaconq = ath_beaconq_setup(ah);
1380 if (sc->beacon.beaconq == -1) {
ff37e337 1381 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1382 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1383 error = -EIO;
1384 goto bad2;
1385 }
b77f483f
S		 1386 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1387 if (sc->beacon.cabq == NULL) {
ff37e337 1388 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1389 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1390 error = -EIO;
1391 goto bad2;
1392 }
1393
1394 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1395 ath_cabq_update(sc);
1396
b77f483f
S		 1397 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1398 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1399
1400 /* Setup data queues */
1401 /* NB: ensure BK queue is the lowest priority h/w queue */
1402 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1403 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1404 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1405 error = -EIO;
1406 goto bad2;
1407 }
1408
1409 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1410 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1411 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1412 error = -EIO;
1413 goto bad2;
1414 }
1415 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1416 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1417 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1418 error = -EIO;
1419 goto bad2;
1420 }
1421 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1422 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1423 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1424 error = -EIO;
1425 goto bad2;
1426 }
1427
1428 /* Initializes the noise floor to a reasonable default value.
1429 * Later on this will be updated during ANI processing. */
1430
1431 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1432 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1433
1434 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1435 ATH9K_CIPHER_TKIP, NULL)) {
1436 /*
1437 * Whether we should enable h/w TKIP MIC.
1438 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1439 * report WMM capable, so it's always safe to turn on
1440 * TKIP MIC in this case.
1441 */
1442 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1443 0, 1, NULL);
1444 }
1445
1446 /*
1447 * Check whether the separate key cache entries
1448 * are required to handle both tx+rx MIC keys.
1449 * With split mic keys the number of stations is limited
1450 * to 27 otherwise 59.
1451 */
1452 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1453 ATH9K_CIPHER_TKIP, NULL)
1454 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1455 ATH9K_CIPHER_MIC, NULL)
1456 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1457 0, NULL))
1458 sc->sc_splitmic = 1;
1459
1460 /* turn on mcast key search if possible */
1461 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1462 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1463 1, NULL);
1464
1465 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1466 sc->sc_config.txpowlimit_override = 0;
1467
1468 /* 11n Capabilities */
1469 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1470 sc->sc_flags |= SC_OP_TXAGGR;
1471 sc->sc_flags |= SC_OP_RXAGGR;
1472 }
1473
1474 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1475 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1476
1477 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1478 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1479
1480 ath9k_hw_getmac(ah, sc->sc_myaddr);
1481 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1482 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1483 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1484 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1485 }
1486
b77f483f 1487 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1488
1489 /* initialize beacon slots */
b77f483f
S		 1490 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1491 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1492
1493 /* save MISC configurations */
1494 sc->sc_config.swBeaconProcess = 1;
1495
ff37e337
S		 1496 /* setup channels and rates */
1497
5f8e077c 1498 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1499 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1500 sc->rates[IEEE80211_BAND_2GHZ];
1501 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1502 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1503 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337
S		 1504
1505 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
5f8e077c 1506 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1507 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1508 sc->rates[IEEE80211_BAND_5GHZ];
1509 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1510 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1511 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1512 }
1513
c97c92d9
VT		 1514 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1515 ath9k_hw_btcoex_enable(sc->sc_ah);
1516
ff37e337
S		 1517 return 0;
1518bad2:
1519 /* cleanup tx queues */
1520 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1521 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1522 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1523bad:
1524 if (ah)
1525 ath9k_hw_detach(ah);
1526
1527 return error;
1528}
1529
6baff7f9 1530int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1531{
8feceb67
VT		 1532 struct ieee80211_hw *hw = sc->hw;
1533 int error = 0;
f078f209 1534
04bd4638 1535 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1536
8feceb67
VT		 1537 error = ath_init(devid, sc);
1538 if (error != 0)
1539 return error;
f078f209 1540
8feceb67 1541 /* get mac address from hardware and set in mac80211 */
f078f209 1542
8feceb67 1543 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1544
9c84b797
S		 1545 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1546 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1547 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1548 IEEE80211_HW_AMPDU_AGGREGATION |
1549 IEEE80211_HW_SUPPORTS_PS |
1550 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1551
0ced0e17
JM		 1552 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1553 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1554
9c84b797
S		 1555 hw->wiphy->interface_modes =
1556 BIT(NL80211_IFTYPE_AP) |
1557 BIT(NL80211_IFTYPE_STATION) |
1558 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1559
5f8e077c
LR		 1560 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1561 hw->wiphy->strict_regulatory = true;
1562
8feceb67 1563 hw->queues = 4;
e63835b0
S		 1564 hw->max_rates = 4;
1565 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1566 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1567 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1568
8feceb67 1569 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1570
9c84b797 1571 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1572 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
9c84b797 1573 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
eb2599ca 1574 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1575 }
1576
1577 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1578 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1579 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1580 &sc->sbands[IEEE80211_BAND_5GHZ];
1581
db93e7b5
SB		 1582 /* initialize tx/rx engine */
1583 error = ath_tx_init(sc, ATH_TXBUF);
1584 if (error != 0)
1585 goto detach;
8feceb67 1586
db93e7b5
SB		 1587 error = ath_rx_init(sc, ATH_RXBUF);
1588 if (error != 0)
1589 goto detach;
8feceb67 1590
e97275cb 1591#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1592 /* Initialze h/w Rfkill */
1593 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1594 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1595
1596 /* Initialize s/w rfkill */
1597 if (ath_init_sw_rfkill(sc))
1598 goto detach;
1599#endif
1600
5f8e077c
LR		 1601 if (ath9k_is_world_regd(sc->sc_ah)) {
1602 /* Anything applied here (prior to wiphy registratoin) gets
1603 * saved on the wiphy orig_* parameters */
1604 const struct ieee80211_regdomain *regd =
1605 ath9k_world_regdomain(sc->sc_ah);
1606 hw->wiphy->custom_regulatory = true;
1607 hw->wiphy->strict_regulatory = false;
1608 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1609 ath9k_reg_apply_radar_flags(hw->wiphy);
1610 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1611 } else {
1612 /* This gets applied in the case of the absense of CRDA,
1613 * its our own custom world regulatory domain, similar to
1614 * cfg80211's but we enable passive scanning */
1615 const struct ieee80211_regdomain *regd =
1616 ath9k_default_world_regdomain();
1617 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1618 ath9k_reg_apply_radar_flags(hw->wiphy);
1619 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1620 }
1621
db93e7b5 1622 error = ieee80211_register_hw(hw);
8feceb67 1623
5f8e077c
LR		 1624 if (!ath9k_is_world_regd(sc->sc_ah))
1625 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1626
db93e7b5
SB		 1627 /* Initialize LED control */
1628 ath_init_leds(sc);
8feceb67 1629
5f8e077c 1630
8feceb67
VT		 1631 return 0;
1632detach:
1633 ath_detach(sc);
8feceb67 1634 return error;
f078f209
LR		 1635}
1636
ff37e337
S		 1637int ath_reset(struct ath_softc *sc, bool retry_tx)
1638{
1639 struct ath_hal *ah = sc->sc_ah;
030bb495 1640 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1641 int r;
ff37e337
S		 1642
1643 ath9k_hw_set_interrupts(ah, 0);
043a0405 1644 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1645 ath_stoprecv(sc);
1646 ath_flushrecv(sc);
1647
1648 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1649 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1650 if (r)
ff37e337 1651 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1652 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1653 spin_unlock_bh(&sc->sc_resetlock);
1654
1655 if (ath_startrecv(sc) != 0)
04bd4638 1656 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1657
1658 /*
1659 * We may be doing a reset in response to a request
1660 * that changes the channel so update any state that
1661 * might change as a result.
1662 */
ce111bad 1663 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1664
1665 ath_update_txpow(sc);
1666
1667 if (sc->sc_flags & SC_OP_BEACONS)
1668 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1669
1670 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1671
1672 if (retry_tx) {
1673 int i;
1674 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1675 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1676 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1677 ath_txq_schedule(sc, &sc->tx.txq[i]);
1678 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1679 }
1680 }
1681 }
1682
ae8d2858 1683 return r;
ff37e337
S		 1684}
1685
1686/*
1687 * This function will allocate both the DMA descriptor structure, and the
1688 * buffers it contains. These are used to contain the descriptors used
1689 * by the system.
1690*/
1691int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1692 struct list_head *head, const char *name,
1693 int nbuf, int ndesc)
1694{
1695#define DS2PHYS(_dd, _ds) \
1696 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1697#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1698#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1699
1700 struct ath_desc *ds;
1701 struct ath_buf *bf;
1702 int i, bsize, error;
1703
04bd4638
S		 1704 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1705 name, nbuf, ndesc);
ff37e337
S		 1706
1707 /* ath_desc must be a multiple of DWORDs */
1708 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1709 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1710 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1711 error = -ENOMEM;
1712 goto fail;
1713 }
1714
1715 dd->dd_name = name;
1716 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1717
1718 /*
1719 * Need additional DMA memory because we can't use
1720 * descriptors that cross the 4K page boundary. Assume
1721 * one skipped descriptor per 4K page.
1722 */
1723 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1724 u32 ndesc_skipped =
1725 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1726 u32 dma_len;
1727
1728 while (ndesc_skipped) {
1729 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1730 dd->dd_desc_len += dma_len;
1731
1732 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1733 };
1734 }
1735
1736 /* allocate descriptors */
7da3c55c
GJ		 1737 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1738 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1739 if (dd->dd_desc == NULL) {
1740 error = -ENOMEM;
1741 goto fail;
1742 }
1743 ds = dd->dd_desc;
04bd4638
S		 1744 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1745 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1746 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1747
1748 /* allocate buffers */
1749 bsize = sizeof(struct ath_buf) * nbuf;
1750 bf = kmalloc(bsize, GFP_KERNEL);
1751 if (bf == NULL) {
1752 error = -ENOMEM;
1753 goto fail2;
1754 }
1755 memset(bf, 0, bsize);
1756 dd->dd_bufptr = bf;
1757
1758 INIT_LIST_HEAD(head);
1759 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1760 bf->bf_desc = ds;
1761 bf->bf_daddr = DS2PHYS(dd, ds);
1762
1763 if (!(sc->sc_ah->ah_caps.hw_caps &
1764 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765 /*
1766 * Skip descriptor addresses which can cause 4KB
1767 * boundary crossing (addr + length) with a 32 dword
1768 * descriptor fetch.
1769 */
1770 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1771 ASSERT((caddr_t) bf->bf_desc <
1772 ((caddr_t) dd->dd_desc +
1773 dd->dd_desc_len));
1774
1775 ds += ndesc;
1776 bf->bf_desc = ds;
1777 bf->bf_daddr = DS2PHYS(dd, ds);
1778 }
1779 }
1780 list_add_tail(&bf->list, head);
1781 }
1782 return 0;
1783fail2:
7da3c55c
GJ		 1784 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1785 dd->dd_desc_paddr);
ff37e337
S		 1786fail:
1787 memset(dd, 0, sizeof(*dd));
1788 return error;
1789#undef ATH_DESC_4KB_BOUND_CHECK
1790#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1791#undef DS2PHYS
1792}
1793
1794void ath_descdma_cleanup(struct ath_softc *sc,
1795 struct ath_descdma *dd,
1796 struct list_head *head)
1797{
7da3c55c
GJ		 1798 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1799 dd->dd_desc_paddr);
ff37e337
S		 1800
1801 INIT_LIST_HEAD(head);
1802 kfree(dd->dd_bufptr);
1803 memset(dd, 0, sizeof(*dd));
1804}
1805
1806int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1807{
1808 int qnum;
1809
1810 switch (queue) {
1811 case 0:
b77f483f 1812 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1813 break;
1814 case 1:
b77f483f 1815 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1816 break;
1817 case 2:
b77f483f 1818 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1819 break;
1820 case 3:
b77f483f 1821 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1822 break;
1823 default:
b77f483f 1824 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1825 break;
1826 }
1827
1828 return qnum;
1829}
1830
1831int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1832{
1833 int qnum;
1834
1835 switch (queue) {
1836 case ATH9K_WME_AC_VO:
1837 qnum = 0;
1838 break;
1839 case ATH9K_WME_AC_VI:
1840 qnum = 1;
1841 break;
1842 case ATH9K_WME_AC_BE:
1843 qnum = 2;
1844 break;
1845 case ATH9K_WME_AC_BK:
1846 qnum = 3;
1847 break;
1848 default:
1849 qnum = -1;
1850 break;
1851 }
1852
1853 return qnum;
1854}
1855
5f8e077c
LR		 1856/* XXX: Remove me once we don't depend on ath9k_channel for all
1857 * this redundant data */
1858static void ath9k_update_ichannel(struct ath_softc *sc,
1859 struct ath9k_channel *ichan)
1860{
1861 struct ieee80211_hw *hw = sc->hw;
1862 struct ieee80211_channel *chan = hw->conf.channel;
1863 struct ieee80211_conf *conf = &hw->conf;
1864
1865 ichan->channel = chan->center_freq;
1866 ichan->chan = chan;
1867
1868 if (chan->band == IEEE80211_BAND_2GHZ) {
1869 ichan->chanmode = CHANNEL_G;
1870 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1871 } else {
1872 ichan->chanmode = CHANNEL_A;
1873 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1874 }
1875
1876 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1877
1878 if (conf_is_ht(conf)) {
1879 if (conf_is_ht40(conf))
1880 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1881
1882 ichan->chanmode = ath_get_extchanmode(sc, chan,
1883 conf->channel_type);
1884 }
1885}
1886
ff37e337
S		 1887/**********************/
1888/* mac80211 callbacks */
1889/**********************/
1890
8feceb67 1891static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1892{
1893 struct ath_softc *sc = hw->priv;
8feceb67 1894 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1895 struct ath9k_channel *init_channel;
ae8d2858 1896 int r, pos;
f078f209 1897
04bd4638
S		 1898 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1899 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1900
8feceb67 1901 /* setup initial channel */
f078f209 1902
5f8e077c 1903 pos = curchan->hw_value;
f078f209 1904
ff37e337 1905 init_channel = &sc->sc_ah->ah_channels[pos];
5f8e077c 1906 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1907
1908 /* Reset SERDES registers */
1909 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1910
1911 /*
1912 * The basic interface to setting the hardware in a good
1913 * state is ``reset''. On return the hardware is known to
1914 * be powered up and with interrupts disabled. This must
1915 * be followed by initialization of the appropriate bits
1916 * and then setup of the interrupt mask.
1917 */
1918 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1919 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1920 if (r) {
ff37e337 1921 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1922 "Unable to reset hardware; reset status %u "
1923 "(freq %u MHz)\n", r,
1924 curchan->center_freq);
ff37e337 1925 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1926 return r;
ff37e337
S		 1927 }
1928 spin_unlock_bh(&sc->sc_resetlock);
1929
1930 /*
1931 * This is needed only to setup initial state
1932 * but it's best done after a reset.
1933 */
1934 ath_update_txpow(sc);
8feceb67 1935
ff37e337
S		 1936 /*
1937 * Setup the hardware after reset:
1938 * The receive engine is set going.
1939 * Frame transmit is handled entirely
1940 * in the frame output path; there's nothing to do
1941 * here except setup the interrupt mask.
1942 */
1943 if (ath_startrecv(sc) != 0) {
8feceb67 1944 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1945 "Unable to start recv logic\n");
ae8d2858 1946 return -EIO;
f078f209 1947 }
8feceb67 1948
ff37e337
S		 1949 /* Setup our intr mask. */
1950 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1951 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1952 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1953
1954 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1955 sc->sc_imask |= ATH9K_INT_GTT;
1956
1957 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1958 sc->sc_imask |= ATH9K_INT_CST;
1959
ce111bad 1960 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1961
1962 sc->sc_flags &= ~SC_OP_INVALID;
1963
1964 /* Disable BMISS interrupt when we're not associated */
1965 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1966 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1967
1968 ieee80211_wake_queues(sc->hw);
1969
e97275cb 1970#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1971 r = ath_start_rfkill_poll(sc);
500c064d 1972#endif
ae8d2858 1973 return r;
f078f209
LR		 1974}
1975
8feceb67
VT		 1976static int ath9k_tx(struct ieee80211_hw *hw,
1977 struct sk_buff *skb)
f078f209 1978{
528f0c6b 1979 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1980 struct ath_softc *sc = hw->priv;
528f0c6b 1981 struct ath_tx_control txctl;
8feceb67 1982 int hdrlen, padsize;
528f0c6b
S		 1983
1984 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1985
8feceb67
VT		 1986 /*
1987 * As a temporary workaround, assign seq# here; this will likely need
1988 * to be cleaned up to work better with Beacon transmission and virtual
1989 * BSSes.
1990 */
1991 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1992 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1993 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1994 sc->tx.seq_no += 0x10;
8feceb67 1995 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1996 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1997 }
f078f209 1998
8feceb67
VT		 1999 /* Add the padding after the header if this is not already done */
2000 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2001 if (hdrlen & 3) {
2002 padsize = hdrlen % 4;
2003 if (skb_headroom(skb) < padsize)
2004 return -1;
2005 skb_push(skb, padsize);
2006 memmove(skb->data, skb->data + padsize, hdrlen);
2007 }
2008
528f0c6b
S		 2009 /* Check if a tx queue is available */
2010
2011 txctl.txq = ath_test_get_txq(sc, skb);
2012 if (!txctl.txq)
2013 goto exit;
2014
04bd4638 2015 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2016
528f0c6b 2017 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2018 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2019 goto exit;
8feceb67
VT		 2020 }
2021
528f0c6b
S		 2022 return 0;
2023exit:
2024 dev_kfree_skb_any(skb);
8feceb67 2025 return 0;
f078f209
LR		 2026}
2027
8feceb67 2028static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2029{
2030 struct ath_softc *sc = hw->priv;
f078f209 2031
9c84b797 2032 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2033 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2034 return;
2035 }
8feceb67 2036
04bd4638 2037 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2038
2039 ieee80211_stop_queues(sc->hw);
2040
2041 /* make sure h/w will not generate any interrupt
2042 * before setting the invalid flag. */
2043 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2044
2045 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2046 ath_drain_all_txq(sc, false);
ff37e337
S		 2047 ath_stoprecv(sc);
2048 ath9k_hw_phy_disable(sc->sc_ah);
2049 } else
b77f483f 2050 sc->rx.rxlink = NULL;
ff37e337
S		 2051
2052#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2053 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2054 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2055#endif
2056 /* disable HAL and put h/w to sleep */
2057 ath9k_hw_disable(sc->sc_ah);
2058 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2059
2060 sc->sc_flags |= SC_OP_INVALID;
500c064d 2061
04bd4638 2062 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2063}
2064
8feceb67
VT		 2065static int ath9k_add_interface(struct ieee80211_hw *hw,
2066 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2067{
2068 struct ath_softc *sc = hw->priv;
5640b08e 2069 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2070 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2071
8feceb67
VT		 2072 /* Support only vap for now */
2073
2074 if (sc->sc_nvaps)
2075 return -ENOBUFS;
2076
2077 switch (conf->type) {
05c914fe 2078 case NL80211_IFTYPE_STATION:
d97809db 2079 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2080 break;
05c914fe 2081 case NL80211_IFTYPE_ADHOC:
d97809db 2082 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2083 break;
05c914fe 2084 case NL80211_IFTYPE_AP:
d97809db 2085 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2086 break;
2087 default:
2088 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2089 "Interface type %d not yet supported\n", conf->type);
8feceb67 2090 return -EOPNOTSUPP;
f078f209
LR		 2091 }
2092
04bd4638 2093 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2094
5640b08e
S		 2095 /* Set the VAP opmode */
2096 avp->av_opmode = ic_opmode;
2097 avp->av_bslot = -1;
2098
d97809db 2099 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2100 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2101
2102 sc->sc_vaps[0] = conf->vif;
2103 sc->sc_nvaps++;
2104
2105 /* Set the device opmode */
2106 sc->sc_ah->ah_opmode = ic_opmode;
2107
4e30ffa2
VN		 2108 /*
2109 * Enable MIB interrupts when there are hardware phy counters.
2110 * Note we only do this (at the moment) for station mode.
2111 */
2112 if (ath9k_hw_phycounters(sc->sc_ah) &&
2113 ((conf->type == NL80211_IFTYPE_STATION) ||
2114 (conf->type == NL80211_IFTYPE_ADHOC)))
2115 sc->sc_imask |= ATH9K_INT_MIB;
2116 /*
2117 * Some hardware processes the TIM IE and fires an
2118 * interrupt when the TIM bit is set. For hardware
2119 * that does, if not overridden by configuration,
2120 * enable the TIM interrupt when operating as station.
2121 */
2122 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2123 (conf->type == NL80211_IFTYPE_STATION) &&
2124 !sc->sc_config.swBeaconProcess)
2125 sc->sc_imask |= ATH9K_INT_TIM;
2126
2127 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2128
6f255425
LR		 2129 if (conf->type == NL80211_IFTYPE_AP) {
2130 /* TODO: is this a suitable place to start ANI for AP mode? */
2131 /* Start ANI */
2132 mod_timer(&sc->sc_ani.timer,
2133 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2134 }
2135
8feceb67 2136 return 0;
f078f209
LR		 2137}
2138
8feceb67
VT		 2139static void ath9k_remove_interface(struct ieee80211_hw *hw,
2140 struct ieee80211_if_init_conf *conf)
f078f209 2141{
8feceb67 2142 struct ath_softc *sc = hw->priv;
5640b08e 2143 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2144
04bd4638 2145 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2146
6f255425
LR		 2147 /* Stop ANI */
2148 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2149
8feceb67 2150 /* Reclaim beacon resources */
d97809db
CM		 2151 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2152 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2153 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2154 ath_beacon_return(sc, avp);
580f0b8a 2155 }
f078f209 2156
8feceb67 2157 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2158
5640b08e
S		 2159 sc->sc_vaps[0] = NULL;
2160 sc->sc_nvaps--;
f078f209
LR		 2161}
2162
e8975581 2163static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2164{
8feceb67 2165 struct ath_softc *sc = hw->priv;
e8975581 2166 struct ieee80211_conf *conf = &hw->conf;
f078f209 2167
aa33de09 2168 mutex_lock(&sc->mutex);
3cbb5dd7
VN		 2169 if (changed & IEEE80211_CONF_CHANGE_PS) {
2170 if (conf->flags & IEEE80211_CONF_PS) {
2171 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2172 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2173 ath9k_hw_set_interrupts(sc->sc_ah,
2174 sc->sc_imask);
2175 }
2176 ath9k_hw_setrxabort(sc->sc_ah, 1);
2177 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2178 } else {
2179 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2180 ath9k_hw_setrxabort(sc->sc_ah, 0);
2181 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2182 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2183 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2184 ath9k_hw_set_interrupts(sc->sc_ah,
2185 sc->sc_imask);
2186 }
2187 }
2188 }
2189
4797938c 2190 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2191 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2192 int pos = curchan->hw_value;
ae5eb026 2193
04bd4638
S		 2194 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2195 curchan->center_freq);
f078f209 2196
5f8e077c
LR		 2197 /* XXX: remove me eventualy */
2198 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
e11602b7 2199
ecf70441 2200 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2201
e11602b7 2202 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2203 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2204 mutex_unlock(&sc->mutex);
e11602b7
S		 2205 return -EINVAL;
2206 }
094d05dc 2207 }
f078f209 2208
5c020dc6
LR		 2209 if (changed & IEEE80211_CONF_CHANGE_POWER)
2210 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2211
aa33de09 2212 mutex_unlock(&sc->mutex);
f078f209
LR		 2213 return 0;
2214}
2215
8feceb67
VT		 2216static int ath9k_config_interface(struct ieee80211_hw *hw,
2217 struct ieee80211_vif *vif,
2218 struct ieee80211_if_conf *conf)
c83be688 2219{
8feceb67
VT		 2220 struct ath_softc *sc = hw->priv;
2221 struct ath_hal *ah = sc->sc_ah;
5640b08e 2222 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2223 u32 rfilt = 0;
2224 int error, i;
c83be688 2225
8feceb67
VT		 2226 /* TODO: Need to decide which hw opmode to use for multi-interface
2227 * cases */
05c914fe 2228 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2229 ah->ah_opmode != NL80211_IFTYPE_AP) {
2230 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2231 ath9k_hw_setopmode(ah);
2232 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2233 /* Request full reset to get hw opmode changed properly */
2234 sc->sc_flags |= SC_OP_FULL_RESET;
2235 }
c83be688 2236
8feceb67
VT		 2237 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2238 !is_zero_ether_addr(conf->bssid)) {
2239 switch (vif->type) {
05c914fe
JB		 2240 case NL80211_IFTYPE_STATION:
2241 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2242 /* Set BSSID */
2243 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2244 sc->sc_curaid = 0;
2245 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2246 sc->sc_curaid);
c83be688 2247
8feceb67
VT		 2248 /* Set aggregation protection mode parameters */
2249 sc->sc_config.ath_aggr_prot = 0;
c83be688 2250
8feceb67 2251 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2252 "RX filter 0x%x bssid %pM aid 0x%x\n",
2253 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2254
8feceb67
VT		 2255 /* need to reconfigure the beacon */
2256 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2257
8feceb67
VT		 2258 break;
2259 default:
2260 break;
2261 }
2262 }
c83be688 2263
1f7d6cbf
S		 2264 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2265 (vif->type == NL80211_IFTYPE_AP)) {
2266 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2267 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2268 conf->enable_beacon)) {
2269 /*
2270 * Allocate and setup the beacon frame.
2271 *
2272 * Stop any previous beacon DMA. This may be
2273 * necessary, for example, when an ibss merge
2274 * causes reconfiguration; we may be called
2275 * with beacon transmission active.
2276 */
2277 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2278
1f7d6cbf
S		 2279 error = ath_beacon_alloc(sc, 0);
2280 if (error != 0)
2281 return error;
c83be688 2282
1f7d6cbf
S		 2283 ath_beacon_sync(sc, 0);
2284 }
8feceb67 2285 }
c83be688 2286
8feceb67 2287 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2288 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2289 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2290 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2291 ath9k_hw_keysetmac(sc->sc_ah,
2292 (u16)i,
2293 sc->sc_curbssid);
2294 }
c83be688 2295
8feceb67 2296 /* Only legacy IBSS for now */
05c914fe 2297 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2298 ath_update_chainmask(sc, 0);
f078f209 2299
8feceb67
VT		 2300 return 0;
2301}
f078f209 2302
8feceb67
VT		 2303#define SUPPORTED_FILTERS \
2304 (FIF_PROMISC_IN_BSS | \
2305 FIF_ALLMULTI | \
2306 FIF_CONTROL | \
2307 FIF_OTHER_BSS | \
2308 FIF_BCN_PRBRESP_PROMISC | \
2309 FIF_FCSFAIL)
c83be688 2310
8feceb67
VT		 2311/* FIXME: sc->sc_full_reset ? */
2312static void ath9k_configure_filter(struct ieee80211_hw *hw,
2313 unsigned int changed_flags,
2314 unsigned int *total_flags,
2315 int mc_count,
2316 struct dev_mc_list *mclist)
2317{
2318 struct ath_softc *sc = hw->priv;
2319 u32 rfilt;
f078f209 2320
8feceb67
VT		 2321 changed_flags &= SUPPORTED_FILTERS;
2322 *total_flags &= SUPPORTED_FILTERS;
f078f209 2323
b77f483f 2324 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2325 rfilt = ath_calcrxfilter(sc);
2326 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2327
8feceb67
VT		 2328 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2329 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2330 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2331 }
f078f209 2332
b77f483f 2333 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2334}
f078f209 2335
8feceb67
VT		 2336static void ath9k_sta_notify(struct ieee80211_hw *hw,
2337 struct ieee80211_vif *vif,
2338 enum sta_notify_cmd cmd,
17741cdc 2339 struct ieee80211_sta *sta)
8feceb67
VT		 2340{
2341 struct ath_softc *sc = hw->priv;
f078f209 2342
8feceb67
VT		 2343 switch (cmd) {
2344 case STA_NOTIFY_ADD:
5640b08e 2345 ath_node_attach(sc, sta);
8feceb67
VT		 2346 break;
2347 case STA_NOTIFY_REMOVE:
b5aa9bf9 2348 ath_node_detach(sc, sta);
8feceb67
VT		 2349 break;
2350 default:
2351 break;
2352 }
f078f209
LR		 2353}
2354
8feceb67
VT		 2355static int ath9k_conf_tx(struct ieee80211_hw *hw,
2356 u16 queue,
2357 const struct ieee80211_tx_queue_params *params)
f078f209 2358{
8feceb67
VT		 2359 struct ath_softc *sc = hw->priv;
2360 struct ath9k_tx_queue_info qi;
2361 int ret = 0, qnum;
f078f209 2362
8feceb67
VT		 2363 if (queue >= WME_NUM_AC)
2364 return 0;
f078f209 2365
8feceb67
VT		 2366 qi.tqi_aifs = params->aifs;
2367 qi.tqi_cwmin = params->cw_min;
2368 qi.tqi_cwmax = params->cw_max;
2369 qi.tqi_burstTime = params->txop;
2370 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2371
8feceb67 2372 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2373 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2374 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2375 queue, qnum, params->aifs, params->cw_min,
2376 params->cw_max, params->txop);
f078f209 2377
8feceb67
VT		 2378 ret = ath_txq_update(sc, qnum, &qi);
2379 if (ret)
04bd4638 2380 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2381
8feceb67
VT		 2382 return ret;
2383}
f078f209 2384
8feceb67
VT		 2385static int ath9k_set_key(struct ieee80211_hw *hw,
2386 enum set_key_cmd cmd,
dc822b5d
JB		 2387 struct ieee80211_vif *vif,
2388 struct ieee80211_sta *sta,
8feceb67
VT		 2389 struct ieee80211_key_conf *key)
2390{
2391 struct ath_softc *sc = hw->priv;
2392 int ret = 0;
f078f209 2393
3cbb5dd7 2394 ath9k_ps_wakeup(sc);
04bd4638 2395 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2396
8feceb67
VT		 2397 switch (cmd) {
2398 case SET_KEY:
dc822b5d 2399 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2400 if (ret >= 0) {
2401 key->hw_key_idx = ret;
8feceb67
VT		 2402 /* push IV and Michael MIC generation to stack */
2403 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2404 if (key->alg == ALG_TKIP)
2405 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2406 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2407 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2408 ret = 0;
8feceb67
VT		 2409 }
2410 break;
2411 case DISABLE_KEY:
2412 ath_key_delete(sc, key);
8feceb67
VT		 2413 break;
2414 default:
2415 ret = -EINVAL;
2416 }
f078f209 2417
3cbb5dd7 2418 ath9k_ps_restore(sc);
8feceb67
VT		 2419 return ret;
2420}
f078f209 2421
8feceb67
VT		 2422static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2423 struct ieee80211_vif *vif,
2424 struct ieee80211_bss_conf *bss_conf,
2425 u32 changed)
2426{
2427 struct ath_softc *sc = hw->priv;
f078f209 2428
8feceb67 2429 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2430 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2431 bss_conf->use_short_preamble);
2432 if (bss_conf->use_short_preamble)
2433 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2434 else
2435 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2436 }
f078f209 2437
8feceb67 2438 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2439 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2440 bss_conf->use_cts_prot);
2441 if (bss_conf->use_cts_prot &&
2442 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2443 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2444 else
2445 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2446 }
f078f209 2447
8feceb67 2448 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2449 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2450 bss_conf->assoc);
5640b08e 2451 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2452 }
2453}
f078f209 2454
8feceb67
VT		 2455static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2456{
2457 u64 tsf;
2458 struct ath_softc *sc = hw->priv;
2459 struct ath_hal *ah = sc->sc_ah;
f078f209 2460
8feceb67 2461 tsf = ath9k_hw_gettsf64(ah);
f078f209 2462
8feceb67
VT		 2463 return tsf;
2464}
f078f209 2465
3b5d665b
AF		 2466static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2467{
2468 struct ath_softc *sc = hw->priv;
2469 struct ath_hal *ah = sc->sc_ah;
2470
2471 ath9k_hw_settsf64(ah, tsf);
2472}
2473
8feceb67
VT		 2474static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2475{
2476 struct ath_softc *sc = hw->priv;
2477 struct ath_hal *ah = sc->sc_ah;
c83be688 2478
8feceb67
VT		 2479 ath9k_hw_reset_tsf(ah);
2480}
f078f209 2481
8feceb67
VT		 2482static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2483 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2484 struct ieee80211_sta *sta,
2485 u16 tid, u16 *ssn)
8feceb67
VT		 2486{
2487 struct ath_softc *sc = hw->priv;
2488 int ret = 0;
f078f209 2489
8feceb67
VT		 2490 switch (action) {
2491 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2492 if (!(sc->sc_flags & SC_OP_RXAGGR))
2493 ret = -ENOTSUPP;
8feceb67
VT		 2494 break;
2495 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2496 break;
2497 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2498 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2499 if (ret < 0)
2500 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2501 "Unable to start TX aggregation\n");
8feceb67 2502 else
17741cdc 2503 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2504 break;
2505 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2506 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2507 if (ret < 0)
2508 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2509 "Unable to stop TX aggregation\n");
f078f209 2510
17741cdc 2511 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2512 break;
8469cdef
S		 2513 case IEEE80211_AMPDU_TX_RESUME:
2514 ath_tx_aggr_resume(sc, sta, tid);
2515 break;
8feceb67 2516 default:
04bd4638 2517 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2518 }
2519
2520 return ret;
f078f209
LR		 2521}
2522
6baff7f9 2523struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2524 .tx = ath9k_tx,
2525 .start = ath9k_start,
2526 .stop = ath9k_stop,
2527 .add_interface = ath9k_add_interface,
2528 .remove_interface = ath9k_remove_interface,
2529 .config = ath9k_config,
2530 .config_interface = ath9k_config_interface,
2531 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2532 .sta_notify = ath9k_sta_notify,
2533 .conf_tx = ath9k_conf_tx,
8feceb67 2534 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2535 .set_key = ath9k_set_key,
8feceb67 2536 .get_tsf = ath9k_get_tsf,
3b5d665b 2537 .set_tsf = ath9k_set_tsf,
8feceb67 2538 .reset_tsf = ath9k_reset_tsf,
4233df6b 2539 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2540};
2541
392dff83
BP		 2542static struct {
2543 u32 version;
2544 const char * name;
2545} ath_mac_bb_names[] = {
2546 { AR_SREV_VERSION_5416_PCI, "5416" },
2547 { AR_SREV_VERSION_5416_PCIE, "5418" },
2548 { AR_SREV_VERSION_9100, "9100" },
2549 { AR_SREV_VERSION_9160, "9160" },
2550 { AR_SREV_VERSION_9280, "9280" },
2551 { AR_SREV_VERSION_9285, "9285" }
2552};
2553
2554static struct {
2555 u16 version;
2556 const char * name;
2557} ath_rf_names[] = {
2558 { 0, "5133" },
2559 { AR_RAD5133_SREV_MAJOR, "5133" },
2560 { AR_RAD5122_SREV_MAJOR, "5122" },
2561 { AR_RAD2133_SREV_MAJOR, "2133" },
2562 { AR_RAD2122_SREV_MAJOR, "2122" }
2563};
2564
2565/*
2566 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2567 */
6baff7f9 2568const char *
392dff83
BP		 2569ath_mac_bb_name(u32 mac_bb_version)
2570{
2571 int i;
2572
2573 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2574 if (ath_mac_bb_names[i].version == mac_bb_version) {
2575 return ath_mac_bb_names[i].name;
2576 }
2577 }
2578
2579 return "????";
2580}
2581
2582/*
2583 * Return the RF name. "????" is returned if the RF is unknown.
2584 */
6baff7f9 2585const char *
392dff83
BP		 2586ath_rf_name(u16 rf_version)
2587{
2588 int i;
2589
2590 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2591 if (ath_rf_names[i].version == rf_version) {
2592 return ath_rf_names[i].name;
2593 }
2594 }
2595
2596 return "????";
2597}
2598
6baff7f9 2599static int __init ath9k_init(void)
f078f209 2600{
ca8a8560
VT		 2601 int error;
2602
ca8a8560
VT		 2603 /* Register rate control algorithm */
2604 error = ath_rate_control_register();
2605 if (error != 0) {
2606 printk(KERN_ERR
b51bb3cd
LR		 2607 "ath9k: Unable to register rate control "
2608 "algorithm: %d\n",
ca8a8560 2609 error);
6baff7f9 2610 goto err_out;
ca8a8560
VT		 2611 }
2612
6baff7f9
GJ		 2613 error = ath_pci_init();
2614 if (error < 0) {
f078f209 2615 printk(KERN_ERR
b51bb3cd 2616 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2617 error = -ENODEV;
2618 goto err_rate_unregister;
f078f209
LR		 2619 }
2620
09329d37
GJ		 2621 error = ath_ahb_init();
2622 if (error < 0) {
2623 error = -ENODEV;
2624 goto err_pci_exit;
2625 }
2626
f078f209 2627 return 0;
6baff7f9 2628
09329d37
GJ		 2629 err_pci_exit:
2630 ath_pci_exit();
2631
6baff7f9
GJ		 2632 err_rate_unregister:
2633 ath_rate_control_unregister();
2634 err_out:
2635 return error;
f078f209 2636}
6baff7f9 2637module_init(ath9k_init);
f078f209 2638
6baff7f9 2639static void __exit ath9k_exit(void)
f078f209 2640{
09329d37 2641 ath_ahb_exit();
6baff7f9 2642 ath_pci_exit();
ca8a8560 2643 ath_rate_control_unregister();
04bd4638 2644 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2645}
6baff7f9 2646module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)