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mac80211: unify and fix TX aggregation start
[linux-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
38 .max_power = 30, \
39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 30, \
46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
192 struct ath_rate_table *rate_table = NULL;
193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
ff37e337
S		 234/*
235 * Set/change channels. If the channel is really being changed, it's done
236 * by reseting the chip. To accomplish this we must first cleanup any pending
237 * DMA, then restart stuff.
238*/
0e2dedf9
JM		 239int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
240 struct ath9k_channel *hchan)
ff37e337 241{
cbe61d8a 242 struct ath_hw *ah = sc->sc_ah;
ff37e337 243 bool fastcc = true, stopped;
ae8d2858
LR		 244 struct ieee80211_channel *channel = hw->conf.channel;
245 int r;
ff37e337
S		 246
247 if (sc->sc_flags & SC_OP_INVALID)
248 return -EIO;
249
3cbb5dd7
VN		 250 ath9k_ps_wakeup(sc);
251
c0d7c7af
LR		 252 /*
253 * This is only performed if the channel settings have
254 * actually changed.
255 *
256 * To switch channels clear any pending DMA operations;
257 * wait long enough for the RX fifo to drain, reset the
258 * hardware at the new frequency, and then re-enable
259 * the relevant bits of the h/w.
260 */
261 ath9k_hw_set_interrupts(ah, 0);
043a0405 262 ath_drain_all_txq(sc, false);
c0d7c7af 263 stopped = ath_stoprecv(sc);
ff37e337 264
c0d7c7af
LR		 265 /* XXX: do not flush receive queue here. We don't want
266 * to flush data frames already in queue because of
267 * changing channel. */
ff37e337 268
c0d7c7af
LR		 269 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
270 fastcc = false;
271
272 DPRINTF(sc, ATH_DBG_CONFIG,
273 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 274 sc->sc_ah->curchan->channel,
c0d7c7af 275 channel->center_freq, sc->tx_chan_width);
ff37e337 276
c0d7c7af
LR		 277 spin_lock_bh(&sc->sc_resetlock);
278
279 r = ath9k_hw_reset(ah, hchan, fastcc);
280 if (r) {
281 DPRINTF(sc, ATH_DBG_FATAL,
282 "Unable to reset channel (%u Mhz) "
283 "reset status %u\n",
284 channel->center_freq, r);
285 spin_unlock_bh(&sc->sc_resetlock);
286 return r;
ff37e337 287 }
c0d7c7af
LR		 288 spin_unlock_bh(&sc->sc_resetlock);
289
290 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
291 sc->sc_flags &= ~SC_OP_FULL_RESET;
292
293 if (ath_startrecv(sc) != 0) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to restart recv logic\n");
296 return -EIO;
297 }
298
299 ath_cache_conf_rate(sc, &hw->conf);
300 ath_update_txpow(sc);
17d7904d 301 ath9k_hw_set_interrupts(ah, sc->imask);
3cbb5dd7 302 ath9k_ps_restore(sc);
ff37e337
S		 303 return 0;
304}
305
306/*
307 * This routine performs the periodic noise floor calibration function
308 * that is used to adjust and optimize the chip performance. This
309 * takes environmental changes (location, temperature) into account.
310 * When the task is complete, it reschedules itself depending on the
311 * appropriate interval that was calculated.
312 */
313static void ath_ani_calibrate(unsigned long data)
314{
20977d3e
S		 315 struct ath_softc *sc = (struct ath_softc *)data;
316 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 317 bool longcal = false;
318 bool shortcal = false;
319 bool aniflag = false;
320 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 321 u32 cal_interval, short_cal_interval;
ff37e337 322
20977d3e
S		 323 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
324 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 325
326 /*
327 * don't calibrate when we're scanning.
328 * we are most likely not on our home channel.
329 */
0c98de65 330 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 331 goto set_timer;
ff37e337
S		 332
333 /* Long calibration runs independently of short calibration. */
17d7904d 334 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 335 longcal = true;
04bd4638 336 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 337 sc->ani.longcal_timer = timestamp;
ff37e337
S		 338 }
339
17d7904d
S		 340 /* Short calibration applies only while caldone is false */
341 if (!sc->ani.caldone) {
20977d3e 342 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 343 shortcal = true;
04bd4638 344 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 345 sc->ani.shortcal_timer = timestamp;
346 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 347 }
348 } else {
17d7904d 349 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 350 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 351 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
352 if (sc->ani.caldone)
353 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 354 }
355 }
356
357 /* Verify whether we must check ANI */
20977d3e 358 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 359 aniflag = true;
17d7904d 360 sc->ani.checkani_timer = timestamp;
ff37e337
S		 361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
20977d3e 367 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 368
369 /* Perform calibration if necessary */
370 if (longcal || shortcal) {
371 bool iscaldone = false;
372
2660b81a 373 if (ath9k_hw_calibrate(ah, ah->curchan,
17d7904d 374 sc->rx_chainmask, longcal,
ff37e337
S		 375 &iscaldone)) {
376 if (longcal)
17d7904d 377 sc->ani.noise_floor =
ff37e337 378 ath9k_hw_getchan_noise(ah,
2660b81a 379 ah->curchan);
ff37e337
S		 380
381 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 382 "calibrate chan %u/%x nf: %d\n",
2660b81a
S		 383 ah->curchan->channel,
384 ah->curchan->channelFlags,
17d7904d 385 sc->ani.noise_floor);
ff37e337
S		 386 } else {
387 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 388 "calibrate chan %u/%x failed\n",
2660b81a
S		 389 ah->curchan->channel,
390 ah->curchan->channelFlags);
ff37e337 391 }
17d7904d 392 sc->ani.caldone = iscaldone;
ff37e337
S		 393 }
394 }
395
20977d3e 396set_timer:
ff37e337
S		 397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e 402 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 403 if (sc->sc_ah->config.enable_ani)
aac9207e 404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 405 if (!sc->ani.caldone)
20977d3e 406 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 407
17d7904d 408 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337 416 */
0e2dedf9 417void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337
S		 418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9 420 if (is_ht ||
2660b81a
S		 421 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
422 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
423 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 424 } else {
17d7904d
S		 425 sc->tx_chainmask = 1;
426 sc->rx_chainmask = 1;
ff37e337
S		 427 }
428
04bd4638 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 430 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 458 u32 status = sc->intrstatus;
ff37e337
S		 459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
17d7904d 478 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337
S		 479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
cbe61d8a 484 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
17d7904d 509 status &= sc->imask; /* discard unasked-for bits */
ff37e337
S		 510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
17d7904d 518 sc->intrstatus = status;
541d8dd5 519 ath9k_ps_wakeup(sc);
ff37e337
S		 520
521 if (status & ATH9K_INT_FATAL) {
522 /* need a chip reset */
523 sched = true;
524 } else if (status & ATH9K_INT_RXORN) {
525 /* need a chip reset */
526 sched = true;
527 } else {
528 if (status & ATH9K_INT_SWBA) {
529 /* schedule a tasklet for beacon handling */
530 tasklet_schedule(&sc->bcon_tasklet);
531 }
532 if (status & ATH9K_INT_RXEOL) {
533 /*
534 * NB: the hardware should re-read the link when
535 * RXE bit is written, but it doesn't work
536 * at least on older hardware revs.
537 */
538 sched = true;
539 }
540
541 if (status & ATH9K_INT_TXURN)
542 /* bump tx trigger level */
543 ath9k_hw_updatetxtriglevel(ah, true);
544 /* XXX: optimize this */
545 if (status & ATH9K_INT_RX)
546 sched = true;
547 if (status & ATH9K_INT_TX)
548 sched = true;
549 if (status & ATH9K_INT_BMISS)
550 sched = true;
551 /* carrier sense timeout */
552 if (status & ATH9K_INT_CST)
553 sched = true;
554 if (status & ATH9K_INT_MIB) {
555 /*
556 * Disable interrupts until we service the MIB
557 * interrupt; otherwise it will continue to
558 * fire.
559 */
560 ath9k_hw_set_interrupts(ah, 0);
561 /*
562 * Let the hal handle the event. We assume
563 * it will clear whatever condition caused
564 * the interrupt.
565 */
17d7904d
S		 566 ath9k_hw_procmibevent(ah, &sc->nodestats);
567 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 568 }
569 if (status & ATH9K_INT_TIM_TIMER) {
2660b81a 570 if (!(ah->caps.hw_caps &
ff37e337
S		 571 ATH9K_HW_CAP_AUTOSLEEP)) {
572 /* Clear RxAbort bit so that we can
573 * receive frames */
3cbb5dd7 574 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 575 ath9k_hw_setrxabort(ah, 0);
576 sched = true;
3cbb5dd7 577 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 578 }
579 }
4af9cf4f
S		 580 if (status & ATH9K_INT_TSFOOR) {
581 /* FIXME: Handle this interrupt for power save */
582 sched = true;
583 }
ff37e337 584 }
541d8dd5 585 ath9k_ps_restore(sc);
ff37e337
S		 586 } while (0);
587
817e11de
S		 588 ath_debug_stat_interrupt(sc, status);
589
ff37e337
S		 590 if (sched) {
591 /* turn off every interrupt except SWBA */
17d7904d 592 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 593 tasklet_schedule(&sc->intr_tq);
594 }
595
596 return IRQ_HANDLED;
597}
598
f078f209 599static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 600 struct ieee80211_channel *chan,
094d05dc 601 enum nl80211_channel_type channel_type)
f078f209
LR		 602{
603 u32 chanmode = 0;
f078f209
LR		 604
605 switch (chan->band) {
606 case IEEE80211_BAND_2GHZ:
094d05dc
S		 607 switch(channel_type) {
608 case NL80211_CHAN_NO_HT:
609 case NL80211_CHAN_HT20:
f078f209 610 chanmode = CHANNEL_G_HT20;
094d05dc
S		 611 break;
612 case NL80211_CHAN_HT40PLUS:
f078f209 613 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 614 break;
615 case NL80211_CHAN_HT40MINUS:
f078f209 616 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 617 break;
618 }
f078f209
LR		 619 break;
620 case IEEE80211_BAND_5GHZ:
094d05dc
S		 621 switch(channel_type) {
622 case NL80211_CHAN_NO_HT:
623 case NL80211_CHAN_HT20:
f078f209 624 chanmode = CHANNEL_A_HT20;
094d05dc
S		 625 break;
626 case NL80211_CHAN_HT40PLUS:
f078f209 627 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 628 break;
629 case NL80211_CHAN_HT40MINUS:
f078f209 630 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 631 break;
632 }
f078f209
LR		 633 break;
634 default:
635 break;
636 }
637
638 return chanmode;
639}
640
6ace2891 641static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 642 struct ath9k_keyval *hk, const u8 *addr,
643 bool authenticator)
f078f209 644{
6ace2891
JM		 645 const u8 *key_rxmic;
646 const u8 *key_txmic;
f078f209 647
6ace2891
JM		 648 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
649 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 650
651 if (addr == NULL) {
d216aaa6
JM		 652 /*
653 * Group key installation - only two key cache entries are used
654 * regardless of splitmic capability since group key is only
655 * used either for TX or RX.
656 */
3f53dd64
JM		 657 if (authenticator) {
658 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
659 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
660 } else {
661 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
662 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
663 }
d216aaa6 664 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 665 }
17d7904d 666 if (!sc->splitmic) {
d216aaa6 667 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 670 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 671 }
d216aaa6
JM		 672
673 /* Separate key cache entries for TX and RX */
674
675 /* TX key goes at first index, RX key at +32. */
f078f209 676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 677 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
678 /* TX MIC entry failed. No need to proceed further */
f078f209 679 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 680 "Setting TX MIC Key Failed\n");
f078f209
LR		 681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
d216aaa6 686 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 687}
688
689static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690{
691 int i;
692
17d7904d
S		 693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
6ace2891 696 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706}
707
708static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709{
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 719 return i;
17d7904d
S		 720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 724 return i + 32;
17d7904d
S		 725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
ea612132 729 return i + 64;
17d7904d
S		 730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
ea612132 734 return i + 64 + 32;
6ace2891
JM		 735 }
736 } else {
17d7904d
S		 737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
6ace2891 740 return i;
17d7904d
S		 741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
17d7904d 748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
17d7904d 754 if (sc->splitmic) {
be2864cf
JM		 755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
17d7904d 761 if (!test_bit(i, sc->keymap))
6ace2891
JM		 762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
f078f209
LR		 767}
768
769static int ath_key_config(struct ath_softc *sc,
3f53dd64 770 struct ieee80211_vif *vif,
dc822b5d 771 struct ieee80211_sta *sta,
f078f209
LR		 772 struct ieee80211_key_conf *key)
773{
f078f209
LR		 774 struct ath9k_keyval hk;
775 const u8 *mac = NULL;
776 int ret = 0;
6ace2891 777 int idx;
f078f209
LR		 778
779 memset(&hk, 0, sizeof(hk));
780
781 switch (key->alg) {
782 case ALG_WEP:
783 hk.kv_type = ATH9K_CIPHER_WEP;
784 break;
785 case ALG_TKIP:
786 hk.kv_type = ATH9K_CIPHER_TKIP;
787 break;
788 case ALG_CCMP:
789 hk.kv_type = ATH9K_CIPHER_AES_CCM;
790 break;
791 default:
ca470b29 792 return -EOPNOTSUPP;
f078f209
LR		 793 }
794
6ace2891 795 hk.kv_len = key->keylen;
f078f209
LR		 796 memcpy(hk.kv_val, key->key, key->keylen);
797
6ace2891
JM		 798 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 } else if (key->keyidx) {
dc822b5d
JB		 803 if (WARN_ON(!sta))
804 return -EOPNOTSUPP;
805 mac = sta->addr;
806
6ace2891
JM		 807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
f078f209 813 } else {
dc822b5d
JB		 814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
6ace2891
JM		 818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
ca470b29 823 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 824 }
825
826 if (key->alg == ALG_TKIP)
3f53dd64
JM		 827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
828 vif->type == NL80211_IFTYPE_AP);
f078f209 829 else
d216aaa6 830 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 831
832 if (!ret)
833 return -EIO;
834
17d7904d 835 set_bit(idx, sc->keymap);
6ace2891 836 if (key->alg == ALG_TKIP) {
17d7904d
S		 837 set_bit(idx + 64, sc->keymap);
838 if (sc->splitmic) {
839 set_bit(idx + 32, sc->keymap);
840 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 841 }
842 }
843
844 return idx;
f078f209
LR		 845}
846
847static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
848{
6ace2891
JM		 849 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
850 if (key->hw_key_idx < IEEE80211_WEP_NKID)
851 return;
852
17d7904d 853 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 854 if (key->alg != ALG_TKIP)
855 return;
f078f209 856
17d7904d
S		 857 clear_bit(key->hw_key_idx + 64, sc->keymap);
858 if (sc->splitmic) {
859 clear_bit(key->hw_key_idx + 32, sc->keymap);
860 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 861 }
f078f209
LR		 862}
863
eb2599ca
S		 864static void setup_ht_cap(struct ath_softc *sc,
865 struct ieee80211_sta_ht_cap *ht_info)
f078f209 866{
60653678
S		 867#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
868#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 869
d9fe60de
JB		 870 ht_info->ht_supported = true;
871 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
872 IEEE80211_HT_CAP_SM_PS |
873 IEEE80211_HT_CAP_SGI_40 |
874 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 875
60653678
S		 876 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
877 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 878
d9fe60de
JB		 879 /* set up supported mcs set */
880 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 881
17d7904d 882 switch(sc->rx_chainmask) {
eb2599ca
S		 883 case 1:
884 ht_info->mcs.rx_mask[0] = 0xff;
885 break;
3c457265 886 case 3:
eb2599ca
S		 887 case 5:
888 case 7:
889 default:
890 ht_info->mcs.rx_mask[0] = 0xff;
891 ht_info->mcs.rx_mask[1] = 0xff;
892 break;
893 }
894
d9fe60de 895 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 896}
897
8feceb67 898static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 899 struct ieee80211_vif *vif,
8feceb67 900 struct ieee80211_bss_conf *bss_conf)
f078f209 901{
17d7904d 902 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 903
8feceb67 904 if (bss_conf->assoc) {
094d05dc 905 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 906 bss_conf->aid, sc->curbssid);
f078f209 907
8feceb67 908 /* New association, store aid */
d97809db 909 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
17d7904d 910 sc->curaid = bss_conf->aid;
ba52da58 911 ath9k_hw_write_associd(sc);
8feceb67 912 }
f078f209 913
8feceb67 914 /* Configure the beacon */
2c3db3d5 915 ath_beacon_config(sc, vif);
f078f209 916
8feceb67 917 /* Reset rssi stats */
17d7904d
S		 918 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
919 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 922
6f255425 923 /* Start ANI */
17d7904d 924 mod_timer(&sc->ani.timer,
20977d3e 925 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
8feceb67 926 } else {
04bd4638 927 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
17d7904d 928 sc->curaid = 0;
f078f209 929 }
8feceb67 930}
f078f209 931
8feceb67
VT		 932/********************************/
933/* LED functions */
934/********************************/
f078f209 935
f2bffa7e
VT		 936static void ath_led_blink_work(struct work_struct *work)
937{
938 struct ath_softc *sc = container_of(work, struct ath_softc,
939 ath_led_blink_work.work);
940
941 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
942 return;
85067c06
VT		 943
944 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
945 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
947 else
948 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
949 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 950
951 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
952 (sc->sc_flags & SC_OP_LED_ON) ?
953 msecs_to_jiffies(sc->led_off_duration) :
954 msecs_to_jiffies(sc->led_on_duration));
955
85067c06
VT		 956 sc->led_on_duration = sc->led_on_cnt ?
957 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
958 ATH_LED_ON_DURATION_IDLE;
959 sc->led_off_duration = sc->led_off_cnt ?
960 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
961 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 962 sc->led_on_cnt = sc->led_off_cnt = 0;
963 if (sc->sc_flags & SC_OP_LED_ON)
964 sc->sc_flags &= ~SC_OP_LED_ON;
965 else
966 sc->sc_flags |= SC_OP_LED_ON;
967}
968
8feceb67
VT		 969static void ath_led_brightness(struct led_classdev *led_cdev,
970 enum led_brightness brightness)
971{
972 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
973 struct ath_softc *sc = led->sc;
f078f209 974
8feceb67
VT		 975 switch (brightness) {
976 case LED_OFF:
977 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 978 led->led_type == ATH_LED_RADIO) {
979 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
980 (led->led_type == ATH_LED_RADIO));
8feceb67 981 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 982 if (led->led_type == ATH_LED_RADIO)
983 sc->sc_flags &= ~SC_OP_LED_ON;
984 } else {
985 sc->led_off_cnt++;
986 }
8feceb67
VT		 987 break;
988 case LED_FULL:
f2bffa7e 989 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 990 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 991 queue_delayed_work(sc->hw->workqueue,
992 &sc->ath_led_blink_work, 0);
993 } else if (led->led_type == ATH_LED_RADIO) {
994 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
995 sc->sc_flags |= SC_OP_LED_ON;
996 } else {
997 sc->led_on_cnt++;
998 }
8feceb67
VT		 999 break;
1000 default:
1001 break;
f078f209 1002 }
8feceb67 1003}
f078f209 1004
8feceb67
VT		 1005static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1006 char *trigger)
1007{
1008 int ret;
f078f209 1009
8feceb67
VT		 1010 led->sc = sc;
1011 led->led_cdev.name = led->name;
1012 led->led_cdev.default_trigger = trigger;
1013 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1014
8feceb67
VT		 1015 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1016 if (ret)
1017 DPRINTF(sc, ATH_DBG_FATAL,
1018 "Failed to register led:%s", led->name);
1019 else
1020 led->registered = 1;
1021 return ret;
1022}
f078f209 1023
8feceb67
VT		 1024static void ath_unregister_led(struct ath_led *led)
1025{
1026 if (led->registered) {
1027 led_classdev_unregister(&led->led_cdev);
1028 led->registered = 0;
f078f209 1029 }
f078f209
LR		 1030}
1031
8feceb67 1032static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1033{
f2bffa7e 1034 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1035 ath_unregister_led(&sc->assoc_led);
1036 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1037 ath_unregister_led(&sc->tx_led);
1038 ath_unregister_led(&sc->rx_led);
1039 ath_unregister_led(&sc->radio_led);
1040 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1041}
f078f209 1042
8feceb67
VT		 1043static void ath_init_leds(struct ath_softc *sc)
1044{
1045 char *trigger;
1046 int ret;
f078f209 1047
8feceb67
VT		 1048 /* Configure gpio 1 for output */
1049 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1050 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1051 /* LED off, active low */
1052 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1053
f2bffa7e
VT		 1054 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1055
8feceb67
VT		 1056 trigger = ieee80211_get_radio_led_name(sc->hw);
1057 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1058 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1059 ret = ath_register_led(sc, &sc->radio_led, trigger);
1060 sc->radio_led.led_type = ATH_LED_RADIO;
1061 if (ret)
1062 goto fail;
7dcfdcd9 1063
8feceb67
VT		 1064 trigger = ieee80211_get_assoc_led_name(sc->hw);
1065 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1066 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1067 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1068 sc->assoc_led.led_type = ATH_LED_ASSOC;
1069 if (ret)
1070 goto fail;
f078f209 1071
8feceb67
VT		 1072 trigger = ieee80211_get_tx_led_name(sc->hw);
1073 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1074 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1075 ret = ath_register_led(sc, &sc->tx_led, trigger);
1076 sc->tx_led.led_type = ATH_LED_TX;
1077 if (ret)
1078 goto fail;
f078f209 1079
8feceb67
VT		 1080 trigger = ieee80211_get_rx_led_name(sc->hw);
1081 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1082 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1083 ret = ath_register_led(sc, &sc->rx_led, trigger);
1084 sc->rx_led.led_type = ATH_LED_RX;
1085 if (ret)
1086 goto fail;
f078f209 1087
8feceb67
VT		 1088 return;
1089
1090fail:
1091 ath_deinit_leds(sc);
f078f209
LR		 1092}
1093
7ec3e514 1094void ath_radio_enable(struct ath_softc *sc)
500c064d 1095{
cbe61d8a 1096 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1097 struct ieee80211_channel *channel = sc->hw->conf.channel;
1098 int r;
500c064d 1099
3cbb5dd7 1100 ath9k_ps_wakeup(sc);
500c064d 1101 spin_lock_bh(&sc->sc_resetlock);
ae8d2858 1102
2660b81a 1103 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858
LR		 1104
1105 if (r) {
500c064d 1106 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1107 "Unable to reset channel %u (%uMhz) ",
1108 "reset status %u\n",
1109 channel->center_freq, r);
500c064d
VT		 1110 }
1111 spin_unlock_bh(&sc->sc_resetlock);
1112
1113 ath_update_txpow(sc);
1114 if (ath_startrecv(sc) != 0) {
1115 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1116 "Unable to restart recv logic\n");
500c064d
VT		 1117 return;
1118 }
1119
1120 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1121 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1122
1123 /* Re-Enable interrupts */
17d7904d 1124 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1125
1126 /* Enable LED */
1127 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1128 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1129 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1130
1131 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1132 ath9k_ps_restore(sc);
500c064d
VT		 1133}
1134
7ec3e514 1135void ath_radio_disable(struct ath_softc *sc)
500c064d 1136{
cbe61d8a 1137 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1138 struct ieee80211_channel *channel = sc->hw->conf.channel;
1139 int r;
500c064d 1140
3cbb5dd7 1141 ath9k_ps_wakeup(sc);
500c064d
VT		 1142 ieee80211_stop_queues(sc->hw);
1143
1144 /* Disable LED */
1145 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1146 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1147
1148 /* Disable interrupts */
1149 ath9k_hw_set_interrupts(ah, 0);
1150
043a0405 1151 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1152 ath_stoprecv(sc); /* turn off frame recv */
1153 ath_flushrecv(sc); /* flush recv queue */
1154
1155 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1156 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1157 if (r) {
500c064d 1158 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1159 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1160 "reset status %u\n",
1161 channel->center_freq, r);
500c064d
VT		 1162 }
1163 spin_unlock_bh(&sc->sc_resetlock);
1164
1165 ath9k_hw_phy_disable(ah);
1166 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1167 ath9k_ps_restore(sc);
500c064d
VT		 1168}
1169
5077fd35
GJ		 1170#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1171
1172/*******************/
1173/* Rfkill */
1174/*******************/
1175
500c064d
VT		 1176static bool ath_is_rfkill_set(struct ath_softc *sc)
1177{
cbe61d8a 1178 struct ath_hw *ah = sc->sc_ah;
500c064d 1179
2660b81a
S		 1180 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1181 ah->rfkill_polarity;
500c064d
VT		 1182}
1183
1184/* h/w rfkill poll function */
1185static void ath_rfkill_poll(struct work_struct *work)
1186{
1187 struct ath_softc *sc = container_of(work, struct ath_softc,
1188 rf_kill.rfkill_poll.work);
1189 bool radio_on;
1190
1191 if (sc->sc_flags & SC_OP_INVALID)
1192 return;
1193
1194 radio_on = !ath_is_rfkill_set(sc);
1195
1196 /*
1197 * enable/disable radio only when there is a
1198 * state change in RF switch
1199 */
1200 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1201 enum rfkill_state state;
1202
1203 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1204 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1205 : RFKILL_STATE_HARD_BLOCKED;
1206 } else if (radio_on) {
1207 ath_radio_enable(sc);
1208 state = RFKILL_STATE_UNBLOCKED;
1209 } else {
1210 ath_radio_disable(sc);
1211 state = RFKILL_STATE_HARD_BLOCKED;
1212 }
1213
1214 if (state == RFKILL_STATE_HARD_BLOCKED)
1215 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1216 else
1217 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1218
1219 rfkill_force_state(sc->rf_kill.rfkill, state);
1220 }
1221
1222 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1223 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1224}
1225
1226/* s/w rfkill handler */
1227static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1228{
1229 struct ath_softc *sc = data;
1230
1231 switch (state) {
1232 case RFKILL_STATE_SOFT_BLOCKED:
1233 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1234 SC_OP_RFKILL_SW_BLOCKED)))
1235 ath_radio_disable(sc);
1236 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1237 return 0;
1238 case RFKILL_STATE_UNBLOCKED:
1239 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1240 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1241 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1242 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1243 "radio as it is disabled by h/w\n");
500c064d
VT		 1244 return -EPERM;
1245 }
1246 ath_radio_enable(sc);
1247 }
1248 return 0;
1249 default:
1250 return -EINVAL;
1251 }
1252}
1253
1254/* Init s/w rfkill */
1255static int ath_init_sw_rfkill(struct ath_softc *sc)
1256{
1257 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1258 RFKILL_TYPE_WLAN);
1259 if (!sc->rf_kill.rfkill) {
1260 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1261 return -ENOMEM;
1262 }
1263
1264 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
0818cb8a 1265 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
500c064d
VT		 1266 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1267 sc->rf_kill.rfkill->data = sc;
1268 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1269 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1270 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1271
1272 return 0;
1273}
1274
1275/* Deinitialize rfkill */
1276static void ath_deinit_rfkill(struct ath_softc *sc)
1277{
2660b81a 1278 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1279 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1280
1281 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1282 rfkill_unregister(sc->rf_kill.rfkill);
1283 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1284 sc->rf_kill.rfkill = NULL;
1285 }
1286}
9c84b797
S		 1287
1288static int ath_start_rfkill_poll(struct ath_softc *sc)
1289{
2660b81a 1290 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
9c84b797
S		 1291 queue_delayed_work(sc->hw->workqueue,
1292 &sc->rf_kill.rfkill_poll, 0);
1293
1294 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1295 if (rfkill_register(sc->rf_kill.rfkill)) {
1296 DPRINTF(sc, ATH_DBG_FATAL,
1297 "Unable to register rfkill\n");
1298 rfkill_free(sc->rf_kill.rfkill);
1299
1300 /* Deinitialize the device */
39c3c2f2 1301 ath_cleanup(sc);
9c84b797
S		 1302 return -EIO;
1303 } else {
1304 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1305 }
1306 }
1307
1308 return 0;
1309}
500c064d
VT		 1310#endif /* CONFIG_RFKILL */
1311
6baff7f9 1312void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1313{
1314 ath_detach(sc);
1315 free_irq(sc->irq, sc);
1316 ath_bus_cleanup(sc);
c52f33d0 1317 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1318 ieee80211_free_hw(sc->hw);
1319}
1320
6baff7f9 1321void ath_detach(struct ath_softc *sc)
f078f209 1322{
8feceb67 1323 struct ieee80211_hw *hw = sc->hw;
9c84b797 1324 int i = 0;
f078f209 1325
3cbb5dd7
VN		 1326 ath9k_ps_wakeup(sc);
1327
04bd4638 1328 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1329
e97275cb 1330#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1331 ath_deinit_rfkill(sc);
1332#endif
3fcdfb4b 1333 ath_deinit_leds(sc);
0e2dedf9 1334 cancel_work_sync(&sc->chan_work);
f98c3bd2 1335 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1336
c52f33d0
JM		 1337 for (i = 0; i < sc->num_sec_wiphy; i++) {
1338 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1339 if (aphy == NULL)
1340 continue;
1341 sc->sec_wiphy[i] = NULL;
1342 ieee80211_unregister_hw(aphy->hw);
1343 ieee80211_free_hw(aphy->hw);
1344 }
3fcdfb4b 1345 ieee80211_unregister_hw(hw);
8feceb67
VT		 1346 ath_rx_cleanup(sc);
1347 ath_tx_cleanup(sc);
f078f209 1348
9c84b797
S		 1349 tasklet_kill(&sc->intr_tq);
1350 tasklet_kill(&sc->bcon_tasklet);
f078f209 1351
9c84b797
S		 1352 if (!(sc->sc_flags & SC_OP_INVALID))
1353 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1354
9c84b797
S		 1355 /* cleanup tx queues */
1356 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1357 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1358 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1359
1360 ath9k_hw_detach(sc->sc_ah);
826d2680 1361 ath9k_exit_debug(sc);
3cbb5dd7 1362 ath9k_ps_restore(sc);
f078f209
LR		 1363}
1364
ff37e337
S		 1365static int ath_init(u16 devid, struct ath_softc *sc)
1366{
cbe61d8a 1367 struct ath_hw *ah = NULL;
ff37e337
S		 1368 int status;
1369 int error = 0, i;
1370 int csz = 0;
1371
1372 /* XXX: hardware will not be ready until ath_open() being called */
1373 sc->sc_flags |= SC_OP_INVALID;
88b126af 1374
826d2680
S		 1375 if (ath9k_init_debug(sc) < 0)
1376 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1377
c52f33d0 1378 spin_lock_init(&sc->wiphy_lock);
ff37e337 1379 spin_lock_init(&sc->sc_resetlock);
6158425b 1380 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1381 mutex_init(&sc->mutex);
ff37e337 1382 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1383 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1384 (unsigned long)sc);
1385
1386 /*
1387 * Cache line size is used to size and align various
1388 * structures used to communicate with the hardware.
1389 */
88d15707 1390 ath_read_cachesize(sc, &csz);
ff37e337 1391 /* XXX assert csz is non-zero */
17d7904d 1392 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1393
cbe61d8a 1394 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1395 if (ah == NULL) {
1396 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1397 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1398 error = -ENXIO;
1399 goto bad;
1400 }
1401 sc->sc_ah = ah;
1402
1403 /* Get the hardware key cache size. */
2660b81a 1404 sc->keymax = ah->caps.keycache_size;
17d7904d 1405 if (sc->keymax > ATH_KEYMAX) {
ff37e337 1406 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 1407 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1408 ATH_KEYMAX, sc->keymax);
1409 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1410 }
1411
1412 /*
1413 * Reset the key cache since some parts do not
1414 * reset the contents on initial power up.
1415 */
17d7904d 1416 for (i = 0; i < sc->keymax; i++)
ff37e337 1417 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1418
5f8e077c 1419 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1420 goto bad;
1421
1422 /* default to MONITOR mode */
2660b81a 1423 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1424
ff37e337
S		 1425 /* Setup rate tables */
1426
1427 ath_rate_attach(sc);
1428 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1429 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1430
1431 /*
1432 * Allocate hardware transmit queues: one queue for
1433 * beacon frames and one data queue for each QoS
1434 * priority. Note that the hal handles reseting
1435 * these queues at the needed time.
1436 */
b77f483f
S		 1437 sc->beacon.beaconq = ath_beaconq_setup(ah);
1438 if (sc->beacon.beaconq == -1) {
ff37e337 1439 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1440 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1441 error = -EIO;
1442 goto bad2;
1443 }
b77f483f
S		 1444 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1445 if (sc->beacon.cabq == NULL) {
ff37e337 1446 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1447 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1448 error = -EIO;
1449 goto bad2;
1450 }
1451
17d7904d 1452 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1453 ath_cabq_update(sc);
1454
b77f483f
S		 1455 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1456 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1457
1458 /* Setup data queues */
1459 /* NB: ensure BK queue is the lowest priority h/w queue */
1460 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1461 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1462 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1463 error = -EIO;
1464 goto bad2;
1465 }
1466
1467 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1468 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1469 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1470 error = -EIO;
1471 goto bad2;
1472 }
1473 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1474 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1475 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1476 error = -EIO;
1477 goto bad2;
1478 }
1479 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1480 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1481 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1482 error = -EIO;
1483 goto bad2;
1484 }
1485
1486 /* Initializes the noise floor to a reasonable default value.
1487 * Later on this will be updated during ANI processing. */
1488
17d7904d
S		 1489 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1490 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1491
1492 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493 ATH9K_CIPHER_TKIP, NULL)) {
1494 /*
1495 * Whether we should enable h/w TKIP MIC.
1496 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1497 * report WMM capable, so it's always safe to turn on
1498 * TKIP MIC in this case.
1499 */
1500 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1501 0, 1, NULL);
1502 }
1503
1504 /*
1505 * Check whether the separate key cache entries
1506 * are required to handle both tx+rx MIC keys.
1507 * With split mic keys the number of stations is limited
1508 * to 27 otherwise 59.
1509 */
1510 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1511 ATH9K_CIPHER_TKIP, NULL)
1512 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1513 ATH9K_CIPHER_MIC, NULL)
1514 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1515 0, NULL))
17d7904d 1516 sc->splitmic = 1;
ff37e337
S		 1517
1518 /* turn on mcast key search if possible */
1519 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1520 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1521 1, NULL);
1522
17d7904d 1523 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1524
1525 /* 11n Capabilities */
2660b81a 1526 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1527 sc->sc_flags |= SC_OP_TXAGGR;
1528 sc->sc_flags |= SC_OP_RXAGGR;
1529 }
1530
2660b81a
S		 1531 sc->tx_chainmask = ah->caps.tx_chainmask;
1532 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1533
1534 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1535 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1536
8ca21f01 1537 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1538 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1539
b77f483f 1540 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1541
1542 /* initialize beacon slots */
c52f33d0 1543 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1544 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1545 sc->beacon.bslot_aphy[i] = NULL;
1546 }
ff37e337
S		 1547
1548 /* save MISC configurations */
17d7904d 1549 sc->config.swBeaconProcess = 1;
ff37e337 1550
ff37e337
S		 1551 /* setup channels and rates */
1552
5f8e077c 1553 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1554 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1555 sc->rates[IEEE80211_BAND_2GHZ];
1556 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1557 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1558 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1559
2660b81a 1560 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1561 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1562 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1563 sc->rates[IEEE80211_BAND_5GHZ];
1564 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1565 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1566 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1567 }
1568
2660b81a 1569 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1570 ath9k_hw_btcoex_enable(sc->sc_ah);
1571
ff37e337
S		 1572 return 0;
1573bad2:
1574 /* cleanup tx queues */
1575 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1576 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1577 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1578bad:
1579 if (ah)
1580 ath9k_hw_detach(ah);
40b130a9 1581 ath9k_exit_debug(sc);
ff37e337
S		 1582
1583 return error;
1584}
1585
c52f33d0 1586void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1587{
9c84b797
S		 1588 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1589 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1590 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1591 IEEE80211_HW_AMPDU_AGGREGATION |
1592 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1593 IEEE80211_HW_PS_NULLFUNC_STACK |
1594 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1595
b3bd89ce 1596 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1597 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1598
9c84b797
S		 1599 hw->wiphy->interface_modes =
1600 BIT(NL80211_IFTYPE_AP) |
1601 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1602 BIT(NL80211_IFTYPE_ADHOC) |
1603 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1604
5f8e077c
LR		 1605 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1606 hw->wiphy->strict_regulatory = true;
1607
8feceb67 1608 hw->queues = 4;
e63835b0 1609 hw->max_rates = 4;
171387ef 1610 hw->channel_change_time = 5000;
465ca84d 1611 hw->max_listen_interval = 10;
e63835b0 1612 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1613 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1614 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1615
8feceb67 1616 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1617
c52f33d0
JM		 1618 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1619 &sc->sbands[IEEE80211_BAND_2GHZ];
1620 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1621 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1622 &sc->sbands[IEEE80211_BAND_5GHZ];
1623}
1624
1625int ath_attach(u16 devid, struct ath_softc *sc)
1626{
1627 struct ieee80211_hw *hw = sc->hw;
1628 const struct ieee80211_regdomain *regd;
1629 int error = 0, i;
1630
1631 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1632
1633 error = ath_init(devid, sc);
1634 if (error != 0)
1635 return error;
1636
1637 /* get mac address from hardware and set in mac80211 */
1638
1639 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1640
1641 ath_set_hw_capab(sc, hw);
1642
2660b81a 1643 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1644 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1645 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1646 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1647 }
1648
db93e7b5
SB		 1649 /* initialize tx/rx engine */
1650 error = ath_tx_init(sc, ATH_TXBUF);
1651 if (error != 0)
40b130a9 1652 goto error_attach;
8feceb67 1653
db93e7b5
SB		 1654 error = ath_rx_init(sc, ATH_RXBUF);
1655 if (error != 0)
40b130a9 1656 goto error_attach;
8feceb67 1657
e97275cb 1658#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d 1659 /* Initialze h/w Rfkill */
2660b81a 1660 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d
VT		 1661 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1662
1663 /* Initialize s/w rfkill */
40b130a9
VT		 1664 error = ath_init_sw_rfkill(sc);
1665 if (error)
1666 goto error_attach;
500c064d
VT		 1667#endif
1668
5f8e077c 1669 if (ath9k_is_world_regd(sc->sc_ah)) {
191a99b7 1670 /* Anything applied here (prior to wiphy registration) gets
5f8e077c 1671 * saved on the wiphy orig_* parameters */
191a99b7 1672 regd = ath9k_world_regdomain(sc->sc_ah);
5f8e077c
LR		 1673 hw->wiphy->custom_regulatory = true;
1674 hw->wiphy->strict_regulatory = false;
5f8e077c
LR		 1675 } else {
1676 /* This gets applied in the case of the absense of CRDA,
191a99b7 1677 * it's our own custom world regulatory domain, similar to
5f8e077c 1678 * cfg80211's but we enable passive scanning */
191a99b7 1679 regd = ath9k_default_world_regdomain();
5f8e077c 1680 }
191a99b7
BC		 1681 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1682 ath9k_reg_apply_radar_flags(hw->wiphy);
7db90f4a 1683 ath9k_reg_apply_world_flags(hw->wiphy, NL80211_REGDOM_SET_BY_DRIVER);
5f8e077c 1684
0e2dedf9 1685 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1686 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1687 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1688
db93e7b5 1689 error = ieee80211_register_hw(hw);
8feceb67 1690
fe33eb39
LR		 1691 if (!ath9k_is_world_regd(sc->sc_ah)) {
1692 error = regulatory_hint(hw->wiphy,
1693 sc->sc_ah->regulatory.alpha2);
1694 if (error)
1695 goto error_attach;
1696 }
5f8e077c 1697
db93e7b5
SB		 1698 /* Initialize LED control */
1699 ath_init_leds(sc);
8feceb67 1700
5f8e077c 1701
8feceb67 1702 return 0;
40b130a9
VT		 1703
1704error_attach:
1705 /* cleanup tx queues */
1706 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1707 if (ATH_TXQ_SETUP(sc, i))
1708 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1709
1710 ath9k_hw_detach(sc->sc_ah);
1711 ath9k_exit_debug(sc);
1712
8feceb67 1713 return error;
f078f209
LR		 1714}
1715
ff37e337
S		 1716int ath_reset(struct ath_softc *sc, bool retry_tx)
1717{
cbe61d8a 1718 struct ath_hw *ah = sc->sc_ah;
030bb495 1719 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1720 int r;
ff37e337
S		 1721
1722 ath9k_hw_set_interrupts(ah, 0);
043a0405 1723 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1724 ath_stoprecv(sc);
1725 ath_flushrecv(sc);
1726
1727 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1728 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1729 if (r)
ff37e337 1730 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1731 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1732 spin_unlock_bh(&sc->sc_resetlock);
1733
1734 if (ath_startrecv(sc) != 0)
04bd4638 1735 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1736
1737 /*
1738 * We may be doing a reset in response to a request
1739 * that changes the channel so update any state that
1740 * might change as a result.
1741 */
ce111bad 1742 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1743
1744 ath_update_txpow(sc);
1745
1746 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1747 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1748
17d7904d 1749 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1750
1751 if (retry_tx) {
1752 int i;
1753 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1754 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1755 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1756 ath_txq_schedule(sc, &sc->tx.txq[i]);
1757 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1758 }
1759 }
1760 }
1761
ae8d2858 1762 return r;
ff37e337
S		 1763}
1764
1765/*
1766 * This function will allocate both the DMA descriptor structure, and the
1767 * buffers it contains. These are used to contain the descriptors used
1768 * by the system.
1769*/
1770int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1771 struct list_head *head, const char *name,
1772 int nbuf, int ndesc)
1773{
1774#define DS2PHYS(_dd, _ds) \
1775 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1776#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1777#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1778
1779 struct ath_desc *ds;
1780 struct ath_buf *bf;
1781 int i, bsize, error;
1782
04bd4638
S		 1783 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1784 name, nbuf, ndesc);
ff37e337 1785
b03a9db9 1786 INIT_LIST_HEAD(head);
ff37e337
S		 1787 /* ath_desc must be a multiple of DWORDs */
1788 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1789 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1790 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1791 error = -ENOMEM;
1792 goto fail;
1793 }
1794
1795 dd->dd_name = name;
1796 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1797
1798 /*
1799 * Need additional DMA memory because we can't use
1800 * descriptors that cross the 4K page boundary. Assume
1801 * one skipped descriptor per 4K page.
1802 */
2660b81a 1803 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1804 u32 ndesc_skipped =
1805 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1806 u32 dma_len;
1807
1808 while (ndesc_skipped) {
1809 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1810 dd->dd_desc_len += dma_len;
1811
1812 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1813 };
1814 }
1815
1816 /* allocate descriptors */
7da3c55c 1817 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1818 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1819 if (dd->dd_desc == NULL) {
1820 error = -ENOMEM;
1821 goto fail;
1822 }
1823 ds = dd->dd_desc;
04bd4638
S		 1824 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1825 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1826 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1827
1828 /* allocate buffers */
1829 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1830 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1831 if (bf == NULL) {
1832 error = -ENOMEM;
1833 goto fail2;
1834 }
ff37e337
S		 1835 dd->dd_bufptr = bf;
1836
ff37e337
S		 1837 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1838 bf->bf_desc = ds;
1839 bf->bf_daddr = DS2PHYS(dd, ds);
1840
2660b81a 1841 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1842 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1843 /*
1844 * Skip descriptor addresses which can cause 4KB
1845 * boundary crossing (addr + length) with a 32 dword
1846 * descriptor fetch.
1847 */
1848 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1849 ASSERT((caddr_t) bf->bf_desc <
1850 ((caddr_t) dd->dd_desc +
1851 dd->dd_desc_len));
1852
1853 ds += ndesc;
1854 bf->bf_desc = ds;
1855 bf->bf_daddr = DS2PHYS(dd, ds);
1856 }
1857 }
1858 list_add_tail(&bf->list, head);
1859 }
1860 return 0;
1861fail2:
7da3c55c
GJ		 1862 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1863 dd->dd_desc_paddr);
ff37e337
S		 1864fail:
1865 memset(dd, 0, sizeof(*dd));
1866 return error;
1867#undef ATH_DESC_4KB_BOUND_CHECK
1868#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1869#undef DS2PHYS
1870}
1871
1872void ath_descdma_cleanup(struct ath_softc *sc,
1873 struct ath_descdma *dd,
1874 struct list_head *head)
1875{
7da3c55c
GJ		 1876 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1877 dd->dd_desc_paddr);
ff37e337
S		 1878
1879 INIT_LIST_HEAD(head);
1880 kfree(dd->dd_bufptr);
1881 memset(dd, 0, sizeof(*dd));
1882}
1883
1884int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1885{
1886 int qnum;
1887
1888 switch (queue) {
1889 case 0:
b77f483f 1890 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1891 break;
1892 case 1:
b77f483f 1893 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1894 break;
1895 case 2:
b77f483f 1896 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1897 break;
1898 case 3:
b77f483f 1899 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1900 break;
1901 default:
b77f483f 1902 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1903 break;
1904 }
1905
1906 return qnum;
1907}
1908
1909int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1910{
1911 int qnum;
1912
1913 switch (queue) {
1914 case ATH9K_WME_AC_VO:
1915 qnum = 0;
1916 break;
1917 case ATH9K_WME_AC_VI:
1918 qnum = 1;
1919 break;
1920 case ATH9K_WME_AC_BE:
1921 qnum = 2;
1922 break;
1923 case ATH9K_WME_AC_BK:
1924 qnum = 3;
1925 break;
1926 default:
1927 qnum = -1;
1928 break;
1929 }
1930
1931 return qnum;
1932}
1933
5f8e077c
LR		 1934/* XXX: Remove me once we don't depend on ath9k_channel for all
1935 * this redundant data */
0e2dedf9
JM		 1936void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1937 struct ath9k_channel *ichan)
5f8e077c 1938{
5f8e077c
LR		 1939 struct ieee80211_channel *chan = hw->conf.channel;
1940 struct ieee80211_conf *conf = &hw->conf;
1941
1942 ichan->channel = chan->center_freq;
1943 ichan->chan = chan;
1944
1945 if (chan->band == IEEE80211_BAND_2GHZ) {
1946 ichan->chanmode = CHANNEL_G;
1947 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1948 } else {
1949 ichan->chanmode = CHANNEL_A;
1950 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1951 }
1952
1953 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1954
1955 if (conf_is_ht(conf)) {
1956 if (conf_is_ht40(conf))
1957 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1958
1959 ichan->chanmode = ath_get_extchanmode(sc, chan,
1960 conf->channel_type);
1961 }
1962}
1963
ff37e337
S		 1964/**********************/
1965/* mac80211 callbacks */
1966/**********************/
1967
8feceb67 1968static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1969{
bce048d7
JM		 1970 struct ath_wiphy *aphy = hw->priv;
1971 struct ath_softc *sc = aphy->sc;
8feceb67 1972 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1973 struct ath9k_channel *init_channel;
ae8d2858 1974 int r, pos;
f078f209 1975
04bd4638
S		 1976 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1977 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1978
141b38b6
S		 1979 mutex_lock(&sc->mutex);
1980
9580a222
JM		 1981 if (ath9k_wiphy_started(sc)) {
1982 if (sc->chan_idx == curchan->hw_value) {
1983 /*
1984 * Already on the operational channel, the new wiphy
1985 * can be marked active.
1986 */
1987 aphy->state = ATH_WIPHY_ACTIVE;
1988 ieee80211_wake_queues(hw);
1989 } else {
1990 /*
1991 * Another wiphy is on another channel, start the new
1992 * wiphy in paused state.
1993 */
1994 aphy->state = ATH_WIPHY_PAUSED;
1995 ieee80211_stop_queues(hw);
1996 }
1997 mutex_unlock(&sc->mutex);
1998 return 0;
1999 }
2000 aphy->state = ATH_WIPHY_ACTIVE;
2001
8feceb67 2002 /* setup initial channel */
f078f209 2003
5f8e077c 2004 pos = curchan->hw_value;
f078f209 2005
0e2dedf9 2006 sc->chan_idx = pos;
2660b81a 2007 init_channel = &sc->sc_ah->channels[pos];
0e2dedf9 2008 ath9k_update_ichannel(sc, hw, init_channel);
ff37e337
S		 2009
2010 /* Reset SERDES registers */
2011 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2012
2013 /*
2014 * The basic interface to setting the hardware in a good
2015 * state is ``reset''. On return the hardware is known to
2016 * be powered up and with interrupts disabled. This must
2017 * be followed by initialization of the appropriate bits
2018 * and then setup of the interrupt mask.
2019 */
2020 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 2021 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2022 if (r) {
ff37e337 2023 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 2024 "Unable to reset hardware; reset status %u "
2025 "(freq %u MHz)\n", r,
2026 curchan->center_freq);
ff37e337 2027 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 2028 goto mutex_unlock;
ff37e337
S		 2029 }
2030 spin_unlock_bh(&sc->sc_resetlock);
2031
2032 /*
2033 * This is needed only to setup initial state
2034 * but it's best done after a reset.
2035 */
2036 ath_update_txpow(sc);
8feceb67 2037
ff37e337
S		 2038 /*
2039 * Setup the hardware after reset:
2040 * The receive engine is set going.
2041 * Frame transmit is handled entirely
2042 * in the frame output path; there's nothing to do
2043 * here except setup the interrupt mask.
2044 */
2045 if (ath_startrecv(sc) != 0) {
8feceb67 2046 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2047 "Unable to start recv logic\n");
141b38b6
S		 2048 r = -EIO;
2049 goto mutex_unlock;
f078f209 2050 }
8feceb67 2051
ff37e337 2052 /* Setup our intr mask. */
17d7904d 2053 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 2054 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2055 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2056
2660b81a 2057 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 2058 sc->imask |= ATH9K_INT_GTT;
ff37e337 2059
2660b81a 2060 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 2061 sc->imask |= ATH9K_INT_CST;
ff37e337 2062
ce111bad 2063 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2064
2065 sc->sc_flags &= ~SC_OP_INVALID;
2066
2067 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 2068 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2069 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 2070
bce048d7 2071 ieee80211_wake_queues(hw);
ff37e337 2072
e97275cb 2073#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2074 r = ath_start_rfkill_poll(sc);
500c064d 2075#endif
141b38b6
S		 2076
2077mutex_unlock:
2078 mutex_unlock(&sc->mutex);
2079
ae8d2858 2080 return r;
f078f209
LR		 2081}
2082
8feceb67
VT		 2083static int ath9k_tx(struct ieee80211_hw *hw,
2084 struct sk_buff *skb)
f078f209 2085{
528f0c6b 2086 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 2087 struct ath_wiphy *aphy = hw->priv;
2088 struct ath_softc *sc = aphy->sc;
528f0c6b 2089 struct ath_tx_control txctl;
8feceb67 2090 int hdrlen, padsize;
528f0c6b 2091
8089cc47 2092 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 2093 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2094 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2095 goto exit;
2096 }
2097
528f0c6b 2098 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2099
8feceb67
VT		 2100 /*
2101 * As a temporary workaround, assign seq# here; this will likely need
2102 * to be cleaned up to work better with Beacon transmission and virtual
2103 * BSSes.
2104 */
2105 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2106 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2107 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2108 sc->tx.seq_no += 0x10;
8feceb67 2109 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2110 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2111 }
f078f209 2112
8feceb67
VT		 2113 /* Add the padding after the header if this is not already done */
2114 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2115 if (hdrlen & 3) {
2116 padsize = hdrlen % 4;
2117 if (skb_headroom(skb) < padsize)
2118 return -1;
2119 skb_push(skb, padsize);
2120 memmove(skb->data, skb->data + padsize, hdrlen);
2121 }
2122
528f0c6b
S		 2123 /* Check if a tx queue is available */
2124
2125 txctl.txq = ath_test_get_txq(sc, skb);
2126 if (!txctl.txq)
2127 goto exit;
2128
04bd4638 2129 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2130
c52f33d0 2131 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2132 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2133 goto exit;
8feceb67
VT		 2134 }
2135
528f0c6b
S		 2136 return 0;
2137exit:
2138 dev_kfree_skb_any(skb);
8feceb67 2139 return 0;
f078f209
LR		 2140}
2141
8feceb67 2142static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2143{
bce048d7
JM		 2144 struct ath_wiphy *aphy = hw->priv;
2145 struct ath_softc *sc = aphy->sc;
f078f209 2146
9580a222
JM		 2147 aphy->state = ATH_WIPHY_INACTIVE;
2148
9c84b797 2149 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2150 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2151 return;
2152 }
8feceb67 2153
141b38b6 2154 mutex_lock(&sc->mutex);
ff37e337 2155
bce048d7 2156 ieee80211_stop_queues(hw);
ff37e337 2157
9580a222
JM		 2158 if (ath9k_wiphy_started(sc)) {
2159 mutex_unlock(&sc->mutex);
2160 return; /* another wiphy still in use */
2161 }
2162
ff37e337
S		 2163 /* make sure h/w will not generate any interrupt
2164 * before setting the invalid flag. */
2165 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2166
2167 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2168 ath_drain_all_txq(sc, false);
ff37e337
S		 2169 ath_stoprecv(sc);
2170 ath9k_hw_phy_disable(sc->sc_ah);
2171 } else
b77f483f 2172 sc->rx.rxlink = NULL;
ff37e337
S		 2173
2174#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a 2175 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
ff37e337
S		 2176 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2177#endif
2178 /* disable HAL and put h/w to sleep */
2179 ath9k_hw_disable(sc->sc_ah);
2180 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2181
2182 sc->sc_flags |= SC_OP_INVALID;
500c064d 2183
141b38b6
S		 2184 mutex_unlock(&sc->mutex);
2185
04bd4638 2186 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2187}
2188
8feceb67
VT		 2189static int ath9k_add_interface(struct ieee80211_hw *hw,
2190 struct ieee80211_if_init_conf *conf)
f078f209 2191{
bce048d7
JM		 2192 struct ath_wiphy *aphy = hw->priv;
2193 struct ath_softc *sc = aphy->sc;
17d7904d 2194 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2195 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2196 int ret = 0;
8feceb67 2197
141b38b6
S		 2198 mutex_lock(&sc->mutex);
2199
8ca21f01
JM		 2200 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2201 sc->nvifs > 0) {
2202 ret = -ENOBUFS;
2203 goto out;
2204 }
2205
8feceb67 2206 switch (conf->type) {
05c914fe 2207 case NL80211_IFTYPE_STATION:
d97809db 2208 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2209 break;
05c914fe 2210 case NL80211_IFTYPE_ADHOC:
05c914fe 2211 case NL80211_IFTYPE_AP:
9cb5412b 2212 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2213 if (sc->nbcnvifs >= ATH_BCBUF) {
2214 ret = -ENOBUFS;
2215 goto out;
2216 }
9cb5412b 2217 ic_opmode = conf->type;
f078f209
LR		 2218 break;
2219 default:
2220 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2221 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2222 ret = -EOPNOTSUPP;
2223 goto out;
f078f209
LR		 2224 }
2225
17d7904d 2226 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2227
17d7904d 2228 /* Set the VIF opmode */
5640b08e
S		 2229 avp->av_opmode = ic_opmode;
2230 avp->av_bslot = -1;
2231
2c3db3d5 2232 sc->nvifs++;
8ca21f01
JM		 2233
2234 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2235 ath9k_set_bssid_mask(hw);
2236
2c3db3d5
JM		 2237 if (sc->nvifs > 1)
2238 goto out; /* skip global settings for secondary vif */
2239
b238e90e 2240 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2241 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2242 sc->sc_flags |= SC_OP_TSF_RESET;
2243 }
5640b08e 2244
5640b08e 2245 /* Set the device opmode */
2660b81a 2246 sc->sc_ah->opmode = ic_opmode;
5640b08e 2247
4e30ffa2
VN		 2248 /*
2249 * Enable MIB interrupts when there are hardware phy counters.
2250 * Note we only do this (at the moment) for station mode.
2251 */
4af9cf4f 2252 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2253 (conf->type == NL80211_IFTYPE_ADHOC) ||
2254 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2255 if (ath9k_hw_phycounters(sc->sc_ah))
2256 sc->imask |= ATH9K_INT_MIB;
2257 sc->imask |= ATH9K_INT_TSFOOR;
2258 }
2259
4e30ffa2
VN		 2260 /*
2261 * Some hardware processes the TIM IE and fires an
2262 * interrupt when the TIM bit is set. For hardware
2263 * that does, if not overridden by configuration,
2264 * enable the TIM interrupt when operating as station.
2265 */
2660b81a 2266 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
4e30ffa2 2267 (conf->type == NL80211_IFTYPE_STATION) &&
17d7904d
S		 2268 !sc->config.swBeaconProcess)
2269 sc->imask |= ATH9K_INT_TIM;
4e30ffa2 2270
17d7904d 2271 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2272
6f255425
LR		 2273 if (conf->type == NL80211_IFTYPE_AP) {
2274 /* TODO: is this a suitable place to start ANI for AP mode? */
2275 /* Start ANI */
17d7904d 2276 mod_timer(&sc->ani.timer,
6f255425
LR		 2277 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2278 }
2279
2c3db3d5 2280out:
141b38b6 2281 mutex_unlock(&sc->mutex);
2c3db3d5 2282 return ret;
f078f209
LR		 2283}
2284
8feceb67
VT		 2285static void ath9k_remove_interface(struct ieee80211_hw *hw,
2286 struct ieee80211_if_init_conf *conf)
f078f209 2287{
bce048d7
JM		 2288 struct ath_wiphy *aphy = hw->priv;
2289 struct ath_softc *sc = aphy->sc;
17d7904d 2290 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2291 int i;
f078f209 2292
04bd4638 2293 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2294
141b38b6
S		 2295 mutex_lock(&sc->mutex);
2296
6f255425 2297 /* Stop ANI */
17d7904d 2298 del_timer_sync(&sc->ani.timer);
580f0b8a 2299
8feceb67 2300 /* Reclaim beacon resources */
9cb5412b
PE		 2301 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2302 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2303 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2304 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2305 ath_beacon_return(sc, avp);
580f0b8a 2306 }
f078f209 2307
8feceb67 2308 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2309
2c3db3d5
JM		 2310 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2311 if (sc->beacon.bslot[i] == conf->vif) {
2312 printk(KERN_DEBUG "%s: vif had allocated beacon "
2313 "slot\n", __func__);
2314 sc->beacon.bslot[i] = NULL;
c52f33d0 2315 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2316 }
2317 }
2318
17d7904d 2319 sc->nvifs--;
141b38b6
S		 2320
2321 mutex_unlock(&sc->mutex);
f078f209
LR		 2322}
2323
e8975581 2324static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2325{
bce048d7
JM		 2326 struct ath_wiphy *aphy = hw->priv;
2327 struct ath_softc *sc = aphy->sc;
e8975581 2328 struct ieee80211_conf *conf = &hw->conf;
f078f209 2329
aa33de09 2330 mutex_lock(&sc->mutex);
141b38b6 2331
3cbb5dd7
VN		 2332 if (changed & IEEE80211_CONF_CHANGE_PS) {
2333 if (conf->flags & IEEE80211_CONF_PS) {
17d7904d
S		 2334 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2335 sc->imask |= ATH9K_INT_TIM_TIMER;
3cbb5dd7 2336 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2337 sc->imask);
3cbb5dd7
VN		 2338 }
2339 ath9k_hw_setrxabort(sc->sc_ah, 1);
2340 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2341 } else {
2342 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2343 ath9k_hw_setrxabort(sc->sc_ah, 0);
2344 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
17d7904d
S		 2345 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2346 sc->imask &= ~ATH9K_INT_TIM_TIMER;
3cbb5dd7 2347 ath9k_hw_set_interrupts(sc->sc_ah,
17d7904d 2348 sc->imask);
3cbb5dd7
VN		 2349 }
2350 }
2351 }
2352
4797938c 2353 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2354 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2355 int pos = curchan->hw_value;
ae5eb026 2356
0e2dedf9
JM		 2357 aphy->chan_idx = pos;
2358 aphy->chan_is_ht = conf_is_ht(conf);
2359
8089cc47
JM		 2360 if (aphy->state == ATH_WIPHY_SCAN ||
2361 aphy->state == ATH_WIPHY_ACTIVE)
2362 ath9k_wiphy_pause_all_forced(sc, aphy);
2363 else {
2364 /*
2365 * Do not change operational channel based on a paused
2366 * wiphy changes.
2367 */
2368 goto skip_chan_change;
2369 }
0e2dedf9 2370
04bd4638
S		 2371 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2372 curchan->center_freq);
f078f209 2373
5f8e077c 2374 /* XXX: remove me eventualy */
0e2dedf9 2375 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2376
ecf70441 2377 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2378
0e2dedf9 2379 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2380 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2381 mutex_unlock(&sc->mutex);
e11602b7
S		 2382 return -EINVAL;
2383 }
094d05dc 2384 }
f078f209 2385
8089cc47 2386skip_chan_change:
5c020dc6 2387 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2388 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2389
b238e90e
S		 2390 /*
2391 * The HW TSF has to be reset when the beacon interval changes.
2392 * We set the flag here, and ath_beacon_config_ap() would take this
2393 * into account when it gets called through the subsequent
2394 * config_interface() call - with IFCC_BEACON in the changed field.
2395 */
2396
2397 if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2398 sc->sc_flags |= SC_OP_TSF_RESET;
2399
aa33de09 2400 mutex_unlock(&sc->mutex);
141b38b6 2401
f078f209
LR		 2402 return 0;
2403}
2404
8feceb67
VT		 2405static int ath9k_config_interface(struct ieee80211_hw *hw,
2406 struct ieee80211_vif *vif,
2407 struct ieee80211_if_conf *conf)
c83be688 2408{
bce048d7
JM		 2409 struct ath_wiphy *aphy = hw->priv;
2410 struct ath_softc *sc = aphy->sc;
cbe61d8a 2411 struct ath_hw *ah = sc->sc_ah;
17d7904d 2412 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67
VT		 2413 u32 rfilt = 0;
2414 int error, i;
c83be688 2415
2554935b
S		 2416 mutex_lock(&sc->mutex);
2417
8feceb67
VT		 2418 /* TODO: Need to decide which hw opmode to use for multi-interface
2419 * cases */
05c914fe 2420 if (vif->type == NL80211_IFTYPE_AP &&
2660b81a
S		 2421 ah->opmode != NL80211_IFTYPE_AP) {
2422 ah->opmode = NL80211_IFTYPE_STATION;
8feceb67 2423 ath9k_hw_setopmode(ah);
ba52da58
S		 2424 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2425 sc->curaid = 0;
2426 ath9k_hw_write_associd(sc);
8feceb67
VT		 2427 /* Request full reset to get hw opmode changed properly */
2428 sc->sc_flags |= SC_OP_FULL_RESET;
2429 }
c83be688 2430
8feceb67
VT		 2431 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2432 !is_zero_ether_addr(conf->bssid)) {
2433 switch (vif->type) {
05c914fe
JB		 2434 case NL80211_IFTYPE_STATION:
2435 case NL80211_IFTYPE_ADHOC:
9cb5412b 2436 case NL80211_IFTYPE_MESH_POINT:
8feceb67 2437 /* Set BSSID */
17d7904d 2438 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
f0ed85c6 2439 memcpy(avp->bssid, conf->bssid, ETH_ALEN);
17d7904d 2440 sc->curaid = 0;
ba52da58 2441 ath9k_hw_write_associd(sc);
c83be688 2442
8feceb67 2443 /* Set aggregation protection mode parameters */
17d7904d 2444 sc->config.ath_aggr_prot = 0;
c83be688 2445
8feceb67 2446 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2447 "RX filter 0x%x bssid %pM aid 0x%x\n",
17d7904d 2448 rfilt, sc->curbssid, sc->curaid);
c83be688 2449
8feceb67
VT		 2450 /* need to reconfigure the beacon */
2451 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2452
8feceb67
VT		 2453 break;
2454 default:
2455 break;
2456 }
2457 }
c83be688 2458
1f7d6cbf 2459 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
9cb5412b
PE		 2460 (vif->type == NL80211_IFTYPE_AP) ||
2461 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
1f7d6cbf
S		 2462 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2463 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2464 conf->enable_beacon)) {
2465 /*
2466 * Allocate and setup the beacon frame.
2467 *
2468 * Stop any previous beacon DMA. This may be
2469 * necessary, for example, when an ibss merge
2470 * causes reconfiguration; we may be called
2471 * with beacon transmission active.
2472 */
2473 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2474
c52f33d0 2475 error = ath_beacon_alloc(aphy, vif);
2554935b
S		 2476 if (error != 0) {
2477 mutex_unlock(&sc->mutex);
1f7d6cbf 2478 return error;
2554935b 2479 }
c83be688 2480
2c3db3d5 2481 ath_beacon_config(sc, vif);
1f7d6cbf 2482 }
8feceb67 2483 }
c83be688 2484
8feceb67 2485 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2486 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2487 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2488 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2489 ath9k_hw_keysetmac(sc->sc_ah,
2490 (u16)i,
17d7904d 2491 sc->curbssid);
8feceb67 2492 }
c83be688 2493
8feceb67 2494 /* Only legacy IBSS for now */
05c914fe 2495 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2496 ath_update_chainmask(sc, 0);
f078f209 2497
2554935b
S		 2498 mutex_unlock(&sc->mutex);
2499
8feceb67
VT		 2500 return 0;
2501}
f078f209 2502
8feceb67
VT		 2503#define SUPPORTED_FILTERS \
2504 (FIF_PROMISC_IN_BSS | \
2505 FIF_ALLMULTI | \
2506 FIF_CONTROL | \
2507 FIF_OTHER_BSS | \
2508 FIF_BCN_PRBRESP_PROMISC | \
2509 FIF_FCSFAIL)
c83be688 2510
8feceb67
VT		 2511/* FIXME: sc->sc_full_reset ? */
2512static void ath9k_configure_filter(struct ieee80211_hw *hw,
2513 unsigned int changed_flags,
2514 unsigned int *total_flags,
2515 int mc_count,
2516 struct dev_mc_list *mclist)
2517{
bce048d7
JM		 2518 struct ath_wiphy *aphy = hw->priv;
2519 struct ath_softc *sc = aphy->sc;
8feceb67 2520 u32 rfilt;
f078f209 2521
8feceb67
VT		 2522 changed_flags &= SUPPORTED_FILTERS;
2523 *total_flags &= SUPPORTED_FILTERS;
f078f209 2524
b77f483f 2525 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2526 rfilt = ath_calcrxfilter(sc);
2527 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2528
b77f483f 2529 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2530}
f078f209 2531
8feceb67
VT		 2532static void ath9k_sta_notify(struct ieee80211_hw *hw,
2533 struct ieee80211_vif *vif,
2534 enum sta_notify_cmd cmd,
17741cdc 2535 struct ieee80211_sta *sta)
8feceb67 2536{
bce048d7
JM		 2537 struct ath_wiphy *aphy = hw->priv;
2538 struct ath_softc *sc = aphy->sc;
f078f209 2539
8feceb67
VT		 2540 switch (cmd) {
2541 case STA_NOTIFY_ADD:
5640b08e 2542 ath_node_attach(sc, sta);
8feceb67
VT		 2543 break;
2544 case STA_NOTIFY_REMOVE:
b5aa9bf9 2545 ath_node_detach(sc, sta);
8feceb67
VT		 2546 break;
2547 default:
2548 break;
2549 }
f078f209
LR		 2550}
2551
141b38b6 2552static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2553 const struct ieee80211_tx_queue_params *params)
f078f209 2554{
bce048d7
JM		 2555 struct ath_wiphy *aphy = hw->priv;
2556 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2557 struct ath9k_tx_queue_info qi;
2558 int ret = 0, qnum;
f078f209 2559
8feceb67
VT		 2560 if (queue >= WME_NUM_AC)
2561 return 0;
f078f209 2562
141b38b6
S		 2563 mutex_lock(&sc->mutex);
2564
8feceb67
VT		 2565 qi.tqi_aifs = params->aifs;
2566 qi.tqi_cwmin = params->cw_min;
2567 qi.tqi_cwmax = params->cw_max;
2568 qi.tqi_burstTime = params->txop;
2569 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2570
8feceb67 2571 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2572 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2573 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2574 queue, qnum, params->aifs, params->cw_min,
2575 params->cw_max, params->txop);
f078f209 2576
8feceb67
VT		 2577 ret = ath_txq_update(sc, qnum, &qi);
2578 if (ret)
04bd4638 2579 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2580
141b38b6
S		 2581 mutex_unlock(&sc->mutex);
2582
8feceb67
VT		 2583 return ret;
2584}
f078f209 2585
8feceb67
VT		 2586static int ath9k_set_key(struct ieee80211_hw *hw,
2587 enum set_key_cmd cmd,
dc822b5d
JB		 2588 struct ieee80211_vif *vif,
2589 struct ieee80211_sta *sta,
8feceb67
VT		 2590 struct ieee80211_key_conf *key)
2591{
bce048d7
JM		 2592 struct ath_wiphy *aphy = hw->priv;
2593 struct ath_softc *sc = aphy->sc;
8feceb67 2594 int ret = 0;
f078f209 2595
b3bd89ce
JM		 2596 if (modparam_nohwcrypt)
2597 return -ENOSPC;
2598
141b38b6 2599 mutex_lock(&sc->mutex);
3cbb5dd7 2600 ath9k_ps_wakeup(sc);
04bd4638 2601 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2602
8feceb67
VT		 2603 switch (cmd) {
2604 case SET_KEY:
3f53dd64 2605 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2606 if (ret >= 0) {
2607 key->hw_key_idx = ret;
8feceb67
VT		 2608 /* push IV and Michael MIC generation to stack */
2609 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2610 if (key->alg == ALG_TKIP)
2611 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2612 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2613 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2614 ret = 0;
8feceb67
VT		 2615 }
2616 break;
2617 case DISABLE_KEY:
2618 ath_key_delete(sc, key);
8feceb67
VT		 2619 break;
2620 default:
2621 ret = -EINVAL;
2622 }
f078f209 2623
3cbb5dd7 2624 ath9k_ps_restore(sc);
141b38b6
S		 2625 mutex_unlock(&sc->mutex);
2626
8feceb67
VT		 2627 return ret;
2628}
f078f209 2629
8feceb67
VT		 2630static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2631 struct ieee80211_vif *vif,
2632 struct ieee80211_bss_conf *bss_conf,
2633 u32 changed)
2634{
bce048d7
JM		 2635 struct ath_wiphy *aphy = hw->priv;
2636 struct ath_softc *sc = aphy->sc;
f078f209 2637
141b38b6
S		 2638 mutex_lock(&sc->mutex);
2639
8feceb67 2640 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2641 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2642 bss_conf->use_short_preamble);
2643 if (bss_conf->use_short_preamble)
2644 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2645 else
2646 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2647 }
f078f209 2648
8feceb67 2649 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2650 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2651 bss_conf->use_cts_prot);
2652 if (bss_conf->use_cts_prot &&
2653 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2654 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2655 else
2656 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2657 }
f078f209 2658
8feceb67 2659 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2660 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2661 bss_conf->assoc);
5640b08e 2662 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2663 }
141b38b6
S		 2664
2665 mutex_unlock(&sc->mutex);
8feceb67 2666}
f078f209 2667
8feceb67
VT		 2668static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2669{
2670 u64 tsf;
bce048d7
JM		 2671 struct ath_wiphy *aphy = hw->priv;
2672 struct ath_softc *sc = aphy->sc;
f078f209 2673
141b38b6
S		 2674 mutex_lock(&sc->mutex);
2675 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2676 mutex_unlock(&sc->mutex);
f078f209 2677
8feceb67
VT		 2678 return tsf;
2679}
f078f209 2680
3b5d665b
AF		 2681static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2682{
bce048d7
JM		 2683 struct ath_wiphy *aphy = hw->priv;
2684 struct ath_softc *sc = aphy->sc;
3b5d665b 2685
141b38b6
S		 2686 mutex_lock(&sc->mutex);
2687 ath9k_hw_settsf64(sc->sc_ah, tsf);
2688 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2689}
2690
8feceb67
VT		 2691static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2692{
bce048d7
JM		 2693 struct ath_wiphy *aphy = hw->priv;
2694 struct ath_softc *sc = aphy->sc;
c83be688 2695
141b38b6
S		 2696 mutex_lock(&sc->mutex);
2697 ath9k_hw_reset_tsf(sc->sc_ah);
2698 mutex_unlock(&sc->mutex);
8feceb67 2699}
f078f209 2700
8feceb67 2701static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2702 enum ieee80211_ampdu_mlme_action action,
2703 struct ieee80211_sta *sta,
2704 u16 tid, u16 *ssn)
8feceb67 2705{
bce048d7
JM		 2706 struct ath_wiphy *aphy = hw->priv;
2707 struct ath_softc *sc = aphy->sc;
8feceb67 2708 int ret = 0;
f078f209 2709
8feceb67
VT		 2710 switch (action) {
2711 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2712 if (!(sc->sc_flags & SC_OP_RXAGGR))
2713 ret = -ENOTSUPP;
8feceb67
VT		 2714 break;
2715 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2716 break;
2717 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2718 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2719 if (ret < 0)
2720 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2721 "Unable to start TX aggregation\n");
8feceb67 2722 else
17741cdc 2723 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2724 break;
2725 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2726 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2727 if (ret < 0)
2728 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2729 "Unable to stop TX aggregation\n");
f078f209 2730
17741cdc 2731 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2732 break;
b1720231 2733 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2734 ath_tx_aggr_resume(sc, sta, tid);
2735 break;
8feceb67 2736 default:
04bd4638 2737 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2738 }
2739
2740 return ret;
f078f209
LR		 2741}
2742
0c98de65
S		 2743static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2744{
bce048d7
JM		 2745 struct ath_wiphy *aphy = hw->priv;
2746 struct ath_softc *sc = aphy->sc;
0c98de65 2747
8089cc47
JM		 2748 if (ath9k_wiphy_scanning(sc)) {
2749 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2750 "same time\n");
2751 /*
2752 * Do not allow the concurrent scanning state for now. This
2753 * could be improved with scanning control moved into ath9k.
2754 */
2755 return;
2756 }
2757
2758 aphy->state = ATH_WIPHY_SCAN;
2759 ath9k_wiphy_pause_all_forced(sc, aphy);
2760
0c98de65
S		 2761 mutex_lock(&sc->mutex);
2762 sc->sc_flags |= SC_OP_SCANNING;
2763 mutex_unlock(&sc->mutex);
2764}
2765
2766static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2767{
bce048d7
JM		 2768 struct ath_wiphy *aphy = hw->priv;
2769 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2770
2771 mutex_lock(&sc->mutex);
8089cc47 2772 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65
S		 2773 sc->sc_flags &= ~SC_OP_SCANNING;
2774 mutex_unlock(&sc->mutex);
2775}
2776
6baff7f9 2777struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2778 .tx = ath9k_tx,
2779 .start = ath9k_start,
2780 .stop = ath9k_stop,
2781 .add_interface = ath9k_add_interface,
2782 .remove_interface = ath9k_remove_interface,
2783 .config = ath9k_config,
2784 .config_interface = ath9k_config_interface,
2785 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2786 .sta_notify = ath9k_sta_notify,
2787 .conf_tx = ath9k_conf_tx,
8feceb67 2788 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2789 .set_key = ath9k_set_key,
8feceb67 2790 .get_tsf = ath9k_get_tsf,
3b5d665b 2791 .set_tsf = ath9k_set_tsf,
8feceb67 2792 .reset_tsf = ath9k_reset_tsf,
4233df6b 2793 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2794 .sw_scan_start = ath9k_sw_scan_start,
2795 .sw_scan_complete = ath9k_sw_scan_complete,
8feceb67
VT		 2796};
2797
392dff83
BP		 2798static struct {
2799 u32 version;
2800 const char * name;
2801} ath_mac_bb_names[] = {
2802 { AR_SREV_VERSION_5416_PCI, "5416" },
2803 { AR_SREV_VERSION_5416_PCIE, "5418" },
2804 { AR_SREV_VERSION_9100, "9100" },
2805 { AR_SREV_VERSION_9160, "9160" },
2806 { AR_SREV_VERSION_9280, "9280" },
2807 { AR_SREV_VERSION_9285, "9285" }
2808};
2809
2810static struct {
2811 u16 version;
2812 const char * name;
2813} ath_rf_names[] = {
2814 { 0, "5133" },
2815 { AR_RAD5133_SREV_MAJOR, "5133" },
2816 { AR_RAD5122_SREV_MAJOR, "5122" },
2817 { AR_RAD2133_SREV_MAJOR, "2133" },
2818 { AR_RAD2122_SREV_MAJOR, "2122" }
2819};
2820
2821/*
2822 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2823 */
6baff7f9 2824const char *
392dff83
BP		 2825ath_mac_bb_name(u32 mac_bb_version)
2826{
2827 int i;
2828
2829 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2830 if (ath_mac_bb_names[i].version == mac_bb_version) {
2831 return ath_mac_bb_names[i].name;
2832 }
2833 }
2834
2835 return "????";
2836}
2837
2838/*
2839 * Return the RF name. "????" is returned if the RF is unknown.
2840 */
6baff7f9 2841const char *
392dff83
BP		 2842ath_rf_name(u16 rf_version)
2843{
2844 int i;
2845
2846 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2847 if (ath_rf_names[i].version == rf_version) {
2848 return ath_rf_names[i].name;
2849 }
2850 }
2851
2852 return "????";
2853}
2854
6baff7f9 2855static int __init ath9k_init(void)
f078f209 2856{
ca8a8560
VT		 2857 int error;
2858
ca8a8560
VT		 2859 /* Register rate control algorithm */
2860 error = ath_rate_control_register();
2861 if (error != 0) {
2862 printk(KERN_ERR
b51bb3cd
LR		 2863 "ath9k: Unable to register rate control "
2864 "algorithm: %d\n",
ca8a8560 2865 error);
6baff7f9 2866 goto err_out;
ca8a8560
VT		 2867 }
2868
19d8bc22
GJ		 2869 error = ath9k_debug_create_root();
2870 if (error) {
2871 printk(KERN_ERR
2872 "ath9k: Unable to create debugfs root: %d\n",
2873 error);
2874 goto err_rate_unregister;
2875 }
2876
6baff7f9
GJ		 2877 error = ath_pci_init();
2878 if (error < 0) {
f078f209 2879 printk(KERN_ERR
b51bb3cd 2880 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2881 error = -ENODEV;
19d8bc22 2882 goto err_remove_root;
f078f209
LR		 2883 }
2884
09329d37
GJ		 2885 error = ath_ahb_init();
2886 if (error < 0) {
2887 error = -ENODEV;
2888 goto err_pci_exit;
2889 }
2890
f078f209 2891 return 0;
6baff7f9 2892
09329d37
GJ		 2893 err_pci_exit:
2894 ath_pci_exit();
2895
19d8bc22
GJ		 2896 err_remove_root:
2897 ath9k_debug_remove_root();
6baff7f9
GJ		 2898 err_rate_unregister:
2899 ath_rate_control_unregister();
2900 err_out:
2901 return error;
f078f209 2902}
6baff7f9 2903module_init(ath9k_init);
f078f209 2904
6baff7f9 2905static void __exit ath9k_exit(void)
f078f209 2906{
09329d37 2907 ath_ahb_exit();
6baff7f9 2908 ath_pci_exit();
19d8bc22 2909 ath9k_debug_remove_root();
ca8a8560 2910 ath_rate_control_unregister();
04bd4638 2911 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2912}
6baff7f9 2913module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)