Commit | Line | Data |
---|---|---|
f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | /* mac80211 and PCI callbacks */ | |
18 | ||
19 | #include <linux/nl80211.h> | |
20 | #include "core.h" | |
392dff83 | 21 | #include "reg.h" |
f078f209 LR |
22 | |
23 | #define ATH_PCI_VERSION "0.1" | |
24 | ||
f078f209 LR |
25 | static char *dev_info = "ath9k"; |
26 | ||
27 | MODULE_AUTHOR("Atheros Communications"); | |
28 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
29 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
30 | MODULE_LICENSE("Dual BSD/GPL"); | |
31 | ||
32 | static struct pci_device_id ath_pci_id_table[] __devinitdata = { | |
33 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ | |
34 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
35 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
36 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
37 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
38 | { 0 } | |
39 | }; | |
40 | ||
9757d556 S |
41 | static void ath_detach(struct ath_softc *sc); |
42 | ||
f078f209 LR |
43 | static int ath_get_channel(struct ath_softc *sc, |
44 | struct ieee80211_channel *chan) | |
45 | { | |
46 | int i; | |
47 | ||
48 | for (i = 0; i < sc->sc_ah->ah_nchan; i++) { | |
49 | if (sc->sc_ah->ah_channels[i].channel == chan->center_freq) | |
50 | return i; | |
51 | } | |
52 | ||
53 | return -1; | |
54 | } | |
55 | ||
56 | static u32 ath_get_extchanmode(struct ath_softc *sc, | |
57 | struct ieee80211_channel *chan) | |
58 | { | |
59 | u32 chanmode = 0; | |
60 | u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset; | |
61 | enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width; | |
62 | ||
63 | switch (chan->band) { | |
64 | case IEEE80211_BAND_2GHZ: | |
d9fe60de | 65 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) && |
f078f209 LR |
66 | (tx_chan_width == ATH9K_HT_MACMODE_20)) |
67 | chanmode = CHANNEL_G_HT20; | |
d9fe60de | 68 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) && |
f078f209 LR |
69 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
70 | chanmode = CHANNEL_G_HT40PLUS; | |
d9fe60de | 71 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) && |
f078f209 LR |
72 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
73 | chanmode = CHANNEL_G_HT40MINUS; | |
74 | break; | |
75 | case IEEE80211_BAND_5GHZ: | |
d9fe60de | 76 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) && |
f078f209 LR |
77 | (tx_chan_width == ATH9K_HT_MACMODE_20)) |
78 | chanmode = CHANNEL_A_HT20; | |
d9fe60de | 79 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) && |
f078f209 LR |
80 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
81 | chanmode = CHANNEL_A_HT40PLUS; | |
d9fe60de | 82 | if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) && |
f078f209 LR |
83 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
84 | chanmode = CHANNEL_A_HT40MINUS; | |
85 | break; | |
86 | default: | |
87 | break; | |
88 | } | |
89 | ||
90 | return chanmode; | |
91 | } | |
92 | ||
93 | ||
94 | static int ath_setkey_tkip(struct ath_softc *sc, | |
95 | struct ieee80211_key_conf *key, | |
96 | struct ath9k_keyval *hk, | |
97 | const u8 *addr) | |
98 | { | |
99 | u8 *key_rxmic = NULL; | |
100 | u8 *key_txmic = NULL; | |
101 | ||
102 | key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; | |
103 | key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
104 | ||
105 | if (addr == NULL) { | |
106 | /* Group key installation */ | |
107 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
108 | return ath_keyset(sc, key->keyidx, hk, addr); | |
109 | } | |
110 | if (!sc->sc_splitmic) { | |
111 | /* | |
112 | * data key goes at first index, | |
113 | * the hal handles the MIC keys at index+64. | |
114 | */ | |
115 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
116 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
117 | return ath_keyset(sc, key->keyidx, hk, addr); | |
118 | } | |
119 | /* | |
120 | * TX key goes at first index, RX key at +32. | |
121 | * The hal handles the MIC keys at index+64. | |
122 | */ | |
123 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
124 | if (!ath_keyset(sc, key->keyidx, hk, NULL)) { | |
125 | /* Txmic entry failed. No need to proceed further */ | |
126 | DPRINTF(sc, ATH_DBG_KEYCACHE, | |
127 | "%s Setting TX MIC Key Failed\n", __func__); | |
128 | return 0; | |
129 | } | |
130 | ||
131 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
132 | /* XXX delete tx key on failure? */ | |
133 | return ath_keyset(sc, key->keyidx+32, hk, addr); | |
134 | } | |
135 | ||
136 | static int ath_key_config(struct ath_softc *sc, | |
137 | const u8 *addr, | |
138 | struct ieee80211_key_conf *key) | |
139 | { | |
140 | struct ieee80211_vif *vif; | |
141 | struct ath9k_keyval hk; | |
142 | const u8 *mac = NULL; | |
143 | int ret = 0; | |
05c914fe | 144 | enum nl80211_iftype opmode; |
f078f209 LR |
145 | |
146 | memset(&hk, 0, sizeof(hk)); | |
147 | ||
148 | switch (key->alg) { | |
149 | case ALG_WEP: | |
150 | hk.kv_type = ATH9K_CIPHER_WEP; | |
151 | break; | |
152 | case ALG_TKIP: | |
153 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
154 | break; | |
155 | case ALG_CCMP: | |
156 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
157 | break; | |
158 | default: | |
159 | return -EINVAL; | |
160 | } | |
161 | ||
162 | hk.kv_len = key->keylen; | |
163 | memcpy(hk.kv_val, key->key, key->keylen); | |
164 | ||
165 | if (!sc->sc_vaps[0]) | |
166 | return -EIO; | |
167 | ||
5640b08e | 168 | vif = sc->sc_vaps[0]; |
f078f209 LR |
169 | opmode = vif->type; |
170 | ||
171 | /* | |
172 | * Strategy: | |
173 | * For _M_STA mc tx, we will not setup a key at all since we never | |
174 | * tx mc. | |
175 | * _M_STA mc rx, we will use the keyID. | |
176 | * for _M_IBSS mc tx, we will use the keyID, and no macaddr. | |
177 | * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the | |
178 | * peer node. BUT we will plumb a cleartext key so that we can do | |
179 | * perSta default key table lookup in software. | |
180 | */ | |
181 | if (is_broadcast_ether_addr(addr)) { | |
182 | switch (opmode) { | |
05c914fe | 183 | case NL80211_IFTYPE_STATION: |
f078f209 LR |
184 | /* default key: could be group WPA key |
185 | * or could be static WEP key */ | |
186 | mac = NULL; | |
187 | break; | |
05c914fe | 188 | case NL80211_IFTYPE_ADHOC: |
f078f209 | 189 | break; |
05c914fe | 190 | case NL80211_IFTYPE_AP: |
f078f209 LR |
191 | break; |
192 | default: | |
193 | ASSERT(0); | |
194 | break; | |
195 | } | |
196 | } else { | |
197 | mac = addr; | |
198 | } | |
199 | ||
200 | if (key->alg == ALG_TKIP) | |
201 | ret = ath_setkey_tkip(sc, key, &hk, mac); | |
202 | else | |
203 | ret = ath_keyset(sc, key->keyidx, &hk, mac); | |
204 | ||
205 | if (!ret) | |
206 | return -EIO; | |
207 | ||
f078f209 LR |
208 | return 0; |
209 | } | |
210 | ||
211 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | |
212 | { | |
f078f209 LR |
213 | int freeslot; |
214 | ||
ff9b662d | 215 | freeslot = (key->keyidx >= 4) ? 1 : 0; |
f078f209 | 216 | ath_key_reset(sc, key->keyidx, freeslot); |
f078f209 LR |
217 | } |
218 | ||
d9fe60de | 219 | static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info) |
f078f209 | 220 | { |
60653678 S |
221 | #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */ |
222 | #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */ | |
f078f209 | 223 | |
d9fe60de JB |
224 | ht_info->ht_supported = true; |
225 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
226 | IEEE80211_HT_CAP_SM_PS | | |
227 | IEEE80211_HT_CAP_SGI_40 | | |
228 | IEEE80211_HT_CAP_DSSSCCK40; | |
f078f209 | 229 | |
60653678 S |
230 | ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536; |
231 | ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8; | |
d9fe60de JB |
232 | /* set up supported mcs set */ |
233 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
234 | ht_info->mcs.rx_mask[0] = 0xff; | |
235 | ht_info->mcs.rx_mask[1] = 0xff; | |
236 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
f078f209 LR |
237 | } |
238 | ||
8feceb67 VT |
239 | static void ath9k_ht_conf(struct ath_softc *sc, |
240 | struct ieee80211_bss_conf *bss_conf) | |
f078f209 | 241 | { |
8feceb67 | 242 | struct ath_ht_info *ht_info = &sc->sc_ht_info; |
f078f209 | 243 | |
ae5eb026 JB |
244 | if (sc->hw->conf.ht.enabled) { |
245 | ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset; | |
246 | ||
247 | if (bss_conf->ht.width_40_ok) | |
8feceb67 VT |
248 | ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040; |
249 | else | |
250 | ht_info->tx_chan_width = ATH9K_HT_MACMODE_20; | |
f078f209 | 251 | |
8feceb67 | 252 | ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width); |
f078f209 | 253 | } |
f078f209 LR |
254 | } |
255 | ||
8feceb67 | 256 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 257 | struct ieee80211_vif *vif, |
8feceb67 | 258 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 259 | { |
8feceb67 VT |
260 | struct ieee80211_hw *hw = sc->hw; |
261 | struct ieee80211_channel *curchan = hw->conf.channel; | |
5640b08e | 262 | struct ath_vap *avp = (void *)vif->drv_priv; |
8feceb67 | 263 | int pos; |
f078f209 | 264 | |
8feceb67 VT |
265 | if (bss_conf->assoc) { |
266 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n", | |
267 | __func__, | |
268 | bss_conf->aid); | |
f078f209 | 269 | |
8feceb67 VT |
270 | /* New association, store aid */ |
271 | if (avp->av_opmode == ATH9K_M_STA) { | |
272 | sc->sc_curaid = bss_conf->aid; | |
273 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | |
274 | sc->sc_curaid); | |
275 | } | |
f078f209 | 276 | |
8feceb67 VT |
277 | /* Configure the beacon */ |
278 | ath_beacon_config(sc, 0); | |
279 | sc->sc_flags |= SC_OP_BEACONS; | |
f078f209 | 280 | |
8feceb67 VT |
281 | /* Reset rssi stats */ |
282 | sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
283 | sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; | |
284 | sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; | |
285 | sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; | |
f078f209 | 286 | |
8feceb67 | 287 | /* Update chainmask */ |
ae5eb026 | 288 | ath_update_chainmask(sc, hw->conf.ht.enabled); |
f078f209 | 289 | |
f078f209 | 290 | DPRINTF(sc, ATH_DBG_CONFIG, |
e174961c | 291 | "%s: bssid %pM aid 0x%x\n", |
8feceb67 | 292 | __func__, |
e174961c | 293 | sc->sc_curbssid, sc->sc_curaid); |
f078f209 | 294 | |
8feceb67 VT |
295 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n", |
296 | __func__, | |
297 | curchan->center_freq); | |
f078f209 | 298 | |
8feceb67 VT |
299 | pos = ath_get_channel(sc, curchan); |
300 | if (pos == -1) { | |
301 | DPRINTF(sc, ATH_DBG_FATAL, | |
302 | "%s: Invalid channel\n", __func__); | |
303 | return; | |
304 | } | |
f078f209 | 305 | |
ae5eb026 | 306 | if (hw->conf.ht.enabled) |
8feceb67 VT |
307 | sc->sc_ah->ah_channels[pos].chanmode = |
308 | ath_get_extchanmode(sc, curchan); | |
309 | else | |
310 | sc->sc_ah->ah_channels[pos].chanmode = | |
311 | (curchan->band == IEEE80211_BAND_2GHZ) ? | |
312 | CHANNEL_G : CHANNEL_A; | |
f078f209 | 313 | |
8feceb67 VT |
314 | /* set h/w channel */ |
315 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) | |
316 | DPRINTF(sc, ATH_DBG_FATAL, | |
317 | "%s: Unable to set channel\n", | |
318 | __func__); | |
6f255425 LR |
319 | /* Start ANI */ |
320 | mod_timer(&sc->sc_ani.timer, | |
321 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
322 | ||
8feceb67 VT |
323 | } else { |
324 | DPRINTF(sc, ATH_DBG_CONFIG, | |
325 | "%s: Bss Info DISSOC\n", __func__); | |
326 | sc->sc_curaid = 0; | |
f078f209 | 327 | } |
8feceb67 | 328 | } |
f078f209 | 329 | |
8feceb67 VT |
330 | void ath_get_beaconconfig(struct ath_softc *sc, |
331 | int if_id, | |
332 | struct ath_beacon_config *conf) | |
333 | { | |
334 | struct ieee80211_hw *hw = sc->hw; | |
f078f209 | 335 | |
8feceb67 | 336 | /* fill in beacon config data */ |
f078f209 | 337 | |
8feceb67 VT |
338 | conf->beacon_interval = hw->conf.beacon_int; |
339 | conf->listen_interval = 100; | |
340 | conf->dtim_count = 1; | |
341 | conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval; | |
f078f209 LR |
342 | } |
343 | ||
8feceb67 | 344 | void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
528f0c6b | 345 | struct ath_xmit_status *tx_status) |
f078f209 | 346 | { |
8feceb67 VT |
347 | struct ieee80211_hw *hw = sc->hw; |
348 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
f078f209 | 349 | |
8feceb67 VT |
350 | DPRINTF(sc, ATH_DBG_XMIT, |
351 | "%s: TX complete: skb: %p\n", __func__, skb); | |
f078f209 | 352 | |
8feceb67 VT |
353 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
354 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
a8efee4f S |
355 | if (tx_info->rate_driver_data[0] != NULL) { |
356 | kfree(tx_info->rate_driver_data[0]); | |
357 | tx_info->rate_driver_data[0] = NULL; | |
358 | } | |
f078f209 LR |
359 | } |
360 | ||
8feceb67 VT |
361 | if (tx_status->flags & ATH_TX_BAR) { |
362 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; | |
363 | tx_status->flags &= ~ATH_TX_BAR; | |
364 | } | |
f078f209 | 365 | |
e6a9854b | 366 | if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
8feceb67 VT |
367 | /* Frame was ACKed */ |
368 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
f078f209 LR |
369 | } |
370 | ||
e6a9854b | 371 | tx_info->status.rates[0].count = tx_status->retries + 1; |
f078f209 | 372 | |
8feceb67 | 373 | ieee80211_tx_status(hw, skb); |
f078f209 LR |
374 | } |
375 | ||
8feceb67 VT |
376 | /********************************/ |
377 | /* LED functions */ | |
378 | /********************************/ | |
f078f209 | 379 | |
8feceb67 VT |
380 | static void ath_led_brightness(struct led_classdev *led_cdev, |
381 | enum led_brightness brightness) | |
382 | { | |
383 | struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev); | |
384 | struct ath_softc *sc = led->sc; | |
f078f209 | 385 | |
8feceb67 VT |
386 | switch (brightness) { |
387 | case LED_OFF: | |
388 | if (led->led_type == ATH_LED_ASSOC || | |
389 | led->led_type == ATH_LED_RADIO) | |
390 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
391 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
392 | (led->led_type == ATH_LED_RADIO) ? 1 : | |
393 | !!(sc->sc_flags & SC_OP_LED_ASSOCIATED)); | |
394 | break; | |
395 | case LED_FULL: | |
396 | if (led->led_type == ATH_LED_ASSOC) | |
397 | sc->sc_flags |= SC_OP_LED_ASSOCIATED; | |
398 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
399 | break; | |
400 | default: | |
401 | break; | |
f078f209 | 402 | } |
8feceb67 | 403 | } |
f078f209 | 404 | |
8feceb67 VT |
405 | static int ath_register_led(struct ath_softc *sc, struct ath_led *led, |
406 | char *trigger) | |
407 | { | |
408 | int ret; | |
f078f209 | 409 | |
8feceb67 VT |
410 | led->sc = sc; |
411 | led->led_cdev.name = led->name; | |
412 | led->led_cdev.default_trigger = trigger; | |
413 | led->led_cdev.brightness_set = ath_led_brightness; | |
f078f209 | 414 | |
8feceb67 VT |
415 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); |
416 | if (ret) | |
417 | DPRINTF(sc, ATH_DBG_FATAL, | |
418 | "Failed to register led:%s", led->name); | |
419 | else | |
420 | led->registered = 1; | |
421 | return ret; | |
422 | } | |
f078f209 | 423 | |
8feceb67 VT |
424 | static void ath_unregister_led(struct ath_led *led) |
425 | { | |
426 | if (led->registered) { | |
427 | led_classdev_unregister(&led->led_cdev); | |
428 | led->registered = 0; | |
f078f209 | 429 | } |
f078f209 LR |
430 | } |
431 | ||
8feceb67 | 432 | static void ath_deinit_leds(struct ath_softc *sc) |
f078f209 | 433 | { |
8feceb67 VT |
434 | ath_unregister_led(&sc->assoc_led); |
435 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
436 | ath_unregister_led(&sc->tx_led); | |
437 | ath_unregister_led(&sc->rx_led); | |
438 | ath_unregister_led(&sc->radio_led); | |
439 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
440 | } | |
f078f209 | 441 | |
8feceb67 VT |
442 | static void ath_init_leds(struct ath_softc *sc) |
443 | { | |
444 | char *trigger; | |
445 | int ret; | |
f078f209 | 446 | |
8feceb67 VT |
447 | /* Configure gpio 1 for output */ |
448 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
449 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
450 | /* LED off, active low */ | |
451 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
7dcfdcd9 | 452 | |
8feceb67 VT |
453 | trigger = ieee80211_get_radio_led_name(sc->hw); |
454 | snprintf(sc->radio_led.name, sizeof(sc->radio_led.name), | |
455 | "ath9k-%s:radio", wiphy_name(sc->hw->wiphy)); | |
456 | ret = ath_register_led(sc, &sc->radio_led, trigger); | |
457 | sc->radio_led.led_type = ATH_LED_RADIO; | |
458 | if (ret) | |
459 | goto fail; | |
7dcfdcd9 | 460 | |
8feceb67 VT |
461 | trigger = ieee80211_get_assoc_led_name(sc->hw); |
462 | snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name), | |
463 | "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy)); | |
464 | ret = ath_register_led(sc, &sc->assoc_led, trigger); | |
465 | sc->assoc_led.led_type = ATH_LED_ASSOC; | |
466 | if (ret) | |
467 | goto fail; | |
f078f209 | 468 | |
8feceb67 VT |
469 | trigger = ieee80211_get_tx_led_name(sc->hw); |
470 | snprintf(sc->tx_led.name, sizeof(sc->tx_led.name), | |
471 | "ath9k-%s:tx", wiphy_name(sc->hw->wiphy)); | |
472 | ret = ath_register_led(sc, &sc->tx_led, trigger); | |
473 | sc->tx_led.led_type = ATH_LED_TX; | |
474 | if (ret) | |
475 | goto fail; | |
f078f209 | 476 | |
8feceb67 VT |
477 | trigger = ieee80211_get_rx_led_name(sc->hw); |
478 | snprintf(sc->rx_led.name, sizeof(sc->rx_led.name), | |
479 | "ath9k-%s:rx", wiphy_name(sc->hw->wiphy)); | |
480 | ret = ath_register_led(sc, &sc->rx_led, trigger); | |
481 | sc->rx_led.led_type = ATH_LED_RX; | |
482 | if (ret) | |
483 | goto fail; | |
f078f209 | 484 | |
8feceb67 VT |
485 | return; |
486 | ||
487 | fail: | |
488 | ath_deinit_leds(sc); | |
f078f209 LR |
489 | } |
490 | ||
e97275cb | 491 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
9c84b797 | 492 | |
500c064d VT |
493 | /*******************/ |
494 | /* Rfkill */ | |
495 | /*******************/ | |
496 | ||
497 | static void ath_radio_enable(struct ath_softc *sc) | |
498 | { | |
499 | struct ath_hal *ah = sc->sc_ah; | |
500 | int status; | |
501 | ||
502 | spin_lock_bh(&sc->sc_resetlock); | |
503 | if (!ath9k_hw_reset(ah, ah->ah_curchan, | |
504 | sc->sc_ht_info.tx_chan_width, | |
505 | sc->sc_tx_chainmask, | |
506 | sc->sc_rx_chainmask, | |
507 | sc->sc_ht_extprotspacing, | |
508 | false, &status)) { | |
509 | DPRINTF(sc, ATH_DBG_FATAL, | |
510 | "%s: unable to reset channel %u (%uMhz) " | |
511 | "flags 0x%x hal status %u\n", __func__, | |
512 | ath9k_hw_mhz2ieee(ah, | |
513 | ah->ah_curchan->channel, | |
514 | ah->ah_curchan->channelFlags), | |
515 | ah->ah_curchan->channel, | |
516 | ah->ah_curchan->channelFlags, status); | |
517 | } | |
518 | spin_unlock_bh(&sc->sc_resetlock); | |
519 | ||
520 | ath_update_txpow(sc); | |
521 | if (ath_startrecv(sc) != 0) { | |
522 | DPRINTF(sc, ATH_DBG_FATAL, | |
523 | "%s: unable to restart recv logic\n", __func__); | |
524 | return; | |
525 | } | |
526 | ||
527 | if (sc->sc_flags & SC_OP_BEACONS) | |
528 | ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ | |
529 | ||
530 | /* Re-Enable interrupts */ | |
531 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
532 | ||
533 | /* Enable LED */ | |
534 | ath9k_hw_cfg_output(ah, ATH_LED_PIN, | |
535 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
536 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0); | |
537 | ||
538 | ieee80211_wake_queues(sc->hw); | |
539 | } | |
540 | ||
541 | static void ath_radio_disable(struct ath_softc *sc) | |
542 | { | |
543 | struct ath_hal *ah = sc->sc_ah; | |
544 | int status; | |
545 | ||
546 | ||
547 | ieee80211_stop_queues(sc->hw); | |
548 | ||
549 | /* Disable LED */ | |
550 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1); | |
551 | ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN); | |
552 | ||
553 | /* Disable interrupts */ | |
554 | ath9k_hw_set_interrupts(ah, 0); | |
555 | ||
556 | ath_draintxq(sc, false); /* clear pending tx frames */ | |
557 | ath_stoprecv(sc); /* turn off frame recv */ | |
558 | ath_flushrecv(sc); /* flush recv queue */ | |
559 | ||
560 | spin_lock_bh(&sc->sc_resetlock); | |
561 | if (!ath9k_hw_reset(ah, ah->ah_curchan, | |
562 | sc->sc_ht_info.tx_chan_width, | |
563 | sc->sc_tx_chainmask, | |
564 | sc->sc_rx_chainmask, | |
565 | sc->sc_ht_extprotspacing, | |
566 | false, &status)) { | |
567 | DPRINTF(sc, ATH_DBG_FATAL, | |
568 | "%s: unable to reset channel %u (%uMhz) " | |
569 | "flags 0x%x hal status %u\n", __func__, | |
570 | ath9k_hw_mhz2ieee(ah, | |
571 | ah->ah_curchan->channel, | |
572 | ah->ah_curchan->channelFlags), | |
573 | ah->ah_curchan->channel, | |
574 | ah->ah_curchan->channelFlags, status); | |
575 | } | |
576 | spin_unlock_bh(&sc->sc_resetlock); | |
577 | ||
578 | ath9k_hw_phy_disable(ah); | |
579 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | |
580 | } | |
581 | ||
582 | static bool ath_is_rfkill_set(struct ath_softc *sc) | |
583 | { | |
584 | struct ath_hal *ah = sc->sc_ah; | |
585 | ||
586 | return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == | |
587 | ah->ah_rfkill_polarity; | |
588 | } | |
589 | ||
590 | /* h/w rfkill poll function */ | |
591 | static void ath_rfkill_poll(struct work_struct *work) | |
592 | { | |
593 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
594 | rf_kill.rfkill_poll.work); | |
595 | bool radio_on; | |
596 | ||
597 | if (sc->sc_flags & SC_OP_INVALID) | |
598 | return; | |
599 | ||
600 | radio_on = !ath_is_rfkill_set(sc); | |
601 | ||
602 | /* | |
603 | * enable/disable radio only when there is a | |
604 | * state change in RF switch | |
605 | */ | |
606 | if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) { | |
607 | enum rfkill_state state; | |
608 | ||
609 | if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) { | |
610 | state = radio_on ? RFKILL_STATE_SOFT_BLOCKED | |
611 | : RFKILL_STATE_HARD_BLOCKED; | |
612 | } else if (radio_on) { | |
613 | ath_radio_enable(sc); | |
614 | state = RFKILL_STATE_UNBLOCKED; | |
615 | } else { | |
616 | ath_radio_disable(sc); | |
617 | state = RFKILL_STATE_HARD_BLOCKED; | |
618 | } | |
619 | ||
620 | if (state == RFKILL_STATE_HARD_BLOCKED) | |
621 | sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED; | |
622 | else | |
623 | sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED; | |
624 | ||
625 | rfkill_force_state(sc->rf_kill.rfkill, state); | |
626 | } | |
627 | ||
628 | queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, | |
629 | msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL)); | |
630 | } | |
631 | ||
632 | /* s/w rfkill handler */ | |
633 | static int ath_sw_toggle_radio(void *data, enum rfkill_state state) | |
634 | { | |
635 | struct ath_softc *sc = data; | |
636 | ||
637 | switch (state) { | |
638 | case RFKILL_STATE_SOFT_BLOCKED: | |
639 | if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED | | |
640 | SC_OP_RFKILL_SW_BLOCKED))) | |
641 | ath_radio_disable(sc); | |
642 | sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED; | |
643 | return 0; | |
644 | case RFKILL_STATE_UNBLOCKED: | |
645 | if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) { | |
646 | sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED; | |
647 | if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) { | |
648 | DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the" | |
649 | "radio as it is disabled by h/w \n"); | |
650 | return -EPERM; | |
651 | } | |
652 | ath_radio_enable(sc); | |
653 | } | |
654 | return 0; | |
655 | default: | |
656 | return -EINVAL; | |
657 | } | |
658 | } | |
659 | ||
660 | /* Init s/w rfkill */ | |
661 | static int ath_init_sw_rfkill(struct ath_softc *sc) | |
662 | { | |
663 | sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy), | |
664 | RFKILL_TYPE_WLAN); | |
665 | if (!sc->rf_kill.rfkill) { | |
666 | DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n"); | |
667 | return -ENOMEM; | |
668 | } | |
669 | ||
670 | snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name), | |
671 | "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy)); | |
672 | sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name; | |
673 | sc->rf_kill.rfkill->data = sc; | |
674 | sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio; | |
675 | sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED; | |
676 | sc->rf_kill.rfkill->user_claim_unsupported = 1; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | /* Deinitialize rfkill */ | |
682 | static void ath_deinit_rfkill(struct ath_softc *sc) | |
683 | { | |
684 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
685 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
686 | ||
687 | if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { | |
688 | rfkill_unregister(sc->rf_kill.rfkill); | |
689 | sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED; | |
690 | sc->rf_kill.rfkill = NULL; | |
691 | } | |
692 | } | |
9c84b797 S |
693 | |
694 | static int ath_start_rfkill_poll(struct ath_softc *sc) | |
695 | { | |
696 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
697 | queue_delayed_work(sc->hw->workqueue, | |
698 | &sc->rf_kill.rfkill_poll, 0); | |
699 | ||
700 | if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) { | |
701 | if (rfkill_register(sc->rf_kill.rfkill)) { | |
702 | DPRINTF(sc, ATH_DBG_FATAL, | |
703 | "Unable to register rfkill\n"); | |
704 | rfkill_free(sc->rf_kill.rfkill); | |
705 | ||
706 | /* Deinitialize the device */ | |
306efdd1 | 707 | ath_detach(sc); |
9c84b797 S |
708 | if (sc->pdev->irq) |
709 | free_irq(sc->pdev->irq, sc); | |
9c84b797 S |
710 | pci_iounmap(sc->pdev, sc->mem); |
711 | pci_release_region(sc->pdev, 0); | |
712 | pci_disable_device(sc->pdev); | |
9757d556 | 713 | ieee80211_free_hw(sc->hw); |
9c84b797 S |
714 | return -EIO; |
715 | } else { | |
716 | sc->sc_flags |= SC_OP_RFKILL_REGISTERED; | |
717 | } | |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
500c064d VT |
722 | #endif /* CONFIG_RFKILL */ |
723 | ||
9c84b797 | 724 | static void ath_detach(struct ath_softc *sc) |
f078f209 | 725 | { |
8feceb67 | 726 | struct ieee80211_hw *hw = sc->hw; |
9c84b797 | 727 | int i = 0; |
f078f209 | 728 | |
8feceb67 | 729 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__); |
f078f209 | 730 | |
e97275cb | 731 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
732 | ath_deinit_rfkill(sc); |
733 | #endif | |
3fcdfb4b VT |
734 | ath_deinit_leds(sc); |
735 | ||
736 | ieee80211_unregister_hw(hw); | |
737 | ||
8feceb67 | 738 | ath_rate_control_unregister(); |
f078f209 | 739 | |
8feceb67 VT |
740 | ath_rx_cleanup(sc); |
741 | ath_tx_cleanup(sc); | |
f078f209 | 742 | |
9c84b797 S |
743 | tasklet_kill(&sc->intr_tq); |
744 | tasklet_kill(&sc->bcon_tasklet); | |
f078f209 | 745 | |
9c84b797 S |
746 | if (!(sc->sc_flags & SC_OP_INVALID)) |
747 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
8feceb67 | 748 | |
9c84b797 S |
749 | /* cleanup tx queues */ |
750 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
751 | if (ATH_TXQ_SETUP(sc, i)) | |
752 | ath_tx_cleanupq(sc, &sc->sc_txq[i]); | |
753 | ||
754 | ath9k_hw_detach(sc->sc_ah); | |
f078f209 LR |
755 | } |
756 | ||
9c84b797 | 757 | static int ath_attach(u16 devid, struct ath_softc *sc) |
f078f209 | 758 | { |
8feceb67 VT |
759 | struct ieee80211_hw *hw = sc->hw; |
760 | int error = 0; | |
f078f209 | 761 | |
8feceb67 | 762 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__); |
f078f209 | 763 | |
8feceb67 VT |
764 | error = ath_init(devid, sc); |
765 | if (error != 0) | |
766 | return error; | |
f078f209 | 767 | |
8feceb67 | 768 | /* get mac address from hardware and set in mac80211 */ |
f078f209 | 769 | |
8feceb67 | 770 | SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr); |
f078f209 | 771 | |
9c84b797 S |
772 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
773 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
774 | IEEE80211_HW_SIGNAL_DBM | | |
775 | IEEE80211_HW_AMPDU_AGGREGATION; | |
f078f209 | 776 | |
9c84b797 S |
777 | hw->wiphy->interface_modes = |
778 | BIT(NL80211_IFTYPE_AP) | | |
779 | BIT(NL80211_IFTYPE_STATION) | | |
780 | BIT(NL80211_IFTYPE_ADHOC); | |
f078f209 | 781 | |
8feceb67 | 782 | hw->queues = 4; |
528f0c6b | 783 | hw->sta_data_size = sizeof(struct ath_node); |
5640b08e | 784 | hw->vif_data_size = sizeof(struct ath_vap); |
f078f209 | 785 | |
8feceb67 VT |
786 | /* Register rate control */ |
787 | hw->rate_control_algorithm = "ath9k_rate_control"; | |
788 | error = ath_rate_control_register(); | |
789 | if (error != 0) { | |
790 | DPRINTF(sc, ATH_DBG_FATAL, | |
791 | "%s: Unable to register rate control " | |
792 | "algorithm:%d\n", __func__, error); | |
793 | ath_rate_control_unregister(); | |
794 | goto bad; | |
795 | } | |
f078f209 | 796 | |
9c84b797 S |
797 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { |
798 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
799 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) | |
800 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
801 | } | |
802 | ||
803 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
804 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) | |
805 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
806 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
807 | ||
db93e7b5 SB |
808 | /* initialize tx/rx engine */ |
809 | error = ath_tx_init(sc, ATH_TXBUF); | |
810 | if (error != 0) | |
811 | goto detach; | |
8feceb67 | 812 | |
db93e7b5 SB |
813 | error = ath_rx_init(sc, ATH_RXBUF); |
814 | if (error != 0) | |
815 | goto detach; | |
8feceb67 | 816 | |
e97275cb | 817 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
818 | /* Initialze h/w Rfkill */ |
819 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
820 | INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); | |
821 | ||
822 | /* Initialize s/w rfkill */ | |
823 | if (ath_init_sw_rfkill(sc)) | |
824 | goto detach; | |
825 | #endif | |
826 | ||
db93e7b5 SB |
827 | error = ieee80211_register_hw(hw); |
828 | if (error != 0) { | |
829 | ath_rate_control_unregister(); | |
830 | goto bad; | |
831 | } | |
8feceb67 | 832 | |
db93e7b5 SB |
833 | /* Initialize LED control */ |
834 | ath_init_leds(sc); | |
8feceb67 VT |
835 | |
836 | return 0; | |
837 | detach: | |
838 | ath_detach(sc); | |
839 | bad: | |
840 | return error; | |
f078f209 LR |
841 | } |
842 | ||
8feceb67 | 843 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 LR |
844 | { |
845 | struct ath_softc *sc = hw->priv; | |
8feceb67 VT |
846 | struct ieee80211_channel *curchan = hw->conf.channel; |
847 | int error = 0, pos; | |
f078f209 | 848 | |
8feceb67 VT |
849 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with " |
850 | "initial channel: %d MHz\n", __func__, curchan->center_freq); | |
f078f209 | 851 | |
7f959032 S |
852 | memset(&sc->sc_ht_info, 0, sizeof(struct ath_ht_info)); |
853 | ||
8feceb67 | 854 | /* setup initial channel */ |
f078f209 | 855 | |
8feceb67 VT |
856 | pos = ath_get_channel(sc, curchan); |
857 | if (pos == -1) { | |
858 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); | |
9c84b797 S |
859 | error = -EINVAL; |
860 | goto exit; | |
f078f209 LR |
861 | } |
862 | ||
8feceb67 VT |
863 | sc->sc_ah->ah_channels[pos].chanmode = |
864 | (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A; | |
865 | ||
8feceb67 VT |
866 | error = ath_open(sc, &sc->sc_ah->ah_channels[pos]); |
867 | if (error) { | |
868 | DPRINTF(sc, ATH_DBG_FATAL, | |
869 | "%s: Unable to complete ath_open\n", __func__); | |
9c84b797 | 870 | goto exit; |
f078f209 | 871 | } |
8feceb67 | 872 | |
e97275cb | 873 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
9c84b797 | 874 | error = ath_start_rfkill_poll(sc); |
500c064d VT |
875 | #endif |
876 | ||
9c84b797 S |
877 | exit: |
878 | return error; | |
f078f209 LR |
879 | } |
880 | ||
8feceb67 VT |
881 | static int ath9k_tx(struct ieee80211_hw *hw, |
882 | struct sk_buff *skb) | |
f078f209 | 883 | { |
528f0c6b | 884 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f078f209 | 885 | struct ath_softc *sc = hw->priv; |
528f0c6b | 886 | struct ath_tx_control txctl; |
8feceb67 | 887 | int hdrlen, padsize; |
528f0c6b S |
888 | |
889 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | |
f078f209 | 890 | |
8feceb67 VT |
891 | /* |
892 | * As a temporary workaround, assign seq# here; this will likely need | |
893 | * to be cleaned up to work better with Beacon transmission and virtual | |
894 | * BSSes. | |
895 | */ | |
896 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
897 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
898 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
899 | sc->seq_no += 0x10; | |
900 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
901 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
902 | } | |
f078f209 | 903 | |
8feceb67 VT |
904 | /* Add the padding after the header if this is not already done */ |
905 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
906 | if (hdrlen & 3) { | |
907 | padsize = hdrlen % 4; | |
908 | if (skb_headroom(skb) < padsize) | |
909 | return -1; | |
910 | skb_push(skb, padsize); | |
911 | memmove(skb->data, skb->data + padsize, hdrlen); | |
912 | } | |
913 | ||
528f0c6b S |
914 | /* Check if a tx queue is available */ |
915 | ||
916 | txctl.txq = ath_test_get_txq(sc, skb); | |
917 | if (!txctl.txq) | |
918 | goto exit; | |
919 | ||
8feceb67 VT |
920 | DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n", |
921 | __func__, | |
922 | skb); | |
923 | ||
528f0c6b | 924 | if (ath_tx_start(sc, skb, &txctl) != 0) { |
8feceb67 | 925 | DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__); |
528f0c6b | 926 | goto exit; |
8feceb67 VT |
927 | } |
928 | ||
528f0c6b S |
929 | return 0; |
930 | exit: | |
931 | dev_kfree_skb_any(skb); | |
8feceb67 | 932 | return 0; |
f078f209 LR |
933 | } |
934 | ||
8feceb67 | 935 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 LR |
936 | { |
937 | struct ath_softc *sc = hw->priv; | |
f078f209 | 938 | |
9c84b797 S |
939 | if (sc->sc_flags & SC_OP_INVALID) { |
940 | DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__); | |
941 | return; | |
942 | } | |
8feceb67 | 943 | |
9c84b797 | 944 | ath_stop(sc); |
500c064d | 945 | |
9c84b797 | 946 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__); |
f078f209 LR |
947 | } |
948 | ||
8feceb67 VT |
949 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
950 | struct ieee80211_if_init_conf *conf) | |
f078f209 LR |
951 | { |
952 | struct ath_softc *sc = hw->priv; | |
5640b08e S |
953 | struct ath_vap *avp = (void *)conf->vif->drv_priv; |
954 | int ic_opmode = 0; | |
f078f209 | 955 | |
8feceb67 VT |
956 | /* Support only vap for now */ |
957 | ||
958 | if (sc->sc_nvaps) | |
959 | return -ENOBUFS; | |
960 | ||
961 | switch (conf->type) { | |
05c914fe | 962 | case NL80211_IFTYPE_STATION: |
8feceb67 | 963 | ic_opmode = ATH9K_M_STA; |
f078f209 | 964 | break; |
05c914fe | 965 | case NL80211_IFTYPE_ADHOC: |
8feceb67 | 966 | ic_opmode = ATH9K_M_IBSS; |
f078f209 | 967 | break; |
05c914fe | 968 | case NL80211_IFTYPE_AP: |
8feceb67 | 969 | ic_opmode = ATH9K_M_HOSTAP; |
f078f209 LR |
970 | break; |
971 | default: | |
972 | DPRINTF(sc, ATH_DBG_FATAL, | |
8feceb67 VT |
973 | "%s: Interface type %d not yet supported\n", |
974 | __func__, conf->type); | |
975 | return -EOPNOTSUPP; | |
f078f209 LR |
976 | } |
977 | ||
8feceb67 VT |
978 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n", |
979 | __func__, | |
980 | ic_opmode); | |
981 | ||
5640b08e S |
982 | /* Set the VAP opmode */ |
983 | avp->av_opmode = ic_opmode; | |
984 | avp->av_bslot = -1; | |
985 | ||
986 | if (ic_opmode == ATH9K_M_HOSTAP) | |
987 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); | |
988 | ||
989 | sc->sc_vaps[0] = conf->vif; | |
990 | sc->sc_nvaps++; | |
991 | ||
992 | /* Set the device opmode */ | |
993 | sc->sc_ah->ah_opmode = ic_opmode; | |
994 | ||
6f255425 LR |
995 | if (conf->type == NL80211_IFTYPE_AP) { |
996 | /* TODO: is this a suitable place to start ANI for AP mode? */ | |
997 | /* Start ANI */ | |
998 | mod_timer(&sc->sc_ani.timer, | |
999 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
1000 | } | |
1001 | ||
8feceb67 | 1002 | return 0; |
f078f209 LR |
1003 | } |
1004 | ||
8feceb67 VT |
1005 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1006 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 1007 | { |
8feceb67 | 1008 | struct ath_softc *sc = hw->priv; |
5640b08e | 1009 | struct ath_vap *avp = (void *)conf->vif->drv_priv; |
f078f209 | 1010 | |
8feceb67 | 1011 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__); |
f078f209 | 1012 | |
8feceb67 VT |
1013 | #ifdef CONFIG_SLOW_ANT_DIV |
1014 | ath_slow_ant_div_stop(&sc->sc_antdiv); | |
1015 | #endif | |
6f255425 LR |
1016 | /* Stop ANI */ |
1017 | del_timer_sync(&sc->sc_ani.timer); | |
580f0b8a | 1018 | |
8feceb67 VT |
1019 | /* Reclaim beacon resources */ |
1020 | if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP || | |
1021 | sc->sc_ah->ah_opmode == ATH9K_M_IBSS) { | |
1022 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | |
1023 | ath_beacon_return(sc, avp); | |
580f0b8a | 1024 | } |
f078f209 | 1025 | |
8feceb67 | 1026 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1027 | |
5640b08e S |
1028 | sc->sc_vaps[0] = NULL; |
1029 | sc->sc_nvaps--; | |
f078f209 LR |
1030 | } |
1031 | ||
e8975581 | 1032 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1033 | { |
8feceb67 VT |
1034 | struct ath_softc *sc = hw->priv; |
1035 | struct ieee80211_channel *curchan = hw->conf.channel; | |
e8975581 | 1036 | struct ieee80211_conf *conf = &hw->conf; |
8feceb67 | 1037 | int pos; |
f078f209 | 1038 | |
8feceb67 VT |
1039 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n", |
1040 | __func__, | |
1041 | curchan->center_freq); | |
f078f209 | 1042 | |
ae5eb026 JB |
1043 | /* Update chainmask */ |
1044 | ath_update_chainmask(sc, conf->ht.enabled); | |
1045 | ||
8feceb67 VT |
1046 | pos = ath_get_channel(sc, curchan); |
1047 | if (pos == -1) { | |
1048 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__); | |
1049 | return -EINVAL; | |
f078f209 | 1050 | } |
f078f209 | 1051 | |
8feceb67 VT |
1052 | sc->sc_ah->ah_channels[pos].chanmode = |
1053 | (curchan->band == IEEE80211_BAND_2GHZ) ? | |
1054 | CHANNEL_G : CHANNEL_A; | |
f078f209 | 1055 | |
ae5eb026 | 1056 | if (sc->sc_curaid && hw->conf.ht.enabled) |
8feceb67 VT |
1057 | sc->sc_ah->ah_channels[pos].chanmode = |
1058 | ath_get_extchanmode(sc, curchan); | |
f078f209 | 1059 | |
5c020dc6 LR |
1060 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
1061 | sc->sc_config.txpowlimit = 2 * conf->power_level; | |
f078f209 | 1062 | |
8feceb67 VT |
1063 | /* set h/w channel */ |
1064 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) | |
1065 | DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n", | |
1066 | __func__); | |
f078f209 LR |
1067 | |
1068 | return 0; | |
1069 | } | |
1070 | ||
8feceb67 VT |
1071 | static int ath9k_config_interface(struct ieee80211_hw *hw, |
1072 | struct ieee80211_vif *vif, | |
1073 | struct ieee80211_if_conf *conf) | |
c83be688 | 1074 | { |
8feceb67 VT |
1075 | struct ath_softc *sc = hw->priv; |
1076 | struct ath_hal *ah = sc->sc_ah; | |
5640b08e | 1077 | struct ath_vap *avp = (void *)vif->drv_priv; |
8feceb67 VT |
1078 | u32 rfilt = 0; |
1079 | int error, i; | |
c83be688 | 1080 | |
8feceb67 VT |
1081 | /* TODO: Need to decide which hw opmode to use for multi-interface |
1082 | * cases */ | |
05c914fe | 1083 | if (vif->type == NL80211_IFTYPE_AP && |
8feceb67 VT |
1084 | ah->ah_opmode != ATH9K_M_HOSTAP) { |
1085 | ah->ah_opmode = ATH9K_M_HOSTAP; | |
1086 | ath9k_hw_setopmode(ah); | |
1087 | ath9k_hw_write_associd(ah, sc->sc_myaddr, 0); | |
1088 | /* Request full reset to get hw opmode changed properly */ | |
1089 | sc->sc_flags |= SC_OP_FULL_RESET; | |
1090 | } | |
c83be688 | 1091 | |
8feceb67 VT |
1092 | if ((conf->changed & IEEE80211_IFCC_BSSID) && |
1093 | !is_zero_ether_addr(conf->bssid)) { | |
1094 | switch (vif->type) { | |
05c914fe JB |
1095 | case NL80211_IFTYPE_STATION: |
1096 | case NL80211_IFTYPE_ADHOC: | |
8feceb67 VT |
1097 | /* Set BSSID */ |
1098 | memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN); | |
1099 | sc->sc_curaid = 0; | |
1100 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | |
1101 | sc->sc_curaid); | |
c83be688 | 1102 | |
8feceb67 VT |
1103 | /* Set aggregation protection mode parameters */ |
1104 | sc->sc_config.ath_aggr_prot = 0; | |
c83be688 | 1105 | |
8feceb67 | 1106 | DPRINTF(sc, ATH_DBG_CONFIG, |
e174961c | 1107 | "%s: RX filter 0x%x bssid %pM aid 0x%x\n", |
8feceb67 | 1108 | __func__, rfilt, |
e174961c | 1109 | sc->sc_curbssid, sc->sc_curaid); |
c83be688 | 1110 | |
8feceb67 VT |
1111 | /* need to reconfigure the beacon */ |
1112 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
c83be688 | 1113 | |
8feceb67 VT |
1114 | break; |
1115 | default: | |
1116 | break; | |
1117 | } | |
1118 | } | |
c83be688 | 1119 | |
8feceb67 | 1120 | if ((conf->changed & IEEE80211_IFCC_BEACON) && |
05c914fe JB |
1121 | ((vif->type == NL80211_IFTYPE_ADHOC) || |
1122 | (vif->type == NL80211_IFTYPE_AP))) { | |
8feceb67 VT |
1123 | /* |
1124 | * Allocate and setup the beacon frame. | |
1125 | * | |
1126 | * Stop any previous beacon DMA. This may be | |
1127 | * necessary, for example, when an ibss merge | |
1128 | * causes reconfiguration; we may be called | |
1129 | * with beacon transmission active. | |
1130 | */ | |
1131 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | |
c83be688 | 1132 | |
8feceb67 VT |
1133 | error = ath_beacon_alloc(sc, 0); |
1134 | if (error != 0) | |
1135 | return error; | |
c83be688 | 1136 | |
8feceb67 VT |
1137 | ath_beacon_sync(sc, 0); |
1138 | } | |
c83be688 | 1139 | |
8feceb67 | 1140 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ |
5640b08e | 1141 | if ((avp->av_opmode != ATH9K_M_STA)) { |
8feceb67 VT |
1142 | for (i = 0; i < IEEE80211_WEP_NKID; i++) |
1143 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | |
1144 | ath9k_hw_keysetmac(sc->sc_ah, | |
1145 | (u16)i, | |
1146 | sc->sc_curbssid); | |
1147 | } | |
c83be688 | 1148 | |
8feceb67 | 1149 | /* Only legacy IBSS for now */ |
05c914fe | 1150 | if (vif->type == NL80211_IFTYPE_ADHOC) |
8feceb67 | 1151 | ath_update_chainmask(sc, 0); |
f078f209 | 1152 | |
8feceb67 VT |
1153 | return 0; |
1154 | } | |
f078f209 | 1155 | |
8feceb67 VT |
1156 | #define SUPPORTED_FILTERS \ |
1157 | (FIF_PROMISC_IN_BSS | \ | |
1158 | FIF_ALLMULTI | \ | |
1159 | FIF_CONTROL | \ | |
1160 | FIF_OTHER_BSS | \ | |
1161 | FIF_BCN_PRBRESP_PROMISC | \ | |
1162 | FIF_FCSFAIL) | |
c83be688 | 1163 | |
8feceb67 VT |
1164 | /* FIXME: sc->sc_full_reset ? */ |
1165 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1166 | unsigned int changed_flags, | |
1167 | unsigned int *total_flags, | |
1168 | int mc_count, | |
1169 | struct dev_mc_list *mclist) | |
1170 | { | |
1171 | struct ath_softc *sc = hw->priv; | |
1172 | u32 rfilt; | |
f078f209 | 1173 | |
8feceb67 VT |
1174 | changed_flags &= SUPPORTED_FILTERS; |
1175 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1176 | |
8feceb67 VT |
1177 | sc->rx_filter = *total_flags; |
1178 | rfilt = ath_calcrxfilter(sc); | |
1179 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
f078f209 | 1180 | |
8feceb67 VT |
1181 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
1182 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
1183 | ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); | |
1184 | } | |
f078f209 | 1185 | |
8feceb67 VT |
1186 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n", |
1187 | __func__, sc->rx_filter); | |
1188 | } | |
f078f209 | 1189 | |
8feceb67 VT |
1190 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
1191 | struct ieee80211_vif *vif, | |
1192 | enum sta_notify_cmd cmd, | |
17741cdc | 1193 | struct ieee80211_sta *sta) |
8feceb67 VT |
1194 | { |
1195 | struct ath_softc *sc = hw->priv; | |
f078f209 | 1196 | |
8feceb67 VT |
1197 | switch (cmd) { |
1198 | case STA_NOTIFY_ADD: | |
5640b08e | 1199 | ath_node_attach(sc, sta); |
8feceb67 VT |
1200 | break; |
1201 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 1202 | ath_node_detach(sc, sta); |
8feceb67 VT |
1203 | break; |
1204 | default: | |
1205 | break; | |
1206 | } | |
f078f209 LR |
1207 | } |
1208 | ||
8feceb67 VT |
1209 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
1210 | u16 queue, | |
1211 | const struct ieee80211_tx_queue_params *params) | |
f078f209 | 1212 | { |
8feceb67 VT |
1213 | struct ath_softc *sc = hw->priv; |
1214 | struct ath9k_tx_queue_info qi; | |
1215 | int ret = 0, qnum; | |
f078f209 | 1216 | |
8feceb67 VT |
1217 | if (queue >= WME_NUM_AC) |
1218 | return 0; | |
f078f209 | 1219 | |
8feceb67 VT |
1220 | qi.tqi_aifs = params->aifs; |
1221 | qi.tqi_cwmin = params->cw_min; | |
1222 | qi.tqi_cwmax = params->cw_max; | |
1223 | qi.tqi_burstTime = params->txop; | |
1224 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1225 | |
8feceb67 VT |
1226 | DPRINTF(sc, ATH_DBG_CONFIG, |
1227 | "%s: Configure tx [queue/halq] [%d/%d], " | |
1228 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1229 | __func__, | |
1230 | queue, | |
1231 | qnum, | |
1232 | params->aifs, | |
1233 | params->cw_min, | |
1234 | params->cw_max, | |
1235 | params->txop); | |
f078f209 | 1236 | |
8feceb67 VT |
1237 | ret = ath_txq_update(sc, qnum, &qi); |
1238 | if (ret) | |
1239 | DPRINTF(sc, ATH_DBG_FATAL, | |
1240 | "%s: TXQ Update failed\n", __func__); | |
f078f209 | 1241 | |
8feceb67 VT |
1242 | return ret; |
1243 | } | |
f078f209 | 1244 | |
8feceb67 VT |
1245 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1246 | enum set_key_cmd cmd, | |
1247 | const u8 *local_addr, | |
1248 | const u8 *addr, | |
1249 | struct ieee80211_key_conf *key) | |
1250 | { | |
1251 | struct ath_softc *sc = hw->priv; | |
1252 | int ret = 0; | |
f078f209 | 1253 | |
8feceb67 | 1254 | DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__); |
f078f209 | 1255 | |
8feceb67 VT |
1256 | switch (cmd) { |
1257 | case SET_KEY: | |
1258 | ret = ath_key_config(sc, addr, key); | |
1259 | if (!ret) { | |
1260 | set_bit(key->keyidx, sc->sc_keymap); | |
1261 | key->hw_key_idx = key->keyidx; | |
1262 | /* push IV and Michael MIC generation to stack */ | |
1263 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1264 | if (key->alg == ALG_TKIP) | |
1265 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
1266 | } | |
1267 | break; | |
1268 | case DISABLE_KEY: | |
1269 | ath_key_delete(sc, key); | |
1270 | clear_bit(key->keyidx, sc->sc_keymap); | |
8feceb67 VT |
1271 | break; |
1272 | default: | |
1273 | ret = -EINVAL; | |
1274 | } | |
f078f209 | 1275 | |
8feceb67 VT |
1276 | return ret; |
1277 | } | |
f078f209 | 1278 | |
8feceb67 VT |
1279 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1280 | struct ieee80211_vif *vif, | |
1281 | struct ieee80211_bss_conf *bss_conf, | |
1282 | u32 changed) | |
1283 | { | |
1284 | struct ath_softc *sc = hw->priv; | |
f078f209 | 1285 | |
8feceb67 VT |
1286 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
1287 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n", | |
1288 | __func__, | |
1289 | bss_conf->use_short_preamble); | |
1290 | if (bss_conf->use_short_preamble) | |
1291 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1292 | else | |
1293 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1294 | } | |
f078f209 | 1295 | |
8feceb67 VT |
1296 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
1297 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n", | |
1298 | __func__, | |
1299 | bss_conf->use_cts_prot); | |
1300 | if (bss_conf->use_cts_prot && | |
1301 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1302 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1303 | else | |
1304 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1305 | } | |
f078f209 | 1306 | |
8feceb67 | 1307 | if (changed & BSS_CHANGED_HT) { |
ae5eb026 JB |
1308 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n", |
1309 | __func__); | |
8feceb67 | 1310 | ath9k_ht_conf(sc, bss_conf); |
f078f209 LR |
1311 | } |
1312 | ||
8feceb67 VT |
1313 | if (changed & BSS_CHANGED_ASSOC) { |
1314 | DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n", | |
1315 | __func__, | |
1316 | bss_conf->assoc); | |
5640b08e | 1317 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 VT |
1318 | } |
1319 | } | |
f078f209 | 1320 | |
8feceb67 VT |
1321 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1322 | { | |
1323 | u64 tsf; | |
1324 | struct ath_softc *sc = hw->priv; | |
1325 | struct ath_hal *ah = sc->sc_ah; | |
f078f209 | 1326 | |
8feceb67 | 1327 | tsf = ath9k_hw_gettsf64(ah); |
f078f209 | 1328 | |
8feceb67 VT |
1329 | return tsf; |
1330 | } | |
f078f209 | 1331 | |
8feceb67 VT |
1332 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1333 | { | |
1334 | struct ath_softc *sc = hw->priv; | |
1335 | struct ath_hal *ah = sc->sc_ah; | |
c83be688 | 1336 | |
8feceb67 VT |
1337 | ath9k_hw_reset_tsf(ah); |
1338 | } | |
f078f209 | 1339 | |
8feceb67 VT |
1340 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
1341 | enum ieee80211_ampdu_mlme_action action, | |
17741cdc JB |
1342 | struct ieee80211_sta *sta, |
1343 | u16 tid, u16 *ssn) | |
8feceb67 VT |
1344 | { |
1345 | struct ath_softc *sc = hw->priv; | |
1346 | int ret = 0; | |
f078f209 | 1347 | |
8feceb67 VT |
1348 | switch (action) { |
1349 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
1350 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
1351 | ret = -ENOTSUPP; | |
8feceb67 VT |
1352 | break; |
1353 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
1354 | break; |
1355 | case IEEE80211_AMPDU_TX_START: | |
b5aa9bf9 | 1356 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
8feceb67 VT |
1357 | if (ret < 0) |
1358 | DPRINTF(sc, ATH_DBG_FATAL, | |
1359 | "%s: Unable to start TX aggregation\n", | |
1360 | __func__); | |
1361 | else | |
17741cdc | 1362 | ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 VT |
1363 | break; |
1364 | case IEEE80211_AMPDU_TX_STOP: | |
b5aa9bf9 | 1365 | ret = ath_tx_aggr_stop(sc, sta, tid); |
8feceb67 VT |
1366 | if (ret < 0) |
1367 | DPRINTF(sc, ATH_DBG_FATAL, | |
1368 | "%s: Unable to stop TX aggregation\n", | |
1369 | __func__); | |
f078f209 | 1370 | |
17741cdc | 1371 | ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 | 1372 | break; |
8469cdef S |
1373 | case IEEE80211_AMPDU_TX_RESUME: |
1374 | ath_tx_aggr_resume(sc, sta, tid); | |
1375 | break; | |
8feceb67 VT |
1376 | default: |
1377 | DPRINTF(sc, ATH_DBG_FATAL, | |
1378 | "%s: Unknown AMPDU action\n", __func__); | |
1379 | } | |
1380 | ||
1381 | return ret; | |
f078f209 LR |
1382 | } |
1383 | ||
4233df6b JB |
1384 | static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value) |
1385 | { | |
1386 | return -EOPNOTSUPP; | |
1387 | } | |
1388 | ||
8feceb67 VT |
1389 | static struct ieee80211_ops ath9k_ops = { |
1390 | .tx = ath9k_tx, | |
1391 | .start = ath9k_start, | |
1392 | .stop = ath9k_stop, | |
1393 | .add_interface = ath9k_add_interface, | |
1394 | .remove_interface = ath9k_remove_interface, | |
1395 | .config = ath9k_config, | |
1396 | .config_interface = ath9k_config_interface, | |
1397 | .configure_filter = ath9k_configure_filter, | |
8feceb67 VT |
1398 | .sta_notify = ath9k_sta_notify, |
1399 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 1400 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 1401 | .set_key = ath9k_set_key, |
8feceb67 VT |
1402 | .get_tsf = ath9k_get_tsf, |
1403 | .reset_tsf = ath9k_reset_tsf, | |
4233df6b JB |
1404 | .ampdu_action = ath9k_ampdu_action, |
1405 | .set_frag_threshold = ath9k_no_fragmentation, | |
8feceb67 VT |
1406 | }; |
1407 | ||
392dff83 BP |
1408 | static struct { |
1409 | u32 version; | |
1410 | const char * name; | |
1411 | } ath_mac_bb_names[] = { | |
1412 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
1413 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
1414 | { AR_SREV_VERSION_9100, "9100" }, | |
1415 | { AR_SREV_VERSION_9160, "9160" }, | |
1416 | { AR_SREV_VERSION_9280, "9280" }, | |
1417 | { AR_SREV_VERSION_9285, "9285" } | |
1418 | }; | |
1419 | ||
1420 | static struct { | |
1421 | u16 version; | |
1422 | const char * name; | |
1423 | } ath_rf_names[] = { | |
1424 | { 0, "5133" }, | |
1425 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
1426 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
1427 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
1428 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
1429 | }; | |
1430 | ||
1431 | /* | |
1432 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
1433 | */ | |
1434 | ||
1435 | static const char * | |
1436 | ath_mac_bb_name(u32 mac_bb_version) | |
1437 | { | |
1438 | int i; | |
1439 | ||
1440 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
1441 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
1442 | return ath_mac_bb_names[i].name; | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | return "????"; | |
1447 | } | |
1448 | ||
1449 | /* | |
1450 | * Return the RF name. "????" is returned if the RF is unknown. | |
1451 | */ | |
1452 | ||
1453 | static const char * | |
1454 | ath_rf_name(u16 rf_version) | |
1455 | { | |
1456 | int i; | |
1457 | ||
1458 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
1459 | if (ath_rf_names[i].version == rf_version) { | |
1460 | return ath_rf_names[i].name; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | return "????"; | |
1465 | } | |
1466 | ||
f078f209 LR |
1467 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1468 | { | |
1469 | void __iomem *mem; | |
1470 | struct ath_softc *sc; | |
1471 | struct ieee80211_hw *hw; | |
f078f209 LR |
1472 | u8 csz; |
1473 | u32 val; | |
1474 | int ret = 0; | |
392dff83 | 1475 | struct ath_hal *ah; |
f078f209 LR |
1476 | |
1477 | if (pci_enable_device(pdev)) | |
1478 | return -EIO; | |
1479 | ||
97b777db LR |
1480 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1481 | ||
1482 | if (ret) { | |
1d450cfc | 1483 | printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); |
97b777db LR |
1484 | goto bad; |
1485 | } | |
1486 | ||
1487 | ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1488 | ||
1489 | if (ret) { | |
1490 | printk(KERN_ERR "ath9k: 32-bit DMA consistent " | |
1491 | "DMA enable faled\n"); | |
f078f209 LR |
1492 | goto bad; |
1493 | } | |
1494 | ||
1495 | /* | |
1496 | * Cache line size is used to size and align various | |
1497 | * structures used to communicate with the hardware. | |
1498 | */ | |
1499 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
1500 | if (csz == 0) { | |
1501 | /* | |
1502 | * Linux 2.4.18 (at least) writes the cache line size | |
1503 | * register as a 16-bit wide register which is wrong. | |
1504 | * We must have this setup properly for rx buffer | |
1505 | * DMA to work so force a reasonable value here if it | |
1506 | * comes up zero. | |
1507 | */ | |
1508 | csz = L1_CACHE_BYTES / sizeof(u32); | |
1509 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
1510 | } | |
1511 | /* | |
1512 | * The default setting of latency timer yields poor results, | |
1513 | * set it to the value used by other systems. It may be worth | |
1514 | * tweaking this setting more. | |
1515 | */ | |
1516 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
1517 | ||
1518 | pci_set_master(pdev); | |
1519 | ||
1520 | /* | |
1521 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
1522 | * PCI Tx retries from interfering with C3 CPU state. | |
1523 | */ | |
1524 | pci_read_config_dword(pdev, 0x40, &val); | |
1525 | if ((val & 0x0000ff00) != 0) | |
1526 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
1527 | ||
1528 | ret = pci_request_region(pdev, 0, "ath9k"); | |
1529 | if (ret) { | |
1530 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
1531 | ret = -ENODEV; | |
1532 | goto bad; | |
1533 | } | |
1534 | ||
1535 | mem = pci_iomap(pdev, 0, 0); | |
1536 | if (!mem) { | |
1537 | printk(KERN_ERR "PCI memory map error\n") ; | |
1538 | ret = -EIO; | |
1539 | goto bad1; | |
1540 | } | |
1541 | ||
1542 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); | |
1543 | if (hw == NULL) { | |
1544 | printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n"); | |
1545 | goto bad2; | |
1546 | } | |
1547 | ||
f078f209 LR |
1548 | SET_IEEE80211_DEV(hw, &pdev->dev); |
1549 | pci_set_drvdata(pdev, hw); | |
1550 | ||
1551 | sc = hw->priv; | |
1552 | sc->hw = hw; | |
1553 | sc->pdev = pdev; | |
1554 | sc->mem = mem; | |
1555 | ||
1556 | if (ath_attach(id->device, sc) != 0) { | |
1557 | ret = -ENODEV; | |
1558 | goto bad3; | |
1559 | } | |
1560 | ||
1561 | /* setup interrupt service routine */ | |
1562 | ||
1563 | if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) { | |
1564 | printk(KERN_ERR "%s: request_irq failed\n", | |
1565 | wiphy_name(hw->wiphy)); | |
1566 | ret = -EIO; | |
1567 | goto bad4; | |
1568 | } | |
1569 | ||
392dff83 BP |
1570 | ah = sc->sc_ah; |
1571 | printk(KERN_INFO | |
1572 | "%s: Atheros AR%s MAC/BB Rev:%x " | |
1573 | "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n", | |
f078f209 | 1574 | wiphy_name(hw->wiphy), |
392dff83 BP |
1575 | ath_mac_bb_name(ah->ah_macVersion), |
1576 | ah->ah_macRev, | |
1577 | ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), | |
1578 | ah->ah_phyRev, | |
f078f209 LR |
1579 | (unsigned long)mem, pdev->irq); |
1580 | ||
1581 | return 0; | |
1582 | bad4: | |
1583 | ath_detach(sc); | |
1584 | bad3: | |
1585 | ieee80211_free_hw(hw); | |
1586 | bad2: | |
1587 | pci_iounmap(pdev, mem); | |
1588 | bad1: | |
1589 | pci_release_region(pdev, 0); | |
1590 | bad: | |
1591 | pci_disable_device(pdev); | |
1592 | return ret; | |
1593 | } | |
1594 | ||
1595 | static void ath_pci_remove(struct pci_dev *pdev) | |
1596 | { | |
1597 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
1598 | struct ath_softc *sc = hw->priv; | |
1599 | ||
f078f209 | 1600 | ath_detach(sc); |
9c84b797 S |
1601 | if (pdev->irq) |
1602 | free_irq(pdev->irq, sc); | |
f078f209 LR |
1603 | pci_iounmap(pdev, sc->mem); |
1604 | pci_release_region(pdev, 0); | |
1605 | pci_disable_device(pdev); | |
1606 | ieee80211_free_hw(hw); | |
1607 | } | |
1608 | ||
1609 | #ifdef CONFIG_PM | |
1610 | ||
1611 | static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
1612 | { | |
c83be688 VT |
1613 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
1614 | struct ath_softc *sc = hw->priv; | |
1615 | ||
1616 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
500c064d | 1617 | |
e97275cb | 1618 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
1619 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
1620 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
1621 | #endif | |
1622 | ||
f078f209 LR |
1623 | pci_save_state(pdev); |
1624 | pci_disable_device(pdev); | |
1625 | pci_set_power_state(pdev, 3); | |
1626 | ||
1627 | return 0; | |
1628 | } | |
1629 | ||
1630 | static int ath_pci_resume(struct pci_dev *pdev) | |
1631 | { | |
c83be688 VT |
1632 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
1633 | struct ath_softc *sc = hw->priv; | |
f078f209 LR |
1634 | u32 val; |
1635 | int err; | |
1636 | ||
1637 | err = pci_enable_device(pdev); | |
1638 | if (err) | |
1639 | return err; | |
1640 | pci_restore_state(pdev); | |
1641 | /* | |
1642 | * Suspend/Resume resets the PCI configuration space, so we have to | |
1643 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
1644 | * PCI Tx retries from interfering with C3 CPU state | |
1645 | */ | |
1646 | pci_read_config_dword(pdev, 0x40, &val); | |
1647 | if ((val & 0x0000ff00) != 0) | |
1648 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
1649 | ||
c83be688 VT |
1650 | /* Enable LED */ |
1651 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
1652 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1653 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
1654 | ||
e97275cb | 1655 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
1656 | /* |
1657 | * check the h/w rfkill state on resume | |
1658 | * and start the rfkill poll timer | |
1659 | */ | |
1660 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
1661 | queue_delayed_work(sc->hw->workqueue, | |
1662 | &sc->rf_kill.rfkill_poll, 0); | |
1663 | #endif | |
1664 | ||
f078f209 LR |
1665 | return 0; |
1666 | } | |
1667 | ||
1668 | #endif /* CONFIG_PM */ | |
1669 | ||
1670 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
1671 | ||
1672 | static struct pci_driver ath_pci_driver = { | |
1673 | .name = "ath9k", | |
1674 | .id_table = ath_pci_id_table, | |
1675 | .probe = ath_pci_probe, | |
1676 | .remove = ath_pci_remove, | |
1677 | #ifdef CONFIG_PM | |
1678 | .suspend = ath_pci_suspend, | |
1679 | .resume = ath_pci_resume, | |
1680 | #endif /* CONFIG_PM */ | |
1681 | }; | |
1682 | ||
1683 | static int __init init_ath_pci(void) | |
1684 | { | |
1685 | printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION); | |
1686 | ||
1687 | if (pci_register_driver(&ath_pci_driver) < 0) { | |
1688 | printk(KERN_ERR | |
1689 | "ath_pci: No devices found, driver not installed.\n"); | |
1690 | pci_unregister_driver(&ath_pci_driver); | |
1691 | return -ENODEV; | |
1692 | } | |
1693 | ||
1694 | return 0; | |
1695 | } | |
1696 | module_init(init_ath_pci); | |
1697 | ||
1698 | static void __exit exit_ath_pci(void) | |
1699 | { | |
1700 | pci_unregister_driver(&ath_pci_driver); | |
1701 | printk(KERN_INFO "%s: driver unloaded\n", dev_info); | |
1702 | } | |
1703 | module_exit(exit_ath_pci); |