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b43: Add LP-PHY register definitions
[linux-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
5f8e077c
LR		 31/* We use the hw_value as an index into our private channel structure */
32
33#define CHAN2G(_freq, _idx) { \
34 .center_freq = (_freq), \
35 .hw_value = (_idx), \
36 .max_power = 30, \
37}
38
39#define CHAN5G(_freq, _idx) { \
40 .band = IEEE80211_BAND_5GHZ, \
41 .center_freq = (_freq), \
42 .hw_value = (_idx), \
43 .max_power = 30, \
44}
45
46/* Some 2 GHz radios are actually tunable on 2312-2732
47 * on 5 MHz steps, we support the channels which we know
48 * we have calibration data for all cards though to make
49 * this static */
50static struct ieee80211_channel ath9k_2ghz_chantable[] = {
51 CHAN2G(2412, 0), /* Channel 1 */
52 CHAN2G(2417, 1), /* Channel 2 */
53 CHAN2G(2422, 2), /* Channel 3 */
54 CHAN2G(2427, 3), /* Channel 4 */
55 CHAN2G(2432, 4), /* Channel 5 */
56 CHAN2G(2437, 5), /* Channel 6 */
57 CHAN2G(2442, 6), /* Channel 7 */
58 CHAN2G(2447, 7), /* Channel 8 */
59 CHAN2G(2452, 8), /* Channel 9 */
60 CHAN2G(2457, 9), /* Channel 10 */
61 CHAN2G(2462, 10), /* Channel 11 */
62 CHAN2G(2467, 11), /* Channel 12 */
63 CHAN2G(2472, 12), /* Channel 13 */
64 CHAN2G(2484, 13), /* Channel 14 */
65};
66
67/* Some 5 GHz radios are actually tunable on XXXX-YYYY
68 * on 5 MHz steps, we support the channels which we know
69 * we have calibration data for all cards though to make
70 * this static */
71static struct ieee80211_channel ath9k_5ghz_chantable[] = {
72 /* _We_ call this UNII 1 */
73 CHAN5G(5180, 14), /* Channel 36 */
74 CHAN5G(5200, 15), /* Channel 40 */
75 CHAN5G(5220, 16), /* Channel 44 */
76 CHAN5G(5240, 17), /* Channel 48 */
77 /* _We_ call this UNII 2 */
78 CHAN5G(5260, 18), /* Channel 52 */
79 CHAN5G(5280, 19), /* Channel 56 */
80 CHAN5G(5300, 20), /* Channel 60 */
81 CHAN5G(5320, 21), /* Channel 64 */
82 /* _We_ call this "Middle band" */
83 CHAN5G(5500, 22), /* Channel 100 */
84 CHAN5G(5520, 23), /* Channel 104 */
85 CHAN5G(5540, 24), /* Channel 108 */
86 CHAN5G(5560, 25), /* Channel 112 */
87 CHAN5G(5580, 26), /* Channel 116 */
88 CHAN5G(5600, 27), /* Channel 120 */
89 CHAN5G(5620, 28), /* Channel 124 */
90 CHAN5G(5640, 29), /* Channel 128 */
91 CHAN5G(5660, 30), /* Channel 132 */
92 CHAN5G(5680, 31), /* Channel 136 */
93 CHAN5G(5700, 32), /* Channel 140 */
94 /* _We_ call this UNII 3 */
95 CHAN5G(5745, 33), /* Channel 149 */
96 CHAN5G(5765, 34), /* Channel 153 */
97 CHAN5G(5785, 35), /* Channel 157 */
98 CHAN5G(5805, 36), /* Channel 161 */
99 CHAN5G(5825, 37), /* Channel 165 */
100};
101
ce111bad
LR		 102static void ath_cache_conf_rate(struct ath_softc *sc,
103 struct ieee80211_conf *conf)
ff37e337 104{
030bb495
LR		 105 switch (conf->channel->band) {
106 case IEEE80211_BAND_2GHZ:
107 if (conf_is_ht20(conf))
108 sc->cur_rate_table =
109 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
110 else if (conf_is_ht40_minus(conf))
111 sc->cur_rate_table =
112 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
113 else if (conf_is_ht40_plus(conf))
114 sc->cur_rate_table =
115 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 116 else
030bb495
LR		 117 sc->cur_rate_table =
118 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 119 break;
120 case IEEE80211_BAND_5GHZ:
121 if (conf_is_ht20(conf))
122 sc->cur_rate_table =
123 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
124 else if (conf_is_ht40_minus(conf))
125 sc->cur_rate_table =
126 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
127 else if (conf_is_ht40_plus(conf))
128 sc->cur_rate_table =
129 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
130 else
96742256
LR		 131 sc->cur_rate_table =
132 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 133 break;
134 default:
ce111bad 135 BUG_ON(1);
030bb495
LR		 136 break;
137 }
ff37e337
S		 138}
139
140static void ath_update_txpow(struct ath_softc *sc)
141{
142 struct ath_hal *ah = sc->sc_ah;
143 u32 txpow;
144
145 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
146 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
147 /* read back in case value is clamped */
148 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
149 sc->sc_curtxpow = txpow;
150 }
151}
152
153static u8 parse_mpdudensity(u8 mpdudensity)
154{
155 /*
156 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
157 * 0 for no restriction
158 * 1 for 1/4 us
159 * 2 for 1/2 us
160 * 3 for 1 us
161 * 4 for 2 us
162 * 5 for 4 us
163 * 6 for 8 us
164 * 7 for 16 us
165 */
166 switch (mpdudensity) {
167 case 0:
168 return 0;
169 case 1:
170 case 2:
171 case 3:
172 /* Our lower layer calculations limit our precision to
173 1 microsecond */
174 return 1;
175 case 4:
176 return 2;
177 case 5:
178 return 4;
179 case 6:
180 return 8;
181 case 7:
182 return 16;
183 default:
184 return 0;
185 }
186}
187
188static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
189{
190 struct ath_rate_table *rate_table = NULL;
191 struct ieee80211_supported_band *sband;
192 struct ieee80211_rate *rate;
193 int i, maxrates;
194
195 switch (band) {
196 case IEEE80211_BAND_2GHZ:
197 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
198 break;
199 case IEEE80211_BAND_5GHZ:
200 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
201 break;
202 default:
203 break;
204 }
205
206 if (rate_table == NULL)
207 return;
208
209 sband = &sc->sbands[band];
210 rate = sc->rates[band];
211
212 if (rate_table->rate_cnt > ATH_RATE_MAX)
213 maxrates = ATH_RATE_MAX;
214 else
215 maxrates = rate_table->rate_cnt;
216
217 for (i = 0; i < maxrates; i++) {
218 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
219 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 220 if (rate_table->info[i].short_preamble) {
221 rate[i].hw_value_short = rate_table->info[i].ratecode |
222 rate_table->info[i].short_preamble;
223 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
224 }
ff37e337 225 sband->n_bitrates++;
f46730d1 226
04bd4638
S		 227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 229 }
230}
231
ff37e337
S		 232/*
233 * Set/change channels. If the channel is really being changed, it's done
234 * by reseting the chip. To accomplish this we must first cleanup any pending
235 * DMA, then restart stuff.
236*/
237static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
238{
239 struct ath_hal *ah = sc->sc_ah;
240 bool fastcc = true, stopped;
030bb495 241 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 242 struct ieee80211_channel *channel = hw->conf.channel;
243 int r;
ff37e337
S		 244
245 if (sc->sc_flags & SC_OP_INVALID)
246 return -EIO;
247
3cbb5dd7
VN		 248 ath9k_ps_wakeup(sc);
249
c0d7c7af
LR		 250 /*
251 * This is only performed if the channel settings have
252 * actually changed.
253 *
254 * To switch channels clear any pending DMA operations;
255 * wait long enough for the RX fifo to drain, reset the
256 * hardware at the new frequency, and then re-enable
257 * the relevant bits of the h/w.
258 */
259 ath9k_hw_set_interrupts(ah, 0);
043a0405 260 ath_drain_all_txq(sc, false);
c0d7c7af 261 stopped = ath_stoprecv(sc);
ff37e337 262
c0d7c7af
LR		 263 /* XXX: do not flush receive queue here. We don't want
264 * to flush data frames already in queue because of
265 * changing channel. */
ff37e337 266
c0d7c7af
LR		 267 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
268 fastcc = false;
269
270 DPRINTF(sc, ATH_DBG_CONFIG,
271 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
272 sc->sc_ah->ah_curchan->channel,
273 channel->center_freq, sc->tx_chan_width);
ff37e337 274
c0d7c7af
LR		 275 spin_lock_bh(&sc->sc_resetlock);
276
277 r = ath9k_hw_reset(ah, hchan, fastcc);
278 if (r) {
279 DPRINTF(sc, ATH_DBG_FATAL,
280 "Unable to reset channel (%u Mhz) "
281 "reset status %u\n",
282 channel->center_freq, r);
283 spin_unlock_bh(&sc->sc_resetlock);
284 return r;
ff37e337 285 }
c0d7c7af
LR		 286 spin_unlock_bh(&sc->sc_resetlock);
287
288 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
289 sc->sc_flags &= ~SC_OP_FULL_RESET;
290
291 if (ath_startrecv(sc) != 0) {
292 DPRINTF(sc, ATH_DBG_FATAL,
293 "Unable to restart recv logic\n");
294 return -EIO;
295 }
296
297 ath_cache_conf_rate(sc, &hw->conf);
298 ath_update_txpow(sc);
299 ath9k_hw_set_interrupts(ah, sc->sc_imask);
3cbb5dd7 300 ath9k_ps_restore(sc);
ff37e337
S		 301 return 0;
302}
303
304/*
305 * This routine performs the periodic noise floor calibration function
306 * that is used to adjust and optimize the chip performance. This
307 * takes environmental changes (location, temperature) into account.
308 * When the task is complete, it reschedules itself depending on the
309 * appropriate interval that was calculated.
310 */
311static void ath_ani_calibrate(unsigned long data)
312{
313 struct ath_softc *sc;
314 struct ath_hal *ah;
315 bool longcal = false;
316 bool shortcal = false;
317 bool aniflag = false;
318 unsigned int timestamp = jiffies_to_msecs(jiffies);
319 u32 cal_interval;
320
321 sc = (struct ath_softc *)data;
322 ah = sc->sc_ah;
323
324 /*
325 * don't calibrate when we're scanning.
326 * we are most likely not on our home channel.
327 */
b77f483f 328 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 329 return;
330
331 /* Long calibration runs independently of short calibration. */
332 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
333 longcal = true;
04bd4638 334 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 335 sc->sc_ani.sc_longcal_timer = timestamp;
336 }
337
338 /* Short calibration applies only while sc_caldone is false */
339 if (!sc->sc_ani.sc_caldone) {
340 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
341 ATH_SHORT_CALINTERVAL) {
342 shortcal = true;
04bd4638 343 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 344 sc->sc_ani.sc_shortcal_timer = timestamp;
345 sc->sc_ani.sc_resetcal_timer = timestamp;
346 }
347 } else {
348 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
349 ATH_RESTART_CALINTERVAL) {
c9e27d94 350 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 351 if (sc->sc_ani.sc_caldone)
352 sc->sc_ani.sc_resetcal_timer = timestamp;
353 }
354 }
355
356 /* Verify whether we must check ANI */
357 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
358 ATH_ANI_POLLINTERVAL) {
359 aniflag = true;
360 sc->sc_ani.sc_checkani_timer = timestamp;
361 }
362
363 /* Skip all processing if there's nothing to do. */
364 if (longcal || shortcal || aniflag) {
365 /* Call ANI routine if necessary */
366 if (aniflag)
367 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
368 ah->ah_curchan);
369
370 /* Perform calibration if necessary */
371 if (longcal || shortcal) {
372 bool iscaldone = false;
373
374 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
375 sc->sc_rx_chainmask, longcal,
376 &iscaldone)) {
377 if (longcal)
378 sc->sc_ani.sc_noise_floor =
379 ath9k_hw_getchan_noise(ah,
380 ah->ah_curchan);
381
382 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 383 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 384 ah->ah_curchan->channel,
385 ah->ah_curchan->channelFlags,
386 sc->sc_ani.sc_noise_floor);
387 } else {
388 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 389 "calibrate chan %u/%x failed\n",
ff37e337
S		 390 ah->ah_curchan->channel,
391 ah->ah_curchan->channelFlags);
392 }
393 sc->sc_ani.sc_caldone = iscaldone;
394 }
395 }
396
397 /*
398 * Set timer interval based on previous results.
399 * The interval must be the shortest necessary to satisfy ANI,
400 * short calibration and long calibration.
401 */
aac9207e
S		 402 cal_interval = ATH_LONG_CALINTERVAL;
403 if (sc->sc_ah->ah_config.enable_ani)
404 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 405 if (!sc->sc_ani.sc_caldone)
406 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
407
408 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
409}
410
411/*
412 * Update tx/rx chainmask. For legacy association,
413 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 414 * the chainmask configuration, for bt coexistence, use
415 * the chainmask configuration even in legacy mode.
ff37e337
S		 416 */
417static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
418{
419 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 420 if (is_ht ||
421 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 422 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
423 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
424 } else {
425 sc->sc_tx_chainmask = 1;
426 sc->sc_rx_chainmask = 1;
427 }
428
04bd4638
S		 429 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
430 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 431}
432
433static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
434{
435 struct ath_node *an;
436
437 an = (struct ath_node *)sta->drv_priv;
438
439 if (sc->sc_flags & SC_OP_TXAGGR)
440 ath_tx_node_init(sc, an);
441
442 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
443 sta->ht_cap.ampdu_factor);
444 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
445}
446
447static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
448{
449 struct ath_node *an = (struct ath_node *)sta->drv_priv;
450
451 if (sc->sc_flags & SC_OP_TXAGGR)
452 ath_tx_node_cleanup(sc, an);
453}
454
455static void ath9k_tasklet(unsigned long data)
456{
457 struct ath_softc *sc = (struct ath_softc *)data;
458 u32 status = sc->sc_intrstatus;
459
460 if (status & ATH9K_INT_FATAL) {
461 /* need a chip reset */
462 ath_reset(sc, false);
463 return;
464 } else {
465
466 if (status &
467 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 468 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 469 ath_rx_tasklet(sc, 0);
b77f483f 470 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 471 }
472 /* XXX: optimize this */
473 if (status & ATH9K_INT_TX)
474 ath_tx_tasklet(sc);
475 }
476
477 /* re-enable hardware interrupt */
478 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
479}
480
6baff7f9 481irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 482{
483 struct ath_softc *sc = dev;
484 struct ath_hal *ah = sc->sc_ah;
485 enum ath9k_int status;
486 bool sched = false;
487
488 do {
489 if (sc->sc_flags & SC_OP_INVALID) {
490 /*
491 * The hardware is not ready/present, don't
492 * touch anything. Note this can happen early
493 * on if the IRQ is shared.
494 */
495 return IRQ_NONE;
496 }
497 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
498 return IRQ_NONE;
499 }
500
501 /*
502 * Figure out the reason(s) for the interrupt. Note
503 * that the hal returns a pseudo-ISR that may include
504 * bits we haven't explicitly enabled so we mask the
505 * value to insure we only process bits we requested.
506 */
507 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
508
509 status &= sc->sc_imask; /* discard unasked-for bits */
510
511 /*
512 * If there are no status bits set, then this interrupt was not
513 * for me (should have been caught above).
514 */
515 if (!status)
516 return IRQ_NONE;
517
518 sc->sc_intrstatus = status;
519
520 if (status & ATH9K_INT_FATAL) {
521 /* need a chip reset */
522 sched = true;
523 } else if (status & ATH9K_INT_RXORN) {
524 /* need a chip reset */
525 sched = true;
526 } else {
527 if (status & ATH9K_INT_SWBA) {
528 /* schedule a tasklet for beacon handling */
529 tasklet_schedule(&sc->bcon_tasklet);
530 }
531 if (status & ATH9K_INT_RXEOL) {
532 /*
533 * NB: the hardware should re-read the link when
534 * RXE bit is written, but it doesn't work
535 * at least on older hardware revs.
536 */
537 sched = true;
538 }
539
540 if (status & ATH9K_INT_TXURN)
541 /* bump tx trigger level */
542 ath9k_hw_updatetxtriglevel(ah, true);
543 /* XXX: optimize this */
544 if (status & ATH9K_INT_RX)
545 sched = true;
546 if (status & ATH9K_INT_TX)
547 sched = true;
548 if (status & ATH9K_INT_BMISS)
549 sched = true;
550 /* carrier sense timeout */
551 if (status & ATH9K_INT_CST)
552 sched = true;
553 if (status & ATH9K_INT_MIB) {
554 /*
555 * Disable interrupts until we service the MIB
556 * interrupt; otherwise it will continue to
557 * fire.
558 */
559 ath9k_hw_set_interrupts(ah, 0);
560 /*
561 * Let the hal handle the event. We assume
562 * it will clear whatever condition caused
563 * the interrupt.
564 */
565 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
566 ath9k_hw_set_interrupts(ah, sc->sc_imask);
567 }
568 if (status & ATH9K_INT_TIM_TIMER) {
569 if (!(ah->ah_caps.hw_caps &
570 ATH9K_HW_CAP_AUTOSLEEP)) {
571 /* Clear RxAbort bit so that we can
572 * receive frames */
3cbb5dd7 573 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 574 ath9k_hw_setrxabort(ah, 0);
575 sched = true;
3cbb5dd7 576 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 577 }
578 }
579 }
580 } while (0);
581
817e11de
S		 582 ath_debug_stat_interrupt(sc, status);
583
ff37e337
S		 584 if (sched) {
585 /* turn off every interrupt except SWBA */
586 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
587 tasklet_schedule(&sc->intr_tq);
588 }
589
590 return IRQ_HANDLED;
591}
592
f078f209 593static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 594 struct ieee80211_channel *chan,
094d05dc 595 enum nl80211_channel_type channel_type)
f078f209
LR		 596{
597 u32 chanmode = 0;
f078f209
LR		 598
599 switch (chan->band) {
600 case IEEE80211_BAND_2GHZ:
094d05dc
S		 601 switch(channel_type) {
602 case NL80211_CHAN_NO_HT:
603 case NL80211_CHAN_HT20:
f078f209 604 chanmode = CHANNEL_G_HT20;
094d05dc
S		 605 break;
606 case NL80211_CHAN_HT40PLUS:
f078f209 607 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 608 break;
609 case NL80211_CHAN_HT40MINUS:
f078f209 610 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 611 break;
612 }
f078f209
LR		 613 break;
614 case IEEE80211_BAND_5GHZ:
094d05dc
S		 615 switch(channel_type) {
616 case NL80211_CHAN_NO_HT:
617 case NL80211_CHAN_HT20:
f078f209 618 chanmode = CHANNEL_A_HT20;
094d05dc
S		 619 break;
620 case NL80211_CHAN_HT40PLUS:
f078f209 621 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 622 break;
623 case NL80211_CHAN_HT40MINUS:
f078f209 624 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 625 break;
626 }
f078f209
LR		 627 break;
628 default:
629 break;
630 }
631
632 return chanmode;
633}
634
ff37e337
S		 635static int ath_keyset(struct ath_softc *sc, u16 keyix,
636 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
637{
638 bool status;
639
640 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
641 keyix, hk, mac, false);
642
643 return status != false;
644}
f078f209 645
6ace2891 646static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 647 struct ath9k_keyval *hk,
648 const u8 *addr)
649{
6ace2891
JM		 650 const u8 *key_rxmic;
651 const u8 *key_txmic;
f078f209 652
6ace2891
JM		 653 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
654 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 655
656 if (addr == NULL) {
657 /* Group key installation */
6ace2891
JM		 658 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
659 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 660 }
661 if (!sc->sc_splitmic) {
662 /*
663 * data key goes at first index,
664 * the hal handles the MIC keys at index+64.
665 */
666 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
667 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 668 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 669 }
670 /*
671 * TX key goes at first index, RX key at +32.
672 * The hal handles the MIC keys at index+64.
673 */
674 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 675 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 676 /* Txmic entry failed. No need to proceed further */
677 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 678 "Setting TX MIC Key Failed\n");
f078f209
LR		 679 return 0;
680 }
681
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 /* XXX delete tx key on failure? */
6ace2891
JM		 684 return ath_keyset(sc, keyix + 32, hk, addr);
685}
686
687static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
688{
689 int i;
690
691 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
692 if (test_bit(i, sc->sc_keymap) ||
693 test_bit(i + 64, sc->sc_keymap))
694 continue; /* At least one part of TKIP key allocated */
695 if (sc->sc_splitmic &&
696 (test_bit(i + 32, sc->sc_keymap) ||
697 test_bit(i + 64 + 32, sc->sc_keymap)))
698 continue; /* At least one part of TKIP key allocated */
699
700 /* Found a free slot for a TKIP key */
701 return i;
702 }
703 return -1;
704}
705
706static int ath_reserve_key_cache_slot(struct ath_softc *sc)
707{
708 int i;
709
710 /* First, try to find slots that would not be available for TKIP. */
711 if (sc->sc_splitmic) {
712 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
713 if (!test_bit(i, sc->sc_keymap) &&
714 (test_bit(i + 32, sc->sc_keymap) ||
715 test_bit(i + 64, sc->sc_keymap) ||
716 test_bit(i + 64 + 32, sc->sc_keymap)))
717 return i;
718 if (!test_bit(i + 32, sc->sc_keymap) &&
719 (test_bit(i, sc->sc_keymap) ||
720 test_bit(i + 64, sc->sc_keymap) ||
721 test_bit(i + 64 + 32, sc->sc_keymap)))
722 return i + 32;
723 if (!test_bit(i + 64, sc->sc_keymap) &&
724 (test_bit(i , sc->sc_keymap) ||
725 test_bit(i + 32, sc->sc_keymap) ||
726 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 727 return i + 64;
6ace2891
JM		 728 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
729 (test_bit(i, sc->sc_keymap) ||
730 test_bit(i + 32, sc->sc_keymap) ||
731 test_bit(i + 64, sc->sc_keymap)))
ea612132 732 return i + 64 + 32;
6ace2891
JM		 733 }
734 } else {
735 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
736 if (!test_bit(i, sc->sc_keymap) &&
737 test_bit(i + 64, sc->sc_keymap))
738 return i;
739 if (test_bit(i, sc->sc_keymap) &&
740 !test_bit(i + 64, sc->sc_keymap))
741 return i + 64;
742 }
743 }
744
745 /* No partially used TKIP slots, pick any available slot */
746 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 747 /* Do not allow slots that could be needed for TKIP group keys
748 * to be used. This limitation could be removed if we know that
749 * TKIP will not be used. */
750 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
751 continue;
752 if (sc->sc_splitmic) {
753 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
754 continue;
755 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
756 continue;
757 }
758
6ace2891
JM		 759 if (!test_bit(i, sc->sc_keymap))
760 return i; /* Found a free slot for a key */
761 }
762
763 /* No free slot found */
764 return -1;
f078f209
LR		 765}
766
767static int ath_key_config(struct ath_softc *sc,
dc822b5d 768 struct ieee80211_sta *sta,
f078f209
LR		 769 struct ieee80211_key_conf *key)
770{
f078f209
LR		 771 struct ath9k_keyval hk;
772 const u8 *mac = NULL;
773 int ret = 0;
6ace2891 774 int idx;
f078f209
LR		 775
776 memset(&hk, 0, sizeof(hk));
777
778 switch (key->alg) {
779 case ALG_WEP:
780 hk.kv_type = ATH9K_CIPHER_WEP;
781 break;
782 case ALG_TKIP:
783 hk.kv_type = ATH9K_CIPHER_TKIP;
784 break;
785 case ALG_CCMP:
786 hk.kv_type = ATH9K_CIPHER_AES_CCM;
787 break;
788 default:
ca470b29 789 return -EOPNOTSUPP;
f078f209
LR		 790 }
791
6ace2891 792 hk.kv_len = key->keylen;
f078f209
LR		 793 memcpy(hk.kv_val, key->key, key->keylen);
794
6ace2891
JM		 795 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
796 /* For now, use the default keys for broadcast keys. This may
797 * need to change with virtual interfaces. */
798 idx = key->keyidx;
799 } else if (key->keyidx) {
800 struct ieee80211_vif *vif;
f078f209 801
dc822b5d
JB		 802 if (WARN_ON(!sta))
803 return -EOPNOTSUPP;
804 mac = sta->addr;
805
6ace2891
JM		 806 vif = sc->sc_vaps[0];
807 if (vif->type != NL80211_IFTYPE_AP) {
808 /* Only keyidx 0 should be used with unicast key, but
809 * allow this for client mode for now. */
810 idx = key->keyidx;
811 } else
812 return -EIO;
f078f209 813 } else {
dc822b5d
JB		 814 if (WARN_ON(!sta))
815 return -EOPNOTSUPP;
816 mac = sta->addr;
817
6ace2891
JM		 818 if (key->alg == ALG_TKIP)
819 idx = ath_reserve_key_cache_slot_tkip(sc);
820 else
821 idx = ath_reserve_key_cache_slot(sc);
822 if (idx < 0)
ca470b29 823 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 824 }
825
826 if (key->alg == ALG_TKIP)
6ace2891 827 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 828 else
6ace2891 829 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 830
831 if (!ret)
832 return -EIO;
833
6ace2891
JM		 834 set_bit(idx, sc->sc_keymap);
835 if (key->alg == ALG_TKIP) {
836 set_bit(idx + 64, sc->sc_keymap);
837 if (sc->sc_splitmic) {
838 set_bit(idx + 32, sc->sc_keymap);
839 set_bit(idx + 64 + 32, sc->sc_keymap);
840 }
841 }
842
843 return idx;
f078f209
LR		 844}
845
846static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
847{
6ace2891
JM		 848 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
849 if (key->hw_key_idx < IEEE80211_WEP_NKID)
850 return;
851
852 clear_bit(key->hw_key_idx, sc->sc_keymap);
853 if (key->alg != ALG_TKIP)
854 return;
f078f209 855
6ace2891
JM		 856 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
857 if (sc->sc_splitmic) {
858 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
859 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
860 }
f078f209
LR		 861}
862
eb2599ca
S		 863static void setup_ht_cap(struct ath_softc *sc,
864 struct ieee80211_sta_ht_cap *ht_info)
f078f209 865{
60653678
S		 866#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
867#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 868
d9fe60de
JB		 869 ht_info->ht_supported = true;
870 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
871 IEEE80211_HT_CAP_SM_PS |
872 IEEE80211_HT_CAP_SGI_40 |
873 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 874
60653678
S		 875 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
876 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 877
d9fe60de
JB		 878 /* set up supported mcs set */
879 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca
S		 880
881 switch(sc->sc_rx_chainmask) {
882 case 1:
883 ht_info->mcs.rx_mask[0] = 0xff;
884 break;
3c457265 885 case 3:
eb2599ca
S		 886 case 5:
887 case 7:
888 default:
889 ht_info->mcs.rx_mask[0] = 0xff;
890 ht_info->mcs.rx_mask[1] = 0xff;
891 break;
892 }
893
d9fe60de 894 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 895}
896
8feceb67 897static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 898 struct ieee80211_vif *vif,
8feceb67 899 struct ieee80211_bss_conf *bss_conf)
f078f209 900{
5640b08e 901 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 902
8feceb67 903 if (bss_conf->assoc) {
094d05dc
S		 904 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
905 bss_conf->aid, sc->sc_curbssid);
f078f209 906
8feceb67 907 /* New association, store aid */
d97809db 908 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 909 sc->sc_curaid = bss_conf->aid;
910 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
911 sc->sc_curaid);
912 }
f078f209 913
8feceb67
VT		 914 /* Configure the beacon */
915 ath_beacon_config(sc, 0);
916 sc->sc_flags |= SC_OP_BEACONS;
f078f209 917
8feceb67
VT		 918 /* Reset rssi stats */
919 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
920 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 923
6f255425
LR		 924 /* Start ANI */
925 mod_timer(&sc->sc_ani.timer,
926 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
927
8feceb67 928 } else {
04bd4638 929 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 930 sc->sc_curaid = 0;
f078f209 931 }
8feceb67 932}
f078f209 933
8feceb67
VT		 934/********************************/
935/* LED functions */
936/********************************/
f078f209 937
f2bffa7e
VT		 938static void ath_led_blink_work(struct work_struct *work)
939{
940 struct ath_softc *sc = container_of(work, struct ath_softc,
941 ath_led_blink_work.work);
942
943 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
944 return;
945 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
946 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
947
948 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
949 (sc->sc_flags & SC_OP_LED_ON) ?
950 msecs_to_jiffies(sc->led_off_duration) :
951 msecs_to_jiffies(sc->led_on_duration));
952
953 sc->led_on_duration =
954 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
955 sc->led_off_duration =
956 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
957 sc->led_on_cnt = sc->led_off_cnt = 0;
958 if (sc->sc_flags & SC_OP_LED_ON)
959 sc->sc_flags &= ~SC_OP_LED_ON;
960 else
961 sc->sc_flags |= SC_OP_LED_ON;
962}
963
8feceb67
VT		 964static void ath_led_brightness(struct led_classdev *led_cdev,
965 enum led_brightness brightness)
966{
967 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
968 struct ath_softc *sc = led->sc;
f078f209 969
8feceb67
VT		 970 switch (brightness) {
971 case LED_OFF:
972 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 973 led->led_type == ATH_LED_RADIO) {
974 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
975 (led->led_type == ATH_LED_RADIO));
8feceb67 976 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 977 if (led->led_type == ATH_LED_RADIO)
978 sc->sc_flags &= ~SC_OP_LED_ON;
979 } else {
980 sc->led_off_cnt++;
981 }
8feceb67
VT		 982 break;
983 case LED_FULL:
f2bffa7e 984 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 985 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 986 queue_delayed_work(sc->hw->workqueue,
987 &sc->ath_led_blink_work, 0);
988 } else if (led->led_type == ATH_LED_RADIO) {
989 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
990 sc->sc_flags |= SC_OP_LED_ON;
991 } else {
992 sc->led_on_cnt++;
993 }
8feceb67
VT		 994 break;
995 default:
996 break;
f078f209 997 }
8feceb67 998}
f078f209 999
8feceb67
VT		 1000static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1001 char *trigger)
1002{
1003 int ret;
f078f209 1004
8feceb67
VT		 1005 led->sc = sc;
1006 led->led_cdev.name = led->name;
1007 led->led_cdev.default_trigger = trigger;
1008 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1009
8feceb67
VT		 1010 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1011 if (ret)
1012 DPRINTF(sc, ATH_DBG_FATAL,
1013 "Failed to register led:%s", led->name);
1014 else
1015 led->registered = 1;
1016 return ret;
1017}
f078f209 1018
8feceb67
VT		 1019static void ath_unregister_led(struct ath_led *led)
1020{
1021 if (led->registered) {
1022 led_classdev_unregister(&led->led_cdev);
1023 led->registered = 0;
f078f209 1024 }
f078f209
LR		 1025}
1026
8feceb67 1027static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1028{
f2bffa7e 1029 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1030 ath_unregister_led(&sc->assoc_led);
1031 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1032 ath_unregister_led(&sc->tx_led);
1033 ath_unregister_led(&sc->rx_led);
1034 ath_unregister_led(&sc->radio_led);
1035 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1036}
f078f209 1037
8feceb67
VT		 1038static void ath_init_leds(struct ath_softc *sc)
1039{
1040 char *trigger;
1041 int ret;
f078f209 1042
8feceb67
VT		 1043 /* Configure gpio 1 for output */
1044 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1045 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1046 /* LED off, active low */
1047 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1048
f2bffa7e
VT		 1049 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1050
8feceb67
VT		 1051 trigger = ieee80211_get_radio_led_name(sc->hw);
1052 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1053 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1054 ret = ath_register_led(sc, &sc->radio_led, trigger);
1055 sc->radio_led.led_type = ATH_LED_RADIO;
1056 if (ret)
1057 goto fail;
7dcfdcd9 1058
8feceb67
VT		 1059 trigger = ieee80211_get_assoc_led_name(sc->hw);
1060 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1061 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1062 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1063 sc->assoc_led.led_type = ATH_LED_ASSOC;
1064 if (ret)
1065 goto fail;
f078f209 1066
8feceb67
VT		 1067 trigger = ieee80211_get_tx_led_name(sc->hw);
1068 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1069 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1070 ret = ath_register_led(sc, &sc->tx_led, trigger);
1071 sc->tx_led.led_type = ATH_LED_TX;
1072 if (ret)
1073 goto fail;
f078f209 1074
8feceb67
VT		 1075 trigger = ieee80211_get_rx_led_name(sc->hw);
1076 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1077 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1078 ret = ath_register_led(sc, &sc->rx_led, trigger);
1079 sc->rx_led.led_type = ATH_LED_RX;
1080 if (ret)
1081 goto fail;
f078f209 1082
8feceb67
VT		 1083 return;
1084
1085fail:
1086 ath_deinit_leds(sc);
f078f209
LR		 1087}
1088
e97275cb 1089#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1090
500c064d
VT		 1091/*******************/
1092/* Rfkill */
1093/*******************/
1094
1095static void ath_radio_enable(struct ath_softc *sc)
1096{
1097 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1098 struct ieee80211_channel *channel = sc->hw->conf.channel;
1099 int r;
500c064d 1100
3cbb5dd7 1101 ath9k_ps_wakeup(sc);
500c064d 1102 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1103
1104 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1105
1106 if (r) {
500c064d 1107 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1108 "Unable to reset channel %u (%uMhz) ",
1109 "reset status %u\n",
1110 channel->center_freq, r);
500c064d
VT		 1111 }
1112 spin_unlock_bh(&sc->sc_resetlock);
1113
1114 ath_update_txpow(sc);
1115 if (ath_startrecv(sc) != 0) {
1116 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1117 "Unable to restart recv logic\n");
500c064d
VT		 1118 return;
1119 }
1120
1121 if (sc->sc_flags & SC_OP_BEACONS)
1122 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1123
1124 /* Re-Enable interrupts */
1125 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1126
1127 /* Enable LED */
1128 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1129 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1130 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1131
1132 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1133 ath9k_ps_restore(sc);
500c064d
VT		 1134}
1135
1136static void ath_radio_disable(struct ath_softc *sc)
1137{
1138 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1139 struct ieee80211_channel *channel = sc->hw->conf.channel;
1140 int r;
500c064d 1141
3cbb5dd7 1142 ath9k_ps_wakeup(sc);
500c064d
VT		 1143 ieee80211_stop_queues(sc->hw);
1144
1145 /* Disable LED */
1146 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1147 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1148
1149 /* Disable interrupts */
1150 ath9k_hw_set_interrupts(ah, 0);
1151
043a0405 1152 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1153 ath_stoprecv(sc); /* turn off frame recv */
1154 ath_flushrecv(sc); /* flush recv queue */
1155
1156 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1157 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1158 if (r) {
500c064d 1159 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1160 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1161 "reset status %u\n",
1162 channel->center_freq, r);
500c064d
VT		 1163 }
1164 spin_unlock_bh(&sc->sc_resetlock);
1165
1166 ath9k_hw_phy_disable(ah);
1167 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1168 ath9k_ps_restore(sc);
500c064d
VT		 1169}
1170
1171static bool ath_is_rfkill_set(struct ath_softc *sc)
1172{
1173 struct ath_hal *ah = sc->sc_ah;
1174
1175 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1176 ah->ah_rfkill_polarity;
1177}
1178
1179/* h/w rfkill poll function */
1180static void ath_rfkill_poll(struct work_struct *work)
1181{
1182 struct ath_softc *sc = container_of(work, struct ath_softc,
1183 rf_kill.rfkill_poll.work);
1184 bool radio_on;
1185
1186 if (sc->sc_flags & SC_OP_INVALID)
1187 return;
1188
1189 radio_on = !ath_is_rfkill_set(sc);
1190
1191 /*
1192 * enable/disable radio only when there is a
1193 * state change in RF switch
1194 */
1195 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1196 enum rfkill_state state;
1197
1198 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1199 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1200 : RFKILL_STATE_HARD_BLOCKED;
1201 } else if (radio_on) {
1202 ath_radio_enable(sc);
1203 state = RFKILL_STATE_UNBLOCKED;
1204 } else {
1205 ath_radio_disable(sc);
1206 state = RFKILL_STATE_HARD_BLOCKED;
1207 }
1208
1209 if (state == RFKILL_STATE_HARD_BLOCKED)
1210 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1211 else
1212 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1213
1214 rfkill_force_state(sc->rf_kill.rfkill, state);
1215 }
1216
1217 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1218 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1219}
1220
1221/* s/w rfkill handler */
1222static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1223{
1224 struct ath_softc *sc = data;
1225
1226 switch (state) {
1227 case RFKILL_STATE_SOFT_BLOCKED:
1228 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1229 SC_OP_RFKILL_SW_BLOCKED)))
1230 ath_radio_disable(sc);
1231 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1232 return 0;
1233 case RFKILL_STATE_UNBLOCKED:
1234 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1235 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1236 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1237 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1238 "radio as it is disabled by h/w\n");
500c064d
VT		 1239 return -EPERM;
1240 }
1241 ath_radio_enable(sc);
1242 }
1243 return 0;
1244 default:
1245 return -EINVAL;
1246 }
1247}
1248
1249/* Init s/w rfkill */
1250static int ath_init_sw_rfkill(struct ath_softc *sc)
1251{
1252 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1253 RFKILL_TYPE_WLAN);
1254 if (!sc->rf_kill.rfkill) {
1255 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1256 return -ENOMEM;
1257 }
1258
1259 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1260 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1261 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1262 sc->rf_kill.rfkill->data = sc;
1263 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1264 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1265 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1266
1267 return 0;
1268}
1269
1270/* Deinitialize rfkill */
1271static void ath_deinit_rfkill(struct ath_softc *sc)
1272{
1273 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1274 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1275
1276 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1277 rfkill_unregister(sc->rf_kill.rfkill);
1278 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1279 sc->rf_kill.rfkill = NULL;
1280 }
1281}
9c84b797
S		 1282
1283static int ath_start_rfkill_poll(struct ath_softc *sc)
1284{
1285 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1286 queue_delayed_work(sc->hw->workqueue,
1287 &sc->rf_kill.rfkill_poll, 0);
1288
1289 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1290 if (rfkill_register(sc->rf_kill.rfkill)) {
1291 DPRINTF(sc, ATH_DBG_FATAL,
1292 "Unable to register rfkill\n");
1293 rfkill_free(sc->rf_kill.rfkill);
1294
1295 /* Deinitialize the device */
39c3c2f2 1296 ath_cleanup(sc);
9c84b797
S		 1297 return -EIO;
1298 } else {
1299 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1300 }
1301 }
1302
1303 return 0;
1304}
500c064d
VT		 1305#endif /* CONFIG_RFKILL */
1306
6baff7f9 1307void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1308{
1309 ath_detach(sc);
1310 free_irq(sc->irq, sc);
1311 ath_bus_cleanup(sc);
1312 ieee80211_free_hw(sc->hw);
1313}
1314
6baff7f9 1315void ath_detach(struct ath_softc *sc)
f078f209 1316{
8feceb67 1317 struct ieee80211_hw *hw = sc->hw;
9c84b797 1318 int i = 0;
f078f209 1319
3cbb5dd7
VN		 1320 ath9k_ps_wakeup(sc);
1321
04bd4638 1322 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1323
e97275cb 1324#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1325 ath_deinit_rfkill(sc);
1326#endif
3fcdfb4b
VT		 1327 ath_deinit_leds(sc);
1328
1329 ieee80211_unregister_hw(hw);
8feceb67
VT		 1330 ath_rx_cleanup(sc);
1331 ath_tx_cleanup(sc);
f078f209 1332
9c84b797
S		 1333 tasklet_kill(&sc->intr_tq);
1334 tasklet_kill(&sc->bcon_tasklet);
f078f209 1335
9c84b797
S		 1336 if (!(sc->sc_flags & SC_OP_INVALID))
1337 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1338
9c84b797
S		 1339 /* cleanup tx queues */
1340 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1341 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1342 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1343
1344 ath9k_hw_detach(sc->sc_ah);
826d2680 1345 ath9k_exit_debug(sc);
3cbb5dd7 1346 ath9k_ps_restore(sc);
f078f209
LR		 1347}
1348
ff37e337
S		 1349static int ath_init(u16 devid, struct ath_softc *sc)
1350{
1351 struct ath_hal *ah = NULL;
1352 int status;
1353 int error = 0, i;
1354 int csz = 0;
1355
1356 /* XXX: hardware will not be ready until ath_open() being called */
1357 sc->sc_flags |= SC_OP_INVALID;
88b126af 1358
826d2680
S		 1359 if (ath9k_init_debug(sc) < 0)
1360 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1361
1362 spin_lock_init(&sc->sc_resetlock);
aa33de09 1363 mutex_init(&sc->mutex);
ff37e337
S		 1364 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1365 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1366 (unsigned long)sc);
1367
1368 /*
1369 * Cache line size is used to size and align various
1370 * structures used to communicate with the hardware.
1371 */
88d15707 1372 ath_read_cachesize(sc, &csz);
ff37e337
S		 1373 /* XXX assert csz is non-zero */
1374 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1375
1376 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1377 if (ah == NULL) {
1378 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1379 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1380 error = -ENXIO;
1381 goto bad;
1382 }
1383 sc->sc_ah = ah;
1384
1385 /* Get the hardware key cache size. */
1386 sc->sc_keymax = ah->ah_caps.keycache_size;
1387 if (sc->sc_keymax > ATH_KEYMAX) {
1388 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1389 "Warning, using only %u entries in %u key cache\n",
1390 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1391 sc->sc_keymax = ATH_KEYMAX;
1392 }
1393
1394 /*
1395 * Reset the key cache since some parts do not
1396 * reset the contents on initial power up.
1397 */
1398 for (i = 0; i < sc->sc_keymax; i++)
1399 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1400
5f8e077c 1401 if (ath9k_regd_init(sc->sc_ah))
ff37e337
S		 1402 goto bad;
1403
1404 /* default to MONITOR mode */
d97809db
CM		 1405 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1406
ff37e337
S		 1407 /* Setup rate tables */
1408
1409 ath_rate_attach(sc);
1410 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1411 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1412
1413 /*
1414 * Allocate hardware transmit queues: one queue for
1415 * beacon frames and one data queue for each QoS
1416 * priority. Note that the hal handles reseting
1417 * these queues at the needed time.
1418 */
b77f483f
S		 1419 sc->beacon.beaconq = ath_beaconq_setup(ah);
1420 if (sc->beacon.beaconq == -1) {
ff37e337 1421 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1422 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1423 error = -EIO;
1424 goto bad2;
1425 }
b77f483f
S		 1426 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1427 if (sc->beacon.cabq == NULL) {
ff37e337 1428 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1429 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1430 error = -EIO;
1431 goto bad2;
1432 }
1433
1434 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1435 ath_cabq_update(sc);
1436
b77f483f
S		 1437 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1438 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1439
1440 /* Setup data queues */
1441 /* NB: ensure BK queue is the lowest priority h/w queue */
1442 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1443 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1444 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1445 error = -EIO;
1446 goto bad2;
1447 }
1448
1449 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1450 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1451 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1452 error = -EIO;
1453 goto bad2;
1454 }
1455 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1456 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1457 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1458 error = -EIO;
1459 goto bad2;
1460 }
1461 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1462 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1463 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1464 error = -EIO;
1465 goto bad2;
1466 }
1467
1468 /* Initializes the noise floor to a reasonable default value.
1469 * Later on this will be updated during ANI processing. */
1470
1471 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1472 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1473
1474 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1475 ATH9K_CIPHER_TKIP, NULL)) {
1476 /*
1477 * Whether we should enable h/w TKIP MIC.
1478 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1479 * report WMM capable, so it's always safe to turn on
1480 * TKIP MIC in this case.
1481 */
1482 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1483 0, 1, NULL);
1484 }
1485
1486 /*
1487 * Check whether the separate key cache entries
1488 * are required to handle both tx+rx MIC keys.
1489 * With split mic keys the number of stations is limited
1490 * to 27 otherwise 59.
1491 */
1492 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493 ATH9K_CIPHER_TKIP, NULL)
1494 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1495 ATH9K_CIPHER_MIC, NULL)
1496 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1497 0, NULL))
1498 sc->sc_splitmic = 1;
1499
1500 /* turn on mcast key search if possible */
1501 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1502 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1503 1, NULL);
1504
1505 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1506 sc->sc_config.txpowlimit_override = 0;
1507
1508 /* 11n Capabilities */
1509 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1510 sc->sc_flags |= SC_OP_TXAGGR;
1511 sc->sc_flags |= SC_OP_RXAGGR;
1512 }
1513
1514 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1515 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1516
1517 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1518 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1519
1520 ath9k_hw_getmac(ah, sc->sc_myaddr);
1521 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1522 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1523 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1524 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1525 }
1526
b77f483f 1527 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1528
1529 /* initialize beacon slots */
b77f483f
S		 1530 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1531 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1532
1533 /* save MISC configurations */
1534 sc->sc_config.swBeaconProcess = 1;
1535
ff37e337
S		 1536 /* setup channels and rates */
1537
5f8e077c 1538 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1539 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1540 sc->rates[IEEE80211_BAND_2GHZ];
1541 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1542 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1543 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337
S		 1544
1545 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
5f8e077c 1546 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1547 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1548 sc->rates[IEEE80211_BAND_5GHZ];
1549 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1550 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1551 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1552 }
1553
c97c92d9
VT		 1554 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1555 ath9k_hw_btcoex_enable(sc->sc_ah);
1556
ff37e337
S		 1557 return 0;
1558bad2:
1559 /* cleanup tx queues */
1560 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1561 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1562 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1563bad:
1564 if (ah)
1565 ath9k_hw_detach(ah);
1566
1567 return error;
1568}
1569
6baff7f9 1570int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1571{
8feceb67
VT		 1572 struct ieee80211_hw *hw = sc->hw;
1573 int error = 0;
f078f209 1574
04bd4638 1575 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1576
8feceb67
VT		 1577 error = ath_init(devid, sc);
1578 if (error != 0)
1579 return error;
f078f209 1580
8feceb67 1581 /* get mac address from hardware and set in mac80211 */
f078f209 1582
8feceb67 1583 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1584
9c84b797
S		 1585 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1586 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1587 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1588 IEEE80211_HW_AMPDU_AGGREGATION |
1589 IEEE80211_HW_SUPPORTS_PS |
1590 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1591
0ced0e17
JM		 1592 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1593 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1594
9c84b797
S		 1595 hw->wiphy->interface_modes =
1596 BIT(NL80211_IFTYPE_AP) |
1597 BIT(NL80211_IFTYPE_STATION) |
1598 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1599
5f8e077c
LR		 1600 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1601 hw->wiphy->strict_regulatory = true;
1602
8feceb67 1603 hw->queues = 4;
e63835b0
S		 1604 hw->max_rates = 4;
1605 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1606 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1607 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1608
8feceb67 1609 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1610
9c84b797 1611 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1612 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
9c84b797 1613 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
eb2599ca 1614 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1615 }
1616
1617 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1618 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1619 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1620 &sc->sbands[IEEE80211_BAND_5GHZ];
1621
db93e7b5
SB		 1622 /* initialize tx/rx engine */
1623 error = ath_tx_init(sc, ATH_TXBUF);
1624 if (error != 0)
1625 goto detach;
8feceb67 1626
db93e7b5
SB		 1627 error = ath_rx_init(sc, ATH_RXBUF);
1628 if (error != 0)
1629 goto detach;
8feceb67 1630
e97275cb 1631#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1632 /* Initialze h/w Rfkill */
1633 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1634 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1635
1636 /* Initialize s/w rfkill */
1637 if (ath_init_sw_rfkill(sc))
1638 goto detach;
1639#endif
1640
5f8e077c
LR		 1641 if (ath9k_is_world_regd(sc->sc_ah)) {
1642 /* Anything applied here (prior to wiphy registratoin) gets
1643 * saved on the wiphy orig_* parameters */
1644 const struct ieee80211_regdomain *regd =
1645 ath9k_world_regdomain(sc->sc_ah);
1646 hw->wiphy->custom_regulatory = true;
1647 hw->wiphy->strict_regulatory = false;
1648 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1649 ath9k_reg_apply_radar_flags(hw->wiphy);
1650 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1651 } else {
1652 /* This gets applied in the case of the absense of CRDA,
1653 * its our own custom world regulatory domain, similar to
1654 * cfg80211's but we enable passive scanning */
1655 const struct ieee80211_regdomain *regd =
1656 ath9k_default_world_regdomain();
1657 wiphy_apply_custom_regulatory(sc->hw->wiphy, regd);
1658 ath9k_reg_apply_radar_flags(hw->wiphy);
1659 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1660 }
1661
db93e7b5 1662 error = ieee80211_register_hw(hw);
8feceb67 1663
5f8e077c
LR		 1664 if (!ath9k_is_world_regd(sc->sc_ah))
1665 regulatory_hint(hw->wiphy, sc->sc_ah->alpha2);
1666
db93e7b5
SB		 1667 /* Initialize LED control */
1668 ath_init_leds(sc);
8feceb67 1669
5f8e077c 1670
8feceb67
VT		 1671 return 0;
1672detach:
1673 ath_detach(sc);
8feceb67 1674 return error;
f078f209
LR		 1675}
1676
ff37e337
S		 1677int ath_reset(struct ath_softc *sc, bool retry_tx)
1678{
1679 struct ath_hal *ah = sc->sc_ah;
030bb495 1680 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1681 int r;
ff37e337
S		 1682
1683 ath9k_hw_set_interrupts(ah, 0);
043a0405 1684 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1685 ath_stoprecv(sc);
1686 ath_flushrecv(sc);
1687
1688 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1689 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1690 if (r)
ff37e337 1691 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1692 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1693 spin_unlock_bh(&sc->sc_resetlock);
1694
1695 if (ath_startrecv(sc) != 0)
04bd4638 1696 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1697
1698 /*
1699 * We may be doing a reset in response to a request
1700 * that changes the channel so update any state that
1701 * might change as a result.
1702 */
ce111bad 1703 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1704
1705 ath_update_txpow(sc);
1706
1707 if (sc->sc_flags & SC_OP_BEACONS)
1708 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1709
1710 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1711
1712 if (retry_tx) {
1713 int i;
1714 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1715 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1716 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1717 ath_txq_schedule(sc, &sc->tx.txq[i]);
1718 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1719 }
1720 }
1721 }
1722
ae8d2858 1723 return r;
ff37e337
S		 1724}
1725
1726/*
1727 * This function will allocate both the DMA descriptor structure, and the
1728 * buffers it contains. These are used to contain the descriptors used
1729 * by the system.
1730*/
1731int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1732 struct list_head *head, const char *name,
1733 int nbuf, int ndesc)
1734{
1735#define DS2PHYS(_dd, _ds) \
1736 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1737#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1738#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1739
1740 struct ath_desc *ds;
1741 struct ath_buf *bf;
1742 int i, bsize, error;
1743
04bd4638
S		 1744 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1745 name, nbuf, ndesc);
ff37e337
S		 1746
1747 /* ath_desc must be a multiple of DWORDs */
1748 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1749 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1750 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1751 error = -ENOMEM;
1752 goto fail;
1753 }
1754
1755 dd->dd_name = name;
1756 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1757
1758 /*
1759 * Need additional DMA memory because we can't use
1760 * descriptors that cross the 4K page boundary. Assume
1761 * one skipped descriptor per 4K page.
1762 */
1763 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1764 u32 ndesc_skipped =
1765 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1766 u32 dma_len;
1767
1768 while (ndesc_skipped) {
1769 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1770 dd->dd_desc_len += dma_len;
1771
1772 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1773 };
1774 }
1775
1776 /* allocate descriptors */
7da3c55c
GJ		 1777 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1778 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1779 if (dd->dd_desc == NULL) {
1780 error = -ENOMEM;
1781 goto fail;
1782 }
1783 ds = dd->dd_desc;
04bd4638
S		 1784 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1785 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1786 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1787
1788 /* allocate buffers */
1789 bsize = sizeof(struct ath_buf) * nbuf;
1790 bf = kmalloc(bsize, GFP_KERNEL);
1791 if (bf == NULL) {
1792 error = -ENOMEM;
1793 goto fail2;
1794 }
1795 memset(bf, 0, bsize);
1796 dd->dd_bufptr = bf;
1797
1798 INIT_LIST_HEAD(head);
1799 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1800 bf->bf_desc = ds;
1801 bf->bf_daddr = DS2PHYS(dd, ds);
1802
1803 if (!(sc->sc_ah->ah_caps.hw_caps &
1804 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1805 /*
1806 * Skip descriptor addresses which can cause 4KB
1807 * boundary crossing (addr + length) with a 32 dword
1808 * descriptor fetch.
1809 */
1810 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1811 ASSERT((caddr_t) bf->bf_desc <
1812 ((caddr_t) dd->dd_desc +
1813 dd->dd_desc_len));
1814
1815 ds += ndesc;
1816 bf->bf_desc = ds;
1817 bf->bf_daddr = DS2PHYS(dd, ds);
1818 }
1819 }
1820 list_add_tail(&bf->list, head);
1821 }
1822 return 0;
1823fail2:
7da3c55c
GJ		 1824 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1825 dd->dd_desc_paddr);
ff37e337
S		 1826fail:
1827 memset(dd, 0, sizeof(*dd));
1828 return error;
1829#undef ATH_DESC_4KB_BOUND_CHECK
1830#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1831#undef DS2PHYS
1832}
1833
1834void ath_descdma_cleanup(struct ath_softc *sc,
1835 struct ath_descdma *dd,
1836 struct list_head *head)
1837{
7da3c55c
GJ		 1838 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1839 dd->dd_desc_paddr);
ff37e337
S		 1840
1841 INIT_LIST_HEAD(head);
1842 kfree(dd->dd_bufptr);
1843 memset(dd, 0, sizeof(*dd));
1844}
1845
1846int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1847{
1848 int qnum;
1849
1850 switch (queue) {
1851 case 0:
b77f483f 1852 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1853 break;
1854 case 1:
b77f483f 1855 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1856 break;
1857 case 2:
b77f483f 1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1859 break;
1860 case 3:
b77f483f 1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1862 break;
1863 default:
b77f483f 1864 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1865 break;
1866 }
1867
1868 return qnum;
1869}
1870
1871int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1872{
1873 int qnum;
1874
1875 switch (queue) {
1876 case ATH9K_WME_AC_VO:
1877 qnum = 0;
1878 break;
1879 case ATH9K_WME_AC_VI:
1880 qnum = 1;
1881 break;
1882 case ATH9K_WME_AC_BE:
1883 qnum = 2;
1884 break;
1885 case ATH9K_WME_AC_BK:
1886 qnum = 3;
1887 break;
1888 default:
1889 qnum = -1;
1890 break;
1891 }
1892
1893 return qnum;
1894}
1895
5f8e077c
LR		 1896/* XXX: Remove me once we don't depend on ath9k_channel for all
1897 * this redundant data */
1898static void ath9k_update_ichannel(struct ath_softc *sc,
1899 struct ath9k_channel *ichan)
1900{
1901 struct ieee80211_hw *hw = sc->hw;
1902 struct ieee80211_channel *chan = hw->conf.channel;
1903 struct ieee80211_conf *conf = &hw->conf;
1904
1905 ichan->channel = chan->center_freq;
1906 ichan->chan = chan;
1907
1908 if (chan->band == IEEE80211_BAND_2GHZ) {
1909 ichan->chanmode = CHANNEL_G;
1910 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1911 } else {
1912 ichan->chanmode = CHANNEL_A;
1913 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1914 }
1915
1916 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1917
1918 if (conf_is_ht(conf)) {
1919 if (conf_is_ht40(conf))
1920 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1921
1922 ichan->chanmode = ath_get_extchanmode(sc, chan,
1923 conf->channel_type);
1924 }
1925}
1926
ff37e337
S		 1927/**********************/
1928/* mac80211 callbacks */
1929/**********************/
1930
8feceb67 1931static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1932{
1933 struct ath_softc *sc = hw->priv;
8feceb67 1934 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1935 struct ath9k_channel *init_channel;
ae8d2858 1936 int r, pos;
f078f209 1937
04bd4638
S		 1938 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1939 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1940
8feceb67 1941 /* setup initial channel */
f078f209 1942
5f8e077c 1943 pos = curchan->hw_value;
f078f209 1944
ff37e337 1945 init_channel = &sc->sc_ah->ah_channels[pos];
5f8e077c 1946 ath9k_update_ichannel(sc, init_channel);
ff37e337
S		 1947
1948 /* Reset SERDES registers */
1949 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1950
1951 /*
1952 * The basic interface to setting the hardware in a good
1953 * state is ``reset''. On return the hardware is known to
1954 * be powered up and with interrupts disabled. This must
1955 * be followed by initialization of the appropriate bits
1956 * and then setup of the interrupt mask.
1957 */
1958 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1959 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1960 if (r) {
ff37e337 1961 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1962 "Unable to reset hardware; reset status %u "
1963 "(freq %u MHz)\n", r,
1964 curchan->center_freq);
ff37e337 1965 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1966 return r;
ff37e337
S		 1967 }
1968 spin_unlock_bh(&sc->sc_resetlock);
1969
1970 /*
1971 * This is needed only to setup initial state
1972 * but it's best done after a reset.
1973 */
1974 ath_update_txpow(sc);
8feceb67 1975
ff37e337
S		 1976 /*
1977 * Setup the hardware after reset:
1978 * The receive engine is set going.
1979 * Frame transmit is handled entirely
1980 * in the frame output path; there's nothing to do
1981 * here except setup the interrupt mask.
1982 */
1983 if (ath_startrecv(sc) != 0) {
8feceb67 1984 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1985 "Unable to start recv logic\n");
ae8d2858 1986 return -EIO;
f078f209 1987 }
8feceb67 1988
ff37e337
S		 1989 /* Setup our intr mask. */
1990 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1991 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1992 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1993
1994 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1995 sc->sc_imask |= ATH9K_INT_GTT;
1996
1997 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1998 sc->sc_imask |= ATH9K_INT_CST;
1999
ce111bad 2000 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 2001
2002 sc->sc_flags &= ~SC_OP_INVALID;
2003
2004 /* Disable BMISS interrupt when we're not associated */
2005 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2006 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2007
2008 ieee80211_wake_queues(sc->hw);
2009
e97275cb 2010#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 2011 r = ath_start_rfkill_poll(sc);
500c064d 2012#endif
ae8d2858 2013 return r;
f078f209
LR		 2014}
2015
8feceb67
VT		 2016static int ath9k_tx(struct ieee80211_hw *hw,
2017 struct sk_buff *skb)
f078f209 2018{
528f0c6b 2019 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 2020 struct ath_softc *sc = hw->priv;
528f0c6b 2021 struct ath_tx_control txctl;
8feceb67 2022 int hdrlen, padsize;
528f0c6b
S		 2023
2024 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2025
8feceb67
VT		 2026 /*
2027 * As a temporary workaround, assign seq# here; this will likely need
2028 * to be cleaned up to work better with Beacon transmission and virtual
2029 * BSSes.
2030 */
2031 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2032 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2033 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2034 sc->tx.seq_no += 0x10;
8feceb67 2035 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2036 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2037 }
f078f209 2038
8feceb67
VT		 2039 /* Add the padding after the header if this is not already done */
2040 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2041 if (hdrlen & 3) {
2042 padsize = hdrlen % 4;
2043 if (skb_headroom(skb) < padsize)
2044 return -1;
2045 skb_push(skb, padsize);
2046 memmove(skb->data, skb->data + padsize, hdrlen);
2047 }
2048
528f0c6b
S		 2049 /* Check if a tx queue is available */
2050
2051 txctl.txq = ath_test_get_txq(sc, skb);
2052 if (!txctl.txq)
2053 goto exit;
2054
04bd4638 2055 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2056
528f0c6b 2057 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2058 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2059 goto exit;
8feceb67
VT		 2060 }
2061
528f0c6b
S		 2062 return 0;
2063exit:
2064 dev_kfree_skb_any(skb);
8feceb67 2065 return 0;
f078f209
LR		 2066}
2067
8feceb67 2068static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2069{
2070 struct ath_softc *sc = hw->priv;
f078f209 2071
9c84b797 2072 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2073 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2074 return;
2075 }
8feceb67 2076
04bd4638 2077 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2078
2079 ieee80211_stop_queues(sc->hw);
2080
2081 /* make sure h/w will not generate any interrupt
2082 * before setting the invalid flag. */
2083 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2084
2085 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2086 ath_drain_all_txq(sc, false);
ff37e337
S		 2087 ath_stoprecv(sc);
2088 ath9k_hw_phy_disable(sc->sc_ah);
2089 } else
b77f483f 2090 sc->rx.rxlink = NULL;
ff37e337
S		 2091
2092#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2093 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2094 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2095#endif
2096 /* disable HAL and put h/w to sleep */
2097 ath9k_hw_disable(sc->sc_ah);
2098 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2099
2100 sc->sc_flags |= SC_OP_INVALID;
500c064d 2101
04bd4638 2102 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2103}
2104
8feceb67
VT		 2105static int ath9k_add_interface(struct ieee80211_hw *hw,
2106 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2107{
2108 struct ath_softc *sc = hw->priv;
5640b08e 2109 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2110 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2111
8feceb67
VT		 2112 /* Support only vap for now */
2113
2114 if (sc->sc_nvaps)
2115 return -ENOBUFS;
2116
2117 switch (conf->type) {
05c914fe 2118 case NL80211_IFTYPE_STATION:
d97809db 2119 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2120 break;
05c914fe 2121 case NL80211_IFTYPE_ADHOC:
d97809db 2122 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2123 break;
05c914fe 2124 case NL80211_IFTYPE_AP:
d97809db 2125 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2126 break;
2127 default:
2128 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2129 "Interface type %d not yet supported\n", conf->type);
8feceb67 2130 return -EOPNOTSUPP;
f078f209
LR		 2131 }
2132
04bd4638 2133 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2134
5640b08e
S		 2135 /* Set the VAP opmode */
2136 avp->av_opmode = ic_opmode;
2137 avp->av_bslot = -1;
2138
d97809db 2139 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2140 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2141
2142 sc->sc_vaps[0] = conf->vif;
2143 sc->sc_nvaps++;
2144
2145 /* Set the device opmode */
2146 sc->sc_ah->ah_opmode = ic_opmode;
2147
4e30ffa2
VN		 2148 /*
2149 * Enable MIB interrupts when there are hardware phy counters.
2150 * Note we only do this (at the moment) for station mode.
2151 */
2152 if (ath9k_hw_phycounters(sc->sc_ah) &&
2153 ((conf->type == NL80211_IFTYPE_STATION) ||
2154 (conf->type == NL80211_IFTYPE_ADHOC)))
2155 sc->sc_imask |= ATH9K_INT_MIB;
2156 /*
2157 * Some hardware processes the TIM IE and fires an
2158 * interrupt when the TIM bit is set. For hardware
2159 * that does, if not overridden by configuration,
2160 * enable the TIM interrupt when operating as station.
2161 */
2162 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2163 (conf->type == NL80211_IFTYPE_STATION) &&
2164 !sc->sc_config.swBeaconProcess)
2165 sc->sc_imask |= ATH9K_INT_TIM;
2166
2167 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
2168
6f255425
LR		 2169 if (conf->type == NL80211_IFTYPE_AP) {
2170 /* TODO: is this a suitable place to start ANI for AP mode? */
2171 /* Start ANI */
2172 mod_timer(&sc->sc_ani.timer,
2173 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2174 }
2175
8feceb67 2176 return 0;
f078f209
LR		 2177}
2178
8feceb67
VT		 2179static void ath9k_remove_interface(struct ieee80211_hw *hw,
2180 struct ieee80211_if_init_conf *conf)
f078f209 2181{
8feceb67 2182 struct ath_softc *sc = hw->priv;
5640b08e 2183 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2184
04bd4638 2185 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2186
6f255425
LR		 2187 /* Stop ANI */
2188 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2189
8feceb67 2190 /* Reclaim beacon resources */
d97809db
CM		 2191 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2192 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2193 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2194 ath_beacon_return(sc, avp);
580f0b8a 2195 }
f078f209 2196
8feceb67 2197 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2198
5640b08e
S		 2199 sc->sc_vaps[0] = NULL;
2200 sc->sc_nvaps--;
f078f209
LR		 2201}
2202
e8975581 2203static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2204{
8feceb67 2205 struct ath_softc *sc = hw->priv;
e8975581 2206 struct ieee80211_conf *conf = &hw->conf;
f078f209 2207
aa33de09 2208 mutex_lock(&sc->mutex);
3cbb5dd7
VN		 2209 if (changed & IEEE80211_CONF_CHANGE_PS) {
2210 if (conf->flags & IEEE80211_CONF_PS) {
2211 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2212 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2213 ath9k_hw_set_interrupts(sc->sc_ah,
2214 sc->sc_imask);
2215 }
2216 ath9k_hw_setrxabort(sc->sc_ah, 1);
2217 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2218 } else {
2219 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2220 ath9k_hw_setrxabort(sc->sc_ah, 0);
2221 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2222 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2223 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2224 ath9k_hw_set_interrupts(sc->sc_ah,
2225 sc->sc_imask);
2226 }
2227 }
2228 }
2229
4797938c 2230 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2231 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2232 int pos = curchan->hw_value;
ae5eb026 2233
04bd4638
S		 2234 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2235 curchan->center_freq);
f078f209 2236
5f8e077c
LR		 2237 /* XXX: remove me eventualy */
2238 ath9k_update_ichannel(sc, &sc->sc_ah->ah_channels[pos]);
e11602b7 2239
ecf70441 2240 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2241
e11602b7 2242 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2243 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2244 mutex_unlock(&sc->mutex);
e11602b7
S		 2245 return -EINVAL;
2246 }
094d05dc 2247 }
f078f209 2248
5c020dc6
LR		 2249 if (changed & IEEE80211_CONF_CHANGE_POWER)
2250 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2251
aa33de09 2252 mutex_unlock(&sc->mutex);
f078f209
LR		 2253 return 0;
2254}
2255
8feceb67
VT		 2256static int ath9k_config_interface(struct ieee80211_hw *hw,
2257 struct ieee80211_vif *vif,
2258 struct ieee80211_if_conf *conf)
c83be688 2259{
8feceb67
VT		 2260 struct ath_softc *sc = hw->priv;
2261 struct ath_hal *ah = sc->sc_ah;
5640b08e 2262 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2263 u32 rfilt = 0;
2264 int error, i;
c83be688 2265
8feceb67
VT		 2266 /* TODO: Need to decide which hw opmode to use for multi-interface
2267 * cases */
05c914fe 2268 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2269 ah->ah_opmode != NL80211_IFTYPE_AP) {
2270 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2271 ath9k_hw_setopmode(ah);
2272 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2273 /* Request full reset to get hw opmode changed properly */
2274 sc->sc_flags |= SC_OP_FULL_RESET;
2275 }
c83be688 2276
8feceb67
VT		 2277 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2278 !is_zero_ether_addr(conf->bssid)) {
2279 switch (vif->type) {
05c914fe
JB		 2280 case NL80211_IFTYPE_STATION:
2281 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2282 /* Set BSSID */
2283 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2284 sc->sc_curaid = 0;
2285 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2286 sc->sc_curaid);
c83be688 2287
8feceb67
VT		 2288 /* Set aggregation protection mode parameters */
2289 sc->sc_config.ath_aggr_prot = 0;
c83be688 2290
8feceb67 2291 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2292 "RX filter 0x%x bssid %pM aid 0x%x\n",
2293 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2294
8feceb67
VT		 2295 /* need to reconfigure the beacon */
2296 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2297
8feceb67
VT		 2298 break;
2299 default:
2300 break;
2301 }
2302 }
c83be688 2303
1f7d6cbf
S		 2304 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2305 (vif->type == NL80211_IFTYPE_AP)) {
2306 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2307 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2308 conf->enable_beacon)) {
2309 /*
2310 * Allocate and setup the beacon frame.
2311 *
2312 * Stop any previous beacon DMA. This may be
2313 * necessary, for example, when an ibss merge
2314 * causes reconfiguration; we may be called
2315 * with beacon transmission active.
2316 */
2317 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2318
1f7d6cbf
S		 2319 error = ath_beacon_alloc(sc, 0);
2320 if (error != 0)
2321 return error;
c83be688 2322
1f7d6cbf
S		 2323 ath_beacon_sync(sc, 0);
2324 }
8feceb67 2325 }
c83be688 2326
8feceb67 2327 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2328 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2329 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2330 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2331 ath9k_hw_keysetmac(sc->sc_ah,
2332 (u16)i,
2333 sc->sc_curbssid);
2334 }
c83be688 2335
8feceb67 2336 /* Only legacy IBSS for now */
05c914fe 2337 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2338 ath_update_chainmask(sc, 0);
f078f209 2339
8feceb67
VT		 2340 return 0;
2341}
f078f209 2342
8feceb67
VT		 2343#define SUPPORTED_FILTERS \
2344 (FIF_PROMISC_IN_BSS | \
2345 FIF_ALLMULTI | \
2346 FIF_CONTROL | \
2347 FIF_OTHER_BSS | \
2348 FIF_BCN_PRBRESP_PROMISC | \
2349 FIF_FCSFAIL)
c83be688 2350
8feceb67
VT		 2351/* FIXME: sc->sc_full_reset ? */
2352static void ath9k_configure_filter(struct ieee80211_hw *hw,
2353 unsigned int changed_flags,
2354 unsigned int *total_flags,
2355 int mc_count,
2356 struct dev_mc_list *mclist)
2357{
2358 struct ath_softc *sc = hw->priv;
2359 u32 rfilt;
f078f209 2360
8feceb67
VT		 2361 changed_flags &= SUPPORTED_FILTERS;
2362 *total_flags &= SUPPORTED_FILTERS;
f078f209 2363
b77f483f 2364 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2365 rfilt = ath_calcrxfilter(sc);
2366 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2367
8feceb67
VT		 2368 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2369 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2370 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2371 }
f078f209 2372
b77f483f 2373 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2374}
f078f209 2375
8feceb67
VT		 2376static void ath9k_sta_notify(struct ieee80211_hw *hw,
2377 struct ieee80211_vif *vif,
2378 enum sta_notify_cmd cmd,
17741cdc 2379 struct ieee80211_sta *sta)
8feceb67
VT		 2380{
2381 struct ath_softc *sc = hw->priv;
f078f209 2382
8feceb67
VT		 2383 switch (cmd) {
2384 case STA_NOTIFY_ADD:
5640b08e 2385 ath_node_attach(sc, sta);
8feceb67
VT		 2386 break;
2387 case STA_NOTIFY_REMOVE:
b5aa9bf9 2388 ath_node_detach(sc, sta);
8feceb67
VT		 2389 break;
2390 default:
2391 break;
2392 }
f078f209
LR		 2393}
2394
8feceb67
VT		 2395static int ath9k_conf_tx(struct ieee80211_hw *hw,
2396 u16 queue,
2397 const struct ieee80211_tx_queue_params *params)
f078f209 2398{
8feceb67
VT		 2399 struct ath_softc *sc = hw->priv;
2400 struct ath9k_tx_queue_info qi;
2401 int ret = 0, qnum;
f078f209 2402
8feceb67
VT		 2403 if (queue >= WME_NUM_AC)
2404 return 0;
f078f209 2405
8feceb67
VT		 2406 qi.tqi_aifs = params->aifs;
2407 qi.tqi_cwmin = params->cw_min;
2408 qi.tqi_cwmax = params->cw_max;
2409 qi.tqi_burstTime = params->txop;
2410 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2411
8feceb67 2412 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2413 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2414 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2415 queue, qnum, params->aifs, params->cw_min,
2416 params->cw_max, params->txop);
f078f209 2417
8feceb67
VT		 2418 ret = ath_txq_update(sc, qnum, &qi);
2419 if (ret)
04bd4638 2420 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2421
8feceb67
VT		 2422 return ret;
2423}
f078f209 2424
8feceb67
VT		 2425static int ath9k_set_key(struct ieee80211_hw *hw,
2426 enum set_key_cmd cmd,
dc822b5d
JB		 2427 struct ieee80211_vif *vif,
2428 struct ieee80211_sta *sta,
8feceb67
VT		 2429 struct ieee80211_key_conf *key)
2430{
2431 struct ath_softc *sc = hw->priv;
2432 int ret = 0;
f078f209 2433
3cbb5dd7 2434 ath9k_ps_wakeup(sc);
04bd4638 2435 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2436
8feceb67
VT		 2437 switch (cmd) {
2438 case SET_KEY:
dc822b5d 2439 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2440 if (ret >= 0) {
2441 key->hw_key_idx = ret;
8feceb67
VT		 2442 /* push IV and Michael MIC generation to stack */
2443 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2444 if (key->alg == ALG_TKIP)
2445 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2446 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2447 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2448 ret = 0;
8feceb67
VT		 2449 }
2450 break;
2451 case DISABLE_KEY:
2452 ath_key_delete(sc, key);
8feceb67
VT		 2453 break;
2454 default:
2455 ret = -EINVAL;
2456 }
f078f209 2457
3cbb5dd7 2458 ath9k_ps_restore(sc);
8feceb67
VT		 2459 return ret;
2460}
f078f209 2461
8feceb67
VT		 2462static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2463 struct ieee80211_vif *vif,
2464 struct ieee80211_bss_conf *bss_conf,
2465 u32 changed)
2466{
2467 struct ath_softc *sc = hw->priv;
f078f209 2468
8feceb67 2469 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2470 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2471 bss_conf->use_short_preamble);
2472 if (bss_conf->use_short_preamble)
2473 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2474 else
2475 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2476 }
f078f209 2477
8feceb67 2478 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2479 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2480 bss_conf->use_cts_prot);
2481 if (bss_conf->use_cts_prot &&
2482 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2483 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2484 else
2485 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2486 }
f078f209 2487
8feceb67 2488 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2489 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2490 bss_conf->assoc);
5640b08e 2491 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2492 }
2493}
f078f209 2494
8feceb67
VT		 2495static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2496{
2497 u64 tsf;
2498 struct ath_softc *sc = hw->priv;
2499 struct ath_hal *ah = sc->sc_ah;
f078f209 2500
8feceb67 2501 tsf = ath9k_hw_gettsf64(ah);
f078f209 2502
8feceb67
VT		 2503 return tsf;
2504}
f078f209 2505
3b5d665b
AF		 2506static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2507{
2508 struct ath_softc *sc = hw->priv;
2509 struct ath_hal *ah = sc->sc_ah;
2510
2511 ath9k_hw_settsf64(ah, tsf);
2512}
2513
8feceb67
VT		 2514static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2515{
2516 struct ath_softc *sc = hw->priv;
2517 struct ath_hal *ah = sc->sc_ah;
c83be688 2518
8feceb67
VT		 2519 ath9k_hw_reset_tsf(ah);
2520}
f078f209 2521
8feceb67
VT		 2522static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2523 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2524 struct ieee80211_sta *sta,
2525 u16 tid, u16 *ssn)
8feceb67
VT		 2526{
2527 struct ath_softc *sc = hw->priv;
2528 int ret = 0;
f078f209 2529
8feceb67
VT		 2530 switch (action) {
2531 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2532 if (!(sc->sc_flags & SC_OP_RXAGGR))
2533 ret = -ENOTSUPP;
8feceb67
VT		 2534 break;
2535 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2536 break;
2537 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2538 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2539 if (ret < 0)
2540 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2541 "Unable to start TX aggregation\n");
8feceb67 2542 else
17741cdc 2543 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2544 break;
2545 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2546 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2547 if (ret < 0)
2548 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2549 "Unable to stop TX aggregation\n");
f078f209 2550
17741cdc 2551 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2552 break;
8469cdef
S		 2553 case IEEE80211_AMPDU_TX_RESUME:
2554 ath_tx_aggr_resume(sc, sta, tid);
2555 break;
8feceb67 2556 default:
04bd4638 2557 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2558 }
2559
2560 return ret;
f078f209
LR		 2561}
2562
6baff7f9 2563struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2564 .tx = ath9k_tx,
2565 .start = ath9k_start,
2566 .stop = ath9k_stop,
2567 .add_interface = ath9k_add_interface,
2568 .remove_interface = ath9k_remove_interface,
2569 .config = ath9k_config,
2570 .config_interface = ath9k_config_interface,
2571 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2572 .sta_notify = ath9k_sta_notify,
2573 .conf_tx = ath9k_conf_tx,
8feceb67 2574 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2575 .set_key = ath9k_set_key,
8feceb67 2576 .get_tsf = ath9k_get_tsf,
3b5d665b 2577 .set_tsf = ath9k_set_tsf,
8feceb67 2578 .reset_tsf = ath9k_reset_tsf,
4233df6b 2579 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2580};
2581
392dff83
BP		 2582static struct {
2583 u32 version;
2584 const char * name;
2585} ath_mac_bb_names[] = {
2586 { AR_SREV_VERSION_5416_PCI, "5416" },
2587 { AR_SREV_VERSION_5416_PCIE, "5418" },
2588 { AR_SREV_VERSION_9100, "9100" },
2589 { AR_SREV_VERSION_9160, "9160" },
2590 { AR_SREV_VERSION_9280, "9280" },
2591 { AR_SREV_VERSION_9285, "9285" }
2592};
2593
2594static struct {
2595 u16 version;
2596 const char * name;
2597} ath_rf_names[] = {
2598 { 0, "5133" },
2599 { AR_RAD5133_SREV_MAJOR, "5133" },
2600 { AR_RAD5122_SREV_MAJOR, "5122" },
2601 { AR_RAD2133_SREV_MAJOR, "2133" },
2602 { AR_RAD2122_SREV_MAJOR, "2122" }
2603};
2604
2605/*
2606 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2607 */
6baff7f9 2608const char *
392dff83
BP		 2609ath_mac_bb_name(u32 mac_bb_version)
2610{
2611 int i;
2612
2613 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2614 if (ath_mac_bb_names[i].version == mac_bb_version) {
2615 return ath_mac_bb_names[i].name;
2616 }
2617 }
2618
2619 return "????";
2620}
2621
2622/*
2623 * Return the RF name. "????" is returned if the RF is unknown.
2624 */
6baff7f9 2625const char *
392dff83
BP		 2626ath_rf_name(u16 rf_version)
2627{
2628 int i;
2629
2630 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2631 if (ath_rf_names[i].version == rf_version) {
2632 return ath_rf_names[i].name;
2633 }
2634 }
2635
2636 return "????";
2637}
2638
6baff7f9 2639static int __init ath9k_init(void)
f078f209 2640{
ca8a8560
VT		 2641 int error;
2642
ca8a8560
VT		 2643 /* Register rate control algorithm */
2644 error = ath_rate_control_register();
2645 if (error != 0) {
2646 printk(KERN_ERR
b51bb3cd
LR		 2647 "ath9k: Unable to register rate control "
2648 "algorithm: %d\n",
ca8a8560 2649 error);
6baff7f9 2650 goto err_out;
ca8a8560
VT		 2651 }
2652
6baff7f9
GJ		 2653 error = ath_pci_init();
2654 if (error < 0) {
f078f209 2655 printk(KERN_ERR
b51bb3cd 2656 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9
GJ		 2657 error = -ENODEV;
2658 goto err_rate_unregister;
f078f209
LR		 2659 }
2660
09329d37
GJ		 2661 error = ath_ahb_init();
2662 if (error < 0) {
2663 error = -ENODEV;
2664 goto err_pci_exit;
2665 }
2666
f078f209 2667 return 0;
6baff7f9 2668
09329d37
GJ		 2669 err_pci_exit:
2670 ath_pci_exit();
2671
6baff7f9
GJ		 2672 err_rate_unregister:
2673 ath_rate_control_unregister();
2674 err_out:
2675 return error;
f078f209 2676}
6baff7f9 2677module_init(ath9k_init);
f078f209 2678
6baff7f9 2679static void __exit ath9k_exit(void)
f078f209 2680{
09329d37 2681 ath_ahb_exit();
6baff7f9 2682 ath_pci_exit();
ca8a8560 2683 ath_rate_control_unregister();
04bd4638 2684 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2685}
6baff7f9 2686module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)