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ath9k: Add initial layout for an ath9k specific debugfs mechanism
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
f078f209
LR		 20
21#define ATH_PCI_VERSION "0.1"
22
f078f209
LR		 23static char *dev_info = "ath9k";
24
25MODULE_AUTHOR("Atheros Communications");
26MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
27MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
28MODULE_LICENSE("Dual BSD/GPL");
29
30static struct pci_device_id ath_pci_id_table[] __devinitdata = {
31 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
32 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
33 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
34 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
36 { 0 }
37};
38
9757d556
S		 39static void ath_detach(struct ath_softc *sc);
40
ff37e337
S		 41/* return bus cachesize in 4B word units */
42
43static void bus_read_cachesize(struct ath_softc *sc, int *csz)
44{
45 u8 u8tmp;
46
47 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
48 *csz = (int)u8tmp;
49
50 /*
51 * This check was put in to avoid "unplesant" consequences if
52 * the bootrom has not fully initialized all PCI devices.
53 * Sometimes the cache line size register is not set
54 */
55
56 if (*csz == 0)
57 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
58}
59
60static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
61{
62 sc->sc_curmode = mode;
63 /*
64 * All protection frames are transmited at 2Mb/s for
65 * 11g, otherwise at 1Mb/s.
66 * XXX select protection rate index from rate table.
67 */
68 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
69}
70
71static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
72{
73 if (chan->chanmode == CHANNEL_A)
74 return ATH9K_MODE_11A;
75 else if (chan->chanmode == CHANNEL_G)
76 return ATH9K_MODE_11G;
77 else if (chan->chanmode == CHANNEL_B)
78 return ATH9K_MODE_11B;
79 else if (chan->chanmode == CHANNEL_A_HT20)
80 return ATH9K_MODE_11NA_HT20;
81 else if (chan->chanmode == CHANNEL_G_HT20)
82 return ATH9K_MODE_11NG_HT20;
83 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
84 return ATH9K_MODE_11NA_HT40PLUS;
85 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
86 return ATH9K_MODE_11NA_HT40MINUS;
87 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
88 return ATH9K_MODE_11NG_HT40PLUS;
89 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
90 return ATH9K_MODE_11NG_HT40MINUS;
91
92 WARN_ON(1); /* should not get here */
93
94 return ATH9K_MODE_11B;
95}
96
97static void ath_update_txpow(struct ath_softc *sc)
98{
99 struct ath_hal *ah = sc->sc_ah;
100 u32 txpow;
101
102 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
103 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
104 /* read back in case value is clamped */
105 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
106 sc->sc_curtxpow = txpow;
107 }
108}
109
110static u8 parse_mpdudensity(u8 mpdudensity)
111{
112 /*
113 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
114 * 0 for no restriction
115 * 1 for 1/4 us
116 * 2 for 1/2 us
117 * 3 for 1 us
118 * 4 for 2 us
119 * 5 for 4 us
120 * 6 for 8 us
121 * 7 for 16 us
122 */
123 switch (mpdudensity) {
124 case 0:
125 return 0;
126 case 1:
127 case 2:
128 case 3:
129 /* Our lower layer calculations limit our precision to
130 1 microsecond */
131 return 1;
132 case 4:
133 return 2;
134 case 5:
135 return 4;
136 case 6:
137 return 8;
138 case 7:
139 return 16;
140 default:
141 return 0;
142 }
143}
144
145static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
146{
147 struct ath_rate_table *rate_table = NULL;
148 struct ieee80211_supported_band *sband;
149 struct ieee80211_rate *rate;
150 int i, maxrates;
151
152 switch (band) {
153 case IEEE80211_BAND_2GHZ:
154 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
155 break;
156 case IEEE80211_BAND_5GHZ:
157 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
158 break;
159 default:
160 break;
161 }
162
163 if (rate_table == NULL)
164 return;
165
166 sband = &sc->sbands[band];
167 rate = sc->rates[band];
168
169 if (rate_table->rate_cnt > ATH_RATE_MAX)
170 maxrates = ATH_RATE_MAX;
171 else
172 maxrates = rate_table->rate_cnt;
173
174 for (i = 0; i < maxrates; i++) {
175 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
176 rate[i].hw_value = rate_table->info[i].ratecode;
177 sband->n_bitrates++;
04bd4638
S		 178 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
179 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 180 }
181}
182
183static int ath_setup_channels(struct ath_softc *sc)
184{
185 struct ath_hal *ah = sc->sc_ah;
186 int nchan, i, a = 0, b = 0;
187 u8 regclassids[ATH_REGCLASSIDS_MAX];
188 u32 nregclass = 0;
189 struct ieee80211_supported_band *band_2ghz;
190 struct ieee80211_supported_band *band_5ghz;
191 struct ieee80211_channel *chan_2ghz;
192 struct ieee80211_channel *chan_5ghz;
193 struct ath9k_channel *c;
194
195 /* Fill in ah->ah_channels */
196 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
197 regclassids, ATH_REGCLASSIDS_MAX,
198 &nregclass, CTRY_DEFAULT, false, 1)) {
199 u32 rd = ah->ah_currentRD;
200 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 201 "Unable to collect channel list; "
ff37e337 202 "regdomain likely %u country code %u\n",
04bd4638 203 rd, CTRY_DEFAULT);
ff37e337
S		 204 return -EINVAL;
205 }
206
207 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
208 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
209 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
210 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
211
212 for (i = 0; i < nchan; i++) {
213 c = &ah->ah_channels[i];
214 if (IS_CHAN_2GHZ(c)) {
215 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
216 chan_2ghz[a].center_freq = c->channel;
217 chan_2ghz[a].max_power = c->maxTxPower;
218
219 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
220 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
221 if (c->channelFlags & CHANNEL_PASSIVE)
222 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
223
224 band_2ghz->n_channels = ++a;
225
04bd4638 226 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 227 "channelFlags: 0x%x\n",
04bd4638 228 c->channel, c->channelFlags);
ff37e337
S		 229 } else if (IS_CHAN_5GHZ(c)) {
230 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
231 chan_5ghz[b].center_freq = c->channel;
232 chan_5ghz[b].max_power = c->maxTxPower;
233
234 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
235 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
236 if (c->channelFlags & CHANNEL_PASSIVE)
237 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
238
239 band_5ghz->n_channels = ++b;
240
04bd4638 241 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 242 "channelFlags: 0x%x\n",
04bd4638 243 c->channel, c->channelFlags);
ff37e337
S		 244 }
245 }
246
247 return 0;
248}
249
250/*
251 * Set/change channels. If the channel is really being changed, it's done
252 * by reseting the chip. To accomplish this we must first cleanup any pending
253 * DMA, then restart stuff.
254*/
255static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
256{
257 struct ath_hal *ah = sc->sc_ah;
258 bool fastcc = true, stopped;
259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
ff37e337
S		 263 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
264 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
265 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
266 (sc->sc_flags & SC_OP_FULL_RESET)) {
267 int status;
268 /*
269 * This is only performed if the channel settings have
270 * actually changed.
271 *
272 * To switch channels clear any pending DMA operations;
273 * wait long enough for the RX fifo to drain, reset the
274 * hardware at the new frequency, and then re-enable
275 * the relevant bits of the h/w.
276 */
04bd4638
S		 277 ath9k_hw_set_interrupts(ah, 0);
278 ath_draintxq(sc, false);
279 stopped = ath_stoprecv(sc);
ff37e337
S		 280
281 /* XXX: do not flush receive queue here. We don't want
282 * to flush data frames already in queue because of
283 * changing channel. */
284
285 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
286 fastcc = false;
287
99405f93 288 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 289 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
99405f93
S		 290 sc->sc_ah->ah_curchan->channel,
291 hchan->channel, hchan->channelFlags, sc->tx_chan_width);
292
ff37e337 293 spin_lock_bh(&sc->sc_resetlock);
99405f93 294 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
ff37e337
S		 295 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
296 sc->sc_ht_extprotspacing, fastcc, &status)) {
297 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638
S		 298 "Unable to reset channel %u (%uMhz) "
299 "flags 0x%x hal status %u\n",
ff37e337
S		 300 ath9k_hw_mhz2ieee(ah, hchan->channel,
301 hchan->channelFlags),
302 hchan->channel, hchan->channelFlags, status);
303 spin_unlock_bh(&sc->sc_resetlock);
304 return -EIO;
305 }
306 spin_unlock_bh(&sc->sc_resetlock);
307
308 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
309 sc->sc_flags &= ~SC_OP_FULL_RESET;
310
311 if (ath_startrecv(sc) != 0) {
312 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 313 "Unable to restart recv logic\n");
ff37e337
S		 314 return -EIO;
315 }
316
317 ath_setcurmode(sc, ath_chan2mode(hchan));
318 ath_update_txpow(sc);
319 ath9k_hw_set_interrupts(ah, sc->sc_imask);
320 }
321 return 0;
322}
323
324/*
325 * This routine performs the periodic noise floor calibration function
326 * that is used to adjust and optimize the chip performance. This
327 * takes environmental changes (location, temperature) into account.
328 * When the task is complete, it reschedules itself depending on the
329 * appropriate interval that was calculated.
330 */
331static void ath_ani_calibrate(unsigned long data)
332{
333 struct ath_softc *sc;
334 struct ath_hal *ah;
335 bool longcal = false;
336 bool shortcal = false;
337 bool aniflag = false;
338 unsigned int timestamp = jiffies_to_msecs(jiffies);
339 u32 cal_interval;
340
341 sc = (struct ath_softc *)data;
342 ah = sc->sc_ah;
343
344 /*
345 * don't calibrate when we're scanning.
346 * we are most likely not on our home channel.
347 */
348 if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
349 return;
350
351 /* Long calibration runs independently of short calibration. */
352 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
353 longcal = true;
04bd4638 354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 355 sc->sc_ani.sc_longcal_timer = timestamp;
356 }
357
358 /* Short calibration applies only while sc_caldone is false */
359 if (!sc->sc_ani.sc_caldone) {
360 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
361 ATH_SHORT_CALINTERVAL) {
362 shortcal = true;
04bd4638 363 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 364 sc->sc_ani.sc_shortcal_timer = timestamp;
365 sc->sc_ani.sc_resetcal_timer = timestamp;
366 }
367 } else {
368 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
369 ATH_RESTART_CALINTERVAL) {
370 ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
371 &sc->sc_ani.sc_caldone);
372 if (sc->sc_ani.sc_caldone)
373 sc->sc_ani.sc_resetcal_timer = timestamp;
374 }
375 }
376
377 /* Verify whether we must check ANI */
378 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
379 ATH_ANI_POLLINTERVAL) {
380 aniflag = true;
381 sc->sc_ani.sc_checkani_timer = timestamp;
382 }
383
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
387 if (aniflag)
388 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
389 ah->ah_curchan);
390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
393 bool iscaldone = false;
394
395 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
396 sc->sc_rx_chainmask, longcal,
397 &iscaldone)) {
398 if (longcal)
399 sc->sc_ani.sc_noise_floor =
400 ath9k_hw_getchan_noise(ah,
401 ah->ah_curchan);
402
403 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 404 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 405 ah->ah_curchan->channel,
406 ah->ah_curchan->channelFlags,
407 sc->sc_ani.sc_noise_floor);
408 } else {
409 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 410 "calibrate chan %u/%x failed\n",
ff37e337
S		 411 ah->ah_curchan->channel,
412 ah->ah_curchan->channelFlags);
413 }
414 sc->sc_ani.sc_caldone = iscaldone;
415 }
416 }
417
418 /*
419 * Set timer interval based on previous results.
420 * The interval must be the shortest necessary to satisfy ANI,
421 * short calibration and long calibration.
422 */
423
424 cal_interval = ATH_ANI_POLLINTERVAL;
425 if (!sc->sc_ani.sc_caldone)
426 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
427
428 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
429}
430
431/*
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
434 * the chainmask configuration.
435 */
436static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
437{
438 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
439 if (is_ht) {
440 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
441 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
442 } else {
443 sc->sc_tx_chainmask = 1;
444 sc->sc_rx_chainmask = 1;
445 }
446
04bd4638
S		 447 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
448 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 449}
450
451static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
452{
453 struct ath_node *an;
454
455 an = (struct ath_node *)sta->drv_priv;
456
457 if (sc->sc_flags & SC_OP_TXAGGR)
458 ath_tx_node_init(sc, an);
459
460 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
461 sta->ht_cap.ampdu_factor);
462 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
463}
464
465static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
466{
467 struct ath_node *an = (struct ath_node *)sta->drv_priv;
468
469 if (sc->sc_flags & SC_OP_TXAGGR)
470 ath_tx_node_cleanup(sc, an);
471}
472
473static void ath9k_tasklet(unsigned long data)
474{
475 struct ath_softc *sc = (struct ath_softc *)data;
476 u32 status = sc->sc_intrstatus;
477
478 if (status & ATH9K_INT_FATAL) {
479 /* need a chip reset */
480 ath_reset(sc, false);
481 return;
482 } else {
483
484 if (status &
485 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
486 spin_lock_bh(&sc->sc_rxflushlock);
487 ath_rx_tasklet(sc, 0);
488 spin_unlock_bh(&sc->sc_rxflushlock);
489 }
490 /* XXX: optimize this */
491 if (status & ATH9K_INT_TX)
492 ath_tx_tasklet(sc);
493 }
494
495 /* re-enable hardware interrupt */
496 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
497}
498
499static irqreturn_t ath_isr(int irq, void *dev)
500{
501 struct ath_softc *sc = dev;
502 struct ath_hal *ah = sc->sc_ah;
503 enum ath9k_int status;
504 bool sched = false;
505
506 do {
507 if (sc->sc_flags & SC_OP_INVALID) {
508 /*
509 * The hardware is not ready/present, don't
510 * touch anything. Note this can happen early
511 * on if the IRQ is shared.
512 */
513 return IRQ_NONE;
514 }
515 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
516 return IRQ_NONE;
517 }
518
519 /*
520 * Figure out the reason(s) for the interrupt. Note
521 * that the hal returns a pseudo-ISR that may include
522 * bits we haven't explicitly enabled so we mask the
523 * value to insure we only process bits we requested.
524 */
525 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
526
527 status &= sc->sc_imask; /* discard unasked-for bits */
528
529 /*
530 * If there are no status bits set, then this interrupt was not
531 * for me (should have been caught above).
532 */
533 if (!status)
534 return IRQ_NONE;
535
536 sc->sc_intrstatus = status;
537
538 if (status & ATH9K_INT_FATAL) {
539 /* need a chip reset */
540 sched = true;
541 } else if (status & ATH9K_INT_RXORN) {
542 /* need a chip reset */
543 sched = true;
544 } else {
545 if (status & ATH9K_INT_SWBA) {
546 /* schedule a tasklet for beacon handling */
547 tasklet_schedule(&sc->bcon_tasklet);
548 }
549 if (status & ATH9K_INT_RXEOL) {
550 /*
551 * NB: the hardware should re-read the link when
552 * RXE bit is written, but it doesn't work
553 * at least on older hardware revs.
554 */
555 sched = true;
556 }
557
558 if (status & ATH9K_INT_TXURN)
559 /* bump tx trigger level */
560 ath9k_hw_updatetxtriglevel(ah, true);
561 /* XXX: optimize this */
562 if (status & ATH9K_INT_RX)
563 sched = true;
564 if (status & ATH9K_INT_TX)
565 sched = true;
566 if (status & ATH9K_INT_BMISS)
567 sched = true;
568 /* carrier sense timeout */
569 if (status & ATH9K_INT_CST)
570 sched = true;
571 if (status & ATH9K_INT_MIB) {
572 /*
573 * Disable interrupts until we service the MIB
574 * interrupt; otherwise it will continue to
575 * fire.
576 */
577 ath9k_hw_set_interrupts(ah, 0);
578 /*
579 * Let the hal handle the event. We assume
580 * it will clear whatever condition caused
581 * the interrupt.
582 */
583 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
584 ath9k_hw_set_interrupts(ah, sc->sc_imask);
585 }
586 if (status & ATH9K_INT_TIM_TIMER) {
587 if (!(ah->ah_caps.hw_caps &
588 ATH9K_HW_CAP_AUTOSLEEP)) {
589 /* Clear RxAbort bit so that we can
590 * receive frames */
591 ath9k_hw_setrxabort(ah, 0);
592 sched = true;
593 }
594 }
595 }
596 } while (0);
597
598 if (sched) {
599 /* turn off every interrupt except SWBA */
600 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
601 tasklet_schedule(&sc->intr_tq);
602 }
603
604 return IRQ_HANDLED;
605}
606
f078f209
LR		 607static int ath_get_channel(struct ath_softc *sc,
608 struct ieee80211_channel *chan)
609{
610 int i;
611
612 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
613 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
614 return i;
615 }
616
617 return -1;
618}
619
e11602b7
S		 620/* ext_chan_offset: (-1, 0, 1) (below, none, above) */
621
f078f209 622static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 623 struct ieee80211_channel *chan,
e11602b7
S		 624 int ext_chan_offset,
625 enum ath9k_ht_macmode tx_chan_width)
f078f209
LR		 626{
627 u32 chanmode = 0;
f078f209
LR		 628
629 switch (chan->band) {
630 case IEEE80211_BAND_2GHZ:
e11602b7 631 if ((ext_chan_offset == 0) &&
f078f209
LR		 632 (tx_chan_width == ATH9K_HT_MACMODE_20))
633 chanmode = CHANNEL_G_HT20;
e11602b7 634 if ((ext_chan_offset == 1) &&
f078f209
LR		 635 (tx_chan_width == ATH9K_HT_MACMODE_2040))
636 chanmode = CHANNEL_G_HT40PLUS;
e11602b7 637 if ((ext_chan_offset == -1) &&
f078f209
LR		 638 (tx_chan_width == ATH9K_HT_MACMODE_2040))
639 chanmode = CHANNEL_G_HT40MINUS;
640 break;
641 case IEEE80211_BAND_5GHZ:
e11602b7 642 if ((ext_chan_offset == 0) &&
f078f209
LR		 643 (tx_chan_width == ATH9K_HT_MACMODE_20))
644 chanmode = CHANNEL_A_HT20;
e11602b7 645 if ((ext_chan_offset == 1) &&
f078f209
LR		 646 (tx_chan_width == ATH9K_HT_MACMODE_2040))
647 chanmode = CHANNEL_A_HT40PLUS;
e11602b7 648 if ((ext_chan_offset == -1) &&
f078f209
LR		 649 (tx_chan_width == ATH9K_HT_MACMODE_2040))
650 chanmode = CHANNEL_A_HT40MINUS;
651 break;
652 default:
653 break;
654 }
655
656 return chanmode;
657}
658
ff37e337
S		 659static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
660{
661 ath9k_hw_keyreset(sc->sc_ah, keyix);
662 if (freeslot)
663 clear_bit(keyix, sc->sc_keymap);
664}
665
666static int ath_keyset(struct ath_softc *sc, u16 keyix,
667 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
668{
669 bool status;
670
671 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
672 keyix, hk, mac, false);
673
674 return status != false;
675}
f078f209
LR		 676
677static int ath_setkey_tkip(struct ath_softc *sc,
678 struct ieee80211_key_conf *key,
679 struct ath9k_keyval *hk,
680 const u8 *addr)
681{
682 u8 *key_rxmic = NULL;
683 u8 *key_txmic = NULL;
684
685 key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
686 key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
687
688 if (addr == NULL) {
689 /* Group key installation */
690 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
691 return ath_keyset(sc, key->keyidx, hk, addr);
692 }
693 if (!sc->sc_splitmic) {
694 /*
695 * data key goes at first index,
696 * the hal handles the MIC keys at index+64.
697 */
698 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
699 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
700 return ath_keyset(sc, key->keyidx, hk, addr);
701 }
702 /*
703 * TX key goes at first index, RX key at +32.
704 * The hal handles the MIC keys at index+64.
705 */
706 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
707 if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
708 /* Txmic entry failed. No need to proceed further */
709 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 710 "Setting TX MIC Key Failed\n");
f078f209
LR		 711 return 0;
712 }
713
714 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
715 /* XXX delete tx key on failure? */
716 return ath_keyset(sc, key->keyidx+32, hk, addr);
717}
718
719static int ath_key_config(struct ath_softc *sc,
720 const u8 *addr,
721 struct ieee80211_key_conf *key)
722{
723 struct ieee80211_vif *vif;
724 struct ath9k_keyval hk;
725 const u8 *mac = NULL;
726 int ret = 0;
05c914fe 727 enum nl80211_iftype opmode;
f078f209
LR		 728
729 memset(&hk, 0, sizeof(hk));
730
731 switch (key->alg) {
732 case ALG_WEP:
733 hk.kv_type = ATH9K_CIPHER_WEP;
734 break;
735 case ALG_TKIP:
736 hk.kv_type = ATH9K_CIPHER_TKIP;
737 break;
738 case ALG_CCMP:
739 hk.kv_type = ATH9K_CIPHER_AES_CCM;
740 break;
741 default:
742 return -EINVAL;
743 }
744
745 hk.kv_len = key->keylen;
746 memcpy(hk.kv_val, key->key, key->keylen);
747
748 if (!sc->sc_vaps[0])
749 return -EIO;
750
5640b08e 751 vif = sc->sc_vaps[0];
f078f209
LR		 752 opmode = vif->type;
753
754 /*
755 * Strategy:
756 * For _M_STA mc tx, we will not setup a key at all since we never
757 * tx mc.
758 * _M_STA mc rx, we will use the keyID.
759 * for _M_IBSS mc tx, we will use the keyID, and no macaddr.
760 * for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
761 * peer node. BUT we will plumb a cleartext key so that we can do
762 * perSta default key table lookup in software.
763 */
764 if (is_broadcast_ether_addr(addr)) {
765 switch (opmode) {
05c914fe 766 case NL80211_IFTYPE_STATION:
f078f209
LR		 767 /* default key: could be group WPA key
768 * or could be static WEP key */
769 mac = NULL;
770 break;
05c914fe 771 case NL80211_IFTYPE_ADHOC:
f078f209 772 break;
05c914fe 773 case NL80211_IFTYPE_AP:
f078f209
LR		 774 break;
775 default:
776 ASSERT(0);
777 break;
778 }
779 } else {
780 mac = addr;
781 }
782
783 if (key->alg == ALG_TKIP)
784 ret = ath_setkey_tkip(sc, key, &hk, mac);
785 else
786 ret = ath_keyset(sc, key->keyidx, &hk, mac);
787
788 if (!ret)
789 return -EIO;
790
f078f209
LR		 791 return 0;
792}
793
794static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
795{
f078f209
LR		 796 int freeslot;
797
ff9b662d 798 freeslot = (key->keyidx >= 4) ? 1 : 0;
f078f209 799 ath_key_reset(sc, key->keyidx, freeslot);
f078f209
LR		 800}
801
d9fe60de 802static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 803{
60653678
S		 804#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
805#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 806
d9fe60de
JB		 807 ht_info->ht_supported = true;
808 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
809 IEEE80211_HT_CAP_SM_PS |
810 IEEE80211_HT_CAP_SGI_40 |
811 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 812
60653678
S		 813 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
814 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 815 /* set up supported mcs set */
816 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
817 ht_info->mcs.rx_mask[0] = 0xff;
818 ht_info->mcs.rx_mask[1] = 0xff;
819 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 820}
821
8feceb67
VT		 822static void ath9k_ht_conf(struct ath_softc *sc,
823 struct ieee80211_bss_conf *bss_conf)
f078f209 824{
ae5eb026 825 if (sc->hw->conf.ht.enabled) {
ae5eb026 826 if (bss_conf->ht.width_40_ok)
99405f93 827 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
8feceb67 828 else
99405f93 829 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
f078f209 830
99405f93
S		 831 ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width);
832
833 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 834 "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width);
f078f209 835 }
f078f209
LR		 836}
837
e11602b7
S		 838static inline int ath_sec_offset(u8 ext_offset)
839{
840 if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE)
841 return 0;
842 else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE)
843 return 1;
844 else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW)
845 return -1;
846
847 return 0;
848}
849
8feceb67 850static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 851 struct ieee80211_vif *vif,
8feceb67 852 struct ieee80211_bss_conf *bss_conf)
f078f209 853{
8feceb67
VT		 854 struct ieee80211_hw *hw = sc->hw;
855 struct ieee80211_channel *curchan = hw->conf.channel;
5640b08e 856 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67 857 int pos;
f078f209 858
8feceb67 859 if (bss_conf->assoc) {
04bd4638 860 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid);
f078f209 861
8feceb67
VT		 862 /* New association, store aid */
863 if (avp->av_opmode == ATH9K_M_STA) {
864 sc->sc_curaid = bss_conf->aid;
865 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
866 sc->sc_curaid);
867 }
f078f209 868
8feceb67
VT		 869 /* Configure the beacon */
870 ath_beacon_config(sc, 0);
871 sc->sc_flags |= SC_OP_BEACONS;
f078f209 872
8feceb67
VT		 873 /* Reset rssi stats */
874 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
875 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
876 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
877 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 878
8feceb67 879 /* Update chainmask */
ae5eb026 880 ath_update_chainmask(sc, hw->conf.ht.enabled);
f078f209 881
f078f209 882 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 883 "bssid %pM aid 0x%x\n",
e174961c 884 sc->sc_curbssid, sc->sc_curaid);
f078f209 885
8feceb67
VT		 886 pos = ath_get_channel(sc, curchan);
887 if (pos == -1) {
888 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 889 "Invalid channel: %d\n", curchan->center_freq);
8feceb67
VT		 890 return;
891 }
f078f209 892
99405f93 893 if (hw->conf.ht.enabled) {
e11602b7
S		 894 int offset =
895 ath_sec_offset(bss_conf->ht.secondary_channel_offset);
896 sc->tx_chan_width = (bss_conf->ht.width_40_ok) ?
897 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
99405f93 898
e11602b7
S		 899 sc->sc_ah->ah_channels[pos].chanmode =
900 ath_get_extchanmode(sc, curchan,
901 offset, sc->tx_chan_width);
99405f93 902 } else {
8feceb67
VT		 903 sc->sc_ah->ah_channels[pos].chanmode =
904 (curchan->band == IEEE80211_BAND_2GHZ) ?
905 CHANNEL_G : CHANNEL_A;
99405f93 906 }
f078f209 907
8feceb67
VT		 908 /* set h/w channel */
909 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
04bd4638
S		 910 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n",
911 curchan->center_freq);
912
6f255425
LR		 913 /* Start ANI */
914 mod_timer(&sc->sc_ani.timer,
915 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
916
8feceb67 917 } else {
04bd4638 918 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 919 sc->sc_curaid = 0;
f078f209 920 }
8feceb67 921}
f078f209 922
8feceb67
VT		 923/********************************/
924/* LED functions */
925/********************************/
f078f209 926
8feceb67
VT		 927static void ath_led_brightness(struct led_classdev *led_cdev,
928 enum led_brightness brightness)
929{
930 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
931 struct ath_softc *sc = led->sc;
f078f209 932
8feceb67
VT		 933 switch (brightness) {
934 case LED_OFF:
935 if (led->led_type == ATH_LED_ASSOC ||
936 led->led_type == ATH_LED_RADIO)
937 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
938 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
939 (led->led_type == ATH_LED_RADIO) ? 1 :
940 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
941 break;
942 case LED_FULL:
943 if (led->led_type == ATH_LED_ASSOC)
944 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
945 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
946 break;
947 default:
948 break;
f078f209 949 }
8feceb67 950}
f078f209 951
8feceb67
VT		 952static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
953 char *trigger)
954{
955 int ret;
f078f209 956
8feceb67
VT		 957 led->sc = sc;
958 led->led_cdev.name = led->name;
959 led->led_cdev.default_trigger = trigger;
960 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 961
8feceb67
VT		 962 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
963 if (ret)
964 DPRINTF(sc, ATH_DBG_FATAL,
965 "Failed to register led:%s", led->name);
966 else
967 led->registered = 1;
968 return ret;
969}
f078f209 970
8feceb67
VT		 971static void ath_unregister_led(struct ath_led *led)
972{
973 if (led->registered) {
974 led_classdev_unregister(&led->led_cdev);
975 led->registered = 0;
f078f209 976 }
f078f209
LR		 977}
978
8feceb67 979static void ath_deinit_leds(struct ath_softc *sc)
f078f209 980{
8feceb67
VT		 981 ath_unregister_led(&sc->assoc_led);
982 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
983 ath_unregister_led(&sc->tx_led);
984 ath_unregister_led(&sc->rx_led);
985 ath_unregister_led(&sc->radio_led);
986 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
987}
f078f209 988
8feceb67
VT		 989static void ath_init_leds(struct ath_softc *sc)
990{
991 char *trigger;
992 int ret;
f078f209 993
8feceb67
VT		 994 /* Configure gpio 1 for output */
995 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
996 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
997 /* LED off, active low */
998 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 999
8feceb67
VT		 1000 trigger = ieee80211_get_radio_led_name(sc->hw);
1001 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1002 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1003 ret = ath_register_led(sc, &sc->radio_led, trigger);
1004 sc->radio_led.led_type = ATH_LED_RADIO;
1005 if (ret)
1006 goto fail;
7dcfdcd9 1007
8feceb67
VT		 1008 trigger = ieee80211_get_assoc_led_name(sc->hw);
1009 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1010 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1011 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1012 sc->assoc_led.led_type = ATH_LED_ASSOC;
1013 if (ret)
1014 goto fail;
f078f209 1015
8feceb67
VT		 1016 trigger = ieee80211_get_tx_led_name(sc->hw);
1017 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1018 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1019 ret = ath_register_led(sc, &sc->tx_led, trigger);
1020 sc->tx_led.led_type = ATH_LED_TX;
1021 if (ret)
1022 goto fail;
f078f209 1023
8feceb67
VT		 1024 trigger = ieee80211_get_rx_led_name(sc->hw);
1025 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1026 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1027 ret = ath_register_led(sc, &sc->rx_led, trigger);
1028 sc->rx_led.led_type = ATH_LED_RX;
1029 if (ret)
1030 goto fail;
f078f209 1031
8feceb67
VT		 1032 return;
1033
1034fail:
1035 ath_deinit_leds(sc);
f078f209
LR		 1036}
1037
e97275cb 1038#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1039
500c064d
VT		 1040/*******************/
1041/* Rfkill */
1042/*******************/
1043
1044static void ath_radio_enable(struct ath_softc *sc)
1045{
1046 struct ath_hal *ah = sc->sc_ah;
1047 int status;
1048
1049 spin_lock_bh(&sc->sc_resetlock);
1050 if (!ath9k_hw_reset(ah, ah->ah_curchan,
99405f93 1051 sc->tx_chan_width,
500c064d
VT		 1052 sc->sc_tx_chainmask,
1053 sc->sc_rx_chainmask,
1054 sc->sc_ht_extprotspacing,
1055 false, &status)) {
1056 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638
S		 1057 "Unable to reset channel %u (%uMhz) "
1058 "flags 0x%x hal status %u\n",
500c064d
VT		 1059 ath9k_hw_mhz2ieee(ah,
1060 ah->ah_curchan->channel,
1061 ah->ah_curchan->channelFlags),
1062 ah->ah_curchan->channel,
1063 ah->ah_curchan->channelFlags, status);
1064 }
1065 spin_unlock_bh(&sc->sc_resetlock);
1066
1067 ath_update_txpow(sc);
1068 if (ath_startrecv(sc) != 0) {
1069 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1070 "Unable to restart recv logic\n");
500c064d
VT		 1071 return;
1072 }
1073
1074 if (sc->sc_flags & SC_OP_BEACONS)
1075 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1076
1077 /* Re-Enable interrupts */
1078 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1079
1080 /* Enable LED */
1081 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1082 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1083 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1084
1085 ieee80211_wake_queues(sc->hw);
1086}
1087
1088static void ath_radio_disable(struct ath_softc *sc)
1089{
1090 struct ath_hal *ah = sc->sc_ah;
1091 int status;
1092
1093
1094 ieee80211_stop_queues(sc->hw);
1095
1096 /* Disable LED */
1097 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1098 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1099
1100 /* Disable interrupts */
1101 ath9k_hw_set_interrupts(ah, 0);
1102
1103 ath_draintxq(sc, false); /* clear pending tx frames */
1104 ath_stoprecv(sc); /* turn off frame recv */
1105 ath_flushrecv(sc); /* flush recv queue */
1106
1107 spin_lock_bh(&sc->sc_resetlock);
1108 if (!ath9k_hw_reset(ah, ah->ah_curchan,
99405f93 1109 sc->tx_chan_width,
500c064d
VT		 1110 sc->sc_tx_chainmask,
1111 sc->sc_rx_chainmask,
1112 sc->sc_ht_extprotspacing,
1113 false, &status)) {
1114 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638
S		 1115 "Unable to reset channel %u (%uMhz) "
1116 "flags 0x%x hal status %u\n",
500c064d
VT		 1117 ath9k_hw_mhz2ieee(ah,
1118 ah->ah_curchan->channel,
1119 ah->ah_curchan->channelFlags),
1120 ah->ah_curchan->channel,
1121 ah->ah_curchan->channelFlags, status);
1122 }
1123 spin_unlock_bh(&sc->sc_resetlock);
1124
1125 ath9k_hw_phy_disable(ah);
1126 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1127}
1128
1129static bool ath_is_rfkill_set(struct ath_softc *sc)
1130{
1131 struct ath_hal *ah = sc->sc_ah;
1132
1133 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1134 ah->ah_rfkill_polarity;
1135}
1136
1137/* h/w rfkill poll function */
1138static void ath_rfkill_poll(struct work_struct *work)
1139{
1140 struct ath_softc *sc = container_of(work, struct ath_softc,
1141 rf_kill.rfkill_poll.work);
1142 bool radio_on;
1143
1144 if (sc->sc_flags & SC_OP_INVALID)
1145 return;
1146
1147 radio_on = !ath_is_rfkill_set(sc);
1148
1149 /*
1150 * enable/disable radio only when there is a
1151 * state change in RF switch
1152 */
1153 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1154 enum rfkill_state state;
1155
1156 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1157 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1158 : RFKILL_STATE_HARD_BLOCKED;
1159 } else if (radio_on) {
1160 ath_radio_enable(sc);
1161 state = RFKILL_STATE_UNBLOCKED;
1162 } else {
1163 ath_radio_disable(sc);
1164 state = RFKILL_STATE_HARD_BLOCKED;
1165 }
1166
1167 if (state == RFKILL_STATE_HARD_BLOCKED)
1168 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1169 else
1170 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1171
1172 rfkill_force_state(sc->rf_kill.rfkill, state);
1173 }
1174
1175 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1176 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1177}
1178
1179/* s/w rfkill handler */
1180static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1181{
1182 struct ath_softc *sc = data;
1183
1184 switch (state) {
1185 case RFKILL_STATE_SOFT_BLOCKED:
1186 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1187 SC_OP_RFKILL_SW_BLOCKED)))
1188 ath_radio_disable(sc);
1189 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1190 return 0;
1191 case RFKILL_STATE_UNBLOCKED:
1192 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1193 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1194 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1195 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1196 "radio as it is disabled by h/w\n");
500c064d
VT		 1197 return -EPERM;
1198 }
1199 ath_radio_enable(sc);
1200 }
1201 return 0;
1202 default:
1203 return -EINVAL;
1204 }
1205}
1206
1207/* Init s/w rfkill */
1208static int ath_init_sw_rfkill(struct ath_softc *sc)
1209{
1210 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1211 RFKILL_TYPE_WLAN);
1212 if (!sc->rf_kill.rfkill) {
1213 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1214 return -ENOMEM;
1215 }
1216
1217 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1218 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1219 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1220 sc->rf_kill.rfkill->data = sc;
1221 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1222 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1223 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1224
1225 return 0;
1226}
1227
1228/* Deinitialize rfkill */
1229static void ath_deinit_rfkill(struct ath_softc *sc)
1230{
1231 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1232 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1233
1234 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1235 rfkill_unregister(sc->rf_kill.rfkill);
1236 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1237 sc->rf_kill.rfkill = NULL;
1238 }
1239}
9c84b797
S		 1240
1241static int ath_start_rfkill_poll(struct ath_softc *sc)
1242{
1243 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1244 queue_delayed_work(sc->hw->workqueue,
1245 &sc->rf_kill.rfkill_poll, 0);
1246
1247 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1248 if (rfkill_register(sc->rf_kill.rfkill)) {
1249 DPRINTF(sc, ATH_DBG_FATAL,
1250 "Unable to register rfkill\n");
1251 rfkill_free(sc->rf_kill.rfkill);
1252
1253 /* Deinitialize the device */
306efdd1 1254 ath_detach(sc);
9c84b797
S		 1255 if (sc->pdev->irq)
1256 free_irq(sc->pdev->irq, sc);
9c84b797
S		 1257 pci_iounmap(sc->pdev, sc->mem);
1258 pci_release_region(sc->pdev, 0);
1259 pci_disable_device(sc->pdev);
9757d556 1260 ieee80211_free_hw(sc->hw);
9c84b797
S		 1261 return -EIO;
1262 } else {
1263 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1264 }
1265 }
1266
1267 return 0;
1268}
500c064d
VT		 1269#endif /* CONFIG_RFKILL */
1270
9c84b797 1271static void ath_detach(struct ath_softc *sc)
f078f209 1272{
8feceb67 1273 struct ieee80211_hw *hw = sc->hw;
9c84b797 1274 int i = 0;
f078f209 1275
04bd4638 1276 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1277
e97275cb 1278#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1279 ath_deinit_rfkill(sc);
1280#endif
3fcdfb4b
VT		 1281 ath_deinit_leds(sc);
1282
1283 ieee80211_unregister_hw(hw);
1284
8feceb67 1285 ath_rate_control_unregister();
f078f209 1286
8feceb67
VT		 1287 ath_rx_cleanup(sc);
1288 ath_tx_cleanup(sc);
f078f209 1289
9c84b797
S		 1290 tasklet_kill(&sc->intr_tq);
1291 tasklet_kill(&sc->bcon_tasklet);
f078f209 1292
9c84b797
S		 1293 if (!(sc->sc_flags & SC_OP_INVALID))
1294 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1295
9c84b797
S		 1296 /* cleanup tx queues */
1297 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1298 if (ATH_TXQ_SETUP(sc, i))
1299 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1300
1301 ath9k_hw_detach(sc->sc_ah);
826d2680 1302 ath9k_exit_debug(sc);
f078f209
LR		 1303}
1304
ff37e337
S		 1305static int ath_init(u16 devid, struct ath_softc *sc)
1306{
1307 struct ath_hal *ah = NULL;
1308 int status;
1309 int error = 0, i;
1310 int csz = 0;
1311
1312 /* XXX: hardware will not be ready until ath_open() being called */
1313 sc->sc_flags |= SC_OP_INVALID;
88b126af 1314
826d2680
S		 1315 if (ath9k_init_debug(sc) < 0)
1316 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1317
1318 spin_lock_init(&sc->sc_resetlock);
1319 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1320 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1321 (unsigned long)sc);
1322
1323 /*
1324 * Cache line size is used to size and align various
1325 * structures used to communicate with the hardware.
1326 */
1327 bus_read_cachesize(sc, &csz);
1328 /* XXX assert csz is non-zero */
1329 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1330
1331 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1332 if (ah == NULL) {
1333 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1334 "Unable to attach hardware; HAL status %u\n", status);
ff37e337
S		 1335 error = -ENXIO;
1336 goto bad;
1337 }
1338 sc->sc_ah = ah;
1339
1340 /* Get the hardware key cache size. */
1341 sc->sc_keymax = ah->ah_caps.keycache_size;
1342 if (sc->sc_keymax > ATH_KEYMAX) {
1343 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1344 "Warning, using only %u entries in %u key cache\n",
1345 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1346 sc->sc_keymax = ATH_KEYMAX;
1347 }
1348
1349 /*
1350 * Reset the key cache since some parts do not
1351 * reset the contents on initial power up.
1352 */
1353 for (i = 0; i < sc->sc_keymax; i++)
1354 ath9k_hw_keyreset(ah, (u16) i);
1355 /*
1356 * Mark key cache slots associated with global keys
1357 * as in use. If we knew TKIP was not to be used we
1358 * could leave the +32, +64, and +32+64 slots free.
1359 * XXX only for splitmic.
1360 */
1361 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1362 set_bit(i, sc->sc_keymap);
1363 set_bit(i + 32, sc->sc_keymap);
1364 set_bit(i + 64, sc->sc_keymap);
1365 set_bit(i + 32 + 64, sc->sc_keymap);
1366 }
1367
1368 /* Collect the channel list using the default country code */
1369
1370 error = ath_setup_channels(sc);
1371 if (error)
1372 goto bad;
1373
1374 /* default to MONITOR mode */
1375 sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1376
1377 /* Setup rate tables */
1378
1379 ath_rate_attach(sc);
1380 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1381 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1382
1383 /*
1384 * Allocate hardware transmit queues: one queue for
1385 * beacon frames and one data queue for each QoS
1386 * priority. Note that the hal handles reseting
1387 * these queues at the needed time.
1388 */
1389 sc->sc_bhalq = ath_beaconq_setup(ah);
1390 if (sc->sc_bhalq == -1) {
1391 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1392 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1393 error = -EIO;
1394 goto bad2;
1395 }
1396 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->sc_cabq == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1405 ath_cabq_update(sc);
1406
1407 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1408 sc->sc_haltype2q[i] = -1;
1409
1410 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1414 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1415 error = -EIO;
1416 goto bad2;
1417 }
1418
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1421 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1422 error = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1428 error = -EIO;
1429 goto bad2;
1430 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1433 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1434 error = -EIO;
1435 goto bad2;
1436 }
1437
1438 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */
1440
1441 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1443
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) {
1446 /*
1447 * Whether we should enable h/w TKIP MIC.
1448 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1449 * report WMM capable, so it's always safe to turn on
1450 * TKIP MIC in this case.
1451 */
1452 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1453 0, 1, NULL);
1454 }
1455
1456 /*
1457 * Check whether the separate key cache entries
1458 * are required to handle both tx+rx MIC keys.
1459 * With split mic keys the number of stations is limited
1460 * to 27 otherwise 59.
1461 */
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)
1464 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL))
1468 sc->sc_splitmic = 1;
1469
1470 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1472 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1473 1, NULL);
1474
1475 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1476 sc->sc_config.txpowlimit_override = 0;
1477
1478 /* 11n Capabilities */
1479 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1480 sc->sc_flags |= SC_OP_TXAGGR;
1481 sc->sc_flags |= SC_OP_RXAGGR;
1482 }
1483
1484 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1485 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1486
1487 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1488 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1489
1490 ath9k_hw_getmac(ah, sc->sc_myaddr);
1491 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1492 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1493 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1494 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1495 }
1496
1497 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1498
1499 /* initialize beacon slots */
1500 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1501 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1502
1503 /* save MISC configurations */
1504 sc->sc_config.swBeaconProcess = 1;
1505
1506#ifdef CONFIG_SLOW_ANT_DIV
1507 /* range is 40 - 255, we use something in the middle */
1508 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1509#endif
1510
1511 /* setup channels and rates */
1512
1513 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1514 sc->channels[IEEE80211_BAND_2GHZ];
1515 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1516 sc->rates[IEEE80211_BAND_2GHZ];
1517 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1518
1519 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1520 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1521 sc->channels[IEEE80211_BAND_5GHZ];
1522 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1523 sc->rates[IEEE80211_BAND_5GHZ];
1524 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1525 }
1526
1527 return 0;
1528bad2:
1529 /* cleanup tx queues */
1530 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1531 if (ATH_TXQ_SETUP(sc, i))
1532 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1533bad:
1534 if (ah)
1535 ath9k_hw_detach(ah);
1536
1537 return error;
1538}
1539
9c84b797 1540static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1541{
8feceb67
VT		 1542 struct ieee80211_hw *hw = sc->hw;
1543 int error = 0;
f078f209 1544
04bd4638 1545 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1546
8feceb67
VT		 1547 error = ath_init(devid, sc);
1548 if (error != 0)
1549 return error;
f078f209 1550
8feceb67 1551 /* get mac address from hardware and set in mac80211 */
f078f209 1552
8feceb67 1553 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1554
9c84b797
S		 1555 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1556 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1557 IEEE80211_HW_SIGNAL_DBM |
1558 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1559
9c84b797
S		 1560 hw->wiphy->interface_modes =
1561 BIT(NL80211_IFTYPE_AP) |
1562 BIT(NL80211_IFTYPE_STATION) |
1563 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1564
8feceb67 1565 hw->queues = 4;
e63835b0
S		 1566 hw->max_rates = 4;
1567 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1568 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1569 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1570
8feceb67
VT		 1571 /* Register rate control */
1572 hw->rate_control_algorithm = "ath9k_rate_control";
1573 error = ath_rate_control_register();
1574 if (error != 0) {
1575 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1576 "Unable to register rate control algorithm: %d\n", error);
8feceb67
VT		 1577 ath_rate_control_unregister();
1578 goto bad;
1579 }
f078f209 1580
9c84b797
S		 1581 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1582 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1583 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1584 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1585 }
1586
1587 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1588 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1589 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1590 &sc->sbands[IEEE80211_BAND_5GHZ];
1591
db93e7b5
SB		 1592 /* initialize tx/rx engine */
1593 error = ath_tx_init(sc, ATH_TXBUF);
1594 if (error != 0)
1595 goto detach;
8feceb67 1596
db93e7b5
SB		 1597 error = ath_rx_init(sc, ATH_RXBUF);
1598 if (error != 0)
1599 goto detach;
8feceb67 1600
e97275cb 1601#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1602 /* Initialze h/w Rfkill */
1603 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1604 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1605
1606 /* Initialize s/w rfkill */
1607 if (ath_init_sw_rfkill(sc))
1608 goto detach;
1609#endif
1610
db93e7b5
SB		 1611 error = ieee80211_register_hw(hw);
1612 if (error != 0) {
1613 ath_rate_control_unregister();
1614 goto bad;
1615 }
8feceb67 1616
db93e7b5
SB		 1617 /* Initialize LED control */
1618 ath_init_leds(sc);
8feceb67
VT		 1619
1620 return 0;
1621detach:
1622 ath_detach(sc);
1623bad:
1624 return error;
f078f209
LR		 1625}
1626
ff37e337
S		 1627int ath_reset(struct ath_softc *sc, bool retry_tx)
1628{
1629 struct ath_hal *ah = sc->sc_ah;
1630 int status;
1631 int error = 0;
1632
1633 ath9k_hw_set_interrupts(ah, 0);
1634 ath_draintxq(sc, retry_tx);
1635 ath_stoprecv(sc);
1636 ath_flushrecv(sc);
1637
1638 spin_lock_bh(&sc->sc_resetlock);
1639 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
99405f93 1640 sc->tx_chan_width,
ff37e337
S		 1641 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1642 sc->sc_ht_extprotspacing, false, &status)) {
1643 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1644 "Unable to reset hardware; hal status %u\n", status);
ff37e337
S		 1645 error = -EIO;
1646 }
1647 spin_unlock_bh(&sc->sc_resetlock);
1648
1649 if (ath_startrecv(sc) != 0)
04bd4638 1650 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1651
1652 /*
1653 * We may be doing a reset in response to a request
1654 * that changes the channel so update any state that
1655 * might change as a result.
1656 */
1657 ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1658
1659 ath_update_txpow(sc);
1660
1661 if (sc->sc_flags & SC_OP_BEACONS)
1662 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1663
1664 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1665
1666 if (retry_tx) {
1667 int i;
1668 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1669 if (ATH_TXQ_SETUP(sc, i)) {
1670 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1671 ath_txq_schedule(sc, &sc->sc_txq[i]);
1672 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1673 }
1674 }
1675 }
1676
1677 return error;
1678}
1679
1680/*
1681 * This function will allocate both the DMA descriptor structure, and the
1682 * buffers it contains. These are used to contain the descriptors used
1683 * by the system.
1684*/
1685int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1686 struct list_head *head, const char *name,
1687 int nbuf, int ndesc)
1688{
1689#define DS2PHYS(_dd, _ds) \
1690 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1691#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1692#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1693
1694 struct ath_desc *ds;
1695 struct ath_buf *bf;
1696 int i, bsize, error;
1697
04bd4638
S		 1698 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1699 name, nbuf, ndesc);
ff37e337
S		 1700
1701 /* ath_desc must be a multiple of DWORDs */
1702 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1703 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1704 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708
1709 dd->dd_name = name;
1710 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1711
1712 /*
1713 * Need additional DMA memory because we can't use
1714 * descriptors that cross the 4K page boundary. Assume
1715 * one skipped descriptor per 4K page.
1716 */
1717 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1718 u32 ndesc_skipped =
1719 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1720 u32 dma_len;
1721
1722 while (ndesc_skipped) {
1723 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1724 dd->dd_desc_len += dma_len;
1725
1726 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1727 };
1728 }
1729
1730 /* allocate descriptors */
1731 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1732 dd->dd_desc_len,
1733 &dd->dd_desc_paddr);
1734 if (dd->dd_desc == NULL) {
1735 error = -ENOMEM;
1736 goto fail;
1737 }
1738 ds = dd->dd_desc;
04bd4638
S		 1739 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1740 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1741 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1742
1743 /* allocate buffers */
1744 bsize = sizeof(struct ath_buf) * nbuf;
1745 bf = kmalloc(bsize, GFP_KERNEL);
1746 if (bf == NULL) {
1747 error = -ENOMEM;
1748 goto fail2;
1749 }
1750 memset(bf, 0, bsize);
1751 dd->dd_bufptr = bf;
1752
1753 INIT_LIST_HEAD(head);
1754 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1755 bf->bf_desc = ds;
1756 bf->bf_daddr = DS2PHYS(dd, ds);
1757
1758 if (!(sc->sc_ah->ah_caps.hw_caps &
1759 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1760 /*
1761 * Skip descriptor addresses which can cause 4KB
1762 * boundary crossing (addr + length) with a 32 dword
1763 * descriptor fetch.
1764 */
1765 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1766 ASSERT((caddr_t) bf->bf_desc <
1767 ((caddr_t) dd->dd_desc +
1768 dd->dd_desc_len));
1769
1770 ds += ndesc;
1771 bf->bf_desc = ds;
1772 bf->bf_daddr = DS2PHYS(dd, ds);
1773 }
1774 }
1775 list_add_tail(&bf->list, head);
1776 }
1777 return 0;
1778fail2:
1779 pci_free_consistent(sc->pdev,
1780 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1781fail:
1782 memset(dd, 0, sizeof(*dd));
1783 return error;
1784#undef ATH_DESC_4KB_BOUND_CHECK
1785#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1786#undef DS2PHYS
1787}
1788
1789void ath_descdma_cleanup(struct ath_softc *sc,
1790 struct ath_descdma *dd,
1791 struct list_head *head)
1792{
1793 pci_free_consistent(sc->pdev,
1794 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1795
1796 INIT_LIST_HEAD(head);
1797 kfree(dd->dd_bufptr);
1798 memset(dd, 0, sizeof(*dd));
1799}
1800
1801int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1802{
1803 int qnum;
1804
1805 switch (queue) {
1806 case 0:
1807 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1808 break;
1809 case 1:
1810 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1811 break;
1812 case 2:
1813 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1814 break;
1815 case 3:
1816 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1817 break;
1818 default:
1819 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1820 break;
1821 }
1822
1823 return qnum;
1824}
1825
1826int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1827{
1828 int qnum;
1829
1830 switch (queue) {
1831 case ATH9K_WME_AC_VO:
1832 qnum = 0;
1833 break;
1834 case ATH9K_WME_AC_VI:
1835 qnum = 1;
1836 break;
1837 case ATH9K_WME_AC_BE:
1838 qnum = 2;
1839 break;
1840 case ATH9K_WME_AC_BK:
1841 qnum = 3;
1842 break;
1843 default:
1844 qnum = -1;
1845 break;
1846 }
1847
1848 return qnum;
1849}
1850
1851/**********************/
1852/* mac80211 callbacks */
1853/**********************/
1854
8feceb67 1855static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1856{
1857 struct ath_softc *sc = hw->priv;
8feceb67 1858 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337
S		 1859 struct ath9k_channel *init_channel;
1860 int error = 0, pos, status;
f078f209 1861
04bd4638
S		 1862 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1863 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1864
8feceb67 1865 /* setup initial channel */
f078f209 1866
8feceb67
VT		 1867 pos = ath_get_channel(sc, curchan);
1868 if (pos == -1) {
04bd4638 1869 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
9c84b797 1870 error = -EINVAL;
ff37e337 1871 goto error;
f078f209
LR		 1872 }
1873
99405f93 1874 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1875 sc->sc_ah->ah_channels[pos].chanmode =
1876 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1877 init_channel = &sc->sc_ah->ah_channels[pos];
1878
1879 /* Reset SERDES registers */
1880 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1881
1882 /*
1883 * The basic interface to setting the hardware in a good
1884 * state is ``reset''. On return the hardware is known to
1885 * be powered up and with interrupts disabled. This must
1886 * be followed by initialization of the appropriate bits
1887 * and then setup of the interrupt mask.
1888 */
1889 spin_lock_bh(&sc->sc_resetlock);
1890 if (!ath9k_hw_reset(sc->sc_ah, init_channel,
99405f93 1891 sc->tx_chan_width,
ff37e337
S		 1892 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1893 sc->sc_ht_extprotspacing, false, &status)) {
1894 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638
S		 1895 "Unable to reset hardware; hal status %u "
1896 "(freq %u flags 0x%x)\n", status,
ff37e337
S		 1897 init_channel->channel, init_channel->channelFlags);
1898 error = -EIO;
1899 spin_unlock_bh(&sc->sc_resetlock);
1900 goto error;
1901 }
1902 spin_unlock_bh(&sc->sc_resetlock);
1903
1904 /*
1905 * This is needed only to setup initial state
1906 * but it's best done after a reset.
1907 */
1908 ath_update_txpow(sc);
8feceb67 1909
ff37e337
S		 1910 /*
1911 * Setup the hardware after reset:
1912 * The receive engine is set going.
1913 * Frame transmit is handled entirely
1914 * in the frame output path; there's nothing to do
1915 * here except setup the interrupt mask.
1916 */
1917 if (ath_startrecv(sc) != 0) {
8feceb67 1918 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1919 "Unable to start recv logic\n");
ff37e337
S		 1920 error = -EIO;
1921 goto error;
f078f209 1922 }
8feceb67 1923
ff37e337
S		 1924 /* Setup our intr mask. */
1925 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1926 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1927 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1928
1929 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1930 sc->sc_imask |= ATH9K_INT_GTT;
1931
1932 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1933 sc->sc_imask |= ATH9K_INT_CST;
1934
1935 /*
1936 * Enable MIB interrupts when there are hardware phy counters.
1937 * Note we only do this (at the moment) for station mode.
1938 */
1939 if (ath9k_hw_phycounters(sc->sc_ah) &&
1940 ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
1941 (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
1942 sc->sc_imask |= ATH9K_INT_MIB;
1943 /*
1944 * Some hardware processes the TIM IE and fires an
1945 * interrupt when the TIM bit is set. For hardware
1946 * that does, if not overridden by configuration,
1947 * enable the TIM interrupt when operating as station.
1948 */
1949 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1950 (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
1951 !sc->sc_config.swBeaconProcess)
1952 sc->sc_imask |= ATH9K_INT_TIM;
1953
1954 ath_setcurmode(sc, ath_chan2mode(init_channel));
1955
1956 sc->sc_flags &= ~SC_OP_INVALID;
1957
1958 /* Disable BMISS interrupt when we're not associated */
1959 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1960 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1961
1962 ieee80211_wake_queues(sc->hw);
1963
e97275cb 1964#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1965 error = ath_start_rfkill_poll(sc);
500c064d
VT		 1966#endif
1967
ff37e337 1968error:
9c84b797 1969 return error;
f078f209
LR		 1970}
1971
8feceb67
VT		 1972static int ath9k_tx(struct ieee80211_hw *hw,
1973 struct sk_buff *skb)
f078f209 1974{
528f0c6b 1975 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1976 struct ath_softc *sc = hw->priv;
528f0c6b 1977 struct ath_tx_control txctl;
8feceb67 1978 int hdrlen, padsize;
528f0c6b
S		 1979
1980 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1981
8feceb67
VT		 1982 /*
1983 * As a temporary workaround, assign seq# here; this will likely need
1984 * to be cleaned up to work better with Beacon transmission and virtual
1985 * BSSes.
1986 */
1987 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1988 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1989 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1990 sc->seq_no += 0x10;
1991 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1992 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1993 }
f078f209 1994
8feceb67
VT		 1995 /* Add the padding after the header if this is not already done */
1996 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1997 if (hdrlen & 3) {
1998 padsize = hdrlen % 4;
1999 if (skb_headroom(skb) < padsize)
2000 return -1;
2001 skb_push(skb, padsize);
2002 memmove(skb->data, skb->data + padsize, hdrlen);
2003 }
2004
528f0c6b
S		 2005 /* Check if a tx queue is available */
2006
2007 txctl.txq = ath_test_get_txq(sc, skb);
2008 if (!txctl.txq)
2009 goto exit;
2010
04bd4638 2011 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2012
528f0c6b 2013 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 2014 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2015 goto exit;
8feceb67
VT		 2016 }
2017
528f0c6b
S		 2018 return 0;
2019exit:
2020 dev_kfree_skb_any(skb);
8feceb67 2021 return 0;
f078f209
LR		 2022}
2023
8feceb67 2024static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 2025{
2026 struct ath_softc *sc = hw->priv;
f078f209 2027
9c84b797 2028 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2029 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2030 return;
2031 }
8feceb67 2032
04bd4638 2033 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2034
2035 ieee80211_stop_queues(sc->hw);
2036
2037 /* make sure h/w will not generate any interrupt
2038 * before setting the invalid flag. */
2039 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2040
2041 if (!(sc->sc_flags & SC_OP_INVALID)) {
2042 ath_draintxq(sc, false);
2043 ath_stoprecv(sc);
2044 ath9k_hw_phy_disable(sc->sc_ah);
2045 } else
2046 sc->sc_rxlink = NULL;
2047
2048#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2049 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2050 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2051#endif
2052 /* disable HAL and put h/w to sleep */
2053 ath9k_hw_disable(sc->sc_ah);
2054 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2055
2056 sc->sc_flags |= SC_OP_INVALID;
500c064d 2057
04bd4638 2058 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2059}
2060
8feceb67
VT		 2061static int ath9k_add_interface(struct ieee80211_hw *hw,
2062 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2063{
2064 struct ath_softc *sc = hw->priv;
5640b08e
S		 2065 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2066 int ic_opmode = 0;
f078f209 2067
8feceb67
VT		 2068 /* Support only vap for now */
2069
2070 if (sc->sc_nvaps)
2071 return -ENOBUFS;
2072
2073 switch (conf->type) {
05c914fe 2074 case NL80211_IFTYPE_STATION:
8feceb67 2075 ic_opmode = ATH9K_M_STA;
f078f209 2076 break;
05c914fe 2077 case NL80211_IFTYPE_ADHOC:
8feceb67 2078 ic_opmode = ATH9K_M_IBSS;
f078f209 2079 break;
05c914fe 2080 case NL80211_IFTYPE_AP:
8feceb67 2081 ic_opmode = ATH9K_M_HOSTAP;
f078f209
LR		 2082 break;
2083 default:
2084 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2085 "Interface type %d not yet supported\n", conf->type);
8feceb67 2086 return -EOPNOTSUPP;
f078f209
LR		 2087 }
2088
04bd4638 2089 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2090
5640b08e
S		 2091 /* Set the VAP opmode */
2092 avp->av_opmode = ic_opmode;
2093 avp->av_bslot = -1;
2094
2095 if (ic_opmode == ATH9K_M_HOSTAP)
2096 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2097
2098 sc->sc_vaps[0] = conf->vif;
2099 sc->sc_nvaps++;
2100
2101 /* Set the device opmode */
2102 sc->sc_ah->ah_opmode = ic_opmode;
2103
6f255425
LR		 2104 if (conf->type == NL80211_IFTYPE_AP) {
2105 /* TODO: is this a suitable place to start ANI for AP mode? */
2106 /* Start ANI */
2107 mod_timer(&sc->sc_ani.timer,
2108 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2109 }
2110
8feceb67 2111 return 0;
f078f209
LR		 2112}
2113
8feceb67
VT		 2114static void ath9k_remove_interface(struct ieee80211_hw *hw,
2115 struct ieee80211_if_init_conf *conf)
f078f209 2116{
8feceb67 2117 struct ath_softc *sc = hw->priv;
5640b08e 2118 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2119
04bd4638 2120 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2121
8feceb67
VT		 2122#ifdef CONFIG_SLOW_ANT_DIV
2123 ath_slow_ant_div_stop(&sc->sc_antdiv);
2124#endif
6f255425
LR		 2125 /* Stop ANI */
2126 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2127
8feceb67
VT		 2128 /* Reclaim beacon resources */
2129 if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
2130 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
2131 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2132 ath_beacon_return(sc, avp);
580f0b8a 2133 }
f078f209 2134
8feceb67 2135 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2136
5640b08e
S		 2137 sc->sc_vaps[0] = NULL;
2138 sc->sc_nvaps--;
f078f209
LR		 2139}
2140
e8975581 2141static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2142{
8feceb67 2143 struct ath_softc *sc = hw->priv;
e8975581 2144 struct ieee80211_conf *conf = &hw->conf;
f078f209 2145
99405f93
S		 2146 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2147 struct ieee80211_channel *curchan = hw->conf.channel;
2148 int pos;
ae5eb026 2149
04bd4638
S		 2150 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2151 curchan->center_freq);
f078f209 2152
99405f93
S		 2153 pos = ath_get_channel(sc, curchan);
2154 if (pos == -1) {
04bd4638
S		 2155 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2156 curchan->center_freq);
99405f93
S		 2157 return -EINVAL;
2158 }
f078f209 2159
99405f93 2160 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2161 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2162 (curchan->band == IEEE80211_BAND_2GHZ) ?
2163 CHANNEL_G : CHANNEL_A;
2164
e11602b7
S		 2165 if ((sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) &&
2166 (conf->ht.enabled)) {
2167 sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ?
2168 ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20;
2169
2170 sc->sc_ah->ah_channels[pos].chanmode =
2171 ath_get_extchanmode(sc, curchan,
2172 conf->ht.sec_chan_offset,
2173 sc->tx_chan_width);
2174 }
2175
2176 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2177 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
e11602b7
S		 2178 return -EINVAL;
2179 }
99405f93
S		 2180 }
2181
2182 if (changed & IEEE80211_CONF_CHANGE_HT)
2183 ath_update_chainmask(sc, conf->ht.enabled);
f078f209 2184
5c020dc6
LR		 2185 if (changed & IEEE80211_CONF_CHANGE_POWER)
2186 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2187
f078f209
LR		 2188 return 0;
2189}
2190
8feceb67
VT		 2191static int ath9k_config_interface(struct ieee80211_hw *hw,
2192 struct ieee80211_vif *vif,
2193 struct ieee80211_if_conf *conf)
c83be688 2194{
8feceb67
VT		 2195 struct ath_softc *sc = hw->priv;
2196 struct ath_hal *ah = sc->sc_ah;
5640b08e 2197 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2198 u32 rfilt = 0;
2199 int error, i;
c83be688 2200
8feceb67
VT		 2201 /* TODO: Need to decide which hw opmode to use for multi-interface
2202 * cases */
05c914fe 2203 if (vif->type == NL80211_IFTYPE_AP &&
8feceb67
VT		 2204 ah->ah_opmode != ATH9K_M_HOSTAP) {
2205 ah->ah_opmode = ATH9K_M_HOSTAP;
2206 ath9k_hw_setopmode(ah);
2207 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2208 /* Request full reset to get hw opmode changed properly */
2209 sc->sc_flags |= SC_OP_FULL_RESET;
2210 }
c83be688 2211
8feceb67
VT		 2212 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2213 !is_zero_ether_addr(conf->bssid)) {
2214 switch (vif->type) {
05c914fe
JB		 2215 case NL80211_IFTYPE_STATION:
2216 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2217 /* Set BSSID */
2218 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2219 sc->sc_curaid = 0;
2220 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2221 sc->sc_curaid);
c83be688 2222
8feceb67
VT		 2223 /* Set aggregation protection mode parameters */
2224 sc->sc_config.ath_aggr_prot = 0;
c83be688 2225
8feceb67 2226 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2227 "RX filter 0x%x bssid %pM aid 0x%x\n",
2228 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2229
8feceb67
VT		 2230 /* need to reconfigure the beacon */
2231 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2232
8feceb67
VT		 2233 break;
2234 default:
2235 break;
2236 }
2237 }
c83be688 2238
8feceb67 2239 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2240 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2241 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2242 /*
2243 * Allocate and setup the beacon frame.
2244 *
2245 * Stop any previous beacon DMA. This may be
2246 * necessary, for example, when an ibss merge
2247 * causes reconfiguration; we may be called
2248 * with beacon transmission active.
2249 */
2250 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
c83be688 2251
8feceb67
VT		 2252 error = ath_beacon_alloc(sc, 0);
2253 if (error != 0)
2254 return error;
c83be688 2255
8feceb67
VT		 2256 ath_beacon_sync(sc, 0);
2257 }
c83be688 2258
8feceb67 2259 /* Check for WLAN_CAPABILITY_PRIVACY ? */
5640b08e 2260 if ((avp->av_opmode != ATH9K_M_STA)) {
8feceb67
VT		 2261 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2262 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2263 ath9k_hw_keysetmac(sc->sc_ah,
2264 (u16)i,
2265 sc->sc_curbssid);
2266 }
c83be688 2267
8feceb67 2268 /* Only legacy IBSS for now */
05c914fe 2269 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2270 ath_update_chainmask(sc, 0);
f078f209 2271
8feceb67
VT		 2272 return 0;
2273}
f078f209 2274
8feceb67
VT		 2275#define SUPPORTED_FILTERS \
2276 (FIF_PROMISC_IN_BSS | \
2277 FIF_ALLMULTI | \
2278 FIF_CONTROL | \
2279 FIF_OTHER_BSS | \
2280 FIF_BCN_PRBRESP_PROMISC | \
2281 FIF_FCSFAIL)
c83be688 2282
8feceb67
VT		 2283/* FIXME: sc->sc_full_reset ? */
2284static void ath9k_configure_filter(struct ieee80211_hw *hw,
2285 unsigned int changed_flags,
2286 unsigned int *total_flags,
2287 int mc_count,
2288 struct dev_mc_list *mclist)
2289{
2290 struct ath_softc *sc = hw->priv;
2291 u32 rfilt;
f078f209 2292
8feceb67
VT		 2293 changed_flags &= SUPPORTED_FILTERS;
2294 *total_flags &= SUPPORTED_FILTERS;
f078f209 2295
8feceb67
VT		 2296 sc->rx_filter = *total_flags;
2297 rfilt = ath_calcrxfilter(sc);
2298 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2299
8feceb67
VT		 2300 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2301 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2302 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2303 }
f078f209 2304
04bd4638 2305 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter);
8feceb67 2306}
f078f209 2307
8feceb67
VT		 2308static void ath9k_sta_notify(struct ieee80211_hw *hw,
2309 struct ieee80211_vif *vif,
2310 enum sta_notify_cmd cmd,
17741cdc 2311 struct ieee80211_sta *sta)
8feceb67
VT		 2312{
2313 struct ath_softc *sc = hw->priv;
f078f209 2314
8feceb67
VT		 2315 switch (cmd) {
2316 case STA_NOTIFY_ADD:
5640b08e 2317 ath_node_attach(sc, sta);
8feceb67
VT		 2318 break;
2319 case STA_NOTIFY_REMOVE:
b5aa9bf9 2320 ath_node_detach(sc, sta);
8feceb67
VT		 2321 break;
2322 default:
2323 break;
2324 }
f078f209
LR		 2325}
2326
8feceb67
VT		 2327static int ath9k_conf_tx(struct ieee80211_hw *hw,
2328 u16 queue,
2329 const struct ieee80211_tx_queue_params *params)
f078f209 2330{
8feceb67
VT		 2331 struct ath_softc *sc = hw->priv;
2332 struct ath9k_tx_queue_info qi;
2333 int ret = 0, qnum;
f078f209 2334
8feceb67
VT		 2335 if (queue >= WME_NUM_AC)
2336 return 0;
f078f209 2337
8feceb67
VT		 2338 qi.tqi_aifs = params->aifs;
2339 qi.tqi_cwmin = params->cw_min;
2340 qi.tqi_cwmax = params->cw_max;
2341 qi.tqi_burstTime = params->txop;
2342 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2343
8feceb67 2344 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2345 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2346 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2347 queue, qnum, params->aifs, params->cw_min,
2348 params->cw_max, params->txop);
f078f209 2349
8feceb67
VT		 2350 ret = ath_txq_update(sc, qnum, &qi);
2351 if (ret)
04bd4638 2352 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2353
8feceb67
VT		 2354 return ret;
2355}
f078f209 2356
8feceb67
VT		 2357static int ath9k_set_key(struct ieee80211_hw *hw,
2358 enum set_key_cmd cmd,
2359 const u8 *local_addr,
2360 const u8 *addr,
2361 struct ieee80211_key_conf *key)
2362{
2363 struct ath_softc *sc = hw->priv;
2364 int ret = 0;
f078f209 2365
04bd4638 2366 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2367
8feceb67
VT		 2368 switch (cmd) {
2369 case SET_KEY:
2370 ret = ath_key_config(sc, addr, key);
2371 if (!ret) {
2372 set_bit(key->keyidx, sc->sc_keymap);
2373 key->hw_key_idx = key->keyidx;
2374 /* push IV and Michael MIC generation to stack */
2375 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2376 if (key->alg == ALG_TKIP)
2377 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2378 }
2379 break;
2380 case DISABLE_KEY:
2381 ath_key_delete(sc, key);
2382 clear_bit(key->keyidx, sc->sc_keymap);
8feceb67
VT		 2383 break;
2384 default:
2385 ret = -EINVAL;
2386 }
f078f209 2387
8feceb67
VT		 2388 return ret;
2389}
f078f209 2390
8feceb67
VT		 2391static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2392 struct ieee80211_vif *vif,
2393 struct ieee80211_bss_conf *bss_conf,
2394 u32 changed)
2395{
2396 struct ath_softc *sc = hw->priv;
f078f209 2397
8feceb67 2398 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2399 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2400 bss_conf->use_short_preamble);
2401 if (bss_conf->use_short_preamble)
2402 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2403 else
2404 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2405 }
f078f209 2406
8feceb67 2407 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2408 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2409 bss_conf->use_cts_prot);
2410 if (bss_conf->use_cts_prot &&
2411 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2412 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2413 else
2414 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2415 }
f078f209 2416
99405f93 2417 if (changed & BSS_CHANGED_HT)
8feceb67 2418 ath9k_ht_conf(sc, bss_conf);
f078f209 2419
8feceb67 2420 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2421 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2422 bss_conf->assoc);
5640b08e 2423 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2424 }
2425}
f078f209 2426
8feceb67
VT		 2427static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2428{
2429 u64 tsf;
2430 struct ath_softc *sc = hw->priv;
2431 struct ath_hal *ah = sc->sc_ah;
f078f209 2432
8feceb67 2433 tsf = ath9k_hw_gettsf64(ah);
f078f209 2434
8feceb67
VT		 2435 return tsf;
2436}
f078f209 2437
8feceb67
VT		 2438static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2439{
2440 struct ath_softc *sc = hw->priv;
2441 struct ath_hal *ah = sc->sc_ah;
c83be688 2442
8feceb67
VT		 2443 ath9k_hw_reset_tsf(ah);
2444}
f078f209 2445
8feceb67
VT		 2446static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2447 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2448 struct ieee80211_sta *sta,
2449 u16 tid, u16 *ssn)
8feceb67
VT		 2450{
2451 struct ath_softc *sc = hw->priv;
2452 int ret = 0;
f078f209 2453
8feceb67
VT		 2454 switch (action) {
2455 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2456 if (!(sc->sc_flags & SC_OP_RXAGGR))
2457 ret = -ENOTSUPP;
8feceb67
VT		 2458 break;
2459 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2460 break;
2461 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2462 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2463 if (ret < 0)
2464 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2465 "Unable to start TX aggregation\n");
8feceb67 2466 else
17741cdc 2467 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2468 break;
2469 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2470 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2471 if (ret < 0)
2472 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2473 "Unable to stop TX aggregation\n");
f078f209 2474
17741cdc 2475 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2476 break;
8469cdef
S		 2477 case IEEE80211_AMPDU_TX_RESUME:
2478 ath_tx_aggr_resume(sc, sta, tid);
2479 break;
8feceb67 2480 default:
04bd4638 2481 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2482 }
2483
2484 return ret;
f078f209
LR		 2485}
2486
4233df6b
JB		 2487static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2488{
2489 return -EOPNOTSUPP;
2490}
2491
8feceb67
VT		 2492static struct ieee80211_ops ath9k_ops = {
2493 .tx = ath9k_tx,
2494 .start = ath9k_start,
2495 .stop = ath9k_stop,
2496 .add_interface = ath9k_add_interface,
2497 .remove_interface = ath9k_remove_interface,
2498 .config = ath9k_config,
2499 .config_interface = ath9k_config_interface,
2500 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2501 .sta_notify = ath9k_sta_notify,
2502 .conf_tx = ath9k_conf_tx,
8feceb67 2503 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2504 .set_key = ath9k_set_key,
8feceb67
VT		 2505 .get_tsf = ath9k_get_tsf,
2506 .reset_tsf = ath9k_reset_tsf,
4233df6b
JB		 2507 .ampdu_action = ath9k_ampdu_action,
2508 .set_frag_threshold = ath9k_no_fragmentation,
8feceb67
VT		 2509};
2510
392dff83
BP		 2511static struct {
2512 u32 version;
2513 const char * name;
2514} ath_mac_bb_names[] = {
2515 { AR_SREV_VERSION_5416_PCI, "5416" },
2516 { AR_SREV_VERSION_5416_PCIE, "5418" },
2517 { AR_SREV_VERSION_9100, "9100" },
2518 { AR_SREV_VERSION_9160, "9160" },
2519 { AR_SREV_VERSION_9280, "9280" },
2520 { AR_SREV_VERSION_9285, "9285" }
2521};
2522
2523static struct {
2524 u16 version;
2525 const char * name;
2526} ath_rf_names[] = {
2527 { 0, "5133" },
2528 { AR_RAD5133_SREV_MAJOR, "5133" },
2529 { AR_RAD5122_SREV_MAJOR, "5122" },
2530 { AR_RAD2133_SREV_MAJOR, "2133" },
2531 { AR_RAD2122_SREV_MAJOR, "2122" }
2532};
2533
2534/*
2535 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2536 */
392dff83
BP		 2537static const char *
2538ath_mac_bb_name(u32 mac_bb_version)
2539{
2540 int i;
2541
2542 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2543 if (ath_mac_bb_names[i].version == mac_bb_version) {
2544 return ath_mac_bb_names[i].name;
2545 }
2546 }
2547
2548 return "????";
2549}
2550
2551/*
2552 * Return the RF name. "????" is returned if the RF is unknown.
2553 */
392dff83
BP		 2554static const char *
2555ath_rf_name(u16 rf_version)
2556{
2557 int i;
2558
2559 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2560 if (ath_rf_names[i].version == rf_version) {
2561 return ath_rf_names[i].name;
2562 }
2563 }
2564
2565 return "????";
2566}
2567
f078f209
LR		 2568static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2569{
2570 void __iomem *mem;
2571 struct ath_softc *sc;
2572 struct ieee80211_hw *hw;
f078f209
LR		 2573 u8 csz;
2574 u32 val;
2575 int ret = 0;
392dff83 2576 struct ath_hal *ah;
f078f209
LR		 2577
2578 if (pci_enable_device(pdev))
2579 return -EIO;
2580
97b777db
LR		 2581 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2582
2583 if (ret) {
1d450cfc 2584 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2585 goto bad;
2586 }
2587
2588 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2589
2590 if (ret) {
2591 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2592 "DMA enable failed\n");
f078f209
LR		 2593 goto bad;
2594 }
2595
2596 /*
2597 * Cache line size is used to size and align various
2598 * structures used to communicate with the hardware.
2599 */
2600 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2601 if (csz == 0) {
2602 /*
2603 * Linux 2.4.18 (at least) writes the cache line size
2604 * register as a 16-bit wide register which is wrong.
2605 * We must have this setup properly for rx buffer
2606 * DMA to work so force a reasonable value here if it
2607 * comes up zero.
2608 */
2609 csz = L1_CACHE_BYTES / sizeof(u32);
2610 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2611 }
2612 /*
2613 * The default setting of latency timer yields poor results,
2614 * set it to the value used by other systems. It may be worth
2615 * tweaking this setting more.
2616 */
2617 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2618
2619 pci_set_master(pdev);
2620
2621 /*
2622 * Disable the RETRY_TIMEOUT register (0x41) to keep
2623 * PCI Tx retries from interfering with C3 CPU state.
2624 */
2625 pci_read_config_dword(pdev, 0x40, &val);
2626 if ((val & 0x0000ff00) != 0)
2627 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2628
2629 ret = pci_request_region(pdev, 0, "ath9k");
2630 if (ret) {
2631 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2632 ret = -ENODEV;
2633 goto bad;
2634 }
2635
2636 mem = pci_iomap(pdev, 0, 0);
2637 if (!mem) {
2638 printk(KERN_ERR "PCI memory map error\n") ;
2639 ret = -EIO;
2640 goto bad1;
2641 }
2642
2643 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2644 if (hw == NULL) {
2645 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2646 goto bad2;
2647 }
2648
f078f209
LR		 2649 SET_IEEE80211_DEV(hw, &pdev->dev);
2650 pci_set_drvdata(pdev, hw);
2651
2652 sc = hw->priv;
2653 sc->hw = hw;
2654 sc->pdev = pdev;
2655 sc->mem = mem;
2656
2657 if (ath_attach(id->device, sc) != 0) {
2658 ret = -ENODEV;
2659 goto bad3;
2660 }
2661
2662 /* setup interrupt service routine */
2663
2664 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2665 printk(KERN_ERR "%s: request_irq failed\n",
2666 wiphy_name(hw->wiphy));
2667 ret = -EIO;
2668 goto bad4;
2669 }
2670
392dff83
BP		 2671 ah = sc->sc_ah;
2672 printk(KERN_INFO
2673 "%s: Atheros AR%s MAC/BB Rev:%x "
2674 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2675 wiphy_name(hw->wiphy),
392dff83
BP		 2676 ath_mac_bb_name(ah->ah_macVersion),
2677 ah->ah_macRev,
2678 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2679 ah->ah_phyRev,
f078f209
LR		 2680 (unsigned long)mem, pdev->irq);
2681
2682 return 0;
2683bad4:
2684 ath_detach(sc);
2685bad3:
2686 ieee80211_free_hw(hw);
2687bad2:
2688 pci_iounmap(pdev, mem);
2689bad1:
2690 pci_release_region(pdev, 0);
2691bad:
2692 pci_disable_device(pdev);
2693 return ret;
2694}
2695
2696static void ath_pci_remove(struct pci_dev *pdev)
2697{
2698 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2699 struct ath_softc *sc = hw->priv;
2700
f078f209 2701 ath_detach(sc);
9c84b797
S		 2702 if (pdev->irq)
2703 free_irq(pdev->irq, sc);
f078f209
LR		 2704 pci_iounmap(pdev, sc->mem);
2705 pci_release_region(pdev, 0);
2706 pci_disable_device(pdev);
2707 ieee80211_free_hw(hw);
2708}
2709
2710#ifdef CONFIG_PM
2711
2712static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2713{
c83be688
VT		 2714 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2715 struct ath_softc *sc = hw->priv;
2716
2717 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2718
e97275cb 2719#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2720 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2721 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2722#endif
2723
f078f209
LR		 2724 pci_save_state(pdev);
2725 pci_disable_device(pdev);
2726 pci_set_power_state(pdev, 3);
2727
2728 return 0;
2729}
2730
2731static int ath_pci_resume(struct pci_dev *pdev)
2732{
c83be688
VT		 2733 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2734 struct ath_softc *sc = hw->priv;
f078f209
LR		 2735 u32 val;
2736 int err;
2737
2738 err = pci_enable_device(pdev);
2739 if (err)
2740 return err;
2741 pci_restore_state(pdev);
2742 /*
2743 * Suspend/Resume resets the PCI configuration space, so we have to
2744 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2745 * PCI Tx retries from interfering with C3 CPU state
2746 */
2747 pci_read_config_dword(pdev, 0x40, &val);
2748 if ((val & 0x0000ff00) != 0)
2749 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2750
c83be688
VT		 2751 /* Enable LED */
2752 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2753 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2754 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2755
e97275cb 2756#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2757 /*
2758 * check the h/w rfkill state on resume
2759 * and start the rfkill poll timer
2760 */
2761 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2762 queue_delayed_work(sc->hw->workqueue,
2763 &sc->rf_kill.rfkill_poll, 0);
2764#endif
2765
f078f209
LR		 2766 return 0;
2767}
2768
2769#endif /* CONFIG_PM */
2770
2771MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2772
2773static struct pci_driver ath_pci_driver = {
2774 .name = "ath9k",
2775 .id_table = ath_pci_id_table,
2776 .probe = ath_pci_probe,
2777 .remove = ath_pci_remove,
2778#ifdef CONFIG_PM
2779 .suspend = ath_pci_suspend,
2780 .resume = ath_pci_resume,
2781#endif /* CONFIG_PM */
2782};
2783
2784static int __init init_ath_pci(void)
2785{
2786 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2787
2788 if (pci_register_driver(&ath_pci_driver) < 0) {
2789 printk(KERN_ERR
2790 "ath_pci: No devices found, driver not installed.\n");
2791 pci_unregister_driver(&ath_pci_driver);
2792 return -ENODEV;
2793 }
2794
2795 return 0;
2796}
2797module_init(init_ath_pci);
2798
2799static void __exit exit_ath_pci(void)
2800{
2801 pci_unregister_driver(&ath_pci_driver);
04bd4638 2802 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2803}
2804module_exit(exit_ath_pci);
Linux 6.x block layer and io_uring tree(s)