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ath5k: fix off-by-one in gpio checks
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
31static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
e7594072 37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
f078f209
LR		 38 { 0 }
39};
40
9757d556
S		 41static void ath_detach(struct ath_softc *sc);
42
ff37e337
S		 43/* return bus cachesize in 4B word units */
44
45static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46{
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60}
61
ce111bad
LR		 62static void ath_cache_conf_rate(struct ath_softc *sc,
63 struct ieee80211_conf *conf)
ff37e337 64{
030bb495
LR		 65 switch (conf->channel->band) {
66 case IEEE80211_BAND_2GHZ:
67 if (conf_is_ht20(conf))
68 sc->cur_rate_table =
69 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
70 else if (conf_is_ht40_minus(conf))
71 sc->cur_rate_table =
72 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
73 else if (conf_is_ht40_plus(conf))
74 sc->cur_rate_table =
75 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 76 else
030bb495
LR		 77 sc->cur_rate_table =
78 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 79 break;
80 case IEEE80211_BAND_5GHZ:
81 if (conf_is_ht20(conf))
82 sc->cur_rate_table =
83 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
84 else if (conf_is_ht40_minus(conf))
85 sc->cur_rate_table =
86 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
87 else if (conf_is_ht40_plus(conf))
88 sc->cur_rate_table =
89 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
90 else
96742256
LR		 91 sc->cur_rate_table =
92 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 93 break;
94 default:
ce111bad 95 BUG_ON(1);
030bb495
LR		 96 break;
97 }
ff37e337
S		 98}
99
100static void ath_update_txpow(struct ath_softc *sc)
101{
102 struct ath_hal *ah = sc->sc_ah;
103 u32 txpow;
104
105 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
106 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
107 /* read back in case value is clamped */
108 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
109 sc->sc_curtxpow = txpow;
110 }
111}
112
113static u8 parse_mpdudensity(u8 mpdudensity)
114{
115 /*
116 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
117 * 0 for no restriction
118 * 1 for 1/4 us
119 * 2 for 1/2 us
120 * 3 for 1 us
121 * 4 for 2 us
122 * 5 for 4 us
123 * 6 for 8 us
124 * 7 for 16 us
125 */
126 switch (mpdudensity) {
127 case 0:
128 return 0;
129 case 1:
130 case 2:
131 case 3:
132 /* Our lower layer calculations limit our precision to
133 1 microsecond */
134 return 1;
135 case 4:
136 return 2;
137 case 5:
138 return 4;
139 case 6:
140 return 8;
141 case 7:
142 return 16;
143 default:
144 return 0;
145 }
146}
147
148static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
149{
150 struct ath_rate_table *rate_table = NULL;
151 struct ieee80211_supported_band *sband;
152 struct ieee80211_rate *rate;
153 int i, maxrates;
154
155 switch (band) {
156 case IEEE80211_BAND_2GHZ:
157 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
158 break;
159 case IEEE80211_BAND_5GHZ:
160 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
161 break;
162 default:
163 break;
164 }
165
166 if (rate_table == NULL)
167 return;
168
169 sband = &sc->sbands[band];
170 rate = sc->rates[band];
171
172 if (rate_table->rate_cnt > ATH_RATE_MAX)
173 maxrates = ATH_RATE_MAX;
174 else
175 maxrates = rate_table->rate_cnt;
176
177 for (i = 0; i < maxrates; i++) {
178 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
179 rate[i].hw_value = rate_table->info[i].ratecode;
180 sband->n_bitrates++;
04bd4638
S		 181 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
182 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 183 }
184}
185
186static int ath_setup_channels(struct ath_softc *sc)
187{
188 struct ath_hal *ah = sc->sc_ah;
189 int nchan, i, a = 0, b = 0;
190 u8 regclassids[ATH_REGCLASSIDS_MAX];
191 u32 nregclass = 0;
192 struct ieee80211_supported_band *band_2ghz;
193 struct ieee80211_supported_band *band_5ghz;
194 struct ieee80211_channel *chan_2ghz;
195 struct ieee80211_channel *chan_5ghz;
196 struct ath9k_channel *c;
197
198 /* Fill in ah->ah_channels */
199 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
200 regclassids, ATH_REGCLASSIDS_MAX,
201 &nregclass, CTRY_DEFAULT, false, 1)) {
202 u32 rd = ah->ah_currentRD;
203 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 204 "Unable to collect channel list; "
ff37e337 205 "regdomain likely %u country code %u\n",
04bd4638 206 rd, CTRY_DEFAULT);
ff37e337
S		 207 return -EINVAL;
208 }
209
210 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
211 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
212 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
213 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
214
215 for (i = 0; i < nchan; i++) {
216 c = &ah->ah_channels[i];
217 if (IS_CHAN_2GHZ(c)) {
218 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
219 chan_2ghz[a].center_freq = c->channel;
220 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 221 c->chan = &chan_2ghz[a];
ff37e337
S		 222
223 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
224 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
225 if (c->channelFlags & CHANNEL_PASSIVE)
226 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
227
228 band_2ghz->n_channels = ++a;
229
04bd4638 230 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 231 "channelFlags: 0x%x\n",
04bd4638 232 c->channel, c->channelFlags);
ff37e337
S		 233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 237 c->chan = &chan_5ghz[a];
ff37e337
S		 238
239 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
240 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
243
244 band_5ghz->n_channels = ++b;
245
04bd4638 246 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 247 "channelFlags: 0x%x\n",
04bd4638 248 c->channel, c->channelFlags);
ff37e337
S		 249 }
250 }
251
252 return 0;
253}
254
255/*
256 * Set/change channels. If the channel is really being changed, it's done
257 * by reseting the chip. To accomplish this we must first cleanup any pending
258 * DMA, then restart stuff.
259*/
260static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
261{
262 struct ath_hal *ah = sc->sc_ah;
263 bool fastcc = true, stopped;
030bb495 264 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 265 struct ieee80211_channel *channel = hw->conf.channel;
266 int r;
ff37e337
S		 267
268 if (sc->sc_flags & SC_OP_INVALID)
269 return -EIO;
270
c0d7c7af
LR		 271 /*
272 * This is only performed if the channel settings have
273 * actually changed.
274 *
275 * To switch channels clear any pending DMA operations;
276 * wait long enough for the RX fifo to drain, reset the
277 * hardware at the new frequency, and then re-enable
278 * the relevant bits of the h/w.
279 */
280 ath9k_hw_set_interrupts(ah, 0);
281 ath_draintxq(sc, false);
282 stopped = ath_stoprecv(sc);
ff37e337 283
c0d7c7af
LR		 284 /* XXX: do not flush receive queue here. We don't want
285 * to flush data frames already in queue because of
286 * changing channel. */
ff37e337 287
c0d7c7af
LR		 288 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
289 fastcc = false;
290
291 DPRINTF(sc, ATH_DBG_CONFIG,
292 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
293 sc->sc_ah->ah_curchan->channel,
294 channel->center_freq, sc->tx_chan_width);
ff37e337 295
c0d7c7af
LR		 296 spin_lock_bh(&sc->sc_resetlock);
297
298 r = ath9k_hw_reset(ah, hchan, fastcc);
299 if (r) {
300 DPRINTF(sc, ATH_DBG_FATAL,
301 "Unable to reset channel (%u Mhz) "
302 "reset status %u\n",
303 channel->center_freq, r);
304 spin_unlock_bh(&sc->sc_resetlock);
305 return r;
ff37e337 306 }
c0d7c7af
LR		 307 spin_unlock_bh(&sc->sc_resetlock);
308
309 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
310 sc->sc_flags &= ~SC_OP_FULL_RESET;
311
312 if (ath_startrecv(sc) != 0) {
313 DPRINTF(sc, ATH_DBG_FATAL,
314 "Unable to restart recv logic\n");
315 return -EIO;
316 }
317
318 ath_cache_conf_rate(sc, &hw->conf);
319 ath_update_txpow(sc);
320 ath9k_hw_set_interrupts(ah, sc->sc_imask);
ff37e337
S		 321 return 0;
322}
323
324/*
325 * This routine performs the periodic noise floor calibration function
326 * that is used to adjust and optimize the chip performance. This
327 * takes environmental changes (location, temperature) into account.
328 * When the task is complete, it reschedules itself depending on the
329 * appropriate interval that was calculated.
330 */
331static void ath_ani_calibrate(unsigned long data)
332{
333 struct ath_softc *sc;
334 struct ath_hal *ah;
335 bool longcal = false;
336 bool shortcal = false;
337 bool aniflag = false;
338 unsigned int timestamp = jiffies_to_msecs(jiffies);
339 u32 cal_interval;
340
341 sc = (struct ath_softc *)data;
342 ah = sc->sc_ah;
343
344 /*
345 * don't calibrate when we're scanning.
346 * we are most likely not on our home channel.
347 */
b77f483f 348 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 349 return;
350
351 /* Long calibration runs independently of short calibration. */
352 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
353 longcal = true;
04bd4638 354 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 355 sc->sc_ani.sc_longcal_timer = timestamp;
356 }
357
358 /* Short calibration applies only while sc_caldone is false */
359 if (!sc->sc_ani.sc_caldone) {
360 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
361 ATH_SHORT_CALINTERVAL) {
362 shortcal = true;
04bd4638 363 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 364 sc->sc_ani.sc_shortcal_timer = timestamp;
365 sc->sc_ani.sc_resetcal_timer = timestamp;
366 }
367 } else {
368 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
369 ATH_RESTART_CALINTERVAL) {
c9e27d94 370 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 371 if (sc->sc_ani.sc_caldone)
372 sc->sc_ani.sc_resetcal_timer = timestamp;
373 }
374 }
375
376 /* Verify whether we must check ANI */
377 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
378 ATH_ANI_POLLINTERVAL) {
379 aniflag = true;
380 sc->sc_ani.sc_checkani_timer = timestamp;
381 }
382
383 /* Skip all processing if there's nothing to do. */
384 if (longcal || shortcal || aniflag) {
385 /* Call ANI routine if necessary */
386 if (aniflag)
387 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
388 ah->ah_curchan);
389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
392 bool iscaldone = false;
393
394 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
395 sc->sc_rx_chainmask, longcal,
396 &iscaldone)) {
397 if (longcal)
398 sc->sc_ani.sc_noise_floor =
399 ath9k_hw_getchan_noise(ah,
400 ah->ah_curchan);
401
402 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 403 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 404 ah->ah_curchan->channel,
405 ah->ah_curchan->channelFlags,
406 sc->sc_ani.sc_noise_floor);
407 } else {
408 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 409 "calibrate chan %u/%x failed\n",
ff37e337
S		 410 ah->ah_curchan->channel,
411 ah->ah_curchan->channelFlags);
412 }
413 sc->sc_ani.sc_caldone = iscaldone;
414 }
415 }
416
417 /*
418 * Set timer interval based on previous results.
419 * The interval must be the shortest necessary to satisfy ANI,
420 * short calibration and long calibration.
421 */
aac9207e
S		 422 cal_interval = ATH_LONG_CALINTERVAL;
423 if (sc->sc_ah->ah_config.enable_ani)
424 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 425 if (!sc->sc_ani.sc_caldone)
426 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
427
428 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
429}
430
431/*
432 * Update tx/rx chainmask. For legacy association,
433 * hard code chainmask to 1x1, for 11n association, use
434 * the chainmask configuration.
435 */
436static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
437{
438 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
439 if (is_ht) {
440 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
441 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
442 } else {
443 sc->sc_tx_chainmask = 1;
444 sc->sc_rx_chainmask = 1;
445 }
446
04bd4638
S		 447 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
448 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 449}
450
451static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
452{
453 struct ath_node *an;
454
455 an = (struct ath_node *)sta->drv_priv;
456
457 if (sc->sc_flags & SC_OP_TXAGGR)
458 ath_tx_node_init(sc, an);
459
460 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
461 sta->ht_cap.ampdu_factor);
462 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
463}
464
465static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
466{
467 struct ath_node *an = (struct ath_node *)sta->drv_priv;
468
469 if (sc->sc_flags & SC_OP_TXAGGR)
470 ath_tx_node_cleanup(sc, an);
471}
472
473static void ath9k_tasklet(unsigned long data)
474{
475 struct ath_softc *sc = (struct ath_softc *)data;
476 u32 status = sc->sc_intrstatus;
477
478 if (status & ATH9K_INT_FATAL) {
479 /* need a chip reset */
480 ath_reset(sc, false);
481 return;
482 } else {
483
484 if (status &
485 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 486 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 487 ath_rx_tasklet(sc, 0);
b77f483f 488 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 489 }
490 /* XXX: optimize this */
491 if (status & ATH9K_INT_TX)
492 ath_tx_tasklet(sc);
493 }
494
495 /* re-enable hardware interrupt */
496 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
497}
498
499static irqreturn_t ath_isr(int irq, void *dev)
500{
501 struct ath_softc *sc = dev;
502 struct ath_hal *ah = sc->sc_ah;
503 enum ath9k_int status;
504 bool sched = false;
505
506 do {
507 if (sc->sc_flags & SC_OP_INVALID) {
508 /*
509 * The hardware is not ready/present, don't
510 * touch anything. Note this can happen early
511 * on if the IRQ is shared.
512 */
513 return IRQ_NONE;
514 }
515 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
516 return IRQ_NONE;
517 }
518
519 /*
520 * Figure out the reason(s) for the interrupt. Note
521 * that the hal returns a pseudo-ISR that may include
522 * bits we haven't explicitly enabled so we mask the
523 * value to insure we only process bits we requested.
524 */
525 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
526
527 status &= sc->sc_imask; /* discard unasked-for bits */
528
529 /*
530 * If there are no status bits set, then this interrupt was not
531 * for me (should have been caught above).
532 */
533 if (!status)
534 return IRQ_NONE;
535
536 sc->sc_intrstatus = status;
537
538 if (status & ATH9K_INT_FATAL) {
539 /* need a chip reset */
540 sched = true;
541 } else if (status & ATH9K_INT_RXORN) {
542 /* need a chip reset */
543 sched = true;
544 } else {
545 if (status & ATH9K_INT_SWBA) {
546 /* schedule a tasklet for beacon handling */
547 tasklet_schedule(&sc->bcon_tasklet);
548 }
549 if (status & ATH9K_INT_RXEOL) {
550 /*
551 * NB: the hardware should re-read the link when
552 * RXE bit is written, but it doesn't work
553 * at least on older hardware revs.
554 */
555 sched = true;
556 }
557
558 if (status & ATH9K_INT_TXURN)
559 /* bump tx trigger level */
560 ath9k_hw_updatetxtriglevel(ah, true);
561 /* XXX: optimize this */
562 if (status & ATH9K_INT_RX)
563 sched = true;
564 if (status & ATH9K_INT_TX)
565 sched = true;
566 if (status & ATH9K_INT_BMISS)
567 sched = true;
568 /* carrier sense timeout */
569 if (status & ATH9K_INT_CST)
570 sched = true;
571 if (status & ATH9K_INT_MIB) {
572 /*
573 * Disable interrupts until we service the MIB
574 * interrupt; otherwise it will continue to
575 * fire.
576 */
577 ath9k_hw_set_interrupts(ah, 0);
578 /*
579 * Let the hal handle the event. We assume
580 * it will clear whatever condition caused
581 * the interrupt.
582 */
583 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
584 ath9k_hw_set_interrupts(ah, sc->sc_imask);
585 }
586 if (status & ATH9K_INT_TIM_TIMER) {
587 if (!(ah->ah_caps.hw_caps &
588 ATH9K_HW_CAP_AUTOSLEEP)) {
589 /* Clear RxAbort bit so that we can
590 * receive frames */
591 ath9k_hw_setrxabort(ah, 0);
592 sched = true;
593 }
594 }
595 }
596 } while (0);
597
817e11de
S		 598 ath_debug_stat_interrupt(sc, status);
599
ff37e337
S		 600 if (sched) {
601 /* turn off every interrupt except SWBA */
602 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
603 tasklet_schedule(&sc->intr_tq);
604 }
605
606 return IRQ_HANDLED;
607}
608
f078f209
LR		 609static int ath_get_channel(struct ath_softc *sc,
610 struct ieee80211_channel *chan)
611{
612 int i;
613
614 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
615 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
616 return i;
617 }
618
619 return -1;
620}
621
622static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 623 struct ieee80211_channel *chan,
094d05dc 624 enum nl80211_channel_type channel_type)
f078f209
LR		 625{
626 u32 chanmode = 0;
f078f209
LR		 627
628 switch (chan->band) {
629 case IEEE80211_BAND_2GHZ:
094d05dc
S		 630 switch(channel_type) {
631 case NL80211_CHAN_NO_HT:
632 case NL80211_CHAN_HT20:
f078f209 633 chanmode = CHANNEL_G_HT20;
094d05dc
S		 634 break;
635 case NL80211_CHAN_HT40PLUS:
f078f209 636 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 637 break;
638 case NL80211_CHAN_HT40MINUS:
f078f209 639 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 640 break;
641 }
f078f209
LR		 642 break;
643 case IEEE80211_BAND_5GHZ:
094d05dc
S		 644 switch(channel_type) {
645 case NL80211_CHAN_NO_HT:
646 case NL80211_CHAN_HT20:
f078f209 647 chanmode = CHANNEL_A_HT20;
094d05dc
S		 648 break;
649 case NL80211_CHAN_HT40PLUS:
f078f209 650 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 651 break;
652 case NL80211_CHAN_HT40MINUS:
f078f209 653 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 654 break;
655 }
f078f209
LR		 656 break;
657 default:
658 break;
659 }
660
661 return chanmode;
662}
663
ff37e337
S		 664static int ath_keyset(struct ath_softc *sc, u16 keyix,
665 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
666{
667 bool status;
668
669 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
670 keyix, hk, mac, false);
671
672 return status != false;
673}
f078f209 674
6ace2891 675static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 676 struct ath9k_keyval *hk,
677 const u8 *addr)
678{
6ace2891
JM		 679 const u8 *key_rxmic;
680 const u8 *key_txmic;
f078f209 681
6ace2891
JM		 682 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
683 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 684
685 if (addr == NULL) {
686 /* Group key installation */
6ace2891
JM		 687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 689 }
690 if (!sc->sc_splitmic) {
691 /*
692 * data key goes at first index,
693 * the hal handles the MIC keys at index+64.
694 */
695 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
696 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 697 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 698 }
699 /*
700 * TX key goes at first index, RX key at +32.
701 * The hal handles the MIC keys at index+64.
702 */
703 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 704 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 705 /* Txmic entry failed. No need to proceed further */
706 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 707 "Setting TX MIC Key Failed\n");
f078f209
LR		 708 return 0;
709 }
710
711 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
712 /* XXX delete tx key on failure? */
6ace2891
JM		 713 return ath_keyset(sc, keyix + 32, hk, addr);
714}
715
716static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
717{
718 int i;
719
720 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
721 if (test_bit(i, sc->sc_keymap) ||
722 test_bit(i + 64, sc->sc_keymap))
723 continue; /* At least one part of TKIP key allocated */
724 if (sc->sc_splitmic &&
725 (test_bit(i + 32, sc->sc_keymap) ||
726 test_bit(i + 64 + 32, sc->sc_keymap)))
727 continue; /* At least one part of TKIP key allocated */
728
729 /* Found a free slot for a TKIP key */
730 return i;
731 }
732 return -1;
733}
734
735static int ath_reserve_key_cache_slot(struct ath_softc *sc)
736{
737 int i;
738
739 /* First, try to find slots that would not be available for TKIP. */
740 if (sc->sc_splitmic) {
741 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
742 if (!test_bit(i, sc->sc_keymap) &&
743 (test_bit(i + 32, sc->sc_keymap) ||
744 test_bit(i + 64, sc->sc_keymap) ||
745 test_bit(i + 64 + 32, sc->sc_keymap)))
746 return i;
747 if (!test_bit(i + 32, sc->sc_keymap) &&
748 (test_bit(i, sc->sc_keymap) ||
749 test_bit(i + 64, sc->sc_keymap) ||
750 test_bit(i + 64 + 32, sc->sc_keymap)))
751 return i + 32;
752 if (!test_bit(i + 64, sc->sc_keymap) &&
753 (test_bit(i , sc->sc_keymap) ||
754 test_bit(i + 32, sc->sc_keymap) ||
755 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 756 return i + 64;
6ace2891
JM		 757 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
758 (test_bit(i, sc->sc_keymap) ||
759 test_bit(i + 32, sc->sc_keymap) ||
760 test_bit(i + 64, sc->sc_keymap)))
ea612132 761 return i + 64 + 32;
6ace2891
JM		 762 }
763 } else {
764 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
765 if (!test_bit(i, sc->sc_keymap) &&
766 test_bit(i + 64, sc->sc_keymap))
767 return i;
768 if (test_bit(i, sc->sc_keymap) &&
769 !test_bit(i + 64, sc->sc_keymap))
770 return i + 64;
771 }
772 }
773
774 /* No partially used TKIP slots, pick any available slot */
775 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 776 /* Do not allow slots that could be needed for TKIP group keys
777 * to be used. This limitation could be removed if we know that
778 * TKIP will not be used. */
779 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
780 continue;
781 if (sc->sc_splitmic) {
782 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
783 continue;
784 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
785 continue;
786 }
787
6ace2891
JM		 788 if (!test_bit(i, sc->sc_keymap))
789 return i; /* Found a free slot for a key */
790 }
791
792 /* No free slot found */
793 return -1;
f078f209
LR		 794}
795
796static int ath_key_config(struct ath_softc *sc,
dc822b5d 797 struct ieee80211_sta *sta,
f078f209
LR		 798 struct ieee80211_key_conf *key)
799{
f078f209
LR		 800 struct ath9k_keyval hk;
801 const u8 *mac = NULL;
802 int ret = 0;
6ace2891 803 int idx;
f078f209
LR		 804
805 memset(&hk, 0, sizeof(hk));
806
807 switch (key->alg) {
808 case ALG_WEP:
809 hk.kv_type = ATH9K_CIPHER_WEP;
810 break;
811 case ALG_TKIP:
812 hk.kv_type = ATH9K_CIPHER_TKIP;
813 break;
814 case ALG_CCMP:
815 hk.kv_type = ATH9K_CIPHER_AES_CCM;
816 break;
817 default:
818 return -EINVAL;
819 }
820
6ace2891 821 hk.kv_len = key->keylen;
f078f209
LR		 822 memcpy(hk.kv_val, key->key, key->keylen);
823
6ace2891
JM		 824 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
825 /* For now, use the default keys for broadcast keys. This may
826 * need to change with virtual interfaces. */
827 idx = key->keyidx;
828 } else if (key->keyidx) {
829 struct ieee80211_vif *vif;
f078f209 830
dc822b5d
JB		 831 if (WARN_ON(!sta))
832 return -EOPNOTSUPP;
833 mac = sta->addr;
834
6ace2891
JM		 835 vif = sc->sc_vaps[0];
836 if (vif->type != NL80211_IFTYPE_AP) {
837 /* Only keyidx 0 should be used with unicast key, but
838 * allow this for client mode for now. */
839 idx = key->keyidx;
840 } else
841 return -EIO;
f078f209 842 } else {
dc822b5d
JB		 843 if (WARN_ON(!sta))
844 return -EOPNOTSUPP;
845 mac = sta->addr;
846
6ace2891
JM		 847 if (key->alg == ALG_TKIP)
848 idx = ath_reserve_key_cache_slot_tkip(sc);
849 else
850 idx = ath_reserve_key_cache_slot(sc);
851 if (idx < 0)
852 return -EIO; /* no free key cache entries */
f078f209
LR		 853 }
854
855 if (key->alg == ALG_TKIP)
6ace2891 856 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 857 else
6ace2891 858 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 859
860 if (!ret)
861 return -EIO;
862
6ace2891
JM		 863 set_bit(idx, sc->sc_keymap);
864 if (key->alg == ALG_TKIP) {
865 set_bit(idx + 64, sc->sc_keymap);
866 if (sc->sc_splitmic) {
867 set_bit(idx + 32, sc->sc_keymap);
868 set_bit(idx + 64 + 32, sc->sc_keymap);
869 }
870 }
871
872 return idx;
f078f209
LR		 873}
874
875static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
876{
6ace2891
JM		 877 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
878 if (key->hw_key_idx < IEEE80211_WEP_NKID)
879 return;
880
881 clear_bit(key->hw_key_idx, sc->sc_keymap);
882 if (key->alg != ALG_TKIP)
883 return;
f078f209 884
6ace2891
JM		 885 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
886 if (sc->sc_splitmic) {
887 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
888 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
889 }
f078f209
LR		 890}
891
d9fe60de 892static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 893{
60653678
S		 894#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
895#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 896
d9fe60de
JB		 897 ht_info->ht_supported = true;
898 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
899 IEEE80211_HT_CAP_SM_PS |
900 IEEE80211_HT_CAP_SGI_40 |
901 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 902
60653678
S		 903 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
904 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 905 /* set up supported mcs set */
906 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
907 ht_info->mcs.rx_mask[0] = 0xff;
908 ht_info->mcs.rx_mask[1] = 0xff;
909 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 910}
911
8feceb67 912static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 913 struct ieee80211_vif *vif,
8feceb67 914 struct ieee80211_bss_conf *bss_conf)
f078f209 915{
5640b08e 916 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 917
8feceb67 918 if (bss_conf->assoc) {
094d05dc
S		 919 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
920 bss_conf->aid, sc->sc_curbssid);
f078f209 921
8feceb67 922 /* New association, store aid */
d97809db 923 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 924 sc->sc_curaid = bss_conf->aid;
925 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
926 sc->sc_curaid);
927 }
f078f209 928
8feceb67
VT		 929 /* Configure the beacon */
930 ath_beacon_config(sc, 0);
931 sc->sc_flags |= SC_OP_BEACONS;
f078f209 932
8feceb67
VT		 933 /* Reset rssi stats */
934 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
935 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
936 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
937 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 938
6f255425
LR		 939 /* Start ANI */
940 mod_timer(&sc->sc_ani.timer,
941 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
942
8feceb67 943 } else {
04bd4638 944 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 945 sc->sc_curaid = 0;
f078f209 946 }
8feceb67 947}
f078f209 948
8feceb67
VT		 949/********************************/
950/* LED functions */
951/********************************/
f078f209 952
8feceb67
VT		 953static void ath_led_brightness(struct led_classdev *led_cdev,
954 enum led_brightness brightness)
955{
956 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
957 struct ath_softc *sc = led->sc;
f078f209 958
8feceb67
VT		 959 switch (brightness) {
960 case LED_OFF:
961 if (led->led_type == ATH_LED_ASSOC ||
962 led->led_type == ATH_LED_RADIO)
963 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
964 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
965 (led->led_type == ATH_LED_RADIO) ? 1 :
966 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
967 break;
968 case LED_FULL:
969 if (led->led_type == ATH_LED_ASSOC)
970 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
972 break;
973 default:
974 break;
f078f209 975 }
8feceb67 976}
f078f209 977
8feceb67
VT		 978static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
979 char *trigger)
980{
981 int ret;
f078f209 982
8feceb67
VT		 983 led->sc = sc;
984 led->led_cdev.name = led->name;
985 led->led_cdev.default_trigger = trigger;
986 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 987
8feceb67
VT		 988 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
989 if (ret)
990 DPRINTF(sc, ATH_DBG_FATAL,
991 "Failed to register led:%s", led->name);
992 else
993 led->registered = 1;
994 return ret;
995}
f078f209 996
8feceb67
VT		 997static void ath_unregister_led(struct ath_led *led)
998{
999 if (led->registered) {
1000 led_classdev_unregister(&led->led_cdev);
1001 led->registered = 0;
f078f209 1002 }
f078f209
LR		 1003}
1004
8feceb67 1005static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1006{
8feceb67
VT		 1007 ath_unregister_led(&sc->assoc_led);
1008 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1009 ath_unregister_led(&sc->tx_led);
1010 ath_unregister_led(&sc->rx_led);
1011 ath_unregister_led(&sc->radio_led);
1012 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1013}
f078f209 1014
8feceb67
VT		 1015static void ath_init_leds(struct ath_softc *sc)
1016{
1017 char *trigger;
1018 int ret;
f078f209 1019
8feceb67
VT		 1020 /* Configure gpio 1 for output */
1021 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1022 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1023 /* LED off, active low */
1024 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1025
8feceb67
VT		 1026 trigger = ieee80211_get_radio_led_name(sc->hw);
1027 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1028 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1029 ret = ath_register_led(sc, &sc->radio_led, trigger);
1030 sc->radio_led.led_type = ATH_LED_RADIO;
1031 if (ret)
1032 goto fail;
7dcfdcd9 1033
8feceb67
VT		 1034 trigger = ieee80211_get_assoc_led_name(sc->hw);
1035 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1036 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1037 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1038 sc->assoc_led.led_type = ATH_LED_ASSOC;
1039 if (ret)
1040 goto fail;
f078f209 1041
8feceb67
VT		 1042 trigger = ieee80211_get_tx_led_name(sc->hw);
1043 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1044 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1045 ret = ath_register_led(sc, &sc->tx_led, trigger);
1046 sc->tx_led.led_type = ATH_LED_TX;
1047 if (ret)
1048 goto fail;
f078f209 1049
8feceb67
VT		 1050 trigger = ieee80211_get_rx_led_name(sc->hw);
1051 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1052 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1053 ret = ath_register_led(sc, &sc->rx_led, trigger);
1054 sc->rx_led.led_type = ATH_LED_RX;
1055 if (ret)
1056 goto fail;
f078f209 1057
8feceb67
VT		 1058 return;
1059
1060fail:
1061 ath_deinit_leds(sc);
f078f209
LR		 1062}
1063
e97275cb 1064#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1065
500c064d
VT		 1066/*******************/
1067/* Rfkill */
1068/*******************/
1069
1070static void ath_radio_enable(struct ath_softc *sc)
1071{
1072 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1073 struct ieee80211_channel *channel = sc->hw->conf.channel;
1074 int r;
500c064d
VT		 1075
1076 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1077
1078 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1079
1080 if (r) {
500c064d 1081 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1082 "Unable to reset channel %u (%uMhz) ",
1083 "reset status %u\n",
1084 channel->center_freq, r);
500c064d
VT		 1085 }
1086 spin_unlock_bh(&sc->sc_resetlock);
1087
1088 ath_update_txpow(sc);
1089 if (ath_startrecv(sc) != 0) {
1090 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1091 "Unable to restart recv logic\n");
500c064d
VT		 1092 return;
1093 }
1094
1095 if (sc->sc_flags & SC_OP_BEACONS)
1096 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1097
1098 /* Re-Enable interrupts */
1099 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1100
1101 /* Enable LED */
1102 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1103 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1104 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1105
1106 ieee80211_wake_queues(sc->hw);
1107}
1108
1109static void ath_radio_disable(struct ath_softc *sc)
1110{
1111 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1112 struct ieee80211_channel *channel = sc->hw->conf.channel;
1113 int r;
500c064d
VT		 1114
1115 ieee80211_stop_queues(sc->hw);
1116
1117 /* Disable LED */
1118 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1119 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1120
1121 /* Disable interrupts */
1122 ath9k_hw_set_interrupts(ah, 0);
1123
1124 ath_draintxq(sc, false); /* clear pending tx frames */
1125 ath_stoprecv(sc); /* turn off frame recv */
1126 ath_flushrecv(sc); /* flush recv queue */
1127
1128 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1129 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1130 if (r) {
500c064d 1131 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1132 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1133 "reset status %u\n",
1134 channel->center_freq, r);
500c064d
VT		 1135 }
1136 spin_unlock_bh(&sc->sc_resetlock);
1137
1138 ath9k_hw_phy_disable(ah);
1139 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1140}
1141
1142static bool ath_is_rfkill_set(struct ath_softc *sc)
1143{
1144 struct ath_hal *ah = sc->sc_ah;
1145
1146 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1147 ah->ah_rfkill_polarity;
1148}
1149
1150/* h/w rfkill poll function */
1151static void ath_rfkill_poll(struct work_struct *work)
1152{
1153 struct ath_softc *sc = container_of(work, struct ath_softc,
1154 rf_kill.rfkill_poll.work);
1155 bool radio_on;
1156
1157 if (sc->sc_flags & SC_OP_INVALID)
1158 return;
1159
1160 radio_on = !ath_is_rfkill_set(sc);
1161
1162 /*
1163 * enable/disable radio only when there is a
1164 * state change in RF switch
1165 */
1166 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1167 enum rfkill_state state;
1168
1169 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1170 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1171 : RFKILL_STATE_HARD_BLOCKED;
1172 } else if (radio_on) {
1173 ath_radio_enable(sc);
1174 state = RFKILL_STATE_UNBLOCKED;
1175 } else {
1176 ath_radio_disable(sc);
1177 state = RFKILL_STATE_HARD_BLOCKED;
1178 }
1179
1180 if (state == RFKILL_STATE_HARD_BLOCKED)
1181 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1182 else
1183 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1184
1185 rfkill_force_state(sc->rf_kill.rfkill, state);
1186 }
1187
1188 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1189 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1190}
1191
1192/* s/w rfkill handler */
1193static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1194{
1195 struct ath_softc *sc = data;
1196
1197 switch (state) {
1198 case RFKILL_STATE_SOFT_BLOCKED:
1199 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1200 SC_OP_RFKILL_SW_BLOCKED)))
1201 ath_radio_disable(sc);
1202 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1203 return 0;
1204 case RFKILL_STATE_UNBLOCKED:
1205 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1206 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1207 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1208 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1209 "radio as it is disabled by h/w\n");
500c064d
VT		 1210 return -EPERM;
1211 }
1212 ath_radio_enable(sc);
1213 }
1214 return 0;
1215 default:
1216 return -EINVAL;
1217 }
1218}
1219
1220/* Init s/w rfkill */
1221static int ath_init_sw_rfkill(struct ath_softc *sc)
1222{
1223 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1224 RFKILL_TYPE_WLAN);
1225 if (!sc->rf_kill.rfkill) {
1226 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1227 return -ENOMEM;
1228 }
1229
1230 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1231 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1232 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1233 sc->rf_kill.rfkill->data = sc;
1234 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1235 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1236 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1237
1238 return 0;
1239}
1240
1241/* Deinitialize rfkill */
1242static void ath_deinit_rfkill(struct ath_softc *sc)
1243{
1244 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1245 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1246
1247 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1248 rfkill_unregister(sc->rf_kill.rfkill);
1249 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1250 sc->rf_kill.rfkill = NULL;
1251 }
1252}
9c84b797
S		 1253
1254static int ath_start_rfkill_poll(struct ath_softc *sc)
1255{
1256 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1257 queue_delayed_work(sc->hw->workqueue,
1258 &sc->rf_kill.rfkill_poll, 0);
1259
1260 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1261 if (rfkill_register(sc->rf_kill.rfkill)) {
1262 DPRINTF(sc, ATH_DBG_FATAL,
1263 "Unable to register rfkill\n");
1264 rfkill_free(sc->rf_kill.rfkill);
1265
1266 /* Deinitialize the device */
306efdd1 1267 ath_detach(sc);
9c84b797
S		 1268 if (sc->pdev->irq)
1269 free_irq(sc->pdev->irq, sc);
9c84b797
S		 1270 pci_iounmap(sc->pdev, sc->mem);
1271 pci_release_region(sc->pdev, 0);
1272 pci_disable_device(sc->pdev);
9757d556 1273 ieee80211_free_hw(sc->hw);
9c84b797
S		 1274 return -EIO;
1275 } else {
1276 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1277 }
1278 }
1279
1280 return 0;
1281}
500c064d
VT		 1282#endif /* CONFIG_RFKILL */
1283
9c84b797 1284static void ath_detach(struct ath_softc *sc)
f078f209 1285{
8feceb67 1286 struct ieee80211_hw *hw = sc->hw;
9c84b797 1287 int i = 0;
f078f209 1288
04bd4638 1289 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1290
e97275cb 1291#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1292 ath_deinit_rfkill(sc);
1293#endif
3fcdfb4b
VT		 1294 ath_deinit_leds(sc);
1295
1296 ieee80211_unregister_hw(hw);
8feceb67
VT		 1297 ath_rx_cleanup(sc);
1298 ath_tx_cleanup(sc);
f078f209 1299
9c84b797
S		 1300 tasklet_kill(&sc->intr_tq);
1301 tasklet_kill(&sc->bcon_tasklet);
f078f209 1302
9c84b797
S		 1303 if (!(sc->sc_flags & SC_OP_INVALID))
1304 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1305
9c84b797
S		 1306 /* cleanup tx queues */
1307 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1308 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1309 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1310
1311 ath9k_hw_detach(sc->sc_ah);
826d2680 1312 ath9k_exit_debug(sc);
f078f209
LR		 1313}
1314
ff37e337
S		 1315static int ath_init(u16 devid, struct ath_softc *sc)
1316{
1317 struct ath_hal *ah = NULL;
1318 int status;
1319 int error = 0, i;
1320 int csz = 0;
1321
1322 /* XXX: hardware will not be ready until ath_open() being called */
1323 sc->sc_flags |= SC_OP_INVALID;
88b126af 1324
826d2680
S		 1325 if (ath9k_init_debug(sc) < 0)
1326 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1327
1328 spin_lock_init(&sc->sc_resetlock);
aa33de09 1329 mutex_init(&sc->mutex);
ff37e337
S		 1330 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1331 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1332 (unsigned long)sc);
1333
1334 /*
1335 * Cache line size is used to size and align various
1336 * structures used to communicate with the hardware.
1337 */
1338 bus_read_cachesize(sc, &csz);
1339 /* XXX assert csz is non-zero */
1340 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1341
1342 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1343 if (ah == NULL) {
1344 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1345 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1346 error = -ENXIO;
1347 goto bad;
1348 }
1349 sc->sc_ah = ah;
1350
1351 /* Get the hardware key cache size. */
1352 sc->sc_keymax = ah->ah_caps.keycache_size;
1353 if (sc->sc_keymax > ATH_KEYMAX) {
1354 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1355 "Warning, using only %u entries in %u key cache\n",
1356 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1357 sc->sc_keymax = ATH_KEYMAX;
1358 }
1359
1360 /*
1361 * Reset the key cache since some parts do not
1362 * reset the contents on initial power up.
1363 */
1364 for (i = 0; i < sc->sc_keymax; i++)
1365 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1366
1367 /* Collect the channel list using the default country code */
1368
1369 error = ath_setup_channels(sc);
1370 if (error)
1371 goto bad;
1372
1373 /* default to MONITOR mode */
d97809db
CM		 1374 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1375
ff37e337
S		 1376
1377 /* Setup rate tables */
1378
1379 ath_rate_attach(sc);
1380 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1381 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1382
1383 /*
1384 * Allocate hardware transmit queues: one queue for
1385 * beacon frames and one data queue for each QoS
1386 * priority. Note that the hal handles reseting
1387 * these queues at the needed time.
1388 */
b77f483f
S		 1389 sc->beacon.beaconq = ath_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) {
ff37e337 1391 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1392 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1393 error = -EIO;
1394 goto bad2;
1395 }
b77f483f
S		 1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) {
ff37e337 1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1405 ath_cabq_update(sc);
1406
b77f483f
S		 1407 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1408 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1409
1410 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1414 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1415 error = -EIO;
1416 goto bad2;
1417 }
1418
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1421 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1422 error = -EIO;
1423 goto bad2;
1424 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1427 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1428 error = -EIO;
1429 goto bad2;
1430 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1433 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1434 error = -EIO;
1435 goto bad2;
1436 }
1437
1438 /* Initializes the noise floor to a reasonable default value.
1439 * Later on this will be updated during ANI processing. */
1440
1441 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1442 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1443
1444 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_TKIP, NULL)) {
1446 /*
1447 * Whether we should enable h/w TKIP MIC.
1448 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1449 * report WMM capable, so it's always safe to turn on
1450 * TKIP MIC in this case.
1451 */
1452 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1453 0, 1, NULL);
1454 }
1455
1456 /*
1457 * Check whether the separate key cache entries
1458 * are required to handle both tx+rx MIC keys.
1459 * With split mic keys the number of stations is limited
1460 * to 27 otherwise 59.
1461 */
1462 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463 ATH9K_CIPHER_TKIP, NULL)
1464 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1465 ATH9K_CIPHER_MIC, NULL)
1466 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1467 0, NULL))
1468 sc->sc_splitmic = 1;
1469
1470 /* turn on mcast key search if possible */
1471 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1472 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1473 1, NULL);
1474
1475 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1476 sc->sc_config.txpowlimit_override = 0;
1477
1478 /* 11n Capabilities */
1479 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1480 sc->sc_flags |= SC_OP_TXAGGR;
1481 sc->sc_flags |= SC_OP_RXAGGR;
1482 }
1483
1484 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1485 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1486
1487 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1488 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1489
1490 ath9k_hw_getmac(ah, sc->sc_myaddr);
1491 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1492 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1493 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1494 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1495 }
1496
b77f483f 1497 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1498
1499 /* initialize beacon slots */
b77f483f
S		 1500 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1501 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1502
1503 /* save MISC configurations */
1504 sc->sc_config.swBeaconProcess = 1;
1505
ff37e337
S		 1506 /* setup channels and rates */
1507
1508 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1509 sc->channels[IEEE80211_BAND_2GHZ];
1510 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1511 sc->rates[IEEE80211_BAND_2GHZ];
1512 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1513
1514 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1515 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1516 sc->channels[IEEE80211_BAND_5GHZ];
1517 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1518 sc->rates[IEEE80211_BAND_5GHZ];
1519 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1520 }
1521
1522 return 0;
1523bad2:
1524 /* cleanup tx queues */
1525 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1526 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1527 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1528bad:
1529 if (ah)
1530 ath9k_hw_detach(ah);
1531
1532 return error;
1533}
1534
9c84b797 1535static int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1536{
8feceb67
VT		 1537 struct ieee80211_hw *hw = sc->hw;
1538 int error = 0;
f078f209 1539
04bd4638 1540 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1541
8feceb67
VT		 1542 error = ath_init(devid, sc);
1543 if (error != 0)
1544 return error;
f078f209 1545
8feceb67 1546 /* get mac address from hardware and set in mac80211 */
f078f209 1547
8feceb67 1548 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1549
9c84b797
S		 1550 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1551 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1552 IEEE80211_HW_SIGNAL_DBM |
1553 IEEE80211_HW_AMPDU_AGGREGATION;
f078f209 1554
9c84b797
S		 1555 hw->wiphy->interface_modes =
1556 BIT(NL80211_IFTYPE_AP) |
1557 BIT(NL80211_IFTYPE_STATION) |
1558 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1559
8feceb67 1560 hw->queues = 4;
e63835b0
S		 1561 hw->max_rates = 4;
1562 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1563 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1564 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1565
8feceb67 1566 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1567
9c84b797
S		 1568 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1569 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1570 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1571 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1572 }
1573
1574 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1575 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1576 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1577 &sc->sbands[IEEE80211_BAND_5GHZ];
1578
db93e7b5
SB		 1579 /* initialize tx/rx engine */
1580 error = ath_tx_init(sc, ATH_TXBUF);
1581 if (error != 0)
1582 goto detach;
8feceb67 1583
db93e7b5
SB		 1584 error = ath_rx_init(sc, ATH_RXBUF);
1585 if (error != 0)
1586 goto detach;
8feceb67 1587
e97275cb 1588#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1589 /* Initialze h/w Rfkill */
1590 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1591 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1592
1593 /* Initialize s/w rfkill */
1594 if (ath_init_sw_rfkill(sc))
1595 goto detach;
1596#endif
1597
db93e7b5 1598 error = ieee80211_register_hw(hw);
8feceb67 1599
db93e7b5
SB		 1600 /* Initialize LED control */
1601 ath_init_leds(sc);
8feceb67
VT		 1602
1603 return 0;
1604detach:
1605 ath_detach(sc);
8feceb67 1606 return error;
f078f209
LR		 1607}
1608
ff37e337
S		 1609int ath_reset(struct ath_softc *sc, bool retry_tx)
1610{
1611 struct ath_hal *ah = sc->sc_ah;
030bb495 1612 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1613 int r;
ff37e337
S		 1614
1615 ath9k_hw_set_interrupts(ah, 0);
1616 ath_draintxq(sc, retry_tx);
1617 ath_stoprecv(sc);
1618 ath_flushrecv(sc);
1619
1620 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1621 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1622 if (r)
ff37e337 1623 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1624 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1625 spin_unlock_bh(&sc->sc_resetlock);
1626
1627 if (ath_startrecv(sc) != 0)
04bd4638 1628 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1629
1630 /*
1631 * We may be doing a reset in response to a request
1632 * that changes the channel so update any state that
1633 * might change as a result.
1634 */
ce111bad 1635 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1636
1637 ath_update_txpow(sc);
1638
1639 if (sc->sc_flags & SC_OP_BEACONS)
1640 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1641
1642 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1643
1644 if (retry_tx) {
1645 int i;
1646 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1647 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1648 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1649 ath_txq_schedule(sc, &sc->tx.txq[i]);
1650 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1651 }
1652 }
1653 }
1654
ae8d2858 1655 return r;
ff37e337
S		 1656}
1657
1658/*
1659 * This function will allocate both the DMA descriptor structure, and the
1660 * buffers it contains. These are used to contain the descriptors used
1661 * by the system.
1662*/
1663int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1664 struct list_head *head, const char *name,
1665 int nbuf, int ndesc)
1666{
1667#define DS2PHYS(_dd, _ds) \
1668 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1669#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1670#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1671
1672 struct ath_desc *ds;
1673 struct ath_buf *bf;
1674 int i, bsize, error;
1675
04bd4638
S		 1676 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1677 name, nbuf, ndesc);
ff37e337
S		 1678
1679 /* ath_desc must be a multiple of DWORDs */
1680 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1681 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1682 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1683 error = -ENOMEM;
1684 goto fail;
1685 }
1686
1687 dd->dd_name = name;
1688 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1689
1690 /*
1691 * Need additional DMA memory because we can't use
1692 * descriptors that cross the 4K page boundary. Assume
1693 * one skipped descriptor per 4K page.
1694 */
1695 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1696 u32 ndesc_skipped =
1697 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1698 u32 dma_len;
1699
1700 while (ndesc_skipped) {
1701 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1702 dd->dd_desc_len += dma_len;
1703
1704 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1705 };
1706 }
1707
1708 /* allocate descriptors */
1709 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1710 dd->dd_desc_len,
1711 &dd->dd_desc_paddr);
1712 if (dd->dd_desc == NULL) {
1713 error = -ENOMEM;
1714 goto fail;
1715 }
1716 ds = dd->dd_desc;
04bd4638
S		 1717 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1718 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1719 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1720
1721 /* allocate buffers */
1722 bsize = sizeof(struct ath_buf) * nbuf;
1723 bf = kmalloc(bsize, GFP_KERNEL);
1724 if (bf == NULL) {
1725 error = -ENOMEM;
1726 goto fail2;
1727 }
1728 memset(bf, 0, bsize);
1729 dd->dd_bufptr = bf;
1730
1731 INIT_LIST_HEAD(head);
1732 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1733 bf->bf_desc = ds;
1734 bf->bf_daddr = DS2PHYS(dd, ds);
1735
1736 if (!(sc->sc_ah->ah_caps.hw_caps &
1737 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1738 /*
1739 * Skip descriptor addresses which can cause 4KB
1740 * boundary crossing (addr + length) with a 32 dword
1741 * descriptor fetch.
1742 */
1743 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1744 ASSERT((caddr_t) bf->bf_desc <
1745 ((caddr_t) dd->dd_desc +
1746 dd->dd_desc_len));
1747
1748 ds += ndesc;
1749 bf->bf_desc = ds;
1750 bf->bf_daddr = DS2PHYS(dd, ds);
1751 }
1752 }
1753 list_add_tail(&bf->list, head);
1754 }
1755 return 0;
1756fail2:
1757 pci_free_consistent(sc->pdev,
1758 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1759fail:
1760 memset(dd, 0, sizeof(*dd));
1761 return error;
1762#undef ATH_DESC_4KB_BOUND_CHECK
1763#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1764#undef DS2PHYS
1765}
1766
1767void ath_descdma_cleanup(struct ath_softc *sc,
1768 struct ath_descdma *dd,
1769 struct list_head *head)
1770{
1771 pci_free_consistent(sc->pdev,
1772 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1773
1774 INIT_LIST_HEAD(head);
1775 kfree(dd->dd_bufptr);
1776 memset(dd, 0, sizeof(*dd));
1777}
1778
1779int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1780{
1781 int qnum;
1782
1783 switch (queue) {
1784 case 0:
b77f483f 1785 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1786 break;
1787 case 1:
b77f483f 1788 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1789 break;
1790 case 2:
b77f483f 1791 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1792 break;
1793 case 3:
b77f483f 1794 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1795 break;
1796 default:
b77f483f 1797 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1798 break;
1799 }
1800
1801 return qnum;
1802}
1803
1804int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1805{
1806 int qnum;
1807
1808 switch (queue) {
1809 case ATH9K_WME_AC_VO:
1810 qnum = 0;
1811 break;
1812 case ATH9K_WME_AC_VI:
1813 qnum = 1;
1814 break;
1815 case ATH9K_WME_AC_BE:
1816 qnum = 2;
1817 break;
1818 case ATH9K_WME_AC_BK:
1819 qnum = 3;
1820 break;
1821 default:
1822 qnum = -1;
1823 break;
1824 }
1825
1826 return qnum;
1827}
1828
1829/**********************/
1830/* mac80211 callbacks */
1831/**********************/
1832
8feceb67 1833static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1834{
1835 struct ath_softc *sc = hw->priv;
8feceb67 1836 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1837 struct ath9k_channel *init_channel;
ae8d2858 1838 int r, pos;
f078f209 1839
04bd4638
S		 1840 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1841 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1842
8feceb67 1843 /* setup initial channel */
f078f209 1844
8feceb67
VT		 1845 pos = ath_get_channel(sc, curchan);
1846 if (pos == -1) {
04bd4638 1847 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1848 return -EINVAL;
f078f209
LR		 1849 }
1850
99405f93 1851 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1852 sc->sc_ah->ah_channels[pos].chanmode =
1853 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1854 init_channel = &sc->sc_ah->ah_channels[pos];
1855
1856 /* Reset SERDES registers */
1857 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1858
1859 /*
1860 * The basic interface to setting the hardware in a good
1861 * state is ``reset''. On return the hardware is known to
1862 * be powered up and with interrupts disabled. This must
1863 * be followed by initialization of the appropriate bits
1864 * and then setup of the interrupt mask.
1865 */
1866 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1867 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1868 if (r) {
ff37e337 1869 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1870 "Unable to reset hardware; reset status %u "
1871 "(freq %u MHz)\n", r,
1872 curchan->center_freq);
ff37e337 1873 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1874 return r;
ff37e337
S		 1875 }
1876 spin_unlock_bh(&sc->sc_resetlock);
1877
1878 /*
1879 * This is needed only to setup initial state
1880 * but it's best done after a reset.
1881 */
1882 ath_update_txpow(sc);
8feceb67 1883
ff37e337
S		 1884 /*
1885 * Setup the hardware after reset:
1886 * The receive engine is set going.
1887 * Frame transmit is handled entirely
1888 * in the frame output path; there's nothing to do
1889 * here except setup the interrupt mask.
1890 */
1891 if (ath_startrecv(sc) != 0) {
8feceb67 1892 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1893 "Unable to start recv logic\n");
ae8d2858 1894 return -EIO;
f078f209 1895 }
8feceb67 1896
ff37e337
S		 1897 /* Setup our intr mask. */
1898 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1899 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1900 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1901
1902 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1903 sc->sc_imask |= ATH9K_INT_GTT;
1904
1905 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1906 sc->sc_imask |= ATH9K_INT_CST;
1907
1908 /*
1909 * Enable MIB interrupts when there are hardware phy counters.
1910 * Note we only do this (at the moment) for station mode.
1911 */
1912 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1913 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1914 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1915 sc->sc_imask |= ATH9K_INT_MIB;
1916 /*
1917 * Some hardware processes the TIM IE and fires an
1918 * interrupt when the TIM bit is set. For hardware
1919 * that does, if not overridden by configuration,
1920 * enable the TIM interrupt when operating as station.
1921 */
1922 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1923 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1924 !sc->sc_config.swBeaconProcess)
1925 sc->sc_imask |= ATH9K_INT_TIM;
1926
ce111bad 1927 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1928
1929 sc->sc_flags &= ~SC_OP_INVALID;
1930
1931 /* Disable BMISS interrupt when we're not associated */
1932 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1933 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1934
1935 ieee80211_wake_queues(sc->hw);
1936
e97275cb 1937#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1938 r = ath_start_rfkill_poll(sc);
500c064d 1939#endif
ae8d2858 1940 return r;
f078f209
LR		 1941}
1942
8feceb67
VT		 1943static int ath9k_tx(struct ieee80211_hw *hw,
1944 struct sk_buff *skb)
f078f209 1945{
528f0c6b 1946 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1947 struct ath_softc *sc = hw->priv;
528f0c6b 1948 struct ath_tx_control txctl;
8feceb67 1949 int hdrlen, padsize;
528f0c6b
S		 1950
1951 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1952
8feceb67
VT		 1953 /*
1954 * As a temporary workaround, assign seq# here; this will likely need
1955 * to be cleaned up to work better with Beacon transmission and virtual
1956 * BSSes.
1957 */
1958 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1959 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1960 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1961 sc->tx.seq_no += 0x10;
8feceb67 1962 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1963 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1964 }
f078f209 1965
8feceb67
VT		 1966 /* Add the padding after the header if this is not already done */
1967 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1968 if (hdrlen & 3) {
1969 padsize = hdrlen % 4;
1970 if (skb_headroom(skb) < padsize)
1971 return -1;
1972 skb_push(skb, padsize);
1973 memmove(skb->data, skb->data + padsize, hdrlen);
1974 }
1975
528f0c6b
S		 1976 /* Check if a tx queue is available */
1977
1978 txctl.txq = ath_test_get_txq(sc, skb);
1979 if (!txctl.txq)
1980 goto exit;
1981
04bd4638 1982 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1983
528f0c6b 1984 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1985 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1986 goto exit;
8feceb67
VT		 1987 }
1988
528f0c6b
S		 1989 return 0;
1990exit:
1991 dev_kfree_skb_any(skb);
8feceb67 1992 return 0;
f078f209
LR		 1993}
1994
8feceb67 1995static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 1996{
1997 struct ath_softc *sc = hw->priv;
f078f209 1998
9c84b797 1999 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2000 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2001 return;
2002 }
8feceb67 2003
04bd4638 2004 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 2005
2006 ieee80211_stop_queues(sc->hw);
2007
2008 /* make sure h/w will not generate any interrupt
2009 * before setting the invalid flag. */
2010 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2011
2012 if (!(sc->sc_flags & SC_OP_INVALID)) {
2013 ath_draintxq(sc, false);
2014 ath_stoprecv(sc);
2015 ath9k_hw_phy_disable(sc->sc_ah);
2016 } else
b77f483f 2017 sc->rx.rxlink = NULL;
ff37e337
S		 2018
2019#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2020 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2021 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2022#endif
2023 /* disable HAL and put h/w to sleep */
2024 ath9k_hw_disable(sc->sc_ah);
2025 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2026
2027 sc->sc_flags |= SC_OP_INVALID;
500c064d 2028
04bd4638 2029 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2030}
2031
8feceb67
VT		 2032static int ath9k_add_interface(struct ieee80211_hw *hw,
2033 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2034{
2035 struct ath_softc *sc = hw->priv;
5640b08e 2036 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2037 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2038
8feceb67
VT		 2039 /* Support only vap for now */
2040
2041 if (sc->sc_nvaps)
2042 return -ENOBUFS;
2043
2044 switch (conf->type) {
05c914fe 2045 case NL80211_IFTYPE_STATION:
d97809db 2046 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2047 break;
05c914fe 2048 case NL80211_IFTYPE_ADHOC:
d97809db 2049 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2050 break;
05c914fe 2051 case NL80211_IFTYPE_AP:
d97809db 2052 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2053 break;
2054 default:
2055 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2056 "Interface type %d not yet supported\n", conf->type);
8feceb67 2057 return -EOPNOTSUPP;
f078f209
LR		 2058 }
2059
04bd4638 2060 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2061
5640b08e
S		 2062 /* Set the VAP opmode */
2063 avp->av_opmode = ic_opmode;
2064 avp->av_bslot = -1;
2065
d97809db 2066 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2067 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2068
2069 sc->sc_vaps[0] = conf->vif;
2070 sc->sc_nvaps++;
2071
2072 /* Set the device opmode */
2073 sc->sc_ah->ah_opmode = ic_opmode;
2074
6f255425
LR		 2075 if (conf->type == NL80211_IFTYPE_AP) {
2076 /* TODO: is this a suitable place to start ANI for AP mode? */
2077 /* Start ANI */
2078 mod_timer(&sc->sc_ani.timer,
2079 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2080 }
2081
8feceb67 2082 return 0;
f078f209
LR		 2083}
2084
8feceb67
VT		 2085static void ath9k_remove_interface(struct ieee80211_hw *hw,
2086 struct ieee80211_if_init_conf *conf)
f078f209 2087{
8feceb67 2088 struct ath_softc *sc = hw->priv;
5640b08e 2089 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2090
04bd4638 2091 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2092
6f255425
LR		 2093 /* Stop ANI */
2094 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2095
8feceb67 2096 /* Reclaim beacon resources */
d97809db
CM		 2097 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2098 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2099 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2100 ath_beacon_return(sc, avp);
580f0b8a 2101 }
f078f209 2102
8feceb67 2103 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2104
5640b08e
S		 2105 sc->sc_vaps[0] = NULL;
2106 sc->sc_nvaps--;
f078f209
LR		 2107}
2108
e8975581 2109static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2110{
8feceb67 2111 struct ath_softc *sc = hw->priv;
e8975581 2112 struct ieee80211_conf *conf = &hw->conf;
f078f209 2113
aa33de09 2114 mutex_lock(&sc->mutex);
094d05dc
S		 2115 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2116 IEEE80211_CONF_CHANGE_HT)) {
99405f93
S		 2117 struct ieee80211_channel *curchan = hw->conf.channel;
2118 int pos;
ae5eb026 2119
04bd4638
S		 2120 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2121 curchan->center_freq);
f078f209 2122
99405f93
S		 2123 pos = ath_get_channel(sc, curchan);
2124 if (pos == -1) {
04bd4638
S		 2125 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2126 curchan->center_freq);
aa33de09 2127 mutex_unlock(&sc->mutex);
99405f93
S		 2128 return -EINVAL;
2129 }
f078f209 2130
99405f93 2131 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2132 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2133 (curchan->band == IEEE80211_BAND_2GHZ) ?
2134 CHANNEL_G : CHANNEL_A;
2135
ecf70441
LR		 2136 if (conf_is_ht(conf)) {
2137 if (conf_is_ht40(conf))
094d05dc 2138 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2139
2140 sc->sc_ah->ah_channels[pos].chanmode =
2141 ath_get_extchanmode(sc, curchan,
094d05dc 2142 conf->ht.channel_type);
e11602b7
S		 2143 }
2144
ecf70441 2145 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2146
e11602b7 2147 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2148 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2149 mutex_unlock(&sc->mutex);
e11602b7
S		 2150 return -EINVAL;
2151 }
094d05dc 2152 }
f078f209 2153
5c020dc6
LR		 2154 if (changed & IEEE80211_CONF_CHANGE_POWER)
2155 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2156
aa33de09 2157 mutex_unlock(&sc->mutex);
f078f209
LR		 2158 return 0;
2159}
2160
8feceb67
VT		 2161static int ath9k_config_interface(struct ieee80211_hw *hw,
2162 struct ieee80211_vif *vif,
2163 struct ieee80211_if_conf *conf)
c83be688 2164{
8feceb67
VT		 2165 struct ath_softc *sc = hw->priv;
2166 struct ath_hal *ah = sc->sc_ah;
5640b08e 2167 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2168 u32 rfilt = 0;
2169 int error, i;
c83be688 2170
8feceb67
VT		 2171 /* TODO: Need to decide which hw opmode to use for multi-interface
2172 * cases */
05c914fe 2173 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2174 ah->ah_opmode != NL80211_IFTYPE_AP) {
2175 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2176 ath9k_hw_setopmode(ah);
2177 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2178 /* Request full reset to get hw opmode changed properly */
2179 sc->sc_flags |= SC_OP_FULL_RESET;
2180 }
c83be688 2181
8feceb67
VT		 2182 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2183 !is_zero_ether_addr(conf->bssid)) {
2184 switch (vif->type) {
05c914fe
JB		 2185 case NL80211_IFTYPE_STATION:
2186 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2187 /* Set BSSID */
2188 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2189 sc->sc_curaid = 0;
2190 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2191 sc->sc_curaid);
c83be688 2192
8feceb67
VT		 2193 /* Set aggregation protection mode parameters */
2194 sc->sc_config.ath_aggr_prot = 0;
c83be688 2195
8feceb67 2196 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2197 "RX filter 0x%x bssid %pM aid 0x%x\n",
2198 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2199
8feceb67
VT		 2200 /* need to reconfigure the beacon */
2201 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2202
8feceb67
VT		 2203 break;
2204 default:
2205 break;
2206 }
2207 }
c83be688 2208
8feceb67 2209 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2210 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2211 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2212 /*
2213 * Allocate and setup the beacon frame.
2214 *
2215 * Stop any previous beacon DMA. This may be
2216 * necessary, for example, when an ibss merge
2217 * causes reconfiguration; we may be called
2218 * with beacon transmission active.
2219 */
b77f483f 2220 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2221
8feceb67
VT		 2222 error = ath_beacon_alloc(sc, 0);
2223 if (error != 0)
2224 return error;
c83be688 2225
8feceb67
VT		 2226 ath_beacon_sync(sc, 0);
2227 }
c83be688 2228
8feceb67 2229 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2230 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2231 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2232 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2233 ath9k_hw_keysetmac(sc->sc_ah,
2234 (u16)i,
2235 sc->sc_curbssid);
2236 }
c83be688 2237
8feceb67 2238 /* Only legacy IBSS for now */
05c914fe 2239 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2240 ath_update_chainmask(sc, 0);
f078f209 2241
8feceb67
VT		 2242 return 0;
2243}
f078f209 2244
8feceb67
VT		 2245#define SUPPORTED_FILTERS \
2246 (FIF_PROMISC_IN_BSS | \
2247 FIF_ALLMULTI | \
2248 FIF_CONTROL | \
2249 FIF_OTHER_BSS | \
2250 FIF_BCN_PRBRESP_PROMISC | \
2251 FIF_FCSFAIL)
c83be688 2252
8feceb67
VT		 2253/* FIXME: sc->sc_full_reset ? */
2254static void ath9k_configure_filter(struct ieee80211_hw *hw,
2255 unsigned int changed_flags,
2256 unsigned int *total_flags,
2257 int mc_count,
2258 struct dev_mc_list *mclist)
2259{
2260 struct ath_softc *sc = hw->priv;
2261 u32 rfilt;
f078f209 2262
8feceb67
VT		 2263 changed_flags &= SUPPORTED_FILTERS;
2264 *total_flags &= SUPPORTED_FILTERS;
f078f209 2265
b77f483f 2266 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2267 rfilt = ath_calcrxfilter(sc);
2268 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2269
8feceb67
VT		 2270 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2271 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2272 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2273 }
f078f209 2274
b77f483f 2275 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2276}
f078f209 2277
8feceb67
VT		 2278static void ath9k_sta_notify(struct ieee80211_hw *hw,
2279 struct ieee80211_vif *vif,
2280 enum sta_notify_cmd cmd,
17741cdc 2281 struct ieee80211_sta *sta)
8feceb67
VT		 2282{
2283 struct ath_softc *sc = hw->priv;
f078f209 2284
8feceb67
VT		 2285 switch (cmd) {
2286 case STA_NOTIFY_ADD:
5640b08e 2287 ath_node_attach(sc, sta);
8feceb67
VT		 2288 break;
2289 case STA_NOTIFY_REMOVE:
b5aa9bf9 2290 ath_node_detach(sc, sta);
8feceb67
VT		 2291 break;
2292 default:
2293 break;
2294 }
f078f209
LR		 2295}
2296
8feceb67
VT		 2297static int ath9k_conf_tx(struct ieee80211_hw *hw,
2298 u16 queue,
2299 const struct ieee80211_tx_queue_params *params)
f078f209 2300{
8feceb67
VT		 2301 struct ath_softc *sc = hw->priv;
2302 struct ath9k_tx_queue_info qi;
2303 int ret = 0, qnum;
f078f209 2304
8feceb67
VT		 2305 if (queue >= WME_NUM_AC)
2306 return 0;
f078f209 2307
8feceb67
VT		 2308 qi.tqi_aifs = params->aifs;
2309 qi.tqi_cwmin = params->cw_min;
2310 qi.tqi_cwmax = params->cw_max;
2311 qi.tqi_burstTime = params->txop;
2312 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2313
8feceb67 2314 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2315 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2316 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2317 queue, qnum, params->aifs, params->cw_min,
2318 params->cw_max, params->txop);
f078f209 2319
8feceb67
VT		 2320 ret = ath_txq_update(sc, qnum, &qi);
2321 if (ret)
04bd4638 2322 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2323
8feceb67
VT		 2324 return ret;
2325}
f078f209 2326
8feceb67
VT		 2327static int ath9k_set_key(struct ieee80211_hw *hw,
2328 enum set_key_cmd cmd,
dc822b5d
JB		 2329 struct ieee80211_vif *vif,
2330 struct ieee80211_sta *sta,
8feceb67
VT		 2331 struct ieee80211_key_conf *key)
2332{
2333 struct ath_softc *sc = hw->priv;
2334 int ret = 0;
f078f209 2335
04bd4638 2336 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2337
8feceb67
VT		 2338 switch (cmd) {
2339 case SET_KEY:
dc822b5d 2340 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2341 if (ret >= 0) {
2342 key->hw_key_idx = ret;
8feceb67
VT		 2343 /* push IV and Michael MIC generation to stack */
2344 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2345 if (key->alg == ALG_TKIP)
2346 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6ace2891 2347 ret = 0;
8feceb67
VT		 2348 }
2349 break;
2350 case DISABLE_KEY:
2351 ath_key_delete(sc, key);
8feceb67
VT		 2352 break;
2353 default:
2354 ret = -EINVAL;
2355 }
f078f209 2356
8feceb67
VT		 2357 return ret;
2358}
f078f209 2359
8feceb67
VT		 2360static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2361 struct ieee80211_vif *vif,
2362 struct ieee80211_bss_conf *bss_conf,
2363 u32 changed)
2364{
2365 struct ath_softc *sc = hw->priv;
f078f209 2366
8feceb67 2367 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2368 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2369 bss_conf->use_short_preamble);
2370 if (bss_conf->use_short_preamble)
2371 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2372 else
2373 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2374 }
f078f209 2375
8feceb67 2376 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2377 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2378 bss_conf->use_cts_prot);
2379 if (bss_conf->use_cts_prot &&
2380 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2381 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2382 else
2383 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2384 }
f078f209 2385
8feceb67 2386 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2387 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2388 bss_conf->assoc);
5640b08e 2389 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2390 }
2391}
f078f209 2392
8feceb67
VT		 2393static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2394{
2395 u64 tsf;
2396 struct ath_softc *sc = hw->priv;
2397 struct ath_hal *ah = sc->sc_ah;
f078f209 2398
8feceb67 2399 tsf = ath9k_hw_gettsf64(ah);
f078f209 2400
8feceb67
VT		 2401 return tsf;
2402}
f078f209 2403
8feceb67
VT		 2404static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2405{
2406 struct ath_softc *sc = hw->priv;
2407 struct ath_hal *ah = sc->sc_ah;
c83be688 2408
8feceb67
VT		 2409 ath9k_hw_reset_tsf(ah);
2410}
f078f209 2411
8feceb67
VT		 2412static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2413 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2414 struct ieee80211_sta *sta,
2415 u16 tid, u16 *ssn)
8feceb67
VT		 2416{
2417 struct ath_softc *sc = hw->priv;
2418 int ret = 0;
f078f209 2419
8feceb67
VT		 2420 switch (action) {
2421 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2422 if (!(sc->sc_flags & SC_OP_RXAGGR))
2423 ret = -ENOTSUPP;
8feceb67
VT		 2424 break;
2425 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2426 break;
2427 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2428 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2429 if (ret < 0)
2430 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2431 "Unable to start TX aggregation\n");
8feceb67 2432 else
17741cdc 2433 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2434 break;
2435 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2436 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2437 if (ret < 0)
2438 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2439 "Unable to stop TX aggregation\n");
f078f209 2440
17741cdc 2441 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2442 break;
8469cdef
S		 2443 case IEEE80211_AMPDU_TX_RESUME:
2444 ath_tx_aggr_resume(sc, sta, tid);
2445 break;
8feceb67 2446 default:
04bd4638 2447 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2448 }
2449
2450 return ret;
f078f209
LR		 2451}
2452
8feceb67
VT		 2453static struct ieee80211_ops ath9k_ops = {
2454 .tx = ath9k_tx,
2455 .start = ath9k_start,
2456 .stop = ath9k_stop,
2457 .add_interface = ath9k_add_interface,
2458 .remove_interface = ath9k_remove_interface,
2459 .config = ath9k_config,
2460 .config_interface = ath9k_config_interface,
2461 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2462 .sta_notify = ath9k_sta_notify,
2463 .conf_tx = ath9k_conf_tx,
8feceb67 2464 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2465 .set_key = ath9k_set_key,
8feceb67
VT		 2466 .get_tsf = ath9k_get_tsf,
2467 .reset_tsf = ath9k_reset_tsf,
4233df6b 2468 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2469};
2470
392dff83
BP		 2471static struct {
2472 u32 version;
2473 const char * name;
2474} ath_mac_bb_names[] = {
2475 { AR_SREV_VERSION_5416_PCI, "5416" },
2476 { AR_SREV_VERSION_5416_PCIE, "5418" },
2477 { AR_SREV_VERSION_9100, "9100" },
2478 { AR_SREV_VERSION_9160, "9160" },
2479 { AR_SREV_VERSION_9280, "9280" },
2480 { AR_SREV_VERSION_9285, "9285" }
2481};
2482
2483static struct {
2484 u16 version;
2485 const char * name;
2486} ath_rf_names[] = {
2487 { 0, "5133" },
2488 { AR_RAD5133_SREV_MAJOR, "5133" },
2489 { AR_RAD5122_SREV_MAJOR, "5122" },
2490 { AR_RAD2133_SREV_MAJOR, "2133" },
2491 { AR_RAD2122_SREV_MAJOR, "2122" }
2492};
2493
2494/*
2495 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2496 */
392dff83
BP		 2497static const char *
2498ath_mac_bb_name(u32 mac_bb_version)
2499{
2500 int i;
2501
2502 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2503 if (ath_mac_bb_names[i].version == mac_bb_version) {
2504 return ath_mac_bb_names[i].name;
2505 }
2506 }
2507
2508 return "????";
2509}
2510
2511/*
2512 * Return the RF name. "????" is returned if the RF is unknown.
2513 */
392dff83
BP		 2514static const char *
2515ath_rf_name(u16 rf_version)
2516{
2517 int i;
2518
2519 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2520 if (ath_rf_names[i].version == rf_version) {
2521 return ath_rf_names[i].name;
2522 }
2523 }
2524
2525 return "????";
2526}
2527
f078f209
LR		 2528static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2529{
2530 void __iomem *mem;
2531 struct ath_softc *sc;
2532 struct ieee80211_hw *hw;
f078f209
LR		 2533 u8 csz;
2534 u32 val;
2535 int ret = 0;
392dff83 2536 struct ath_hal *ah;
f078f209
LR		 2537
2538 if (pci_enable_device(pdev))
2539 return -EIO;
2540
97b777db
LR		 2541 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2542
2543 if (ret) {
1d450cfc 2544 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
97b777db
LR		 2545 goto bad;
2546 }
2547
2548 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2549
2550 if (ret) {
2551 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
04bd4638 2552 "DMA enable failed\n");
f078f209
LR		 2553 goto bad;
2554 }
2555
2556 /*
2557 * Cache line size is used to size and align various
2558 * structures used to communicate with the hardware.
2559 */
2560 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2561 if (csz == 0) {
2562 /*
2563 * Linux 2.4.18 (at least) writes the cache line size
2564 * register as a 16-bit wide register which is wrong.
2565 * We must have this setup properly for rx buffer
2566 * DMA to work so force a reasonable value here if it
2567 * comes up zero.
2568 */
2569 csz = L1_CACHE_BYTES / sizeof(u32);
2570 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2571 }
2572 /*
2573 * The default setting of latency timer yields poor results,
2574 * set it to the value used by other systems. It may be worth
2575 * tweaking this setting more.
2576 */
2577 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2578
2579 pci_set_master(pdev);
2580
2581 /*
2582 * Disable the RETRY_TIMEOUT register (0x41) to keep
2583 * PCI Tx retries from interfering with C3 CPU state.
2584 */
2585 pci_read_config_dword(pdev, 0x40, &val);
2586 if ((val & 0x0000ff00) != 0)
2587 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2588
2589 ret = pci_request_region(pdev, 0, "ath9k");
2590 if (ret) {
2591 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2592 ret = -ENODEV;
2593 goto bad;
2594 }
2595
2596 mem = pci_iomap(pdev, 0, 0);
2597 if (!mem) {
2598 printk(KERN_ERR "PCI memory map error\n") ;
2599 ret = -EIO;
2600 goto bad1;
2601 }
2602
2603 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2604 if (hw == NULL) {
2605 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2606 goto bad2;
2607 }
2608
f078f209
LR		 2609 SET_IEEE80211_DEV(hw, &pdev->dev);
2610 pci_set_drvdata(pdev, hw);
2611
2612 sc = hw->priv;
2613 sc->hw = hw;
2614 sc->pdev = pdev;
2615 sc->mem = mem;
2616
2617 if (ath_attach(id->device, sc) != 0) {
2618 ret = -ENODEV;
2619 goto bad3;
2620 }
2621
2622 /* setup interrupt service routine */
2623
2624 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2625 printk(KERN_ERR "%s: request_irq failed\n",
2626 wiphy_name(hw->wiphy));
2627 ret = -EIO;
2628 goto bad4;
2629 }
2630
392dff83
BP		 2631 ah = sc->sc_ah;
2632 printk(KERN_INFO
2633 "%s: Atheros AR%s MAC/BB Rev:%x "
2634 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
f078f209 2635 wiphy_name(hw->wiphy),
392dff83
BP		 2636 ath_mac_bb_name(ah->ah_macVersion),
2637 ah->ah_macRev,
2638 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2639 ah->ah_phyRev,
f078f209
LR		 2640 (unsigned long)mem, pdev->irq);
2641
2642 return 0;
2643bad4:
2644 ath_detach(sc);
2645bad3:
2646 ieee80211_free_hw(hw);
2647bad2:
2648 pci_iounmap(pdev, mem);
2649bad1:
2650 pci_release_region(pdev, 0);
2651bad:
2652 pci_disable_device(pdev);
2653 return ret;
2654}
2655
2656static void ath_pci_remove(struct pci_dev *pdev)
2657{
2658 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2659 struct ath_softc *sc = hw->priv;
2660
f078f209 2661 ath_detach(sc);
9c84b797
S		 2662 if (pdev->irq)
2663 free_irq(pdev->irq, sc);
f078f209
LR		 2664 pci_iounmap(pdev, sc->mem);
2665 pci_release_region(pdev, 0);
2666 pci_disable_device(pdev);
2667 ieee80211_free_hw(hw);
2668}
2669
2670#ifdef CONFIG_PM
2671
2672static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2673{
c83be688
VT		 2674 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2675 struct ath_softc *sc = hw->priv;
2676
2677 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
500c064d 2678
e97275cb 2679#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2680 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2681 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2682#endif
2683
f078f209
LR		 2684 pci_save_state(pdev);
2685 pci_disable_device(pdev);
2686 pci_set_power_state(pdev, 3);
2687
2688 return 0;
2689}
2690
2691static int ath_pci_resume(struct pci_dev *pdev)
2692{
c83be688
VT		 2693 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2694 struct ath_softc *sc = hw->priv;
f078f209
LR		 2695 u32 val;
2696 int err;
2697
2698 err = pci_enable_device(pdev);
2699 if (err)
2700 return err;
2701 pci_restore_state(pdev);
2702 /*
2703 * Suspend/Resume resets the PCI configuration space, so we have to
2704 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2705 * PCI Tx retries from interfering with C3 CPU state
2706 */
2707 pci_read_config_dword(pdev, 0x40, &val);
2708 if ((val & 0x0000ff00) != 0)
2709 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2710
c83be688
VT		 2711 /* Enable LED */
2712 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2713 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2714 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2715
e97275cb 2716#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 2717 /*
2718 * check the h/w rfkill state on resume
2719 * and start the rfkill poll timer
2720 */
2721 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2722 queue_delayed_work(sc->hw->workqueue,
2723 &sc->rf_kill.rfkill_poll, 0);
2724#endif
2725
f078f209
LR		 2726 return 0;
2727}
2728
2729#endif /* CONFIG_PM */
2730
2731MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2732
2733static struct pci_driver ath_pci_driver = {
2734 .name = "ath9k",
2735 .id_table = ath_pci_id_table,
2736 .probe = ath_pci_probe,
2737 .remove = ath_pci_remove,
2738#ifdef CONFIG_PM
2739 .suspend = ath_pci_suspend,
2740 .resume = ath_pci_resume,
2741#endif /* CONFIG_PM */
2742};
2743
2744static int __init init_ath_pci(void)
2745{
ca8a8560
VT		 2746 int error;
2747
f078f209
LR		 2748 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2749
ca8a8560
VT		 2750 /* Register rate control algorithm */
2751 error = ath_rate_control_register();
2752 if (error != 0) {
2753 printk(KERN_ERR
2754 "Unable to register rate control algorithm: %d\n",
2755 error);
2756 ath_rate_control_unregister();
2757 return error;
2758 }
2759
f078f209
LR		 2760 if (pci_register_driver(&ath_pci_driver) < 0) {
2761 printk(KERN_ERR
2762 "ath_pci: No devices found, driver not installed.\n");
ca8a8560 2763 ath_rate_control_unregister();
f078f209
LR		 2764 pci_unregister_driver(&ath_pci_driver);
2765 return -ENODEV;
2766 }
2767
2768 return 0;
2769}
2770module_init(init_ath_pci);
2771
2772static void __exit exit_ath_pci(void)
2773{
ca8a8560 2774 ath_rate_control_unregister();
f078f209 2775 pci_unregister_driver(&ath_pci_driver);
04bd4638 2776 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209
LR		 2777}
2778module_exit(exit_ath_pci);
Linux 6.x block layer and io_uring tree(s)