Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 LR |
17 | #include <linux/nl80211.h> |
18 | #include "core.h" | |
392dff83 | 19 | #include "reg.h" |
2a163c6d | 20 | #include "hw.h" |
f078f209 LR |
21 | |
22 | #define ATH_PCI_VERSION "0.1" | |
23 | ||
f078f209 LR |
24 | static char *dev_info = "ath9k"; |
25 | ||
26 | MODULE_AUTHOR("Atheros Communications"); | |
27 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); | |
28 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); | |
29 | MODULE_LICENSE("Dual BSD/GPL"); | |
30 | ||
31 | static struct pci_device_id ath_pci_id_table[] __devinitdata = { | |
32 | { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */ | |
33 | { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */ | |
34 | { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */ | |
35 | { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */ | |
36 | { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */ | |
37 | { 0 } | |
38 | }; | |
39 | ||
9757d556 S |
40 | static void ath_detach(struct ath_softc *sc); |
41 | ||
ff37e337 S |
42 | /* return bus cachesize in 4B word units */ |
43 | ||
44 | static void bus_read_cachesize(struct ath_softc *sc, int *csz) | |
45 | { | |
46 | u8 u8tmp; | |
47 | ||
48 | pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp); | |
49 | *csz = (int)u8tmp; | |
50 | ||
51 | /* | |
52 | * This check was put in to avoid "unplesant" consequences if | |
53 | * the bootrom has not fully initialized all PCI devices. | |
54 | * Sometimes the cache line size register is not set | |
55 | */ | |
56 | ||
57 | if (*csz == 0) | |
58 | *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */ | |
59 | } | |
60 | ||
61 | static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode) | |
62 | { | |
63 | sc->sc_curmode = mode; | |
64 | /* | |
65 | * All protection frames are transmited at 2Mb/s for | |
66 | * 11g, otherwise at 1Mb/s. | |
67 | * XXX select protection rate index from rate table. | |
68 | */ | |
69 | sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0); | |
70 | } | |
71 | ||
72 | static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan) | |
73 | { | |
74 | if (chan->chanmode == CHANNEL_A) | |
75 | return ATH9K_MODE_11A; | |
76 | else if (chan->chanmode == CHANNEL_G) | |
77 | return ATH9K_MODE_11G; | |
78 | else if (chan->chanmode == CHANNEL_B) | |
79 | return ATH9K_MODE_11B; | |
80 | else if (chan->chanmode == CHANNEL_A_HT20) | |
81 | return ATH9K_MODE_11NA_HT20; | |
82 | else if (chan->chanmode == CHANNEL_G_HT20) | |
83 | return ATH9K_MODE_11NG_HT20; | |
84 | else if (chan->chanmode == CHANNEL_A_HT40PLUS) | |
85 | return ATH9K_MODE_11NA_HT40PLUS; | |
86 | else if (chan->chanmode == CHANNEL_A_HT40MINUS) | |
87 | return ATH9K_MODE_11NA_HT40MINUS; | |
88 | else if (chan->chanmode == CHANNEL_G_HT40PLUS) | |
89 | return ATH9K_MODE_11NG_HT40PLUS; | |
90 | else if (chan->chanmode == CHANNEL_G_HT40MINUS) | |
91 | return ATH9K_MODE_11NG_HT40MINUS; | |
92 | ||
93 | WARN_ON(1); /* should not get here */ | |
94 | ||
95 | return ATH9K_MODE_11B; | |
96 | } | |
97 | ||
98 | static void ath_update_txpow(struct ath_softc *sc) | |
99 | { | |
100 | struct ath_hal *ah = sc->sc_ah; | |
101 | u32 txpow; | |
102 | ||
103 | if (sc->sc_curtxpow != sc->sc_config.txpowlimit) { | |
104 | ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit); | |
105 | /* read back in case value is clamped */ | |
106 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
107 | sc->sc_curtxpow = txpow; | |
108 | } | |
109 | } | |
110 | ||
111 | static u8 parse_mpdudensity(u8 mpdudensity) | |
112 | { | |
113 | /* | |
114 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
115 | * 0 for no restriction | |
116 | * 1 for 1/4 us | |
117 | * 2 for 1/2 us | |
118 | * 3 for 1 us | |
119 | * 4 for 2 us | |
120 | * 5 for 4 us | |
121 | * 6 for 8 us | |
122 | * 7 for 16 us | |
123 | */ | |
124 | switch (mpdudensity) { | |
125 | case 0: | |
126 | return 0; | |
127 | case 1: | |
128 | case 2: | |
129 | case 3: | |
130 | /* Our lower layer calculations limit our precision to | |
131 | 1 microsecond */ | |
132 | return 1; | |
133 | case 4: | |
134 | return 2; | |
135 | case 5: | |
136 | return 4; | |
137 | case 6: | |
138 | return 8; | |
139 | case 7: | |
140 | return 16; | |
141 | default: | |
142 | return 0; | |
143 | } | |
144 | } | |
145 | ||
146 | static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band) | |
147 | { | |
148 | struct ath_rate_table *rate_table = NULL; | |
149 | struct ieee80211_supported_band *sband; | |
150 | struct ieee80211_rate *rate; | |
151 | int i, maxrates; | |
152 | ||
153 | switch (band) { | |
154 | case IEEE80211_BAND_2GHZ: | |
155 | rate_table = sc->hw_rate_table[ATH9K_MODE_11G]; | |
156 | break; | |
157 | case IEEE80211_BAND_5GHZ: | |
158 | rate_table = sc->hw_rate_table[ATH9K_MODE_11A]; | |
159 | break; | |
160 | default: | |
161 | break; | |
162 | } | |
163 | ||
164 | if (rate_table == NULL) | |
165 | return; | |
166 | ||
167 | sband = &sc->sbands[band]; | |
168 | rate = sc->rates[band]; | |
169 | ||
170 | if (rate_table->rate_cnt > ATH_RATE_MAX) | |
171 | maxrates = ATH_RATE_MAX; | |
172 | else | |
173 | maxrates = rate_table->rate_cnt; | |
174 | ||
175 | for (i = 0; i < maxrates; i++) { | |
176 | rate[i].bitrate = rate_table->info[i].ratekbps / 100; | |
177 | rate[i].hw_value = rate_table->info[i].ratecode; | |
178 | sband->n_bitrates++; | |
04bd4638 S |
179 | DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", |
180 | rate[i].bitrate / 10, rate[i].hw_value); | |
ff37e337 S |
181 | } |
182 | } | |
183 | ||
184 | static int ath_setup_channels(struct ath_softc *sc) | |
185 | { | |
186 | struct ath_hal *ah = sc->sc_ah; | |
187 | int nchan, i, a = 0, b = 0; | |
188 | u8 regclassids[ATH_REGCLASSIDS_MAX]; | |
189 | u32 nregclass = 0; | |
190 | struct ieee80211_supported_band *band_2ghz; | |
191 | struct ieee80211_supported_band *band_5ghz; | |
192 | struct ieee80211_channel *chan_2ghz; | |
193 | struct ieee80211_channel *chan_5ghz; | |
194 | struct ath9k_channel *c; | |
195 | ||
196 | /* Fill in ah->ah_channels */ | |
197 | if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan, | |
198 | regclassids, ATH_REGCLASSIDS_MAX, | |
199 | &nregclass, CTRY_DEFAULT, false, 1)) { | |
200 | u32 rd = ah->ah_currentRD; | |
201 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 202 | "Unable to collect channel list; " |
ff37e337 | 203 | "regdomain likely %u country code %u\n", |
04bd4638 | 204 | rd, CTRY_DEFAULT); |
ff37e337 S |
205 | return -EINVAL; |
206 | } | |
207 | ||
208 | band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
209 | band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ]; | |
210 | chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ]; | |
211 | chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ]; | |
212 | ||
213 | for (i = 0; i < nchan; i++) { | |
214 | c = &ah->ah_channels[i]; | |
215 | if (IS_CHAN_2GHZ(c)) { | |
216 | chan_2ghz[a].band = IEEE80211_BAND_2GHZ; | |
217 | chan_2ghz[a].center_freq = c->channel; | |
218 | chan_2ghz[a].max_power = c->maxTxPower; | |
219 | ||
220 | if (c->privFlags & CHANNEL_DISALLOW_ADHOC) | |
221 | chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS; | |
222 | if (c->channelFlags & CHANNEL_PASSIVE) | |
223 | chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
224 | ||
225 | band_2ghz->n_channels = ++a; | |
226 | ||
04bd4638 | 227 | DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, " |
ff37e337 | 228 | "channelFlags: 0x%x\n", |
04bd4638 | 229 | c->channel, c->channelFlags); |
ff37e337 S |
230 | } else if (IS_CHAN_5GHZ(c)) { |
231 | chan_5ghz[b].band = IEEE80211_BAND_5GHZ; | |
232 | chan_5ghz[b].center_freq = c->channel; | |
233 | chan_5ghz[b].max_power = c->maxTxPower; | |
234 | ||
235 | if (c->privFlags & CHANNEL_DISALLOW_ADHOC) | |
236 | chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS; | |
237 | if (c->channelFlags & CHANNEL_PASSIVE) | |
238 | chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN; | |
239 | ||
240 | band_5ghz->n_channels = ++b; | |
241 | ||
04bd4638 | 242 | DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, " |
ff37e337 | 243 | "channelFlags: 0x%x\n", |
04bd4638 | 244 | c->channel, c->channelFlags); |
ff37e337 S |
245 | } |
246 | } | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
251 | /* | |
252 | * Set/change channels. If the channel is really being changed, it's done | |
253 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
254 | * DMA, then restart stuff. | |
255 | */ | |
256 | static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan) | |
257 | { | |
258 | struct ath_hal *ah = sc->sc_ah; | |
259 | bool fastcc = true, stopped; | |
260 | ||
261 | if (sc->sc_flags & SC_OP_INVALID) | |
262 | return -EIO; | |
263 | ||
ff37e337 S |
264 | if (hchan->channel != sc->sc_ah->ah_curchan->channel || |
265 | hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags || | |
266 | (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) || | |
267 | (sc->sc_flags & SC_OP_FULL_RESET)) { | |
268 | int status; | |
269 | /* | |
270 | * This is only performed if the channel settings have | |
271 | * actually changed. | |
272 | * | |
273 | * To switch channels clear any pending DMA operations; | |
274 | * wait long enough for the RX fifo to drain, reset the | |
275 | * hardware at the new frequency, and then re-enable | |
276 | * the relevant bits of the h/w. | |
277 | */ | |
04bd4638 S |
278 | ath9k_hw_set_interrupts(ah, 0); |
279 | ath_draintxq(sc, false); | |
280 | stopped = ath_stoprecv(sc); | |
ff37e337 S |
281 | |
282 | /* XXX: do not flush receive queue here. We don't want | |
283 | * to flush data frames already in queue because of | |
284 | * changing channel. */ | |
285 | ||
286 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) | |
287 | fastcc = false; | |
288 | ||
99405f93 | 289 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 | 290 | "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n", |
99405f93 S |
291 | sc->sc_ah->ah_curchan->channel, |
292 | hchan->channel, hchan->channelFlags, sc->tx_chan_width); | |
293 | ||
ff37e337 | 294 | spin_lock_bh(&sc->sc_resetlock); |
99405f93 | 295 | if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width, |
ff37e337 S |
296 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, |
297 | sc->sc_ht_extprotspacing, fastcc, &status)) { | |
298 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 S |
299 | "Unable to reset channel %u (%uMhz) " |
300 | "flags 0x%x hal status %u\n", | |
ff37e337 S |
301 | ath9k_hw_mhz2ieee(ah, hchan->channel, |
302 | hchan->channelFlags), | |
303 | hchan->channel, hchan->channelFlags, status); | |
304 | spin_unlock_bh(&sc->sc_resetlock); | |
305 | return -EIO; | |
306 | } | |
307 | spin_unlock_bh(&sc->sc_resetlock); | |
308 | ||
309 | sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE; | |
310 | sc->sc_flags &= ~SC_OP_FULL_RESET; | |
311 | ||
312 | if (ath_startrecv(sc) != 0) { | |
313 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 314 | "Unable to restart recv logic\n"); |
ff37e337 S |
315 | return -EIO; |
316 | } | |
317 | ||
318 | ath_setcurmode(sc, ath_chan2mode(hchan)); | |
319 | ath_update_txpow(sc); | |
320 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
321 | } | |
322 | return 0; | |
323 | } | |
324 | ||
325 | /* | |
326 | * This routine performs the periodic noise floor calibration function | |
327 | * that is used to adjust and optimize the chip performance. This | |
328 | * takes environmental changes (location, temperature) into account. | |
329 | * When the task is complete, it reschedules itself depending on the | |
330 | * appropriate interval that was calculated. | |
331 | */ | |
332 | static void ath_ani_calibrate(unsigned long data) | |
333 | { | |
334 | struct ath_softc *sc; | |
335 | struct ath_hal *ah; | |
336 | bool longcal = false; | |
337 | bool shortcal = false; | |
338 | bool aniflag = false; | |
339 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
340 | u32 cal_interval; | |
341 | ||
342 | sc = (struct ath_softc *)data; | |
343 | ah = sc->sc_ah; | |
344 | ||
345 | /* | |
346 | * don't calibrate when we're scanning. | |
347 | * we are most likely not on our home channel. | |
348 | */ | |
349 | if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC) | |
350 | return; | |
351 | ||
352 | /* Long calibration runs independently of short calibration. */ | |
353 | if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) { | |
354 | longcal = true; | |
04bd4638 | 355 | DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
ff37e337 S |
356 | sc->sc_ani.sc_longcal_timer = timestamp; |
357 | } | |
358 | ||
359 | /* Short calibration applies only while sc_caldone is false */ | |
360 | if (!sc->sc_ani.sc_caldone) { | |
361 | if ((timestamp - sc->sc_ani.sc_shortcal_timer) >= | |
362 | ATH_SHORT_CALINTERVAL) { | |
363 | shortcal = true; | |
04bd4638 | 364 | DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); |
ff37e337 S |
365 | sc->sc_ani.sc_shortcal_timer = timestamp; |
366 | sc->sc_ani.sc_resetcal_timer = timestamp; | |
367 | } | |
368 | } else { | |
369 | if ((timestamp - sc->sc_ani.sc_resetcal_timer) >= | |
370 | ATH_RESTART_CALINTERVAL) { | |
371 | ath9k_hw_reset_calvalid(ah, ah->ah_curchan, | |
372 | &sc->sc_ani.sc_caldone); | |
373 | if (sc->sc_ani.sc_caldone) | |
374 | sc->sc_ani.sc_resetcal_timer = timestamp; | |
375 | } | |
376 | } | |
377 | ||
378 | /* Verify whether we must check ANI */ | |
379 | if ((timestamp - sc->sc_ani.sc_checkani_timer) >= | |
380 | ATH_ANI_POLLINTERVAL) { | |
381 | aniflag = true; | |
382 | sc->sc_ani.sc_checkani_timer = timestamp; | |
383 | } | |
384 | ||
385 | /* Skip all processing if there's nothing to do. */ | |
386 | if (longcal || shortcal || aniflag) { | |
387 | /* Call ANI routine if necessary */ | |
388 | if (aniflag) | |
389 | ath9k_hw_ani_monitor(ah, &sc->sc_halstats, | |
390 | ah->ah_curchan); | |
391 | ||
392 | /* Perform calibration if necessary */ | |
393 | if (longcal || shortcal) { | |
394 | bool iscaldone = false; | |
395 | ||
396 | if (ath9k_hw_calibrate(ah, ah->ah_curchan, | |
397 | sc->sc_rx_chainmask, longcal, | |
398 | &iscaldone)) { | |
399 | if (longcal) | |
400 | sc->sc_ani.sc_noise_floor = | |
401 | ath9k_hw_getchan_noise(ah, | |
402 | ah->ah_curchan); | |
403 | ||
404 | DPRINTF(sc, ATH_DBG_ANI, | |
04bd4638 | 405 | "calibrate chan %u/%x nf: %d\n", |
ff37e337 S |
406 | ah->ah_curchan->channel, |
407 | ah->ah_curchan->channelFlags, | |
408 | sc->sc_ani.sc_noise_floor); | |
409 | } else { | |
410 | DPRINTF(sc, ATH_DBG_ANY, | |
04bd4638 | 411 | "calibrate chan %u/%x failed\n", |
ff37e337 S |
412 | ah->ah_curchan->channel, |
413 | ah->ah_curchan->channelFlags); | |
414 | } | |
415 | sc->sc_ani.sc_caldone = iscaldone; | |
416 | } | |
417 | } | |
418 | ||
419 | /* | |
420 | * Set timer interval based on previous results. | |
421 | * The interval must be the shortest necessary to satisfy ANI, | |
422 | * short calibration and long calibration. | |
423 | */ | |
424 | ||
425 | cal_interval = ATH_ANI_POLLINTERVAL; | |
426 | if (!sc->sc_ani.sc_caldone) | |
427 | cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL); | |
428 | ||
429 | mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval)); | |
430 | } | |
431 | ||
432 | /* | |
433 | * Update tx/rx chainmask. For legacy association, | |
434 | * hard code chainmask to 1x1, for 11n association, use | |
435 | * the chainmask configuration. | |
436 | */ | |
437 | static void ath_update_chainmask(struct ath_softc *sc, int is_ht) | |
438 | { | |
439 | sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; | |
440 | if (is_ht) { | |
441 | sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask; | |
442 | sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask; | |
443 | } else { | |
444 | sc->sc_tx_chainmask = 1; | |
445 | sc->sc_rx_chainmask = 1; | |
446 | } | |
447 | ||
04bd4638 S |
448 | DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", |
449 | sc->sc_tx_chainmask, sc->sc_rx_chainmask); | |
ff37e337 S |
450 | } |
451 | ||
452 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
453 | { | |
454 | struct ath_node *an; | |
455 | ||
456 | an = (struct ath_node *)sta->drv_priv; | |
457 | ||
458 | if (sc->sc_flags & SC_OP_TXAGGR) | |
459 | ath_tx_node_init(sc, an); | |
460 | ||
461 | an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR + | |
462 | sta->ht_cap.ampdu_factor); | |
463 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
464 | } | |
465 | ||
466 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
467 | { | |
468 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
469 | ||
470 | if (sc->sc_flags & SC_OP_TXAGGR) | |
471 | ath_tx_node_cleanup(sc, an); | |
472 | } | |
473 | ||
474 | static void ath9k_tasklet(unsigned long data) | |
475 | { | |
476 | struct ath_softc *sc = (struct ath_softc *)data; | |
477 | u32 status = sc->sc_intrstatus; | |
478 | ||
479 | if (status & ATH9K_INT_FATAL) { | |
480 | /* need a chip reset */ | |
481 | ath_reset(sc, false); | |
482 | return; | |
483 | } else { | |
484 | ||
485 | if (status & | |
486 | (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) { | |
487 | spin_lock_bh(&sc->sc_rxflushlock); | |
488 | ath_rx_tasklet(sc, 0); | |
489 | spin_unlock_bh(&sc->sc_rxflushlock); | |
490 | } | |
491 | /* XXX: optimize this */ | |
492 | if (status & ATH9K_INT_TX) | |
493 | ath_tx_tasklet(sc); | |
494 | } | |
495 | ||
496 | /* re-enable hardware interrupt */ | |
497 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); | |
498 | } | |
499 | ||
500 | static irqreturn_t ath_isr(int irq, void *dev) | |
501 | { | |
502 | struct ath_softc *sc = dev; | |
503 | struct ath_hal *ah = sc->sc_ah; | |
504 | enum ath9k_int status; | |
505 | bool sched = false; | |
506 | ||
507 | do { | |
508 | if (sc->sc_flags & SC_OP_INVALID) { | |
509 | /* | |
510 | * The hardware is not ready/present, don't | |
511 | * touch anything. Note this can happen early | |
512 | * on if the IRQ is shared. | |
513 | */ | |
514 | return IRQ_NONE; | |
515 | } | |
516 | if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */ | |
517 | return IRQ_NONE; | |
518 | } | |
519 | ||
520 | /* | |
521 | * Figure out the reason(s) for the interrupt. Note | |
522 | * that the hal returns a pseudo-ISR that may include | |
523 | * bits we haven't explicitly enabled so we mask the | |
524 | * value to insure we only process bits we requested. | |
525 | */ | |
526 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
527 | ||
528 | status &= sc->sc_imask; /* discard unasked-for bits */ | |
529 | ||
530 | /* | |
531 | * If there are no status bits set, then this interrupt was not | |
532 | * for me (should have been caught above). | |
533 | */ | |
534 | if (!status) | |
535 | return IRQ_NONE; | |
536 | ||
537 | sc->sc_intrstatus = status; | |
538 | ||
539 | if (status & ATH9K_INT_FATAL) { | |
540 | /* need a chip reset */ | |
541 | sched = true; | |
542 | } else if (status & ATH9K_INT_RXORN) { | |
543 | /* need a chip reset */ | |
544 | sched = true; | |
545 | } else { | |
546 | if (status & ATH9K_INT_SWBA) { | |
547 | /* schedule a tasklet for beacon handling */ | |
548 | tasklet_schedule(&sc->bcon_tasklet); | |
549 | } | |
550 | if (status & ATH9K_INT_RXEOL) { | |
551 | /* | |
552 | * NB: the hardware should re-read the link when | |
553 | * RXE bit is written, but it doesn't work | |
554 | * at least on older hardware revs. | |
555 | */ | |
556 | sched = true; | |
557 | } | |
558 | ||
559 | if (status & ATH9K_INT_TXURN) | |
560 | /* bump tx trigger level */ | |
561 | ath9k_hw_updatetxtriglevel(ah, true); | |
562 | /* XXX: optimize this */ | |
563 | if (status & ATH9K_INT_RX) | |
564 | sched = true; | |
565 | if (status & ATH9K_INT_TX) | |
566 | sched = true; | |
567 | if (status & ATH9K_INT_BMISS) | |
568 | sched = true; | |
569 | /* carrier sense timeout */ | |
570 | if (status & ATH9K_INT_CST) | |
571 | sched = true; | |
572 | if (status & ATH9K_INT_MIB) { | |
573 | /* | |
574 | * Disable interrupts until we service the MIB | |
575 | * interrupt; otherwise it will continue to | |
576 | * fire. | |
577 | */ | |
578 | ath9k_hw_set_interrupts(ah, 0); | |
579 | /* | |
580 | * Let the hal handle the event. We assume | |
581 | * it will clear whatever condition caused | |
582 | * the interrupt. | |
583 | */ | |
584 | ath9k_hw_procmibevent(ah, &sc->sc_halstats); | |
585 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
586 | } | |
587 | if (status & ATH9K_INT_TIM_TIMER) { | |
588 | if (!(ah->ah_caps.hw_caps & | |
589 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
590 | /* Clear RxAbort bit so that we can | |
591 | * receive frames */ | |
592 | ath9k_hw_setrxabort(ah, 0); | |
593 | sched = true; | |
594 | } | |
595 | } | |
596 | } | |
597 | } while (0); | |
598 | ||
599 | if (sched) { | |
600 | /* turn off every interrupt except SWBA */ | |
601 | ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA)); | |
602 | tasklet_schedule(&sc->intr_tq); | |
603 | } | |
604 | ||
605 | return IRQ_HANDLED; | |
606 | } | |
607 | ||
f078f209 LR |
608 | static int ath_get_channel(struct ath_softc *sc, |
609 | struct ieee80211_channel *chan) | |
610 | { | |
611 | int i; | |
612 | ||
613 | for (i = 0; i < sc->sc_ah->ah_nchan; i++) { | |
614 | if (sc->sc_ah->ah_channels[i].channel == chan->center_freq) | |
615 | return i; | |
616 | } | |
617 | ||
618 | return -1; | |
619 | } | |
620 | ||
e11602b7 S |
621 | /* ext_chan_offset: (-1, 0, 1) (below, none, above) */ |
622 | ||
f078f209 | 623 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 624 | struct ieee80211_channel *chan, |
e11602b7 S |
625 | int ext_chan_offset, |
626 | enum ath9k_ht_macmode tx_chan_width) | |
f078f209 LR |
627 | { |
628 | u32 chanmode = 0; | |
f078f209 LR |
629 | |
630 | switch (chan->band) { | |
631 | case IEEE80211_BAND_2GHZ: | |
e11602b7 | 632 | if ((ext_chan_offset == 0) && |
f078f209 LR |
633 | (tx_chan_width == ATH9K_HT_MACMODE_20)) |
634 | chanmode = CHANNEL_G_HT20; | |
e11602b7 | 635 | if ((ext_chan_offset == 1) && |
f078f209 LR |
636 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
637 | chanmode = CHANNEL_G_HT40PLUS; | |
e11602b7 | 638 | if ((ext_chan_offset == -1) && |
f078f209 LR |
639 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
640 | chanmode = CHANNEL_G_HT40MINUS; | |
641 | break; | |
642 | case IEEE80211_BAND_5GHZ: | |
e11602b7 | 643 | if ((ext_chan_offset == 0) && |
f078f209 LR |
644 | (tx_chan_width == ATH9K_HT_MACMODE_20)) |
645 | chanmode = CHANNEL_A_HT20; | |
e11602b7 | 646 | if ((ext_chan_offset == 1) && |
f078f209 LR |
647 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
648 | chanmode = CHANNEL_A_HT40PLUS; | |
e11602b7 | 649 | if ((ext_chan_offset == -1) && |
f078f209 LR |
650 | (tx_chan_width == ATH9K_HT_MACMODE_2040)) |
651 | chanmode = CHANNEL_A_HT40MINUS; | |
652 | break; | |
653 | default: | |
654 | break; | |
655 | } | |
656 | ||
657 | return chanmode; | |
658 | } | |
659 | ||
ff37e337 S |
660 | static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot) |
661 | { | |
662 | ath9k_hw_keyreset(sc->sc_ah, keyix); | |
663 | if (freeslot) | |
664 | clear_bit(keyix, sc->sc_keymap); | |
665 | } | |
666 | ||
667 | static int ath_keyset(struct ath_softc *sc, u16 keyix, | |
668 | struct ath9k_keyval *hk, const u8 mac[ETH_ALEN]) | |
669 | { | |
670 | bool status; | |
671 | ||
672 | status = ath9k_hw_set_keycache_entry(sc->sc_ah, | |
673 | keyix, hk, mac, false); | |
674 | ||
675 | return status != false; | |
676 | } | |
f078f209 LR |
677 | |
678 | static int ath_setkey_tkip(struct ath_softc *sc, | |
679 | struct ieee80211_key_conf *key, | |
680 | struct ath9k_keyval *hk, | |
681 | const u8 *addr) | |
682 | { | |
683 | u8 *key_rxmic = NULL; | |
684 | u8 *key_txmic = NULL; | |
685 | ||
686 | key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; | |
687 | key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
688 | ||
689 | if (addr == NULL) { | |
690 | /* Group key installation */ | |
691 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
692 | return ath_keyset(sc, key->keyidx, hk, addr); | |
693 | } | |
694 | if (!sc->sc_splitmic) { | |
695 | /* | |
696 | * data key goes at first index, | |
697 | * the hal handles the MIC keys at index+64. | |
698 | */ | |
699 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
700 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
701 | return ath_keyset(sc, key->keyidx, hk, addr); | |
702 | } | |
703 | /* | |
704 | * TX key goes at first index, RX key at +32. | |
705 | * The hal handles the MIC keys at index+64. | |
706 | */ | |
707 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
708 | if (!ath_keyset(sc, key->keyidx, hk, NULL)) { | |
709 | /* Txmic entry failed. No need to proceed further */ | |
710 | DPRINTF(sc, ATH_DBG_KEYCACHE, | |
04bd4638 | 711 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
712 | return 0; |
713 | } | |
714 | ||
715 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
716 | /* XXX delete tx key on failure? */ | |
717 | return ath_keyset(sc, key->keyidx+32, hk, addr); | |
718 | } | |
719 | ||
720 | static int ath_key_config(struct ath_softc *sc, | |
721 | const u8 *addr, | |
722 | struct ieee80211_key_conf *key) | |
723 | { | |
724 | struct ieee80211_vif *vif; | |
725 | struct ath9k_keyval hk; | |
726 | const u8 *mac = NULL; | |
727 | int ret = 0; | |
05c914fe | 728 | enum nl80211_iftype opmode; |
f078f209 LR |
729 | |
730 | memset(&hk, 0, sizeof(hk)); | |
731 | ||
732 | switch (key->alg) { | |
733 | case ALG_WEP: | |
734 | hk.kv_type = ATH9K_CIPHER_WEP; | |
735 | break; | |
736 | case ALG_TKIP: | |
737 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
738 | break; | |
739 | case ALG_CCMP: | |
740 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
741 | break; | |
742 | default: | |
743 | return -EINVAL; | |
744 | } | |
745 | ||
746 | hk.kv_len = key->keylen; | |
747 | memcpy(hk.kv_val, key->key, key->keylen); | |
748 | ||
749 | if (!sc->sc_vaps[0]) | |
750 | return -EIO; | |
751 | ||
5640b08e | 752 | vif = sc->sc_vaps[0]; |
f078f209 LR |
753 | opmode = vif->type; |
754 | ||
755 | /* | |
756 | * Strategy: | |
d97809db CM |
757 | * For STA mc tx, we will not setup a key at |
758 | * all since we never tx mc. | |
759 | * | |
760 | * For STA mc rx, we will use the keyID. | |
761 | * | |
762 | * For ADHOC mc tx, we will use the keyID, and no macaddr. | |
763 | * | |
764 | * For ADHOC mc rx, we will alloc a slot and plumb the mac of | |
765 | * the peer node. | |
766 | * BUT we will plumb a cleartext key so that we can do | |
767 | * per-Sta default key table lookup in software. | |
f078f209 LR |
768 | */ |
769 | if (is_broadcast_ether_addr(addr)) { | |
770 | switch (opmode) { | |
05c914fe | 771 | case NL80211_IFTYPE_STATION: |
f078f209 LR |
772 | /* default key: could be group WPA key |
773 | * or could be static WEP key */ | |
774 | mac = NULL; | |
775 | break; | |
05c914fe | 776 | case NL80211_IFTYPE_ADHOC: |
f078f209 | 777 | break; |
05c914fe | 778 | case NL80211_IFTYPE_AP: |
f078f209 LR |
779 | break; |
780 | default: | |
781 | ASSERT(0); | |
782 | break; | |
783 | } | |
784 | } else { | |
785 | mac = addr; | |
786 | } | |
787 | ||
788 | if (key->alg == ALG_TKIP) | |
789 | ret = ath_setkey_tkip(sc, key, &hk, mac); | |
790 | else | |
791 | ret = ath_keyset(sc, key->keyidx, &hk, mac); | |
792 | ||
793 | if (!ret) | |
794 | return -EIO; | |
795 | ||
f078f209 LR |
796 | return 0; |
797 | } | |
798 | ||
799 | static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key) | |
800 | { | |
f078f209 LR |
801 | int freeslot; |
802 | ||
ff9b662d | 803 | freeslot = (key->keyidx >= 4) ? 1 : 0; |
f078f209 | 804 | ath_key_reset(sc, key->keyidx, freeslot); |
f078f209 LR |
805 | } |
806 | ||
d9fe60de | 807 | static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info) |
f078f209 | 808 | { |
60653678 S |
809 | #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */ |
810 | #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */ | |
f078f209 | 811 | |
d9fe60de JB |
812 | ht_info->ht_supported = true; |
813 | ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | | |
814 | IEEE80211_HT_CAP_SM_PS | | |
815 | IEEE80211_HT_CAP_SGI_40 | | |
816 | IEEE80211_HT_CAP_DSSSCCK40; | |
f078f209 | 817 | |
60653678 S |
818 | ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536; |
819 | ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8; | |
d9fe60de JB |
820 | /* set up supported mcs set */ |
821 | memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); | |
822 | ht_info->mcs.rx_mask[0] = 0xff; | |
823 | ht_info->mcs.rx_mask[1] = 0xff; | |
824 | ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; | |
f078f209 LR |
825 | } |
826 | ||
8feceb67 VT |
827 | static void ath9k_ht_conf(struct ath_softc *sc, |
828 | struct ieee80211_bss_conf *bss_conf) | |
f078f209 | 829 | { |
ae5eb026 | 830 | if (sc->hw->conf.ht.enabled) { |
ae5eb026 | 831 | if (bss_conf->ht.width_40_ok) |
99405f93 | 832 | sc->tx_chan_width = ATH9K_HT_MACMODE_2040; |
8feceb67 | 833 | else |
99405f93 | 834 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; |
f078f209 | 835 | |
99405f93 S |
836 | ath9k_hw_set11nmac2040(sc->sc_ah, sc->tx_chan_width); |
837 | ||
838 | DPRINTF(sc, ATH_DBG_CONFIG, | |
04bd4638 | 839 | "BSS Changed HT, chanwidth: %d\n", sc->tx_chan_width); |
f078f209 | 840 | } |
f078f209 LR |
841 | } |
842 | ||
e11602b7 S |
843 | static inline int ath_sec_offset(u8 ext_offset) |
844 | { | |
845 | if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) | |
846 | return 0; | |
847 | else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) | |
848 | return 1; | |
849 | else if (ext_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) | |
850 | return -1; | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
8feceb67 | 855 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 856 | struct ieee80211_vif *vif, |
8feceb67 | 857 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 858 | { |
8feceb67 VT |
859 | struct ieee80211_hw *hw = sc->hw; |
860 | struct ieee80211_channel *curchan = hw->conf.channel; | |
5640b08e | 861 | struct ath_vap *avp = (void *)vif->drv_priv; |
8feceb67 | 862 | int pos; |
f078f209 | 863 | |
8feceb67 | 864 | if (bss_conf->assoc) { |
04bd4638 | 865 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d\n", bss_conf->aid); |
f078f209 | 866 | |
8feceb67 | 867 | /* New association, store aid */ |
d97809db | 868 | if (avp->av_opmode == NL80211_IFTYPE_STATION) { |
8feceb67 VT |
869 | sc->sc_curaid = bss_conf->aid; |
870 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | |
871 | sc->sc_curaid); | |
872 | } | |
f078f209 | 873 | |
8feceb67 VT |
874 | /* Configure the beacon */ |
875 | ath_beacon_config(sc, 0); | |
876 | sc->sc_flags |= SC_OP_BEACONS; | |
f078f209 | 877 | |
8feceb67 VT |
878 | /* Reset rssi stats */ |
879 | sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; | |
880 | sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; | |
881 | sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; | |
882 | sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER; | |
f078f209 | 883 | |
8feceb67 | 884 | /* Update chainmask */ |
ae5eb026 | 885 | ath_update_chainmask(sc, hw->conf.ht.enabled); |
f078f209 | 886 | |
f078f209 | 887 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 | 888 | "bssid %pM aid 0x%x\n", |
e174961c | 889 | sc->sc_curbssid, sc->sc_curaid); |
f078f209 | 890 | |
8feceb67 VT |
891 | pos = ath_get_channel(sc, curchan); |
892 | if (pos == -1) { | |
893 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 894 | "Invalid channel: %d\n", curchan->center_freq); |
8feceb67 VT |
895 | return; |
896 | } | |
f078f209 | 897 | |
99405f93 | 898 | if (hw->conf.ht.enabled) { |
e11602b7 S |
899 | int offset = |
900 | ath_sec_offset(bss_conf->ht.secondary_channel_offset); | |
901 | sc->tx_chan_width = (bss_conf->ht.width_40_ok) ? | |
902 | ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20; | |
99405f93 | 903 | |
e11602b7 S |
904 | sc->sc_ah->ah_channels[pos].chanmode = |
905 | ath_get_extchanmode(sc, curchan, | |
906 | offset, sc->tx_chan_width); | |
99405f93 | 907 | } else { |
8feceb67 VT |
908 | sc->sc_ah->ah_channels[pos].chanmode = |
909 | (curchan->band == IEEE80211_BAND_2GHZ) ? | |
910 | CHANNEL_G : CHANNEL_A; | |
99405f93 | 911 | } |
f078f209 | 912 | |
8feceb67 VT |
913 | /* set h/w channel */ |
914 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) | |
04bd4638 S |
915 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel: %d\n", |
916 | curchan->center_freq); | |
917 | ||
6f255425 LR |
918 | /* Start ANI */ |
919 | mod_timer(&sc->sc_ani.timer, | |
920 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
921 | ||
8feceb67 | 922 | } else { |
04bd4638 | 923 | DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n"); |
8feceb67 | 924 | sc->sc_curaid = 0; |
f078f209 | 925 | } |
8feceb67 | 926 | } |
f078f209 | 927 | |
8feceb67 VT |
928 | /********************************/ |
929 | /* LED functions */ | |
930 | /********************************/ | |
f078f209 | 931 | |
8feceb67 VT |
932 | static void ath_led_brightness(struct led_classdev *led_cdev, |
933 | enum led_brightness brightness) | |
934 | { | |
935 | struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev); | |
936 | struct ath_softc *sc = led->sc; | |
f078f209 | 937 | |
8feceb67 VT |
938 | switch (brightness) { |
939 | case LED_OFF: | |
940 | if (led->led_type == ATH_LED_ASSOC || | |
941 | led->led_type == ATH_LED_RADIO) | |
942 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
943 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, | |
944 | (led->led_type == ATH_LED_RADIO) ? 1 : | |
945 | !!(sc->sc_flags & SC_OP_LED_ASSOCIATED)); | |
946 | break; | |
947 | case LED_FULL: | |
948 | if (led->led_type == ATH_LED_ASSOC) | |
949 | sc->sc_flags |= SC_OP_LED_ASSOCIATED; | |
950 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0); | |
951 | break; | |
952 | default: | |
953 | break; | |
f078f209 | 954 | } |
8feceb67 | 955 | } |
f078f209 | 956 | |
8feceb67 VT |
957 | static int ath_register_led(struct ath_softc *sc, struct ath_led *led, |
958 | char *trigger) | |
959 | { | |
960 | int ret; | |
f078f209 | 961 | |
8feceb67 VT |
962 | led->sc = sc; |
963 | led->led_cdev.name = led->name; | |
964 | led->led_cdev.default_trigger = trigger; | |
965 | led->led_cdev.brightness_set = ath_led_brightness; | |
f078f209 | 966 | |
8feceb67 VT |
967 | ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); |
968 | if (ret) | |
969 | DPRINTF(sc, ATH_DBG_FATAL, | |
970 | "Failed to register led:%s", led->name); | |
971 | else | |
972 | led->registered = 1; | |
973 | return ret; | |
974 | } | |
f078f209 | 975 | |
8feceb67 VT |
976 | static void ath_unregister_led(struct ath_led *led) |
977 | { | |
978 | if (led->registered) { | |
979 | led_classdev_unregister(&led->led_cdev); | |
980 | led->registered = 0; | |
f078f209 | 981 | } |
f078f209 LR |
982 | } |
983 | ||
8feceb67 | 984 | static void ath_deinit_leds(struct ath_softc *sc) |
f078f209 | 985 | { |
8feceb67 VT |
986 | ath_unregister_led(&sc->assoc_led); |
987 | sc->sc_flags &= ~SC_OP_LED_ASSOCIATED; | |
988 | ath_unregister_led(&sc->tx_led); | |
989 | ath_unregister_led(&sc->rx_led); | |
990 | ath_unregister_led(&sc->radio_led); | |
991 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
992 | } | |
f078f209 | 993 | |
8feceb67 VT |
994 | static void ath_init_leds(struct ath_softc *sc) |
995 | { | |
996 | char *trigger; | |
997 | int ret; | |
f078f209 | 998 | |
8feceb67 VT |
999 | /* Configure gpio 1 for output */ |
1000 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
1001 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1002 | /* LED off, active low */ | |
1003 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
7dcfdcd9 | 1004 | |
8feceb67 VT |
1005 | trigger = ieee80211_get_radio_led_name(sc->hw); |
1006 | snprintf(sc->radio_led.name, sizeof(sc->radio_led.name), | |
1007 | "ath9k-%s:radio", wiphy_name(sc->hw->wiphy)); | |
1008 | ret = ath_register_led(sc, &sc->radio_led, trigger); | |
1009 | sc->radio_led.led_type = ATH_LED_RADIO; | |
1010 | if (ret) | |
1011 | goto fail; | |
7dcfdcd9 | 1012 | |
8feceb67 VT |
1013 | trigger = ieee80211_get_assoc_led_name(sc->hw); |
1014 | snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name), | |
1015 | "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy)); | |
1016 | ret = ath_register_led(sc, &sc->assoc_led, trigger); | |
1017 | sc->assoc_led.led_type = ATH_LED_ASSOC; | |
1018 | if (ret) | |
1019 | goto fail; | |
f078f209 | 1020 | |
8feceb67 VT |
1021 | trigger = ieee80211_get_tx_led_name(sc->hw); |
1022 | snprintf(sc->tx_led.name, sizeof(sc->tx_led.name), | |
1023 | "ath9k-%s:tx", wiphy_name(sc->hw->wiphy)); | |
1024 | ret = ath_register_led(sc, &sc->tx_led, trigger); | |
1025 | sc->tx_led.led_type = ATH_LED_TX; | |
1026 | if (ret) | |
1027 | goto fail; | |
f078f209 | 1028 | |
8feceb67 VT |
1029 | trigger = ieee80211_get_rx_led_name(sc->hw); |
1030 | snprintf(sc->rx_led.name, sizeof(sc->rx_led.name), | |
1031 | "ath9k-%s:rx", wiphy_name(sc->hw->wiphy)); | |
1032 | ret = ath_register_led(sc, &sc->rx_led, trigger); | |
1033 | sc->rx_led.led_type = ATH_LED_RX; | |
1034 | if (ret) | |
1035 | goto fail; | |
f078f209 | 1036 | |
8feceb67 VT |
1037 | return; |
1038 | ||
1039 | fail: | |
1040 | ath_deinit_leds(sc); | |
f078f209 LR |
1041 | } |
1042 | ||
e97275cb | 1043 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
9c84b797 | 1044 | |
500c064d VT |
1045 | /*******************/ |
1046 | /* Rfkill */ | |
1047 | /*******************/ | |
1048 | ||
1049 | static void ath_radio_enable(struct ath_softc *sc) | |
1050 | { | |
1051 | struct ath_hal *ah = sc->sc_ah; | |
1052 | int status; | |
1053 | ||
1054 | spin_lock_bh(&sc->sc_resetlock); | |
1055 | if (!ath9k_hw_reset(ah, ah->ah_curchan, | |
99405f93 | 1056 | sc->tx_chan_width, |
500c064d VT |
1057 | sc->sc_tx_chainmask, |
1058 | sc->sc_rx_chainmask, | |
1059 | sc->sc_ht_extprotspacing, | |
1060 | false, &status)) { | |
1061 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 S |
1062 | "Unable to reset channel %u (%uMhz) " |
1063 | "flags 0x%x hal status %u\n", | |
500c064d VT |
1064 | ath9k_hw_mhz2ieee(ah, |
1065 | ah->ah_curchan->channel, | |
1066 | ah->ah_curchan->channelFlags), | |
1067 | ah->ah_curchan->channel, | |
1068 | ah->ah_curchan->channelFlags, status); | |
1069 | } | |
1070 | spin_unlock_bh(&sc->sc_resetlock); | |
1071 | ||
1072 | ath_update_txpow(sc); | |
1073 | if (ath_startrecv(sc) != 0) { | |
1074 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1075 | "Unable to restart recv logic\n"); |
500c064d VT |
1076 | return; |
1077 | } | |
1078 | ||
1079 | if (sc->sc_flags & SC_OP_BEACONS) | |
1080 | ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ | |
1081 | ||
1082 | /* Re-Enable interrupts */ | |
1083 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
1084 | ||
1085 | /* Enable LED */ | |
1086 | ath9k_hw_cfg_output(ah, ATH_LED_PIN, | |
1087 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
1088 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0); | |
1089 | ||
1090 | ieee80211_wake_queues(sc->hw); | |
1091 | } | |
1092 | ||
1093 | static void ath_radio_disable(struct ath_softc *sc) | |
1094 | { | |
1095 | struct ath_hal *ah = sc->sc_ah; | |
1096 | int status; | |
1097 | ||
1098 | ||
1099 | ieee80211_stop_queues(sc->hw); | |
1100 | ||
1101 | /* Disable LED */ | |
1102 | ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1); | |
1103 | ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN); | |
1104 | ||
1105 | /* Disable interrupts */ | |
1106 | ath9k_hw_set_interrupts(ah, 0); | |
1107 | ||
1108 | ath_draintxq(sc, false); /* clear pending tx frames */ | |
1109 | ath_stoprecv(sc); /* turn off frame recv */ | |
1110 | ath_flushrecv(sc); /* flush recv queue */ | |
1111 | ||
1112 | spin_lock_bh(&sc->sc_resetlock); | |
1113 | if (!ath9k_hw_reset(ah, ah->ah_curchan, | |
99405f93 | 1114 | sc->tx_chan_width, |
500c064d VT |
1115 | sc->sc_tx_chainmask, |
1116 | sc->sc_rx_chainmask, | |
1117 | sc->sc_ht_extprotspacing, | |
1118 | false, &status)) { | |
1119 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 S |
1120 | "Unable to reset channel %u (%uMhz) " |
1121 | "flags 0x%x hal status %u\n", | |
500c064d VT |
1122 | ath9k_hw_mhz2ieee(ah, |
1123 | ah->ah_curchan->channel, | |
1124 | ah->ah_curchan->channelFlags), | |
1125 | ah->ah_curchan->channel, | |
1126 | ah->ah_curchan->channelFlags, status); | |
1127 | } | |
1128 | spin_unlock_bh(&sc->sc_resetlock); | |
1129 | ||
1130 | ath9k_hw_phy_disable(ah); | |
1131 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); | |
1132 | } | |
1133 | ||
1134 | static bool ath_is_rfkill_set(struct ath_softc *sc) | |
1135 | { | |
1136 | struct ath_hal *ah = sc->sc_ah; | |
1137 | ||
1138 | return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) == | |
1139 | ah->ah_rfkill_polarity; | |
1140 | } | |
1141 | ||
1142 | /* h/w rfkill poll function */ | |
1143 | static void ath_rfkill_poll(struct work_struct *work) | |
1144 | { | |
1145 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
1146 | rf_kill.rfkill_poll.work); | |
1147 | bool radio_on; | |
1148 | ||
1149 | if (sc->sc_flags & SC_OP_INVALID) | |
1150 | return; | |
1151 | ||
1152 | radio_on = !ath_is_rfkill_set(sc); | |
1153 | ||
1154 | /* | |
1155 | * enable/disable radio only when there is a | |
1156 | * state change in RF switch | |
1157 | */ | |
1158 | if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) { | |
1159 | enum rfkill_state state; | |
1160 | ||
1161 | if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) { | |
1162 | state = radio_on ? RFKILL_STATE_SOFT_BLOCKED | |
1163 | : RFKILL_STATE_HARD_BLOCKED; | |
1164 | } else if (radio_on) { | |
1165 | ath_radio_enable(sc); | |
1166 | state = RFKILL_STATE_UNBLOCKED; | |
1167 | } else { | |
1168 | ath_radio_disable(sc); | |
1169 | state = RFKILL_STATE_HARD_BLOCKED; | |
1170 | } | |
1171 | ||
1172 | if (state == RFKILL_STATE_HARD_BLOCKED) | |
1173 | sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED; | |
1174 | else | |
1175 | sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED; | |
1176 | ||
1177 | rfkill_force_state(sc->rf_kill.rfkill, state); | |
1178 | } | |
1179 | ||
1180 | queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll, | |
1181 | msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL)); | |
1182 | } | |
1183 | ||
1184 | /* s/w rfkill handler */ | |
1185 | static int ath_sw_toggle_radio(void *data, enum rfkill_state state) | |
1186 | { | |
1187 | struct ath_softc *sc = data; | |
1188 | ||
1189 | switch (state) { | |
1190 | case RFKILL_STATE_SOFT_BLOCKED: | |
1191 | if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED | | |
1192 | SC_OP_RFKILL_SW_BLOCKED))) | |
1193 | ath_radio_disable(sc); | |
1194 | sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED; | |
1195 | return 0; | |
1196 | case RFKILL_STATE_UNBLOCKED: | |
1197 | if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) { | |
1198 | sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED; | |
1199 | if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) { | |
1200 | DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the" | |
04bd4638 | 1201 | "radio as it is disabled by h/w\n"); |
500c064d VT |
1202 | return -EPERM; |
1203 | } | |
1204 | ath_radio_enable(sc); | |
1205 | } | |
1206 | return 0; | |
1207 | default: | |
1208 | return -EINVAL; | |
1209 | } | |
1210 | } | |
1211 | ||
1212 | /* Init s/w rfkill */ | |
1213 | static int ath_init_sw_rfkill(struct ath_softc *sc) | |
1214 | { | |
1215 | sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy), | |
1216 | RFKILL_TYPE_WLAN); | |
1217 | if (!sc->rf_kill.rfkill) { | |
1218 | DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n"); | |
1219 | return -ENOMEM; | |
1220 | } | |
1221 | ||
1222 | snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name), | |
1223 | "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy)); | |
1224 | sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name; | |
1225 | sc->rf_kill.rfkill->data = sc; | |
1226 | sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio; | |
1227 | sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED; | |
1228 | sc->rf_kill.rfkill->user_claim_unsupported = 1; | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | /* Deinitialize rfkill */ | |
1234 | static void ath_deinit_rfkill(struct ath_softc *sc) | |
1235 | { | |
1236 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
1237 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
1238 | ||
1239 | if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) { | |
1240 | rfkill_unregister(sc->rf_kill.rfkill); | |
1241 | sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED; | |
1242 | sc->rf_kill.rfkill = NULL; | |
1243 | } | |
1244 | } | |
9c84b797 S |
1245 | |
1246 | static int ath_start_rfkill_poll(struct ath_softc *sc) | |
1247 | { | |
1248 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
1249 | queue_delayed_work(sc->hw->workqueue, | |
1250 | &sc->rf_kill.rfkill_poll, 0); | |
1251 | ||
1252 | if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) { | |
1253 | if (rfkill_register(sc->rf_kill.rfkill)) { | |
1254 | DPRINTF(sc, ATH_DBG_FATAL, | |
1255 | "Unable to register rfkill\n"); | |
1256 | rfkill_free(sc->rf_kill.rfkill); | |
1257 | ||
1258 | /* Deinitialize the device */ | |
306efdd1 | 1259 | ath_detach(sc); |
9c84b797 S |
1260 | if (sc->pdev->irq) |
1261 | free_irq(sc->pdev->irq, sc); | |
9c84b797 S |
1262 | pci_iounmap(sc->pdev, sc->mem); |
1263 | pci_release_region(sc->pdev, 0); | |
1264 | pci_disable_device(sc->pdev); | |
9757d556 | 1265 | ieee80211_free_hw(sc->hw); |
9c84b797 S |
1266 | return -EIO; |
1267 | } else { | |
1268 | sc->sc_flags |= SC_OP_RFKILL_REGISTERED; | |
1269 | } | |
1270 | } | |
1271 | ||
1272 | return 0; | |
1273 | } | |
500c064d VT |
1274 | #endif /* CONFIG_RFKILL */ |
1275 | ||
9c84b797 | 1276 | static void ath_detach(struct ath_softc *sc) |
f078f209 | 1277 | { |
8feceb67 | 1278 | struct ieee80211_hw *hw = sc->hw; |
9c84b797 | 1279 | int i = 0; |
f078f209 | 1280 | |
04bd4638 | 1281 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n"); |
f078f209 | 1282 | |
e97275cb | 1283 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
1284 | ath_deinit_rfkill(sc); |
1285 | #endif | |
3fcdfb4b VT |
1286 | ath_deinit_leds(sc); |
1287 | ||
1288 | ieee80211_unregister_hw(hw); | |
1289 | ||
8feceb67 | 1290 | ath_rate_control_unregister(); |
f078f209 | 1291 | |
8feceb67 VT |
1292 | ath_rx_cleanup(sc); |
1293 | ath_tx_cleanup(sc); | |
f078f209 | 1294 | |
9c84b797 S |
1295 | tasklet_kill(&sc->intr_tq); |
1296 | tasklet_kill(&sc->bcon_tasklet); | |
f078f209 | 1297 | |
9c84b797 S |
1298 | if (!(sc->sc_flags & SC_OP_INVALID)) |
1299 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); | |
8feceb67 | 1300 | |
9c84b797 S |
1301 | /* cleanup tx queues */ |
1302 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1303 | if (ATH_TXQ_SETUP(sc, i)) | |
1304 | ath_tx_cleanupq(sc, &sc->sc_txq[i]); | |
1305 | ||
1306 | ath9k_hw_detach(sc->sc_ah); | |
826d2680 | 1307 | ath9k_exit_debug(sc); |
f078f209 LR |
1308 | } |
1309 | ||
ff37e337 S |
1310 | static int ath_init(u16 devid, struct ath_softc *sc) |
1311 | { | |
1312 | struct ath_hal *ah = NULL; | |
1313 | int status; | |
1314 | int error = 0, i; | |
1315 | int csz = 0; | |
1316 | ||
1317 | /* XXX: hardware will not be ready until ath_open() being called */ | |
1318 | sc->sc_flags |= SC_OP_INVALID; | |
88b126af | 1319 | |
826d2680 S |
1320 | if (ath9k_init_debug(sc) < 0) |
1321 | printk(KERN_ERR "Unable to create debugfs files\n"); | |
ff37e337 S |
1322 | |
1323 | spin_lock_init(&sc->sc_resetlock); | |
1324 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | |
1325 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, | |
1326 | (unsigned long)sc); | |
1327 | ||
1328 | /* | |
1329 | * Cache line size is used to size and align various | |
1330 | * structures used to communicate with the hardware. | |
1331 | */ | |
1332 | bus_read_cachesize(sc, &csz); | |
1333 | /* XXX assert csz is non-zero */ | |
1334 | sc->sc_cachelsz = csz << 2; /* convert to bytes */ | |
1335 | ||
1336 | ah = ath9k_hw_attach(devid, sc, sc->mem, &status); | |
1337 | if (ah == NULL) { | |
1338 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1339 | "Unable to attach hardware; HAL status %u\n", status); |
ff37e337 S |
1340 | error = -ENXIO; |
1341 | goto bad; | |
1342 | } | |
1343 | sc->sc_ah = ah; | |
1344 | ||
1345 | /* Get the hardware key cache size. */ | |
1346 | sc->sc_keymax = ah->ah_caps.keycache_size; | |
1347 | if (sc->sc_keymax > ATH_KEYMAX) { | |
1348 | DPRINTF(sc, ATH_DBG_KEYCACHE, | |
04bd4638 S |
1349 | "Warning, using only %u entries in %u key cache\n", |
1350 | ATH_KEYMAX, sc->sc_keymax); | |
ff37e337 S |
1351 | sc->sc_keymax = ATH_KEYMAX; |
1352 | } | |
1353 | ||
1354 | /* | |
1355 | * Reset the key cache since some parts do not | |
1356 | * reset the contents on initial power up. | |
1357 | */ | |
1358 | for (i = 0; i < sc->sc_keymax; i++) | |
1359 | ath9k_hw_keyreset(ah, (u16) i); | |
1360 | /* | |
1361 | * Mark key cache slots associated with global keys | |
1362 | * as in use. If we knew TKIP was not to be used we | |
1363 | * could leave the +32, +64, and +32+64 slots free. | |
1364 | * XXX only for splitmic. | |
1365 | */ | |
1366 | for (i = 0; i < IEEE80211_WEP_NKID; i++) { | |
1367 | set_bit(i, sc->sc_keymap); | |
1368 | set_bit(i + 32, sc->sc_keymap); | |
1369 | set_bit(i + 64, sc->sc_keymap); | |
1370 | set_bit(i + 32 + 64, sc->sc_keymap); | |
1371 | } | |
1372 | ||
1373 | /* Collect the channel list using the default country code */ | |
1374 | ||
1375 | error = ath_setup_channels(sc); | |
1376 | if (error) | |
1377 | goto bad; | |
1378 | ||
1379 | /* default to MONITOR mode */ | |
d97809db CM |
1380 | sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR; |
1381 | ||
ff37e337 S |
1382 | |
1383 | /* Setup rate tables */ | |
1384 | ||
1385 | ath_rate_attach(sc); | |
1386 | ath_setup_rates(sc, IEEE80211_BAND_2GHZ); | |
1387 | ath_setup_rates(sc, IEEE80211_BAND_5GHZ); | |
1388 | ||
1389 | /* | |
1390 | * Allocate hardware transmit queues: one queue for | |
1391 | * beacon frames and one data queue for each QoS | |
1392 | * priority. Note that the hal handles reseting | |
1393 | * these queues at the needed time. | |
1394 | */ | |
1395 | sc->sc_bhalq = ath_beaconq_setup(ah); | |
1396 | if (sc->sc_bhalq == -1) { | |
1397 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1398 | "Unable to setup a beacon xmit queue\n"); |
ff37e337 S |
1399 | error = -EIO; |
1400 | goto bad2; | |
1401 | } | |
1402 | sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); | |
1403 | if (sc->sc_cabq == NULL) { | |
1404 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1405 | "Unable to setup CAB xmit queue\n"); |
ff37e337 S |
1406 | error = -EIO; |
1407 | goto bad2; | |
1408 | } | |
1409 | ||
1410 | sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME; | |
1411 | ath_cabq_update(sc); | |
1412 | ||
1413 | for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++) | |
1414 | sc->sc_haltype2q[i] = -1; | |
1415 | ||
1416 | /* Setup data queues */ | |
1417 | /* NB: ensure BK queue is the lowest priority h/w queue */ | |
1418 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { | |
1419 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1420 | "Unable to setup xmit queue for BK traffic\n"); |
ff37e337 S |
1421 | error = -EIO; |
1422 | goto bad2; | |
1423 | } | |
1424 | ||
1425 | if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { | |
1426 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1427 | "Unable to setup xmit queue for BE traffic\n"); |
ff37e337 S |
1428 | error = -EIO; |
1429 | goto bad2; | |
1430 | } | |
1431 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { | |
1432 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1433 | "Unable to setup xmit queue for VI traffic\n"); |
ff37e337 S |
1434 | error = -EIO; |
1435 | goto bad2; | |
1436 | } | |
1437 | if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { | |
1438 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1439 | "Unable to setup xmit queue for VO traffic\n"); |
ff37e337 S |
1440 | error = -EIO; |
1441 | goto bad2; | |
1442 | } | |
1443 | ||
1444 | /* Initializes the noise floor to a reasonable default value. | |
1445 | * Later on this will be updated during ANI processing. */ | |
1446 | ||
1447 | sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR; | |
1448 | setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc); | |
1449 | ||
1450 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1451 | ATH9K_CIPHER_TKIP, NULL)) { | |
1452 | /* | |
1453 | * Whether we should enable h/w TKIP MIC. | |
1454 | * XXX: if we don't support WME TKIP MIC, then we wouldn't | |
1455 | * report WMM capable, so it's always safe to turn on | |
1456 | * TKIP MIC in this case. | |
1457 | */ | |
1458 | ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC, | |
1459 | 0, 1, NULL); | |
1460 | } | |
1461 | ||
1462 | /* | |
1463 | * Check whether the separate key cache entries | |
1464 | * are required to handle both tx+rx MIC keys. | |
1465 | * With split mic keys the number of stations is limited | |
1466 | * to 27 otherwise 59. | |
1467 | */ | |
1468 | if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1469 | ATH9K_CIPHER_TKIP, NULL) | |
1470 | && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER, | |
1471 | ATH9K_CIPHER_MIC, NULL) | |
1472 | && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT, | |
1473 | 0, NULL)) | |
1474 | sc->sc_splitmic = 1; | |
1475 | ||
1476 | /* turn on mcast key search if possible */ | |
1477 | if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL)) | |
1478 | (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1, | |
1479 | 1, NULL); | |
1480 | ||
1481 | sc->sc_config.txpowlimit = ATH_TXPOWER_MAX; | |
1482 | sc->sc_config.txpowlimit_override = 0; | |
1483 | ||
1484 | /* 11n Capabilities */ | |
1485 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { | |
1486 | sc->sc_flags |= SC_OP_TXAGGR; | |
1487 | sc->sc_flags |= SC_OP_RXAGGR; | |
1488 | } | |
1489 | ||
1490 | sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask; | |
1491 | sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask; | |
1492 | ||
1493 | ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); | |
1494 | sc->sc_defant = ath9k_hw_getdefantenna(ah); | |
1495 | ||
1496 | ath9k_hw_getmac(ah, sc->sc_myaddr); | |
1497 | if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) { | |
1498 | ath9k_hw_getbssidmask(ah, sc->sc_bssidmask); | |
1499 | ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask); | |
1500 | ath9k_hw_setbssidmask(ah, sc->sc_bssidmask); | |
1501 | } | |
1502 | ||
1503 | sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */ | |
1504 | ||
1505 | /* initialize beacon slots */ | |
1506 | for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++) | |
1507 | sc->sc_bslot[i] = ATH_IF_ID_ANY; | |
1508 | ||
1509 | /* save MISC configurations */ | |
1510 | sc->sc_config.swBeaconProcess = 1; | |
1511 | ||
1512 | #ifdef CONFIG_SLOW_ANT_DIV | |
1513 | /* range is 40 - 255, we use something in the middle */ | |
1514 | ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127); | |
1515 | #endif | |
1516 | ||
1517 | /* setup channels and rates */ | |
1518 | ||
1519 | sc->sbands[IEEE80211_BAND_2GHZ].channels = | |
1520 | sc->channels[IEEE80211_BAND_2GHZ]; | |
1521 | sc->sbands[IEEE80211_BAND_2GHZ].bitrates = | |
1522 | sc->rates[IEEE80211_BAND_2GHZ]; | |
1523 | sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; | |
1524 | ||
1525 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) { | |
1526 | sc->sbands[IEEE80211_BAND_5GHZ].channels = | |
1527 | sc->channels[IEEE80211_BAND_5GHZ]; | |
1528 | sc->sbands[IEEE80211_BAND_5GHZ].bitrates = | |
1529 | sc->rates[IEEE80211_BAND_5GHZ]; | |
1530 | sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; | |
1531 | } | |
1532 | ||
1533 | return 0; | |
1534 | bad2: | |
1535 | /* cleanup tx queues */ | |
1536 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
1537 | if (ATH_TXQ_SETUP(sc, i)) | |
1538 | ath_tx_cleanupq(sc, &sc->sc_txq[i]); | |
1539 | bad: | |
1540 | if (ah) | |
1541 | ath9k_hw_detach(ah); | |
1542 | ||
1543 | return error; | |
1544 | } | |
1545 | ||
9c84b797 | 1546 | static int ath_attach(u16 devid, struct ath_softc *sc) |
f078f209 | 1547 | { |
8feceb67 VT |
1548 | struct ieee80211_hw *hw = sc->hw; |
1549 | int error = 0; | |
f078f209 | 1550 | |
04bd4638 | 1551 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n"); |
f078f209 | 1552 | |
8feceb67 VT |
1553 | error = ath_init(devid, sc); |
1554 | if (error != 0) | |
1555 | return error; | |
f078f209 | 1556 | |
8feceb67 | 1557 | /* get mac address from hardware and set in mac80211 */ |
f078f209 | 1558 | |
8feceb67 | 1559 | SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr); |
f078f209 | 1560 | |
9c84b797 S |
1561 | hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | |
1562 | IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | | |
1563 | IEEE80211_HW_SIGNAL_DBM | | |
1564 | IEEE80211_HW_AMPDU_AGGREGATION; | |
f078f209 | 1565 | |
9c84b797 S |
1566 | hw->wiphy->interface_modes = |
1567 | BIT(NL80211_IFTYPE_AP) | | |
1568 | BIT(NL80211_IFTYPE_STATION) | | |
1569 | BIT(NL80211_IFTYPE_ADHOC); | |
f078f209 | 1570 | |
8feceb67 | 1571 | hw->queues = 4; |
e63835b0 S |
1572 | hw->max_rates = 4; |
1573 | hw->max_rate_tries = ATH_11N_TXMAXTRY; | |
528f0c6b | 1574 | hw->sta_data_size = sizeof(struct ath_node); |
5640b08e | 1575 | hw->vif_data_size = sizeof(struct ath_vap); |
f078f209 | 1576 | |
8feceb67 VT |
1577 | /* Register rate control */ |
1578 | hw->rate_control_algorithm = "ath9k_rate_control"; | |
1579 | error = ath_rate_control_register(); | |
1580 | if (error != 0) { | |
1581 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1582 | "Unable to register rate control algorithm: %d\n", error); |
8feceb67 VT |
1583 | ath_rate_control_unregister(); |
1584 | goto bad; | |
1585 | } | |
f078f209 | 1586 | |
9c84b797 S |
1587 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) { |
1588 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); | |
1589 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) | |
1590 | setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); | |
1591 | } | |
1592 | ||
1593 | hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ]; | |
1594 | if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) | |
1595 | hw->wiphy->bands[IEEE80211_BAND_5GHZ] = | |
1596 | &sc->sbands[IEEE80211_BAND_5GHZ]; | |
1597 | ||
db93e7b5 SB |
1598 | /* initialize tx/rx engine */ |
1599 | error = ath_tx_init(sc, ATH_TXBUF); | |
1600 | if (error != 0) | |
1601 | goto detach; | |
8feceb67 | 1602 | |
db93e7b5 SB |
1603 | error = ath_rx_init(sc, ATH_RXBUF); |
1604 | if (error != 0) | |
1605 | goto detach; | |
8feceb67 | 1606 | |
e97275cb | 1607 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
1608 | /* Initialze h/w Rfkill */ |
1609 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
1610 | INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll); | |
1611 | ||
1612 | /* Initialize s/w rfkill */ | |
1613 | if (ath_init_sw_rfkill(sc)) | |
1614 | goto detach; | |
1615 | #endif | |
1616 | ||
db93e7b5 SB |
1617 | error = ieee80211_register_hw(hw); |
1618 | if (error != 0) { | |
1619 | ath_rate_control_unregister(); | |
1620 | goto bad; | |
1621 | } | |
8feceb67 | 1622 | |
db93e7b5 SB |
1623 | /* Initialize LED control */ |
1624 | ath_init_leds(sc); | |
8feceb67 VT |
1625 | |
1626 | return 0; | |
1627 | detach: | |
1628 | ath_detach(sc); | |
1629 | bad: | |
1630 | return error; | |
f078f209 LR |
1631 | } |
1632 | ||
ff37e337 S |
1633 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
1634 | { | |
1635 | struct ath_hal *ah = sc->sc_ah; | |
1636 | int status; | |
1637 | int error = 0; | |
1638 | ||
1639 | ath9k_hw_set_interrupts(ah, 0); | |
1640 | ath_draintxq(sc, retry_tx); | |
1641 | ath_stoprecv(sc); | |
1642 | ath_flushrecv(sc); | |
1643 | ||
1644 | spin_lock_bh(&sc->sc_resetlock); | |
1645 | if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, | |
99405f93 | 1646 | sc->tx_chan_width, |
ff37e337 S |
1647 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, |
1648 | sc->sc_ht_extprotspacing, false, &status)) { | |
1649 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 1650 | "Unable to reset hardware; hal status %u\n", status); |
ff37e337 S |
1651 | error = -EIO; |
1652 | } | |
1653 | spin_unlock_bh(&sc->sc_resetlock); | |
1654 | ||
1655 | if (ath_startrecv(sc) != 0) | |
04bd4638 | 1656 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); |
ff37e337 S |
1657 | |
1658 | /* | |
1659 | * We may be doing a reset in response to a request | |
1660 | * that changes the channel so update any state that | |
1661 | * might change as a result. | |
1662 | */ | |
1663 | ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan)); | |
1664 | ||
1665 | ath_update_txpow(sc); | |
1666 | ||
1667 | if (sc->sc_flags & SC_OP_BEACONS) | |
1668 | ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */ | |
1669 | ||
1670 | ath9k_hw_set_interrupts(ah, sc->sc_imask); | |
1671 | ||
1672 | if (retry_tx) { | |
1673 | int i; | |
1674 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1675 | if (ATH_TXQ_SETUP(sc, i)) { | |
1676 | spin_lock_bh(&sc->sc_txq[i].axq_lock); | |
1677 | ath_txq_schedule(sc, &sc->sc_txq[i]); | |
1678 | spin_unlock_bh(&sc->sc_txq[i].axq_lock); | |
1679 | } | |
1680 | } | |
1681 | } | |
1682 | ||
1683 | return error; | |
1684 | } | |
1685 | ||
1686 | /* | |
1687 | * This function will allocate both the DMA descriptor structure, and the | |
1688 | * buffers it contains. These are used to contain the descriptors used | |
1689 | * by the system. | |
1690 | */ | |
1691 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
1692 | struct list_head *head, const char *name, | |
1693 | int nbuf, int ndesc) | |
1694 | { | |
1695 | #define DS2PHYS(_dd, _ds) \ | |
1696 | ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) | |
1697 | #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0) | |
1698 | #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096) | |
1699 | ||
1700 | struct ath_desc *ds; | |
1701 | struct ath_buf *bf; | |
1702 | int i, bsize, error; | |
1703 | ||
04bd4638 S |
1704 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", |
1705 | name, nbuf, ndesc); | |
ff37e337 S |
1706 | |
1707 | /* ath_desc must be a multiple of DWORDs */ | |
1708 | if ((sizeof(struct ath_desc) % 4) != 0) { | |
04bd4638 | 1709 | DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); |
ff37e337 S |
1710 | ASSERT((sizeof(struct ath_desc) % 4) == 0); |
1711 | error = -ENOMEM; | |
1712 | goto fail; | |
1713 | } | |
1714 | ||
1715 | dd->dd_name = name; | |
1716 | dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; | |
1717 | ||
1718 | /* | |
1719 | * Need additional DMA memory because we can't use | |
1720 | * descriptors that cross the 4K page boundary. Assume | |
1721 | * one skipped descriptor per 4K page. | |
1722 | */ | |
1723 | if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
1724 | u32 ndesc_skipped = | |
1725 | ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len); | |
1726 | u32 dma_len; | |
1727 | ||
1728 | while (ndesc_skipped) { | |
1729 | dma_len = ndesc_skipped * sizeof(struct ath_desc); | |
1730 | dd->dd_desc_len += dma_len; | |
1731 | ||
1732 | ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len); | |
1733 | }; | |
1734 | } | |
1735 | ||
1736 | /* allocate descriptors */ | |
1737 | dd->dd_desc = pci_alloc_consistent(sc->pdev, | |
1738 | dd->dd_desc_len, | |
1739 | &dd->dd_desc_paddr); | |
1740 | if (dd->dd_desc == NULL) { | |
1741 | error = -ENOMEM; | |
1742 | goto fail; | |
1743 | } | |
1744 | ds = dd->dd_desc; | |
04bd4638 S |
1745 | DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", |
1746 | dd->dd_name, ds, (u32) dd->dd_desc_len, | |
ff37e337 S |
1747 | ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); |
1748 | ||
1749 | /* allocate buffers */ | |
1750 | bsize = sizeof(struct ath_buf) * nbuf; | |
1751 | bf = kmalloc(bsize, GFP_KERNEL); | |
1752 | if (bf == NULL) { | |
1753 | error = -ENOMEM; | |
1754 | goto fail2; | |
1755 | } | |
1756 | memset(bf, 0, bsize); | |
1757 | dd->dd_bufptr = bf; | |
1758 | ||
1759 | INIT_LIST_HEAD(head); | |
1760 | for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { | |
1761 | bf->bf_desc = ds; | |
1762 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1763 | ||
1764 | if (!(sc->sc_ah->ah_caps.hw_caps & | |
1765 | ATH9K_HW_CAP_4KB_SPLITTRANS)) { | |
1766 | /* | |
1767 | * Skip descriptor addresses which can cause 4KB | |
1768 | * boundary crossing (addr + length) with a 32 dword | |
1769 | * descriptor fetch. | |
1770 | */ | |
1771 | while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) { | |
1772 | ASSERT((caddr_t) bf->bf_desc < | |
1773 | ((caddr_t) dd->dd_desc + | |
1774 | dd->dd_desc_len)); | |
1775 | ||
1776 | ds += ndesc; | |
1777 | bf->bf_desc = ds; | |
1778 | bf->bf_daddr = DS2PHYS(dd, ds); | |
1779 | } | |
1780 | } | |
1781 | list_add_tail(&bf->list, head); | |
1782 | } | |
1783 | return 0; | |
1784 | fail2: | |
1785 | pci_free_consistent(sc->pdev, | |
1786 | dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr); | |
1787 | fail: | |
1788 | memset(dd, 0, sizeof(*dd)); | |
1789 | return error; | |
1790 | #undef ATH_DESC_4KB_BOUND_CHECK | |
1791 | #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED | |
1792 | #undef DS2PHYS | |
1793 | } | |
1794 | ||
1795 | void ath_descdma_cleanup(struct ath_softc *sc, | |
1796 | struct ath_descdma *dd, | |
1797 | struct list_head *head) | |
1798 | { | |
1799 | pci_free_consistent(sc->pdev, | |
1800 | dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr); | |
1801 | ||
1802 | INIT_LIST_HEAD(head); | |
1803 | kfree(dd->dd_bufptr); | |
1804 | memset(dd, 0, sizeof(*dd)); | |
1805 | } | |
1806 | ||
1807 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) | |
1808 | { | |
1809 | int qnum; | |
1810 | ||
1811 | switch (queue) { | |
1812 | case 0: | |
1813 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO]; | |
1814 | break; | |
1815 | case 1: | |
1816 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI]; | |
1817 | break; | |
1818 | case 2: | |
1819 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; | |
1820 | break; | |
1821 | case 3: | |
1822 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK]; | |
1823 | break; | |
1824 | default: | |
1825 | qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE]; | |
1826 | break; | |
1827 | } | |
1828 | ||
1829 | return qnum; | |
1830 | } | |
1831 | ||
1832 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1833 | { | |
1834 | int qnum; | |
1835 | ||
1836 | switch (queue) { | |
1837 | case ATH9K_WME_AC_VO: | |
1838 | qnum = 0; | |
1839 | break; | |
1840 | case ATH9K_WME_AC_VI: | |
1841 | qnum = 1; | |
1842 | break; | |
1843 | case ATH9K_WME_AC_BE: | |
1844 | qnum = 2; | |
1845 | break; | |
1846 | case ATH9K_WME_AC_BK: | |
1847 | qnum = 3; | |
1848 | break; | |
1849 | default: | |
1850 | qnum = -1; | |
1851 | break; | |
1852 | } | |
1853 | ||
1854 | return qnum; | |
1855 | } | |
1856 | ||
1857 | /**********************/ | |
1858 | /* mac80211 callbacks */ | |
1859 | /**********************/ | |
1860 | ||
8feceb67 | 1861 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 LR |
1862 | { |
1863 | struct ath_softc *sc = hw->priv; | |
8feceb67 | 1864 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 S |
1865 | struct ath9k_channel *init_channel; |
1866 | int error = 0, pos, status; | |
f078f209 | 1867 | |
04bd4638 S |
1868 | DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " |
1869 | "initial channel: %d MHz\n", curchan->center_freq); | |
f078f209 | 1870 | |
8feceb67 | 1871 | /* setup initial channel */ |
f078f209 | 1872 | |
8feceb67 VT |
1873 | pos = ath_get_channel(sc, curchan); |
1874 | if (pos == -1) { | |
04bd4638 | 1875 | DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq); |
9c84b797 | 1876 | error = -EINVAL; |
ff37e337 | 1877 | goto error; |
f078f209 LR |
1878 | } |
1879 | ||
99405f93 | 1880 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; |
8feceb67 VT |
1881 | sc->sc_ah->ah_channels[pos].chanmode = |
1882 | (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A; | |
ff37e337 S |
1883 | init_channel = &sc->sc_ah->ah_channels[pos]; |
1884 | ||
1885 | /* Reset SERDES registers */ | |
1886 | ath9k_hw_configpcipowersave(sc->sc_ah, 0); | |
1887 | ||
1888 | /* | |
1889 | * The basic interface to setting the hardware in a good | |
1890 | * state is ``reset''. On return the hardware is known to | |
1891 | * be powered up and with interrupts disabled. This must | |
1892 | * be followed by initialization of the appropriate bits | |
1893 | * and then setup of the interrupt mask. | |
1894 | */ | |
1895 | spin_lock_bh(&sc->sc_resetlock); | |
1896 | if (!ath9k_hw_reset(sc->sc_ah, init_channel, | |
99405f93 | 1897 | sc->tx_chan_width, |
ff37e337 S |
1898 | sc->sc_tx_chainmask, sc->sc_rx_chainmask, |
1899 | sc->sc_ht_extprotspacing, false, &status)) { | |
1900 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 S |
1901 | "Unable to reset hardware; hal status %u " |
1902 | "(freq %u flags 0x%x)\n", status, | |
ff37e337 S |
1903 | init_channel->channel, init_channel->channelFlags); |
1904 | error = -EIO; | |
1905 | spin_unlock_bh(&sc->sc_resetlock); | |
1906 | goto error; | |
1907 | } | |
1908 | spin_unlock_bh(&sc->sc_resetlock); | |
1909 | ||
1910 | /* | |
1911 | * This is needed only to setup initial state | |
1912 | * but it's best done after a reset. | |
1913 | */ | |
1914 | ath_update_txpow(sc); | |
8feceb67 | 1915 | |
ff37e337 S |
1916 | /* |
1917 | * Setup the hardware after reset: | |
1918 | * The receive engine is set going. | |
1919 | * Frame transmit is handled entirely | |
1920 | * in the frame output path; there's nothing to do | |
1921 | * here except setup the interrupt mask. | |
1922 | */ | |
1923 | if (ath_startrecv(sc) != 0) { | |
8feceb67 | 1924 | DPRINTF(sc, ATH_DBG_FATAL, |
04bd4638 | 1925 | "Unable to start recv logic\n"); |
ff37e337 S |
1926 | error = -EIO; |
1927 | goto error; | |
f078f209 | 1928 | } |
8feceb67 | 1929 | |
ff37e337 S |
1930 | /* Setup our intr mask. */ |
1931 | sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX | |
1932 | | ATH9K_INT_RXEOL | ATH9K_INT_RXORN | |
1933 | | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL; | |
1934 | ||
1935 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT) | |
1936 | sc->sc_imask |= ATH9K_INT_GTT; | |
1937 | ||
1938 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) | |
1939 | sc->sc_imask |= ATH9K_INT_CST; | |
1940 | ||
1941 | /* | |
1942 | * Enable MIB interrupts when there are hardware phy counters. | |
1943 | * Note we only do this (at the moment) for station mode. | |
1944 | */ | |
1945 | if (ath9k_hw_phycounters(sc->sc_ah) && | |
d97809db CM |
1946 | ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) || |
1947 | (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC))) | |
ff37e337 S |
1948 | sc->sc_imask |= ATH9K_INT_MIB; |
1949 | /* | |
1950 | * Some hardware processes the TIM IE and fires an | |
1951 | * interrupt when the TIM bit is set. For hardware | |
1952 | * that does, if not overridden by configuration, | |
1953 | * enable the TIM interrupt when operating as station. | |
1954 | */ | |
1955 | if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) && | |
d97809db | 1956 | (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) && |
ff37e337 S |
1957 | !sc->sc_config.swBeaconProcess) |
1958 | sc->sc_imask |= ATH9K_INT_TIM; | |
1959 | ||
1960 | ath_setcurmode(sc, ath_chan2mode(init_channel)); | |
1961 | ||
1962 | sc->sc_flags &= ~SC_OP_INVALID; | |
1963 | ||
1964 | /* Disable BMISS interrupt when we're not associated */ | |
1965 | sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); | |
1966 | ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask); | |
1967 | ||
1968 | ieee80211_wake_queues(sc->hw); | |
1969 | ||
e97275cb | 1970 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
9c84b797 | 1971 | error = ath_start_rfkill_poll(sc); |
500c064d VT |
1972 | #endif |
1973 | ||
ff37e337 | 1974 | error: |
9c84b797 | 1975 | return error; |
f078f209 LR |
1976 | } |
1977 | ||
8feceb67 VT |
1978 | static int ath9k_tx(struct ieee80211_hw *hw, |
1979 | struct sk_buff *skb) | |
f078f209 | 1980 | { |
528f0c6b | 1981 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
f078f209 | 1982 | struct ath_softc *sc = hw->priv; |
528f0c6b | 1983 | struct ath_tx_control txctl; |
8feceb67 | 1984 | int hdrlen, padsize; |
528f0c6b S |
1985 | |
1986 | memset(&txctl, 0, sizeof(struct ath_tx_control)); | |
f078f209 | 1987 | |
8feceb67 VT |
1988 | /* |
1989 | * As a temporary workaround, assign seq# here; this will likely need | |
1990 | * to be cleaned up to work better with Beacon transmission and virtual | |
1991 | * BSSes. | |
1992 | */ | |
1993 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
1994 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1995 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1996 | sc->seq_no += 0x10; | |
1997 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1998 | hdr->seq_ctrl |= cpu_to_le16(sc->seq_no); | |
1999 | } | |
f078f209 | 2000 | |
8feceb67 VT |
2001 | /* Add the padding after the header if this is not already done */ |
2002 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
2003 | if (hdrlen & 3) { | |
2004 | padsize = hdrlen % 4; | |
2005 | if (skb_headroom(skb) < padsize) | |
2006 | return -1; | |
2007 | skb_push(skb, padsize); | |
2008 | memmove(skb->data, skb->data + padsize, hdrlen); | |
2009 | } | |
2010 | ||
528f0c6b S |
2011 | /* Check if a tx queue is available */ |
2012 | ||
2013 | txctl.txq = ath_test_get_txq(sc, skb); | |
2014 | if (!txctl.txq) | |
2015 | goto exit; | |
2016 | ||
04bd4638 | 2017 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 2018 | |
528f0c6b | 2019 | if (ath_tx_start(sc, skb, &txctl) != 0) { |
04bd4638 | 2020 | DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 2021 | goto exit; |
8feceb67 VT |
2022 | } |
2023 | ||
528f0c6b S |
2024 | return 0; |
2025 | exit: | |
2026 | dev_kfree_skb_any(skb); | |
8feceb67 | 2027 | return 0; |
f078f209 LR |
2028 | } |
2029 | ||
8feceb67 | 2030 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 LR |
2031 | { |
2032 | struct ath_softc *sc = hw->priv; | |
f078f209 | 2033 | |
9c84b797 | 2034 | if (sc->sc_flags & SC_OP_INVALID) { |
04bd4638 | 2035 | DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); |
9c84b797 S |
2036 | return; |
2037 | } | |
8feceb67 | 2038 | |
04bd4638 | 2039 | DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n"); |
ff37e337 S |
2040 | |
2041 | ieee80211_stop_queues(sc->hw); | |
2042 | ||
2043 | /* make sure h/w will not generate any interrupt | |
2044 | * before setting the invalid flag. */ | |
2045 | ath9k_hw_set_interrupts(sc->sc_ah, 0); | |
2046 | ||
2047 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
2048 | ath_draintxq(sc, false); | |
2049 | ath_stoprecv(sc); | |
2050 | ath9k_hw_phy_disable(sc->sc_ah); | |
2051 | } else | |
2052 | sc->sc_rxlink = NULL; | |
2053 | ||
2054 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) | |
2055 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
2056 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
2057 | #endif | |
2058 | /* disable HAL and put h/w to sleep */ | |
2059 | ath9k_hw_disable(sc->sc_ah); | |
2060 | ath9k_hw_configpcipowersave(sc->sc_ah, 1); | |
2061 | ||
2062 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 2063 | |
04bd4638 | 2064 | DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
2065 | } |
2066 | ||
8feceb67 VT |
2067 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
2068 | struct ieee80211_if_init_conf *conf) | |
f078f209 LR |
2069 | { |
2070 | struct ath_softc *sc = hw->priv; | |
5640b08e | 2071 | struct ath_vap *avp = (void *)conf->vif->drv_priv; |
d97809db | 2072 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
f078f209 | 2073 | |
8feceb67 VT |
2074 | /* Support only vap for now */ |
2075 | ||
2076 | if (sc->sc_nvaps) | |
2077 | return -ENOBUFS; | |
2078 | ||
2079 | switch (conf->type) { | |
05c914fe | 2080 | case NL80211_IFTYPE_STATION: |
d97809db | 2081 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 2082 | break; |
05c914fe | 2083 | case NL80211_IFTYPE_ADHOC: |
d97809db | 2084 | ic_opmode = NL80211_IFTYPE_ADHOC; |
f078f209 | 2085 | break; |
05c914fe | 2086 | case NL80211_IFTYPE_AP: |
d97809db | 2087 | ic_opmode = NL80211_IFTYPE_AP; |
f078f209 LR |
2088 | break; |
2089 | default: | |
2090 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2091 | "Interface type %d not yet supported\n", conf->type); |
8feceb67 | 2092 | return -EOPNOTSUPP; |
f078f209 LR |
2093 | } |
2094 | ||
04bd4638 | 2095 | DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode); |
8feceb67 | 2096 | |
5640b08e S |
2097 | /* Set the VAP opmode */ |
2098 | avp->av_opmode = ic_opmode; | |
2099 | avp->av_bslot = -1; | |
2100 | ||
d97809db | 2101 | if (ic_opmode == NL80211_IFTYPE_AP) |
5640b08e S |
2102 | ath9k_hw_set_tsfadjust(sc->sc_ah, 1); |
2103 | ||
2104 | sc->sc_vaps[0] = conf->vif; | |
2105 | sc->sc_nvaps++; | |
2106 | ||
2107 | /* Set the device opmode */ | |
2108 | sc->sc_ah->ah_opmode = ic_opmode; | |
2109 | ||
6f255425 LR |
2110 | if (conf->type == NL80211_IFTYPE_AP) { |
2111 | /* TODO: is this a suitable place to start ANI for AP mode? */ | |
2112 | /* Start ANI */ | |
2113 | mod_timer(&sc->sc_ani.timer, | |
2114 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); | |
2115 | } | |
2116 | ||
8feceb67 | 2117 | return 0; |
f078f209 LR |
2118 | } |
2119 | ||
8feceb67 VT |
2120 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
2121 | struct ieee80211_if_init_conf *conf) | |
f078f209 | 2122 | { |
8feceb67 | 2123 | struct ath_softc *sc = hw->priv; |
5640b08e | 2124 | struct ath_vap *avp = (void *)conf->vif->drv_priv; |
f078f209 | 2125 | |
04bd4638 | 2126 | DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 2127 | |
8feceb67 VT |
2128 | #ifdef CONFIG_SLOW_ANT_DIV |
2129 | ath_slow_ant_div_stop(&sc->sc_antdiv); | |
2130 | #endif | |
6f255425 LR |
2131 | /* Stop ANI */ |
2132 | del_timer_sync(&sc->sc_ani.timer); | |
580f0b8a | 2133 | |
8feceb67 | 2134 | /* Reclaim beacon resources */ |
d97809db CM |
2135 | if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP || |
2136 | sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) { | |
8feceb67 VT |
2137 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); |
2138 | ath_beacon_return(sc, avp); | |
580f0b8a | 2139 | } |
f078f209 | 2140 | |
8feceb67 | 2141 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 2142 | |
5640b08e S |
2143 | sc->sc_vaps[0] = NULL; |
2144 | sc->sc_nvaps--; | |
f078f209 LR |
2145 | } |
2146 | ||
e8975581 | 2147 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 2148 | { |
8feceb67 | 2149 | struct ath_softc *sc = hw->priv; |
e8975581 | 2150 | struct ieee80211_conf *conf = &hw->conf; |
f078f209 | 2151 | |
99405f93 S |
2152 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
2153 | struct ieee80211_channel *curchan = hw->conf.channel; | |
2154 | int pos; | |
ae5eb026 | 2155 | |
04bd4638 S |
2156 | DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
2157 | curchan->center_freq); | |
f078f209 | 2158 | |
99405f93 S |
2159 | pos = ath_get_channel(sc, curchan); |
2160 | if (pos == -1) { | |
04bd4638 S |
2161 | DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", |
2162 | curchan->center_freq); | |
99405f93 S |
2163 | return -EINVAL; |
2164 | } | |
f078f209 | 2165 | |
99405f93 | 2166 | sc->tx_chan_width = ATH9K_HT_MACMODE_20; |
8feceb67 | 2167 | sc->sc_ah->ah_channels[pos].chanmode = |
99405f93 S |
2168 | (curchan->band == IEEE80211_BAND_2GHZ) ? |
2169 | CHANNEL_G : CHANNEL_A; | |
2170 | ||
d97809db | 2171 | if ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP) && |
e11602b7 S |
2172 | (conf->ht.enabled)) { |
2173 | sc->tx_chan_width = (!!conf->ht.sec_chan_offset) ? | |
2174 | ATH9K_HT_MACMODE_2040 : ATH9K_HT_MACMODE_20; | |
2175 | ||
2176 | sc->sc_ah->ah_channels[pos].chanmode = | |
2177 | ath_get_extchanmode(sc, curchan, | |
2178 | conf->ht.sec_chan_offset, | |
2179 | sc->tx_chan_width); | |
2180 | } | |
2181 | ||
2182 | if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) { | |
04bd4638 | 2183 | DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); |
e11602b7 S |
2184 | return -EINVAL; |
2185 | } | |
99405f93 S |
2186 | } |
2187 | ||
2188 | if (changed & IEEE80211_CONF_CHANGE_HT) | |
2189 | ath_update_chainmask(sc, conf->ht.enabled); | |
f078f209 | 2190 | |
5c020dc6 LR |
2191 | if (changed & IEEE80211_CONF_CHANGE_POWER) |
2192 | sc->sc_config.txpowlimit = 2 * conf->power_level; | |
f078f209 | 2193 | |
f078f209 LR |
2194 | return 0; |
2195 | } | |
2196 | ||
8feceb67 VT |
2197 | static int ath9k_config_interface(struct ieee80211_hw *hw, |
2198 | struct ieee80211_vif *vif, | |
2199 | struct ieee80211_if_conf *conf) | |
c83be688 | 2200 | { |
8feceb67 VT |
2201 | struct ath_softc *sc = hw->priv; |
2202 | struct ath_hal *ah = sc->sc_ah; | |
5640b08e | 2203 | struct ath_vap *avp = (void *)vif->drv_priv; |
8feceb67 VT |
2204 | u32 rfilt = 0; |
2205 | int error, i; | |
c83be688 | 2206 | |
8feceb67 VT |
2207 | /* TODO: Need to decide which hw opmode to use for multi-interface |
2208 | * cases */ | |
05c914fe | 2209 | if (vif->type == NL80211_IFTYPE_AP && |
d97809db CM |
2210 | ah->ah_opmode != NL80211_IFTYPE_AP) { |
2211 | ah->ah_opmode = NL80211_IFTYPE_STATION; | |
8feceb67 VT |
2212 | ath9k_hw_setopmode(ah); |
2213 | ath9k_hw_write_associd(ah, sc->sc_myaddr, 0); | |
2214 | /* Request full reset to get hw opmode changed properly */ | |
2215 | sc->sc_flags |= SC_OP_FULL_RESET; | |
2216 | } | |
c83be688 | 2217 | |
8feceb67 VT |
2218 | if ((conf->changed & IEEE80211_IFCC_BSSID) && |
2219 | !is_zero_ether_addr(conf->bssid)) { | |
2220 | switch (vif->type) { | |
05c914fe JB |
2221 | case NL80211_IFTYPE_STATION: |
2222 | case NL80211_IFTYPE_ADHOC: | |
8feceb67 VT |
2223 | /* Set BSSID */ |
2224 | memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN); | |
2225 | sc->sc_curaid = 0; | |
2226 | ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid, | |
2227 | sc->sc_curaid); | |
c83be688 | 2228 | |
8feceb67 VT |
2229 | /* Set aggregation protection mode parameters */ |
2230 | sc->sc_config.ath_aggr_prot = 0; | |
c83be688 | 2231 | |
8feceb67 | 2232 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 S |
2233 | "RX filter 0x%x bssid %pM aid 0x%x\n", |
2234 | rfilt, sc->sc_curbssid, sc->sc_curaid); | |
c83be688 | 2235 | |
8feceb67 VT |
2236 | /* need to reconfigure the beacon */ |
2237 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
c83be688 | 2238 | |
8feceb67 VT |
2239 | break; |
2240 | default: | |
2241 | break; | |
2242 | } | |
2243 | } | |
c83be688 | 2244 | |
8feceb67 | 2245 | if ((conf->changed & IEEE80211_IFCC_BEACON) && |
05c914fe JB |
2246 | ((vif->type == NL80211_IFTYPE_ADHOC) || |
2247 | (vif->type == NL80211_IFTYPE_AP))) { | |
8feceb67 VT |
2248 | /* |
2249 | * Allocate and setup the beacon frame. | |
2250 | * | |
2251 | * Stop any previous beacon DMA. This may be | |
2252 | * necessary, for example, when an ibss merge | |
2253 | * causes reconfiguration; we may be called | |
2254 | * with beacon transmission active. | |
2255 | */ | |
2256 | ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq); | |
c83be688 | 2257 | |
8feceb67 VT |
2258 | error = ath_beacon_alloc(sc, 0); |
2259 | if (error != 0) | |
2260 | return error; | |
c83be688 | 2261 | |
8feceb67 VT |
2262 | ath_beacon_sync(sc, 0); |
2263 | } | |
c83be688 | 2264 | |
8feceb67 | 2265 | /* Check for WLAN_CAPABILITY_PRIVACY ? */ |
d97809db | 2266 | if ((avp->av_opmode != NL80211_IFTYPE_STATION)) { |
8feceb67 VT |
2267 | for (i = 0; i < IEEE80211_WEP_NKID; i++) |
2268 | if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i)) | |
2269 | ath9k_hw_keysetmac(sc->sc_ah, | |
2270 | (u16)i, | |
2271 | sc->sc_curbssid); | |
2272 | } | |
c83be688 | 2273 | |
8feceb67 | 2274 | /* Only legacy IBSS for now */ |
05c914fe | 2275 | if (vif->type == NL80211_IFTYPE_ADHOC) |
8feceb67 | 2276 | ath_update_chainmask(sc, 0); |
f078f209 | 2277 | |
8feceb67 VT |
2278 | return 0; |
2279 | } | |
f078f209 | 2280 | |
8feceb67 VT |
2281 | #define SUPPORTED_FILTERS \ |
2282 | (FIF_PROMISC_IN_BSS | \ | |
2283 | FIF_ALLMULTI | \ | |
2284 | FIF_CONTROL | \ | |
2285 | FIF_OTHER_BSS | \ | |
2286 | FIF_BCN_PRBRESP_PROMISC | \ | |
2287 | FIF_FCSFAIL) | |
c83be688 | 2288 | |
8feceb67 VT |
2289 | /* FIXME: sc->sc_full_reset ? */ |
2290 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
2291 | unsigned int changed_flags, | |
2292 | unsigned int *total_flags, | |
2293 | int mc_count, | |
2294 | struct dev_mc_list *mclist) | |
2295 | { | |
2296 | struct ath_softc *sc = hw->priv; | |
2297 | u32 rfilt; | |
f078f209 | 2298 | |
8feceb67 VT |
2299 | changed_flags &= SUPPORTED_FILTERS; |
2300 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 2301 | |
8feceb67 VT |
2302 | sc->rx_filter = *total_flags; |
2303 | rfilt = ath_calcrxfilter(sc); | |
2304 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
f078f209 | 2305 | |
8feceb67 VT |
2306 | if (changed_flags & FIF_BCN_PRBRESP_PROMISC) { |
2307 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) | |
2308 | ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0); | |
2309 | } | |
f078f209 | 2310 | |
04bd4638 | 2311 | DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx_filter); |
8feceb67 | 2312 | } |
f078f209 | 2313 | |
8feceb67 VT |
2314 | static void ath9k_sta_notify(struct ieee80211_hw *hw, |
2315 | struct ieee80211_vif *vif, | |
2316 | enum sta_notify_cmd cmd, | |
17741cdc | 2317 | struct ieee80211_sta *sta) |
8feceb67 VT |
2318 | { |
2319 | struct ath_softc *sc = hw->priv; | |
f078f209 | 2320 | |
8feceb67 VT |
2321 | switch (cmd) { |
2322 | case STA_NOTIFY_ADD: | |
5640b08e | 2323 | ath_node_attach(sc, sta); |
8feceb67 VT |
2324 | break; |
2325 | case STA_NOTIFY_REMOVE: | |
b5aa9bf9 | 2326 | ath_node_detach(sc, sta); |
8feceb67 VT |
2327 | break; |
2328 | default: | |
2329 | break; | |
2330 | } | |
f078f209 LR |
2331 | } |
2332 | ||
8feceb67 VT |
2333 | static int ath9k_conf_tx(struct ieee80211_hw *hw, |
2334 | u16 queue, | |
2335 | const struct ieee80211_tx_queue_params *params) | |
f078f209 | 2336 | { |
8feceb67 VT |
2337 | struct ath_softc *sc = hw->priv; |
2338 | struct ath9k_tx_queue_info qi; | |
2339 | int ret = 0, qnum; | |
f078f209 | 2340 | |
8feceb67 VT |
2341 | if (queue >= WME_NUM_AC) |
2342 | return 0; | |
f078f209 | 2343 | |
8feceb67 VT |
2344 | qi.tqi_aifs = params->aifs; |
2345 | qi.tqi_cwmin = params->cw_min; | |
2346 | qi.tqi_cwmax = params->cw_max; | |
2347 | qi.tqi_burstTime = params->txop; | |
2348 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 2349 | |
8feceb67 | 2350 | DPRINTF(sc, ATH_DBG_CONFIG, |
04bd4638 | 2351 | "Configure tx [queue/halq] [%d/%d], " |
8feceb67 | 2352 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", |
04bd4638 S |
2353 | queue, qnum, params->aifs, params->cw_min, |
2354 | params->cw_max, params->txop); | |
f078f209 | 2355 | |
8feceb67 VT |
2356 | ret = ath_txq_update(sc, qnum, &qi); |
2357 | if (ret) | |
04bd4638 | 2358 | DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 2359 | |
8feceb67 VT |
2360 | return ret; |
2361 | } | |
f078f209 | 2362 | |
8feceb67 VT |
2363 | static int ath9k_set_key(struct ieee80211_hw *hw, |
2364 | enum set_key_cmd cmd, | |
2365 | const u8 *local_addr, | |
2366 | const u8 *addr, | |
2367 | struct ieee80211_key_conf *key) | |
2368 | { | |
2369 | struct ath_softc *sc = hw->priv; | |
2370 | int ret = 0; | |
f078f209 | 2371 | |
04bd4638 | 2372 | DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n"); |
f078f209 | 2373 | |
8feceb67 VT |
2374 | switch (cmd) { |
2375 | case SET_KEY: | |
2376 | ret = ath_key_config(sc, addr, key); | |
2377 | if (!ret) { | |
2378 | set_bit(key->keyidx, sc->sc_keymap); | |
2379 | key->hw_key_idx = key->keyidx; | |
2380 | /* push IV and Michael MIC generation to stack */ | |
2381 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
2382 | if (key->alg == ALG_TKIP) | |
2383 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
2384 | } | |
2385 | break; | |
2386 | case DISABLE_KEY: | |
2387 | ath_key_delete(sc, key); | |
2388 | clear_bit(key->keyidx, sc->sc_keymap); | |
8feceb67 VT |
2389 | break; |
2390 | default: | |
2391 | ret = -EINVAL; | |
2392 | } | |
f078f209 | 2393 | |
8feceb67 VT |
2394 | return ret; |
2395 | } | |
f078f209 | 2396 | |
8feceb67 VT |
2397 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
2398 | struct ieee80211_vif *vif, | |
2399 | struct ieee80211_bss_conf *bss_conf, | |
2400 | u32 changed) | |
2401 | { | |
2402 | struct ath_softc *sc = hw->priv; | |
f078f209 | 2403 | |
8feceb67 | 2404 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
04bd4638 | 2405 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
8feceb67 VT |
2406 | bss_conf->use_short_preamble); |
2407 | if (bss_conf->use_short_preamble) | |
2408 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
2409 | else | |
2410 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
2411 | } | |
f078f209 | 2412 | |
8feceb67 | 2413 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
04bd4638 | 2414 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
8feceb67 VT |
2415 | bss_conf->use_cts_prot); |
2416 | if (bss_conf->use_cts_prot && | |
2417 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
2418 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
2419 | else | |
2420 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
2421 | } | |
f078f209 | 2422 | |
99405f93 | 2423 | if (changed & BSS_CHANGED_HT) |
8feceb67 | 2424 | ath9k_ht_conf(sc, bss_conf); |
f078f209 | 2425 | |
8feceb67 | 2426 | if (changed & BSS_CHANGED_ASSOC) { |
04bd4638 | 2427 | DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 2428 | bss_conf->assoc); |
5640b08e | 2429 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 VT |
2430 | } |
2431 | } | |
f078f209 | 2432 | |
8feceb67 VT |
2433 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
2434 | { | |
2435 | u64 tsf; | |
2436 | struct ath_softc *sc = hw->priv; | |
2437 | struct ath_hal *ah = sc->sc_ah; | |
f078f209 | 2438 | |
8feceb67 | 2439 | tsf = ath9k_hw_gettsf64(ah); |
f078f209 | 2440 | |
8feceb67 VT |
2441 | return tsf; |
2442 | } | |
f078f209 | 2443 | |
8feceb67 VT |
2444 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
2445 | { | |
2446 | struct ath_softc *sc = hw->priv; | |
2447 | struct ath_hal *ah = sc->sc_ah; | |
c83be688 | 2448 | |
8feceb67 VT |
2449 | ath9k_hw_reset_tsf(ah); |
2450 | } | |
f078f209 | 2451 | |
8feceb67 VT |
2452 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
2453 | enum ieee80211_ampdu_mlme_action action, | |
17741cdc JB |
2454 | struct ieee80211_sta *sta, |
2455 | u16 tid, u16 *ssn) | |
8feceb67 VT |
2456 | { |
2457 | struct ath_softc *sc = hw->priv; | |
2458 | int ret = 0; | |
f078f209 | 2459 | |
8feceb67 VT |
2460 | switch (action) { |
2461 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2462 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2463 | ret = -ENOTSUPP; | |
8feceb67 VT |
2464 | break; |
2465 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2466 | break; |
2467 | case IEEE80211_AMPDU_TX_START: | |
b5aa9bf9 | 2468 | ret = ath_tx_aggr_start(sc, sta, tid, ssn); |
8feceb67 VT |
2469 | if (ret < 0) |
2470 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2471 | "Unable to start TX aggregation\n"); |
8feceb67 | 2472 | else |
17741cdc | 2473 | ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 VT |
2474 | break; |
2475 | case IEEE80211_AMPDU_TX_STOP: | |
b5aa9bf9 | 2476 | ret = ath_tx_aggr_stop(sc, sta, tid); |
8feceb67 VT |
2477 | if (ret < 0) |
2478 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 2479 | "Unable to stop TX aggregation\n"); |
f078f209 | 2480 | |
17741cdc | 2481 | ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid); |
8feceb67 | 2482 | break; |
8469cdef S |
2483 | case IEEE80211_AMPDU_TX_RESUME: |
2484 | ath_tx_aggr_resume(sc, sta, tid); | |
2485 | break; | |
8feceb67 | 2486 | default: |
04bd4638 | 2487 | DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); |
8feceb67 VT |
2488 | } |
2489 | ||
2490 | return ret; | |
f078f209 LR |
2491 | } |
2492 | ||
4233df6b JB |
2493 | static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value) |
2494 | { | |
2495 | return -EOPNOTSUPP; | |
2496 | } | |
2497 | ||
8feceb67 VT |
2498 | static struct ieee80211_ops ath9k_ops = { |
2499 | .tx = ath9k_tx, | |
2500 | .start = ath9k_start, | |
2501 | .stop = ath9k_stop, | |
2502 | .add_interface = ath9k_add_interface, | |
2503 | .remove_interface = ath9k_remove_interface, | |
2504 | .config = ath9k_config, | |
2505 | .config_interface = ath9k_config_interface, | |
2506 | .configure_filter = ath9k_configure_filter, | |
8feceb67 VT |
2507 | .sta_notify = ath9k_sta_notify, |
2508 | .conf_tx = ath9k_conf_tx, | |
8feceb67 | 2509 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2510 | .set_key = ath9k_set_key, |
8feceb67 VT |
2511 | .get_tsf = ath9k_get_tsf, |
2512 | .reset_tsf = ath9k_reset_tsf, | |
4233df6b JB |
2513 | .ampdu_action = ath9k_ampdu_action, |
2514 | .set_frag_threshold = ath9k_no_fragmentation, | |
8feceb67 VT |
2515 | }; |
2516 | ||
392dff83 BP |
2517 | static struct { |
2518 | u32 version; | |
2519 | const char * name; | |
2520 | } ath_mac_bb_names[] = { | |
2521 | { AR_SREV_VERSION_5416_PCI, "5416" }, | |
2522 | { AR_SREV_VERSION_5416_PCIE, "5418" }, | |
2523 | { AR_SREV_VERSION_9100, "9100" }, | |
2524 | { AR_SREV_VERSION_9160, "9160" }, | |
2525 | { AR_SREV_VERSION_9280, "9280" }, | |
2526 | { AR_SREV_VERSION_9285, "9285" } | |
2527 | }; | |
2528 | ||
2529 | static struct { | |
2530 | u16 version; | |
2531 | const char * name; | |
2532 | } ath_rf_names[] = { | |
2533 | { 0, "5133" }, | |
2534 | { AR_RAD5133_SREV_MAJOR, "5133" }, | |
2535 | { AR_RAD5122_SREV_MAJOR, "5122" }, | |
2536 | { AR_RAD2133_SREV_MAJOR, "2133" }, | |
2537 | { AR_RAD2122_SREV_MAJOR, "2122" } | |
2538 | }; | |
2539 | ||
2540 | /* | |
2541 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. | |
2542 | */ | |
392dff83 BP |
2543 | static const char * |
2544 | ath_mac_bb_name(u32 mac_bb_version) | |
2545 | { | |
2546 | int i; | |
2547 | ||
2548 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { | |
2549 | if (ath_mac_bb_names[i].version == mac_bb_version) { | |
2550 | return ath_mac_bb_names[i].name; | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | return "????"; | |
2555 | } | |
2556 | ||
2557 | /* | |
2558 | * Return the RF name. "????" is returned if the RF is unknown. | |
2559 | */ | |
392dff83 BP |
2560 | static const char * |
2561 | ath_rf_name(u16 rf_version) | |
2562 | { | |
2563 | int i; | |
2564 | ||
2565 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { | |
2566 | if (ath_rf_names[i].version == rf_version) { | |
2567 | return ath_rf_names[i].name; | |
2568 | } | |
2569 | } | |
2570 | ||
2571 | return "????"; | |
2572 | } | |
2573 | ||
f078f209 LR |
2574 | static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
2575 | { | |
2576 | void __iomem *mem; | |
2577 | struct ath_softc *sc; | |
2578 | struct ieee80211_hw *hw; | |
f078f209 LR |
2579 | u8 csz; |
2580 | u32 val; | |
2581 | int ret = 0; | |
392dff83 | 2582 | struct ath_hal *ah; |
f078f209 LR |
2583 | |
2584 | if (pci_enable_device(pdev)) | |
2585 | return -EIO; | |
2586 | ||
97b777db LR |
2587 | ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
2588 | ||
2589 | if (ret) { | |
1d450cfc | 2590 | printk(KERN_ERR "ath9k: 32-bit DMA not available\n"); |
97b777db LR |
2591 | goto bad; |
2592 | } | |
2593 | ||
2594 | ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
2595 | ||
2596 | if (ret) { | |
2597 | printk(KERN_ERR "ath9k: 32-bit DMA consistent " | |
04bd4638 | 2598 | "DMA enable failed\n"); |
f078f209 LR |
2599 | goto bad; |
2600 | } | |
2601 | ||
2602 | /* | |
2603 | * Cache line size is used to size and align various | |
2604 | * structures used to communicate with the hardware. | |
2605 | */ | |
2606 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
2607 | if (csz == 0) { | |
2608 | /* | |
2609 | * Linux 2.4.18 (at least) writes the cache line size | |
2610 | * register as a 16-bit wide register which is wrong. | |
2611 | * We must have this setup properly for rx buffer | |
2612 | * DMA to work so force a reasonable value here if it | |
2613 | * comes up zero. | |
2614 | */ | |
2615 | csz = L1_CACHE_BYTES / sizeof(u32); | |
2616 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
2617 | } | |
2618 | /* | |
2619 | * The default setting of latency timer yields poor results, | |
2620 | * set it to the value used by other systems. It may be worth | |
2621 | * tweaking this setting more. | |
2622 | */ | |
2623 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
2624 | ||
2625 | pci_set_master(pdev); | |
2626 | ||
2627 | /* | |
2628 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
2629 | * PCI Tx retries from interfering with C3 CPU state. | |
2630 | */ | |
2631 | pci_read_config_dword(pdev, 0x40, &val); | |
2632 | if ((val & 0x0000ff00) != 0) | |
2633 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
2634 | ||
2635 | ret = pci_request_region(pdev, 0, "ath9k"); | |
2636 | if (ret) { | |
2637 | dev_err(&pdev->dev, "PCI memory region reserve error\n"); | |
2638 | ret = -ENODEV; | |
2639 | goto bad; | |
2640 | } | |
2641 | ||
2642 | mem = pci_iomap(pdev, 0, 0); | |
2643 | if (!mem) { | |
2644 | printk(KERN_ERR "PCI memory map error\n") ; | |
2645 | ret = -EIO; | |
2646 | goto bad1; | |
2647 | } | |
2648 | ||
2649 | hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops); | |
2650 | if (hw == NULL) { | |
2651 | printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n"); | |
2652 | goto bad2; | |
2653 | } | |
2654 | ||
f078f209 LR |
2655 | SET_IEEE80211_DEV(hw, &pdev->dev); |
2656 | pci_set_drvdata(pdev, hw); | |
2657 | ||
2658 | sc = hw->priv; | |
2659 | sc->hw = hw; | |
2660 | sc->pdev = pdev; | |
2661 | sc->mem = mem; | |
2662 | ||
2663 | if (ath_attach(id->device, sc) != 0) { | |
2664 | ret = -ENODEV; | |
2665 | goto bad3; | |
2666 | } | |
2667 | ||
2668 | /* setup interrupt service routine */ | |
2669 | ||
2670 | if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) { | |
2671 | printk(KERN_ERR "%s: request_irq failed\n", | |
2672 | wiphy_name(hw->wiphy)); | |
2673 | ret = -EIO; | |
2674 | goto bad4; | |
2675 | } | |
2676 | ||
392dff83 BP |
2677 | ah = sc->sc_ah; |
2678 | printk(KERN_INFO | |
2679 | "%s: Atheros AR%s MAC/BB Rev:%x " | |
2680 | "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n", | |
f078f209 | 2681 | wiphy_name(hw->wiphy), |
392dff83 BP |
2682 | ath_mac_bb_name(ah->ah_macVersion), |
2683 | ah->ah_macRev, | |
2684 | ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)), | |
2685 | ah->ah_phyRev, | |
f078f209 LR |
2686 | (unsigned long)mem, pdev->irq); |
2687 | ||
2688 | return 0; | |
2689 | bad4: | |
2690 | ath_detach(sc); | |
2691 | bad3: | |
2692 | ieee80211_free_hw(hw); | |
2693 | bad2: | |
2694 | pci_iounmap(pdev, mem); | |
2695 | bad1: | |
2696 | pci_release_region(pdev, 0); | |
2697 | bad: | |
2698 | pci_disable_device(pdev); | |
2699 | return ret; | |
2700 | } | |
2701 | ||
2702 | static void ath_pci_remove(struct pci_dev *pdev) | |
2703 | { | |
2704 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
2705 | struct ath_softc *sc = hw->priv; | |
2706 | ||
f078f209 | 2707 | ath_detach(sc); |
9c84b797 S |
2708 | if (pdev->irq) |
2709 | free_irq(pdev->irq, sc); | |
f078f209 LR |
2710 | pci_iounmap(pdev, sc->mem); |
2711 | pci_release_region(pdev, 0); | |
2712 | pci_disable_device(pdev); | |
2713 | ieee80211_free_hw(hw); | |
2714 | } | |
2715 | ||
2716 | #ifdef CONFIG_PM | |
2717 | ||
2718 | static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
2719 | { | |
c83be688 VT |
2720 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
2721 | struct ath_softc *sc = hw->priv; | |
2722 | ||
2723 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
500c064d | 2724 | |
e97275cb | 2725 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
2726 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
2727 | cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll); | |
2728 | #endif | |
2729 | ||
f078f209 LR |
2730 | pci_save_state(pdev); |
2731 | pci_disable_device(pdev); | |
2732 | pci_set_power_state(pdev, 3); | |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | ||
2737 | static int ath_pci_resume(struct pci_dev *pdev) | |
2738 | { | |
c83be688 VT |
2739 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); |
2740 | struct ath_softc *sc = hw->priv; | |
f078f209 LR |
2741 | u32 val; |
2742 | int err; | |
2743 | ||
2744 | err = pci_enable_device(pdev); | |
2745 | if (err) | |
2746 | return err; | |
2747 | pci_restore_state(pdev); | |
2748 | /* | |
2749 | * Suspend/Resume resets the PCI configuration space, so we have to | |
2750 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
2751 | * PCI Tx retries from interfering with C3 CPU state | |
2752 | */ | |
2753 | pci_read_config_dword(pdev, 0x40, &val); | |
2754 | if ((val & 0x0000ff00) != 0) | |
2755 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
2756 | ||
c83be688 VT |
2757 | /* Enable LED */ |
2758 | ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN, | |
2759 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); | |
2760 | ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1); | |
2761 | ||
e97275cb | 2762 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
500c064d VT |
2763 | /* |
2764 | * check the h/w rfkill state on resume | |
2765 | * and start the rfkill poll timer | |
2766 | */ | |
2767 | if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT) | |
2768 | queue_delayed_work(sc->hw->workqueue, | |
2769 | &sc->rf_kill.rfkill_poll, 0); | |
2770 | #endif | |
2771 | ||
f078f209 LR |
2772 | return 0; |
2773 | } | |
2774 | ||
2775 | #endif /* CONFIG_PM */ | |
2776 | ||
2777 | MODULE_DEVICE_TABLE(pci, ath_pci_id_table); | |
2778 | ||
2779 | static struct pci_driver ath_pci_driver = { | |
2780 | .name = "ath9k", | |
2781 | .id_table = ath_pci_id_table, | |
2782 | .probe = ath_pci_probe, | |
2783 | .remove = ath_pci_remove, | |
2784 | #ifdef CONFIG_PM | |
2785 | .suspend = ath_pci_suspend, | |
2786 | .resume = ath_pci_resume, | |
2787 | #endif /* CONFIG_PM */ | |
2788 | }; | |
2789 | ||
2790 | static int __init init_ath_pci(void) | |
2791 | { | |
2792 | printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION); | |
2793 | ||
2794 | if (pci_register_driver(&ath_pci_driver) < 0) { | |
2795 | printk(KERN_ERR | |
2796 | "ath_pci: No devices found, driver not installed.\n"); | |
2797 | pci_unregister_driver(&ath_pci_driver); | |
2798 | return -ENODEV; | |
2799 | } | |
2800 | ||
2801 | return 0; | |
2802 | } | |
2803 | module_init(init_ath_pci); | |
2804 | ||
2805 | static void __exit exit_ath_pci(void) | |
2806 | { | |
2807 | pci_unregister_driver(&ath_pci_driver); | |
04bd4638 | 2808 | printk(KERN_INFO "%s: Driver unloaded\n", dev_info); |
f078f209 LR |
2809 | } |
2810 | module_exit(exit_ath_pci); |