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cfg80211: allow users to help a driver's compliance
[linux-2.6-block.git] / drivers / net / wireless / ath9k / main.c
CommitLineData
f078f209
LR		 1/*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209
LR		 17#include <linux/nl80211.h>
18#include "core.h"
392dff83 19#include "reg.h"
2a163c6d 20#include "hw.h"
f078f209
LR		 21
22#define ATH_PCI_VERSION "0.1"
23
f078f209
LR		 24static char *dev_info = "ath9k";
25
26MODULE_AUTHOR("Atheros Communications");
27MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29MODULE_LICENSE("Dual BSD/GPL");
30
ce111bad
LR		 31static void ath_cache_conf_rate(struct ath_softc *sc,
32 struct ieee80211_conf *conf)
ff37e337 33{
030bb495
LR		 34 switch (conf->channel->band) {
35 case IEEE80211_BAND_2GHZ:
36 if (conf_is_ht20(conf))
37 sc->cur_rate_table =
38 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
39 else if (conf_is_ht40_minus(conf))
40 sc->cur_rate_table =
41 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
42 else if (conf_is_ht40_plus(conf))
43 sc->cur_rate_table =
44 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 45 else
030bb495
LR		 46 sc->cur_rate_table =
47 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 48 break;
49 case IEEE80211_BAND_5GHZ:
50 if (conf_is_ht20(conf))
51 sc->cur_rate_table =
52 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
53 else if (conf_is_ht40_minus(conf))
54 sc->cur_rate_table =
55 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
56 else if (conf_is_ht40_plus(conf))
57 sc->cur_rate_table =
58 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
59 else
96742256
LR		 60 sc->cur_rate_table =
61 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 62 break;
63 default:
ce111bad 64 BUG_ON(1);
030bb495
LR		 65 break;
66 }
ff37e337
S		 67}
68
69static void ath_update_txpow(struct ath_softc *sc)
70{
71 struct ath_hal *ah = sc->sc_ah;
72 u32 txpow;
73
74 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
75 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
76 /* read back in case value is clamped */
77 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
78 sc->sc_curtxpow = txpow;
79 }
80}
81
82static u8 parse_mpdudensity(u8 mpdudensity)
83{
84 /*
85 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
86 * 0 for no restriction
87 * 1 for 1/4 us
88 * 2 for 1/2 us
89 * 3 for 1 us
90 * 4 for 2 us
91 * 5 for 4 us
92 * 6 for 8 us
93 * 7 for 16 us
94 */
95 switch (mpdudensity) {
96 case 0:
97 return 0;
98 case 1:
99 case 2:
100 case 3:
101 /* Our lower layer calculations limit our precision to
102 1 microsecond */
103 return 1;
104 case 4:
105 return 2;
106 case 5:
107 return 4;
108 case 6:
109 return 8;
110 case 7:
111 return 16;
112 default:
113 return 0;
114 }
115}
116
117static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
118{
119 struct ath_rate_table *rate_table = NULL;
120 struct ieee80211_supported_band *sband;
121 struct ieee80211_rate *rate;
122 int i, maxrates;
123
124 switch (band) {
125 case IEEE80211_BAND_2GHZ:
126 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
127 break;
128 case IEEE80211_BAND_5GHZ:
129 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
130 break;
131 default:
132 break;
133 }
134
135 if (rate_table == NULL)
136 return;
137
138 sband = &sc->sbands[band];
139 rate = sc->rates[band];
140
141 if (rate_table->rate_cnt > ATH_RATE_MAX)
142 maxrates = ATH_RATE_MAX;
143 else
144 maxrates = rate_table->rate_cnt;
145
146 for (i = 0; i < maxrates; i++) {
147 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
148 rate[i].hw_value = rate_table->info[i].ratecode;
149 sband->n_bitrates++;
04bd4638
S		 150 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
151 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 152 }
153}
154
155static int ath_setup_channels(struct ath_softc *sc)
156{
157 struct ath_hal *ah = sc->sc_ah;
158 int nchan, i, a = 0, b = 0;
159 u8 regclassids[ATH_REGCLASSIDS_MAX];
160 u32 nregclass = 0;
161 struct ieee80211_supported_band *band_2ghz;
162 struct ieee80211_supported_band *band_5ghz;
163 struct ieee80211_channel *chan_2ghz;
164 struct ieee80211_channel *chan_5ghz;
165 struct ath9k_channel *c;
166
167 /* Fill in ah->ah_channels */
168 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
169 regclassids, ATH_REGCLASSIDS_MAX,
170 &nregclass, CTRY_DEFAULT, false, 1)) {
171 u32 rd = ah->ah_currentRD;
172 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 173 "Unable to collect channel list; "
ff37e337 174 "regdomain likely %u country code %u\n",
04bd4638 175 rd, CTRY_DEFAULT);
ff37e337
S		 176 return -EINVAL;
177 }
178
179 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
180 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
181 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
182 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
183
184 for (i = 0; i < nchan; i++) {
185 c = &ah->ah_channels[i];
186 if (IS_CHAN_2GHZ(c)) {
187 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
188 chan_2ghz[a].center_freq = c->channel;
189 chan_2ghz[a].max_power = c->maxTxPower;
76061abb 190 c->chan = &chan_2ghz[a];
ff37e337
S		 191
192 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
193 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
194 if (c->channelFlags & CHANNEL_PASSIVE)
195 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
196
197 band_2ghz->n_channels = ++a;
198
04bd4638 199 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
ff37e337 200 "channelFlags: 0x%x\n",
04bd4638 201 c->channel, c->channelFlags);
ff37e337
S		 202 } else if (IS_CHAN_5GHZ(c)) {
203 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
204 chan_5ghz[b].center_freq = c->channel;
205 chan_5ghz[b].max_power = c->maxTxPower;
76061abb 206 c->chan = &chan_5ghz[a];
ff37e337
S		 207
208 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
209 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
210 if (c->channelFlags & CHANNEL_PASSIVE)
211 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
212
213 band_5ghz->n_channels = ++b;
214
04bd4638 215 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
ff37e337 216 "channelFlags: 0x%x\n",
04bd4638 217 c->channel, c->channelFlags);
ff37e337
S		 218 }
219 }
220
221 return 0;
222}
223
224/*
225 * Set/change channels. If the channel is really being changed, it's done
226 * by reseting the chip. To accomplish this we must first cleanup any pending
227 * DMA, then restart stuff.
228*/
229static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
230{
231 struct ath_hal *ah = sc->sc_ah;
232 bool fastcc = true, stopped;
030bb495 233 struct ieee80211_hw *hw = sc->hw;
ae8d2858
LR		 234 struct ieee80211_channel *channel = hw->conf.channel;
235 int r;
ff37e337
S		 236
237 if (sc->sc_flags & SC_OP_INVALID)
238 return -EIO;
239
3cbb5dd7
VN		 240 ath9k_ps_wakeup(sc);
241
c0d7c7af
LR		 242 /*
243 * This is only performed if the channel settings have
244 * actually changed.
245 *
246 * To switch channels clear any pending DMA operations;
247 * wait long enough for the RX fifo to drain, reset the
248 * hardware at the new frequency, and then re-enable
249 * the relevant bits of the h/w.
250 */
251 ath9k_hw_set_interrupts(ah, 0);
043a0405 252 ath_drain_all_txq(sc, false);
c0d7c7af 253 stopped = ath_stoprecv(sc);
ff37e337 254
c0d7c7af
LR		 255 /* XXX: do not flush receive queue here. We don't want
256 * to flush data frames already in queue because of
257 * changing channel. */
ff37e337 258
c0d7c7af
LR		 259 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
260 fastcc = false;
261
262 DPRINTF(sc, ATH_DBG_CONFIG,
263 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
264 sc->sc_ah->ah_curchan->channel,
265 channel->center_freq, sc->tx_chan_width);
ff37e337 266
c0d7c7af
LR		 267 spin_lock_bh(&sc->sc_resetlock);
268
269 r = ath9k_hw_reset(ah, hchan, fastcc);
270 if (r) {
271 DPRINTF(sc, ATH_DBG_FATAL,
272 "Unable to reset channel (%u Mhz) "
273 "reset status %u\n",
274 channel->center_freq, r);
275 spin_unlock_bh(&sc->sc_resetlock);
276 return r;
ff37e337 277 }
c0d7c7af
LR		 278 spin_unlock_bh(&sc->sc_resetlock);
279
280 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
281 sc->sc_flags &= ~SC_OP_FULL_RESET;
282
283 if (ath_startrecv(sc) != 0) {
284 DPRINTF(sc, ATH_DBG_FATAL,
285 "Unable to restart recv logic\n");
286 return -EIO;
287 }
288
289 ath_cache_conf_rate(sc, &hw->conf);
290 ath_update_txpow(sc);
291 ath9k_hw_set_interrupts(ah, sc->sc_imask);
3cbb5dd7 292 ath9k_ps_restore(sc);
ff37e337
S		 293 return 0;
294}
295
296/*
297 * This routine performs the periodic noise floor calibration function
298 * that is used to adjust and optimize the chip performance. This
299 * takes environmental changes (location, temperature) into account.
300 * When the task is complete, it reschedules itself depending on the
301 * appropriate interval that was calculated.
302 */
303static void ath_ani_calibrate(unsigned long data)
304{
305 struct ath_softc *sc;
306 struct ath_hal *ah;
307 bool longcal = false;
308 bool shortcal = false;
309 bool aniflag = false;
310 unsigned int timestamp = jiffies_to_msecs(jiffies);
311 u32 cal_interval;
312
313 sc = (struct ath_softc *)data;
314 ah = sc->sc_ah;
315
316 /*
317 * don't calibrate when we're scanning.
318 * we are most likely not on our home channel.
319 */
b77f483f 320 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
ff37e337
S		 321 return;
322
323 /* Long calibration runs independently of short calibration. */
324 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
325 longcal = true;
04bd4638 326 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
ff37e337
S		 327 sc->sc_ani.sc_longcal_timer = timestamp;
328 }
329
330 /* Short calibration applies only while sc_caldone is false */
331 if (!sc->sc_ani.sc_caldone) {
332 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
333 ATH_SHORT_CALINTERVAL) {
334 shortcal = true;
04bd4638 335 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
ff37e337
S		 336 sc->sc_ani.sc_shortcal_timer = timestamp;
337 sc->sc_ani.sc_resetcal_timer = timestamp;
338 }
339 } else {
340 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
341 ATH_RESTART_CALINTERVAL) {
c9e27d94 342 sc->sc_ani.sc_caldone = ath9k_hw_reset_calvalid(ah);
ff37e337
S		 343 if (sc->sc_ani.sc_caldone)
344 sc->sc_ani.sc_resetcal_timer = timestamp;
345 }
346 }
347
348 /* Verify whether we must check ANI */
349 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
350 ATH_ANI_POLLINTERVAL) {
351 aniflag = true;
352 sc->sc_ani.sc_checkani_timer = timestamp;
353 }
354
355 /* Skip all processing if there's nothing to do. */
356 if (longcal || shortcal || aniflag) {
357 /* Call ANI routine if necessary */
358 if (aniflag)
359 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
360 ah->ah_curchan);
361
362 /* Perform calibration if necessary */
363 if (longcal || shortcal) {
364 bool iscaldone = false;
365
366 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
367 sc->sc_rx_chainmask, longcal,
368 &iscaldone)) {
369 if (longcal)
370 sc->sc_ani.sc_noise_floor =
371 ath9k_hw_getchan_noise(ah,
372 ah->ah_curchan);
373
374 DPRINTF(sc, ATH_DBG_ANI,
04bd4638 375 "calibrate chan %u/%x nf: %d\n",
ff37e337
S		 376 ah->ah_curchan->channel,
377 ah->ah_curchan->channelFlags,
378 sc->sc_ani.sc_noise_floor);
379 } else {
380 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 381 "calibrate chan %u/%x failed\n",
ff37e337
S		 382 ah->ah_curchan->channel,
383 ah->ah_curchan->channelFlags);
384 }
385 sc->sc_ani.sc_caldone = iscaldone;
386 }
387 }
388
389 /*
390 * Set timer interval based on previous results.
391 * The interval must be the shortest necessary to satisfy ANI,
392 * short calibration and long calibration.
393 */
aac9207e
S		 394 cal_interval = ATH_LONG_CALINTERVAL;
395 if (sc->sc_ah->ah_config.enable_ani)
396 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
ff37e337
S		 397 if (!sc->sc_ani.sc_caldone)
398 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
399
400 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
401}
402
403/*
404 * Update tx/rx chainmask. For legacy association,
405 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 406 * the chainmask configuration, for bt coexistence, use
407 * the chainmask configuration even in legacy mode.
ff37e337
S		 408 */
409static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
410{
411 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
c97c92d9
VT		 412 if (is_ht ||
413 (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
ff37e337
S		 414 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
415 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
416 } else {
417 sc->sc_tx_chainmask = 1;
418 sc->sc_rx_chainmask = 1;
419 }
420
04bd4638
S		 421 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
422 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
ff37e337
S		 423}
424
425static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
426{
427 struct ath_node *an;
428
429 an = (struct ath_node *)sta->drv_priv;
430
431 if (sc->sc_flags & SC_OP_TXAGGR)
432 ath_tx_node_init(sc, an);
433
434 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
435 sta->ht_cap.ampdu_factor);
436 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
437}
438
439static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
440{
441 struct ath_node *an = (struct ath_node *)sta->drv_priv;
442
443 if (sc->sc_flags & SC_OP_TXAGGR)
444 ath_tx_node_cleanup(sc, an);
445}
446
447static void ath9k_tasklet(unsigned long data)
448{
449 struct ath_softc *sc = (struct ath_softc *)data;
450 u32 status = sc->sc_intrstatus;
451
452 if (status & ATH9K_INT_FATAL) {
453 /* need a chip reset */
454 ath_reset(sc, false);
455 return;
456 } else {
457
458 if (status &
459 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
b77f483f 460 spin_lock_bh(&sc->rx.rxflushlock);
ff37e337 461 ath_rx_tasklet(sc, 0);
b77f483f 462 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 463 }
464 /* XXX: optimize this */
465 if (status & ATH9K_INT_TX)
466 ath_tx_tasklet(sc);
467 }
468
469 /* re-enable hardware interrupt */
470 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
471}
472
6baff7f9 473irqreturn_t ath_isr(int irq, void *dev)
ff37e337
S		 474{
475 struct ath_softc *sc = dev;
476 struct ath_hal *ah = sc->sc_ah;
477 enum ath9k_int status;
478 bool sched = false;
479
480 do {
481 if (sc->sc_flags & SC_OP_INVALID) {
482 /*
483 * The hardware is not ready/present, don't
484 * touch anything. Note this can happen early
485 * on if the IRQ is shared.
486 */
487 return IRQ_NONE;
488 }
489 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
490 return IRQ_NONE;
491 }
492
493 /*
494 * Figure out the reason(s) for the interrupt. Note
495 * that the hal returns a pseudo-ISR that may include
496 * bits we haven't explicitly enabled so we mask the
497 * value to insure we only process bits we requested.
498 */
499 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
500
501 status &= sc->sc_imask; /* discard unasked-for bits */
502
503 /*
504 * If there are no status bits set, then this interrupt was not
505 * for me (should have been caught above).
506 */
507 if (!status)
508 return IRQ_NONE;
509
510 sc->sc_intrstatus = status;
511
512 if (status & ATH9K_INT_FATAL) {
513 /* need a chip reset */
514 sched = true;
515 } else if (status & ATH9K_INT_RXORN) {
516 /* need a chip reset */
517 sched = true;
518 } else {
519 if (status & ATH9K_INT_SWBA) {
520 /* schedule a tasklet for beacon handling */
521 tasklet_schedule(&sc->bcon_tasklet);
522 }
523 if (status & ATH9K_INT_RXEOL) {
524 /*
525 * NB: the hardware should re-read the link when
526 * RXE bit is written, but it doesn't work
527 * at least on older hardware revs.
528 */
529 sched = true;
530 }
531
532 if (status & ATH9K_INT_TXURN)
533 /* bump tx trigger level */
534 ath9k_hw_updatetxtriglevel(ah, true);
535 /* XXX: optimize this */
536 if (status & ATH9K_INT_RX)
537 sched = true;
538 if (status & ATH9K_INT_TX)
539 sched = true;
540 if (status & ATH9K_INT_BMISS)
541 sched = true;
542 /* carrier sense timeout */
543 if (status & ATH9K_INT_CST)
544 sched = true;
545 if (status & ATH9K_INT_MIB) {
546 /*
547 * Disable interrupts until we service the MIB
548 * interrupt; otherwise it will continue to
549 * fire.
550 */
551 ath9k_hw_set_interrupts(ah, 0);
552 /*
553 * Let the hal handle the event. We assume
554 * it will clear whatever condition caused
555 * the interrupt.
556 */
557 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
558 ath9k_hw_set_interrupts(ah, sc->sc_imask);
559 }
560 if (status & ATH9K_INT_TIM_TIMER) {
561 if (!(ah->ah_caps.hw_caps &
562 ATH9K_HW_CAP_AUTOSLEEP)) {
563 /* Clear RxAbort bit so that we can
564 * receive frames */
3cbb5dd7 565 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
ff37e337
S		 566 ath9k_hw_setrxabort(ah, 0);
567 sched = true;
3cbb5dd7 568 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337
S		 569 }
570 }
571 }
572 } while (0);
573
817e11de
S		 574 ath_debug_stat_interrupt(sc, status);
575
ff37e337
S		 576 if (sched) {
577 /* turn off every interrupt except SWBA */
578 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
579 tasklet_schedule(&sc->intr_tq);
580 }
581
582 return IRQ_HANDLED;
583}
584
f078f209
LR		 585static int ath_get_channel(struct ath_softc *sc,
586 struct ieee80211_channel *chan)
587{
588 int i;
589
590 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
591 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
592 return i;
593 }
594
595 return -1;
596}
597
598static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 599 struct ieee80211_channel *chan,
094d05dc 600 enum nl80211_channel_type channel_type)
f078f209
LR		 601{
602 u32 chanmode = 0;
f078f209
LR		 603
604 switch (chan->band) {
605 case IEEE80211_BAND_2GHZ:
094d05dc
S		 606 switch(channel_type) {
607 case NL80211_CHAN_NO_HT:
608 case NL80211_CHAN_HT20:
f078f209 609 chanmode = CHANNEL_G_HT20;
094d05dc
S		 610 break;
611 case NL80211_CHAN_HT40PLUS:
f078f209 612 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 613 break;
614 case NL80211_CHAN_HT40MINUS:
f078f209 615 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 616 break;
617 }
f078f209
LR		 618 break;
619 case IEEE80211_BAND_5GHZ:
094d05dc
S		 620 switch(channel_type) {
621 case NL80211_CHAN_NO_HT:
622 case NL80211_CHAN_HT20:
f078f209 623 chanmode = CHANNEL_A_HT20;
094d05dc
S		 624 break;
625 case NL80211_CHAN_HT40PLUS:
f078f209 626 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 627 break;
628 case NL80211_CHAN_HT40MINUS:
f078f209 629 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 630 break;
631 }
f078f209
LR		 632 break;
633 default:
634 break;
635 }
636
637 return chanmode;
638}
639
ff37e337
S		 640static int ath_keyset(struct ath_softc *sc, u16 keyix,
641 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
642{
643 bool status;
644
645 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
646 keyix, hk, mac, false);
647
648 return status != false;
649}
f078f209 650
6ace2891 651static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
f078f209
LR		 652 struct ath9k_keyval *hk,
653 const u8 *addr)
654{
6ace2891
JM		 655 const u8 *key_rxmic;
656 const u8 *key_txmic;
f078f209 657
6ace2891
JM		 658 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
659 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 660
661 if (addr == NULL) {
662 /* Group key installation */
6ace2891
JM		 663 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
664 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 665 }
666 if (!sc->sc_splitmic) {
667 /*
668 * data key goes at first index,
669 * the hal handles the MIC keys at index+64.
670 */
671 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
672 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
6ace2891 673 return ath_keyset(sc, keyix, hk, addr);
f078f209
LR		 674 }
675 /*
676 * TX key goes at first index, RX key at +32.
677 * The hal handles the MIC keys at index+64.
678 */
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
6ace2891 680 if (!ath_keyset(sc, keyix, hk, NULL)) {
f078f209
LR		 681 /* Txmic entry failed. No need to proceed further */
682 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638 683 "Setting TX MIC Key Failed\n");
f078f209
LR		 684 return 0;
685 }
686
687 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
688 /* XXX delete tx key on failure? */
6ace2891
JM		 689 return ath_keyset(sc, keyix + 32, hk, addr);
690}
691
692static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
693{
694 int i;
695
696 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
697 if (test_bit(i, sc->sc_keymap) ||
698 test_bit(i + 64, sc->sc_keymap))
699 continue; /* At least one part of TKIP key allocated */
700 if (sc->sc_splitmic &&
701 (test_bit(i + 32, sc->sc_keymap) ||
702 test_bit(i + 64 + 32, sc->sc_keymap)))
703 continue; /* At least one part of TKIP key allocated */
704
705 /* Found a free slot for a TKIP key */
706 return i;
707 }
708 return -1;
709}
710
711static int ath_reserve_key_cache_slot(struct ath_softc *sc)
712{
713 int i;
714
715 /* First, try to find slots that would not be available for TKIP. */
716 if (sc->sc_splitmic) {
717 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
718 if (!test_bit(i, sc->sc_keymap) &&
719 (test_bit(i + 32, sc->sc_keymap) ||
720 test_bit(i + 64, sc->sc_keymap) ||
721 test_bit(i + 64 + 32, sc->sc_keymap)))
722 return i;
723 if (!test_bit(i + 32, sc->sc_keymap) &&
724 (test_bit(i, sc->sc_keymap) ||
725 test_bit(i + 64, sc->sc_keymap) ||
726 test_bit(i + 64 + 32, sc->sc_keymap)))
727 return i + 32;
728 if (!test_bit(i + 64, sc->sc_keymap) &&
729 (test_bit(i , sc->sc_keymap) ||
730 test_bit(i + 32, sc->sc_keymap) ||
731 test_bit(i + 64 + 32, sc->sc_keymap)))
ea612132 732 return i + 64;
6ace2891
JM		 733 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
734 (test_bit(i, sc->sc_keymap) ||
735 test_bit(i + 32, sc->sc_keymap) ||
736 test_bit(i + 64, sc->sc_keymap)))
ea612132 737 return i + 64 + 32;
6ace2891
JM		 738 }
739 } else {
740 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
741 if (!test_bit(i, sc->sc_keymap) &&
742 test_bit(i + 64, sc->sc_keymap))
743 return i;
744 if (test_bit(i, sc->sc_keymap) &&
745 !test_bit(i + 64, sc->sc_keymap))
746 return i + 64;
747 }
748 }
749
750 /* No partially used TKIP slots, pick any available slot */
751 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
be2864cf
JM		 752 /* Do not allow slots that could be needed for TKIP group keys
753 * to be used. This limitation could be removed if we know that
754 * TKIP will not be used. */
755 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
756 continue;
757 if (sc->sc_splitmic) {
758 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
759 continue;
760 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
761 continue;
762 }
763
6ace2891
JM		 764 if (!test_bit(i, sc->sc_keymap))
765 return i; /* Found a free slot for a key */
766 }
767
768 /* No free slot found */
769 return -1;
f078f209
LR		 770}
771
772static int ath_key_config(struct ath_softc *sc,
dc822b5d 773 struct ieee80211_sta *sta,
f078f209
LR		 774 struct ieee80211_key_conf *key)
775{
f078f209
LR		 776 struct ath9k_keyval hk;
777 const u8 *mac = NULL;
778 int ret = 0;
6ace2891 779 int idx;
f078f209
LR		 780
781 memset(&hk, 0, sizeof(hk));
782
783 switch (key->alg) {
784 case ALG_WEP:
785 hk.kv_type = ATH9K_CIPHER_WEP;
786 break;
787 case ALG_TKIP:
788 hk.kv_type = ATH9K_CIPHER_TKIP;
789 break;
790 case ALG_CCMP:
791 hk.kv_type = ATH9K_CIPHER_AES_CCM;
792 break;
793 default:
ca470b29 794 return -EOPNOTSUPP;
f078f209
LR		 795 }
796
6ace2891 797 hk.kv_len = key->keylen;
f078f209
LR		 798 memcpy(hk.kv_val, key->key, key->keylen);
799
6ace2891
JM		 800 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
801 /* For now, use the default keys for broadcast keys. This may
802 * need to change with virtual interfaces. */
803 idx = key->keyidx;
804 } else if (key->keyidx) {
805 struct ieee80211_vif *vif;
f078f209 806
dc822b5d
JB		 807 if (WARN_ON(!sta))
808 return -EOPNOTSUPP;
809 mac = sta->addr;
810
6ace2891
JM		 811 vif = sc->sc_vaps[0];
812 if (vif->type != NL80211_IFTYPE_AP) {
813 /* Only keyidx 0 should be used with unicast key, but
814 * allow this for client mode for now. */
815 idx = key->keyidx;
816 } else
817 return -EIO;
f078f209 818 } else {
dc822b5d
JB		 819 if (WARN_ON(!sta))
820 return -EOPNOTSUPP;
821 mac = sta->addr;
822
6ace2891
JM		 823 if (key->alg == ALG_TKIP)
824 idx = ath_reserve_key_cache_slot_tkip(sc);
825 else
826 idx = ath_reserve_key_cache_slot(sc);
827 if (idx < 0)
ca470b29 828 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 829 }
830
831 if (key->alg == ALG_TKIP)
6ace2891 832 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
f078f209 833 else
6ace2891 834 ret = ath_keyset(sc, idx, &hk, mac);
f078f209
LR		 835
836 if (!ret)
837 return -EIO;
838
6ace2891
JM		 839 set_bit(idx, sc->sc_keymap);
840 if (key->alg == ALG_TKIP) {
841 set_bit(idx + 64, sc->sc_keymap);
842 if (sc->sc_splitmic) {
843 set_bit(idx + 32, sc->sc_keymap);
844 set_bit(idx + 64 + 32, sc->sc_keymap);
845 }
846 }
847
848 return idx;
f078f209
LR		 849}
850
851static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
852{
6ace2891
JM		 853 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
854 if (key->hw_key_idx < IEEE80211_WEP_NKID)
855 return;
856
857 clear_bit(key->hw_key_idx, sc->sc_keymap);
858 if (key->alg != ALG_TKIP)
859 return;
f078f209 860
6ace2891
JM		 861 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
862 if (sc->sc_splitmic) {
863 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
864 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
865 }
f078f209
LR		 866}
867
d9fe60de 868static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
f078f209 869{
60653678
S		 870#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
871#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 872
d9fe60de
JB		 873 ht_info->ht_supported = true;
874 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
875 IEEE80211_HT_CAP_SM_PS |
876 IEEE80211_HT_CAP_SGI_40 |
877 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 878
60653678
S		 879 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
880 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
d9fe60de
JB		 881 /* set up supported mcs set */
882 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
883 ht_info->mcs.rx_mask[0] = 0xff;
884 ht_info->mcs.rx_mask[1] = 0xff;
885 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 886}
887
8feceb67 888static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 889 struct ieee80211_vif *vif,
8feceb67 890 struct ieee80211_bss_conf *bss_conf)
f078f209 891{
5640b08e 892 struct ath_vap *avp = (void *)vif->drv_priv;
f078f209 893
8feceb67 894 if (bss_conf->assoc) {
094d05dc
S		 895 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
896 bss_conf->aid, sc->sc_curbssid);
f078f209 897
8feceb67 898 /* New association, store aid */
d97809db 899 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
8feceb67
VT		 900 sc->sc_curaid = bss_conf->aid;
901 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
902 sc->sc_curaid);
903 }
f078f209 904
8feceb67
VT		 905 /* Configure the beacon */
906 ath_beacon_config(sc, 0);
907 sc->sc_flags |= SC_OP_BEACONS;
f078f209 908
8feceb67
VT		 909 /* Reset rssi stats */
910 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
911 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
912 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
913 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 914
6f255425
LR		 915 /* Start ANI */
916 mod_timer(&sc->sc_ani.timer,
917 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
918
8feceb67 919 } else {
04bd4638 920 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
8feceb67 921 sc->sc_curaid = 0;
f078f209 922 }
8feceb67 923}
f078f209 924
8feceb67
VT		 925/********************************/
926/* LED functions */
927/********************************/
f078f209 928
8feceb67
VT		 929static void ath_led_brightness(struct led_classdev *led_cdev,
930 enum led_brightness brightness)
931{
932 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
933 struct ath_softc *sc = led->sc;
f078f209 934
8feceb67
VT		 935 switch (brightness) {
936 case LED_OFF:
937 if (led->led_type == ATH_LED_ASSOC ||
938 led->led_type == ATH_LED_RADIO)
939 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
940 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
941 (led->led_type == ATH_LED_RADIO) ? 1 :
942 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
943 break;
944 case LED_FULL:
945 if (led->led_type == ATH_LED_ASSOC)
946 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
947 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
948 break;
949 default:
950 break;
f078f209 951 }
8feceb67 952}
f078f209 953
8feceb67
VT		 954static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
955 char *trigger)
956{
957 int ret;
f078f209 958
8feceb67
VT		 959 led->sc = sc;
960 led->led_cdev.name = led->name;
961 led->led_cdev.default_trigger = trigger;
962 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 963
8feceb67
VT		 964 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
965 if (ret)
966 DPRINTF(sc, ATH_DBG_FATAL,
967 "Failed to register led:%s", led->name);
968 else
969 led->registered = 1;
970 return ret;
971}
f078f209 972
8feceb67
VT		 973static void ath_unregister_led(struct ath_led *led)
974{
975 if (led->registered) {
976 led_classdev_unregister(&led->led_cdev);
977 led->registered = 0;
f078f209 978 }
f078f209
LR		 979}
980
8feceb67 981static void ath_deinit_leds(struct ath_softc *sc)
f078f209 982{
8feceb67
VT		 983 ath_unregister_led(&sc->assoc_led);
984 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
985 ath_unregister_led(&sc->tx_led);
986 ath_unregister_led(&sc->rx_led);
987 ath_unregister_led(&sc->radio_led);
988 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
989}
f078f209 990
8feceb67
VT		 991static void ath_init_leds(struct ath_softc *sc)
992{
993 char *trigger;
994 int ret;
f078f209 995
8feceb67
VT		 996 /* Configure gpio 1 for output */
997 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
998 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
999 /* LED off, active low */
1000 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1001
8feceb67
VT		 1002 trigger = ieee80211_get_radio_led_name(sc->hw);
1003 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1004 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1005 ret = ath_register_led(sc, &sc->radio_led, trigger);
1006 sc->radio_led.led_type = ATH_LED_RADIO;
1007 if (ret)
1008 goto fail;
7dcfdcd9 1009
8feceb67
VT		 1010 trigger = ieee80211_get_assoc_led_name(sc->hw);
1011 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1012 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1013 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1014 sc->assoc_led.led_type = ATH_LED_ASSOC;
1015 if (ret)
1016 goto fail;
f078f209 1017
8feceb67
VT		 1018 trigger = ieee80211_get_tx_led_name(sc->hw);
1019 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1020 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1021 ret = ath_register_led(sc, &sc->tx_led, trigger);
1022 sc->tx_led.led_type = ATH_LED_TX;
1023 if (ret)
1024 goto fail;
f078f209 1025
8feceb67
VT		 1026 trigger = ieee80211_get_rx_led_name(sc->hw);
1027 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1028 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1029 ret = ath_register_led(sc, &sc->rx_led, trigger);
1030 sc->rx_led.led_type = ATH_LED_RX;
1031 if (ret)
1032 goto fail;
f078f209 1033
8feceb67
VT		 1034 return;
1035
1036fail:
1037 ath_deinit_leds(sc);
f078f209
LR		 1038}
1039
e97275cb 1040#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
9c84b797 1041
500c064d
VT		 1042/*******************/
1043/* Rfkill */
1044/*******************/
1045
1046static void ath_radio_enable(struct ath_softc *sc)
1047{
1048 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1049 struct ieee80211_channel *channel = sc->hw->conf.channel;
1050 int r;
500c064d 1051
3cbb5dd7 1052 ath9k_ps_wakeup(sc);
500c064d 1053 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1054
1055 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1056
1057 if (r) {
500c064d 1058 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1059 "Unable to reset channel %u (%uMhz) ",
1060 "reset status %u\n",
1061 channel->center_freq, r);
500c064d
VT		 1062 }
1063 spin_unlock_bh(&sc->sc_resetlock);
1064
1065 ath_update_txpow(sc);
1066 if (ath_startrecv(sc) != 0) {
1067 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1068 "Unable to restart recv logic\n");
500c064d
VT		 1069 return;
1070 }
1071
1072 if (sc->sc_flags & SC_OP_BEACONS)
1073 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1074
1075 /* Re-Enable interrupts */
1076 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1077
1078 /* Enable LED */
1079 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1080 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1081 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1082
1083 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1084 ath9k_ps_restore(sc);
500c064d
VT		 1085}
1086
1087static void ath_radio_disable(struct ath_softc *sc)
1088{
1089 struct ath_hal *ah = sc->sc_ah;
ae8d2858
LR		 1090 struct ieee80211_channel *channel = sc->hw->conf.channel;
1091 int r;
500c064d 1092
3cbb5dd7 1093 ath9k_ps_wakeup(sc);
500c064d
VT		 1094 ieee80211_stop_queues(sc->hw);
1095
1096 /* Disable LED */
1097 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1098 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1099
1100 /* Disable interrupts */
1101 ath9k_hw_set_interrupts(ah, 0);
1102
043a0405 1103 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1104 ath_stoprecv(sc); /* turn off frame recv */
1105 ath_flushrecv(sc); /* flush recv queue */
1106
1107 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1108 r = ath9k_hw_reset(ah, ah->ah_curchan, false);
1109 if (r) {
500c064d 1110 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1111 "Unable to reset channel %u (%uMhz) "
ae8d2858
LR		 1112 "reset status %u\n",
1113 channel->center_freq, r);
500c064d
VT		 1114 }
1115 spin_unlock_bh(&sc->sc_resetlock);
1116
1117 ath9k_hw_phy_disable(ah);
1118 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
3cbb5dd7 1119 ath9k_ps_restore(sc);
500c064d
VT		 1120}
1121
1122static bool ath_is_rfkill_set(struct ath_softc *sc)
1123{
1124 struct ath_hal *ah = sc->sc_ah;
1125
1126 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1127 ah->ah_rfkill_polarity;
1128}
1129
1130/* h/w rfkill poll function */
1131static void ath_rfkill_poll(struct work_struct *work)
1132{
1133 struct ath_softc *sc = container_of(work, struct ath_softc,
1134 rf_kill.rfkill_poll.work);
1135 bool radio_on;
1136
1137 if (sc->sc_flags & SC_OP_INVALID)
1138 return;
1139
1140 radio_on = !ath_is_rfkill_set(sc);
1141
1142 /*
1143 * enable/disable radio only when there is a
1144 * state change in RF switch
1145 */
1146 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1147 enum rfkill_state state;
1148
1149 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1150 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1151 : RFKILL_STATE_HARD_BLOCKED;
1152 } else if (radio_on) {
1153 ath_radio_enable(sc);
1154 state = RFKILL_STATE_UNBLOCKED;
1155 } else {
1156 ath_radio_disable(sc);
1157 state = RFKILL_STATE_HARD_BLOCKED;
1158 }
1159
1160 if (state == RFKILL_STATE_HARD_BLOCKED)
1161 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1162 else
1163 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1164
1165 rfkill_force_state(sc->rf_kill.rfkill, state);
1166 }
1167
1168 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1169 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1170}
1171
1172/* s/w rfkill handler */
1173static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1174{
1175 struct ath_softc *sc = data;
1176
1177 switch (state) {
1178 case RFKILL_STATE_SOFT_BLOCKED:
1179 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1180 SC_OP_RFKILL_SW_BLOCKED)))
1181 ath_radio_disable(sc);
1182 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1183 return 0;
1184 case RFKILL_STATE_UNBLOCKED:
1185 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1186 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1187 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1188 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
04bd4638 1189 "radio as it is disabled by h/w\n");
500c064d
VT		 1190 return -EPERM;
1191 }
1192 ath_radio_enable(sc);
1193 }
1194 return 0;
1195 default:
1196 return -EINVAL;
1197 }
1198}
1199
1200/* Init s/w rfkill */
1201static int ath_init_sw_rfkill(struct ath_softc *sc)
1202{
1203 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1204 RFKILL_TYPE_WLAN);
1205 if (!sc->rf_kill.rfkill) {
1206 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1207 return -ENOMEM;
1208 }
1209
1210 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1211 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1212 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1213 sc->rf_kill.rfkill->data = sc;
1214 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1215 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1216 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1217
1218 return 0;
1219}
1220
1221/* Deinitialize rfkill */
1222static void ath_deinit_rfkill(struct ath_softc *sc)
1223{
1224 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1225 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1226
1227 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1228 rfkill_unregister(sc->rf_kill.rfkill);
1229 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1230 sc->rf_kill.rfkill = NULL;
1231 }
1232}
9c84b797
S		 1233
1234static int ath_start_rfkill_poll(struct ath_softc *sc)
1235{
1236 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1237 queue_delayed_work(sc->hw->workqueue,
1238 &sc->rf_kill.rfkill_poll, 0);
1239
1240 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1241 if (rfkill_register(sc->rf_kill.rfkill)) {
1242 DPRINTF(sc, ATH_DBG_FATAL,
1243 "Unable to register rfkill\n");
1244 rfkill_free(sc->rf_kill.rfkill);
1245
1246 /* Deinitialize the device */
39c3c2f2 1247 ath_cleanup(sc);
9c84b797
S		 1248 return -EIO;
1249 } else {
1250 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1251 }
1252 }
1253
1254 return 0;
1255}
500c064d
VT		 1256#endif /* CONFIG_RFKILL */
1257
6baff7f9 1258void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1259{
1260 ath_detach(sc);
1261 free_irq(sc->irq, sc);
1262 ath_bus_cleanup(sc);
1263 ieee80211_free_hw(sc->hw);
1264}
1265
6baff7f9 1266void ath_detach(struct ath_softc *sc)
f078f209 1267{
8feceb67 1268 struct ieee80211_hw *hw = sc->hw;
9c84b797 1269 int i = 0;
f078f209 1270
3cbb5dd7
VN		 1271 ath9k_ps_wakeup(sc);
1272
04bd4638 1273 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1274
e97275cb 1275#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1276 ath_deinit_rfkill(sc);
1277#endif
3fcdfb4b
VT		 1278 ath_deinit_leds(sc);
1279
1280 ieee80211_unregister_hw(hw);
8feceb67
VT		 1281 ath_rx_cleanup(sc);
1282 ath_tx_cleanup(sc);
f078f209 1283
9c84b797
S		 1284 tasklet_kill(&sc->intr_tq);
1285 tasklet_kill(&sc->bcon_tasklet);
f078f209 1286
9c84b797
S		 1287 if (!(sc->sc_flags & SC_OP_INVALID))
1288 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1289
9c84b797
S		 1290 /* cleanup tx queues */
1291 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1292 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1293 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1294
1295 ath9k_hw_detach(sc->sc_ah);
826d2680 1296 ath9k_exit_debug(sc);
3cbb5dd7 1297 ath9k_ps_restore(sc);
f078f209
LR		 1298}
1299
ff37e337
S		 1300static int ath_init(u16 devid, struct ath_softc *sc)
1301{
1302 struct ath_hal *ah = NULL;
1303 int status;
1304 int error = 0, i;
1305 int csz = 0;
1306
1307 /* XXX: hardware will not be ready until ath_open() being called */
1308 sc->sc_flags |= SC_OP_INVALID;
88b126af 1309
826d2680
S		 1310 if (ath9k_init_debug(sc) < 0)
1311 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337
S		 1312
1313 spin_lock_init(&sc->sc_resetlock);
aa33de09 1314 mutex_init(&sc->mutex);
ff37e337
S		 1315 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1316 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1317 (unsigned long)sc);
1318
1319 /*
1320 * Cache line size is used to size and align various
1321 * structures used to communicate with the hardware.
1322 */
88d15707 1323 ath_read_cachesize(sc, &csz);
ff37e337
S		 1324 /* XXX assert csz is non-zero */
1325 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1326
1327 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1328 if (ah == NULL) {
1329 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1330 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1331 error = -ENXIO;
1332 goto bad;
1333 }
1334 sc->sc_ah = ah;
1335
1336 /* Get the hardware key cache size. */
1337 sc->sc_keymax = ah->ah_caps.keycache_size;
1338 if (sc->sc_keymax > ATH_KEYMAX) {
1339 DPRINTF(sc, ATH_DBG_KEYCACHE,
04bd4638
S		 1340 "Warning, using only %u entries in %u key cache\n",
1341 ATH_KEYMAX, sc->sc_keymax);
ff37e337
S		 1342 sc->sc_keymax = ATH_KEYMAX;
1343 }
1344
1345 /*
1346 * Reset the key cache since some parts do not
1347 * reset the contents on initial power up.
1348 */
1349 for (i = 0; i < sc->sc_keymax; i++)
1350 ath9k_hw_keyreset(ah, (u16) i);
ff37e337
S		 1351
1352 /* Collect the channel list using the default country code */
1353
1354 error = ath_setup_channels(sc);
1355 if (error)
1356 goto bad;
1357
1358 /* default to MONITOR mode */
d97809db
CM		 1359 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1360
ff37e337
S		 1361
1362 /* Setup rate tables */
1363
1364 ath_rate_attach(sc);
1365 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1366 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1367
1368 /*
1369 * Allocate hardware transmit queues: one queue for
1370 * beacon frames and one data queue for each QoS
1371 * priority. Note that the hal handles reseting
1372 * these queues at the needed time.
1373 */
b77f483f
S		 1374 sc->beacon.beaconq = ath_beaconq_setup(ah);
1375 if (sc->beacon.beaconq == -1) {
ff37e337 1376 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1377 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1378 error = -EIO;
1379 goto bad2;
1380 }
b77f483f
S		 1381 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1382 if (sc->beacon.cabq == NULL) {
ff37e337 1383 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1384 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1385 error = -EIO;
1386 goto bad2;
1387 }
1388
1389 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1390 ath_cabq_update(sc);
1391
b77f483f
S		 1392 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1393 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1394
1395 /* Setup data queues */
1396 /* NB: ensure BK queue is the lowest priority h/w queue */
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1406 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1407 error = -EIO;
1408 goto bad2;
1409 }
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1412 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1413 error = -EIO;
1414 goto bad2;
1415 }
1416 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1417 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1418 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1419 error = -EIO;
1420 goto bad2;
1421 }
1422
1423 /* Initializes the noise floor to a reasonable default value.
1424 * Later on this will be updated during ANI processing. */
1425
1426 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1427 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1428
1429 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1430 ATH9K_CIPHER_TKIP, NULL)) {
1431 /*
1432 * Whether we should enable h/w TKIP MIC.
1433 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1434 * report WMM capable, so it's always safe to turn on
1435 * TKIP MIC in this case.
1436 */
1437 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1438 0, 1, NULL);
1439 }
1440
1441 /*
1442 * Check whether the separate key cache entries
1443 * are required to handle both tx+rx MIC keys.
1444 * With split mic keys the number of stations is limited
1445 * to 27 otherwise 59.
1446 */
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)
1449 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_MIC, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1452 0, NULL))
1453 sc->sc_splitmic = 1;
1454
1455 /* turn on mcast key search if possible */
1456 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1457 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1458 1, NULL);
1459
1460 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1461 sc->sc_config.txpowlimit_override = 0;
1462
1463 /* 11n Capabilities */
1464 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1465 sc->sc_flags |= SC_OP_TXAGGR;
1466 sc->sc_flags |= SC_OP_RXAGGR;
1467 }
1468
1469 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1470 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1471
1472 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1473 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337
S		 1474
1475 ath9k_hw_getmac(ah, sc->sc_myaddr);
1476 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1477 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1478 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1479 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1480 }
1481
b77f483f 1482 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1483
1484 /* initialize beacon slots */
b77f483f
S		 1485 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1486 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
ff37e337
S		 1487
1488 /* save MISC configurations */
1489 sc->sc_config.swBeaconProcess = 1;
1490
ff37e337
S		 1491 /* setup channels and rates */
1492
1493 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1494 sc->channels[IEEE80211_BAND_2GHZ];
1495 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1496 sc->rates[IEEE80211_BAND_2GHZ];
1497 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1498
1499 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1500 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1501 sc->channels[IEEE80211_BAND_5GHZ];
1502 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1503 sc->rates[IEEE80211_BAND_5GHZ];
1504 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1505 }
1506
c97c92d9
VT		 1507 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1508 ath9k_hw_btcoex_enable(sc->sc_ah);
1509
ff37e337
S		 1510 return 0;
1511bad2:
1512 /* cleanup tx queues */
1513 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1514 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1515 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1516bad:
1517 if (ah)
1518 ath9k_hw_detach(ah);
1519
1520 return error;
1521}
1522
6baff7f9 1523int ath_attach(u16 devid, struct ath_softc *sc)
f078f209 1524{
8feceb67
VT		 1525 struct ieee80211_hw *hw = sc->hw;
1526 int error = 0;
f078f209 1527
04bd4638 1528 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
f078f209 1529
8feceb67
VT		 1530 error = ath_init(devid, sc);
1531 if (error != 0)
1532 return error;
f078f209 1533
8feceb67 1534 /* get mac address from hardware and set in mac80211 */
f078f209 1535
8feceb67 1536 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
f078f209 1537
9c84b797
S		 1538 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1539 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1540 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1541 IEEE80211_HW_AMPDU_AGGREGATION |
1542 IEEE80211_HW_SUPPORTS_PS |
1543 IEEE80211_HW_PS_NULLFUNC_STACK;
f078f209 1544
0ced0e17
JM		 1545 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1546 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1547
9c84b797
S		 1548 hw->wiphy->interface_modes =
1549 BIT(NL80211_IFTYPE_AP) |
1550 BIT(NL80211_IFTYPE_STATION) |
1551 BIT(NL80211_IFTYPE_ADHOC);
f078f209 1552
8feceb67 1553 hw->queues = 4;
e63835b0
S		 1554 hw->max_rates = 4;
1555 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1556 hw->sta_data_size = sizeof(struct ath_node);
5640b08e 1557 hw->vif_data_size = sizeof(struct ath_vap);
f078f209 1558
8feceb67 1559 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1560
9c84b797
S		 1561 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1562 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1563 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1564 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1565 }
1566
1567 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1568 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1569 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1570 &sc->sbands[IEEE80211_BAND_5GHZ];
1571
db93e7b5
SB		 1572 /* initialize tx/rx engine */
1573 error = ath_tx_init(sc, ATH_TXBUF);
1574 if (error != 0)
1575 goto detach;
8feceb67 1576
db93e7b5
SB		 1577 error = ath_rx_init(sc, ATH_RXBUF);
1578 if (error != 0)
1579 goto detach;
8feceb67 1580
e97275cb 1581#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
500c064d
VT		 1582 /* Initialze h/w Rfkill */
1583 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1584 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1585
1586 /* Initialize s/w rfkill */
1587 if (ath_init_sw_rfkill(sc))
1588 goto detach;
1589#endif
1590
db93e7b5 1591 error = ieee80211_register_hw(hw);
8feceb67 1592
db93e7b5
SB		 1593 /* Initialize LED control */
1594 ath_init_leds(sc);
8feceb67
VT		 1595
1596 return 0;
1597detach:
1598 ath_detach(sc);
8feceb67 1599 return error;
f078f209
LR		 1600}
1601
ff37e337
S		 1602int ath_reset(struct ath_softc *sc, bool retry_tx)
1603{
1604 struct ath_hal *ah = sc->sc_ah;
030bb495 1605 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1606 int r;
ff37e337
S		 1607
1608 ath9k_hw_set_interrupts(ah, 0);
043a0405 1609 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1610 ath_stoprecv(sc);
1611 ath_flushrecv(sc);
1612
1613 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1614 r = ath9k_hw_reset(ah, sc->sc_ah->ah_curchan, false);
1615 if (r)
ff37e337 1616 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1617 "Unable to reset hardware; reset status %u\n", r);
ff37e337
S		 1618 spin_unlock_bh(&sc->sc_resetlock);
1619
1620 if (ath_startrecv(sc) != 0)
04bd4638 1621 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1622
1623 /*
1624 * We may be doing a reset in response to a request
1625 * that changes the channel so update any state that
1626 * might change as a result.
1627 */
ce111bad 1628 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1629
1630 ath_update_txpow(sc);
1631
1632 if (sc->sc_flags & SC_OP_BEACONS)
1633 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1634
1635 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1636
1637 if (retry_tx) {
1638 int i;
1639 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1640 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1641 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1642 ath_txq_schedule(sc, &sc->tx.txq[i]);
1643 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1644 }
1645 }
1646 }
1647
ae8d2858 1648 return r;
ff37e337
S		 1649}
1650
1651/*
1652 * This function will allocate both the DMA descriptor structure, and the
1653 * buffers it contains. These are used to contain the descriptors used
1654 * by the system.
1655*/
1656int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1657 struct list_head *head, const char *name,
1658 int nbuf, int ndesc)
1659{
1660#define DS2PHYS(_dd, _ds) \
1661 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1662#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1663#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1664
1665 struct ath_desc *ds;
1666 struct ath_buf *bf;
1667 int i, bsize, error;
1668
04bd4638
S		 1669 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1670 name, nbuf, ndesc);
ff37e337
S		 1671
1672 /* ath_desc must be a multiple of DWORDs */
1673 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1674 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1675 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1676 error = -ENOMEM;
1677 goto fail;
1678 }
1679
1680 dd->dd_name = name;
1681 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1682
1683 /*
1684 * Need additional DMA memory because we can't use
1685 * descriptors that cross the 4K page boundary. Assume
1686 * one skipped descriptor per 4K page.
1687 */
1688 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1689 u32 ndesc_skipped =
1690 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1691 u32 dma_len;
1692
1693 while (ndesc_skipped) {
1694 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1695 dd->dd_desc_len += dma_len;
1696
1697 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1698 };
1699 }
1700
1701 /* allocate descriptors */
7da3c55c
GJ		 1702 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1703 &dd->dd_desc_paddr, GFP_ATOMIC);
ff37e337
S		 1704 if (dd->dd_desc == NULL) {
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708 ds = dd->dd_desc;
04bd4638
S		 1709 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1710 dd->dd_name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1711 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1712
1713 /* allocate buffers */
1714 bsize = sizeof(struct ath_buf) * nbuf;
1715 bf = kmalloc(bsize, GFP_KERNEL);
1716 if (bf == NULL) {
1717 error = -ENOMEM;
1718 goto fail2;
1719 }
1720 memset(bf, 0, bsize);
1721 dd->dd_bufptr = bf;
1722
1723 INIT_LIST_HEAD(head);
1724 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1725 bf->bf_desc = ds;
1726 bf->bf_daddr = DS2PHYS(dd, ds);
1727
1728 if (!(sc->sc_ah->ah_caps.hw_caps &
1729 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1730 /*
1731 * Skip descriptor addresses which can cause 4KB
1732 * boundary crossing (addr + length) with a 32 dword
1733 * descriptor fetch.
1734 */
1735 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1736 ASSERT((caddr_t) bf->bf_desc <
1737 ((caddr_t) dd->dd_desc +
1738 dd->dd_desc_len));
1739
1740 ds += ndesc;
1741 bf->bf_desc = ds;
1742 bf->bf_daddr = DS2PHYS(dd, ds);
1743 }
1744 }
1745 list_add_tail(&bf->list, head);
1746 }
1747 return 0;
1748fail2:
7da3c55c
GJ		 1749 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1750 dd->dd_desc_paddr);
ff37e337
S		 1751fail:
1752 memset(dd, 0, sizeof(*dd));
1753 return error;
1754#undef ATH_DESC_4KB_BOUND_CHECK
1755#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1756#undef DS2PHYS
1757}
1758
1759void ath_descdma_cleanup(struct ath_softc *sc,
1760 struct ath_descdma *dd,
1761 struct list_head *head)
1762{
7da3c55c
GJ		 1763 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1764 dd->dd_desc_paddr);
ff37e337
S		 1765
1766 INIT_LIST_HEAD(head);
1767 kfree(dd->dd_bufptr);
1768 memset(dd, 0, sizeof(*dd));
1769}
1770
1771int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1772{
1773 int qnum;
1774
1775 switch (queue) {
1776 case 0:
b77f483f 1777 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1778 break;
1779 case 1:
b77f483f 1780 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1781 break;
1782 case 2:
b77f483f 1783 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1784 break;
1785 case 3:
b77f483f 1786 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1787 break;
1788 default:
b77f483f 1789 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1790 break;
1791 }
1792
1793 return qnum;
1794}
1795
1796int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1797{
1798 int qnum;
1799
1800 switch (queue) {
1801 case ATH9K_WME_AC_VO:
1802 qnum = 0;
1803 break;
1804 case ATH9K_WME_AC_VI:
1805 qnum = 1;
1806 break;
1807 case ATH9K_WME_AC_BE:
1808 qnum = 2;
1809 break;
1810 case ATH9K_WME_AC_BK:
1811 qnum = 3;
1812 break;
1813 default:
1814 qnum = -1;
1815 break;
1816 }
1817
1818 return qnum;
1819}
1820
1821/**********************/
1822/* mac80211 callbacks */
1823/**********************/
1824
8feceb67 1825static int ath9k_start(struct ieee80211_hw *hw)
f078f209
LR		 1826{
1827 struct ath_softc *sc = hw->priv;
8feceb67 1828 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1829 struct ath9k_channel *init_channel;
ae8d2858 1830 int r, pos;
f078f209 1831
04bd4638
S		 1832 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1833 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1834
8feceb67 1835 /* setup initial channel */
f078f209 1836
8feceb67
VT		 1837 pos = ath_get_channel(sc, curchan);
1838 if (pos == -1) {
04bd4638 1839 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
ae8d2858 1840 return -EINVAL;
f078f209
LR		 1841 }
1842
99405f93 1843 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67
VT		 1844 sc->sc_ah->ah_channels[pos].chanmode =
1845 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
ff37e337
S		 1846 init_channel = &sc->sc_ah->ah_channels[pos];
1847
1848 /* Reset SERDES registers */
1849 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1850
1851 /*
1852 * The basic interface to setting the hardware in a good
1853 * state is ``reset''. On return the hardware is known to
1854 * be powered up and with interrupts disabled. This must
1855 * be followed by initialization of the appropriate bits
1856 * and then setup of the interrupt mask.
1857 */
1858 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1859 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1860 if (r) {
ff37e337 1861 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858
LR		 1862 "Unable to reset hardware; reset status %u "
1863 "(freq %u MHz)\n", r,
1864 curchan->center_freq);
ff37e337 1865 spin_unlock_bh(&sc->sc_resetlock);
ae8d2858 1866 return r;
ff37e337
S		 1867 }
1868 spin_unlock_bh(&sc->sc_resetlock);
1869
1870 /*
1871 * This is needed only to setup initial state
1872 * but it's best done after a reset.
1873 */
1874 ath_update_txpow(sc);
8feceb67 1875
ff37e337
S		 1876 /*
1877 * Setup the hardware after reset:
1878 * The receive engine is set going.
1879 * Frame transmit is handled entirely
1880 * in the frame output path; there's nothing to do
1881 * here except setup the interrupt mask.
1882 */
1883 if (ath_startrecv(sc) != 0) {
8feceb67 1884 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1885 "Unable to start recv logic\n");
ae8d2858 1886 return -EIO;
f078f209 1887 }
8feceb67 1888
ff37e337
S		 1889 /* Setup our intr mask. */
1890 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1891 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1892 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1893
1894 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1895 sc->sc_imask |= ATH9K_INT_GTT;
1896
1897 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1898 sc->sc_imask |= ATH9K_INT_CST;
1899
1900 /*
1901 * Enable MIB interrupts when there are hardware phy counters.
1902 * Note we only do this (at the moment) for station mode.
1903 */
1904 if (ath9k_hw_phycounters(sc->sc_ah) &&
d97809db
CM		 1905 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1906 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
ff37e337
S		 1907 sc->sc_imask |= ATH9K_INT_MIB;
1908 /*
1909 * Some hardware processes the TIM IE and fires an
1910 * interrupt when the TIM bit is set. For hardware
1911 * that does, if not overridden by configuration,
1912 * enable the TIM interrupt when operating as station.
1913 */
1914 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
d97809db 1915 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
ff37e337
S		 1916 !sc->sc_config.swBeaconProcess)
1917 sc->sc_imask |= ATH9K_INT_TIM;
1918
ce111bad 1919 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1920
1921 sc->sc_flags &= ~SC_OP_INVALID;
1922
1923 /* Disable BMISS interrupt when we're not associated */
1924 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1925 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1926
1927 ieee80211_wake_queues(sc->hw);
1928
e97275cb 1929#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
ae8d2858 1930 r = ath_start_rfkill_poll(sc);
500c064d 1931#endif
ae8d2858 1932 return r;
f078f209
LR		 1933}
1934
8feceb67
VT		 1935static int ath9k_tx(struct ieee80211_hw *hw,
1936 struct sk_buff *skb)
f078f209 1937{
528f0c6b 1938 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
f078f209 1939 struct ath_softc *sc = hw->priv;
528f0c6b 1940 struct ath_tx_control txctl;
8feceb67 1941 int hdrlen, padsize;
528f0c6b
S		 1942
1943 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1944
8feceb67
VT		 1945 /*
1946 * As a temporary workaround, assign seq# here; this will likely need
1947 * to be cleaned up to work better with Beacon transmission and virtual
1948 * BSSes.
1949 */
1950 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1951 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1952 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1953 sc->tx.seq_no += 0x10;
8feceb67 1954 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1955 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1956 }
f078f209 1957
8feceb67
VT		 1958 /* Add the padding after the header if this is not already done */
1959 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1960 if (hdrlen & 3) {
1961 padsize = hdrlen % 4;
1962 if (skb_headroom(skb) < padsize)
1963 return -1;
1964 skb_push(skb, padsize);
1965 memmove(skb->data, skb->data + padsize, hdrlen);
1966 }
1967
528f0c6b
S		 1968 /* Check if a tx queue is available */
1969
1970 txctl.txq = ath_test_get_txq(sc, skb);
1971 if (!txctl.txq)
1972 goto exit;
1973
04bd4638 1974 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1975
528f0c6b 1976 if (ath_tx_start(sc, skb, &txctl) != 0) {
04bd4638 1977 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1978 goto exit;
8feceb67
VT		 1979 }
1980
528f0c6b
S		 1981 return 0;
1982exit:
1983 dev_kfree_skb_any(skb);
8feceb67 1984 return 0;
f078f209
LR		 1985}
1986
8feceb67 1987static void ath9k_stop(struct ieee80211_hw *hw)
f078f209
LR		 1988{
1989 struct ath_softc *sc = hw->priv;
f078f209 1990
9c84b797 1991 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 1992 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 1993 return;
1994 }
8feceb67 1995
04bd4638 1996 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
ff37e337
S		 1997
1998 ieee80211_stop_queues(sc->hw);
1999
2000 /* make sure h/w will not generate any interrupt
2001 * before setting the invalid flag. */
2002 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2003
2004 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2005 ath_drain_all_txq(sc, false);
ff37e337
S		 2006 ath_stoprecv(sc);
2007 ath9k_hw_phy_disable(sc->sc_ah);
2008 } else
b77f483f 2009 sc->rx.rxlink = NULL;
ff37e337
S		 2010
2011#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2012 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2013 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2014#endif
2015 /* disable HAL and put h/w to sleep */
2016 ath9k_hw_disable(sc->sc_ah);
2017 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2018
2019 sc->sc_flags |= SC_OP_INVALID;
500c064d 2020
04bd4638 2021 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2022}
2023
8feceb67
VT		 2024static int ath9k_add_interface(struct ieee80211_hw *hw,
2025 struct ieee80211_if_init_conf *conf)
f078f209
LR		 2026{
2027 struct ath_softc *sc = hw->priv;
5640b08e 2028 struct ath_vap *avp = (void *)conf->vif->drv_priv;
d97809db 2029 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
f078f209 2030
8feceb67
VT		 2031 /* Support only vap for now */
2032
2033 if (sc->sc_nvaps)
2034 return -ENOBUFS;
2035
2036 switch (conf->type) {
05c914fe 2037 case NL80211_IFTYPE_STATION:
d97809db 2038 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2039 break;
05c914fe 2040 case NL80211_IFTYPE_ADHOC:
d97809db 2041 ic_opmode = NL80211_IFTYPE_ADHOC;
f078f209 2042 break;
05c914fe 2043 case NL80211_IFTYPE_AP:
d97809db 2044 ic_opmode = NL80211_IFTYPE_AP;
f078f209
LR		 2045 break;
2046 default:
2047 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2048 "Interface type %d not yet supported\n", conf->type);
8feceb67 2049 return -EOPNOTSUPP;
f078f209
LR		 2050 }
2051
04bd4638 2052 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
8feceb67 2053
5640b08e
S		 2054 /* Set the VAP opmode */
2055 avp->av_opmode = ic_opmode;
2056 avp->av_bslot = -1;
2057
d97809db 2058 if (ic_opmode == NL80211_IFTYPE_AP)
5640b08e
S		 2059 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2060
2061 sc->sc_vaps[0] = conf->vif;
2062 sc->sc_nvaps++;
2063
2064 /* Set the device opmode */
2065 sc->sc_ah->ah_opmode = ic_opmode;
2066
6f255425
LR		 2067 if (conf->type == NL80211_IFTYPE_AP) {
2068 /* TODO: is this a suitable place to start ANI for AP mode? */
2069 /* Start ANI */
2070 mod_timer(&sc->sc_ani.timer,
2071 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2072 }
2073
8feceb67 2074 return 0;
f078f209
LR		 2075}
2076
8feceb67
VT		 2077static void ath9k_remove_interface(struct ieee80211_hw *hw,
2078 struct ieee80211_if_init_conf *conf)
f078f209 2079{
8feceb67 2080 struct ath_softc *sc = hw->priv;
5640b08e 2081 struct ath_vap *avp = (void *)conf->vif->drv_priv;
f078f209 2082
04bd4638 2083 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2084
6f255425
LR		 2085 /* Stop ANI */
2086 del_timer_sync(&sc->sc_ani.timer);
580f0b8a 2087
8feceb67 2088 /* Reclaim beacon resources */
d97809db
CM		 2089 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2090 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
b77f483f 2091 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2092 ath_beacon_return(sc, avp);
580f0b8a 2093 }
f078f209 2094
8feceb67 2095 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2096
5640b08e
S		 2097 sc->sc_vaps[0] = NULL;
2098 sc->sc_nvaps--;
f078f209
LR		 2099}
2100
e8975581 2101static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2102{
8feceb67 2103 struct ath_softc *sc = hw->priv;
e8975581 2104 struct ieee80211_conf *conf = &hw->conf;
f078f209 2105
aa33de09 2106 mutex_lock(&sc->mutex);
3cbb5dd7
VN		 2107 if (changed & IEEE80211_CONF_CHANGE_PS) {
2108 if (conf->flags & IEEE80211_CONF_PS) {
2109 if ((sc->sc_imask & ATH9K_INT_TIM_TIMER) == 0) {
2110 sc->sc_imask |= ATH9K_INT_TIM_TIMER;
2111 ath9k_hw_set_interrupts(sc->sc_ah,
2112 sc->sc_imask);
2113 }
2114 ath9k_hw_setrxabort(sc->sc_ah, 1);
2115 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2116 } else {
2117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2118 ath9k_hw_setrxabort(sc->sc_ah, 0);
2119 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2120 if (sc->sc_imask & ATH9K_INT_TIM_TIMER) {
2121 sc->sc_imask &= ~ATH9K_INT_TIM_TIMER;
2122 ath9k_hw_set_interrupts(sc->sc_ah,
2123 sc->sc_imask);
2124 }
2125 }
2126 }
2127
4797938c 2128 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93
S		 2129 struct ieee80211_channel *curchan = hw->conf.channel;
2130 int pos;
ae5eb026 2131
04bd4638
S		 2132 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2133 curchan->center_freq);
f078f209 2134
99405f93
S		 2135 pos = ath_get_channel(sc, curchan);
2136 if (pos == -1) {
04bd4638
S		 2137 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2138 curchan->center_freq);
aa33de09 2139 mutex_unlock(&sc->mutex);
99405f93
S		 2140 return -EINVAL;
2141 }
f078f209 2142
99405f93 2143 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
8feceb67 2144 sc->sc_ah->ah_channels[pos].chanmode =
99405f93
S		 2145 (curchan->band == IEEE80211_BAND_2GHZ) ?
2146 CHANNEL_G : CHANNEL_A;
2147
ecf70441
LR		 2148 if (conf_is_ht(conf)) {
2149 if (conf_is_ht40(conf))
094d05dc 2150 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
e11602b7
S		 2151
2152 sc->sc_ah->ah_channels[pos].chanmode =
2153 ath_get_extchanmode(sc, curchan,
4797938c 2154 conf->channel_type);
e11602b7
S		 2155 }
2156
ecf70441 2157 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2158
e11602b7 2159 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
04bd4638 2160 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2161 mutex_unlock(&sc->mutex);
e11602b7
S		 2162 return -EINVAL;
2163 }
094d05dc 2164 }
f078f209 2165
5c020dc6
LR		 2166 if (changed & IEEE80211_CONF_CHANGE_POWER)
2167 sc->sc_config.txpowlimit = 2 * conf->power_level;
f078f209 2168
aa33de09 2169 mutex_unlock(&sc->mutex);
f078f209
LR		 2170 return 0;
2171}
2172
8feceb67
VT		 2173static int ath9k_config_interface(struct ieee80211_hw *hw,
2174 struct ieee80211_vif *vif,
2175 struct ieee80211_if_conf *conf)
c83be688 2176{
8feceb67
VT		 2177 struct ath_softc *sc = hw->priv;
2178 struct ath_hal *ah = sc->sc_ah;
5640b08e 2179 struct ath_vap *avp = (void *)vif->drv_priv;
8feceb67
VT		 2180 u32 rfilt = 0;
2181 int error, i;
c83be688 2182
8feceb67
VT		 2183 /* TODO: Need to decide which hw opmode to use for multi-interface
2184 * cases */
05c914fe 2185 if (vif->type == NL80211_IFTYPE_AP &&
d97809db
CM		 2186 ah->ah_opmode != NL80211_IFTYPE_AP) {
2187 ah->ah_opmode = NL80211_IFTYPE_STATION;
8feceb67
VT		 2188 ath9k_hw_setopmode(ah);
2189 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2190 /* Request full reset to get hw opmode changed properly */
2191 sc->sc_flags |= SC_OP_FULL_RESET;
2192 }
c83be688 2193
8feceb67
VT		 2194 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2195 !is_zero_ether_addr(conf->bssid)) {
2196 switch (vif->type) {
05c914fe
JB		 2197 case NL80211_IFTYPE_STATION:
2198 case NL80211_IFTYPE_ADHOC:
8feceb67
VT		 2199 /* Set BSSID */
2200 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2201 sc->sc_curaid = 0;
2202 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2203 sc->sc_curaid);
c83be688 2204
8feceb67
VT		 2205 /* Set aggregation protection mode parameters */
2206 sc->sc_config.ath_aggr_prot = 0;
c83be688 2207
8feceb67 2208 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638
S		 2209 "RX filter 0x%x bssid %pM aid 0x%x\n",
2210 rfilt, sc->sc_curbssid, sc->sc_curaid);
c83be688 2211
8feceb67
VT		 2212 /* need to reconfigure the beacon */
2213 sc->sc_flags &= ~SC_OP_BEACONS ;
c83be688 2214
8feceb67
VT		 2215 break;
2216 default:
2217 break;
2218 }
2219 }
c83be688 2220
8feceb67 2221 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
05c914fe
JB		 2222 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2223 (vif->type == NL80211_IFTYPE_AP))) {
8feceb67
VT		 2224 /*
2225 * Allocate and setup the beacon frame.
2226 *
2227 * Stop any previous beacon DMA. This may be
2228 * necessary, for example, when an ibss merge
2229 * causes reconfiguration; we may be called
2230 * with beacon transmission active.
2231 */
b77f483f 2232 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
c83be688 2233
8feceb67
VT		 2234 error = ath_beacon_alloc(sc, 0);
2235 if (error != 0)
2236 return error;
c83be688 2237
8feceb67
VT		 2238 ath_beacon_sync(sc, 0);
2239 }
c83be688 2240
8feceb67 2241 /* Check for WLAN_CAPABILITY_PRIVACY ? */
d97809db 2242 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
8feceb67
VT		 2243 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2244 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2245 ath9k_hw_keysetmac(sc->sc_ah,
2246 (u16)i,
2247 sc->sc_curbssid);
2248 }
c83be688 2249
8feceb67 2250 /* Only legacy IBSS for now */
05c914fe 2251 if (vif->type == NL80211_IFTYPE_ADHOC)
8feceb67 2252 ath_update_chainmask(sc, 0);
f078f209 2253
8feceb67
VT		 2254 return 0;
2255}
f078f209 2256
8feceb67
VT		 2257#define SUPPORTED_FILTERS \
2258 (FIF_PROMISC_IN_BSS | \
2259 FIF_ALLMULTI | \
2260 FIF_CONTROL | \
2261 FIF_OTHER_BSS | \
2262 FIF_BCN_PRBRESP_PROMISC | \
2263 FIF_FCSFAIL)
c83be688 2264
8feceb67
VT		 2265/* FIXME: sc->sc_full_reset ? */
2266static void ath9k_configure_filter(struct ieee80211_hw *hw,
2267 unsigned int changed_flags,
2268 unsigned int *total_flags,
2269 int mc_count,
2270 struct dev_mc_list *mclist)
2271{
2272 struct ath_softc *sc = hw->priv;
2273 u32 rfilt;
f078f209 2274
8feceb67
VT		 2275 changed_flags &= SUPPORTED_FILTERS;
2276 *total_flags &= SUPPORTED_FILTERS;
f078f209 2277
b77f483f 2278 sc->rx.rxfilter = *total_flags;
8feceb67
VT		 2279 rfilt = ath_calcrxfilter(sc);
2280 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
f078f209 2281
8feceb67
VT		 2282 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2283 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2284 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2285 }
f078f209 2286
b77f483f 2287 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2288}
f078f209 2289
8feceb67
VT		 2290static void ath9k_sta_notify(struct ieee80211_hw *hw,
2291 struct ieee80211_vif *vif,
2292 enum sta_notify_cmd cmd,
17741cdc 2293 struct ieee80211_sta *sta)
8feceb67
VT		 2294{
2295 struct ath_softc *sc = hw->priv;
f078f209 2296
8feceb67
VT		 2297 switch (cmd) {
2298 case STA_NOTIFY_ADD:
5640b08e 2299 ath_node_attach(sc, sta);
8feceb67
VT		 2300 break;
2301 case STA_NOTIFY_REMOVE:
b5aa9bf9 2302 ath_node_detach(sc, sta);
8feceb67
VT		 2303 break;
2304 default:
2305 break;
2306 }
f078f209
LR		 2307}
2308
8feceb67
VT		 2309static int ath9k_conf_tx(struct ieee80211_hw *hw,
2310 u16 queue,
2311 const struct ieee80211_tx_queue_params *params)
f078f209 2312{
8feceb67
VT		 2313 struct ath_softc *sc = hw->priv;
2314 struct ath9k_tx_queue_info qi;
2315 int ret = 0, qnum;
f078f209 2316
8feceb67
VT		 2317 if (queue >= WME_NUM_AC)
2318 return 0;
f078f209 2319
8feceb67
VT		 2320 qi.tqi_aifs = params->aifs;
2321 qi.tqi_cwmin = params->cw_min;
2322 qi.tqi_cwmax = params->cw_max;
2323 qi.tqi_burstTime = params->txop;
2324 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2325
8feceb67 2326 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2327 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2328 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2329 queue, qnum, params->aifs, params->cw_min,
2330 params->cw_max, params->txop);
f078f209 2331
8feceb67
VT		 2332 ret = ath_txq_update(sc, qnum, &qi);
2333 if (ret)
04bd4638 2334 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2335
8feceb67
VT		 2336 return ret;
2337}
f078f209 2338
8feceb67
VT		 2339static int ath9k_set_key(struct ieee80211_hw *hw,
2340 enum set_key_cmd cmd,
dc822b5d
JB		 2341 struct ieee80211_vif *vif,
2342 struct ieee80211_sta *sta,
8feceb67
VT		 2343 struct ieee80211_key_conf *key)
2344{
2345 struct ath_softc *sc = hw->priv;
2346 int ret = 0;
f078f209 2347
3cbb5dd7 2348 ath9k_ps_wakeup(sc);
04bd4638 2349 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
f078f209 2350
8feceb67
VT		 2351 switch (cmd) {
2352 case SET_KEY:
dc822b5d 2353 ret = ath_key_config(sc, sta, key);
6ace2891
JM		 2354 if (ret >= 0) {
2355 key->hw_key_idx = ret;
8feceb67
VT		 2356 /* push IV and Michael MIC generation to stack */
2357 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2358 if (key->alg == ALG_TKIP)
2359 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2360 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2361 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2362 ret = 0;
8feceb67
VT		 2363 }
2364 break;
2365 case DISABLE_KEY:
2366 ath_key_delete(sc, key);
8feceb67
VT		 2367 break;
2368 default:
2369 ret = -EINVAL;
2370 }
f078f209 2371
3cbb5dd7 2372 ath9k_ps_restore(sc);
8feceb67
VT		 2373 return ret;
2374}
f078f209 2375
8feceb67
VT		 2376static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2377 struct ieee80211_vif *vif,
2378 struct ieee80211_bss_conf *bss_conf,
2379 u32 changed)
2380{
2381 struct ath_softc *sc = hw->priv;
f078f209 2382
8feceb67 2383 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2384 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2385 bss_conf->use_short_preamble);
2386 if (bss_conf->use_short_preamble)
2387 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2388 else
2389 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2390 }
f078f209 2391
8feceb67 2392 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2393 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2394 bss_conf->use_cts_prot);
2395 if (bss_conf->use_cts_prot &&
2396 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2397 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2398 else
2399 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2400 }
f078f209 2401
8feceb67 2402 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2403 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2404 bss_conf->assoc);
5640b08e 2405 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67
VT		 2406 }
2407}
f078f209 2408
8feceb67
VT		 2409static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2410{
2411 u64 tsf;
2412 struct ath_softc *sc = hw->priv;
2413 struct ath_hal *ah = sc->sc_ah;
f078f209 2414
8feceb67 2415 tsf = ath9k_hw_gettsf64(ah);
f078f209 2416
8feceb67
VT		 2417 return tsf;
2418}
f078f209 2419
8feceb67
VT		 2420static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2421{
2422 struct ath_softc *sc = hw->priv;
2423 struct ath_hal *ah = sc->sc_ah;
c83be688 2424
8feceb67
VT		 2425 ath9k_hw_reset_tsf(ah);
2426}
f078f209 2427
8feceb67
VT		 2428static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2429 enum ieee80211_ampdu_mlme_action action,
17741cdc
JB		 2430 struct ieee80211_sta *sta,
2431 u16 tid, u16 *ssn)
8feceb67
VT		 2432{
2433 struct ath_softc *sc = hw->priv;
2434 int ret = 0;
f078f209 2435
8feceb67
VT		 2436 switch (action) {
2437 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2438 if (!(sc->sc_flags & SC_OP_RXAGGR))
2439 ret = -ENOTSUPP;
8feceb67
VT		 2440 break;
2441 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2442 break;
2443 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2444 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2445 if (ret < 0)
2446 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2447 "Unable to start TX aggregation\n");
8feceb67 2448 else
17741cdc 2449 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2450 break;
2451 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2452 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2453 if (ret < 0)
2454 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2455 "Unable to stop TX aggregation\n");
f078f209 2456
17741cdc 2457 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2458 break;
8469cdef
S		 2459 case IEEE80211_AMPDU_TX_RESUME:
2460 ath_tx_aggr_resume(sc, sta, tid);
2461 break;
8feceb67 2462 default:
04bd4638 2463 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2464 }
2465
2466 return ret;
f078f209
LR		 2467}
2468
6baff7f9 2469struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2470 .tx = ath9k_tx,
2471 .start = ath9k_start,
2472 .stop = ath9k_stop,
2473 .add_interface = ath9k_add_interface,
2474 .remove_interface = ath9k_remove_interface,
2475 .config = ath9k_config,
2476 .config_interface = ath9k_config_interface,
2477 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2478 .sta_notify = ath9k_sta_notify,
2479 .conf_tx = ath9k_conf_tx,
8feceb67 2480 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2481 .set_key = ath9k_set_key,
8feceb67
VT		 2482 .get_tsf = ath9k_get_tsf,
2483 .reset_tsf = ath9k_reset_tsf,
4233df6b 2484 .ampdu_action = ath9k_ampdu_action,
8feceb67
VT		 2485};
2486
392dff83
BP		 2487static struct {
2488 u32 version;
2489 const char * name;
2490} ath_mac_bb_names[] = {
2491 { AR_SREV_VERSION_5416_PCI, "5416" },
2492 { AR_SREV_VERSION_5416_PCIE, "5418" },
2493 { AR_SREV_VERSION_9100, "9100" },
2494 { AR_SREV_VERSION_9160, "9160" },
2495 { AR_SREV_VERSION_9280, "9280" },
2496 { AR_SREV_VERSION_9285, "9285" }
2497};
2498
2499static struct {
2500 u16 version;
2501 const char * name;
2502} ath_rf_names[] = {
2503 { 0, "5133" },
2504 { AR_RAD5133_SREV_MAJOR, "5133" },
2505 { AR_RAD5122_SREV_MAJOR, "5122" },
2506 { AR_RAD2133_SREV_MAJOR, "2133" },
2507 { AR_RAD2122_SREV_MAJOR, "2122" }
2508};
2509
2510/*
2511 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2512 */
6baff7f9 2513const char *
392dff83
BP		 2514ath_mac_bb_name(u32 mac_bb_version)
2515{
2516 int i;
2517
2518 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2519 if (ath_mac_bb_names[i].version == mac_bb_version) {
2520 return ath_mac_bb_names[i].name;
2521 }
2522 }
2523
2524 return "????";
2525}
2526
2527/*
2528 * Return the RF name. "????" is returned if the RF is unknown.
2529 */
6baff7f9 2530const char *
392dff83
BP		 2531ath_rf_name(u16 rf_version)
2532{
2533 int i;
2534
2535 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2536 if (ath_rf_names[i].version == rf_version) {
2537 return ath_rf_names[i].name;
2538 }
2539 }
2540
2541 return "????";
2542}
2543
6baff7f9 2544static int __init ath9k_init(void)
f078f209 2545{
ca8a8560
VT		 2546 int error;
2547
f078f209
LR		 2548 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2549
ca8a8560
VT		 2550 /* Register rate control algorithm */
2551 error = ath_rate_control_register();
2552 if (error != 0) {
2553 printk(KERN_ERR
2554 "Unable to register rate control algorithm: %d\n",
2555 error);
6baff7f9 2556 goto err_out;
ca8a8560
VT		 2557 }
2558
6baff7f9
GJ		 2559 error = ath_pci_init();
2560 if (error < 0) {
f078f209
LR		 2561 printk(KERN_ERR
2562 "ath_pci: No devices found, driver not installed.\n");
6baff7f9
GJ		 2563 error = -ENODEV;
2564 goto err_rate_unregister;
f078f209
LR		 2565 }
2566
09329d37
GJ		 2567 error = ath_ahb_init();
2568 if (error < 0) {
2569 error = -ENODEV;
2570 goto err_pci_exit;
2571 }
2572
f078f209 2573 return 0;
6baff7f9 2574
09329d37
GJ		 2575 err_pci_exit:
2576 ath_pci_exit();
2577
6baff7f9
GJ		 2578 err_rate_unregister:
2579 ath_rate_control_unregister();
2580 err_out:
2581 return error;
f078f209 2582}
6baff7f9 2583module_init(ath9k_init);
f078f209 2584
6baff7f9 2585static void __exit ath9k_exit(void)
f078f209 2586{
09329d37 2587 ath_ahb_exit();
6baff7f9 2588 ath_pci_exit();
ca8a8560 2589 ath_rate_control_unregister();
04bd4638 2590 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2591}
6baff7f9 2592module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)