Commit | Line | Data |
---|---|---|
394cf0a1 S |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef EEPROM_H | |
18 | #define EEPROM_H | |
19 | ||
20 | #define AH_USE_EEPROM 0x1 | |
21 | ||
22 | #ifdef __BIG_ENDIAN | |
23 | #define AR5416_EEPROM_MAGIC 0x5aa5 | |
24 | #else | |
25 | #define AR5416_EEPROM_MAGIC 0xa55a | |
26 | #endif | |
27 | ||
28 | #define CTRY_DEBUG 0x1ff | |
29 | #define CTRY_DEFAULT 0 | |
30 | ||
31 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 | |
32 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 | |
33 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 | |
34 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 | |
35 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 | |
36 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 | |
37 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 | |
38 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 | |
39 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 | |
40 | ||
41 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 | |
42 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 | |
43 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 | |
44 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 | |
45 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 | |
46 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 | |
47 | ||
48 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 | |
49 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 | |
50 | ||
51 | #define AR5416_EEPROM_MAGIC_OFFSET 0x0 | |
52 | #define AR5416_EEPROM_S 2 | |
53 | #define AR5416_EEPROM_OFFSET 0x2000 | |
54 | #define AR5416_EEPROM_MAX 0xae0 | |
55 | ||
56 | #define AR5416_EEPROM_START_ADDR \ | |
57 | (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 | |
58 | ||
59 | #define SD_NO_CTL 0xE0 | |
60 | #define NO_CTL 0xff | |
61 | #define CTL_MODE_M 7 | |
62 | #define CTL_11A 0 | |
63 | #define CTL_11B 1 | |
64 | #define CTL_11G 2 | |
65 | #define CTL_2GHT20 5 | |
66 | #define CTL_5GHT20 6 | |
67 | #define CTL_2GHT40 7 | |
68 | #define CTL_5GHT40 8 | |
69 | ||
70 | #define EXT_ADDITIVE (0x8000) | |
71 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) | |
72 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) | |
73 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) | |
74 | ||
75 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 | |
76 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 | |
77 | ||
78 | #define AR_EEPROM_MAC(i) (0x1d+(i)) | |
79 | #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) | |
80 | #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) | |
81 | #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) | |
82 | ||
83 | #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c | |
84 | #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 | |
85 | #define AR_EEPROM_RFSILENT_POLARITY 0x0002 | |
86 | #define AR_EEPROM_RFSILENT_POLARITY_S 1 | |
87 | ||
88 | #define EEP_RFSILENT_ENABLED 0x0001 | |
89 | #define EEP_RFSILENT_ENABLED_S 0 | |
90 | #define EEP_RFSILENT_POLARITY 0x0002 | |
91 | #define EEP_RFSILENT_POLARITY_S 1 | |
92 | #define EEP_RFSILENT_GPIO_SEL 0x001c | |
93 | #define EEP_RFSILENT_GPIO_SEL_S 2 | |
94 | ||
95 | #define AR5416_OPFLAGS_11A 0x01 | |
96 | #define AR5416_OPFLAGS_11G 0x02 | |
97 | #define AR5416_OPFLAGS_N_5G_HT40 0x04 | |
98 | #define AR5416_OPFLAGS_N_2G_HT40 0x08 | |
99 | #define AR5416_OPFLAGS_N_5G_HT20 0x10 | |
100 | #define AR5416_OPFLAGS_N_2G_HT20 0x20 | |
101 | ||
102 | #define AR5416_EEP_NO_BACK_VER 0x1 | |
103 | #define AR5416_EEP_VER 0xE | |
104 | #define AR5416_EEP_VER_MINOR_MASK 0x0FFF | |
105 | #define AR5416_EEP_MINOR_VER_2 0x2 | |
106 | #define AR5416_EEP_MINOR_VER_3 0x3 | |
107 | #define AR5416_EEP_MINOR_VER_7 0x7 | |
108 | #define AR5416_EEP_MINOR_VER_9 0x9 | |
109 | #define AR5416_EEP_MINOR_VER_16 0x10 | |
110 | #define AR5416_EEP_MINOR_VER_17 0x11 | |
111 | #define AR5416_EEP_MINOR_VER_19 0x13 | |
112 | #define AR5416_EEP_MINOR_VER_20 0x14 | |
113 | ||
114 | #define AR5416_NUM_5G_CAL_PIERS 8 | |
115 | #define AR5416_NUM_2G_CAL_PIERS 4 | |
116 | #define AR5416_NUM_5G_20_TARGET_POWERS 8 | |
117 | #define AR5416_NUM_5G_40_TARGET_POWERS 8 | |
118 | #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 | |
119 | #define AR5416_NUM_2G_20_TARGET_POWERS 4 | |
120 | #define AR5416_NUM_2G_40_TARGET_POWERS 4 | |
121 | #define AR5416_NUM_CTLS 24 | |
122 | #define AR5416_NUM_BAND_EDGES 8 | |
123 | #define AR5416_NUM_PD_GAINS 4 | |
124 | #define AR5416_PD_GAINS_IN_MASK 4 | |
125 | #define AR5416_PD_GAIN_ICEPTS 5 | |
126 | #define AR5416_EEPROM_MODAL_SPURS 5 | |
127 | #define AR5416_MAX_RATE_POWER 63 | |
128 | #define AR5416_NUM_PDADC_VALUES 128 | |
129 | #define AR5416_BCHAN_UNUSED 0xFF | |
130 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 | |
131 | #define AR5416_MAX_CHAINS 3 | |
132 | #define AR5416_PWR_TABLE_OFFSET -5 | |
133 | ||
134 | /* Rx gain type values */ | |
135 | #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 | |
136 | #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 | |
137 | #define AR5416_EEP_RXGAIN_ORIG 2 | |
138 | ||
139 | /* Tx gain type values */ | |
140 | #define AR5416_EEP_TXGAIN_ORIGINAL 0 | |
141 | #define AR5416_EEP_TXGAIN_HIGH_POWER 1 | |
142 | ||
143 | #define AR5416_EEP4K_START_LOC 64 | |
144 | #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 | |
145 | #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 | |
146 | #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 | |
147 | #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 | |
148 | #define AR5416_EEP4K_NUM_CTLS 12 | |
149 | #define AR5416_EEP4K_NUM_BAND_EDGES 4 | |
150 | #define AR5416_EEP4K_NUM_PD_GAINS 2 | |
151 | #define AR5416_EEP4K_PD_GAINS_IN_MASK 4 | |
152 | #define AR5416_EEP4K_PD_GAIN_ICEPTS 5 | |
153 | #define AR5416_EEP4K_MAX_CHAINS 1 | |
154 | ||
155 | enum eeprom_param { | |
156 | EEP_NFTHRESH_5, | |
157 | EEP_NFTHRESH_2, | |
158 | EEP_MAC_MSW, | |
159 | EEP_MAC_MID, | |
160 | EEP_MAC_LSW, | |
161 | EEP_REG_0, | |
162 | EEP_REG_1, | |
163 | EEP_OP_CAP, | |
164 | EEP_OP_MODE, | |
165 | EEP_RF_SILENT, | |
166 | EEP_OB_5, | |
167 | EEP_DB_5, | |
168 | EEP_OB_2, | |
169 | EEP_DB_2, | |
170 | EEP_MINOR_REV, | |
171 | EEP_TX_MASK, | |
172 | EEP_RX_MASK, | |
173 | EEP_RXGAIN_TYPE, | |
174 | EEP_TXGAIN_TYPE, | |
175 | EEP_DAC_HPWR_5G, | |
176 | }; | |
177 | ||
178 | enum ar5416_rates { | |
179 | rate6mb, rate9mb, rate12mb, rate18mb, | |
180 | rate24mb, rate36mb, rate48mb, rate54mb, | |
181 | rate1l, rate2l, rate2s, rate5_5l, | |
182 | rate5_5s, rate11l, rate11s, rateXr, | |
183 | rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, | |
184 | rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, | |
185 | rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, | |
186 | rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, | |
187 | rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, | |
188 | Ar5416RateSize | |
189 | }; | |
190 | ||
191 | enum ath9k_hal_freq_band { | |
192 | ATH9K_HAL_FREQ_BAND_5GHZ = 0, | |
193 | ATH9K_HAL_FREQ_BAND_2GHZ = 1 | |
194 | }; | |
195 | ||
196 | struct base_eep_header { | |
197 | u16 length; | |
198 | u16 checksum; | |
199 | u16 version; | |
200 | u8 opCapFlags; | |
201 | u8 eepMisc; | |
202 | u16 regDmn[2]; | |
203 | u8 macAddr[6]; | |
204 | u8 rxMask; | |
205 | u8 txMask; | |
206 | u16 rfSilent; | |
207 | u16 blueToothOptions; | |
208 | u16 deviceCap; | |
209 | u32 binBuildNumber; | |
210 | u8 deviceType; | |
211 | u8 pwdclkind; | |
212 | u8 futureBase_1[2]; | |
213 | u8 rxGainType; | |
214 | u8 dacHiPwrMode_5G; | |
215 | u8 futureBase_2; | |
216 | u8 dacLpMode; | |
217 | u8 txGainType; | |
218 | u8 rcChainMask; | |
219 | u8 desiredScaleCCK; | |
220 | u8 futureBase_3[23]; | |
221 | } __packed; | |
222 | ||
223 | struct base_eep_header_4k { | |
224 | u16 length; | |
225 | u16 checksum; | |
226 | u16 version; | |
227 | u8 opCapFlags; | |
228 | u8 eepMisc; | |
229 | u16 regDmn[2]; | |
230 | u8 macAddr[6]; | |
231 | u8 rxMask; | |
232 | u8 txMask; | |
233 | u16 rfSilent; | |
234 | u16 blueToothOptions; | |
235 | u16 deviceCap; | |
236 | u32 binBuildNumber; | |
237 | u8 deviceType; | |
238 | u8 futureBase[1]; | |
239 | } __packed; | |
240 | ||
241 | ||
242 | struct spur_chan { | |
243 | u16 spurChan; | |
244 | u8 spurRangeLow; | |
245 | u8 spurRangeHigh; | |
246 | } __packed; | |
247 | ||
248 | struct modal_eep_header { | |
249 | u32 antCtrlChain[AR5416_MAX_CHAINS]; | |
250 | u32 antCtrlCommon; | |
251 | u8 antennaGainCh[AR5416_MAX_CHAINS]; | |
252 | u8 switchSettling; | |
253 | u8 txRxAttenCh[AR5416_MAX_CHAINS]; | |
254 | u8 rxTxMarginCh[AR5416_MAX_CHAINS]; | |
255 | u8 adcDesiredSize; | |
256 | u8 pgaDesiredSize; | |
257 | u8 xlnaGainCh[AR5416_MAX_CHAINS]; | |
258 | u8 txEndToXpaOff; | |
259 | u8 txEndToRxOn; | |
260 | u8 txFrameToXpaOn; | |
261 | u8 thresh62; | |
262 | u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; | |
263 | u8 xpdGain; | |
264 | u8 xpd; | |
265 | u8 iqCalICh[AR5416_MAX_CHAINS]; | |
266 | u8 iqCalQCh[AR5416_MAX_CHAINS]; | |
267 | u8 pdGainOverlap; | |
268 | u8 ob; | |
269 | u8 db; | |
270 | u8 xpaBiasLvl; | |
271 | u8 pwrDecreaseFor2Chain; | |
272 | u8 pwrDecreaseFor3Chain; | |
273 | u8 txFrameToDataStart; | |
274 | u8 txFrameToPaOn; | |
275 | u8 ht40PowerIncForPdadc; | |
276 | u8 bswAtten[AR5416_MAX_CHAINS]; | |
277 | u8 bswMargin[AR5416_MAX_CHAINS]; | |
278 | u8 swSettleHt40; | |
279 | u8 xatten2Db[AR5416_MAX_CHAINS]; | |
280 | u8 xatten2Margin[AR5416_MAX_CHAINS]; | |
281 | u8 ob_ch1; | |
282 | u8 db_ch1; | |
283 | u8 useAnt1:1, | |
284 | force_xpaon:1, | |
285 | local_bias:1, | |
286 | femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; | |
287 | u8 miscBits; | |
288 | u16 xpaBiasLvlFreq[3]; | |
289 | u8 futureModal[6]; | |
290 | ||
291 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | |
292 | } __packed; | |
293 | ||
294 | struct modal_eep_4k_header { | |
295 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; | |
296 | u32 antCtrlCommon; | |
297 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; | |
298 | u8 switchSettling; | |
299 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; | |
300 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; | |
301 | u8 adcDesiredSize; | |
302 | u8 pgaDesiredSize; | |
303 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; | |
304 | u8 txEndToXpaOff; | |
305 | u8 txEndToRxOn; | |
306 | u8 txFrameToXpaOn; | |
307 | u8 thresh62; | |
308 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; | |
309 | u8 xpdGain; | |
310 | u8 xpd; | |
311 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; | |
312 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; | |
313 | u8 pdGainOverlap; | |
314 | u8 ob_01; | |
315 | u8 db1_01; | |
316 | u8 xpaBiasLvl; | |
317 | u8 txFrameToDataStart; | |
318 | u8 txFrameToPaOn; | |
319 | u8 ht40PowerIncForPdadc; | |
320 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; | |
321 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; | |
322 | u8 swSettleHt40; | |
323 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; | |
324 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; | |
325 | u8 db2_01; | |
326 | u8 version; | |
327 | u16 ob_234; | |
328 | u16 db1_234; | |
329 | u16 db2_234; | |
330 | u8 futureModal[4]; | |
331 | ||
332 | struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; | |
333 | } __packed; | |
334 | ||
335 | ||
336 | struct cal_data_per_freq { | |
337 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | |
338 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; | |
339 | } __packed; | |
340 | ||
341 | struct cal_data_per_freq_4k { | |
342 | u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; | |
343 | u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; | |
344 | } __packed; | |
345 | ||
346 | struct cal_target_power_leg { | |
347 | u8 bChannel; | |
348 | u8 tPow2x[4]; | |
349 | } __packed; | |
350 | ||
351 | struct cal_target_power_ht { | |
352 | u8 bChannel; | |
353 | u8 tPow2x[8]; | |
354 | } __packed; | |
355 | ||
356 | ||
357 | #ifdef __BIG_ENDIAN_BITFIELD | |
358 | struct cal_ctl_edges { | |
359 | u8 bChannel; | |
360 | u8 flag:2, tPower:6; | |
361 | } __packed; | |
362 | #else | |
363 | struct cal_ctl_edges { | |
364 | u8 bChannel; | |
365 | u8 tPower:6, flag:2; | |
366 | } __packed; | |
367 | #endif | |
368 | ||
369 | struct cal_ctl_data { | |
370 | struct cal_ctl_edges | |
371 | ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; | |
372 | } __packed; | |
373 | ||
374 | struct cal_ctl_data_4k { | |
375 | struct cal_ctl_edges | |
376 | ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; | |
377 | } __packed; | |
378 | ||
379 | struct ar5416_eeprom_def { | |
380 | struct base_eep_header baseEepHeader; | |
381 | u8 custData[64]; | |
382 | struct modal_eep_header modalHeader[2]; | |
383 | u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; | |
384 | u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; | |
385 | struct cal_data_per_freq | |
386 | calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; | |
387 | struct cal_data_per_freq | |
388 | calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; | |
389 | struct cal_target_power_leg | |
390 | calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; | |
391 | struct cal_target_power_ht | |
392 | calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; | |
393 | struct cal_target_power_ht | |
394 | calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; | |
395 | struct cal_target_power_leg | |
396 | calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; | |
397 | struct cal_target_power_leg | |
398 | calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; | |
399 | struct cal_target_power_ht | |
400 | calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; | |
401 | struct cal_target_power_ht | |
402 | calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; | |
403 | u8 ctlIndex[AR5416_NUM_CTLS]; | |
404 | struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; | |
405 | u8 padding; | |
406 | } __packed; | |
407 | ||
408 | struct ar5416_eeprom_4k { | |
409 | struct base_eep_header_4k baseEepHeader; | |
410 | u8 custData[20]; | |
411 | struct modal_eep_4k_header modalHeader; | |
412 | u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; | |
413 | struct cal_data_per_freq_4k | |
414 | calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; | |
415 | struct cal_target_power_leg | |
416 | calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; | |
417 | struct cal_target_power_leg | |
418 | calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; | |
419 | struct cal_target_power_ht | |
420 | calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; | |
421 | struct cal_target_power_ht | |
422 | calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; | |
423 | u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; | |
424 | struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; | |
425 | u8 padding; | |
426 | } __packed; | |
427 | ||
428 | enum reg_ext_bitmap { | |
429 | REG_EXT_JAPAN_MIDBAND = 1, | |
430 | REG_EXT_FCC_DFS_HT40 = 2, | |
431 | REG_EXT_JAPAN_NONDFS_HT40 = 3, | |
432 | REG_EXT_JAPAN_DFS_HT40 = 4 | |
433 | }; | |
434 | ||
435 | struct ath9k_country_entry { | |
436 | u16 countryCode; | |
437 | u16 regDmnEnum; | |
438 | u16 regDmn5G; | |
439 | u16 regDmn2G; | |
440 | u8 isMultidomain; | |
441 | u8 iso[3]; | |
442 | }; | |
443 | ||
444 | enum hal_eep_map { | |
445 | EEP_MAP_DEFAULT = 0x0, | |
446 | EEP_MAP_4KBITS, | |
447 | EEP_MAP_MAX | |
448 | }; | |
449 | ||
e153789d S |
450 | struct eeprom_ops { |
451 | int (*check_eeprom)(struct ath_hw *hw); | |
452 | u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); | |
453 | bool (*fill_eeprom)(struct ath_hw *hw); | |
454 | int (*get_eeprom_ver)(struct ath_hw *hw); | |
455 | int (*get_eeprom_rev)(struct ath_hw *hw); | |
456 | u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); | |
457 | u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, | |
458 | struct ath9k_channel *chan); | |
459 | bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); | |
460 | void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); | |
461 | int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, | |
462 | u16 cfgCtl, u8 twiceAntennaReduction, | |
463 | u8 twiceMaxRegulatoryPower, u8 powerLimit); | |
464 | u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); | |
465 | }; | |
466 | ||
cbe61d8a S |
467 | #define ar5416_get_eep_ver(_ah) \ |
468 | (((_ah)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF) | |
469 | #define ar5416_get_eep_rev(_ah) \ | |
470 | (((_ah)->ah_eeprom.def.baseEepHeader.version) & 0xFFF) | |
394cf0a1 S |
471 | #define ar5416_get_ntxchains(_txchainmask) \ |
472 | (((_txchainmask >> 2) & 1) + \ | |
473 | ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) | |
474 | ||
cbe61d8a S |
475 | #define ar5416_get_eep4k_ver(_ah) \ |
476 | (((_ah)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF) | |
477 | #define ar5416_get_eep4k_rev(_ah) \ | |
478 | (((_ah)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF) | |
394cf0a1 | 479 | |
cbe61d8a | 480 | int ath9k_hw_set_txpower(struct ath_hw *ah, struct ath9k_channel *chan, |
394cf0a1 S |
481 | u16 cfgCtl, u8 twiceAntennaReduction, |
482 | u8 twiceMaxRegulatoryPower, u8 powerLimit); | |
cbe61d8a S |
483 | void ath9k_hw_set_addac(struct ath_hw *ah, struct ath9k_channel *chan); |
484 | bool ath9k_hw_set_power_per_rate_table(struct ath_hw *ah, | |
394cf0a1 S |
485 | struct ath9k_channel *chan, int16_t *ratesArray, |
486 | u16 cfgCtl, u8 AntennaReduction, | |
487 | u8 twiceMaxRegulatoryPower, u8 powerLimit); | |
cbe61d8a | 488 | bool ath9k_hw_set_power_cal_table(struct ath_hw *ah, |
394cf0a1 S |
489 | struct ath9k_channel *chan, |
490 | int16_t *pTxPowerIndexOffset); | |
cbe61d8a | 491 | bool ath9k_hw_eeprom_set_board_values(struct ath_hw *ah, |
394cf0a1 | 492 | struct ath9k_channel *chan); |
cbe61d8a | 493 | u16 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hw *ah, |
394cf0a1 | 494 | struct ath9k_channel *chan); |
cbe61d8a | 495 | u8 ath9k_hw_get_num_ant_config(struct ath_hw *ah, |
394cf0a1 | 496 | enum ieee80211_band freq_band); |
cbe61d8a S |
497 | u16 ath9k_hw_eeprom_get_spur_chan(struct ath_hw *ah, u16 i, bool is2GHz); |
498 | u32 ath9k_hw_get_eeprom(struct ath_hw *ah, enum eeprom_param param); | |
499 | int ath9k_hw_eeprom_attach(struct ath_hw *ah); | |
394cf0a1 S |
500 | |
501 | #endif /* EEPROM_H */ |