Commit | Line | Data |
---|---|---|
f1dc5600 S |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f1dc5600 | 18 | |
f1dc5600 S |
19 | /* We can tune this as we go by monitoring really low values */ |
20 | #define ATH9K_NF_TOO_LOW -60 | |
21 | ||
22 | /* AR5416 may return very high value (like -31 dBm), in those cases the nf | |
23 | * is incorrect and we should use the static NF value. Later we can try to | |
24 | * find out why they are reporting these values */ | |
25 | ||
cbe61d8a | 26 | static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) |
f1dc5600 S |
27 | { |
28 | if (nf > ATH9K_NF_TOO_LOW) { | |
04bd4638 S |
29 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
30 | "noise floor value detected (%d) is " | |
f1dc5600 S |
31 | "lower than what we think is a " |
32 | "reasonable value (%d)\n", | |
04bd4638 | 33 | nf, ATH9K_NF_TOO_LOW); |
f1dc5600 S |
34 | return false; |
35 | } | |
36 | return true; | |
37 | } | |
38 | ||
39 | static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer) | |
40 | { | |
41 | int16_t nfval; | |
42 | int16_t sort[ATH9K_NF_CAL_HIST_MAX]; | |
43 | int i, j; | |
44 | ||
45 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++) | |
46 | sort[i] = nfCalBuffer[i]; | |
47 | ||
48 | for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) { | |
49 | for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) { | |
50 | if (sort[j] > sort[j - 1]) { | |
51 | nfval = sort[j]; | |
52 | sort[j] = sort[j - 1]; | |
53 | sort[j - 1] = nfval; | |
54 | } | |
55 | } | |
56 | } | |
57 | nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1]; | |
58 | ||
59 | return nfval; | |
60 | } | |
61 | ||
62 | static void ath9k_hw_update_nfcal_hist_buffer(struct ath9k_nfcal_hist *h, | |
63 | int16_t *nfarray) | |
64 | { | |
65 | int i; | |
66 | ||
67 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
68 | h[i].nfCalBuffer[h[i].currIndex] = nfarray[i]; | |
69 | ||
70 | if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX) | |
71 | h[i].currIndex = 0; | |
72 | ||
73 | if (h[i].invalidNFcount > 0) { | |
74 | if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE || | |
75 | nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) { | |
76 | h[i].invalidNFcount = ATH9K_NF_CAL_HIST_MAX; | |
77 | } else { | |
78 | h[i].invalidNFcount--; | |
79 | h[i].privNF = nfarray[i]; | |
80 | } | |
81 | } else { | |
82 | h[i].privNF = | |
83 | ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer); | |
84 | } | |
85 | } | |
86 | return; | |
87 | } | |
88 | ||
cbe61d8a | 89 | static void ath9k_hw_do_getnf(struct ath_hw *ah, |
f1dc5600 S |
90 | int16_t nfarray[NUM_NF_READINGS]) |
91 | { | |
92 | int16_t nf; | |
93 | ||
94 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
95 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); | |
96 | else | |
97 | nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); | |
98 | ||
99 | if (nf & 0x100) | |
100 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
101 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
102 | "NF calibrated [ctl] [chain 0] is %d\n", nf); | |
103 | nfarray[0] = nf; | |
104 | ||
793c5929 SB |
105 | if (!AR_SREV_9285(ah)) { |
106 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
107 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | |
108 | AR9280_PHY_CH1_MINCCA_PWR); | |
109 | else | |
110 | nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), | |
111 | AR_PHY_CH1_MINCCA_PWR); | |
f1dc5600 | 112 | |
f1dc5600 S |
113 | if (nf & 0x100) |
114 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 115 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
793c5929 SB |
116 | "NF calibrated [ctl] [chain 1] is %d\n", nf); |
117 | nfarray[1] = nf; | |
118 | ||
119 | if (!AR_SREV_9280(ah)) { | |
120 | nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), | |
121 | AR_PHY_CH2_MINCCA_PWR); | |
122 | if (nf & 0x100) | |
123 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
124 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
125 | "NF calibrated [ctl] [chain 2] is %d\n", nf); | |
126 | nfarray[2] = nf; | |
127 | } | |
f1dc5600 S |
128 | } |
129 | ||
130 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
131 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | |
132 | AR9280_PHY_EXT_MINCCA_PWR); | |
133 | else | |
134 | nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), | |
135 | AR_PHY_EXT_MINCCA_PWR); | |
136 | ||
137 | if (nf & 0x100) | |
138 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 139 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
f1dc5600 S |
140 | "NF calibrated [ext] [chain 0] is %d\n", nf); |
141 | nfarray[3] = nf; | |
142 | ||
793c5929 SB |
143 | if (!AR_SREV_9285(ah)) { |
144 | if (AR_SREV_9280_10_OR_LATER(ah)) | |
145 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | |
146 | AR9280_PHY_CH1_EXT_MINCCA_PWR); | |
147 | else | |
148 | nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), | |
149 | AR_PHY_CH1_EXT_MINCCA_PWR); | |
f1dc5600 | 150 | |
f1dc5600 S |
151 | if (nf & 0x100) |
152 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
04bd4638 | 153 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
793c5929 SB |
154 | "NF calibrated [ext] [chain 1] is %d\n", nf); |
155 | nfarray[4] = nf; | |
156 | ||
157 | if (!AR_SREV_9280(ah)) { | |
158 | nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), | |
159 | AR_PHY_CH2_EXT_MINCCA_PWR); | |
160 | if (nf & 0x100) | |
161 | nf = 0 - ((nf ^ 0x1ff) + 1); | |
162 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
163 | "NF calibrated [ext] [chain 2] is %d\n", nf); | |
164 | nfarray[5] = nf; | |
165 | } | |
f1dc5600 S |
166 | } |
167 | } | |
168 | ||
cbe61d8a | 169 | static bool getNoiseFloorThresh(struct ath_hw *ah, |
76061abb | 170 | enum ieee80211_band band, |
f1dc5600 S |
171 | int16_t *nft) |
172 | { | |
76061abb LR |
173 | switch (band) { |
174 | case IEEE80211_BAND_5GHZ: | |
f9bbf431 | 175 | *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_5); |
f1dc5600 | 176 | break; |
76061abb | 177 | case IEEE80211_BAND_2GHZ: |
f9bbf431 | 178 | *nft = (int8_t)ath9k_hw_get_eeprom(ah, EEP_NFTHRESH_2); |
f1dc5600 S |
179 | break; |
180 | default: | |
76061abb | 181 | BUG_ON(1); |
f1dc5600 S |
182 | return false; |
183 | } | |
184 | ||
185 | return true; | |
186 | } | |
187 | ||
cbe61d8a | 188 | static void ath9k_hw_setup_calibration(struct ath_hw *ah, |
f1dc5600 S |
189 | struct hal_cal_list *currCal) |
190 | { | |
191 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), | |
192 | AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, | |
193 | currCal->calData->calCountMax); | |
194 | ||
195 | switch (currCal->calData->calType) { | |
196 | case IQ_MISMATCH_CAL: | |
197 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); | |
198 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 199 | "starting IQ Mismatch Calibration\n"); |
f1dc5600 S |
200 | break; |
201 | case ADC_GAIN_CAL: | |
202 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); | |
203 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 204 | "starting ADC Gain Calibration\n"); |
f1dc5600 S |
205 | break; |
206 | case ADC_DC_CAL: | |
207 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); | |
208 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 209 | "starting ADC DC Calibration\n"); |
f1dc5600 S |
210 | break; |
211 | case ADC_DC_INIT_CAL: | |
212 | REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); | |
213 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 214 | "starting Init ADC DC Calibration\n"); |
f1dc5600 S |
215 | break; |
216 | } | |
217 | ||
218 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | |
219 | AR_PHY_TIMING_CTRL4_DO_CAL); | |
220 | } | |
221 | ||
cbe61d8a | 222 | static void ath9k_hw_reset_calibration(struct ath_hw *ah, |
f1dc5600 S |
223 | struct hal_cal_list *currCal) |
224 | { | |
f1dc5600 S |
225 | int i; |
226 | ||
227 | ath9k_hw_setup_calibration(ah, currCal); | |
228 | ||
229 | currCal->calState = CAL_RUNNING; | |
230 | ||
231 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
cbe61d8a S |
232 | ah->ah_Meas0.sign[i] = 0; |
233 | ah->ah_Meas1.sign[i] = 0; | |
234 | ah->ah_Meas2.sign[i] = 0; | |
235 | ah->ah_Meas3.sign[i] = 0; | |
f1dc5600 S |
236 | } |
237 | ||
cbe61d8a | 238 | ah->ah_CalSamples = 0; |
f1dc5600 S |
239 | } |
240 | ||
cbe61d8a | 241 | static void ath9k_hw_per_calibration(struct ath_hw *ah, |
f1dc5600 S |
242 | struct ath9k_channel *ichan, |
243 | u8 rxchainmask, | |
244 | struct hal_cal_list *currCal, | |
245 | bool *isCalDone) | |
246 | { | |
f1dc5600 S |
247 | *isCalDone = false; |
248 | ||
249 | if (currCal->calState == CAL_RUNNING) { | |
250 | if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & | |
251 | AR_PHY_TIMING_CTRL4_DO_CAL)) { | |
252 | ||
253 | currCal->calData->calCollect(ah); | |
cbe61d8a | 254 | ah->ah_CalSamples++; |
f1dc5600 | 255 | |
cbe61d8a | 256 | if (ah->ah_CalSamples >= currCal->calData->calNumSamples) { |
f1dc5600 S |
257 | int i, numChains = 0; |
258 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
259 | if (rxchainmask & (1 << i)) | |
260 | numChains++; | |
261 | } | |
262 | ||
263 | currCal->calData->calPostProc(ah, numChains); | |
264 | ichan->CalValid |= currCal->calData->calType; | |
265 | currCal->calState = CAL_DONE; | |
266 | *isCalDone = true; | |
267 | } else { | |
268 | ath9k_hw_setup_calibration(ah, currCal); | |
269 | } | |
270 | } | |
271 | } else if (!(ichan->CalValid & currCal->calData->calType)) { | |
272 | ath9k_hw_reset_calibration(ah, currCal); | |
273 | } | |
274 | } | |
275 | ||
c9e27d94 | 276 | /* Assumes you are talking about the currently configured channel */ |
cbe61d8a | 277 | static bool ath9k_hw_iscal_supported(struct ath_hw *ah, |
f1dc5600 S |
278 | enum hal_cal_types calType) |
279 | { | |
c9e27d94 | 280 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
f1dc5600 | 281 | |
cbe61d8a | 282 | switch (calType & ah->ah_suppCals) { |
c9e27d94 LR |
283 | case IQ_MISMATCH_CAL: /* Both 2 GHz and 5 GHz support OFDM */ |
284 | return true; | |
f1dc5600 S |
285 | case ADC_GAIN_CAL: |
286 | case ADC_DC_CAL: | |
c9e27d94 LR |
287 | if (conf->channel->band == IEEE80211_BAND_5GHZ && |
288 | conf_is_ht20(conf)) | |
289 | return true; | |
f1dc5600 S |
290 | break; |
291 | } | |
c9e27d94 | 292 | return false; |
f1dc5600 S |
293 | } |
294 | ||
cbe61d8a | 295 | static void ath9k_hw_iqcal_collect(struct ath_hw *ah) |
f1dc5600 | 296 | { |
f1dc5600 S |
297 | int i; |
298 | ||
299 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
cbe61d8a | 300 | ah->ah_totalPowerMeasI[i] += |
f1dc5600 | 301 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
cbe61d8a | 302 | ah->ah_totalPowerMeasQ[i] += |
f1dc5600 | 303 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
cbe61d8a | 304 | ah->ah_totalIqCorrMeas[i] += |
f1dc5600 S |
305 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
306 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
307 | "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", | |
cbe61d8a S |
308 | ah->ah_CalSamples, i, ah->ah_totalPowerMeasI[i], |
309 | ah->ah_totalPowerMeasQ[i], | |
310 | ah->ah_totalIqCorrMeas[i]); | |
f1dc5600 S |
311 | } |
312 | } | |
313 | ||
cbe61d8a | 314 | static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah) |
f1dc5600 | 315 | { |
f1dc5600 S |
316 | int i; |
317 | ||
318 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
cbe61d8a | 319 | ah->ah_totalAdcIOddPhase[i] += |
f1dc5600 | 320 | REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
cbe61d8a | 321 | ah->ah_totalAdcIEvenPhase[i] += |
f1dc5600 | 322 | REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
cbe61d8a | 323 | ah->ah_totalAdcQOddPhase[i] += |
f1dc5600 | 324 | REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
cbe61d8a | 325 | ah->ah_totalAdcQEvenPhase[i] += |
f1dc5600 S |
326 | REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
327 | ||
328 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
329 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | |
330 | "oddq=0x%08x; evenq=0x%08x;\n", | |
cbe61d8a S |
331 | ah->ah_CalSamples, i, |
332 | ah->ah_totalAdcIOddPhase[i], | |
333 | ah->ah_totalAdcIEvenPhase[i], | |
334 | ah->ah_totalAdcQOddPhase[i], | |
335 | ah->ah_totalAdcQEvenPhase[i]); | |
f1dc5600 S |
336 | } |
337 | } | |
338 | ||
cbe61d8a | 339 | static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah) |
f1dc5600 | 340 | { |
f1dc5600 S |
341 | int i; |
342 | ||
343 | for (i = 0; i < AR5416_MAX_CHAINS; i++) { | |
cbe61d8a | 344 | ah->ah_totalAdcDcOffsetIOddPhase[i] += |
f1dc5600 | 345 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); |
cbe61d8a | 346 | ah->ah_totalAdcDcOffsetIEvenPhase[i] += |
f1dc5600 | 347 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); |
cbe61d8a | 348 | ah->ah_totalAdcDcOffsetQOddPhase[i] += |
f1dc5600 | 349 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); |
cbe61d8a | 350 | ah->ah_totalAdcDcOffsetQEvenPhase[i] += |
f1dc5600 S |
351 | (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); |
352 | ||
353 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
354 | "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " | |
355 | "oddq=0x%08x; evenq=0x%08x;\n", | |
cbe61d8a S |
356 | ah->ah_CalSamples, i, |
357 | ah->ah_totalAdcDcOffsetIOddPhase[i], | |
358 | ah->ah_totalAdcDcOffsetIEvenPhase[i], | |
359 | ah->ah_totalAdcDcOffsetQOddPhase[i], | |
360 | ah->ah_totalAdcDcOffsetQEvenPhase[i]); | |
f1dc5600 S |
361 | } |
362 | } | |
363 | ||
cbe61d8a | 364 | static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) |
f1dc5600 | 365 | { |
f1dc5600 S |
366 | u32 powerMeasQ, powerMeasI, iqCorrMeas; |
367 | u32 qCoffDenom, iCoffDenom; | |
368 | int32_t qCoff, iCoff; | |
369 | int iqCorrNeg, i; | |
370 | ||
371 | for (i = 0; i < numChains; i++) { | |
cbe61d8a S |
372 | powerMeasI = ah->ah_totalPowerMeasI[i]; |
373 | powerMeasQ = ah->ah_totalPowerMeasQ[i]; | |
374 | iqCorrMeas = ah->ah_totalIqCorrMeas[i]; | |
f1dc5600 S |
375 | |
376 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
377 | "Starting IQ Cal and Correction for Chain %d\n", | |
378 | i); | |
379 | ||
380 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
381 | "Orignal: Chn %diq_corr_meas = 0x%08x\n", | |
cbe61d8a | 382 | i, ah->ah_totalIqCorrMeas[i]); |
f1dc5600 S |
383 | |
384 | iqCorrNeg = 0; | |
385 | ||
386 | if (iqCorrMeas > 0x80000000) { | |
387 | iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; | |
388 | iqCorrNeg = 1; | |
389 | } | |
390 | ||
391 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
392 | "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); | |
393 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
394 | "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); | |
395 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", | |
396 | iqCorrNeg); | |
397 | ||
398 | iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; | |
399 | qCoffDenom = powerMeasQ / 64; | |
400 | ||
401 | if (powerMeasQ != 0) { | |
402 | iCoff = iqCorrMeas / iCoffDenom; | |
403 | qCoff = powerMeasI / qCoffDenom - 64; | |
404 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
405 | "Chn %d iCoff = 0x%08x\n", i, iCoff); | |
406 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
407 | "Chn %d qCoff = 0x%08x\n", i, qCoff); | |
408 | ||
409 | iCoff = iCoff & 0x3f; | |
410 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
411 | "New: Chn %d iCoff = 0x%08x\n", i, iCoff); | |
412 | if (iqCorrNeg == 0x0) | |
413 | iCoff = 0x40 - iCoff; | |
414 | ||
415 | if (qCoff > 15) | |
416 | qCoff = 15; | |
417 | else if (qCoff <= -16) | |
418 | qCoff = 16; | |
419 | ||
420 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
421 | "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", | |
422 | i, iCoff, qCoff); | |
423 | ||
424 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | |
425 | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, | |
426 | iCoff); | |
427 | REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), | |
428 | AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, | |
429 | qCoff); | |
430 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
431 | "IQ Cal and Correction done for Chain %d\n", | |
432 | i); | |
433 | } | |
434 | } | |
435 | ||
436 | REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), | |
437 | AR_PHY_TIMING_CTRL4_IQCORR_ENABLE); | |
438 | } | |
439 | ||
cbe61d8a | 440 | static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) |
f1dc5600 | 441 | { |
f1dc5600 S |
442 | u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset; |
443 | u32 qGainMismatch, iGainMismatch, val, i; | |
444 | ||
445 | for (i = 0; i < numChains; i++) { | |
cbe61d8a S |
446 | iOddMeasOffset = ah->ah_totalAdcIOddPhase[i]; |
447 | iEvenMeasOffset = ah->ah_totalAdcIEvenPhase[i]; | |
448 | qOddMeasOffset = ah->ah_totalAdcQOddPhase[i]; | |
449 | qEvenMeasOffset = ah->ah_totalAdcQEvenPhase[i]; | |
f1dc5600 S |
450 | |
451 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
452 | "Starting ADC Gain Cal for Chain %d\n", i); | |
453 | ||
454 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
455 | "Chn %d pwr_meas_odd_i = 0x%08x\n", i, | |
456 | iOddMeasOffset); | |
457 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
458 | "Chn %d pwr_meas_even_i = 0x%08x\n", i, | |
459 | iEvenMeasOffset); | |
460 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
461 | "Chn %d pwr_meas_odd_q = 0x%08x\n", i, | |
462 | qOddMeasOffset); | |
463 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
464 | "Chn %d pwr_meas_even_q = 0x%08x\n", i, | |
465 | qEvenMeasOffset); | |
466 | ||
467 | if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) { | |
468 | iGainMismatch = | |
469 | ((iEvenMeasOffset * 32) / | |
470 | iOddMeasOffset) & 0x3f; | |
471 | qGainMismatch = | |
472 | ((qOddMeasOffset * 32) / | |
473 | qEvenMeasOffset) & 0x3f; | |
474 | ||
475 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
476 | "Chn %d gain_mismatch_i = 0x%08x\n", i, | |
477 | iGainMismatch); | |
478 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
479 | "Chn %d gain_mismatch_q = 0x%08x\n", i, | |
480 | qGainMismatch); | |
481 | ||
482 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | |
483 | val &= 0xfffff000; | |
484 | val |= (qGainMismatch) | (iGainMismatch << 6); | |
485 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | |
486 | ||
487 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
488 | "ADC Gain Cal done for Chain %d\n", i); | |
489 | } | |
490 | } | |
491 | ||
492 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | |
493 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | |
494 | AR_PHY_NEW_ADC_GAIN_CORR_ENABLE); | |
495 | } | |
496 | ||
cbe61d8a | 497 | static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) |
f1dc5600 | 498 | { |
f1dc5600 S |
499 | u32 iOddMeasOffset, iEvenMeasOffset, val, i; |
500 | int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch; | |
501 | const struct hal_percal_data *calData = | |
cbe61d8a | 502 | ah->ah_cal_list_curr->calData; |
f1dc5600 S |
503 | u32 numSamples = |
504 | (1 << (calData->calCountMax + 5)) * calData->calNumSamples; | |
505 | ||
506 | for (i = 0; i < numChains; i++) { | |
cbe61d8a S |
507 | iOddMeasOffset = ah->ah_totalAdcDcOffsetIOddPhase[i]; |
508 | iEvenMeasOffset = ah->ah_totalAdcDcOffsetIEvenPhase[i]; | |
509 | qOddMeasOffset = ah->ah_totalAdcDcOffsetQOddPhase[i]; | |
510 | qEvenMeasOffset = ah->ah_totalAdcDcOffsetQEvenPhase[i]; | |
f1dc5600 S |
511 | |
512 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
513 | "Starting ADC DC Offset Cal for Chain %d\n", i); | |
514 | ||
515 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
516 | "Chn %d pwr_meas_odd_i = %d\n", i, | |
517 | iOddMeasOffset); | |
518 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
519 | "Chn %d pwr_meas_even_i = %d\n", i, | |
520 | iEvenMeasOffset); | |
521 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
522 | "Chn %d pwr_meas_odd_q = %d\n", i, | |
523 | qOddMeasOffset); | |
524 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
525 | "Chn %d pwr_meas_even_q = %d\n", i, | |
526 | qEvenMeasOffset); | |
527 | ||
528 | iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) / | |
529 | numSamples) & 0x1ff; | |
530 | qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / | |
531 | numSamples) & 0x1ff; | |
532 | ||
533 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
534 | "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, | |
535 | iDcMismatch); | |
536 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
537 | "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, | |
538 | qDcMismatch); | |
539 | ||
540 | val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); | |
541 | val &= 0xc0000fff; | |
542 | val |= (qDcMismatch << 12) | (iDcMismatch << 21); | |
543 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); | |
544 | ||
545 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
546 | "ADC DC Offset Cal done for Chain %d\n", i); | |
547 | } | |
548 | ||
549 | REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), | |
550 | REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | | |
551 | AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE); | |
552 | } | |
553 | ||
c9e27d94 | 554 | /* This is done for the currently configured channel */ |
cbe61d8a | 555 | bool ath9k_hw_reset_calvalid(struct ath_hw *ah) |
f1dc5600 | 556 | { |
c9e27d94 | 557 | struct ieee80211_conf *conf = &ah->ah_sc->hw->conf; |
cbe61d8a | 558 | struct hal_cal_list *currCal = ah->ah_cal_list_curr; |
f1dc5600 | 559 | |
c9e27d94 LR |
560 | if (!ah->ah_curchan) |
561 | return true; | |
f1dc5600 S |
562 | |
563 | if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah)) | |
c9e27d94 | 564 | return true; |
f1dc5600 S |
565 | |
566 | if (currCal == NULL) | |
c9e27d94 | 567 | return true; |
f1dc5600 S |
568 | |
569 | if (currCal->calState != CAL_DONE) { | |
570 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
571 | "Calibration state incorrect, %d\n", |
572 | currCal->calState); | |
c9e27d94 | 573 | return true; |
f1dc5600 S |
574 | } |
575 | ||
c9e27d94 LR |
576 | if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) |
577 | return true; | |
f1dc5600 S |
578 | |
579 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
c9e27d94 LR |
580 | "Resetting Cal %d state for channel %u\n", |
581 | currCal->calData->calType, conf->channel->center_freq); | |
f1dc5600 | 582 | |
c9e27d94 | 583 | ah->ah_curchan->CalValid &= ~currCal->calData->calType; |
f1dc5600 S |
584 | currCal->calState = CAL_WAITING; |
585 | ||
c9e27d94 | 586 | return false; |
f1dc5600 S |
587 | } |
588 | ||
cbe61d8a | 589 | void ath9k_hw_start_nfcal(struct ath_hw *ah) |
f1dc5600 S |
590 | { |
591 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | |
592 | AR_PHY_AGC_CONTROL_ENABLE_NF); | |
593 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, | |
594 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | |
595 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | |
596 | } | |
597 | ||
cbe61d8a | 598 | void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan) |
f1dc5600 S |
599 | { |
600 | struct ath9k_nfcal_hist *h; | |
601 | int i, j; | |
602 | int32_t val; | |
603 | const u32 ar5416_cca_regs[6] = { | |
604 | AR_PHY_CCA, | |
605 | AR_PHY_CH1_CCA, | |
606 | AR_PHY_CH2_CCA, | |
607 | AR_PHY_EXT_CCA, | |
608 | AR_PHY_CH1_EXT_CCA, | |
609 | AR_PHY_CH2_EXT_CCA | |
610 | }; | |
611 | u8 chainmask; | |
612 | ||
5dad40c1 S |
613 | if (AR_SREV_9285(ah)) |
614 | chainmask = 0x9; | |
615 | else if (AR_SREV_9280(ah)) | |
f1dc5600 S |
616 | chainmask = 0x1B; |
617 | else | |
618 | chainmask = 0x3F; | |
619 | ||
f1dc5600 | 620 | h = ah->nfCalHist; |
f1dc5600 S |
621 | |
622 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
623 | if (chainmask & (1 << i)) { | |
624 | val = REG_READ(ah, ar5416_cca_regs[i]); | |
625 | val &= 0xFFFFFE00; | |
626 | val |= (((u32) (h[i].privNF) << 1) & 0x1ff); | |
627 | REG_WRITE(ah, ar5416_cca_regs[i], val); | |
628 | } | |
629 | } | |
630 | ||
631 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | |
632 | AR_PHY_AGC_CONTROL_ENABLE_NF); | |
633 | REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, | |
634 | AR_PHY_AGC_CONTROL_NO_UPDATE_NF); | |
635 | REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); | |
636 | ||
637 | for (j = 0; j < 1000; j++) { | |
638 | if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & | |
639 | AR_PHY_AGC_CONTROL_NF) == 0) | |
640 | break; | |
641 | udelay(10); | |
642 | } | |
643 | ||
644 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
645 | if (chainmask & (1 << i)) { | |
646 | val = REG_READ(ah, ar5416_cca_regs[i]); | |
647 | val &= 0xFFFFFE00; | |
648 | val |= (((u32) (-50) << 1) & 0x1ff); | |
649 | REG_WRITE(ah, ar5416_cca_regs[i], val); | |
650 | } | |
651 | } | |
652 | } | |
653 | ||
cbe61d8a | 654 | int16_t ath9k_hw_getnf(struct ath_hw *ah, |
f1dc5600 S |
655 | struct ath9k_channel *chan) |
656 | { | |
657 | int16_t nf, nfThresh; | |
658 | int16_t nfarray[NUM_NF_READINGS] = { 0 }; | |
659 | struct ath9k_nfcal_hist *h; | |
76061abb | 660 | struct ieee80211_channel *c = chan->chan; |
f1dc5600 S |
661 | |
662 | chan->channelFlags &= (~CHANNEL_CW_INT); | |
663 | if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { | |
664 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 | 665 | "NF did not complete in calibration window\n"); |
f1dc5600 S |
666 | nf = 0; |
667 | chan->rawNoiseFloor = nf; | |
668 | return chan->rawNoiseFloor; | |
669 | } else { | |
670 | ath9k_hw_do_getnf(ah, nfarray); | |
671 | nf = nfarray[0]; | |
76061abb | 672 | if (getNoiseFloorThresh(ah, c->band, &nfThresh) |
f1dc5600 S |
673 | && nf > nfThresh) { |
674 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
675 | "noise floor failed detected; " |
676 | "detected %d, threshold %d\n", | |
f1dc5600 S |
677 | nf, nfThresh); |
678 | chan->channelFlags |= CHANNEL_CW_INT; | |
679 | } | |
680 | } | |
681 | ||
f1dc5600 | 682 | h = ah->nfCalHist; |
f1dc5600 S |
683 | |
684 | ath9k_hw_update_nfcal_hist_buffer(h, nfarray); | |
685 | chan->rawNoiseFloor = h[0].privNF; | |
686 | ||
687 | return chan->rawNoiseFloor; | |
688 | } | |
689 | ||
cbe61d8a | 690 | void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah) |
f1dc5600 S |
691 | { |
692 | int i, j; | |
693 | ||
694 | for (i = 0; i < NUM_NF_READINGS; i++) { | |
695 | ah->nfCalHist[i].currIndex = 0; | |
696 | ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE; | |
697 | ah->nfCalHist[i].invalidNFcount = | |
698 | AR_PHY_CCA_FILTERWINDOW_LENGTH; | |
699 | for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) { | |
700 | ah->nfCalHist[i].nfCalBuffer[j] = | |
701 | AR_PHY_CCA_MAX_GOOD_VALUE; | |
702 | } | |
703 | } | |
f1dc5600 S |
704 | } |
705 | ||
cbe61d8a | 706 | s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan) |
f1dc5600 | 707 | { |
f1dc5600 S |
708 | s16 nf; |
709 | ||
5f8e077c | 710 | if (chan->rawNoiseFloor == 0) |
e56db718 LR |
711 | nf = -96; |
712 | else | |
5f8e077c | 713 | nf = chan->rawNoiseFloor; |
f1dc5600 S |
714 | |
715 | if (!ath9k_hw_nf_in_range(ah, nf)) | |
716 | nf = ATH_DEFAULT_NOISE_FLOOR; | |
717 | ||
718 | return nf; | |
719 | } | |
720 | ||
cbe61d8a | 721 | bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, |
f1dc5600 S |
722 | u8 rxchainmask, bool longcal, |
723 | bool *isCalDone) | |
724 | { | |
cbe61d8a | 725 | struct hal_cal_list *currCal = ah->ah_cal_list_curr; |
f1dc5600 S |
726 | |
727 | *isCalDone = true; | |
728 | ||
f1dc5600 S |
729 | if (currCal && |
730 | (currCal->calState == CAL_RUNNING || | |
731 | currCal->calState == CAL_WAITING)) { | |
5f8e077c | 732 | ath9k_hw_per_calibration(ah, chan, rxchainmask, currCal, |
f1dc5600 S |
733 | isCalDone); |
734 | if (*isCalDone) { | |
cbe61d8a | 735 | ah->ah_cal_list_curr = currCal = currCal->calNext; |
f1dc5600 S |
736 | |
737 | if (currCal->calState == CAL_WAITING) { | |
738 | *isCalDone = false; | |
739 | ath9k_hw_reset_calibration(ah, currCal); | |
740 | } | |
741 | } | |
742 | } | |
743 | ||
744 | if (longcal) { | |
5f8e077c | 745 | ath9k_hw_getnf(ah, chan); |
f1dc5600 S |
746 | ath9k_hw_loadnf(ah, ah->ah_curchan); |
747 | ath9k_hw_start_nfcal(ah); | |
748 | ||
5f8e077c LR |
749 | if (chan->channelFlags & CHANNEL_CW_INT) |
750 | chan->channelFlags &= ~CHANNEL_CW_INT; | |
f1dc5600 S |
751 | } |
752 | ||
753 | return true; | |
754 | } | |
755 | ||
cbe61d8a | 756 | static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah) |
e7594072 SB |
757 | { |
758 | ||
759 | u32 regVal; | |
760 | int i, offset, offs_6_1, offs_0; | |
761 | u32 ccomp_org, reg_field; | |
762 | u32 regList[][2] = { | |
763 | { 0x786c, 0 }, | |
764 | { 0x7854, 0 }, | |
765 | { 0x7820, 0 }, | |
766 | { 0x7824, 0 }, | |
767 | { 0x7868, 0 }, | |
768 | { 0x783c, 0 }, | |
769 | { 0x7838, 0 }, | |
770 | }; | |
771 | ||
772 | if (AR_SREV_9285_11(ah)) { | |
773 | REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14)); | |
774 | udelay(10); | |
775 | } | |
776 | ||
777 | for (i = 0; i < ARRAY_SIZE(regList); i++) | |
778 | regList[i][1] = REG_READ(ah, regList[i][0]); | |
779 | ||
780 | regVal = REG_READ(ah, 0x7834); | |
781 | regVal &= (~(0x1)); | |
782 | REG_WRITE(ah, 0x7834, regVal); | |
783 | regVal = REG_READ(ah, 0x9808); | |
784 | regVal |= (0x1 << 27); | |
785 | REG_WRITE(ah, 0x9808, regVal); | |
786 | ||
787 | REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); | |
788 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); | |
789 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); | |
790 | REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); | |
791 | REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); | |
792 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); | |
793 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); | |
794 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1); | |
795 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); | |
796 | REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); | |
797 | REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); | |
798 | REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); | |
799 | ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); | |
800 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7); | |
801 | ||
802 | REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); | |
803 | udelay(30); | |
804 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); | |
805 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); | |
806 | ||
807 | for (i = 6; i > 0; i--) { | |
808 | regVal = REG_READ(ah, 0x7834); | |
809 | regVal |= (1 << (19 + i)); | |
810 | REG_WRITE(ah, 0x7834, regVal); | |
811 | udelay(1); | |
812 | regVal = REG_READ(ah, 0x7834); | |
813 | regVal &= (~(0x1 << (19 + i))); | |
814 | reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); | |
815 | regVal |= (reg_field << (19 + i)); | |
816 | REG_WRITE(ah, 0x7834, regVal); | |
817 | } | |
818 | ||
819 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); | |
820 | udelay(1); | |
821 | reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); | |
822 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); | |
823 | offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); | |
824 | offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); | |
825 | ||
826 | offset = (offs_6_1<<1) | offs_0; | |
827 | offset = offset - 0; | |
828 | offs_6_1 = offset>>1; | |
829 | offs_0 = offset & 1; | |
830 | ||
831 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); | |
832 | REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); | |
833 | ||
834 | regVal = REG_READ(ah, 0x7834); | |
835 | regVal |= 0x1; | |
836 | REG_WRITE(ah, 0x7834, regVal); | |
837 | regVal = REG_READ(ah, 0x9808); | |
838 | regVal &= (~(0x1 << 27)); | |
839 | REG_WRITE(ah, 0x9808, regVal); | |
840 | ||
841 | for (i = 0; i < ARRAY_SIZE(regList); i++) | |
842 | REG_WRITE(ah, regList[i][0], regList[i][1]); | |
843 | ||
844 | REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); | |
845 | ||
846 | if (AR_SREV_9285_11(ah)) | |
847 | REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT); | |
848 | ||
849 | } | |
850 | ||
cbe61d8a | 851 | bool ath9k_hw_init_cal(struct ath_hw *ah, |
f1dc5600 S |
852 | struct ath9k_channel *chan) |
853 | { | |
f1dc5600 S |
854 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
855 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | |
856 | AR_PHY_AGC_CONTROL_CAL); | |
857 | ||
858 | if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { | |
859 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, | |
04bd4638 S |
860 | "offset calibration failed to complete in 1ms; " |
861 | "noisy environment?\n"); | |
f1dc5600 S |
862 | return false; |
863 | } | |
864 | ||
e7594072 SB |
865 | if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah)) |
866 | ath9k_hw_9285_pa_cal(ah); | |
867 | ||
f1dc5600 S |
868 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
869 | REG_READ(ah, AR_PHY_AGC_CONTROL) | | |
870 | AR_PHY_AGC_CONTROL_NF); | |
871 | ||
cbe61d8a | 872 | ah->ah_cal_list = ah->ah_cal_list_last = ah->ah_cal_list_curr = NULL; |
f1dc5600 S |
873 | |
874 | if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { | |
c9e27d94 | 875 | if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { |
cbe61d8a S |
876 | INIT_CAL(&ah->ah_adcGainCalData); |
877 | INSERT_CAL(ah, &ah->ah_adcGainCalData); | |
f1dc5600 | 878 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
04bd4638 | 879 | "enabling ADC Gain Calibration.\n"); |
f1dc5600 | 880 | } |
c9e27d94 | 881 | if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { |
cbe61d8a S |
882 | INIT_CAL(&ah->ah_adcDcCalData); |
883 | INSERT_CAL(ah, &ah->ah_adcDcCalData); | |
f1dc5600 | 884 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
04bd4638 | 885 | "enabling ADC DC Calibration.\n"); |
f1dc5600 | 886 | } |
c9e27d94 | 887 | if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { |
cbe61d8a S |
888 | INIT_CAL(&ah->ah_iqCalData); |
889 | INSERT_CAL(ah, &ah->ah_iqCalData); | |
f1dc5600 | 890 | DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, |
04bd4638 | 891 | "enabling IQ Calibration.\n"); |
f1dc5600 S |
892 | } |
893 | ||
cbe61d8a | 894 | ah->ah_cal_list_curr = ah->ah_cal_list; |
f1dc5600 | 895 | |
cbe61d8a S |
896 | if (ah->ah_cal_list_curr) |
897 | ath9k_hw_reset_calibration(ah, ah->ah_cal_list_curr); | |
f1dc5600 S |
898 | } |
899 | ||
5f8e077c | 900 | chan->CalValid = 0; |
f1dc5600 S |
901 | |
902 | return true; | |
903 | } | |
904 | ||
905 | const struct hal_percal_data iq_cal_multi_sample = { | |
906 | IQ_MISMATCH_CAL, | |
907 | MAX_CAL_SAMPLES, | |
908 | PER_MIN_LOG_COUNT, | |
909 | ath9k_hw_iqcal_collect, | |
910 | ath9k_hw_iqcalibrate | |
911 | }; | |
912 | const struct hal_percal_data iq_cal_single_sample = { | |
913 | IQ_MISMATCH_CAL, | |
914 | MIN_CAL_SAMPLES, | |
915 | PER_MAX_LOG_COUNT, | |
916 | ath9k_hw_iqcal_collect, | |
917 | ath9k_hw_iqcalibrate | |
918 | }; | |
919 | const struct hal_percal_data adc_gain_cal_multi_sample = { | |
920 | ADC_GAIN_CAL, | |
921 | MAX_CAL_SAMPLES, | |
922 | PER_MIN_LOG_COUNT, | |
923 | ath9k_hw_adc_gaincal_collect, | |
924 | ath9k_hw_adc_gaincal_calibrate | |
925 | }; | |
926 | const struct hal_percal_data adc_gain_cal_single_sample = { | |
927 | ADC_GAIN_CAL, | |
928 | MIN_CAL_SAMPLES, | |
929 | PER_MAX_LOG_COUNT, | |
930 | ath9k_hw_adc_gaincal_collect, | |
931 | ath9k_hw_adc_gaincal_calibrate | |
932 | }; | |
933 | const struct hal_percal_data adc_dc_cal_multi_sample = { | |
934 | ADC_DC_CAL, | |
935 | MAX_CAL_SAMPLES, | |
936 | PER_MIN_LOG_COUNT, | |
937 | ath9k_hw_adc_dccal_collect, | |
938 | ath9k_hw_adc_dccal_calibrate | |
939 | }; | |
940 | const struct hal_percal_data adc_dc_cal_single_sample = { | |
941 | ADC_DC_CAL, | |
942 | MIN_CAL_SAMPLES, | |
943 | PER_MAX_LOG_COUNT, | |
944 | ath9k_hw_adc_dccal_collect, | |
945 | ath9k_hw_adc_dccal_calibrate | |
946 | }; | |
947 | const struct hal_percal_data adc_init_dc_cal = { | |
948 | ADC_DC_INIT_CAL, | |
949 | MIN_CAL_SAMPLES, | |
950 | INIT_LOG_COUNT, | |
951 | ath9k_hw_adc_dccal_collect, | |
952 | ath9k_hw_adc_dccal_calibrate | |
953 | }; |