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ath5k: Update gain_F calibration code and add documentation
[linux-2.6-block.git] / drivers / net / wireless / ath5k / phy.c
CommitLineData
fa1c114f
JS		 1/*
2 * PHY functions
3 *
c6e387a2 4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
33a31826 5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
c6e387a2 6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
fa1c114f
JS		 7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
c6e387a2
NK		 22#define _ATH5K_PHY
23
fa1c114f
JS		 24#include <linux/delay.h>
25
26#include "ath5k.h"
27#include "reg.h"
28#include "base.h"
33a31826
NK		 29#include "rfbuffer.h"
30#include "rfgain.h"
fa1c114f
JS		 31
32/*
33 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
34 */
35static unsigned int ath5k_hw_rfregs_op(u32 *rf, u32 offset, u32 reg, u32 bits,
36 u32 first, u32 col, bool set)
37{
38 u32 mask, entry, last, data, shift, position;
39 s32 left;
40 int i;
41
42 data = 0;
43
44 if (rf == NULL)
45 /* should not happen */
46 return 0;
47
48 if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
49 ATH5K_PRINTF("invalid values at offset %u\n", offset);
50 return 0;
51 }
52
53 entry = ((first - 1) / 8) + offset;
54 position = (first - 1) % 8;
55
e9010e2f 56 if (set)
fa1c114f
JS		 57 data = ath5k_hw_bitswap(reg, bits);
58
59 for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
60 last = (position + left > 8) ? 8 : position + left;
61 mask = (((1 << last) - 1) ^ ((1 << position) - 1)) << (col * 8);
62
e9010e2f 63 if (set) {
fa1c114f
JS		 64 rf[entry] &= ~mask;
65 rf[entry] |= ((data << position) << (col * 8)) & mask;
66 data >>= (8 - position);
67 } else {
68 data = (((rf[entry] & mask) >> (col * 8)) >> position)
69 << shift;
70 shift += last - position;
71 }
72
73 left -= 8 - position;
74 }
75
e9010e2f 76 data = set ? 1 : ath5k_hw_bitswap(data, bits);
fa1c114f
JS		 77
78 return data;
79}
80
6f3b414a
NK		 81/**********************\
82* RF Gain optimization *
83\**********************/
84
85/*
86 * This code is used to optimize rf gain on different environments
87 * (temprature mostly) based on feedback from a power detector.
88 *
89 * It's only used on RF5111 and RF5112, later RF chips seem to have
90 * auto adjustment on hw -notice they have a much smaller BANK 7 and
91 * no gain optimization ladder-.
92 *
93 * For more infos check out this patent doc
94 * http://www.freepatentsonline.com/7400691.html
95 *
96 * This paper describes power drops as seen on the receiver due to
97 * probe packets
98 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
99 * %20of%20Power%20Control.pdf
100 *
101 * And this is the MadWiFi bug entry related to the above
102 * http://madwifi-project.org/ticket/1659
103 * with various measurements and diagrams
104 *
105 * TODO: Deal with power drops due to probes by setting an apropriate
106 * tx power on the probe packets ! Make this part of the calibration process.
107 */
108
109/* Initialize ah_gain durring attach */
110int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
111{
112 /* Initialize the gain optimization values */
113 switch (ah->ah_radio) {
114 case AR5K_RF5111:
115 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
116 ah->ah_gain.g_low = 20;
117 ah->ah_gain.g_high = 35;
118 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
119 break;
120 case AR5K_RF5112:
121 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
122 ah->ah_gain.g_low = 20;
123 ah->ah_gain.g_high = 85;
124 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
125 break;
126 default:
127 return -EINVAL;
128 }
129
130 return 0;
131}
132
133/* Schedule a gain probe check on the next transmited packet.
134 * That means our next packet is going to be sent with lower
135 * tx power and a Peak to Average Power Detector (PAPD) will try
136 * to measure the gain.
137 *
138 * TODO: Use propper tx power setting for the probe packet so
139 * that we don't observe a serious power drop on the receiver
140 *
141 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
142 * just after we enable the probe so that we don't mess with
143 * standard traffic ? Maybe it's time to use sw interrupts and
144 * a probe tasklet !!!
145 */
146static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
147{
148
149 /* Skip if gain calibration is inactive or
150 * we already handle a probe request */
151 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
152 return;
153
154 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_max,
155 AR5K_PHY_PAPD_PROBE_TXPOWER) |
156 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
157
158 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
159
160}
161
162/* Calculate gain_F measurement correction
163 * based on the current step for RF5112 rev. 2 */
164static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
fa1c114f
JS		 165{
166 u32 mix, step;
167 u32 *rf;
6f3b414a
NK		 168 const struct ath5k_gain_opt *go;
169 const struct ath5k_gain_opt_step *g_step;
170
171 /* Only RF5112 Rev. 2 supports it */
172 if ((ah->ah_radio != AR5K_RF5112) ||
173 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
174 return 0;
175
176 go = &rfgain_opt_5112;
177
178 g_step = &go->go_step[ah->ah_gain.g_step_idx];
fa1c114f
JS		 179
180 if (ah->ah_rf_banks == NULL)
181 return 0;
182
183 rf = ah->ah_rf_banks;
184 ah->ah_gain.g_f_corr = 0;
185
6f3b414a 186 /* No VGA (Variable Gain Amplifier) override, skip */
fa1c114f
JS		 187 if (ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0, false) != 1)
188 return 0;
189
6f3b414a 190 /* Mix gain stepping */
fa1c114f 191 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 4, 32, 0, false);
6f3b414a
NK		 192
193 /* Mix gain override */
194 mix = g_step->gos_param[0];
fa1c114f
JS		 195
196 switch (mix) {
197 case 3:
198 ah->ah_gain.g_f_corr = step * 2;
199 break;
200 case 2:
201 ah->ah_gain.g_f_corr = (step - 5) * 2;
202 break;
203 case 1:
204 ah->ah_gain.g_f_corr = step;
205 break;
206 default:
207 ah->ah_gain.g_f_corr = 0;
208 break;
209 }
210
211 return ah->ah_gain.g_f_corr;
212}
213
6f3b414a
NK		 214/* Check if current gain_F measurement is in the range of our
215 * power detector windows. If we get a measurement outside range
216 * we know it's not accurate (detectors can't measure anything outside
217 * their detection window) so we must ignore it */
218static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
fa1c114f 219{
6f3b414a 220 u32 step, mix_ovr, level[4];
fa1c114f
JS		 221 u32 *rf;
222
223 if (ah->ah_rf_banks == NULL)
224 return false;
225
226 rf = ah->ah_rf_banks;
227
228 if (ah->ah_radio == AR5K_RF5111) {
229 step = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 6, 37, 0,
230 false);
231 level[0] = 0;
6f3b414a
NK		 232 level[1] = (step == 63) ? 50 : step + 4;
233 level[2] = (step != 63) ? 64 : level[0];
234 level[3] = level[2] + 50 ;
fa1c114f
JS		 235
236 ah->ah_gain.g_high = level[3] -
6f3b414a 237 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
fa1c114f 238 ah->ah_gain.g_low = level[0] +
6f3b414a 239 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
fa1c114f 240 } else {
6f3b414a 241 mix_ovr = ath5k_hw_rfregs_op(rf, ah->ah_offset[7], 0, 1, 36, 0,
fa1c114f
JS		 242 false);
243 level[0] = level[2] = 0;
244
6f3b414a 245 if (mix_ovr == 1) {
fa1c114f
JS		 246 level[1] = level[3] = 83;
247 } else {
248 level[1] = level[3] = 107;
249 ah->ah_gain.g_high = 55;
250 }
251 }
252
253 return (ah->ah_gain.g_current >= level[0] &&
254 ah->ah_gain.g_current <= level[1]) ||
255 (ah->ah_gain.g_current >= level[2] &&
256 ah->ah_gain.g_current <= level[3]);
257}
258
6f3b414a
NK		 259/* Perform gain_F adjustment by choosing the right set
260 * of parameters from rf gain optimization ladder */
261static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
fa1c114f
JS		 262{
263 const struct ath5k_gain_opt *go;
6f3b414a 264 const struct ath5k_gain_opt_step *g_step;
fa1c114f
JS		 265 int ret = 0;
266
267 switch (ah->ah_radio) {
268 case AR5K_RF5111:
269 go = &rfgain_opt_5111;
270 break;
271 case AR5K_RF5112:
fa1c114f
JS		 272 go = &rfgain_opt_5112;
273 break;
274 default:
275 return 0;
276 }
277
6f3b414a 278 g_step = &go->go_step[ah->ah_gain.g_step_idx];
fa1c114f
JS		 279
280 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
6f3b414a
NK		 281
282 /* Reached maximum */
fa1c114f
JS		 283 if (ah->ah_gain.g_step_idx == 0)
284 return -1;
6f3b414a 285
fa1c114f
JS		 286 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
287 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
288 ah->ah_gain.g_step_idx > 0;
6f3b414a 289 g_step = &go->go_step[ah->ah_gain.g_step_idx])
fa1c114f
JS		 290 ah->ah_gain.g_target -= 2 *
291 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
6f3b414a 292 g_step->gos_gain);
fa1c114f
JS		 293
294 ret = 1;
295 goto done;
296 }
297
298 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
6f3b414a
NK		 299
300 /* Reached minimum */
fa1c114f
JS		 301 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
302 return -2;
6f3b414a 303
fa1c114f
JS		 304 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
305 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
306 ah->ah_gain.g_step_idx < go->go_steps_count-1;
6f3b414a 307 g_step = &go->go_step[ah->ah_gain.g_step_idx])
fa1c114f
JS		 308 ah->ah_gain.g_target -= 2 *
309 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
6f3b414a 310 g_step->gos_gain);
fa1c114f
JS		 311
312 ret = 2;
313 goto done;
314 }
315
316done:
317 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
318 "ret %d, gain step %u, current gain %u, target gain %u\n",
319 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
320 ah->ah_gain.g_target);
321
322 return ret;
323}
324
6f3b414a
NK		 325/* Main callback for thermal rf gain calibration engine
326 * Check for a new gain reading and schedule an adjustment
327 * if needed.
328 *
329 * TODO: Use sw interrupt to schedule reset if gain_F needs
330 * adjustment */
331enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
332{
333 u32 data, type;
334 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
335
336 ATH5K_TRACE(ah->ah_sc);
337
338 if (ah->ah_rf_banks == NULL ||
339 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
340 return AR5K_RFGAIN_INACTIVE;
341
342 /* No check requested, either engine is inactive
343 * or an adjustment is already requested */
344 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
345 goto done;
346
347 /* Read the PAPD (Peak to Average Power Detector)
348 * register */
349 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
350
351 /* No probe is scheduled, read gain_F measurement */
352 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
353 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
354 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
355
356 /* If tx packet is CCK correct the gain_F measurement
357 * by cck ofdm gain delta */
358 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
359 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
360 ah->ah_gain.g_current +=
361 ee->ee_cck_ofdm_gain_delta;
362 else
363 ah->ah_gain.g_current +=
364 AR5K_GAIN_CCK_PROBE_CORR;
365 }
366
367 /* Further correct gain_F measurement for
368 * RF5112A radios */
369 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
370 ath5k_hw_rf_gainf_corr(ah);
371 ah->ah_gain.g_current =
372 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
373 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
374 0;
375 }
376
377 /* Check if measurement is ok and if we need
378 * to adjust gain, schedule a gain adjustment,
379 * else switch back to the acive state */
380 if (ath5k_hw_rf_check_gainf_readback(ah) &&
381 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
382 ath5k_hw_rf_gainf_adjust(ah)) {
383 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
384 } else {
385 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
386 }
387 }
388
389done:
390 return ah->ah_gain.g_state;
391}
392
393/* Write initial rf gain table to set the RF sensitivity
394 * this one works on all RF chips and has nothing to do
395 * with gain_F calibration */
396int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
397{
398 const struct ath5k_ini_rfgain *ath5k_rfg;
399 unsigned int i, size;
400
401 switch (ah->ah_radio) {
402 case AR5K_RF5111:
403 ath5k_rfg = rfgain_5111;
404 size = ARRAY_SIZE(rfgain_5111);
405 break;
406 case AR5K_RF5112:
407 ath5k_rfg = rfgain_5112;
408 size = ARRAY_SIZE(rfgain_5112);
409 break;
410 case AR5K_RF2413:
411 ath5k_rfg = rfgain_2413;
412 size = ARRAY_SIZE(rfgain_2413);
413 break;
414 case AR5K_RF2316:
415 ath5k_rfg = rfgain_2316;
416 size = ARRAY_SIZE(rfgain_2316);
417 break;
418 case AR5K_RF5413:
419 ath5k_rfg = rfgain_5413;
420 size = ARRAY_SIZE(rfgain_5413);
421 break;
422 case AR5K_RF2317:
423 case AR5K_RF2425:
424 ath5k_rfg = rfgain_2425;
425 size = ARRAY_SIZE(rfgain_2425);
426 break;
427 default:
428 return -EINVAL;
429 }
430
431 switch (freq) {
432 case AR5K_INI_RFGAIN_2GHZ:
433 case AR5K_INI_RFGAIN_5GHZ:
434 break;
435 default:
436 return -EINVAL;
437 }
438
439 for (i = 0; i < size; i++) {
440 AR5K_REG_WAIT(i);
441 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
442 (u32)ath5k_rfg[i].rfg_register);
443 }
444
445 return 0;
446}
447
448
449
450/********************\
451* RF Registers setup *
452\********************/
453
fa1c114f
JS		 454/*
455 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
456 */
457static int ath5k_hw_rf5111_rfregs(struct ath5k_hw *ah,
458 struct ieee80211_channel *channel, unsigned int mode)
459{
460 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
461 u32 *rf;
33a31826 462 const unsigned int rf_size = ARRAY_SIZE(rfb_5111);
fa1c114f
JS		 463 unsigned int i;
464 int obdb = -1, bank = -1;
465 u32 ee_mode;
466
d8ee398d 467 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
fa1c114f
JS		 468
469 rf = ah->ah_rf_banks;
470
471 /* Copy values to modify them */
472 for (i = 0; i < rf_size; i++) {
33a31826 473 if (rfb_5111[i].rfb_bank >= AR5K_RF5111_INI_RF_MAX_BANKS) {
fa1c114f
JS		 474 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
475 return -EINVAL;
476 }
477
33a31826
NK		 478 if (bank != rfb_5111[i].rfb_bank) {
479 bank = rfb_5111[i].rfb_bank;
fa1c114f
JS		 480 ah->ah_offset[bank] = i;
481 }
482
33a31826 483 rf[i] = rfb_5111[i].rfb_mode_data[mode];
fa1c114f
JS		 484 }
485
486 /* Modify bank 0 */
d8ee398d
LR		 487 if (channel->hw_value & CHANNEL_2GHZ) {
488 if (channel->hw_value & CHANNEL_CCK)
fa1c114f
JS		 489 ee_mode = AR5K_EEPROM_MODE_11B;
490 else
491 ee_mode = AR5K_EEPROM_MODE_11G;
492 obdb = 0;
493
494 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
495 ee->ee_ob[ee_mode][obdb], 3, 119, 0, true))
496 return -EINVAL;
497
498 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[0],
499 ee->ee_ob[ee_mode][obdb], 3, 122, 0, true))
500 return -EINVAL;
501
502 obdb = 1;
503 /* Modify bank 6 */
504 } else {
505 /* For 11a, Turbo and XR */
506 ee_mode = AR5K_EEPROM_MODE_11A;
d8ee398d
LR		 507 obdb = channel->center_freq >= 5725 ? 3 :
508 (channel->center_freq >= 5500 ? 2 :
509 (channel->center_freq >= 5260 ? 1 :
510 (channel->center_freq > 4000 ? 0 : -1)));
fa1c114f
JS		 511
512 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
513 ee->ee_pwd_84, 1, 51, 3, true))
514 return -EINVAL;
515
516 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
517 ee->ee_pwd_90, 1, 45, 3, true))
518 return -EINVAL;
519 }
520
521 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
522 !ee->ee_xpd[ee_mode], 1, 95, 0, true))
523 return -EINVAL;
524
525 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
526 ee->ee_x_gain[ee_mode], 4, 96, 0, true))
527 return -EINVAL;
528
529 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
530 ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, true))
531 return -EINVAL;
532
533 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6], obdb >= 0 ?
534 ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, true))
535 return -EINVAL;
536
537 /* Modify bank 7 */
538 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
539 ee->ee_i_gain[ee_mode], 6, 29, 0, true))
540 return -EINVAL;
541
542 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
543 ee->ee_xpd[ee_mode], 1, 4, 0, true))
544 return -EINVAL;
545
546 /* Write RF values */
547 for (i = 0; i < rf_size; i++) {
548 AR5K_REG_WAIT(i);
33a31826 549 ath5k_hw_reg_write(ah, rf[i], rfb_5111[i].rfb_ctrl_register);
fa1c114f
JS		 550 }
551
6f3b414a
NK		 552 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
553
fa1c114f
JS		 554 return 0;
555}
556
557/*
558 * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
559 */
560static int ath5k_hw_rf5112_rfregs(struct ath5k_hw *ah,
561 struct ieee80211_channel *channel, unsigned int mode)
562{
33a31826 563 const struct ath5k_ini_rfbuffer *rf_ini;
fa1c114f
JS		 564 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
565 u32 *rf;
566 unsigned int rf_size, i;
567 int obdb = -1, bank = -1;
568 u32 ee_mode;
569
d8ee398d 570 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
fa1c114f
JS		 571
572 rf = ah->ah_rf_banks;
573
33a31826
NK		 574 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
575 rf_ini = rfb_5112a;
576 rf_size = ARRAY_SIZE(rfb_5112a);
fa1c114f 577 } else {
33a31826
NK		 578 rf_ini = rfb_5112;
579 rf_size = ARRAY_SIZE(rfb_5112);
fa1c114f
JS		 580 }
581
582 /* Copy values to modify them */
583 for (i = 0; i < rf_size; i++) {
33a31826 584 if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
fa1c114f
JS		 585 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
586 return -EINVAL;
587 }
588
33a31826
NK		 589 if (bank != rf_ini[i].rfb_bank) {
590 bank = rf_ini[i].rfb_bank;
fa1c114f
JS		 591 ah->ah_offset[bank] = i;
592 }
593
33a31826 594 rf[i] = rf_ini[i].rfb_mode_data[mode];
fa1c114f
JS		 595 }
596
597 /* Modify bank 6 */
d8ee398d
LR		 598 if (channel->hw_value & CHANNEL_2GHZ) {
599 if (channel->hw_value & CHANNEL_OFDM)
fa1c114f
JS		 600 ee_mode = AR5K_EEPROM_MODE_11G;
601 else
602 ee_mode = AR5K_EEPROM_MODE_11B;
603 obdb = 0;
604
605 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
606 ee->ee_ob[ee_mode][obdb], 3, 287, 0, true))
607 return -EINVAL;
608
609 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
610 ee->ee_ob[ee_mode][obdb], 3, 290, 0, true))
611 return -EINVAL;
612 } else {
613 /* For 11a, Turbo and XR */
614 ee_mode = AR5K_EEPROM_MODE_11A;
d8ee398d
LR		 615 obdb = channel->center_freq >= 5725 ? 3 :
616 (channel->center_freq >= 5500 ? 2 :
617 (channel->center_freq >= 5260 ? 1 :
618 (channel->center_freq > 4000 ? 0 : -1)));
fa1c114f 619
e71c9fac
LR		 620 if (obdb == -1)
621 return -EINVAL;
622
fa1c114f
JS		 623 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
624 ee->ee_ob[ee_mode][obdb], 3, 279, 0, true))
625 return -EINVAL;
626
627 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
628 ee->ee_ob[ee_mode][obdb], 3, 282, 0, true))
629 return -EINVAL;
630 }
631
632 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
633 ee->ee_x_gain[ee_mode], 2, 270, 0, true);
634 ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
635 ee->ee_x_gain[ee_mode], 2, 257, 0, true);
636
637 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[6],
638 ee->ee_xpd[ee_mode], 1, 302, 0, true))
639 return -EINVAL;
640
641 /* Modify bank 7 */
642 if (!ath5k_hw_rfregs_op(rf, ah->ah_offset[7],
643 ee->ee_i_gain[ee_mode], 6, 14, 0, true))
644 return -EINVAL;
645
646 /* Write RF values */
647 for (i = 0; i < rf_size; i++)
33a31826 648 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
fa1c114f 649
6f3b414a
NK		 650
651 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
652
fa1c114f
JS		 653 return 0;
654}
655
656/*
136bfc79
NK		 657 * Initialize RF5413/5414 and future chips
658 * (until we come up with a better solution)
fa1c114f
JS		 659 */
660static int ath5k_hw_rf5413_rfregs(struct ath5k_hw *ah,
661 struct ieee80211_channel *channel, unsigned int mode)
662{
33a31826 663 const struct ath5k_ini_rfbuffer *rf_ini;
fa1c114f
JS		 664 u32 *rf;
665 unsigned int rf_size, i;
666 int bank = -1;
667
d8ee398d 668 AR5K_ASSERT_ENTRY(mode, AR5K_MODE_MAX);
fa1c114f
JS		 669
670 rf = ah->ah_rf_banks;
671
136bfc79
NK		 672 switch (ah->ah_radio) {
673 case AR5K_RF5413:
33a31826
NK		 674 rf_ini = rfb_5413;
675 rf_size = ARRAY_SIZE(rfb_5413);
136bfc79
NK		 676 break;
677 case AR5K_RF2413:
33a31826
NK		 678 rf_ini = rfb_2413;
679 rf_size = ARRAY_SIZE(rfb_2413);
136bfc79 680
f714dd6d
NK		 681 if (mode < 2) {
682 ATH5K_ERR(ah->ah_sc,
683 "invalid channel mode: %i\n", mode);
684 return -EINVAL;
685 }
136bfc79 686
136bfc79
NK		 687 break;
688 case AR5K_RF2425:
33a31826
NK		 689 rf_ini = rfb_2425;
690 rf_size = ARRAY_SIZE(rfb_2425);
136bfc79
NK		 691
692 if (mode < 2) {
693 ATH5K_ERR(ah->ah_sc,
694 "invalid channel mode: %i\n", mode);
695 return -EINVAL;
696 }
697
136bfc79
NK		 698 break;
699 default:
f714dd6d
NK		 700 return -EINVAL;
701 }
fa1c114f
JS		 702
703 /* Copy values to modify them */
704 for (i = 0; i < rf_size; i++) {
33a31826 705 if (rf_ini[i].rfb_bank >= AR5K_RF5112_INI_RF_MAX_BANKS) {
fa1c114f
JS		 706 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
707 return -EINVAL;
708 }
709
33a31826
NK		 710 if (bank != rf_ini[i].rfb_bank) {
711 bank = rf_ini[i].rfb_bank;
fa1c114f
JS		 712 ah->ah_offset[bank] = i;
713 }
714
33a31826 715 rf[i] = rf_ini[i].rfb_mode_data[mode];
fa1c114f
JS		 716 }
717
718 /*
719 * After compairing dumps from different cards
720 * we get the same RF_BUFFER settings (diff returns
721 * 0 lines). It seems that RF_BUFFER settings are static
722 * and are written unmodified (no EEPROM stuff
723 * is used because calibration data would be
724 * different between different cards and would result
725 * different RF_BUFFER settings)
726 */
727
728 /* Write RF values */
729 for (i = 0; i < rf_size; i++)
33a31826 730 ath5k_hw_reg_write(ah, rf[i], rf_ini[i].rfb_ctrl_register);
fa1c114f
JS		 731
732 return 0;
733}
734
735/*
736 * Initialize RF
737 */
738int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel,
739 unsigned int mode)
740{
741 int (*func)(struct ath5k_hw *, struct ieee80211_channel *, unsigned int);
742 int ret;
743
744 switch (ah->ah_radio) {
745 case AR5K_RF5111:
33a31826 746 ah->ah_rf_banks_size = sizeof(rfb_5111);
fa1c114f
JS		 747 func = ath5k_hw_rf5111_rfregs;
748 break;
749 case AR5K_RF5112:
750 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
33a31826 751 ah->ah_rf_banks_size = sizeof(rfb_5112a);
fa1c114f 752 else
33a31826 753 ah->ah_rf_banks_size = sizeof(rfb_5112);
fa1c114f
JS		 754 func = ath5k_hw_rf5112_rfregs;
755 break;
756 case AR5K_RF5413:
33a31826 757 ah->ah_rf_banks_size = sizeof(rfb_5413);
fa1c114f
JS		 758 func = ath5k_hw_rf5413_rfregs;
759 break;
f714dd6d 760 case AR5K_RF2413:
33a31826 761 ah->ah_rf_banks_size = sizeof(rfb_2413);
f714dd6d
NK		 762 func = ath5k_hw_rf5413_rfregs;
763 break;
136bfc79 764 case AR5K_RF2425:
33a31826 765 ah->ah_rf_banks_size = sizeof(rfb_2425);
136bfc79
NK		 766 func = ath5k_hw_rf5413_rfregs;
767 break;
fa1c114f
JS		 768 default:
769 return -EINVAL;
770 }
771
772 if (ah->ah_rf_banks == NULL) {
773 /* XXX do extra checks? */
774 ah->ah_rf_banks = kmalloc(ah->ah_rf_banks_size, GFP_KERNEL);
775 if (ah->ah_rf_banks == NULL) {
776 ATH5K_ERR(ah->ah_sc, "out of memory\n");
777 return -ENOMEM;
778 }
779 }
780
781 ret = func(ah, channel, mode);
fa1c114f
JS		 782
783 return ret;
784}
785
fa1c114f 786
fa1c114f 787
fa1c114f
JS		 788
789/**************************\
790 PHY/RF channel functions
791\**************************/
792
793/*
794 * Check if a channel is supported
795 */
796bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
797{
798 /* Check if the channel is in our supported range */
799 if (flags & CHANNEL_2GHZ) {
800 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
801 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
802 return true;
803 } else if (flags & CHANNEL_5GHZ)
804 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
805 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
806 return true;
807
808 return false;
809}
810
811/*
812 * Convertion needed for RF5110
813 */
814static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
815{
816 u32 athchan;
817
818 /*
819 * Convert IEEE channel/MHz to an internal channel value used
820 * by the AR5210 chipset. This has not been verified with
821 * newer chipsets like the AR5212A who have a completely
822 * different RF/PHY part.
823 */
400ec45a
LR		 824 athchan = (ath5k_hw_bitswap(
825 (ieee80211_frequency_to_channel(
826 channel->center_freq) - 24) / 2, 5)
827 << 1) | (1 << 6) | 0x1;
fa1c114f
JS		 828 return athchan;
829}
830
831/*
832 * Set channel on RF5110
833 */
834static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
835 struct ieee80211_channel *channel)
836{
837 u32 data;
838
839 /*
840 * Set the channel and wait
841 */
842 data = ath5k_hw_rf5110_chan2athchan(channel);
843 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
844 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
845 mdelay(1);
846
847 return 0;
848}
849
850/*
851 * Convertion needed for 5111
852 */
853static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
854 struct ath5k_athchan_2ghz *athchan)
855{
856 int channel;
857
858 /* Cast this value to catch negative channel numbers (>= -19) */
859 channel = (int)ieee;
860
861 /*
862 * Map 2GHz IEEE channel to 5GHz Atheros channel
863 */
864 if (channel <= 13) {
865 athchan->a2_athchan = 115 + channel;
866 athchan->a2_flags = 0x46;
867 } else if (channel == 14) {
868 athchan->a2_athchan = 124;
869 athchan->a2_flags = 0x44;
870 } else if (channel >= 15 && channel <= 26) {
871 athchan->a2_athchan = ((channel - 14) * 4) + 132;
872 athchan->a2_flags = 0x46;
873 } else
874 return -EINVAL;
875
876 return 0;
877}
878
879/*
880 * Set channel on 5111
881 */
882static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
883 struct ieee80211_channel *channel)
884{
885 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
400ec45a
LR		 886 unsigned int ath5k_channel =
887 ieee80211_frequency_to_channel(channel->center_freq);
fa1c114f
JS		 888 u32 data0, data1, clock;
889 int ret;
890
891 /*
892 * Set the channel on the RF5111 radio
893 */
894 data0 = data1 = 0;
895
d8ee398d 896 if (channel->hw_value & CHANNEL_2GHZ) {
fa1c114f 897 /* Map 2GHz channel to 5GHz Atheros channel ID */
400ec45a
LR		 898 ret = ath5k_hw_rf5111_chan2athchan(
899 ieee80211_frequency_to_channel(channel->center_freq),
900 &ath5k_channel_2ghz);
fa1c114f
JS		 901 if (ret)
902 return ret;
903
904 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
905 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
906 << 5) | (1 << 4);
907 }
908
909 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
910 clock = 1;
911 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
912 (clock << 1) | (1 << 10) | 1;
913 } else {
914 clock = 0;
915 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
916 << 2) | (clock << 1) | (1 << 10) | 1;
917 }
918
919 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
920 AR5K_RF_BUFFER);
921 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
922 AR5K_RF_BUFFER_CONTROL_3);
923
924 return 0;
925}
926
927/*
928 * Set channel on 5112 and newer
929 */
930static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
931 struct ieee80211_channel *channel)
932{
933 u32 data, data0, data1, data2;
934 u16 c;
935
936 data = data0 = data1 = data2 = 0;
d8ee398d 937 c = channel->center_freq;
fa1c114f 938
fa1c114f
JS		 939 if (c < 4800) {
940 if (!((c - 2224) % 5)) {
941 data0 = ((2 * (c - 704)) - 3040) / 10;
942 data1 = 1;
943 } else if (!((c - 2192) % 5)) {
944 data0 = ((2 * (c - 672)) - 3040) / 10;
945 data1 = 0;
946 } else
947 return -EINVAL;
948
949 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
cc6323c7 950 } else if ((c - (c % 5)) != 2 || c > 5435) {
fa1c114f
JS		 951 if (!(c % 20) && c >= 5120) {
952 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
953 data2 = ath5k_hw_bitswap(3, 2);
954 } else if (!(c % 10)) {
955 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
956 data2 = ath5k_hw_bitswap(2, 2);
957 } else if (!(c % 5)) {
958 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
959 data2 = ath5k_hw_bitswap(1, 2);
960 } else
961 return -EINVAL;
cc6323c7
NK		 962 } else {
963 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
964 data2 = ath5k_hw_bitswap(0, 2);
fa1c114f
JS		 965 }
966
967 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
968
969 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
970 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
971
972 return 0;
973}
974
cc6323c7
NK		 975/*
976 * Set the channel on the RF2425
977 */
978static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
979 struct ieee80211_channel *channel)
980{
981 u32 data, data0, data2;
982 u16 c;
983
984 data = data0 = data2 = 0;
985 c = channel->center_freq;
986
987 if (c < 4800) {
988 data0 = ath5k_hw_bitswap((c - 2272), 8);
989 data2 = 0;
990 /* ? 5GHz ? */
991 } else if ((c - (c % 5)) != 2 || c > 5435) {
992 if (!(c % 20) && c < 5120)
993 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
994 else if (!(c % 10))
995 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
996 else if (!(c % 5))
997 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
998 else
999 return -EINVAL;
1000 data2 = ath5k_hw_bitswap(1, 2);
1001 } else {
1002 data0 = ath5k_hw_bitswap((10 * (c - 2) - 4800) / 25 + 1, 8);
1003 data2 = ath5k_hw_bitswap(0, 2);
1004 }
1005
1006 data = (data0 << 4) | data2 << 2 | 0x1001;
1007
1008 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1009 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1010
1011 return 0;
1012}
1013
fa1c114f
JS		 1014/*
1015 * Set a channel on the radio chip
1016 */
1017int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel)
1018{
1019 int ret;
fa1c114f 1020 /*
400ec45a
LR		 1021 * Check bounds supported by the PHY (we don't care about regultory
1022 * restrictions at this point). Note: hw_value already has the band
1023 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1024 * of the band by that */
1025 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
fa1c114f 1026 ATH5K_ERR(ah->ah_sc,
400ec45a
LR		 1027 "channel frequency (%u MHz) out of supported "
1028 "band range\n",
d8ee398d 1029 channel->center_freq);
400ec45a 1030 return -EINVAL;
fa1c114f
JS		 1031 }
1032
1033 /*
1034 * Set the channel and wait
1035 */
1036 switch (ah->ah_radio) {
1037 case AR5K_RF5110:
1038 ret = ath5k_hw_rf5110_channel(ah, channel);
1039 break;
1040 case AR5K_RF5111:
1041 ret = ath5k_hw_rf5111_channel(ah, channel);
1042 break;
cc6323c7
NK		 1043 case AR5K_RF2425:
1044 ret = ath5k_hw_rf2425_channel(ah, channel);
1045 break;
fa1c114f
JS		 1046 default:
1047 ret = ath5k_hw_rf5112_channel(ah, channel);
1048 break;
1049 }
1050
1051 if (ret)
1052 return ret;
1053
cc6323c7
NK		 1054 /* Set JAPAN setting for channel 14 */
1055 if (channel->center_freq == 2484) {
1056 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1057 AR5K_PHY_CCKTXCTL_JAPAN);
1058 } else {
1059 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1060 AR5K_PHY_CCKTXCTL_WORLD);
1061 }
1062
d8ee398d
LR		 1063 ah->ah_current_channel.center_freq = channel->center_freq;
1064 ah->ah_current_channel.hw_value = channel->hw_value;
1065 ah->ah_turbo = channel->hw_value == CHANNEL_T ? true : false;
fa1c114f
JS		 1066
1067 return 0;
1068}
1069
1070/*****************\
1071 PHY calibration
1072\*****************/
1073
1074/**
1075 * ath5k_hw_noise_floor_calibration - perform PHY noise floor calibration
1076 *
1077 * @ah: struct ath5k_hw pointer we are operating on
1078 * @freq: the channel frequency, just used for error logging
1079 *
1080 * This function performs a noise floor calibration of the PHY and waits for
1081 * it to complete. Then the noise floor value is compared to some maximum
1082 * noise floor we consider valid.
1083 *
1084 * Note that this is different from what the madwifi HAL does: it reads the
1085 * noise floor and afterwards initiates the calibration. Since the noise floor
1086 * calibration can take some time to finish, depending on the current channel
1087 * use, that avoids the occasional timeout warnings we are seeing now.
1088 *
1089 * See the following link for an Atheros patent on noise floor calibration:
1090 * http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL \
1091 * &p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=7245893.PN.&OS=PN/7
1092 *
f860ee26
NK		 1093 * XXX: Since during noise floor calibration antennas are detached according to
1094 * the patent, we should stop tx queues here.
fa1c114f
JS		 1095 */
1096int
1097ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq)
1098{
1099 int ret;
1100 unsigned int i;
1101 s32 noise_floor;
1102
1103 /*
f860ee26 1104 * Enable noise floor calibration
fa1c114f
JS		 1105 */
1106 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1107 AR5K_PHY_AGCCTL_NF);
1108
1109 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1110 AR5K_PHY_AGCCTL_NF, 0, false);
1111 if (ret) {
1112 ATH5K_ERR(ah->ah_sc,
1113 "noise floor calibration timeout (%uMHz)\n", freq);
f860ee26 1114 return -EAGAIN;
fa1c114f
JS		 1115 }
1116
1117 /* Wait until the noise floor is calibrated and read the value */
1118 for (i = 20; i > 0; i--) {
1119 mdelay(1);
1120 noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1121 noise_floor = AR5K_PHY_NF_RVAL(noise_floor);
1122 if (noise_floor & AR5K_PHY_NF_ACTIVE) {
1123 noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
1124
1125 if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
1126 break;
1127 }
1128 }
1129
1130 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1131 "noise floor %d\n", noise_floor);
1132
1133 if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
1134 ATH5K_ERR(ah->ah_sc,
1135 "noise floor calibration failed (%uMHz)\n", freq);
f860ee26 1136 return -EAGAIN;
fa1c114f
JS		 1137 }
1138
1139 ah->ah_noise_floor = noise_floor;
1140
1141 return 0;
1142}
1143
1144/*
1145 * Perform a PHY calibration on RF5110
1146 * -Fix BPSK/QAM Constellation (I/Q correction)
1147 * -Calculate Noise Floor
1148 */
1149static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1150 struct ieee80211_channel *channel)
1151{
1152 u32 phy_sig, phy_agc, phy_sat, beacon;
1153 int ret;
1154
1155 /*
1156 * Disable beacons and RX/TX queues, wait
1157 */
1158 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1159 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1160 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1161 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1162
84e463fa 1163 mdelay(2);
fa1c114f
JS		 1164
1165 /*
1166 * Set the channel (with AGC turned off)
1167 */
1168 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1169 udelay(10);
1170 ret = ath5k_hw_channel(ah, channel);
1171
1172 /*
1173 * Activate PHY and wait
1174 */
1175 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1176 mdelay(1);
1177
1178 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1179
1180 if (ret)
1181 return ret;
1182
1183 /*
1184 * Calibrate the radio chip
1185 */
1186
1187 /* Remember normal state */
1188 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1189 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1190 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1191
1192 /* Update radio registers */
1193 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1194 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1195
1196 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1197 AR5K_PHY_AGCCOARSE_LO)) |
1198 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1199 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1200
1201 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1202 AR5K_PHY_ADCSAT_THR)) |
1203 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1204 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1205
1206 udelay(20);
1207
1208 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1209 udelay(10);
1210 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1211 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1212
1213 mdelay(1);
1214
1215 /*
1216 * Enable calibration and wait until completion
1217 */
1218 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1219
1220 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1221 AR5K_PHY_AGCCTL_CAL, 0, false);
1222
1223 /* Reset to normal state */
1224 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1225 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1226 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1227
1228 if (ret) {
1229 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
d8ee398d 1230 channel->center_freq);
fa1c114f
JS		 1231 return ret;
1232 }
1233
8b0162a3 1234 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f
JS		 1235
1236 /*
1237 * Re-enable RX/TX and beacons
1238 */
1239 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1240 AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
1241 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1242
1243 return 0;
1244}
1245
1246/*
f860ee26 1247 * Perform a PHY calibration on RF5111/5112 and newer chips
fa1c114f
JS		 1248 */
1249static int ath5k_hw_rf511x_calibrate(struct ath5k_hw *ah,
1250 struct ieee80211_channel *channel)
1251{
1252 u32 i_pwr, q_pwr;
1253 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
f860ee26 1254 int i;
fa1c114f
JS		 1255 ATH5K_TRACE(ah->ah_sc);
1256
e9010e2f 1257 if (!ah->ah_calibration ||
f860ee26 1258 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
fa1c114f
JS		 1259 goto done;
1260
f860ee26
NK		 1261 /* Calibration has finished, get the results and re-run */
1262 for (i = 0; i <= 10; i++) {
1263 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1264 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1265 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1266 }
fa1c114f 1267
fa1c114f 1268 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
f860ee26 1269 q_coffd = q_pwr >> 7;
fa1c114f 1270
f860ee26 1271 /* No correction */
fa1c114f
JS		 1272 if (i_coffd == 0 || q_coffd == 0)
1273 goto done;
1274
1275 i_coff = ((-iq_corr) / i_coffd) & 0x3f;
fa1c114f 1276
f860ee26
NK		 1277 /* Boundary check */
1278 if (i_coff > 31)
1279 i_coff = 31;
1280 if (i_coff < -32)
1281 i_coff = -32;
1282
1283 q_coff = (((s32)i_pwr / q_coffd) - 128) & 0x1f;
1284
1285 /* Boundary check */
1286 if (q_coff > 15)
1287 q_coff = 15;
1288 if (q_coff < -16)
1289 q_coff = -16;
1290
1291 /* Commit new I/Q value */
fa1c114f
JS		 1292 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE |
1293 ((u32)q_coff) | ((u32)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
1294
f860ee26
NK		 1295 /* Re-enable calibration -if we don't we'll commit
1296 * the same values again and again */
1297 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1298 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1299 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1300
fa1c114f 1301done:
f860ee26
NK		 1302
1303 /* TODO: Separate noise floor calibration from I/Q calibration
1304 * since noise floor calibration interrupts rx path while I/Q
1305 * calibration doesn't. We don't need to run noise floor calibration
1306 * as often as I/Q calibration.*/
d8ee398d 1307 ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f 1308
6f3b414a
NK		 1309 /* Initiate a gain_F calibration */
1310 ath5k_hw_request_rfgain_probe(ah);
fa1c114f
JS		 1311
1312 return 0;
1313}
1314
1315/*
1316 * Perform a PHY calibration
1317 */
1318int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1319 struct ieee80211_channel *channel)
1320{
1321 int ret;
1322
1323 if (ah->ah_radio == AR5K_RF5110)
1324 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1325 else
1326 ret = ath5k_hw_rf511x_calibrate(ah, channel);
1327
1328 return ret;
1329}
1330
1331int ath5k_hw_phy_disable(struct ath5k_hw *ah)
1332{
1333 ATH5K_TRACE(ah->ah_sc);
1334 /*Just a try M.F.*/
1335 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1336
1337 return 0;
1338}
1339
1340/********************\
1341 Misc PHY functions
1342\********************/
1343
1344/*
1345 * Get the PHY Chip revision
1346 */
1347u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
1348{
1349 unsigned int i;
1350 u32 srev;
1351 u16 ret;
1352
1353 ATH5K_TRACE(ah->ah_sc);
1354
1355 /*
1356 * Set the radio chip access register
1357 */
1358 switch (chan) {
1359 case CHANNEL_2GHZ:
1360 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
1361 break;
1362 case CHANNEL_5GHZ:
1363 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1364 break;
1365 default:
1366 return 0;
1367 }
1368
1369 mdelay(2);
1370
1371 /* ...wait until PHY is ready and read the selected radio revision */
1372 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
1373
1374 for (i = 0; i < 8; i++)
1375 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
1376
1377 if (ah->ah_version == AR5K_AR5210) {
1378 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
1379 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
1380 } else {
1381 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
1382 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
1383 ((srev & 0x0f) << 4), 8);
1384 }
1385
1386 /* Reset to the 5GHz mode */
1387 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
1388
1389 return ret;
1390}
1391
1392void /*TODO:Boundary check*/
1393ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant)
1394{
1395 ATH5K_TRACE(ah->ah_sc);
1396 /*Just a try M.F.*/
1397 if (ah->ah_version != AR5K_AR5210)
1398 ath5k_hw_reg_write(ah, ant, AR5K_DEFAULT_ANTENNA);
1399}
1400
1401unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah)
1402{
1403 ATH5K_TRACE(ah->ah_sc);
1404 /*Just a try M.F.*/
1405 if (ah->ah_version != AR5K_AR5210)
1406 return ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
1407
1408 return false; /*XXX: What do we return for 5210 ?*/
1409}
1410
1411/*
1412 * TX power setup
1413 */
1414
1415/*
1416 * Initialize the tx power table (not fully implemented)
1417 */
1418static void ath5k_txpower_table(struct ath5k_hw *ah,
1419 struct ieee80211_channel *channel, s16 max_power)
1420{
1421 unsigned int i, min, max, n;
1422 u16 txpower, *rates;
1423
1424 rates = ah->ah_txpower.txp_rates;
1425
1426 txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
1427 if (max_power > txpower)
1428 txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
1429 AR5K_TUNE_MAX_TXPOWER : max_power;
1430
1431 for (i = 0; i < AR5K_MAX_RATES; i++)
1432 rates[i] = txpower;
1433
1434 /* XXX setup target powers by rate */
1435
1436 ah->ah_txpower.txp_min = rates[7];
1437 ah->ah_txpower.txp_max = rates[0];
1438 ah->ah_txpower.txp_ofdm = rates[0];
1439
1440 /* Calculate the power table */
1441 n = ARRAY_SIZE(ah->ah_txpower.txp_pcdac);
1442 min = AR5K_EEPROM_PCDAC_START;
1443 max = AR5K_EEPROM_PCDAC_STOP;
1444 for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
1445 ah->ah_txpower.txp_pcdac[i] =
1446#ifdef notyet
1447 min + ((i * (max - min)) / n);
1448#else
1449 min;
1450#endif
1451}
1452
1453/*
1454 * Set transmition power
1455 */
1456int /*O.K. - txpower_table is unimplemented so this doesn't work*/
1457ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1458 unsigned int txpower)
1459{
1460 bool tpc = ah->ah_txpower.txp_tpc;
1461 unsigned int i;
1462
1463 ATH5K_TRACE(ah->ah_sc);
1464 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
1465 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
1466 return -EINVAL;
1467 }
1468
903b474e
NK		 1469 /*
1470 * RF2413 for some reason can't
1471 * transmit anything if we call
1472 * this funtion, so we skip it
1473 * until we fix txpower.
136bfc79
NK		 1474 *
1475 * XXX: Assume same for RF2425
1476 * to be safe.
903b474e 1477 */
136bfc79 1478 if ((ah->ah_radio == AR5K_RF2413) || (ah->ah_radio == AR5K_RF2425))
903b474e
NK		 1479 return 0;
1480
fa1c114f
JS		 1481 /* Reset TX power values */
1482 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
1483 ah->ah_txpower.txp_tpc = tpc;
1484
1485 /* Initialize TX power table */
1486 ath5k_txpower_table(ah, channel, txpower);
1487
1488 /*
1489 * Write TX power values
1490 */
1491 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
1492 ath5k_hw_reg_write(ah,
1493 ((((ah->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff) & 0xffff) << 16) |
1494 (((ah->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff) & 0xffff),
1495 AR5K_PHY_PCDAC_TXPOWER(i));
1496 }
1497
1498 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
1499 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
1500 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
1501
1502 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
1503 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
1504 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
1505
1506 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
1507 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
1508 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
1509
1510 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
1511 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
1512 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
1513
e9010e2f 1514 if (ah->ah_txpower.txp_tpc)
fa1c114f
JS		 1515 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
1516 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
1517 else
1518 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
1519 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
1520
1521 return 0;
1522}
1523
1524int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power)
1525{
1526 /*Just a try M.F.*/
1527 struct ieee80211_channel *channel = &ah->ah_current_channel;
1528
1529 ATH5K_TRACE(ah->ah_sc);
1530 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
1531 "changing txpower to %d\n", power);
1532
1533 return ath5k_hw_txpower(ah, channel, power);
1534}
c6e387a2
NK		 1535
1536#undef _ATH5K_PHY
Linux 6.x block layer and io_uring tree(s)