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ath5k: Port to new bitrate/channel API
[linux-2.6-block.git] / drivers / net / wireless / ath5k / hw.c
CommitLineData
fa1c114f
JS		 1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23/*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27#include <linux/pci.h>
28#include <linux/delay.h>
29
30#include "reg.h"
31#include "base.h"
32#include "debug.h"
33
34/*Rate tables*/
35static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41/*Prototypes*/
42static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
b9887638 48static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
52static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
53 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
54 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int);
56static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
57static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *);
58static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *);
59static int ath5k_hw_get_capabilities(struct ath5k_hw *);
60
61static int ath5k_eeprom_init(struct ath5k_hw *);
62static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
63
64static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
65static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
66
67/*
68 * Enable to overwrite the country code (use "00" for debug)
69 */
70#if 0
71#define COUNTRYCODE "00"
72#endif
73
74/*******************\
75 General Functions
76\*******************/
77
78/*
79 * Functions used internaly
80 */
81
82static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
83{
84 return turbo == true ? (usec * 80) : (usec * 40);
85}
86
87static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
88{
89 return turbo == true ? (clock / 80) : (clock / 40);
90}
91
92/*
93 * Check if a register write has been completed
94 */
95int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
96 bool is_set)
97{
98 int i;
99 u32 data;
100
101 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
102 data = ath5k_hw_reg_read(ah, reg);
103 if ((is_set == true) && (data & flag))
104 break;
105 else if ((data & flag) == val)
106 break;
107 udelay(15);
108 }
109
110 return (i <= 0) ? -EAGAIN : 0;
111}
112
113
114/***************************************\
115 Attach/Detach Functions
116\***************************************/
117
118/*
119 * Check if the device is supported and initialize the needed structs
120 */
121struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
122{
123 struct ath5k_hw *ah;
124 u8 mac[ETH_ALEN];
125 int ret;
126 u32 srev;
127
128 /*If we passed the test malloc a ath5k_hw struct*/
129 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
130 if (ah == NULL) {
131 ret = -ENOMEM;
132 ATH5K_ERR(sc, "out of memory\n");
133 goto err;
134 }
135
136 ah->ah_sc = sc;
137 ah->ah_iobase = sc->iobase;
138
139 /*
140 * HW information
141 */
142
fa1c114f
JS		 143 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
144 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
145 ah->ah_turbo = false;
146 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
147 ah->ah_imr = 0;
148 ah->ah_atim_window = 0;
149 ah->ah_aifs = AR5K_TUNE_AIFS;
150 ah->ah_cw_min = AR5K_TUNE_CWMIN;
151 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
152 ah->ah_software_retry = false;
153 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
154
155 /*
156 * Set the mac revision based on the pci id
157 */
158 ah->ah_version = mac_version;
159
160 /*Fill the ath5k_hw struct with the needed functions*/
161 if (ah->ah_version == AR5K_AR5212)
162 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
163 else if (ah->ah_version == AR5K_AR5211)
164 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
165
166 if (ah->ah_version == AR5K_AR5212) {
167 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
168 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
169 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
170 } else {
171 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
172 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
173 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
174 }
175
176 if (ah->ah_version == AR5K_AR5212)
177 ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
178 else if (ah->ah_version <= AR5K_AR5211)
179 ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
180
181 /* Bring device out of sleep and reset it's units */
182 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
183 if (ret)
184 goto err_free;
185
186 /* Get MAC, PHY and RADIO revisions */
187 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
188 ah->ah_mac_srev = srev;
189 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
190 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
191 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
192 0xffffffff;
193 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
194 CHANNEL_5GHZ);
195
196 if (ah->ah_version == AR5K_AR5210)
197 ah->ah_radio_2ghz_revision = 0;
198 else
199 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
200 CHANNEL_2GHZ);
201
202 /* Return on unsuported chips (unsupported eeprom etc) */
203 if(srev >= AR5K_SREV_VER_AR5416){
204 ATH5K_ERR(sc, "Device not yet supported.\n");
205 ret = -ENODEV;
206 goto err_free;
207 }
208
209 /* Identify single chip solutions */
210 if((srev <= AR5K_SREV_VER_AR5414) &&
211 (srev >= AR5K_SREV_VER_AR2424)) {
212 ah->ah_single_chip = true;
213 } else {
214 ah->ah_single_chip = false;
215 }
216
217 /* Single chip radio */
218 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
219 ah->ah_radio_2ghz_revision = 0;
220
221 /* Identify the radio chip*/
222 if (ah->ah_version == AR5K_AR5210) {
223 ah->ah_radio = AR5K_RF5110;
224 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
225 ah->ah_radio = AR5K_RF5111;
226 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
227 ah->ah_radio = AR5K_RF5112;
228 } else {
229 ah->ah_radio = AR5K_RF5413;
230 }
231
232 ah->ah_phy = AR5K_PHY(0);
233
234 /*
235 * Get card capabilities, values, ...
236 */
237
238 ret = ath5k_eeprom_init(ah);
239 if (ret) {
240 ATH5K_ERR(sc, "unable to init EEPROM\n");
241 goto err_free;
242 }
243
244 /* Get misc capabilities */
245 ret = ath5k_hw_get_capabilities(ah);
246 if (ret) {
247 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
248 sc->pdev->device);
249 goto err_free;
250 }
251
252 /* Get MAC address */
253 ret = ath5k_eeprom_read_mac(ah, mac);
254 if (ret) {
255 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
256 sc->pdev->device);
257 goto err_free;
258 }
259
260 ath5k_hw_set_lladdr(ah, mac);
261 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
262 memset(ah->ah_bssid, 0xff, ETH_ALEN);
263 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
264 ath5k_hw_set_opmode(ah);
265
266 ath5k_hw_set_rfgain_opt(ah);
267
268 return ah;
269err_free:
270 kfree(ah);
271err:
272 return ERR_PTR(ret);
273}
274
275/*
276 * Bring up MAC + PHY Chips
277 */
278static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
279{
280 u32 turbo, mode, clock;
281 int ret;
282
283 turbo = 0;
284 mode = 0;
285 clock = 0;
286
287 ATH5K_TRACE(ah->ah_sc);
288
289 /* Wakeup the device */
290 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
291 if (ret) {
292 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
293 return ret;
294 }
295
296 if (ah->ah_version != AR5K_AR5210) {
297 /*
298 * Get channel mode flags
299 */
300
301 if (ah->ah_radio >= AR5K_RF5112) {
302 mode = AR5K_PHY_MODE_RAD_RF5112;
303 clock = AR5K_PHY_PLL_RF5112;
304 } else {
305 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
306 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
307 }
308
309 if (flags & CHANNEL_2GHZ) {
310 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
311 clock |= AR5K_PHY_PLL_44MHZ;
312
313 if (flags & CHANNEL_CCK) {
314 mode |= AR5K_PHY_MODE_MOD_CCK;
315 } else if (flags & CHANNEL_OFDM) {
316 /* XXX Dynamic OFDM/CCK is not supported by the
317 * AR5211 so we set MOD_OFDM for plain g (no
318 * CCK headers) operation. We need to test
319 * this, 5211 might support ofdm-only g after
320 * all, there are also initial register values
321 * in the code for g mode (see initvals.c). */
322 if (ah->ah_version == AR5K_AR5211)
323 mode |= AR5K_PHY_MODE_MOD_OFDM;
324 else
325 mode |= AR5K_PHY_MODE_MOD_DYN;
326 } else {
327 ATH5K_ERR(ah->ah_sc,
328 "invalid radio modulation mode\n");
329 return -EINVAL;
330 }
331 } else if (flags & CHANNEL_5GHZ) {
332 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
333 clock |= AR5K_PHY_PLL_40MHZ;
334
335 if (flags & CHANNEL_OFDM)
336 mode |= AR5K_PHY_MODE_MOD_OFDM;
337 else {
338 ATH5K_ERR(ah->ah_sc,
339 "invalid radio modulation mode\n");
340 return -EINVAL;
341 }
342 } else {
343 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
344 return -EINVAL;
345 }
346
347 if (flags & CHANNEL_TURBO)
348 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
349 } else { /* Reset the device */
350
351 /* ...enable Atheros turbo mode if requested */
352 if (flags & CHANNEL_TURBO)
353 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
354 AR5K_PHY_TURBO);
355 }
356
357 /* ...reset chipset and PCI device */
358 if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah,
359 AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
360 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n");
361 return -EIO;
362 }
363
364 if (ah->ah_version == AR5K_AR5210)
365 udelay(2300);
366
367 /* ...wakeup again!*/
368 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
369 if (ret) {
370 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
371 return ret;
372 }
373
374 /* ...final warm reset */
375 if (ath5k_hw_nic_reset(ah, 0)) {
376 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
377 return -EIO;
378 }
379
380 if (ah->ah_version != AR5K_AR5210) {
381 /* ...set the PHY operating mode */
382 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
383 udelay(300);
384
385 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
386 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
387 }
388
389 return 0;
390}
391
392/*
393 * Get the rate table for a specific operation mode
394 */
395const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
396 unsigned int mode)
397{
398 ATH5K_TRACE(ah->ah_sc);
399
400 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
401 return NULL;
402
403 /* Get rate tables */
404 switch (mode) {
d8ee398d 405 case AR5K_MODE_11A:
fa1c114f 406 return &ath5k_rt_11a;
d8ee398d 407 case AR5K_MODE_11A_TURBO:
fa1c114f 408 return &ath5k_rt_turbo;
d8ee398d 409 case AR5K_MODE_11B:
fa1c114f 410 return &ath5k_rt_11b;
d8ee398d 411 case AR5K_MODE_11G:
fa1c114f 412 return &ath5k_rt_11g;
d8ee398d 413 case AR5K_MODE_11G_TURBO:
fa1c114f
JS		 414 return &ath5k_rt_xr;
415 }
416
417 return NULL;
418}
419
420/*
421 * Free the ath5k_hw struct
422 */
423void ath5k_hw_detach(struct ath5k_hw *ah)
424{
425 ATH5K_TRACE(ah->ah_sc);
426
427 if (ah->ah_rf_banks != NULL)
428 kfree(ah->ah_rf_banks);
429
430 /* assume interrupts are down */
431 kfree(ah);
432}
433
434/****************************\
435 Reset function and helpers
436\****************************/
437
438/**
439 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
440 *
441 * @ah: the &struct ath5k_hw
442 * @channel: the currently set channel upon reset
443 *
444 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
445 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
446 * depending on the bandwidth of the channel.
447 *
448 */
449static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
450 struct ieee80211_channel *channel)
451{
452 /* Get exponent and mantissa and set it */
453 u32 coef_scaled, coef_exp, coef_man,
454 ds_coef_exp, ds_coef_man, clock;
455
456 if (!(ah->ah_version == AR5K_AR5212) ||
d8ee398d 457 !(channel->hw_value & CHANNEL_OFDM))
fa1c114f
JS		 458 BUG();
459
460 /* Seems there are two PLLs, one for baseband sampling and one
461 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
462 * turbo. */
d8ee398d 463 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
fa1c114f 464 coef_scaled = ((5 * (clock << 24)) / 2) /
d8ee398d 465 channel->center_freq;
fa1c114f
JS		 466
467 for (coef_exp = 31; coef_exp > 0; coef_exp--)
468 if ((coef_scaled >> coef_exp) & 0x1)
469 break;
470
471 if (!coef_exp)
472 return -EINVAL;
473
474 coef_exp = 14 - (coef_exp - 24);
475 coef_man = coef_scaled +
476 (1 << (24 - coef_exp - 1));
477 ds_coef_man = coef_man >> (24 - coef_exp);
478 ds_coef_exp = coef_exp - 16;
479
480 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
481 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
482 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
483 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
484
485 return 0;
486}
487
488/**
489 * ath5k_hw_write_rate_duration - set rate duration during hw resets
490 *
491 * @ah: the &struct ath5k_hw
d8ee398d 492 * @mode: one of enum ath5k_driver_mode
fa1c114f
JS		 493 *
494 * Write the rate duration table for the current mode upon hw reset. This
495 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
496 * an ACK timeout for the hardware for the current mode for each rate. The
497 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
498 * and 11Mbps) have another register for the short preamble ACK timeout
499 * calculation.
500 *
501 */
502static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
d8ee398d 503 unsigned int mode)
fa1c114f
JS		 504{
505 struct ath5k_softc *sc = ah->ah_sc;
506 const struct ath5k_rate_table *rt;
d8ee398d 507 struct ieee80211_rate srate = {};
fa1c114f
JS		 508 unsigned int i;
509
510 /* Get rate table for the current operating mode */
d8ee398d 511 rt = ath5k_hw_get_rate_table(ah, mode);
fa1c114f
JS		 512
513 /* Write rate duration table */
514 for (i = 0; i < rt->rate_count; i++) {
515 const struct ath5k_rate *rate, *control_rate;
d8ee398d 516
fa1c114f
JS		 517 u32 reg;
518 u16 tx_time;
519
520 rate = &rt->rates[i];
521 control_rate = &rt->rates[rate->control_rate];
522
523 /* Set ACK timeout */
524 reg = AR5K_RATE_DUR(rate->rate_code);
525
d8ee398d
LR		 526 srate.bitrate = control_rate->rate_kbps/100;
527
fa1c114f
JS		 528 /* An ACK frame consists of 10 bytes. If you add the FCS,
529 * which ieee80211_generic_frame_duration() adds,
530 * its 14 bytes. Note we use the control rate and not the
531 * actual rate for this rate. See mac80211 tx.c
532 * ieee80211_duration() for a brief description of
533 * what rate we should choose to TX ACKs. */
534 tx_time = ieee80211_generic_frame_duration(sc->hw,
d8ee398d 535 sc->vif, 10, &srate);
fa1c114f
JS		 536
537 ath5k_hw_reg_write(ah, tx_time, reg);
538
539 if (!HAS_SHPREAMBLE(i))
540 continue;
541
542 /*
543 * We're not distinguishing short preamble here,
544 * This is true, all we'll get is a longer value here
545 * which is not necessarilly bad. We could use
546 * export ieee80211_frame_duration() but that needs to be
547 * fixed first to be properly used by mac802111 drivers:
548 *
549 * - remove erp stuff and let the routine figure ofdm
550 * erp rates
551 * - remove passing argument ieee80211_local as
552 * drivers don't have access to it
553 * - move drivers using ieee80211_generic_frame_duration()
554 * to this
555 */
556 ath5k_hw_reg_write(ah, tx_time,
557 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
558 }
559}
560
561/*
562 * Main reset function
563 */
564int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
565 struct ieee80211_channel *channel, bool change_channel)
566{
567 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
568 u32 data, s_seq, s_ant, s_led[3];
d8ee398d 569 unsigned int i, mode, freq, ee_mode, ant[2];
fa1c114f
JS		 570 int ret;
571
572 ATH5K_TRACE(ah->ah_sc);
573
574 s_seq = 0;
575 s_ant = 0;
576 ee_mode = 0;
577 freq = 0;
578 mode = 0;
579
580 /*
581 * Save some registers before a reset
582 */
583 /*DCU/Antenna selection not available on 5210*/
584 if (ah->ah_version != AR5K_AR5210) {
585 if (change_channel == true) {
586 /* Seq number for queue 0 -do this for all queues ? */
587 s_seq = ath5k_hw_reg_read(ah,
588 AR5K_QUEUE_DFS_SEQNUM(0));
589 /*Default antenna*/
590 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
591 }
592 }
593
594 /*GPIOs*/
595 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
596 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
597 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
598
599 if (change_channel == true && ah->ah_rf_banks != NULL)
600 ath5k_hw_get_rf_gain(ah);
601
602
603 /*Wakeup the device*/
d8ee398d 604 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
fa1c114f
JS		 605 if (ret)
606 return ret;
607
608 /*
609 * Initialize operating mode
610 */
611 ah->ah_op_mode = op_mode;
612
613 /*
614 * 5111/5112 Settings
615 * 5210 only comes with RF5110
616 */
617 if (ah->ah_version != AR5K_AR5210) {
618 if (ah->ah_radio != AR5K_RF5111 &&
619 ah->ah_radio != AR5K_RF5112 &&
620 ah->ah_radio != AR5K_RF5413) {
621 ATH5K_ERR(ah->ah_sc,
622 "invalid phy radio: %u\n", ah->ah_radio);
623 return -EINVAL;
624 }
625
d8ee398d 626 switch (channel->hw_value & CHANNEL_MODES) {
fa1c114f 627 case CHANNEL_A:
d8ee398d 628 mode = AR5K_MODE_11A;
fa1c114f
JS		 629 freq = AR5K_INI_RFGAIN_5GHZ;
630 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 631 break;
632 case CHANNEL_G:
d8ee398d 633 mode = AR5K_MODE_11G;
fa1c114f
JS		 634 freq = AR5K_INI_RFGAIN_2GHZ;
635 ee_mode = AR5K_EEPROM_MODE_11G;
fa1c114f
JS		 636 break;
637 case CHANNEL_B:
d8ee398d 638 mode = AR5K_MODE_11B;
fa1c114f
JS		 639 freq = AR5K_INI_RFGAIN_2GHZ;
640 ee_mode = AR5K_EEPROM_MODE_11B;
fa1c114f
JS		 641 break;
642 case CHANNEL_T:
d8ee398d 643 mode = AR5K_MODE_11A_TURBO;
fa1c114f
JS		 644 freq = AR5K_INI_RFGAIN_5GHZ;
645 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 646 break;
647 /*Is this ok on 5211 too ?*/
648 case CHANNEL_TG:
d8ee398d 649 mode = AR5K_MODE_11G_TURBO;
fa1c114f
JS		 650 freq = AR5K_INI_RFGAIN_2GHZ;
651 ee_mode = AR5K_EEPROM_MODE_11G;
fa1c114f
JS		 652 break;
653 case CHANNEL_XR:
654 if (ah->ah_version == AR5K_AR5211) {
655 ATH5K_ERR(ah->ah_sc,
656 "XR mode not available on 5211");
657 return -EINVAL;
658 }
d8ee398d 659 mode = AR5K_MODE_XR;
fa1c114f
JS		 660 freq = AR5K_INI_RFGAIN_5GHZ;
661 ee_mode = AR5K_EEPROM_MODE_11A;
fa1c114f
JS		 662 break;
663 default:
664 ATH5K_ERR(ah->ah_sc,
d8ee398d 665 "invalid channel: %d\n", channel->center_freq);
fa1c114f
JS		 666 return -EINVAL;
667 }
668
669 /* PHY access enable */
670 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
671
672 }
673
674 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
675 if (ret)
676 return ret;
677
678 /*
679 * 5211/5212 Specific
680 */
681 if (ah->ah_version != AR5K_AR5210) {
682 /*
683 * Write initial RF gain settings
684 * This should work for both 5111/5112
685 */
686 ret = ath5k_hw_rfgain(ah, freq);
687 if (ret)
688 return ret;
689
690 mdelay(1);
691
692 /*
693 * Write some more initial register settings
694 */
695 if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */
696 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
697
d8ee398d 698 if (channel->hw_value == CHANNEL_G)
fa1c114f
JS		 699 ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */
700 else
701 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));
702
703 ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */
704 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
705 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
706 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
707 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
708 }
709
710 /* Fix for first revision of the RF5112 RF chipset */
711 if (ah->ah_radio >= AR5K_RF5112 &&
712 ah->ah_radio_5ghz_revision <
713 AR5K_SREV_RAD_5112A) {
714 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
715 AR5K_PHY_CCKTXCTL);
d8ee398d 716 if (channel->hw_value & CHANNEL_5GHZ)
fa1c114f
JS		 717 data = 0xffb81020;
718 else
719 data = 0xffb80d20;
720 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
721 }
722
723 /*
724 * Set TX power (FIXME)
725 */
726 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
727 if (ret)
728 return ret;
729
132127e5
LR		 730 /* Write rate duration table only on AR5212 and if
731 * virtual interface has already been brought up
732 * XXX: rethink this after new mode changes to
733 * mac80211 are integrated */
734 if (ah->ah_version == AR5K_AR5212 &&
735 ah->ah_sc->vif != NULL)
d8ee398d 736 ath5k_hw_write_rate_duration(ah, mode);
fa1c114f
JS		 737
738 /*
739 * Write RF registers
740 * TODO:Does this work on 5211 (5111) ?
741 */
742 ret = ath5k_hw_rfregs(ah, channel, mode);
743 if (ret)
744 return ret;
745
746 /*
747 * Configure additional registers
748 */
749
750 /* Write OFDM timings on 5212*/
751 if (ah->ah_version == AR5K_AR5212 &&
d8ee398d 752 channel->hw_value & CHANNEL_OFDM) {
fa1c114f
JS		 753 ret = ath5k_hw_write_ofdm_timings(ah, channel);
754 if (ret)
755 return ret;
756 }
757
758 /*Enable/disable 802.11b mode on 5111
759 (enable 2111 frequency converter + CCK)*/
760 if (ah->ah_radio == AR5K_RF5111) {
d8ee398d 761 if (mode == AR5K_MODE_11B)
fa1c114f
JS		 762 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
763 AR5K_TXCFG_B_MODE);
764 else
765 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
766 AR5K_TXCFG_B_MODE);
767 }
768
769 /*
770 * Set channel and calibrate the PHY
771 */
772 ret = ath5k_hw_channel(ah, channel);
773 if (ret)
774 return ret;
775
776 /* Set antenna mode */
777 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
778 ah->ah_antenna[ee_mode][0], 0xfffffc06);
779
780 /*
781 * In case a fixed antenna was set as default
782 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
783 * registers.
784 */
785 if (s_ant != 0){
786 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
787 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
788 else /* 2 - Aux */
789 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
790 } else {
791 ant[0] = AR5K_ANT_FIXED_A;
792 ant[1] = AR5K_ANT_FIXED_B;
793 }
794
795 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
796 AR5K_PHY_ANT_SWITCH_TABLE_0);
797 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
798 AR5K_PHY_ANT_SWITCH_TABLE_1);
799
800 /* Commit values from EEPROM */
801 if (ah->ah_radio == AR5K_RF5111)
802 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
803 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
804
805 ath5k_hw_reg_write(ah,
806 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
807 AR5K_PHY(0x5a));
808
809 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
810 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
811 0xffffc07f);
812 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
813 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
814 0xfffc0fff);
815 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
816 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
817 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
818 0xffff0000);
819
820 ath5k_hw_reg_write(ah,
821 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
822 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
823 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
824 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
825
826 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
827 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
828 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
829 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
830 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
831
832 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
833 AR5K_PHY_IQ_CORR_ENABLE |
834 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
835 ee->ee_q_cal[ee_mode]);
836
837 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
838 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
839 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
840 ee->ee_margin_tx_rx[ee_mode]);
841
842 } else {
843 mdelay(1);
844 /* Disable phy and wait */
845 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
846 mdelay(1);
847 }
848
849 /*
850 * Restore saved values
851 */
852 /*DCU/Antenna selection not available on 5210*/
853 if (ah->ah_version != AR5K_AR5210) {
854 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
855 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
856 }
857 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
858 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
859 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
860
861 /*
862 * Misc
863 */
864 /* XXX: add ah->aid once mac80211 gives this to us */
865 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
866
867 ath5k_hw_set_opmode(ah);
868 /*PISR/SISR Not available on 5210*/
869 if (ah->ah_version != AR5K_AR5210) {
870 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
871 /* If we later allow tuning for this, store into sc structure */
872 data = AR5K_TUNE_RSSI_THRES |
873 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
874 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
875 }
876
877 /*
878 * Set Rx/Tx DMA Configuration
879 *(passing dma size not available on 5210)
880 */
881 if (ah->ah_version != AR5K_AR5210) {
882 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
883 AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
884 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
885 AR5K_DMASIZE_512B);
886 }
887
888 /*
889 * Enable the PHY and wait until completion
890 */
891 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
892
893 /*
894 * 5111/5112 Specific
895 */
896 if (ah->ah_version != AR5K_AR5210) {
897 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
898 AR5K_PHY_RX_DELAY_M;
d8ee398d 899 data = (channel->hw_value & CHANNEL_CCK) ?
fa1c114f
JS		 900 ((data << 2) / 22) : (data / 10);
901
902 udelay(100 + data);
903 } else {
904 mdelay(1);
905 }
906
907 /*
908 * Enable calibration and wait until completion
909 */
910 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
911 AR5K_PHY_AGCCTL_CAL);
912
913 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
914 AR5K_PHY_AGCCTL_CAL, 0, false)) {
915 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
d8ee398d 916 channel->center_freq);
fa1c114f
JS		 917 return -EAGAIN;
918 }
919
d8ee398d 920 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
fa1c114f
JS		 921 if (ret)
922 return ret;
923
924 ah->ah_calibration = false;
925
926 /* A and G modes can use QAM modulation which requires enabling
927 * I and Q calibration. Don't bother in B mode. */
d8ee398d 928 if (!(mode == AR5K_MODE_11B)) {
fa1c114f
JS		 929 ah->ah_calibration = true;
930 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
931 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
932 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
933 AR5K_PHY_IQ_RUN);
934 }
935
936 /*
937 * Reset queues and start beacon timers at the end of the reset routine
938 */
939 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
940 /*No QCU on 5210*/
941 if (ah->ah_version != AR5K_AR5210)
942 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
943
944 ret = ath5k_hw_reset_tx_queue(ah, i);
945 if (ret) {
946 ATH5K_ERR(ah->ah_sc,
947 "failed to reset TX queue #%d\n", i);
948 return ret;
949 }
950 }
951
952 /* Pre-enable interrupts on 5211/5212*/
953 if (ah->ah_version != AR5K_AR5210)
954 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
955 AR5K_INT_FATAL);
956
957 /*
958 * Set RF kill flags if supported by the device (read from the EEPROM)
959 * Disable gpio_intr for now since it results system hang.
960 * TODO: Handle this in ath5k_intr
961 */
962#if 0
963 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
964 ath5k_hw_set_gpio_input(ah, 0);
965 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
966 if (ah->ah_gpio[0] == 0)
967 ath5k_hw_set_gpio_intr(ah, 0, 1);
968 else
969 ath5k_hw_set_gpio_intr(ah, 0, 0);
970 }
971#endif
972
973 /*
974 * Set the 32MHz reference clock on 5212 phy clock sleep register
975 */
976 if (ah->ah_version == AR5K_AR5212) {
977 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
978 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
979 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
980 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
981 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
982 ath5k_hw_reg_write(ah, ah->ah_radio == AR5K_RF5111 ?
983 AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112,
984 AR5K_PHY_SPENDING);
985 }
986
987 /*
988 * Disable beacons and reset the register
989 */
990 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
991 AR5K_BEACON_RESET_TSF);
992
993 return 0;
994}
995
996/*
997 * Reset chipset
998 */
999static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1000{
1001 int ret;
1002 u32 mask = val ? val : ~0U;
1003
1004 ATH5K_TRACE(ah->ah_sc);
1005
1006 /* Read-and-clear RX Descriptor Pointer*/
1007 ath5k_hw_reg_read(ah, AR5K_RXDP);
1008
1009 /*
1010 * Reset the device and wait until success
1011 */
1012 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1013
1014 /* Wait at least 128 PCI clocks */
1015 udelay(15);
1016
1017 if (ah->ah_version == AR5K_AR5210) {
1018 val &= AR5K_RESET_CTL_CHIP;
1019 mask &= AR5K_RESET_CTL_CHIP;
1020 } else {
1021 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1022 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1023 }
1024
1025 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1026
1027 /*
1028 * Reset configuration register (for hw byte-swap). Note that this
1029 * is only set for big endian. We do the necessary magic in
1030 * AR5K_INIT_CFG.
1031 */
1032 if ((val & AR5K_RESET_CTL_PCU) == 0)
1033 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1034
1035 return ret;
1036}
1037
1038/*
1039 * Power management functions
1040 */
1041
1042/*
1043 * Sleep control
1044 */
1045int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1046 bool set_chip, u16 sleep_duration)
1047{
1048 unsigned int i;
1049 u32 staid;
1050
1051 ATH5K_TRACE(ah->ah_sc);
1052 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1053
1054 switch (mode) {
1055 case AR5K_PM_AUTO:
1056 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1057 /* fallthrough */
1058 case AR5K_PM_NETWORK_SLEEP:
1059 if (set_chip == true)
1060 ath5k_hw_reg_write(ah,
1061 AR5K_SLEEP_CTL_SLE | sleep_duration,
1062 AR5K_SLEEP_CTL);
1063
1064 staid |= AR5K_STA_ID1_PWR_SV;
1065 break;
1066
1067 case AR5K_PM_FULL_SLEEP:
1068 if (set_chip == true)
1069 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1070 AR5K_SLEEP_CTL);
1071
1072 staid |= AR5K_STA_ID1_PWR_SV;
1073 break;
1074
1075 case AR5K_PM_AWAKE:
1076 if (set_chip == false)
1077 goto commit;
1078
1079 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1080 AR5K_SLEEP_CTL);
1081
1082 for (i = 5000; i > 0; i--) {
1083 /* Check if the chip did wake up */
1084 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1085 AR5K_PCICFG_SPWR_DN) == 0)
1086 break;
1087
1088 /* Wait a bit and retry */
1089 udelay(200);
1090 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1091 AR5K_SLEEP_CTL);
1092 }
1093
1094 /* Fail if the chip didn't wake up */
1095 if (i <= 0)
1096 return -EIO;
1097
1098 staid &= ~AR5K_STA_ID1_PWR_SV;
1099 break;
1100
1101 default:
1102 return -EINVAL;
1103 }
1104
1105commit:
1106 ah->ah_power_mode = mode;
1107 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1108
1109 return 0;
1110}
1111
1112/***********************\
1113 DMA Related Functions
1114\***********************/
1115
1116/*
1117 * Receive functions
1118 */
1119
1120/*
1121 * Start DMA receive
1122 */
1123void ath5k_hw_start_rx(struct ath5k_hw *ah)
1124{
1125 ATH5K_TRACE(ah->ah_sc);
1126 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1127}
1128
1129/*
1130 * Stop DMA receive
1131 */
1132int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1133{
1134 unsigned int i;
1135
1136 ATH5K_TRACE(ah->ah_sc);
1137 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1138
1139 /*
1140 * It may take some time to disable the DMA receive unit
1141 */
1142 for (i = 2000; i > 0 &&
1143 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1144 i--)
1145 udelay(10);
1146
1147 return i ? 0 : -EBUSY;
1148}
1149
1150/*
1151 * Get the address of the RX Descriptor
1152 */
1153u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1154{
1155 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1156}
1157
1158/*
1159 * Set the address of the RX Descriptor
1160 */
1161void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1162{
1163 ATH5K_TRACE(ah->ah_sc);
1164
1165 /*TODO:Shouldn't we check if RX is enabled first ?*/
1166 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1167}
1168
1169/*
1170 * Transmit functions
1171 */
1172
1173/*
1174 * Start DMA transmit for a specific queue
1175 * (see also QCU/DCU functions)
1176 */
1177int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1178{
1179 u32 tx_queue;
1180
1181 ATH5K_TRACE(ah->ah_sc);
1182 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1183
1184 /* Return if queue is declared inactive */
1185 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1186 return -EIO;
1187
1188 if (ah->ah_version == AR5K_AR5210) {
1189 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1190
1191 /*
1192 * Set the queue by type on 5210
1193 */
1194 switch (ah->ah_txq[queue].tqi_type) {
1195 case AR5K_TX_QUEUE_DATA:
1196 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1197 break;
1198 case AR5K_TX_QUEUE_BEACON:
1199 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1200 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1201 AR5K_BSR);
1202 break;
1203 case AR5K_TX_QUEUE_CAB:
1204 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1205 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1206 AR5K_BCR_BDMAE, AR5K_BSR);
1207 break;
1208 default:
1209 return -EINVAL;
1210 }
1211 /* Start queue */
1212 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1213 } else {
1214 /* Return if queue is disabled */
1215 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1216 return -EIO;
1217
1218 /* Start queue */
1219 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1220 }
1221
1222 return 0;
1223}
1224
1225/*
1226 * Stop DMA transmit for a specific queue
1227 * (see also QCU/DCU functions)
1228 */
1229int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1230{
1231 unsigned int i = 100;
1232 u32 tx_queue, pending;
1233
1234 ATH5K_TRACE(ah->ah_sc);
1235 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1236
1237 /* Return if queue is declared inactive */
1238 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1239 return -EIO;
1240
1241 if (ah->ah_version == AR5K_AR5210) {
1242 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1243
1244 /*
1245 * Set by queue type
1246 */
1247 switch (ah->ah_txq[queue].tqi_type) {
1248 case AR5K_TX_QUEUE_DATA:
1249 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1250 break;
1251 case AR5K_TX_QUEUE_BEACON:
1252 case AR5K_TX_QUEUE_CAB:
1253 /* XXX Fix me... */
1254 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1255 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1256 break;
1257 default:
1258 return -EINVAL;
1259 }
1260
1261 /* Stop queue */
1262 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1263 } else {
1264 /*
1265 * Schedule TX disable and wait until queue is empty
1266 */
1267 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1268
1269 /*Check for pending frames*/
1270 do {
1271 pending = ath5k_hw_reg_read(ah,
1272 AR5K_QUEUE_STATUS(queue)) &
1273 AR5K_QCU_STS_FRMPENDCNT;
1274 udelay(100);
1275 } while (--i && pending);
1276
1277 /* Clear register */
1278 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1279 }
1280
1281 /* TODO: Check for success else return error */
1282 return 0;
1283}
1284
1285/*
1286 * Get the address of the TX Descriptor for a specific queue
1287 * (see also QCU/DCU functions)
1288 */
1289u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1290{
1291 u16 tx_reg;
1292
1293 ATH5K_TRACE(ah->ah_sc);
1294 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1295
1296 /*
1297 * Get the transmit queue descriptor pointer from the selected queue
1298 */
1299 /*5210 doesn't have QCU*/
1300 if (ah->ah_version == AR5K_AR5210) {
1301 switch (ah->ah_txq[queue].tqi_type) {
1302 case AR5K_TX_QUEUE_DATA:
1303 tx_reg = AR5K_NOQCU_TXDP0;
1304 break;
1305 case AR5K_TX_QUEUE_BEACON:
1306 case AR5K_TX_QUEUE_CAB:
1307 tx_reg = AR5K_NOQCU_TXDP1;
1308 break;
1309 default:
1310 return 0xffffffff;
1311 }
1312 } else {
1313 tx_reg = AR5K_QUEUE_TXDP(queue);
1314 }
1315
1316 return ath5k_hw_reg_read(ah, tx_reg);
1317}
1318
1319/*
1320 * Set the address of the TX Descriptor for a specific queue
1321 * (see also QCU/DCU functions)
1322 */
1323int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1324{
1325 u16 tx_reg;
1326
1327 ATH5K_TRACE(ah->ah_sc);
1328 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1329
1330 /*
1331 * Set the transmit queue descriptor pointer register by type
1332 * on 5210
1333 */
1334 if (ah->ah_version == AR5K_AR5210) {
1335 switch (ah->ah_txq[queue].tqi_type) {
1336 case AR5K_TX_QUEUE_DATA:
1337 tx_reg = AR5K_NOQCU_TXDP0;
1338 break;
1339 case AR5K_TX_QUEUE_BEACON:
1340 case AR5K_TX_QUEUE_CAB:
1341 tx_reg = AR5K_NOQCU_TXDP1;
1342 break;
1343 default:
1344 return -EINVAL;
1345 }
1346 } else {
1347 /*
1348 * Set the transmit queue descriptor pointer for
1349 * the selected queue on QCU for 5211+
1350 * (this won't work if the queue is still active)
1351 */
1352 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1353 return -EIO;
1354
1355 tx_reg = AR5K_QUEUE_TXDP(queue);
1356 }
1357
1358 /* Set descriptor pointer */
1359 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1360
1361 return 0;
1362}
1363
1364/*
1365 * Update tx trigger level
1366 */
1367int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1368{
1369 u32 trigger_level, imr;
1370 int ret = -EIO;
1371
1372 ATH5K_TRACE(ah->ah_sc);
1373
1374 /*
1375 * Disable interrupts by setting the mask
1376 */
1377 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1378
1379 /*TODO: Boundary check on trigger_level*/
1380 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1381 AR5K_TXCFG_TXFULL);
1382
1383 if (increase == false) {
1384 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1385 goto done;
1386 } else
1387 trigger_level +=
1388 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1389
1390 /*
1391 * Update trigger level on success
1392 */
1393 if (ah->ah_version == AR5K_AR5210)
1394 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1395 else
1396 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1397 AR5K_TXCFG_TXFULL, trigger_level);
1398
1399 ret = 0;
1400
1401done:
1402 /*
1403 * Restore interrupt mask
1404 */
1405 ath5k_hw_set_intr(ah, imr);
1406
1407 return ret;
1408}
1409
1410/*
1411 * Interrupt handling
1412 */
1413
1414/*
1415 * Check if we have pending interrupts
1416 */
1417bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1418{
1419 ATH5K_TRACE(ah->ah_sc);
1420 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1421}
1422
1423/*
1424 * Get interrupt mask (ISR)
1425 */
1426int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1427{
1428 u32 data;
1429
1430 ATH5K_TRACE(ah->ah_sc);
1431
1432 /*
1433 * Read interrupt status from the Interrupt Status register
1434 * on 5210
1435 */
1436 if (ah->ah_version == AR5K_AR5210) {
1437 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1438 if (unlikely(data == AR5K_INT_NOCARD)) {
1439 *interrupt_mask = data;
1440 return -ENODEV;
1441 }
1442 } else {
1443 /*
1444 * Read interrupt status from the Read-And-Clear shadow register
1445 * Note: PISR/SISR Not available on 5210
1446 */
1447 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1448 }
1449
1450 /*
1451 * Get abstract interrupt mask (driver-compatible)
1452 */
1453 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1454
1455 if (unlikely(data == AR5K_INT_NOCARD))
1456 return -ENODEV;
1457
1458 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1459 *interrupt_mask |= AR5K_INT_RX;
1460
1461 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1462 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1463 *interrupt_mask |= AR5K_INT_TX;
1464
1465 if (ah->ah_version != AR5K_AR5210) {
1466 /*HIU = Host Interface Unit (PCI etc)*/
1467 if (unlikely(data & (AR5K_ISR_HIUERR)))
1468 *interrupt_mask |= AR5K_INT_FATAL;
1469
1470 /*Beacon Not Ready*/
1471 if (unlikely(data & (AR5K_ISR_BNR)))
1472 *interrupt_mask |= AR5K_INT_BNR;
1473 }
1474
1475 /*
1476 * XXX: BMISS interrupts may occur after association.
1477 * I found this on 5210 code but it needs testing. If this is
1478 * true we should disable them before assoc and re-enable them
1479 * after a successfull assoc + some jiffies.
1480 */
1481#if 0
1482 interrupt_mask &= ~AR5K_INT_BMISS;
1483#endif
1484
1485 /*
1486 * In case we didn't handle anything,
1487 * print the register value.
1488 */
1489 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1490 ATH5K_PRINTF("0x%08x\n", data);
1491
1492 return 0;
1493}
1494
1495/*
1496 * Set interrupt mask
1497 */
1498enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1499{
1500 enum ath5k_int old_mask, int_mask;
1501
1502 /*
1503 * Disable card interrupts to prevent any race conditions
1504 * (they will be re-enabled afterwards).
1505 */
1506 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1507
1508 old_mask = ah->ah_imr;
1509
1510 /*
1511 * Add additional, chipset-dependent interrupt mask flags
1512 * and write them to the IMR (interrupt mask register).
1513 */
1514 int_mask = new_mask & AR5K_INT_COMMON;
1515
1516 if (new_mask & AR5K_INT_RX)
1517 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1518 AR5K_IMR_RXDESC;
1519
1520 if (new_mask & AR5K_INT_TX)
1521 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1522 AR5K_IMR_TXURN;
1523
1524 if (ah->ah_version != AR5K_AR5210) {
1525 if (new_mask & AR5K_INT_FATAL) {
1526 int_mask |= AR5K_IMR_HIUERR;
1527 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1528 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1529 }
1530 }
1531
1532 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1533
1534 /* Store new interrupt mask */
1535 ah->ah_imr = new_mask;
1536
1537 /* ..re-enable interrupts */
1538 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1539
1540 return old_mask;
1541}
1542
1543
1544/*************************\
1545 EEPROM access functions
1546\*************************/
1547
1548/*
1549 * Read from eeprom
1550 */
1551static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1552{
1553 u32 status, timeout;
1554
1555 ATH5K_TRACE(ah->ah_sc);
1556 /*
1557 * Initialize EEPROM access
1558 */
1559 if (ah->ah_version == AR5K_AR5210) {
1560 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1561 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1562 } else {
1563 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1564 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1565 AR5K_EEPROM_CMD_READ);
1566 }
1567
1568 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1569 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1570 if (status & AR5K_EEPROM_STAT_RDDONE) {
1571 if (status & AR5K_EEPROM_STAT_RDERR)
1572 return -EIO;
1573 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1574 0xffff);
1575 return 0;
1576 }
1577 udelay(15);
1578 }
1579
1580 return -ETIMEDOUT;
1581}
1582
1583/*
1584 * Write to eeprom - currently disabled, use at your own risk
1585 */
d8ee398d 1586#if 0
fa1c114f
JS		 1587static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1588{
d8ee398d 1589
fa1c114f
JS		 1590 u32 status, timeout;
1591
1592 ATH5K_TRACE(ah->ah_sc);
1593
1594 /*
1595 * Initialize eeprom access
1596 */
1597
1598 if (ah->ah_version == AR5K_AR5210) {
1599 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1600 } else {
1601 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1602 AR5K_EEPROM_CMD_RESET);
1603 }
1604
1605 /*
1606 * Write data to data register
1607 */
1608
1609 if (ah->ah_version == AR5K_AR5210) {
1610 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1611 } else {
1612 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1613 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1614 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1615 AR5K_EEPROM_CMD_WRITE);
1616 }
1617
1618 /*
1619 * Check status
1620 */
1621
1622 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1623 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1624 if (status & AR5K_EEPROM_STAT_WRDONE) {
1625 if (status & AR5K_EEPROM_STAT_WRERR)
1626 return EIO;
1627 return 0;
1628 }
1629 udelay(15);
1630 }
d8ee398d 1631
fa1c114f
JS		 1632 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1633 return -EIO;
1634}
d8ee398d 1635#endif
fa1c114f
JS		 1636
1637/*
1638 * Translate binary channel representation in EEPROM to frequency
1639 */
1640static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1641{
1642 u16 val;
1643
1644 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1645 return bin;
1646
1647 if (mode == AR5K_EEPROM_MODE_11A) {
1648 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1649 val = (5 * bin) + 4800;
1650 else
1651 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1652 (bin * 10) + 5100;
1653 } else {
1654 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1655 val = bin + 2300;
1656 else
1657 val = bin + 2400;
1658 }
1659
1660 return val;
1661}
1662
1663/*
1664 * Read antenna infos from eeprom
1665 */
1666static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1667 unsigned int mode)
1668{
1669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1670 u32 o = *offset;
1671 u16 val;
1672 int ret, i = 0;
1673
1674 AR5K_EEPROM_READ(o++, val);
1675 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1676 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1677 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1678
1679 AR5K_EEPROM_READ(o++, val);
1680 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1681 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1682 ee->ee_ant_control[mode][i++] = val & 0x3f;
1683
1684 AR5K_EEPROM_READ(o++, val);
1685 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1686 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1687 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1688
1689 AR5K_EEPROM_READ(o++, val);
1690 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1691 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1692 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1693 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1694
1695 AR5K_EEPROM_READ(o++, val);
1696 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1697 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1698 ee->ee_ant_control[mode][i++] = val & 0x3f;
1699
1700 /* Get antenna modes */
1701 ah->ah_antenna[mode][0] =
1702 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1703 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1704 ee->ee_ant_control[mode][1] |
1705 (ee->ee_ant_control[mode][2] << 6) |
1706 (ee->ee_ant_control[mode][3] << 12) |
1707 (ee->ee_ant_control[mode][4] << 18) |
1708 (ee->ee_ant_control[mode][5] << 24);
1709 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1710 ee->ee_ant_control[mode][6] |
1711 (ee->ee_ant_control[mode][7] << 6) |
1712 (ee->ee_ant_control[mode][8] << 12) |
1713 (ee->ee_ant_control[mode][9] << 18) |
1714 (ee->ee_ant_control[mode][10] << 24);
1715
1716 /* return new offset */
1717 *offset = o;
1718
1719 return 0;
1720}
1721
1722/*
1723 * Read supported modes from eeprom
1724 */
1725static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1726 unsigned int mode)
1727{
1728 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1729 u32 o = *offset;
1730 u16 val;
1731 int ret;
1732
1733 AR5K_EEPROM_READ(o++, val);
1734 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1735 ee->ee_thr_62[mode] = val & 0xff;
1736
1737 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1738 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1739
1740 AR5K_EEPROM_READ(o++, val);
1741 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1742 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1743
1744 AR5K_EEPROM_READ(o++, val);
1745 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1746
1747 if ((val & 0xff) & 0x80)
1748 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1749 else
1750 ee->ee_noise_floor_thr[mode] = val & 0xff;
1751
1752 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1753 ee->ee_noise_floor_thr[mode] =
1754 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1755
1756 AR5K_EEPROM_READ(o++, val);
1757 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1758 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1759 ee->ee_xpd[mode] = val & 0x1;
1760
1761 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1762 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1763
1764 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1765 AR5K_EEPROM_READ(o++, val);
1766 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1767
1768 if (mode == AR5K_EEPROM_MODE_11A)
1769 ee->ee_xr_power[mode] = val & 0x3f;
1770 else {
1771 ee->ee_ob[mode][0] = val & 0x7;
1772 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1773 }
1774 }
1775
1776 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1777 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1778 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1779 } else {
1780 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1781
1782 AR5K_EEPROM_READ(o++, val);
1783 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1784
1785 if (mode == AR5K_EEPROM_MODE_11G)
1786 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1787 }
1788
1789 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1790 mode == AR5K_EEPROM_MODE_11A) {
1791 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1792 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1793 }
1794
1795 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1796 mode == AR5K_EEPROM_MODE_11G)
1797 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1798
1799 /* return new offset */
1800 *offset = o;
1801
1802 return 0;
1803}
1804
1805/*
1806 * Initialize eeprom & capabilities structs
1807 */
1808static int ath5k_eeprom_init(struct ath5k_hw *ah)
1809{
1810 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1811 unsigned int mode, i;
1812 int ret;
1813 u32 offset;
1814 u16 val;
1815
1816 /* Initial TX thermal adjustment values */
1817 ee->ee_tx_clip = 4;
1818 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1819 ee->ee_gain_select = 1;
1820
1821 /*
1822 * Read values from EEPROM and store them in the capability structure
1823 */
1824 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1825 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1826 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1827 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1828 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1829
1830 /* Return if we have an old EEPROM */
1831 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
1832 return 0;
1833
1834#ifdef notyet
1835 /*
1836 * Validate the checksum of the EEPROM date. There are some
1837 * devices with invalid EEPROMs.
1838 */
1839 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
1840 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
1841 cksum ^= val;
1842 }
1843 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
1844 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
1845 return -EIO;
1846 }
1847#endif
1848
1849 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
1850 ee_ant_gain);
1851
1852 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1853 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
1854 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
1855 }
1856
1857 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
1858 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
1859 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
1860 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
1861
1862 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
1863 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
1864 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
1865 }
1866
1867 /*
1868 * Get conformance test limit values
1869 */
1870 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
1871 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
1872
1873 for (i = 0; i < ee->ee_ctls; i++) {
1874 AR5K_EEPROM_READ(offset++, val);
1875 ee->ee_ctl[i] = (val >> 8) & 0xff;
1876 ee->ee_ctl[i + 1] = val & 0xff;
1877 }
1878
1879 /*
1880 * Get values for 802.11a (5GHz)
1881 */
1882 mode = AR5K_EEPROM_MODE_11A;
1883
1884 ee->ee_turbo_max_power[mode] =
1885 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
1886
1887 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
1888
1889 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1890 if (ret)
1891 return ret;
1892
1893 AR5K_EEPROM_READ(offset++, val);
1894 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1895 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
1896 ee->ee_db[mode][3] = (val >> 2) & 0x7;
1897 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1898
1899 AR5K_EEPROM_READ(offset++, val);
1900 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
1901 ee->ee_db[mode][2] = (val >> 12) & 0x7;
1902 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
1903 ee->ee_db[mode][1] = (val >> 6) & 0x7;
1904 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
1905 ee->ee_db[mode][0] = val & 0x7;
1906
1907 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1908 if (ret)
1909 return ret;
1910
1911 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
1912 AR5K_EEPROM_READ(offset++, val);
1913 ee->ee_margin_tx_rx[mode] = val & 0x3f;
1914 }
1915
1916 /*
1917 * Get values for 802.11b (2.4GHz)
1918 */
1919 mode = AR5K_EEPROM_MODE_11B;
1920 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
1921
1922 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1923 if (ret)
1924 return ret;
1925
1926 AR5K_EEPROM_READ(offset++, val);
1927 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1928 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1929 ee->ee_db[mode][1] = val & 0x7;
1930
1931 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1932 if (ret)
1933 return ret;
1934
1935 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1936 AR5K_EEPROM_READ(offset++, val);
1937 ee->ee_cal_pier[mode][0] =
1938 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1939 ee->ee_cal_pier[mode][1] =
1940 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1941
1942 AR5K_EEPROM_READ(offset++, val);
1943 ee->ee_cal_pier[mode][2] =
1944 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1945 }
1946
1947 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1948 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1949
1950 /*
1951 * Get values for 802.11g (2.4GHz)
1952 */
1953 mode = AR5K_EEPROM_MODE_11G;
1954 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
1955
1956 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1957 if (ret)
1958 return ret;
1959
1960 AR5K_EEPROM_READ(offset++, val);
1961 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1962 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1963 ee->ee_db[mode][1] = val & 0x7;
1964
1965 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1966 if (ret)
1967 return ret;
1968
1969 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1970 AR5K_EEPROM_READ(offset++, val);
1971 ee->ee_cal_pier[mode][0] =
1972 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1973 ee->ee_cal_pier[mode][1] =
1974 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1975
1976 AR5K_EEPROM_READ(offset++, val);
1977 ee->ee_turbo_max_power[mode] = val & 0x7f;
1978 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
1979
1980 AR5K_EEPROM_READ(offset++, val);
1981 ee->ee_cal_pier[mode][2] =
1982 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1983
1984 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1985 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1986
1987 AR5K_EEPROM_READ(offset++, val);
1988 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1989 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1990
1991 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
1992 AR5K_EEPROM_READ(offset++, val);
1993 ee->ee_cck_ofdm_gain_delta = val & 0xff;
1994 }
1995 }
1996
1997 /*
1998 * Read 5GHz EEPROM channels
1999 */
2000
2001 return 0;
2002}
2003
2004/*
2005 * Read the MAC address from eeprom
2006 */
2007static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2008{
2009 u8 mac_d[ETH_ALEN];
2010 u32 total, offset;
2011 u16 data;
2012 int octet, ret;
2013
2014 memset(mac, 0, ETH_ALEN);
2015 memset(mac_d, 0, ETH_ALEN);
2016
2017 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2018 if (ret)
2019 return ret;
2020
2021 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2022 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2023 if (ret)
2024 return ret;
2025
2026 total += data;
2027 mac_d[octet + 1] = data & 0xff;
2028 mac_d[octet] = data >> 8;
2029 octet += 2;
2030 }
2031
2032 memcpy(mac, mac_d, ETH_ALEN);
2033
2034 if (!total || total == 3 * 0xffff)
2035 return -EINVAL;
2036
2037 return 0;
2038}
2039
fa1c114f
JS		 2040/*
2041 * Fill the capabilities struct
2042 */
2043static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2044{
2045 u16 ee_header;
2046
2047 ATH5K_TRACE(ah->ah_sc);
2048 /* Capabilities stored in the EEPROM */
2049 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2050
2051 if (ah->ah_version == AR5K_AR5210) {
2052 /*
2053 * Set radio capabilities
2054 * (The AR5110 only supports the middle 5GHz band)
2055 */
2056 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2057 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2058 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2059 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2060
2061 /* Set supported modes */
d8ee398d
LR		 2062 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2063 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
fa1c114f
JS		 2064 } else {
2065 /*
2066 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2067 * XXX and from 2312 to 2732GHz. There are problems with the
2068 * XXX current ieee80211 implementation because the IEEE
2069 * XXX channel mapping does not support negative channel
2070 * XXX numbers (2312MHz is channel -19). Of course, this
2071 * XXX doesn't matter because these channels are out of range
2072 * XXX but some regulation domains like MKK (Japan) will
2073 * XXX support frequencies somewhere around 4.8GHz.
2074 */
2075
2076 /*
2077 * Set radio capabilities
2078 */
2079
2080 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2081 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2082 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2083
2084 /* Set supported modes */
d8ee398d 2085 __set_bit(AR5K_MODE_11A,
fa1c114f 2086 ah->ah_capabilities.cap_mode);
d8ee398d 2087 __set_bit(AR5K_MODE_11A_TURBO,
fa1c114f
JS		 2088 ah->ah_capabilities.cap_mode);
2089 if (ah->ah_version == AR5K_AR5212)
d8ee398d 2090 __set_bit(AR5K_MODE_11G_TURBO,
fa1c114f
JS		 2091 ah->ah_capabilities.cap_mode);
2092 }
2093
2094 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2095 * connected */
2096 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2097 AR5K_EEPROM_HDR_11G(ee_header)) {
2098 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2099 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2100
2101 if (AR5K_EEPROM_HDR_11B(ee_header))
d8ee398d 2102 __set_bit(AR5K_MODE_11B,
fa1c114f
JS		 2103 ah->ah_capabilities.cap_mode);
2104
2105 if (AR5K_EEPROM_HDR_11G(ee_header))
d8ee398d 2106 __set_bit(AR5K_MODE_11G,
fa1c114f
JS		 2107 ah->ah_capabilities.cap_mode);
2108 }
2109 }
2110
2111 /* GPIO */
2112 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2113
2114 /* Set number of supported TX queues */
2115 if (ah->ah_version == AR5K_AR5210)
2116 ah->ah_capabilities.cap_queues.q_tx_num =
2117 AR5K_NUM_TX_QUEUES_NOQCU;
2118 else
2119 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2120
2121 return 0;
2122}
2123
2124/*********************************\
2125 Protocol Control Unit Functions
2126\*********************************/
2127
2128/*
2129 * Set Operation mode
2130 */
2131int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2132{
2133 u32 pcu_reg, beacon_reg, low_id, high_id;
2134
2135 pcu_reg = 0;
2136 beacon_reg = 0;
2137
2138 ATH5K_TRACE(ah->ah_sc);
2139
2140 switch (ah->ah_op_mode) {
2141 case IEEE80211_IF_TYPE_IBSS:
2142 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2143 (ah->ah_version == AR5K_AR5210 ?
2144 AR5K_STA_ID1_NO_PSPOLL : 0);
2145 beacon_reg |= AR5K_BCR_ADHOC;
2146 break;
2147
2148 case IEEE80211_IF_TYPE_AP:
2149 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2150 (ah->ah_version == AR5K_AR5210 ?
2151 AR5K_STA_ID1_NO_PSPOLL : 0);
2152 beacon_reg |= AR5K_BCR_AP;
2153 break;
2154
2155 case IEEE80211_IF_TYPE_STA:
2156 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2157 (ah->ah_version == AR5K_AR5210 ?
2158 AR5K_STA_ID1_PWR_SV : 0);
2159 case IEEE80211_IF_TYPE_MNTR:
2160 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2161 (ah->ah_version == AR5K_AR5210 ?
2162 AR5K_STA_ID1_NO_PSPOLL : 0);
2163 break;
2164
2165 default:
2166 return -EINVAL;
2167 }
2168
2169 /*
2170 * Set PCU registers
2171 */
2172 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2173 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2174 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2175 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2176
2177 /*
2178 * Set Beacon Control Register on 5210
2179 */
2180 if (ah->ah_version == AR5K_AR5210)
2181 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2182
2183 return 0;
2184}
2185
2186/*
2187 * BSSID Functions
2188 */
2189
2190/*
2191 * Get station id
2192 */
2193void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2194{
2195 ATH5K_TRACE(ah->ah_sc);
2196 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2197}
2198
2199/*
2200 * Set station id
2201 */
2202int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2203{
2204 u32 low_id, high_id;
2205
2206 ATH5K_TRACE(ah->ah_sc);
2207 /* Set new station ID */
2208 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2209
2210 low_id = AR5K_LOW_ID(mac);
2211 high_id = AR5K_HIGH_ID(mac);
2212
2213 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2214 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2215
2216 return 0;
2217}
2218
2219/*
2220 * Set BSSID
2221 */
2222void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2223{
2224 u32 low_id, high_id;
2225 u16 tim_offset = 0;
2226
2227 /*
2228 * Set simple BSSID mask on 5212
2229 */
2230 if (ah->ah_version == AR5K_AR5212) {
2231 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0);
2232 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1);
2233 }
2234
2235 /*
2236 * Set BSSID which triggers the "SME Join" operation
2237 */
2238 low_id = AR5K_LOW_ID(bssid);
2239 high_id = AR5K_HIGH_ID(bssid);
2240 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2241 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2242 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2243
2244 if (assoc_id == 0) {
2245 ath5k_hw_disable_pspoll(ah);
2246 return;
2247 }
2248
2249 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2250 tim_offset ? tim_offset + 4 : 0);
2251
2252 ath5k_hw_enable_pspoll(ah, NULL, 0);
2253}
2254/**
2255 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2256 *
2257 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2258 * which bits of the interface's MAC address should be looked at when trying
2259 * to decide which packets to ACK. In station mode every bit matters. In AP
2260 * mode with a single BSS every bit matters as well. In AP mode with
2261 * multiple BSSes not every bit matters.
2262 *
2263 * @ah: the &struct ath5k_hw
2264 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2265 *
2266 * Note that this is a simple filter and *does* not filter out all
2267 * relevant frames. Some non-relevant frames will get through, probability
2268 * jocks are welcomed to compute.
2269 *
2270 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2271 * computing the set of:
2272 *
2273 * ~ ( MAC XOR BSSID )
2274 *
2275 * When you do this you are essentially computing the common bits. Later it
2276 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2277 * to obtain the relevant bits which should match on the destination frame.
2278 *
2279 * Simple example: on your card you have have two BSSes you have created with
2280 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2281 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2282 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2283 *
2284 * \
2285 * MAC: 0001 |
2286 * BSSID-01: 0100 | --> Belongs to us
2287 * BSSID-02: 1001 |
2288 * /
2289 * -------------------
2290 * BSSID-03: 0110 | --> External
2291 * -------------------
2292 *
2293 * Our bssid_mask would then be:
2294 *
2295 * On loop iteration for BSSID-01:
2296 * ~(0001 ^ 0100) -> ~(0101)
2297 * -> 1010
2298 * bssid_mask = 1010
2299 *
2300 * On loop iteration for BSSID-02:
2301 * bssid_mask &= ~(0001 ^ 1001)
2302 * bssid_mask = (1010) & ~(0001 ^ 1001)
2303 * bssid_mask = (1010) & ~(1001)
2304 * bssid_mask = (1010) & (0110)
2305 * bssid_mask = 0010
2306 *
2307 * A bssid_mask of 0010 means "only pay attention to the second least
2308 * significant bit". This is because its the only bit common
2309 * amongst the MAC and all BSSIDs we support. To findout what the real
2310 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2311 * or our MAC address (we assume the hardware uses the MAC address).
2312 *
2313 * Now, suppose there's an incoming frame for BSSID-03:
2314 *
2315 * IFRAME-01: 0110
2316 *
2317 * An easy eye-inspeciton of this already should tell you that this frame
2318 * will not pass our check. This is beacuse the bssid_mask tells the
2319 * hardware to only look at the second least significant bit and the
2320 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2321 * as 1, which does not match 0.
2322 *
2323 * So with IFRAME-01 we *assume* the hardware will do:
2324 *
2325 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2326 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2327 * --> allow = (0010) == 0000 ? 1 : 0;
2328 * --> allow = 0
2329 *
2330 * Lets now test a frame that should work:
2331 *
2332 * IFRAME-02: 0001 (we should allow)
2333 *
2334 * allow = (0001 & 1010) == 1010
2335 *
2336 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2337 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2338 * --> allow = (0010) == (0010)
2339 * --> allow = 1
2340 *
2341 * Other examples:
2342 *
2343 * IFRAME-03: 0100 --> allowed
2344 * IFRAME-04: 1001 --> allowed
2345 * IFRAME-05: 1101 --> allowed but its not for us!!!
2346 *
2347 */
2348int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2349{
2350 u32 low_id, high_id;
2351 ATH5K_TRACE(ah->ah_sc);
2352
2353 if (ah->ah_version == AR5K_AR5212) {
2354 low_id = AR5K_LOW_ID(mask);
2355 high_id = AR5K_HIGH_ID(mask);
2356
2357 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2358 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2359
2360 return 0;
2361 }
2362
2363 return -EIO;
2364}
2365
2366/*
2367 * Receive start/stop functions
2368 */
2369
2370/*
2371 * Start receive on PCU
2372 */
2373void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2374{
2375 ATH5K_TRACE(ah->ah_sc);
2376 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2377}
2378
2379/*
2380 * Stop receive on PCU
2381 */
2382void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2383{
2384 ATH5K_TRACE(ah->ah_sc);
2385 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2386}
2387
2388/*
2389 * RX Filter functions
2390 */
2391
2392/*
2393 * Set multicast filter
2394 */
2395void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2396{
2397 ATH5K_TRACE(ah->ah_sc);
2398 /* Set the multicat filter */
2399 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2400 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2401}
2402
2403/*
2404 * Set multicast filter by index
2405 */
2406int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2407{
2408
2409 ATH5K_TRACE(ah->ah_sc);
2410 if (index >= 64)
2411 return -EINVAL;
2412 else if (index >= 32)
2413 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2414 (1 << (index - 32)));
2415 else
2416 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2417
2418 return 0;
2419}
2420
2421/*
2422 * Clear Multicast filter by index
2423 */
2424int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2425{
2426
2427 ATH5K_TRACE(ah->ah_sc);
2428 if (index >= 64)
2429 return -EINVAL;
2430 else if (index >= 32)
2431 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2432 (1 << (index - 32)));
2433 else
2434 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2435
2436 return 0;
2437}
2438
2439/*
2440 * Get current rx filter
2441 */
2442u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2443{
2444 u32 data, filter = 0;
2445
2446 ATH5K_TRACE(ah->ah_sc);
2447 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2448
2449 /*Radar detection for 5212*/
2450 if (ah->ah_version == AR5K_AR5212) {
2451 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2452
2453 if (data & AR5K_PHY_ERR_FIL_RADAR)
2454 filter |= AR5K_RX_FILTER_RADARERR;
2455 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2456 filter |= AR5K_RX_FILTER_PHYERR;
2457 }
2458
2459 return filter;
2460}
2461
2462/*
2463 * Set rx filter
2464 */
2465void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2466{
2467 u32 data = 0;
2468
2469 ATH5K_TRACE(ah->ah_sc);
2470
2471 /* Set PHY error filter register on 5212*/
2472 if (ah->ah_version == AR5K_AR5212) {
2473 if (filter & AR5K_RX_FILTER_RADARERR)
2474 data |= AR5K_PHY_ERR_FIL_RADAR;
2475 if (filter & AR5K_RX_FILTER_PHYERR)
2476 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2477 }
2478
2479 /*
2480 * The AR5210 uses promiscous mode to detect radar activity
2481 */
2482 if (ah->ah_version == AR5K_AR5210 &&
2483 (filter & AR5K_RX_FILTER_RADARERR)) {
2484 filter &= ~AR5K_RX_FILTER_RADARERR;
2485 filter |= AR5K_RX_FILTER_PROM;
2486 }
2487
2488 /*Zero length DMA*/
2489 if (data)
2490 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2491 else
2492 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2493
2494 /*Write RX Filter register*/
2495 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2496
2497 /*Write PHY error filter register on 5212*/
2498 if (ah->ah_version == AR5K_AR5212)
2499 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2500
2501}
2502
2503/*
2504 * Beacon related functions
2505 */
2506
2507/*
2508 * Get a 32bit TSF
2509 */
2510u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2511{
2512 ATH5K_TRACE(ah->ah_sc);
2513 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2514}
2515
2516/*
2517 * Get the full 64bit TSF
2518 */
2519u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2520{
2521 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2522 ATH5K_TRACE(ah->ah_sc);
2523
2524 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2525}
2526
2527/*
2528 * Force a TSF reset
2529 */
2530void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2531{
2532 ATH5K_TRACE(ah->ah_sc);
2533 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2534}
2535
2536/*
2537 * Initialize beacon timers
2538 */
2539void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2540{
2541 u32 timer1, timer2, timer3;
2542
2543 ATH5K_TRACE(ah->ah_sc);
2544 /*
2545 * Set the additional timers by mode
2546 */
2547 switch (ah->ah_op_mode) {
2548 case IEEE80211_IF_TYPE_STA:
2549 if (ah->ah_version == AR5K_AR5210) {
2550 timer1 = 0xffffffff;
2551 timer2 = 0xffffffff;
2552 } else {
2553 timer1 = 0x0000ffff;
2554 timer2 = 0x0007ffff;
2555 }
2556 break;
2557
2558 default:
1008e0f7
BR		 2559 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2560 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
fa1c114f
JS		 2561 }
2562
2563 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2564
2565 /*
2566 * Set the beacon register and enable all timers.
2567 * (next beacon, DMA beacon, software beacon, ATIM window time)
2568 */
2569 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2570 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2571 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2572 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2573
2574 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2575 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2576 AR5K_BEACON);
2577}
2578
2579#if 0
2580/*
2581 * Set beacon timers
2582 */
2583int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2584 const struct ath5k_beacon_state *state)
2585{
2586 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2587
2588 /*
2589 * TODO: should be changed through *state
2590 * review struct ath5k_beacon_state struct
2591 *
2592 * XXX: These are used for cfp period bellow, are they
2593 * ok ? Is it O.K. for tsf here to be 0 or should we use
2594 * get_tsf ?
2595 */
2596 u32 dtim_count = 0; /* XXX */
2597 u32 cfp_count = 0; /* XXX */
2598 u32 tsf = 0; /* XXX */
2599
2600 ATH5K_TRACE(ah->ah_sc);
2601 /* Return on an invalid beacon state */
2602 if (state->bs_interval < 1)
2603 return -EINVAL;
2604
2605 interval = state->bs_interval;
2606 dtim = state->bs_dtim_period;
2607
2608 /*
2609 * PCF support?
2610 */
2611 if (state->bs_cfp_period > 0) {
2612 /*
2613 * Enable PCF mode and set the CFP
2614 * (Contention Free Period) and timer registers
2615 */
2616 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2617 state->bs_interval;
2618 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2619 state->bs_interval;
2620
2621 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2622 AR5K_STA_ID1_DEFAULT_ANTENNA |
2623 AR5K_STA_ID1_PCF);
2624 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2625 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2626 AR5K_CFP_DUR);
2627 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2628 next_cfp)) << 3, AR5K_TIMER2);
2629 } else {
2630 /* Disable PCF mode */
2631 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2632 AR5K_STA_ID1_DEFAULT_ANTENNA |
2633 AR5K_STA_ID1_PCF);
2634 }
2635
2636 /*
2637 * Enable the beacon timer register
2638 */
2639 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2640
2641 /*
2642 * Start the beacon timers
2643 */
2644 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2645 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2646 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2647 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2648 AR5K_BEACON_PERIOD), AR5K_BEACON);
2649
2650 /*
2651 * Write new beacon miss threshold, if it appears to be valid
2652 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2653 * and return if its not in range. We can test this by reading value and
2654 * setting value to a largest value and seeing which values register.
2655 */
2656
2657 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2658 state->bs_bmiss_threshold);
2659
2660 /*
2661 * Set sleep control register
2662 * XXX: Didn't find this in 5210 code but since this register
2663 * exists also in ar5k's 5210 headers i leave it as common code.
2664 */
2665 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2666 (state->bs_sleep_duration - 3) << 3);
2667
2668 /*
2669 * Set enhanced sleep registers on 5212
2670 */
2671 if (ah->ah_version == AR5K_AR5212) {
2672 if (state->bs_sleep_duration > state->bs_interval &&
2673 roundup(state->bs_sleep_duration, interval) ==
2674 state->bs_sleep_duration)
2675 interval = state->bs_sleep_duration;
2676
2677 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2678 roundup(state->bs_sleep_duration, dtim) ==
2679 state->bs_sleep_duration))
2680 dtim = state->bs_sleep_duration;
2681
2682 if (interval > dtim)
2683 return -EINVAL;
2684
2685 next_beacon = interval == dtim ? state->bs_next_dtim :
2686 state->bs_next_beacon;
2687
2688 ath5k_hw_reg_write(ah,
2689 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2690 AR5K_SLEEP0_NEXT_DTIM) |
2691 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2692 AR5K_SLEEP0_ENH_SLEEP_EN |
2693 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2694
2695 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2696 AR5K_SLEEP1_NEXT_TIM) |
2697 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2698
2699 ath5k_hw_reg_write(ah,
2700 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2701 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2702 }
2703
2704 return 0;
2705}
2706
2707/*
2708 * Reset beacon timers
2709 */
2710void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2711{
2712 ATH5K_TRACE(ah->ah_sc);
2713 /*
2714 * Disable beacon timer
2715 */
2716 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2717
2718 /*
2719 * Disable some beacon register values
2720 */
2721 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2722 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2723 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2724}
2725
2726/*
2727 * Wait for beacon queue to finish
2728 */
2729int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2730{
2731 unsigned int i;
2732 int ret;
2733
2734 ATH5K_TRACE(ah->ah_sc);
2735
2736 /* 5210 doesn't have QCU*/
2737 if (ah->ah_version == AR5K_AR5210) {
2738 /*
2739 * Wait for beaconn queue to finish by checking
2740 * Control Register and Beacon Status Register.
2741 */
2742 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2743 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2744 ||
2745 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2746 break;
2747 udelay(10);
2748 }
2749
2750 /* Timeout... */
2751 if (i <= 0) {
2752 /*
2753 * Re-schedule the beacon queue
2754 */
2755 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2756 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2757 AR5K_BCR);
2758
2759 return -EIO;
2760 }
2761 ret = 0;
2762 } else {
2763 /*5211/5212*/
2764 ret = ath5k_hw_register_timeout(ah,
2765 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2766 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2767
2768 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2769 return -EIO;
2770 }
2771
2772 return ret;
2773}
2774#endif
2775
2776/*
2777 * Update mib counters (statistics)
2778 */
2779void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2780 struct ath5k_mib_stats *statistics)
2781{
2782 ATH5K_TRACE(ah->ah_sc);
2783 /* Read-And-Clear */
2784 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2785 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2786 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2787 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2788 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2789
2790 /* Reset profile count registers on 5212*/
2791 if (ah->ah_version == AR5K_AR5212) {
2792 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2793 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2794 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2795 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2796 }
2797}
2798
2799/** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2800 *
2801 * @ah: the &struct ath5k_hw
2802 * @high: determines if to use low bit rate or now
2803 */
2804void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2805{
2806 if (ah->ah_version != AR5K_AR5212)
2807 return;
2808 else {
2809 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2810 if (high)
2811 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2812 else
2813 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2814 }
2815}
2816
2817
2818/*
2819 * ACK/CTS Timeouts
2820 */
2821
2822/*
2823 * Set ACK timeout on PCU
2824 */
2825int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
2826{
2827 ATH5K_TRACE(ah->ah_sc);
2828 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
2829 ah->ah_turbo) <= timeout)
2830 return -EINVAL;
2831
2832 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
2833 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2834
2835 return 0;
2836}
2837
2838/*
2839 * Read the ACK timeout from PCU
2840 */
2841unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
2842{
2843 ATH5K_TRACE(ah->ah_sc);
2844
2845 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2846 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
2847}
2848
2849/*
2850 * Set CTS timeout on PCU
2851 */
2852int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
2853{
2854 ATH5K_TRACE(ah->ah_sc);
2855 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
2856 ah->ah_turbo) <= timeout)
2857 return -EINVAL;
2858
2859 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
2860 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2861
2862 return 0;
2863}
2864
2865/*
2866 * Read CTS timeout from PCU
2867 */
2868unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
2869{
2870 ATH5K_TRACE(ah->ah_sc);
2871 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2872 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
2873}
2874
2875/*
2876 * Key table (WEP) functions
2877 */
2878
2879int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2880{
2881 unsigned int i;
2882
2883 ATH5K_TRACE(ah->ah_sc);
2884 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2885
2886 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2887 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2888
2889 /* Set NULL encryption on non-5210*/
2890 if (ah->ah_version != AR5K_AR5210)
2891 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2892 AR5K_KEYTABLE_TYPE(entry));
2893
2894 return 0;
2895}
2896
2897int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
2898{
2899 ATH5K_TRACE(ah->ah_sc);
2900 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2901
2902 /* Check the validation flag at the end of the entry */
2903 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
2904 AR5K_KEYTABLE_VALID;
2905}
2906
2907int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
2908 const struct ieee80211_key_conf *key, const u8 *mac)
2909{
2910 unsigned int i;
2911 __le32 key_v[5] = {};
2912 u32 keytype;
2913
2914 ATH5K_TRACE(ah->ah_sc);
2915
2916 /* key->keylen comes in from mac80211 in bytes */
2917
2918 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
2919 return -EOPNOTSUPP;
2920
2921 switch (key->keylen) {
2922 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
2923 case 40 / 8:
2924 memcpy(&key_v[0], key->key, 5);
2925 keytype = AR5K_KEYTABLE_TYPE_40;
2926 break;
2927
2928 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
2929 case 104 / 8:
2930 memcpy(&key_v[0], &key->key[0], 6);
2931 memcpy(&key_v[2], &key->key[6], 6);
2932 memcpy(&key_v[4], &key->key[12], 1);
2933 keytype = AR5K_KEYTABLE_TYPE_104;
2934 break;
2935 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
2936 case 128 / 8:
2937 memcpy(&key_v[0], &key->key[0], 6);
2938 memcpy(&key_v[2], &key->key[6], 6);
2939 memcpy(&key_v[4], &key->key[12], 4);
2940 keytype = AR5K_KEYTABLE_TYPE_128;
2941 break;
2942
2943 default:
2944 return -EINVAL; /* shouldn't happen */
2945 }
2946
2947 for (i = 0; i < ARRAY_SIZE(key_v); i++)
2948 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
2949 AR5K_KEYTABLE_OFF(entry, i));
2950
2951 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
2952
2953 return ath5k_hw_set_key_lladdr(ah, entry, mac);
2954}
2955
2956int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
2957{
2958 u32 low_id, high_id;
2959
2960 ATH5K_TRACE(ah->ah_sc);
2961 /* Invalid entry (key table overflow) */
2962 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2963
2964 /* MAC may be NULL if it's a broadcast key. In this case no need to
2965 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
2966 if (unlikely(mac == NULL)) {
2967 low_id = 0xffffffff;
2968 high_id = 0xffff | AR5K_KEYTABLE_VALID;
2969 } else {
2970 low_id = AR5K_LOW_ID(mac);
2971 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
2972 }
2973
2974 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
2975 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
2976
2977 return 0;
2978}
2979
2980
2981/********************************************\
2982Queue Control Unit, DFS Control Unit Functions
2983\********************************************/
2984
2985/*
2986 * Initialize a transmit queue
2987 */
2988int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
2989 struct ath5k_txq_info *queue_info)
2990{
2991 unsigned int queue;
2992 int ret;
2993
2994 ATH5K_TRACE(ah->ah_sc);
2995
2996 /*
2997 * Get queue by type
2998 */
2999 /*5210 only has 2 queues*/
3000 if (ah->ah_version == AR5K_AR5210) {
3001 switch (queue_type) {
3002 case AR5K_TX_QUEUE_DATA:
3003 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3004 break;
3005 case AR5K_TX_QUEUE_BEACON:
3006 case AR5K_TX_QUEUE_CAB:
3007 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3008 break;
3009 default:
3010 return -EINVAL;
3011 }
3012 } else {
3013 switch (queue_type) {
3014 case AR5K_TX_QUEUE_DATA:
3015 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3016 ah->ah_txq[queue].tqi_type !=
3017 AR5K_TX_QUEUE_INACTIVE; queue++) {
3018
3019 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3020 return -EINVAL;
3021 }
3022 break;
3023 case AR5K_TX_QUEUE_UAPSD:
3024 queue = AR5K_TX_QUEUE_ID_UAPSD;
3025 break;
3026 case AR5K_TX_QUEUE_BEACON:
3027 queue = AR5K_TX_QUEUE_ID_BEACON;
3028 break;
3029 case AR5K_TX_QUEUE_CAB:
3030 queue = AR5K_TX_QUEUE_ID_CAB;
3031 break;
3032 case AR5K_TX_QUEUE_XR_DATA:
3033 if (ah->ah_version != AR5K_AR5212)
3034 ATH5K_ERR(ah->ah_sc,
3035 "XR data queues only supported in"
3036 " 5212!\n");
3037 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3038 break;
3039 default:
3040 return -EINVAL;
3041 }
3042 }
3043
3044 /*
3045 * Setup internal queue structure
3046 */
3047 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3048 ah->ah_txq[queue].tqi_type = queue_type;
3049
3050 if (queue_info != NULL) {
3051 queue_info->tqi_type = queue_type;
3052 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3053 if (ret)
3054 return ret;
3055 }
3056 /*
3057 * We use ah_txq_status to hold a temp value for
3058 * the Secondary interrupt mask registers on 5211+
3059 * check out ath5k_hw_reset_tx_queue
3060 */
3061 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3062
3063 return queue;
3064}
3065
3066/*
3067 * Setup a transmit queue
3068 */
3069int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3070 const struct ath5k_txq_info *queue_info)
3071{
3072 ATH5K_TRACE(ah->ah_sc);
3073 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3074
3075 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3076 return -EIO;
3077
3078 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3079
3080 /*XXX: Is this supported on 5210 ?*/
3081 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3082 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3083 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3084 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3085 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3086
3087 return 0;
3088}
3089
3090/*
3091 * Get properties for a specific transmit queue
3092 */
3093int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3094 struct ath5k_txq_info *queue_info)
3095{
3096 ATH5K_TRACE(ah->ah_sc);
3097 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3098 return 0;
3099}
3100
3101/*
3102 * Set a transmit queue inactive
3103 */
3104void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3105{
3106 ATH5K_TRACE(ah->ah_sc);
3107 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3108 return;
3109
3110 /* This queue will be skipped in further operations */
3111 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3112 /*For SIMR setup*/
3113 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3114}
3115
3116/*
3117 * Set DFS params for a transmit queue
3118 */
3119int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3120{
3121 u32 cw_min, cw_max, retry_lg, retry_sh;
3122 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3123
3124 ATH5K_TRACE(ah->ah_sc);
3125 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3126
3127 tq = &ah->ah_txq[queue];
3128
3129 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3130 return 0;
3131
3132 if (ah->ah_version == AR5K_AR5210) {
3133 /* Only handle data queues, others will be ignored */
3134 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3135 return 0;
3136
3137 /* Set Slot time */
3138 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3139 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3140 AR5K_SLOT_TIME);
3141 /* Set ACK_CTS timeout */
3142 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3143 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3144 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3145 /* Set Transmit Latency */
3146 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3147 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3148 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3149 /* Set IFS0 */
3150 if (ah->ah_turbo == true)
3151 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3152 (ah->ah_aifs + tq->tqi_aifs) *
3153 AR5K_INIT_SLOT_TIME_TURBO) <<
3154 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3155 AR5K_IFS0);
3156 else
3157 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3158 (ah->ah_aifs + tq->tqi_aifs) *
3159 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3160 AR5K_INIT_SIFS, AR5K_IFS0);
3161
3162 /* Set IFS1 */
3163 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3164 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3165 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3166 /* Set PHY register 0x9844 (??) */
3167 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3168 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3169 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3170 AR5K_PHY(17));
3171 /* Set Frame Control Register */
3172 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3173 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3174 AR5K_PHY_TURBO_SHORT | 0x2020) :
3175 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3176 AR5K_PHY_FRAME_CTL_5210);
3177 }
3178
3179 /*
3180 * Calculate cwmin/max by channel mode
3181 */
3182 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3183 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3184 ah->ah_aifs = AR5K_TUNE_AIFS;
3185 /*XR is only supported on 5212*/
3186 if (IS_CHAN_XR(ah->ah_current_channel) &&
3187 ah->ah_version == AR5K_AR5212) {
3188 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3189 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3190 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3191 /*B mode is not supported on 5210*/
3192 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3193 ah->ah_version != AR5K_AR5210) {
3194 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3195 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3196 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3197 }
3198
3199 cw_min = 1;
3200 while (cw_min < ah->ah_cw_min)
3201 cw_min = (cw_min << 1) | 1;
3202
3203 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3204 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3205 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3206 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3207
3208 /*
3209 * Calculate and set retry limits
3210 */
3211 if (ah->ah_software_retry == true) {
3212 /* XXX Need to test this */
3213 retry_lg = ah->ah_limit_tx_retries;
3214 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3215 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3216 } else {
3217 retry_lg = AR5K_INIT_LG_RETRY;
3218 retry_sh = AR5K_INIT_SH_RETRY;
3219 }
3220
3221 /*No QCU/DCU [5210]*/
3222 if (ah->ah_version == AR5K_AR5210) {
3223 ath5k_hw_reg_write(ah,
3224 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3225 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3226 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3227 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3228 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3229 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3230 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3231 AR5K_NODCU_RETRY_LMT);
3232 } else {
3233 /*QCU/DCU [5211+]*/
3234 ath5k_hw_reg_write(ah,
3235 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3236 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3237 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3238 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3239 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3240 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3241 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3242
3243 /*===Rest is also for QCU/DCU only [5211+]===*/
3244
3245 /*
3246 * Set initial content window (cw_min/cw_max)
3247 * and arbitrated interframe space (aifs)...
3248 */
3249 ath5k_hw_reg_write(ah,
3250 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3251 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3252 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3253 AR5K_DCU_LCL_IFS_AIFS),
3254 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3255
3256 /*
3257 * Set misc registers
3258 */
3259 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3260 AR5K_QUEUE_MISC(queue));
3261
3262 if (tq->tqi_cbr_period) {
3263 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3264 AR5K_QCU_CBRCFG_INTVAL) |
3265 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3266 AR5K_QCU_CBRCFG_ORN_THRES),
3267 AR5K_QUEUE_CBRCFG(queue));
3268 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3269 AR5K_QCU_MISC_FRSHED_CBR);
3270 if (tq->tqi_cbr_overflow_limit)
3271 AR5K_REG_ENABLE_BITS(ah,
3272 AR5K_QUEUE_MISC(queue),
3273 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3274 }
3275
3276 if (tq->tqi_ready_time)
3277 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3278 AR5K_QCU_RDYTIMECFG_INTVAL) |
3279 AR5K_QCU_RDYTIMECFG_ENABLE,
3280 AR5K_QUEUE_RDYTIMECFG(queue));
3281
3282 if (tq->tqi_burst_time) {
3283 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3284 AR5K_DCU_CHAN_TIME_DUR) |
3285 AR5K_DCU_CHAN_TIME_ENABLE,
3286 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3287
3288 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3289 AR5K_REG_ENABLE_BITS(ah,
3290 AR5K_QUEUE_MISC(queue),
3291 AR5K_QCU_MISC_TXE);
3292 }
3293
3294 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3295 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3296 AR5K_QUEUE_DFS_MISC(queue));
3297
3298 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3299 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3300 AR5K_QUEUE_DFS_MISC(queue));
3301
3302 /*
3303 * Set registers by queue type
3304 */
3305 switch (tq->tqi_type) {
3306 case AR5K_TX_QUEUE_BEACON:
3307 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3308 AR5K_QCU_MISC_FRSHED_DBA_GT |
3309 AR5K_QCU_MISC_CBREXP_BCN |
3310 AR5K_QCU_MISC_BCN_ENABLE);
3311
3312 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3313 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3314 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3315 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3316 AR5K_DCU_MISC_BCN_ENABLE);
3317
3318 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3319 (AR5K_TUNE_SW_BEACON_RESP -
3320 AR5K_TUNE_DMA_BEACON_RESP) -
3321 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3322 AR5K_QCU_RDYTIMECFG_ENABLE,
3323 AR5K_QUEUE_RDYTIMECFG(queue));
3324 break;
3325
3326 case AR5K_TX_QUEUE_CAB:
3327 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3328 AR5K_QCU_MISC_FRSHED_DBA_GT |
3329 AR5K_QCU_MISC_CBREXP |
3330 AR5K_QCU_MISC_CBREXP_BCN);
3331
3332 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3333 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3334 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3335 break;
3336
3337 case AR5K_TX_QUEUE_UAPSD:
3338 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3339 AR5K_QCU_MISC_CBREXP);
3340 break;
3341
3342 case AR5K_TX_QUEUE_DATA:
3343 default:
3344 break;
3345 }
3346
3347 /*
3348 * Enable interrupts for this tx queue
3349 * in the secondary interrupt mask registers
3350 */
3351 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3352 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3353
3354 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3355 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3356
3357 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3358 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3359
3360 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3361 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3362
3363 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3364 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3365
3366
3367 /* Update secondary interrupt mask registers */
3368 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3369 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3370 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3371 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3372 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3373
3374 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3375 AR5K_SIMR0_QCU_TXOK) |
3376 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3377 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3378 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3379 AR5K_SIMR1_QCU_TXERR) |
3380 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3381 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3382 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3383 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3384 }
3385
3386 return 0;
3387}
3388
3389/*
3390 * Get number of pending frames
3391 * for a specific queue [5211+]
3392 */
3393u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3394 ATH5K_TRACE(ah->ah_sc);
3395 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3396
3397 /* Return if queue is declared inactive */
3398 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3399 return false;
3400
3401 /* XXX: How about AR5K_CFG_TXCNT ? */
3402 if (ah->ah_version == AR5K_AR5210)
3403 return false;
3404
3405 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3406}
3407
3408/*
3409 * Set slot time
3410 */
3411int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3412{
3413 ATH5K_TRACE(ah->ah_sc);
3414 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3415 return -EINVAL;
3416
3417 if (ah->ah_version == AR5K_AR5210)
3418 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3419 ah->ah_turbo), AR5K_SLOT_TIME);
3420 else
3421 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3422
3423 return 0;
3424}
3425
3426/*
3427 * Get slot time
3428 */
3429unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3430{
3431 ATH5K_TRACE(ah->ah_sc);
3432 if (ah->ah_version == AR5K_AR5210)
3433 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3434 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3435 else
3436 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3437}
3438
3439
3440/******************************\
3441 Hardware Descriptor Functions
3442\******************************/
3443
3444/*
3445 * TX Descriptor
3446 */
3447
3448/*
3449 * Initialize the 2-word tx descriptor on 5210/5211
3450 */
3451static int
3452ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3453 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3454 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3455 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3456 unsigned int rtscts_rate, unsigned int rtscts_duration)
3457{
3458 u32 frame_type;
3459 struct ath5k_hw_2w_tx_desc *tx_desc;
281c56dd 3460 unsigned int frame_len;
fa1c114f
JS		 3461
3462 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3463
3464 /*
3465 * Validate input
3466 * - Zero retries don't make sense.
3467 * - A zero rate will put the HW into a mode where it continously sends
3468 * noise on the channel, so it is important to avoid this.
3469 */
3470 if (unlikely(tx_tries0 == 0)) {
3471 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3472 WARN_ON(1);
3473 return -EINVAL;
3474 }
3475 if (unlikely(tx_rate0 == 0)) {
3476 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3477 WARN_ON(1);
3478 return -EINVAL;
3479 }
3480
3481 /* Clear status descriptor */
3482 memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status));
3483
3484 /* Initialize control descriptor */
3485 tx_desc->tx_control_0 = 0;
3486 tx_desc->tx_control_1 = 0;
3487
3488 /* Setup control descriptor */
3489
3490 /* Verify and set frame length */
281c56dd
BR		 3491
3492 /* remove padding we might have added before */
3493 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3494
3495 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
fa1c114f
JS		 3496 return -EINVAL;
3497
281c56dd 3498 tx_desc->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
fa1c114f
JS		 3499
3500 /* Verify and set buffer length */
fa1c114f
JS		 3501
3502 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3503 if(type == AR5K_PKT_TYPE_BEACON)
281c56dd 3504 pkt_len = roundup(pkt_len, 4);
fa1c114f 3505
281c56dd 3506 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
fa1c114f
JS		 3507 return -EINVAL;
3508
281c56dd 3509 tx_desc->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
fa1c114f
JS		 3510
3511 /*
3512 * Verify and set header length
3513 * XXX: I only found that on 5210 code, does it work on 5211 ?
3514 */
3515 if (ah->ah_version == AR5K_AR5210) {
3516 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3517 return -EINVAL;
3518 tx_desc->tx_control_0 |=
3519 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3520 }
3521
3522 /*Diferences between 5210-5211*/
3523 if (ah->ah_version == AR5K_AR5210) {
3524 switch (type) {
3525 case AR5K_PKT_TYPE_BEACON:
3526 case AR5K_PKT_TYPE_PROBE_RESP:
3527 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3528 case AR5K_PKT_TYPE_PIFS:
3529 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3530 default:
3531 frame_type = type /*<< 2 ?*/;
3532 }
3533
3534 tx_desc->tx_control_0 |=
3535 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3536 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3537 } else {
3538 tx_desc->tx_control_0 |=
3539 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3540 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3541 tx_desc->tx_control_1 |=
3542 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3543 }
3544#define _TX_FLAGS(_c, _flag) \
3545 if (flags & AR5K_TXDESC_##_flag) \
3546 tx_desc->tx_control_##_c |= \
3547 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3548
3549 _TX_FLAGS(0, CLRDMASK);
3550 _TX_FLAGS(0, VEOL);
3551 _TX_FLAGS(0, INTREQ);
3552 _TX_FLAGS(0, RTSENA);
3553 _TX_FLAGS(1, NOACK);
3554
3555#undef _TX_FLAGS
3556
3557 /*
3558 * WEP crap
3559 */
3560 if (key_index != AR5K_TXKEYIX_INVALID) {
3561 tx_desc->tx_control_0 |=
3562 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3563 tx_desc->tx_control_1 |=
3564 AR5K_REG_SM(key_index,
3565 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3566 }
3567
3568 /*
3569 * RTS/CTS Duration [5210 ?]
3570 */
3571 if ((ah->ah_version == AR5K_AR5210) &&
3572 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3573 tx_desc->tx_control_1 |= rtscts_duration &
3574 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3575
3576 return 0;
3577}
3578
3579/*
3580 * Initialize the 4-word tx descriptor on 5212
3581 */
3582static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3583 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3584 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3585 unsigned int tx_tries0, unsigned int key_index,
3586 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3587 unsigned int rtscts_duration)
3588{
3589 struct ath5k_hw_4w_tx_desc *tx_desc;
3590 struct ath5k_hw_tx_status *tx_status;
281c56dd 3591 unsigned int frame_len;
fa1c114f
JS		 3592
3593 ATH5K_TRACE(ah->ah_sc);
3594 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3595 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3596
3597 /*
3598 * Validate input
3599 * - Zero retries don't make sense.
3600 * - A zero rate will put the HW into a mode where it continously sends
3601 * noise on the channel, so it is important to avoid this.
3602 */
3603 if (unlikely(tx_tries0 == 0)) {
3604 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3605 WARN_ON(1);
3606 return -EINVAL;
3607 }
3608 if (unlikely(tx_rate0 == 0)) {
3609 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3610 WARN_ON(1);
3611 return -EINVAL;
3612 }
3613
3614 /* Clear status descriptor */
3615 memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
3616
3617 /* Initialize control descriptor */
3618 tx_desc->tx_control_0 = 0;
3619 tx_desc->tx_control_1 = 0;
3620 tx_desc->tx_control_2 = 0;
3621 tx_desc->tx_control_3 = 0;
3622
3623 /* Setup control descriptor */
3624
3625 /* Verify and set frame length */
281c56dd
BR		 3626
3627 /* remove padding we might have added before */
3628 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3629
3630 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
fa1c114f
JS		 3631 return -EINVAL;
3632
281c56dd 3633 tx_desc->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
fa1c114f
JS		 3634
3635 /* Verify and set buffer length */
fa1c114f
JS		 3636
3637 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3638 if(type == AR5K_PKT_TYPE_BEACON)
281c56dd 3639 pkt_len = roundup(pkt_len, 4);
fa1c114f 3640
281c56dd 3641 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
fa1c114f
JS		 3642 return -EINVAL;
3643
281c56dd 3644 tx_desc->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
fa1c114f
JS		 3645
3646 tx_desc->tx_control_0 |=
3647 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3648 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3649 tx_desc->tx_control_1 |= AR5K_REG_SM(type,
3650 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3651 tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3652 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3653 tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3654
3655#define _TX_FLAGS(_c, _flag) \
3656 if (flags & AR5K_TXDESC_##_flag) \
3657 tx_desc->tx_control_##_c |= \
3658 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3659
3660 _TX_FLAGS(0, CLRDMASK);
3661 _TX_FLAGS(0, VEOL);
3662 _TX_FLAGS(0, INTREQ);
3663 _TX_FLAGS(0, RTSENA);
3664 _TX_FLAGS(0, CTSENA);
3665 _TX_FLAGS(1, NOACK);
3666
3667#undef _TX_FLAGS
3668
3669 /*
3670 * WEP crap
3671 */
3672 if (key_index != AR5K_TXKEYIX_INVALID) {
3673 tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3674 tx_desc->tx_control_1 |= AR5K_REG_SM(key_index,
3675 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3676 }
3677
3678 /*
3679 * RTS/CTS
3680 */
3681 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3682 if ((flags & AR5K_TXDESC_RTSENA) &&
3683 (flags & AR5K_TXDESC_CTSENA))
3684 return -EINVAL;
3685 tx_desc->tx_control_2 |= rtscts_duration &
3686 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3687 tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3688 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3689 }
3690
3691 return 0;
3692}
3693
3694/*
3695 * Initialize a 4-word multirate tx descriptor on 5212
3696 */
b9887638 3697static int
fa1c114f
JS		 3698ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3699 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3700 unsigned int tx_rate3, u_int tx_tries3)
3701{
3702 struct ath5k_hw_4w_tx_desc *tx_desc;
3703
3704 /*
3705 * Rates can be 0 as long as the retry count is 0 too.
3706 * A zero rate and nonzero retry count will put the HW into a mode where
3707 * it continously sends noise on the channel, so it is important to
3708 * avoid this.
3709 */
3710 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3711 (tx_rate2 == 0 && tx_tries2 != 0) ||
3712 (tx_rate3 == 0 && tx_tries3 != 0))) {
3713 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3714 WARN_ON(1);
3715 return -EINVAL;
3716 }
3717
3718 if (ah->ah_version == AR5K_AR5212) {
3719 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3720
3721#define _XTX_TRIES(_n) \
3722 if (tx_tries##_n) { \
3723 tx_desc->tx_control_2 |= \
3724 AR5K_REG_SM(tx_tries##_n, \
3725 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3726 tx_desc->tx_control_3 |= \
3727 AR5K_REG_SM(tx_rate##_n, \
3728 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3729 }
3730
3731 _XTX_TRIES(1);
3732 _XTX_TRIES(2);
3733 _XTX_TRIES(3);
3734
3735#undef _XTX_TRIES
3736
b9887638 3737 return 1;
fa1c114f
JS		 3738 }
3739
b9887638 3740 return 0;
fa1c114f
JS		 3741}
3742
3743/*
3744 * Proccess the tx status descriptor on 5210/5211
3745 */
3746static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3747 struct ath5k_desc *desc)
3748{
3749 struct ath5k_hw_tx_status *tx_status;
3750 struct ath5k_hw_2w_tx_desc *tx_desc;
3751
3752 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3753 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
3754
3755 /* No frame has been send or error */
3756 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3757 return -EINPROGRESS;
3758
3759 /*
3760 * Get descriptor status
3761 */
3762 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3763 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3764 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3765 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3766 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3767 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3768 /*TODO: desc->ds_us.tx.ts_virtcol + test*/
3769 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3770 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3771 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3772 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3773 desc->ds_us.tx.ts_antenna = 1;
3774 desc->ds_us.tx.ts_status = 0;
3775 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0,
3776 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3777
3778 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3779 if (tx_status->tx_status_0 &
3780 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3781 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3782
3783 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3784 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3785
3786 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3787 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3788 }
3789
3790 return 0;
3791}
3792
3793/*
3794 * Proccess a tx descriptor on 5212
3795 */
3796static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3797 struct ath5k_desc *desc)
3798{
3799 struct ath5k_hw_tx_status *tx_status;
3800 struct ath5k_hw_4w_tx_desc *tx_desc;
3801
3802 ATH5K_TRACE(ah->ah_sc);
3803 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3804 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3805
3806 /* No frame has been send or error */
3807 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3808 return -EINPROGRESS;
3809
3810 /*
3811 * Get descriptor status
3812 */
3813 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3814 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3815 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3816 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3817 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3818 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3819 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3820 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3821 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3822 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3823 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
3824 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3825 desc->ds_us.tx.ts_status = 0;
3826
3827 switch (AR5K_REG_MS(tx_status->tx_status_1,
3828 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3829 case 0:
3830 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
3831 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3832 break;
3833 case 1:
3834 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3835 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3836 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3837 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3838 break;
3839 case 2:
3840 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3841 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3842 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3843 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3844 break;
3845 case 3:
3846 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3847 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3848 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3849 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3850 break;
3851 }
3852
3853 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3854 if (tx_status->tx_status_0 &
3855 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3856 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3857
3858 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3859 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3860
3861 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3862 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3863 }
3864
3865 return 0;
3866}
3867
3868/*
3869 * RX Descriptor
3870 */
3871
3872/*
3873 * Initialize an rx descriptor
3874 */
3875int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3876 u32 size, unsigned int flags)
3877{
3878 struct ath5k_rx_desc *rx_desc;
3879
3880 ATH5K_TRACE(ah->ah_sc);
3881 rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
3882
3883 /*
3884 *Clear ds_hw
3885 * If we don't clean the status descriptor,
3886 * while scanning we get too many results,
3887 * most of them virtual, after some secs
3888 * of scanning system hangs. M.F.
3889 */
3890 memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
3891
3892 /*Initialize rx descriptor*/
3893 rx_desc->rx_control_0 = 0;
3894 rx_desc->rx_control_1 = 0;
3895
3896 /* Setup descriptor */
3897 rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
3898 if (unlikely(rx_desc->rx_control_1 != size))
3899 return -EINVAL;
3900
3901 if (flags & AR5K_RXDESC_INTREQ)
3902 rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
3903
3904 return 0;
3905}
3906
3907/*
3908 * Proccess the rx status descriptor on 5210/5211
3909 */
3910static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah,
3911 struct ath5k_desc *desc)
3912{
3913 struct ath5k_hw_old_rx_status *rx_status;
3914
3915 rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
3916
3917 /* No frame received / not ready */
3918 if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
3919 == 0))
3920 return -EINPROGRESS;
3921
3922 /*
3923 * Frame receive status
3924 */
3925 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
3926 AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
3927 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
3928 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
3929 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
3930 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
3931 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
3932 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
3933 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
3934 AR5K_OLD_RX_DESC_STATUS0_MORE;
3935 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
3936 AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
3937 desc->ds_us.rx.rs_status = 0;
3938
3939 /*
3940 * Key table status
3941 */
3942 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
3943 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
3944 AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
3945 else
3946 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
3947
3948 /*
3949 * Receive/descriptor errors
3950 */
3951 if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK)
3952 == 0) {
3953 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
3954 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
3955
3956 if (rx_status->rx_status_1 &
3957 AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN)
3958 desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO;
3959
3960 if (rx_status->rx_status_1 &
3961 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) {
3962 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
3963 desc->ds_us.rx.rs_phyerr =
3964 AR5K_REG_MS(rx_status->rx_status_1,
3965 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
3966 }
3967
3968 if (rx_status->rx_status_1 &
3969 AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
3970 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
3971 }
3972
3973 return 0;
3974}
3975
3976/*
3977 * Proccess the rx status descriptor on 5212
3978 */
3979static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah,
3980 struct ath5k_desc *desc)
3981{
3982 struct ath5k_hw_new_rx_status *rx_status;
3983 struct ath5k_hw_rx_error *rx_err;
3984
3985 ATH5K_TRACE(ah->ah_sc);
3986 rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
3987
3988 /* Overlay on error */
3989 rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
3990
3991 /* No frame received / not ready */
3992 if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
3993 == 0))
3994 return -EINPROGRESS;
3995
3996 /*
3997 * Frame receive status
3998 */
3999 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
4000 AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
4001 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4002 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4003 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4004 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
4005 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
4006 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4007 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
4008 AR5K_NEW_RX_DESC_STATUS0_MORE;
4009 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4010 AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4011 desc->ds_us.rx.rs_status = 0;
4012
4013 /*
4014 * Key table status
4015 */
4016 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID)
4017 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4018 AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX);
4019 else
4020 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
4021
4022 /*
4023 * Receive/descriptor errors
4024 */
4025 if ((rx_status->rx_status_1 &
4026 AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4027 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
4028 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
4029
4030 if (rx_status->rx_status_1 &
4031 AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
4032 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4033 desc->ds_us.rx.rs_phyerr =
4034 AR5K_REG_MS(rx_err->rx_error_1,
4035 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4036 }
4037
4038 if (rx_status->rx_status_1 &
4039 AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4040 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4041
4042 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
4043 desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
4044 }
4045
4046 return 0;
4047}
4048
4049
4050/****************\
4051 GPIO Functions
4052\****************/
4053
4054/*
4055 * Set led state
4056 */
4057void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4058{
4059 u32 led;
4060 /*5210 has different led mode handling*/
4061 u32 led_5210;
4062
4063 ATH5K_TRACE(ah->ah_sc);
4064
4065 /*Reset led status*/
4066 if (ah->ah_version != AR5K_AR5210)
4067 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4068 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4069 else
4070 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4071
4072 /*
4073 * Some blinking values, define at your wish
4074 */
4075 switch (state) {
4076 case AR5K_LED_SCAN:
4077 case AR5K_LED_AUTH:
4078 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4079 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4080 break;
4081
4082 case AR5K_LED_INIT:
4083 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4084 led_5210 = AR5K_PCICFG_LED_PEND;
4085 break;
4086
4087 case AR5K_LED_ASSOC:
4088 case AR5K_LED_RUN:
4089 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4090 led_5210 = AR5K_PCICFG_LED_ASSOC;
4091 break;
4092
4093 default:
4094 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4095 led_5210 = AR5K_PCICFG_LED_PEND;
4096 break;
4097 }
4098
4099 /*Write new status to the register*/
4100 if (ah->ah_version != AR5K_AR5210)
4101 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4102 else
4103 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4104}
4105
4106/*
4107 * Set GPIO outputs
4108 */
4109int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4110{
4111 ATH5K_TRACE(ah->ah_sc);
4112 if (gpio > AR5K_NUM_GPIO)
4113 return -EINVAL;
4114
4115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4116 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4117
4118 return 0;
4119}
4120
4121/*
4122 * Set GPIO inputs
4123 */
4124int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4125{
4126 ATH5K_TRACE(ah->ah_sc);
4127 if (gpio > AR5K_NUM_GPIO)
4128 return -EINVAL;
4129
4130 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4131 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4132
4133 return 0;
4134}
4135
4136/*
4137 * Get GPIO state
4138 */
4139u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4140{
4141 ATH5K_TRACE(ah->ah_sc);
4142 if (gpio > AR5K_NUM_GPIO)
4143 return 0xffffffff;
4144
4145 /* GPIO input magic */
4146 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4147 0x1;
4148}
4149
4150/*
4151 * Set GPIO state
4152 */
4153int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4154{
4155 u32 data;
4156 ATH5K_TRACE(ah->ah_sc);
4157
4158 if (gpio > AR5K_NUM_GPIO)
4159 return -EINVAL;
4160
4161 /* GPIO output magic */
4162 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4163
4164 data &= ~(1 << gpio);
4165 data |= (val & 1) << gpio;
4166
4167 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4168
4169 return 0;
4170}
4171
4172/*
4173 * Initialize the GPIO interrupt (RFKill switch)
4174 */
4175void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4176 u32 interrupt_level)
4177{
4178 u32 data;
4179
4180 ATH5K_TRACE(ah->ah_sc);
4181 if (gpio > AR5K_NUM_GPIO)
4182 return;
4183
4184 /*
4185 * Set the GPIO interrupt
4186 */
4187 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4188 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4189 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4190 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4191
4192 ath5k_hw_reg_write(ah, interrupt_level ? data :
4193 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4194
4195 ah->ah_imr |= AR5K_IMR_GPIO;
4196
4197 /* Enable GPIO interrupts */
4198 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4199}
4200
4201
fa1c114f
JS		 4202
4203
4204/****************\
4205 Misc functions
4206\****************/
4207
4208int ath5k_hw_get_capability(struct ath5k_hw *ah,
4209 enum ath5k_capability_type cap_type,
4210 u32 capability, u32 *result)
4211{
4212 ATH5K_TRACE(ah->ah_sc);
4213
4214 switch (cap_type) {
4215 case AR5K_CAP_NUM_TXQUEUES:
4216 if (result) {
4217 if (ah->ah_version == AR5K_AR5210)
4218 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4219 else
4220 *result = AR5K_NUM_TX_QUEUES;
4221 goto yes;
4222 }
4223 case AR5K_CAP_VEOL:
4224 goto yes;
4225 case AR5K_CAP_COMPRESSION:
4226 if (ah->ah_version == AR5K_AR5212)
4227 goto yes;
4228 else
4229 goto no;
4230 case AR5K_CAP_BURST:
4231 goto yes;
4232 case AR5K_CAP_TPC:
4233 goto yes;
4234 case AR5K_CAP_BSSIDMASK:
4235 if (ah->ah_version == AR5K_AR5212)
4236 goto yes;
4237 else
4238 goto no;
4239 case AR5K_CAP_XR:
4240 if (ah->ah_version == AR5K_AR5212)
4241 goto yes;
4242 else
4243 goto no;
4244 default:
4245 goto no;
4246 }
4247
4248no:
4249 return -EINVAL;
4250yes:
4251 return 0;
4252}
4253
4254static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4255 u16 assoc_id)
4256{
4257 ATH5K_TRACE(ah->ah_sc);
4258
4259 if (ah->ah_version == AR5K_AR5210) {
4260 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4261 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4262 return 0;
4263 }
4264
4265 return -EIO;
4266}
4267
4268static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4269{
4270 ATH5K_TRACE(ah->ah_sc);
4271
4272 if (ah->ah_version == AR5K_AR5210) {
4273 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4274 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4275 return 0;
4276 }
4277
4278 return -EIO;
4279}
Linux 6.x block layer and io_uring tree(s)