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[linux-2.6-block.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 75MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 98 { 0 }
99};
100MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
101
102/* Known SREVs */
103static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 104 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
105 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
106 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
107 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
108 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
109 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
110 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
111 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
112 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
113 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
114 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
115 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
116 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
117 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
118 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
119 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
120 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
121 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
135 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
136 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
137 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 138 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
139 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
140};
141
63266a65
BR		 142static struct ieee80211_rate ath5k_rates[] = {
143 { .bitrate = 10,
144 .hw_value = ATH5K_RATE_CODE_1M, },
145 { .bitrate = 20,
146 .hw_value = ATH5K_RATE_CODE_2M,
147 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
148 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
149 { .bitrate = 55,
150 .hw_value = ATH5K_RATE_CODE_5_5M,
151 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
152 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 { .bitrate = 110,
154 .hw_value = ATH5K_RATE_CODE_11M,
155 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 60,
158 .hw_value = ATH5K_RATE_CODE_6M,
159 .flags = 0 },
160 { .bitrate = 90,
161 .hw_value = ATH5K_RATE_CODE_9M,
162 .flags = 0 },
163 { .bitrate = 120,
164 .hw_value = ATH5K_RATE_CODE_12M,
165 .flags = 0 },
166 { .bitrate = 180,
167 .hw_value = ATH5K_RATE_CODE_18M,
168 .flags = 0 },
169 { .bitrate = 240,
170 .hw_value = ATH5K_RATE_CODE_24M,
171 .flags = 0 },
172 { .bitrate = 360,
173 .hw_value = ATH5K_RATE_CODE_36M,
174 .flags = 0 },
175 { .bitrate = 480,
176 .hw_value = ATH5K_RATE_CODE_48M,
177 .flags = 0 },
178 { .bitrate = 540,
179 .hw_value = ATH5K_RATE_CODE_54M,
180 .flags = 0 },
181 /* XR missing */
182};
183
fa1c114f
JS		 184/*
185 * Prototypes - PCI stack related functions
186 */
187static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
188 const struct pci_device_id *id);
189static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
190#ifdef CONFIG_PM
191static int ath5k_pci_suspend(struct pci_dev *pdev,
192 pm_message_t state);
193static int ath5k_pci_resume(struct pci_dev *pdev);
194#else
195#define ath5k_pci_suspend NULL
196#define ath5k_pci_resume NULL
197#endif /* CONFIG_PM */
198
04a9e451 199static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 200 .name = "ath5k_pci",
201 .id_table = ath5k_pci_id_table,
202 .probe = ath5k_pci_probe,
203 .remove = __devexit_p(ath5k_pci_remove),
204 .suspend = ath5k_pci_suspend,
205 .resume = ath5k_pci_resume,
206};
207
208
209
210/*
211 * Prototypes - MAC 802.11 stack related functions
212 */
e039fa4a 213static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 214static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
215static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 216static int ath5k_start(struct ieee80211_hw *hw);
217static void ath5k_stop(struct ieee80211_hw *hw);
218static int ath5k_add_interface(struct ieee80211_hw *hw,
219 struct ieee80211_if_init_conf *conf);
220static void ath5k_remove_interface(struct ieee80211_hw *hw,
221 struct ieee80211_if_init_conf *conf);
222static int ath5k_config(struct ieee80211_hw *hw,
223 struct ieee80211_conf *conf);
32bfd35d
JB		 224static int ath5k_config_interface(struct ieee80211_hw *hw,
225 struct ieee80211_vif *vif,
fa1c114f
JS		 226 struct ieee80211_if_conf *conf);
227static void ath5k_configure_filter(struct ieee80211_hw *hw,
228 unsigned int changed_flags,
229 unsigned int *new_flags,
230 int mc_count, struct dev_mc_list *mclist);
231static int ath5k_set_key(struct ieee80211_hw *hw,
232 enum set_key_cmd cmd,
233 const u8 *local_addr, const u8 *addr,
234 struct ieee80211_key_conf *key);
235static int ath5k_get_stats(struct ieee80211_hw *hw,
236 struct ieee80211_low_level_stats *stats);
237static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
238 struct ieee80211_tx_queue_stats *stats);
239static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
240static void ath5k_reset_tsf(struct ieee80211_hw *hw);
241static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 242 struct sk_buff *skb);
02969b38
MX		 243static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
244 struct ieee80211_vif *vif,
245 struct ieee80211_bss_conf *bss_conf,
246 u32 changes);
fa1c114f
JS		 247
248static struct ieee80211_ops ath5k_hw_ops = {
249 .tx = ath5k_tx,
250 .start = ath5k_start,
251 .stop = ath5k_stop,
252 .add_interface = ath5k_add_interface,
253 .remove_interface = ath5k_remove_interface,
254 .config = ath5k_config,
255 .config_interface = ath5k_config_interface,
256 .configure_filter = ath5k_configure_filter,
257 .set_key = ath5k_set_key,
258 .get_stats = ath5k_get_stats,
259 .conf_tx = NULL,
260 .get_tx_stats = ath5k_get_tx_stats,
261 .get_tsf = ath5k_get_tsf,
262 .reset_tsf = ath5k_reset_tsf,
02969b38 263 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 264};
265
266/*
267 * Prototypes - Internal functions
268 */
269/* Attach detach */
270static int ath5k_attach(struct pci_dev *pdev,
271 struct ieee80211_hw *hw);
272static void ath5k_detach(struct pci_dev *pdev,
273 struct ieee80211_hw *hw);
274/* Channel/mode setup */
275static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 276static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
277 struct ieee80211_channel *channels,
278 unsigned int mode,
279 unsigned int max);
63266a65 280static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 281static int ath5k_chan_set(struct ath5k_softc *sc,
282 struct ieee80211_channel *chan);
283static void ath5k_setcurmode(struct ath5k_softc *sc,
284 unsigned int mode);
285static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 286
fa1c114f
JS		 287/* Descriptor setup */
288static int ath5k_desc_alloc(struct ath5k_softc *sc,
289 struct pci_dev *pdev);
290static void ath5k_desc_free(struct ath5k_softc *sc,
291 struct pci_dev *pdev);
292/* Buffers setup */
293static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
294 struct ath5k_buf *bf);
295static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 296 struct ath5k_buf *bf);
fa1c114f
JS		 297static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
298 struct ath5k_buf *bf)
299{
300 BUG_ON(!bf);
301 if (!bf->skb)
302 return;
303 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
304 PCI_DMA_TODEVICE);
00482973 305 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 306 bf->skb = NULL;
307}
308
309/* Queues setup */
310static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
311 int qtype, int subtype);
312static int ath5k_beaconq_setup(struct ath5k_hw *ah);
313static int ath5k_beaconq_config(struct ath5k_softc *sc);
314static void ath5k_txq_drainq(struct ath5k_softc *sc,
315 struct ath5k_txq *txq);
316static void ath5k_txq_cleanup(struct ath5k_softc *sc);
317static void ath5k_txq_release(struct ath5k_softc *sc);
318/* Rx handling */
319static int ath5k_rx_start(struct ath5k_softc *sc);
320static void ath5k_rx_stop(struct ath5k_softc *sc);
321static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
322 struct ath5k_desc *ds,
b47f407b
BR		 323 struct sk_buff *skb,
324 struct ath5k_rx_status *rs);
fa1c114f
JS		 325static void ath5k_tasklet_rx(unsigned long data);
326/* Tx handling */
327static void ath5k_tx_processq(struct ath5k_softc *sc,
328 struct ath5k_txq *txq);
329static void ath5k_tasklet_tx(unsigned long data);
330/* Beacon handling */
331static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 332 struct ath5k_buf *bf);
fa1c114f
JS		 333static void ath5k_beacon_send(struct ath5k_softc *sc);
334static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 335static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 336
337static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
338{
339 u64 tsf = ath5k_hw_get_tsf64(ah);
340
341 if ((tsf & 0x7fff) < rstamp)
342 tsf -= 0x8000;
343
344 return (tsf & ~0x7fff) | rstamp;
345}
346
347/* Interrupt handling */
8bdd5b9c 348static int ath5k_init(struct ath5k_softc *sc, bool is_resume);
fa1c114f 349static int ath5k_stop_locked(struct ath5k_softc *sc);
8bdd5b9c 350static int ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
fa1c114f
JS		 351static irqreturn_t ath5k_intr(int irq, void *dev_id);
352static void ath5k_tasklet_reset(unsigned long data);
353
354static void ath5k_calibrate(unsigned long data);
355/* LED functions */
3a078876
BC		 356static int ath5k_init_leds(struct ath5k_softc *sc);
357static void ath5k_led_enable(struct ath5k_softc *sc);
358static void ath5k_led_off(struct ath5k_softc *sc);
359static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 360
361/*
362 * Module init/exit functions
363 */
364static int __init
365init_ath5k_pci(void)
366{
367 int ret;
368
369 ath5k_debug_init();
370
04a9e451 371 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 372 if (ret) {
373 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
374 return ret;
375 }
376
377 return 0;
378}
379
380static void __exit
381exit_ath5k_pci(void)
382{
04a9e451 383 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 384
385 ath5k_debug_finish();
386}
387
388module_init(init_ath5k_pci);
389module_exit(exit_ath5k_pci);
390
391
392/********************\
393* PCI Initialization *
394\********************/
395
396static const char *
397ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
398{
399 const char *name = "xxxxx";
400 unsigned int i;
401
402 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
403 if (srev_names[i].sr_type != type)
404 continue;
75d0edb8
NK		 405
406 if ((val & 0xf0) == srev_names[i].sr_val)
407 name = srev_names[i].sr_name;
408
409 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 410 name = srev_names[i].sr_name;
411 break;
412 }
413 }
414
415 return name;
416}
417
418static int __devinit
419ath5k_pci_probe(struct pci_dev *pdev,
420 const struct pci_device_id *id)
421{
422 void __iomem *mem;
423 struct ath5k_softc *sc;
424 struct ieee80211_hw *hw;
425 int ret;
426 u8 csz;
427
428 ret = pci_enable_device(pdev);
429 if (ret) {
430 dev_err(&pdev->dev, "can't enable device\n");
431 goto err;
432 }
433
434 /* XXX 32-bit addressing only */
435 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
436 if (ret) {
437 dev_err(&pdev->dev, "32-bit DMA not available\n");
438 goto err_dis;
439 }
440
441 /*
442 * Cache line size is used to size and align various
443 * structures used to communicate with the hardware.
444 */
445 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
446 if (csz == 0) {
447 /*
448 * Linux 2.4.18 (at least) writes the cache line size
449 * register as a 16-bit wide register which is wrong.
450 * We must have this setup properly for rx buffer
451 * DMA to work so force a reasonable value here if it
452 * comes up zero.
453 */
454 csz = L1_CACHE_BYTES / sizeof(u32);
455 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
456 }
457 /*
458 * The default setting of latency timer yields poor results,
459 * set it to the value used by other systems. It may be worth
460 * tweaking this setting more.
461 */
462 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
463
464 /* Enable bus mastering */
465 pci_set_master(pdev);
466
467 /*
468 * Disable the RETRY_TIMEOUT register (0x41) to keep
469 * PCI Tx retries from interfering with C3 CPU state.
470 */
471 pci_write_config_byte(pdev, 0x41, 0);
472
473 ret = pci_request_region(pdev, 0, "ath5k");
474 if (ret) {
475 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
476 goto err_dis;
477 }
478
479 mem = pci_iomap(pdev, 0, 0);
480 if (!mem) {
481 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
482 ret = -EIO;
483 goto err_reg;
484 }
485
486 /*
487 * Allocate hw (mac80211 main struct)
488 * and hw->priv (driver private data)
489 */
490 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
491 if (hw == NULL) {
492 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
493 ret = -ENOMEM;
494 goto err_map;
495 }
496
497 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
498
499 /* Initialize driver private data */
500 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 501 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
502 IEEE80211_HW_SIGNAL_DBM |
503 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 504
505 hw->wiphy->interface_modes =
506 BIT(NL80211_IFTYPE_STATION) |
507 BIT(NL80211_IFTYPE_ADHOC) |
508 BIT(NL80211_IFTYPE_MESH_POINT);
509
fa1c114f
JS		 510 hw->extra_tx_headroom = 2;
511 hw->channel_change_time = 5000;
fa1c114f
JS		 512 sc = hw->priv;
513 sc->hw = hw;
514 sc->pdev = pdev;
515
516 ath5k_debug_init_device(sc);
517
518 /*
519 * Mark the device as detached to avoid processing
520 * interrupts until setup is complete.
521 */
522 __set_bit(ATH_STAT_INVALID, sc->status);
523
524 sc->iobase = mem; /* So we can unmap it on detach */
525 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 526 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 527 mutex_init(&sc->lock);
528 spin_lock_init(&sc->rxbuflock);
529 spin_lock_init(&sc->txbuflock);
00482973 530 spin_lock_init(&sc->block);
fa1c114f
JS		 531
532 /* Set private data */
533 pci_set_drvdata(pdev, hw);
534
fa1c114f
JS		 535 /* Setup interrupt handler */
536 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
537 if (ret) {
538 ATH5K_ERR(sc, "request_irq failed\n");
539 goto err_free;
540 }
541
542 /* Initialize device */
543 sc->ah = ath5k_hw_attach(sc, id->driver_data);
544 if (IS_ERR(sc->ah)) {
545 ret = PTR_ERR(sc->ah);
546 goto err_irq;
547 }
548
2f7fe870
FF		 549 /* set up multi-rate retry capabilities */
550 if (sc->ah->ah_version == AR5K_AR5212) {
551 hw->max_altrates = 3;
552 hw->max_altrate_tries = 11;
553 }
554
fa1c114f
JS		 555 /* Finish private driver data initialization */
556 ret = ath5k_attach(pdev, hw);
557 if (ret)
558 goto err_ah;
559
560 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 561 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 562 sc->ah->ah_mac_srev,
563 sc->ah->ah_phy_revision);
564
400ec45a 565 if (!sc->ah->ah_single_chip) {
fa1c114f 566 /* Single chip radio (!RF5111) */
400ec45a
LR		 567 if (sc->ah->ah_radio_5ghz_revision &&
568 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 569 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 570 if (!test_bit(AR5K_MODE_11A,
571 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 572 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 573 ath5k_chip_name(AR5K_VERSION_RAD,
574 sc->ah->ah_radio_5ghz_revision),
575 sc->ah->ah_radio_5ghz_revision);
576 /* No 2GHz support (5110 and some
577 * 5Ghz only cards) -> report 5Ghz radio */
578 } else if (!test_bit(AR5K_MODE_11B,
579 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 580 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 581 ath5k_chip_name(AR5K_VERSION_RAD,
582 sc->ah->ah_radio_5ghz_revision),
583 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 584 /* Multiband radio */
585 } else {
586 ATH5K_INFO(sc, "RF%s multiband radio found"
587 " (0x%x)\n",
400ec45a
LR		 588 ath5k_chip_name(AR5K_VERSION_RAD,
589 sc->ah->ah_radio_5ghz_revision),
590 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 591 }
592 }
400ec45a
LR		 593 /* Multi chip radio (RF5111 - RF2111) ->
594 * report both 2GHz/5GHz radios */
595 else if (sc->ah->ah_radio_5ghz_revision &&
596 sc->ah->ah_radio_2ghz_revision){
fa1c114f 597 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_5ghz_revision),
600 sc->ah->ah_radio_5ghz_revision);
fa1c114f 601 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 602 ath5k_chip_name(AR5K_VERSION_RAD,
603 sc->ah->ah_radio_2ghz_revision),
604 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 605 }
606 }
607
608
609 /* ready to process interrupts */
610 __clear_bit(ATH_STAT_INVALID, sc->status);
611
612 return 0;
613err_ah:
614 ath5k_hw_detach(sc->ah);
615err_irq:
616 free_irq(pdev->irq, sc);
617err_free:
fa1c114f
JS		 618 ieee80211_free_hw(hw);
619err_map:
620 pci_iounmap(pdev, mem);
621err_reg:
622 pci_release_region(pdev, 0);
623err_dis:
624 pci_disable_device(pdev);
625err:
626 return ret;
627}
628
629static void __devexit
630ath5k_pci_remove(struct pci_dev *pdev)
631{
632 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
633 struct ath5k_softc *sc = hw->priv;
634
635 ath5k_debug_finish_device(sc);
636 ath5k_detach(pdev, hw);
637 ath5k_hw_detach(sc->ah);
638 free_irq(pdev->irq, sc);
fa1c114f
JS		 639 pci_iounmap(pdev, sc->iobase);
640 pci_release_region(pdev, 0);
641 pci_disable_device(pdev);
642 ieee80211_free_hw(hw);
643}
644
645#ifdef CONFIG_PM
646static int
647ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
648{
649 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
650 struct ath5k_softc *sc = hw->priv;
651
3a078876 652 ath5k_led_off(sc);
fa1c114f 653
8bdd5b9c 654 ath5k_stop_hw(sc, true);
3e4242b9
JS		 655
656 free_irq(pdev->irq, sc);
fa1c114f
JS		 657 pci_save_state(pdev);
658 pci_disable_device(pdev);
659 pci_set_power_state(pdev, PCI_D3hot);
660
661 return 0;
662}
663
664static int
665ath5k_pci_resume(struct pci_dev *pdev)
666{
667 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
668 struct ath5k_softc *sc = hw->priv;
bc1b32d6 669 int err;
fa1c114f 670
3e4242b9 671 pci_restore_state(pdev);
fa1c114f
JS		 672
673 err = pci_enable_device(pdev);
674 if (err)
675 return err;
676
fa1c114f
JS		 677 /*
678 * Suspend/Resume resets the PCI configuration space, so we have to
679 * re-disable the RETRY_TIMEOUT register (0x41) to keep
680 * PCI Tx retries from interfering with C3 CPU state
681 */
682 pci_write_config_byte(pdev, 0x41, 0);
683
3e4242b9
JS		 684 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
685 if (err) {
686 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 687 goto err_no_irq;
3e4242b9
JS		 688 }
689
8bdd5b9c 690 err = ath5k_init(sc, true);
3e4242b9
JS		 691 if (err)
692 goto err_irq;
3a078876 693 ath5k_led_enable(sc);
fa1c114f
JS		 694
695 return 0;
3e4242b9
JS		 696err_irq:
697 free_irq(pdev->irq, sc);
37465c8a 698err_no_irq:
3e4242b9
JS		 699 pci_disable_device(pdev);
700 return err;
fa1c114f
JS		 701}
702#endif /* CONFIG_PM */
703
704
fa1c114f
JS		 705/***********************\
706* Driver Initialization *
707\***********************/
708
709static int
710ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
711{
712 struct ath5k_softc *sc = hw->priv;
713 struct ath5k_hw *ah = sc->ah;
714 u8 mac[ETH_ALEN];
fa1c114f
JS		 715 int ret;
716
717 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
718
719 /*
720 * Check if the MAC has multi-rate retry support.
721 * We do this by trying to setup a fake extended
722 * descriptor. MAC's that don't have support will
723 * return false w/o doing anything. MAC's that do
724 * support it will return true w/o doing anything.
725 */
c6e387a2 726 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 727 if (ret < 0)
728 goto err;
729 if (ret > 0)
fa1c114f
JS		 730 __set_bit(ATH_STAT_MRRETRY, sc->status);
731
fa1c114f
JS		 732 /*
733 * Collect the channel list. The 802.11 layer
734 * is resposible for filtering this list based
735 * on settings like the phy mode and regulatory
736 * domain restrictions.
737 */
63266a65 738 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 739 if (ret) {
740 ATH5K_ERR(sc, "can't get channels\n");
741 goto err;
742 }
743
744 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 745 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
746 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 747 else
d8ee398d 748 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 749
750 /*
751 * Allocate tx+rx descriptors and populate the lists.
752 */
753 ret = ath5k_desc_alloc(sc, pdev);
754 if (ret) {
755 ATH5K_ERR(sc, "can't allocate descriptors\n");
756 goto err;
757 }
758
759 /*
760 * Allocate hardware transmit queues: one queue for
761 * beacon frames and one data queue for each QoS
762 * priority. Note that hw functions handle reseting
763 * these queues at the needed time.
764 */
765 ret = ath5k_beaconq_setup(ah);
766 if (ret < 0) {
767 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
768 goto err_desc;
769 }
770 sc->bhalq = ret;
771
772 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
773 if (IS_ERR(sc->txq)) {
774 ATH5K_ERR(sc, "can't setup xmit queue\n");
775 ret = PTR_ERR(sc->txq);
776 goto err_bhal;
777 }
778
779 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
780 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
781 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
782 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 783
784 ath5k_hw_get_lladdr(ah, mac);
785 SET_IEEE80211_PERM_ADDR(hw, mac);
786 /* All MAC address bits matter for ACKs */
787 memset(sc->bssidmask, 0xff, ETH_ALEN);
788 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
789
790 ret = ieee80211_register_hw(hw);
791 if (ret) {
792 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
793 goto err_queues;
794 }
795
3a078876
BC		 796 ath5k_init_leds(sc);
797
fa1c114f
JS		 798 return 0;
799err_queues:
800 ath5k_txq_release(sc);
801err_bhal:
802 ath5k_hw_release_tx_queue(ah, sc->bhalq);
803err_desc:
804 ath5k_desc_free(sc, pdev);
805err:
806 return ret;
807}
808
809static void
810ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
811{
812 struct ath5k_softc *sc = hw->priv;
813
814 /*
815 * NB: the order of these is important:
816 * o call the 802.11 layer before detaching ath5k_hw to
817 * insure callbacks into the driver to delete global
818 * key cache entries can be handled
819 * o reclaim the tx queue data structures after calling
820 * the 802.11 layer as we'll get called back to reclaim
821 * node state and potentially want to use them
822 * o to cleanup the tx queues the hal is called, so detach
823 * it last
824 * XXX: ??? detach ath5k_hw ???
825 * Other than that, it's straightforward...
826 */
827 ieee80211_unregister_hw(hw);
828 ath5k_desc_free(sc, pdev);
829 ath5k_txq_release(sc);
830 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 831 ath5k_unregister_leds(sc);
fa1c114f
JS		 832
833 /*
834 * NB: can't reclaim these until after ieee80211_ifdetach
835 * returns because we'll get called back to reclaim node
836 * state and potentially want to use them.
837 */
838}
839
840
841
842
843/********************\
844* Channel/mode setup *
845\********************/
846
847/*
848 * Convert IEEE channel number to MHz frequency.
849 */
850static inline short
851ath5k_ieee2mhz(short chan)
852{
853 if (chan <= 14 || chan >= 27)
854 return ieee80211chan2mhz(chan);
855 else
856 return 2212 + chan * 20;
857}
858
fa1c114f
JS		 859static unsigned int
860ath5k_copy_channels(struct ath5k_hw *ah,
861 struct ieee80211_channel *channels,
862 unsigned int mode,
863 unsigned int max)
864{
d8ee398d 865 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 866
867 if (!test_bit(mode, ah->ah_modes))
868 return 0;
869
fa1c114f 870 switch (mode) {
d8ee398d
LR		 871 case AR5K_MODE_11A:
872 case AR5K_MODE_11A_TURBO:
fa1c114f 873 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 874 size = 220 ;
fa1c114f
JS		 875 chfreq = CHANNEL_5GHZ;
876 break;
d8ee398d
LR		 877 case AR5K_MODE_11B:
878 case AR5K_MODE_11G:
879 case AR5K_MODE_11G_TURBO:
880 size = 26;
fa1c114f
JS		 881 chfreq = CHANNEL_2GHZ;
882 break;
883 default:
884 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
885 return 0;
886 }
887
888 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 889 ch = i + 1 ;
890 freq = ath5k_ieee2mhz(ch);
fa1c114f 891
d8ee398d
LR		 892 /* Check if channel is supported by the chipset */
893 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 894 continue;
895
d8ee398d
LR		 896 /* Write channel info and increment counter */
897 channels[count].center_freq = freq;
a3f4b914
LR		 898 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
899 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 900 switch (mode) {
901 case AR5K_MODE_11A:
902 case AR5K_MODE_11G:
903 channels[count].hw_value = chfreq | CHANNEL_OFDM;
904 break;
905 case AR5K_MODE_11A_TURBO:
906 case AR5K_MODE_11G_TURBO:
907 channels[count].hw_value = chfreq |
908 CHANNEL_OFDM | CHANNEL_TURBO;
909 break;
910 case AR5K_MODE_11B:
d8ee398d
LR		 911 channels[count].hw_value = CHANNEL_B;
912 }
fa1c114f 913
fa1c114f
JS		 914 count++;
915 max--;
916 }
917
918 return count;
919}
920
63266a65
BR		 921static void
922ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
923{
924 u8 i;
925
926 for (i = 0; i < AR5K_MAX_RATES; i++)
927 sc->rate_idx[b->band][i] = -1;
928
929 for (i = 0; i < b->n_bitrates; i++) {
930 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
931 if (b->bitrates[i].hw_value_short)
932 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
933 }
934}
935
d8ee398d 936static int
63266a65 937ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 938{
939 struct ath5k_softc *sc = hw->priv;
d8ee398d 940 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 941 struct ieee80211_supported_band *sband;
942 int max_c, count_c = 0;
943 int i;
fa1c114f 944
d8ee398d 945 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 946 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 947
948 /* 2GHz band */
63266a65
BR		 949 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
950 sband->band = IEEE80211_BAND_2GHZ;
951 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 952
63266a65
BR		 953 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
954 /* G mode */
955 memcpy(sband->bitrates, &ath5k_rates[0],
956 sizeof(struct ieee80211_rate) * 12);
957 sband->n_bitrates = 12;
fa1c114f 958
d8ee398d 959 sband->channels = sc->channels;
d8ee398d 960 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 961 AR5K_MODE_11G, max_c);
fa1c114f 962
63266a65 963 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 964 count_c = sband->n_channels;
63266a65
BR		 965 max_c -= count_c;
966 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
967 /* B mode */
968 memcpy(sband->bitrates, &ath5k_rates[0],
969 sizeof(struct ieee80211_rate) * 4);
970 sband->n_bitrates = 4;
971
972 /* 5211 only supports B rates and uses 4bit rate codes
973 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
974 * fix them up here:
975 */
976 if (ah->ah_version == AR5K_AR5211) {
977 for (i = 0; i < 4; i++) {
978 sband->bitrates[i].hw_value =
979 sband->bitrates[i].hw_value & 0xF;
980 sband->bitrates[i].hw_value_short =
981 sband->bitrates[i].hw_value_short & 0xF;
982 }
983 }
fa1c114f 984
63266a65
BR		 985 sband->channels = sc->channels;
986 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
987 AR5K_MODE_11B, max_c);
d8ee398d 988
63266a65
BR		 989 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
990 count_c = sband->n_channels;
d8ee398d 991 max_c -= count_c;
fa1c114f 992 }
63266a65 993 ath5k_setup_rate_idx(sc, sband);
fa1c114f 994
63266a65 995 /* 5GHz band, A mode */
400ec45a 996 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 997 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
998 sband->band = IEEE80211_BAND_5GHZ;
999 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1000
63266a65
BR		 1001 memcpy(sband->bitrates, &ath5k_rates[4],
1002 sizeof(struct ieee80211_rate) * 8);
1003 sband->n_bitrates = 8;
fa1c114f 1004
63266a65 1005 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1006 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1007 AR5K_MODE_11A, max_c);
1008
d8ee398d
LR		 1009 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1010 }
63266a65 1011 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1012
b446197c 1013 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1014
1015 return 0;
fa1c114f
JS		 1016}
1017
1018/*
1019 * Set/change channels. If the channel is really being changed,
1020 * it's done by reseting the chip. To accomplish this we must
1021 * first cleanup any pending DMA, then restart stuff after a la
1022 * ath5k_init.
1023 */
1024static int
1025ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1026{
d8ee398d
LR		 1027 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1028 sc->curchan->center_freq, chan->center_freq);
1029
1030 if (chan->center_freq != sc->curchan->center_freq ||
1031 chan->hw_value != sc->curchan->hw_value) {
1032
1033 sc->curchan = chan;
1034 sc->curband = &sc->sbands[chan->band];
fa1c114f 1035
fa1c114f
JS		 1036 /*
1037 * To switch channels clear any pending DMA operations;
1038 * wait long enough for the RX fifo to drain, reset the
1039 * hardware at the new frequency, and then re-enable
1040 * the relevant bits of the h/w.
1041 */
d7dc1003 1042 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1043 }
1044
1045 return 0;
1046}
1047
1048static void
1049ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1050{
fa1c114f 1051 sc->curmode = mode;
d8ee398d 1052
400ec45a 1053 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1054 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1055 } else {
1056 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1057 }
fa1c114f
JS		 1058}
1059
1060static void
1061ath5k_mode_setup(struct ath5k_softc *sc)
1062{
1063 struct ath5k_hw *ah = sc->ah;
1064 u32 rfilt;
1065
1066 /* configure rx filter */
1067 rfilt = sc->filter_flags;
1068 ath5k_hw_set_rx_filter(ah, rfilt);
1069
1070 if (ath5k_hw_hasbssidmask(ah))
1071 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1072
1073 /* configure operational mode */
1074 ath5k_hw_set_opmode(ah);
1075
1076 ath5k_hw_set_mcast_filter(ah, 0, 0);
1077 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1078}
1079
d8ee398d 1080static inline int
63266a65
BR		 1081ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1082{
1083 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1084 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1085}
1086
fa1c114f
JS		 1087/***************\
1088* Buffers setup *
1089\***************/
1090
1091static int
1092ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1093{
1094 struct ath5k_hw *ah = sc->ah;
1095 struct sk_buff *skb = bf->skb;
1096 struct ath5k_desc *ds;
1097
1098 if (likely(skb == NULL)) {
1099 unsigned int off;
1100
1101 /*
1102 * Allocate buffer with headroom_needed space for the
1103 * fake physical layer header at the start.
1104 */
1105 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1106 if (unlikely(skb == NULL)) {
1107 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1108 sc->rxbufsize + sc->cachelsz - 1);
1109 return -ENOMEM;
1110 }
1111 /*
1112 * Cache-line-align. This is important (for the
1113 * 5210 at least) as not doing so causes bogus data
1114 * in rx'd frames.
1115 */
1116 off = ((unsigned long)skb->data) % sc->cachelsz;
1117 if (off != 0)
1118 skb_reserve(skb, sc->cachelsz - off);
1119
1120 bf->skb = skb;
1121 bf->skbaddr = pci_map_single(sc->pdev,
1122 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1123 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1124 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1125 dev_kfree_skb(skb);
1126 bf->skb = NULL;
1127 return -ENOMEM;
1128 }
1129 }
1130
1131 /*
1132 * Setup descriptors. For receive we always terminate
1133 * the descriptor list with a self-linked entry so we'll
1134 * not get overrun under high load (as can happen with a
1135 * 5212 when ANI processing enables PHY error frames).
1136 *
1137 * To insure the last descriptor is self-linked we create
1138 * each descriptor as self-linked and add it to the end. As
1139 * each additional descriptor is added the previous self-linked
1140 * entry is ``fixed'' naturally. This should be safe even
1141 * if DMA is happening. When processing RX interrupts we
1142 * never remove/process the last, self-linked, entry on the
1143 * descriptor list. This insures the hardware always has
1144 * someplace to write a new frame.
1145 */
1146 ds = bf->desc;
1147 ds->ds_link = bf->daddr; /* link to self */
1148 ds->ds_data = bf->skbaddr;
c6e387a2 1149 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1150 skb_tailroom(skb), /* buffer size */
1151 0);
1152
1153 if (sc->rxlink != NULL)
1154 *sc->rxlink = bf->daddr;
1155 sc->rxlink = &ds->ds_link;
1156 return 0;
1157}
1158
1159static int
e039fa4a 1160ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1161{
1162 struct ath5k_hw *ah = sc->ah;
1163 struct ath5k_txq *txq = sc->txq;
1164 struct ath5k_desc *ds = bf->desc;
1165 struct sk_buff *skb = bf->skb;
a888d52d 1166 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1167 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1168 struct ieee80211_rate *rate;
1169 unsigned int mrr_rate[3], mrr_tries[3];
1170 int i, ret;
fa1c114f
JS		 1171
1172 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1173
fa1c114f
JS		 1174 /* XXX endianness */
1175 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1176 PCI_DMA_TODEVICE);
1177
e039fa4a 1178 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1179 flags |= AR5K_TXDESC_NOACK;
1180
281c56dd 1181 pktlen = skb->len;
fa1c114f 1182
d0f09804 1183 if (info->control.hw_key) {
e039fa4a 1184 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1185 pktlen += info->control.hw_key->icv_len;
fa1c114f 1186 }
fa1c114f
JS		 1187 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1188 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1189 (sc->power_level * 2),
e039fa4a
JB		 1190 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1191 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1192 if (ret)
1193 goto err_unmap;
1194
2f7fe870
FF		 1195 memset(mrr_rate, 0, sizeof(mrr_rate));
1196 memset(mrr_tries, 0, sizeof(mrr_tries));
1197 for (i = 0; i < 3; i++) {
1198 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1199 if (!rate)
1200 break;
1201
1202 mrr_rate[i] = rate->hw_value;
1203 mrr_tries[i] = info->control.retries[i].limit;
1204 }
1205
1206 ah->ah_setup_mrr_tx_desc(ah, ds,
1207 mrr_rate[0], mrr_tries[0],
1208 mrr_rate[1], mrr_tries[1],
1209 mrr_rate[2], mrr_tries[2]);
1210
fa1c114f
JS		 1211 ds->ds_link = 0;
1212 ds->ds_data = bf->skbaddr;
1213
1214 spin_lock_bh(&txq->lock);
1215 list_add_tail(&bf->list, &txq->q);
57ffc589 1216 sc->tx_stats[txq->qnum].len++;
fa1c114f 1217 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1218 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1219 else /* no, so only link it */
1220 *txq->link = bf->daddr;
1221
1222 txq->link = &ds->ds_link;
c6e387a2 1223 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1224 mmiowb();
fa1c114f
JS		 1225 spin_unlock_bh(&txq->lock);
1226
1227 return 0;
1228err_unmap:
1229 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1230 return ret;
1231}
1232
1233/*******************\
1234* Descriptors setup *
1235\*******************/
1236
1237static int
1238ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1239{
1240 struct ath5k_desc *ds;
1241 struct ath5k_buf *bf;
1242 dma_addr_t da;
1243 unsigned int i;
1244 int ret;
1245
1246 /* allocate descriptors */
1247 sc->desc_len = sizeof(struct ath5k_desc) *
1248 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1249 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1250 if (sc->desc == NULL) {
1251 ATH5K_ERR(sc, "can't allocate descriptors\n");
1252 ret = -ENOMEM;
1253 goto err;
1254 }
1255 ds = sc->desc;
1256 da = sc->desc_daddr;
1257 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1258 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1259
1260 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1261 sizeof(struct ath5k_buf), GFP_KERNEL);
1262 if (bf == NULL) {
1263 ATH5K_ERR(sc, "can't allocate bufptr\n");
1264 ret = -ENOMEM;
1265 goto err_free;
1266 }
1267 sc->bufptr = bf;
1268
1269 INIT_LIST_HEAD(&sc->rxbuf);
1270 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1271 bf->desc = ds;
1272 bf->daddr = da;
1273 list_add_tail(&bf->list, &sc->rxbuf);
1274 }
1275
1276 INIT_LIST_HEAD(&sc->txbuf);
1277 sc->txbuf_len = ATH_TXBUF;
1278 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1279 da += sizeof(*ds)) {
1280 bf->desc = ds;
1281 bf->daddr = da;
1282 list_add_tail(&bf->list, &sc->txbuf);
1283 }
1284
1285 /* beacon buffer */
1286 bf->desc = ds;
1287 bf->daddr = da;
1288 sc->bbuf = bf;
1289
1290 return 0;
1291err_free:
1292 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1293err:
1294 sc->desc = NULL;
1295 return ret;
1296}
1297
1298static void
1299ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1300{
1301 struct ath5k_buf *bf;
1302
1303 ath5k_txbuf_free(sc, sc->bbuf);
1304 list_for_each_entry(bf, &sc->txbuf, list)
1305 ath5k_txbuf_free(sc, bf);
1306 list_for_each_entry(bf, &sc->rxbuf, list)
1307 ath5k_txbuf_free(sc, bf);
1308
1309 /* Free memory associated with all descriptors */
1310 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1311
1312 kfree(sc->bufptr);
1313 sc->bufptr = NULL;
1314}
1315
1316
1317
1318
1319
1320/**************\
1321* Queues setup *
1322\**************/
1323
1324static struct ath5k_txq *
1325ath5k_txq_setup(struct ath5k_softc *sc,
1326 int qtype, int subtype)
1327{
1328 struct ath5k_hw *ah = sc->ah;
1329 struct ath5k_txq *txq;
1330 struct ath5k_txq_info qi = {
1331 .tqi_subtype = subtype,
1332 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1333 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1334 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1335 };
1336 int qnum;
1337
1338 /*
1339 * Enable interrupts only for EOL and DESC conditions.
1340 * We mark tx descriptors to receive a DESC interrupt
1341 * when a tx queue gets deep; otherwise waiting for the
1342 * EOL to reap descriptors. Note that this is done to
1343 * reduce interrupt load and this only defers reaping
1344 * descriptors, never transmitting frames. Aside from
1345 * reducing interrupts this also permits more concurrency.
1346 * The only potential downside is if the tx queue backs
1347 * up in which case the top half of the kernel may backup
1348 * due to a lack of tx descriptors.
1349 */
1350 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1351 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1352 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1353 if (qnum < 0) {
1354 /*
1355 * NB: don't print a message, this happens
1356 * normally on parts with too few tx queues
1357 */
1358 return ERR_PTR(qnum);
1359 }
1360 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1361 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1362 qnum, ARRAY_SIZE(sc->txqs));
1363 ath5k_hw_release_tx_queue(ah, qnum);
1364 return ERR_PTR(-EINVAL);
1365 }
1366 txq = &sc->txqs[qnum];
1367 if (!txq->setup) {
1368 txq->qnum = qnum;
1369 txq->link = NULL;
1370 INIT_LIST_HEAD(&txq->q);
1371 spin_lock_init(&txq->lock);
1372 txq->setup = true;
1373 }
1374 return &sc->txqs[qnum];
1375}
1376
1377static int
1378ath5k_beaconq_setup(struct ath5k_hw *ah)
1379{
1380 struct ath5k_txq_info qi = {
1381 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1382 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1383 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1384 /* NB: for dynamic turbo, don't enable any other interrupts */
1385 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1386 };
1387
1388 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1389}
1390
1391static int
1392ath5k_beaconq_config(struct ath5k_softc *sc)
1393{
1394 struct ath5k_hw *ah = sc->ah;
1395 struct ath5k_txq_info qi;
1396 int ret;
1397
1398 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1399 if (ret)
1400 return ret;
05c914fe
JB		 1401 if (sc->opmode == NL80211_IFTYPE_AP ||
1402 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1403 /*
1404 * Always burst out beacon and CAB traffic
1405 * (aifs = cwmin = cwmax = 0)
1406 */
1407 qi.tqi_aifs = 0;
1408 qi.tqi_cw_min = 0;
1409 qi.tqi_cw_max = 0;
05c914fe 1410 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1411 /*
1412 * Adhoc mode; backoff between 0 and (2 * cw_min).
1413 */
1414 qi.tqi_aifs = 0;
1415 qi.tqi_cw_min = 0;
1416 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1417 }
1418
6d91e1d8
BR		 1419 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1420 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1421 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1422
c6e387a2 1423 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1424 if (ret) {
1425 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1426 "hardware queue!\n", __func__);
1427 return ret;
1428 }
1429
1430 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1431}
1432
1433static void
1434ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1435{
1436 struct ath5k_buf *bf, *bf0;
1437
1438 /*
1439 * NB: this assumes output has been stopped and
1440 * we do not need to block ath5k_tx_tasklet
1441 */
1442 spin_lock_bh(&txq->lock);
1443 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1444 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1445
1446 ath5k_txbuf_free(sc, bf);
1447
1448 spin_lock_bh(&sc->txbuflock);
57ffc589 1449 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1450 list_move_tail(&bf->list, &sc->txbuf);
1451 sc->txbuf_len++;
1452 spin_unlock_bh(&sc->txbuflock);
1453 }
1454 txq->link = NULL;
1455 spin_unlock_bh(&txq->lock);
1456}
1457
1458/*
1459 * Drain the transmit queues and reclaim resources.
1460 */
1461static void
1462ath5k_txq_cleanup(struct ath5k_softc *sc)
1463{
1464 struct ath5k_hw *ah = sc->ah;
1465 unsigned int i;
1466
1467 /* XXX return value */
1468 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1469 /* don't touch the hardware if marked invalid */
1470 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1471 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1472 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1473 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1474 if (sc->txqs[i].setup) {
1475 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1476 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1477 "link %p\n",
1478 sc->txqs[i].qnum,
c6e387a2 1479 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1480 sc->txqs[i].qnum),
1481 sc->txqs[i].link);
1482 }
1483 }
36d6825b 1484 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1485
1486 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1487 if (sc->txqs[i].setup)
1488 ath5k_txq_drainq(sc, &sc->txqs[i]);
1489}
1490
1491static void
1492ath5k_txq_release(struct ath5k_softc *sc)
1493{
1494 struct ath5k_txq *txq = sc->txqs;
1495 unsigned int i;
1496
1497 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1498 if (txq->setup) {
1499 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1500 txq->setup = false;
1501 }
1502}
1503
1504
1505
1506
1507/*************\
1508* RX Handling *
1509\*************/
1510
1511/*
1512 * Enable the receive h/w following a reset.
1513 */
1514static int
1515ath5k_rx_start(struct ath5k_softc *sc)
1516{
1517 struct ath5k_hw *ah = sc->ah;
1518 struct ath5k_buf *bf;
1519 int ret;
1520
1521 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1522
1523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1524 sc->cachelsz, sc->rxbufsize);
1525
1526 sc->rxlink = NULL;
1527
1528 spin_lock_bh(&sc->rxbuflock);
1529 list_for_each_entry(bf, &sc->rxbuf, list) {
1530 ret = ath5k_rxbuf_setup(sc, bf);
1531 if (ret != 0) {
1532 spin_unlock_bh(&sc->rxbuflock);
1533 goto err;
1534 }
1535 }
1536 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1537 spin_unlock_bh(&sc->rxbuflock);
1538
c6e387a2
NK		 1539 ath5k_hw_set_rxdp(ah, bf->daddr);
1540 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1541 ath5k_mode_setup(sc); /* set filters, etc. */
1542 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1543
1544 return 0;
1545err:
1546 return ret;
1547}
1548
1549/*
1550 * Disable the receive h/w in preparation for a reset.
1551 */
1552static void
1553ath5k_rx_stop(struct ath5k_softc *sc)
1554{
1555 struct ath5k_hw *ah = sc->ah;
1556
c6e387a2 1557 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1558 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1559 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1560
1561 ath5k_debug_printrxbuffs(sc, ah);
1562
1563 sc->rxlink = NULL; /* just in case */
1564}
1565
1566static unsigned int
1567ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1568 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1569{
1570 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1571 unsigned int keyix, hlen;
fa1c114f 1572
b47f407b
BR		 1573 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1574 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1575 return RX_FLAG_DECRYPTED;
1576
1577 /* Apparently when a default key is used to decrypt the packet
1578 the hw does not set the index used to decrypt. In such cases
1579 get the index from the packet. */
798ee985 1580 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1581 if (ieee80211_has_protected(hdr->frame_control) &&
1582 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1583 skb->len >= hlen + 4) {
fa1c114f
JS		 1584 keyix = skb->data[hlen + 3] >> 6;
1585
1586 if (test_bit(keyix, sc->keymap))
1587 return RX_FLAG_DECRYPTED;
1588 }
1589
1590 return 0;
1591}
1592
036cd1ec
BR		 1593
1594static void
6ba81c2c
BR		 1595ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1596 struct ieee80211_rx_status *rxs)
036cd1ec 1597{
6ba81c2c 1598 u64 tsf, bc_tstamp;
036cd1ec
BR		 1599 u32 hw_tu;
1600 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1601
24b56e70 1602 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1603 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1604 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1605 /*
6ba81c2c
BR		 1606 * Received an IBSS beacon with the same BSSID. Hardware *must*
1607 * have updated the local TSF. We have to work around various
1608 * hardware bugs, though...
036cd1ec 1609 */
6ba81c2c
BR		 1610 tsf = ath5k_hw_get_tsf64(sc->ah);
1611 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1612 hw_tu = TSF_TO_TU(tsf);
1613
1614 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1615 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1616 (unsigned long long)bc_tstamp,
1617 (unsigned long long)rxs->mactime,
1618 (unsigned long long)(rxs->mactime - bc_tstamp),
1619 (unsigned long long)tsf);
6ba81c2c
BR		 1620
1621 /*
1622 * Sometimes the HW will give us a wrong tstamp in the rx
1623 * status, causing the timestamp extension to go wrong.
1624 * (This seems to happen especially with beacon frames bigger
1625 * than 78 byte (incl. FCS))
1626 * But we know that the receive timestamp must be later than the
1627 * timestamp of the beacon since HW must have synced to that.
1628 *
1629 * NOTE: here we assume mactime to be after the frame was
1630 * received, not like mac80211 which defines it at the start.
1631 */
1632 if (bc_tstamp > rxs->mactime) {
036cd1ec 1633 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1634 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1635 (unsigned long long)rxs->mactime,
1636 (unsigned long long)tsf);
6ba81c2c 1637 rxs->mactime = tsf;
036cd1ec 1638 }
6ba81c2c
BR		 1639
1640 /*
1641 * Local TSF might have moved higher than our beacon timers,
1642 * in that case we have to update them to continue sending
1643 * beacons. This also takes care of synchronizing beacon sending
1644 * times with other stations.
1645 */
1646 if (hw_tu >= sc->nexttbtt)
1647 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1648 }
1649}
1650
1651
fa1c114f
JS		 1652static void
1653ath5k_tasklet_rx(unsigned long data)
1654{
1655 struct ieee80211_rx_status rxs = {};
b47f407b 1656 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1657 struct sk_buff *skb;
1658 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1659 struct ath5k_buf *bf, *bf_last;
fa1c114f 1660 struct ath5k_desc *ds;
fa1c114f
JS		 1661 int ret;
1662 int hdrlen;
1663 int pad;
1664
1665 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1666 if (list_empty(&sc->rxbuf)) {
1667 ATH5K_WARN(sc, "empty rx buf pool\n");
1668 goto unlock;
1669 }
1670 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1671 do {
d6894b5b
BC		 1672 rxs.flag = 0;
1673
fa1c114f
JS		 1674 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1675 BUG_ON(bf->skb == NULL);
1676 skb = bf->skb;
1677 ds = bf->desc;
1678
3a0f2c87
JS		 1679 /*
1680 * last buffer must not be freed to ensure proper hardware
1681 * function. When the hardware finishes also a packet next to
1682 * it, we are sure, it doesn't use it anymore and we can go on.
1683 */
1684 if (bf_last == bf)
1685 bf->flags |= 1;
1686 if (bf->flags) {
1687 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1688 struct ath5k_buf, list);
1689 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1690 &rs);
1691 if (ret)
1692 break;
1693 bf->flags &= ~1;
1694 /* skip the overwritten one (even status is martian) */
1695 goto next;
1696 }
fa1c114f 1697
b47f407b 1698 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1699 if (unlikely(ret == -EINPROGRESS))
1700 break;
1701 else if (unlikely(ret)) {
1702 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1703 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1704 return;
1705 }
1706
b47f407b 1707 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1708 ATH5K_WARN(sc, "unsupported jumbo\n");
1709 goto next;
1710 }
1711
b47f407b
BR		 1712 if (unlikely(rs.rs_status)) {
1713 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1714 goto next;
b47f407b 1715 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1716 /*
1717 * Decrypt error. If the error occurred
1718 * because there was no hardware key, then
1719 * let the frame through so the upper layers
1720 * can process it. This is necessary for 5210
1721 * parts which have no way to setup a ``clear''
1722 * key cache entry.
1723 *
1724 * XXX do key cache faulting
1725 */
b47f407b
BR		 1726 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1727 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1728 goto accept;
1729 }
b47f407b 1730 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1731 rxs.flag |= RX_FLAG_MMIC_ERROR;
1732 goto accept;
1733 }
1734
1735 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1736 if ((rs.rs_status &
1737 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1738 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1739 goto next;
1740 }
1741accept:
fa1c114f
JS		 1742 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1743 PCI_DMA_FROMDEVICE);
1744 bf->skb = NULL;
1745
b47f407b 1746 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1747
1748 /*
1749 * the hardware adds a padding to 4 byte boundaries between
1750 * the header and the payload data if the header length is
1751 * not multiples of 4 - remove it
1752 */
1753 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1754 if (hdrlen & 3) {
1755 pad = hdrlen % 4;
1756 memmove(skb->data + pad, skb->data, hdrlen);
1757 skb_pull(skb, pad);
1758 }
1759
c0e1899b
BR		 1760 /*
1761 * always extend the mac timestamp, since this information is
1762 * also needed for proper IBSS merging.
1763 *
1764 * XXX: it might be too late to do it here, since rs_tstamp is
1765 * 15bit only. that means TSF extension has to be done within
1766 * 32768usec (about 32ms). it might be necessary to move this to
1767 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1768 *
1769 * Unfortunately we don't know when the hardware takes the rx
1770 * timestamp (beginning of phy frame, data frame, end of rx?).
1771 * The only thing we know is that it is hardware specific...
1772 * On AR5213 it seems the rx timestamp is at the end of the
1773 * frame, but i'm not sure.
1774 *
1775 * NOTE: mac80211 defines mactime at the beginning of the first
1776 * data symbol. Since we don't have any time references it's
1777 * impossible to comply to that. This affects IBSS merge only
1778 * right now, so it's not too bad...
c0e1899b 1779 */
b47f407b 1780 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1781 rxs.flag |= RX_FLAG_TSFT;
1782
d8ee398d
LR		 1783 rxs.freq = sc->curchan->center_freq;
1784 rxs.band = sc->curband->band;
fa1c114f 1785
fa1c114f 1786 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1787 rxs.signal = rxs.noise + rs.rs_rssi;
1788 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1789
b47f407b
BR		 1790 rxs.antenna = rs.rs_antenna;
1791 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1792 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1793
06303352
BR		 1794 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1795 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1796 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1797
fa1c114f
JS		 1798 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1799
036cd1ec 1800 /* check beacons in IBSS mode */
05c914fe 1801 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1802 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1803
fa1c114f 1804 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1805next:
1806 list_move_tail(&bf->list, &sc->rxbuf);
1807 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1808unlock:
fa1c114f
JS		 1809 spin_unlock(&sc->rxbuflock);
1810}
1811
1812
1813
1814
1815/*************\
1816* TX Handling *
1817\*************/
1818
1819static void
1820ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1821{
b47f407b 1822 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1823 struct ath5k_buf *bf, *bf0;
1824 struct ath5k_desc *ds;
1825 struct sk_buff *skb;
e039fa4a 1826 struct ieee80211_tx_info *info;
2f7fe870 1827 int i, ret;
fa1c114f
JS		 1828
1829 spin_lock(&txq->lock);
1830 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1831 ds = bf->desc;
1832
b47f407b 1833 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1834 if (unlikely(ret == -EINPROGRESS))
1835 break;
1836 else if (unlikely(ret)) {
1837 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1838 ret, txq->qnum);
1839 break;
1840 }
1841
1842 skb = bf->skb;
a888d52d 1843 info = IEEE80211_SKB_CB(skb);
fa1c114f 1844 bf->skb = NULL;
e039fa4a 1845
fa1c114f
JS		 1846 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1847 PCI_DMA_TODEVICE);
1848
2f7fe870
FF		 1849 memset(&info->status, 0, sizeof(info->status));
1850 info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
1851 ts.ts_rate[ts.ts_final_idx]);
1852 info->status.retry_count = ts.ts_longretry;
1853
1854 for (i = 0; i < 4; i++) {
1855 struct ieee80211_tx_altrate *r =
1856 &info->status.retries[i];
1857
1858 if (ts.ts_rate[i]) {
1859 r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1860 r->limit = ts.ts_retry[i];
1861 } else {
1862 r->rate_idx = -1;
1863 r->limit = 0;
1864 }
1865 }
1866
1867 info->status.excessive_retries = 0;
b47f407b 1868 if (unlikely(ts.ts_status)) {
fa1c114f 1869 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1870 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1871 info->status.excessive_retries = 1;
b47f407b 1872 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1873 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1874 } else {
e039fa4a
JB		 1875 info->flags |= IEEE80211_TX_STAT_ACK;
1876 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1877 }
1878
e039fa4a 1879 ieee80211_tx_status(sc->hw, skb);
57ffc589 1880 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1881
1882 spin_lock(&sc->txbuflock);
57ffc589 1883 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1884 list_move_tail(&bf->list, &sc->txbuf);
1885 sc->txbuf_len++;
1886 spin_unlock(&sc->txbuflock);
1887 }
1888 if (likely(list_empty(&txq->q)))
1889 txq->link = NULL;
1890 spin_unlock(&txq->lock);
1891 if (sc->txbuf_len > ATH_TXBUF / 5)
1892 ieee80211_wake_queues(sc->hw);
1893}
1894
1895static void
1896ath5k_tasklet_tx(unsigned long data)
1897{
1898 struct ath5k_softc *sc = (void *)data;
1899
1900 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1901}
1902
1903
fa1c114f
JS		 1904/*****************\
1905* Beacon handling *
1906\*****************/
1907
1908/*
1909 * Setup the beacon frame for transmit.
1910 */
1911static int
e039fa4a 1912ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1913{
1914 struct sk_buff *skb = bf->skb;
a888d52d 1915 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1916 struct ath5k_hw *ah = sc->ah;
1917 struct ath5k_desc *ds;
1918 int ret, antenna = 0;
1919 u32 flags;
1920
1921 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1922 PCI_DMA_TODEVICE);
1923 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1924 "skbaddr %llx\n", skb, skb->data, skb->len,
1925 (unsigned long long)bf->skbaddr);
8d8bb39b 1926 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1927 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1928 return -EIO;
1929 }
1930
1931 ds = bf->desc;
1932
1933 flags = AR5K_TXDESC_NOACK;
05c914fe 1934 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1935 ds->ds_link = bf->daddr; /* self-linked */
1936 flags |= AR5K_TXDESC_VEOL;
1937 /*
1938 * Let hardware handle antenna switching if txantenna is not set
1939 */
1940 } else {
1941 ds->ds_link = 0;
1942 /*
1943 * Switch antenna every 4 beacons if txantenna is not set
1944 * XXX assumes two antennas
1945 */
1946 if (antenna == 0)
1947 antenna = sc->bsent & 4 ? 2 : 1;
1948 }
1949
1950 ds->ds_data = bf->skbaddr;
281c56dd 1951 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1952 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1953 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1954 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1955 1, AR5K_TXKEYIX_INVALID,
400ec45a 1956 antenna, flags, 0, 0);
fa1c114f
JS		 1957 if (ret)
1958 goto err_unmap;
1959
1960 return 0;
1961err_unmap:
1962 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1963 return ret;
1964}
1965
1966/*
1967 * Transmit a beacon frame at SWBA. Dynamic updates to the
1968 * frame contents are done as needed and the slot time is
1969 * also adjusted based on current state.
1970 *
1971 * this is usually called from interrupt context (ath5k_intr())
1972 * but also from ath5k_beacon_config() in IBSS mode which in turn
1973 * can be called from a tasklet and user context
1974 */
1975static void
1976ath5k_beacon_send(struct ath5k_softc *sc)
1977{
1978 struct ath5k_buf *bf = sc->bbuf;
1979 struct ath5k_hw *ah = sc->ah;
1980
be9b7259 1981 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1982
05c914fe
JB		 1983 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1984 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 1985 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1986 return;
1987 }
1988 /*
1989 * Check if the previous beacon has gone out. If
1990 * not don't don't try to post another, skip this
1991 * period and wait for the next. Missed beacons
1992 * indicate a problem and should not occur. If we
1993 * miss too many consecutive beacons reset the device.
1994 */
1995 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1996 sc->bmisscount++;
be9b7259 1997 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1998 "missed %u consecutive beacons\n", sc->bmisscount);
1999 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2000 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2001 "stuck beacon time (%u missed)\n",
2002 sc->bmisscount);
2003 tasklet_schedule(&sc->restq);
2004 }
2005 return;
2006 }
2007 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2008 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2009 "resume beacon xmit after %u misses\n",
2010 sc->bmisscount);
2011 sc->bmisscount = 0;
2012 }
2013
2014 /*
2015 * Stop any current dma and put the new frame on the queue.
2016 * This should never fail since we check above that no frames
2017 * are still pending on the queue.
2018 */
2019 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2020 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2021 /* NB: hw still stops DMA, so proceed */
2022 }
fa1c114f 2023
c6e387a2
NK		 2024 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2025 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2026 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2027 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2028
2029 sc->bsent++;
2030}
2031
2032
9804b98d
BR		 2033/**
2034 * ath5k_beacon_update_timers - update beacon timers
2035 *
2036 * @sc: struct ath5k_softc pointer we are operating on
2037 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2038 * beacon timer update based on the current HW TSF.
2039 *
2040 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2041 * of a received beacon or the current local hardware TSF and write it to the
2042 * beacon timer registers.
2043 *
2044 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2045 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2046 * when we otherwise know we have to update the timers, but we keep it in this
2047 * function to have it all together in one place.
2048 */
fa1c114f 2049static void
9804b98d 2050ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2051{
2052 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2053 u32 nexttbtt, intval, hw_tu, bc_tu;
2054 u64 hw_tsf;
fa1c114f
JS		 2055
2056 intval = sc->bintval & AR5K_BEACON_PERIOD;
2057 if (WARN_ON(!intval))
2058 return;
2059
9804b98d
BR		 2060 /* beacon TSF converted to TU */
2061 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2062
9804b98d
BR		 2063 /* current TSF converted to TU */
2064 hw_tsf = ath5k_hw_get_tsf64(ah);
2065 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2066
9804b98d
BR		 2067#define FUDGE 3
2068 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2069 if (bc_tsf == -1) {
2070 /*
2071 * no beacons received, called internally.
2072 * just need to refresh timers based on HW TSF.
2073 */
2074 nexttbtt = roundup(hw_tu + FUDGE, intval);
2075 } else if (bc_tsf == 0) {
2076 /*
2077 * no beacon received, probably called by ath5k_reset_tsf().
2078 * reset TSF to start with 0.
2079 */
2080 nexttbtt = intval;
2081 intval |= AR5K_BEACON_RESET_TSF;
2082 } else if (bc_tsf > hw_tsf) {
2083 /*
2084 * beacon received, SW merge happend but HW TSF not yet updated.
2085 * not possible to reconfigure timers yet, but next time we
2086 * receive a beacon with the same BSSID, the hardware will
2087 * automatically update the TSF and then we need to reconfigure
2088 * the timers.
2089 */
2090 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2091 "need to wait for HW TSF sync\n");
2092 return;
2093 } else {
2094 /*
2095 * most important case for beacon synchronization between STA.
2096 *
2097 * beacon received and HW TSF has been already updated by HW.
2098 * update next TBTT based on the TSF of the beacon, but make
2099 * sure it is ahead of our local TSF timer.
2100 */
2101 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2102 }
2103#undef FUDGE
fa1c114f 2104
036cd1ec
BR		 2105 sc->nexttbtt = nexttbtt;
2106
fa1c114f 2107 intval |= AR5K_BEACON_ENA;
fa1c114f 2108 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2109
2110 /*
2111 * debugging output last in order to preserve the time critical aspect
2112 * of this function
2113 */
2114 if (bc_tsf == -1)
2115 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2116 "reconfigured timers based on HW TSF\n");
2117 else if (bc_tsf == 0)
2118 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2119 "reset HW TSF and timers\n");
2120 else
2121 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2122 "updated timers based on beacon TSF\n");
2123
2124 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2125 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2126 (unsigned long long) bc_tsf,
2127 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2128 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2129 intval & AR5K_BEACON_PERIOD,
2130 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2131 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2132}
2133
2134
036cd1ec
BR		 2135/**
2136 * ath5k_beacon_config - Configure the beacon queues and interrupts
2137 *
2138 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2139 *
2140 * When operating in station mode we want to receive a BMISS interrupt when we
2141 * stop seeing beacons from the AP we've associated with so we can look for
2142 * another AP to associate with.
2143 *
036cd1ec 2144 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2145 * interrupts to detect TSF updates only.
036cd1ec
BR		 2146 *
2147 * AP mode is missing.
fa1c114f
JS		 2148 */
2149static void
2150ath5k_beacon_config(struct ath5k_softc *sc)
2151{
2152 struct ath5k_hw *ah = sc->ah;
2153
c6e387a2 2154 ath5k_hw_set_imr(ah, 0);
fa1c114f 2155 sc->bmisscount = 0;
dc1968e7 2156 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2157
05c914fe 2158 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2159 sc->imask |= AR5K_INT_BMISS;
05c914fe 2160 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2161 /*
036cd1ec
BR		 2162 * In IBSS mode we use a self-linked tx descriptor and let the
2163 * hardware send the beacons automatically. We have to load it
fa1c114f 2164 * only once here.
036cd1ec 2165 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2166 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2167 */
2168 ath5k_beaconq_config(sc);
fa1c114f 2169
036cd1ec
BR		 2170 sc->imask |= AR5K_INT_SWBA;
2171
00482973
JS		 2172 if (ath5k_hw_hasveol(ah)) {
2173 spin_lock(&sc->block);
fa1c114f 2174 ath5k_beacon_send(sc);
00482973
JS		 2175 spin_unlock(&sc->block);
2176 }
fa1c114f
JS		 2177 }
2178 /* TODO else AP */
2179
c6e387a2 2180 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2181}
2182
2183
2184/********************\
2185* Interrupt handling *
2186\********************/
2187
2188static int
8bdd5b9c 2189ath5k_init(struct ath5k_softc *sc, bool is_resume)
fa1c114f 2190{
bc1b32d6
EO		 2191 struct ath5k_hw *ah = sc->ah;
2192 int ret, i;
fa1c114f
JS		 2193
2194 mutex_lock(&sc->lock);
2195
8bdd5b9c
BC		 2196 if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2197 goto out_ok;
2198
2199 __clear_bit(ATH_STAT_STARTED, sc->status);
2200
fa1c114f
JS		 2201 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2202
2203 /*
2204 * Stop anything previously setup. This is safe
2205 * no matter this is the first time through or not.
2206 */
2207 ath5k_stop_locked(sc);
2208
2209 /*
2210 * The basic interface to setting the hardware in a good
2211 * state is ``reset''. On return the hardware is known to
2212 * be powered up and with interrupts disabled. This must
2213 * be followed by initialization of the appropriate bits
2214 * and then setup of the interrupt mask.
2215 */
d8ee398d
LR		 2216 sc->curchan = sc->hw->conf.channel;
2217 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2218 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2219 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2220 AR5K_INT_MIB;
d7dc1003
JS		 2221 ret = ath5k_reset(sc, false, false);
2222 if (ret)
2223 goto done;
fa1c114f 2224
bc1b32d6
EO		 2225 /*
2226 * Reset the key cache since some parts do not reset the
2227 * contents on initial power up or resume from suspend.
2228 */
2229 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2230 ath5k_hw_reset_key(ah, i);
2231
8bdd5b9c
BC		 2232 __set_bit(ATH_STAT_STARTED, sc->status);
2233
fa1c114f 2234 /* Set ack to be sent at low bit-rates */
bc1b32d6 2235 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2236
2237 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2238 msecs_to_jiffies(ath5k_calinterval * 1000)));
2239
8bdd5b9c 2240out_ok:
fa1c114f
JS		 2241 ret = 0;
2242done:
274c7c36 2243 mmiowb();
fa1c114f
JS		 2244 mutex_unlock(&sc->lock);
2245 return ret;
2246}
2247
2248static int
2249ath5k_stop_locked(struct ath5k_softc *sc)
2250{
2251 struct ath5k_hw *ah = sc->ah;
2252
2253 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2254 test_bit(ATH_STAT_INVALID, sc->status));
2255
2256 /*
2257 * Shutdown the hardware and driver:
2258 * stop output from above
2259 * disable interrupts
2260 * turn off timers
2261 * turn off the radio
2262 * clear transmit machinery
2263 * clear receive machinery
2264 * drain and release tx queues
2265 * reclaim beacon resources
2266 * power down hardware
2267 *
2268 * Note that some of this work is not possible if the
2269 * hardware is gone (invalid).
2270 */
2271 ieee80211_stop_queues(sc->hw);
2272
2273 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2274 ath5k_led_off(sc);
c6e387a2 2275 ath5k_hw_set_imr(ah, 0);
274c7c36 2276 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2277 }
2278 ath5k_txq_cleanup(sc);
2279 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2280 ath5k_rx_stop(sc);
2281 ath5k_hw_phy_disable(ah);
2282 } else
2283 sc->rxlink = NULL;
2284
2285 return 0;
2286}
2287
2288/*
2289 * Stop the device, grabbing the top-level lock to protect
2290 * against concurrent entry through ath5k_init (which can happen
2291 * if another thread does a system call and the thread doing the
2292 * stop is preempted).
2293 */
2294static int
8bdd5b9c 2295ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
fa1c114f
JS		 2296{
2297 int ret;
2298
2299 mutex_lock(&sc->lock);
2300 ret = ath5k_stop_locked(sc);
2301 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2302 /*
2303 * Set the chip in full sleep mode. Note that we are
2304 * careful to do this only when bringing the interface
2305 * completely to a stop. When the chip is in this state
2306 * it must be carefully woken up or references to
2307 * registers in the PCI clock domain may freeze the bus
2308 * (and system). This varies by chip and is mostly an
2309 * issue with newer parts that go to sleep more quickly.
2310 */
2311 if (sc->ah->ah_mac_srev >= 0x78) {
2312 /*
2313 * XXX
2314 * don't put newer MAC revisions > 7.8 to sleep because
2315 * of the above mentioned problems
2316 */
2317 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2318 "not putting device to sleep\n");
2319 } else {
2320 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2321 "putting device to full sleep\n");
2322 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2323 }
2324 }
2325 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c
BC		 2326 if (!is_suspend)
2327 __clear_bit(ATH_STAT_STARTED, sc->status);
2328
274c7c36 2329 mmiowb();
fa1c114f
JS		 2330 mutex_unlock(&sc->lock);
2331
2332 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2333 tasklet_kill(&sc->rxtq);
2334 tasklet_kill(&sc->txtq);
2335 tasklet_kill(&sc->restq);
fa1c114f
JS		 2336
2337 return ret;
2338}
2339
2340static irqreturn_t
2341ath5k_intr(int irq, void *dev_id)
2342{
2343 struct ath5k_softc *sc = dev_id;
2344 struct ath5k_hw *ah = sc->ah;
2345 enum ath5k_int status;
2346 unsigned int counter = 1000;
2347
2348 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2349 !ath5k_hw_is_intr_pending(ah)))
2350 return IRQ_NONE;
2351
2352 do {
2353 /*
2354 * Figure out the reason(s) for the interrupt. Note
2355 * that get_isr returns a pseudo-ISR that may include
2356 * bits we haven't explicitly enabled so we mask the
2357 * value to insure we only process bits we requested.
2358 */
2359 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2360 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2361 status, sc->imask);
2362 status &= sc->imask; /* discard unasked for bits */
2363 if (unlikely(status & AR5K_INT_FATAL)) {
2364 /*
2365 * Fatal errors are unrecoverable.
2366 * Typically these are caused by DMA errors.
2367 */
2368 tasklet_schedule(&sc->restq);
2369 } else if (unlikely(status & AR5K_INT_RXORN)) {
2370 tasklet_schedule(&sc->restq);
2371 } else {
2372 if (status & AR5K_INT_SWBA) {
2373 /*
2374 * Software beacon alert--time to send a beacon.
2375 * Handle beacon transmission directly; deferring
2376 * this is too slow to meet timing constraints
2377 * under load.
036cd1ec
BR		 2378 *
2379 * In IBSS mode we use this interrupt just to
2380 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2381 * transmission time) in order to detect wether
2382 * automatic TSF updates happened.
fa1c114f 2383 */
05c914fe 2384 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2385 /* XXX: only if VEOL suppported */
2386 u64 tsf = ath5k_hw_get_tsf64(ah);
2387 sc->nexttbtt += sc->bintval;
2388 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2389 "SWBA nexttbtt: %x hw_tu: %x "
2390 "TSF: %llx\n",
2391 sc->nexttbtt,
2392 TSF_TO_TU(tsf),
2393 (unsigned long long) tsf);
036cd1ec 2394 } else {
00482973 2395 spin_lock(&sc->block);
036cd1ec 2396 ath5k_beacon_send(sc);
00482973 2397 spin_unlock(&sc->block);
036cd1ec 2398 }
fa1c114f
JS		 2399 }
2400 if (status & AR5K_INT_RXEOL) {
2401 /*
2402 * NB: the hardware should re-read the link when
2403 * RXE bit is written, but it doesn't work at
2404 * least on older hardware revs.
2405 */
2406 sc->rxlink = NULL;
2407 }
2408 if (status & AR5K_INT_TXURN) {
2409 /* bump tx trigger level */
2410 ath5k_hw_update_tx_triglevel(ah, true);
2411 }
2412 if (status & AR5K_INT_RX)
2413 tasklet_schedule(&sc->rxtq);
2414 if (status & AR5K_INT_TX)
2415 tasklet_schedule(&sc->txtq);
2416 if (status & AR5K_INT_BMISS) {
2417 }
2418 if (status & AR5K_INT_MIB) {
194828a2
NK		 2419 /*
2420 * These stats are also used for ANI i think
2421 * so how about updating them more often ?
2422 */
2423 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2424 }
2425 }
2426 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2427
2428 if (unlikely(!counter))
2429 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2430
2431 return IRQ_HANDLED;
2432}
2433
2434static void
2435ath5k_tasklet_reset(unsigned long data)
2436{
2437 struct ath5k_softc *sc = (void *)data;
2438
d7dc1003 2439 ath5k_reset_wake(sc);
fa1c114f
JS		 2440}
2441
2442/*
2443 * Periodically recalibrate the PHY to account
2444 * for temperature/environment changes.
2445 */
2446static void
2447ath5k_calibrate(unsigned long data)
2448{
2449 struct ath5k_softc *sc = (void *)data;
2450 struct ath5k_hw *ah = sc->ah;
2451
2452 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2453 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2454 sc->curchan->hw_value);
fa1c114f
JS		 2455
2456 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2457 /*
2458 * Rfgain is out of bounds, reset the chip
2459 * to load new gain values.
2460 */
2461 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2462 ath5k_reset_wake(sc);
fa1c114f
JS		 2463 }
2464 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2465 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2466 ieee80211_frequency_to_channel(
2467 sc->curchan->center_freq));
fa1c114f
JS		 2468
2469 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2470 msecs_to_jiffies(ath5k_calinterval * 1000)));
2471}
2472
2473
2474
2475/***************\
2476* LED functions *
2477\***************/
2478
2479static void
3a078876 2480ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2481{
3a078876
BC		 2482 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2483 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2484 ath5k_led_off(sc);
fa1c114f
JS		 2485 }
2486}
2487
fa1c114f 2488static void
3a078876 2489ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2490{
3a078876
BC		 2491 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2492 return;
fa1c114f 2493 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2494}
2495
2496static void
3a078876 2497ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2498{
3a078876 2499 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2500 return;
3a078876
BC		 2501 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2502}
2503
2504static void
2505ath5k_led_brightness_set(struct led_classdev *led_dev,
2506 enum led_brightness brightness)
2507{
2508 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2509 led_dev);
2510
2511 if (brightness == LED_OFF)
2512 ath5k_led_off(led->sc);
2513 else
2514 ath5k_led_on(led->sc);
2515}
2516
2517static int
2518ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2519 const char *name, char *trigger)
2520{
2521 int err;
2522
2523 led->sc = sc;
2524 strncpy(led->name, name, sizeof(led->name));
2525 led->led_dev.name = led->name;
2526 led->led_dev.default_trigger = trigger;
2527 led->led_dev.brightness_set = ath5k_led_brightness_set;
2528
2529 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2530 if (err)
2531 {
2532 ATH5K_WARN(sc, "could not register LED %s\n", name);
2533 led->sc = NULL;
fa1c114f 2534 }
3a078876 2535 return err;
fa1c114f
JS		 2536}
2537
3a078876
BC		 2538static void
2539ath5k_unregister_led(struct ath5k_led *led)
2540{
2541 if (!led->sc)
2542 return;
2543 led_classdev_unregister(&led->led_dev);
2544 ath5k_led_off(led->sc);
2545 led->sc = NULL;
2546}
2547
2548static void
2549ath5k_unregister_leds(struct ath5k_softc *sc)
2550{
2551 ath5k_unregister_led(&sc->rx_led);
2552 ath5k_unregister_led(&sc->tx_led);
2553}
2554
2555
2556static int
2557ath5k_init_leds(struct ath5k_softc *sc)
2558{
2559 int ret = 0;
2560 struct ieee80211_hw *hw = sc->hw;
2561 struct pci_dev *pdev = sc->pdev;
2562 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2563
3a078876
BC		 2564 /*
2565 * Auto-enable soft led processing for IBM cards and for
2566 * 5211 minipci cards.
2567 */
2568 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2569 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2570 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2571 sc->led_pin = 0;
734b5aa9 2572 sc->led_on = 0; /* active low */
3a078876
BC		 2573 }
2574 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2575 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2576 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2577 sc->led_pin = 1;
734b5aa9 2578 sc->led_on = 1; /* active high */
3a078876
BC		 2579 }
2580 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2581 goto out;
2582
2583 ath5k_led_enable(sc);
2584
2585 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2586 ret = ath5k_register_led(sc, &sc->rx_led, name,
2587 ieee80211_get_rx_led_name(hw));
2588 if (ret)
2589 goto out;
2590
2591 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2592 ret = ath5k_register_led(sc, &sc->tx_led, name,
2593 ieee80211_get_tx_led_name(hw));
2594out:
2595 return ret;
2596}
fa1c114f
JS		 2597
2598
2599/********************\
2600* Mac80211 functions *
2601\********************/
2602
2603static int
e039fa4a 2604ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2605{
2606 struct ath5k_softc *sc = hw->priv;
2607 struct ath5k_buf *bf;
2608 unsigned long flags;
2609 int hdrlen;
2610 int pad;
2611
2612 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2613
05c914fe 2614 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2615 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2616
2617 /*
2618 * the hardware expects the header padded to 4 byte boundaries
2619 * if this is not the case we add the padding after the header
2620 */
2621 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2622 if (hdrlen & 3) {
2623 pad = hdrlen % 4;
2624 if (skb_headroom(skb) < pad) {
2625 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2626 " headroom to pad %d\n", hdrlen, pad);
2627 return -1;
2628 }
2629 skb_push(skb, pad);
2630 memmove(skb->data, skb->data+pad, hdrlen);
2631 }
2632
fa1c114f
JS		 2633 spin_lock_irqsave(&sc->txbuflock, flags);
2634 if (list_empty(&sc->txbuf)) {
2635 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2636 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2637 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2638 return -1;
2639 }
2640 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2641 list_del(&bf->list);
2642 sc->txbuf_len--;
2643 if (list_empty(&sc->txbuf))
2644 ieee80211_stop_queues(hw);
2645 spin_unlock_irqrestore(&sc->txbuflock, flags);
2646
2647 bf->skb = skb;
2648
e039fa4a 2649 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2650 bf->skb = NULL;
2651 spin_lock_irqsave(&sc->txbuflock, flags);
2652 list_add_tail(&bf->list, &sc->txbuf);
2653 sc->txbuf_len++;
2654 spin_unlock_irqrestore(&sc->txbuflock, flags);
2655 dev_kfree_skb_any(skb);
2656 return 0;
2657 }
2658
2659 return 0;
2660}
2661
2662static int
d7dc1003 2663ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2664{
fa1c114f
JS		 2665 struct ath5k_hw *ah = sc->ah;
2666 int ret;
2667
2668 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2669
d7dc1003 2670 if (stop) {
c6e387a2 2671 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2672 ath5k_txq_cleanup(sc);
2673 ath5k_rx_stop(sc);
2674 }
fa1c114f 2675 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2676 if (ret) {
fa1c114f
JS		 2677 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2678 goto err;
2679 }
d7dc1003
JS		 2680
2681 /*
2682 * This is needed only to setup initial state
2683 * but it's best done after a reset.
2684 */
fa1c114f
JS		 2685 ath5k_hw_set_txpower_limit(sc->ah, 0);
2686
2687 ret = ath5k_rx_start(sc);
d7dc1003 2688 if (ret) {
fa1c114f
JS		 2689 ATH5K_ERR(sc, "can't start recv logic\n");
2690 goto err;
2691 }
d7dc1003 2692
fa1c114f 2693 /*
d7dc1003
JS		 2694 * Change channels and update the h/w rate map if we're switching;
2695 * e.g. 11a to 11b/g.
2696 *
2697 * We may be doing a reset in response to an ioctl that changes the
2698 * channel so update any state that might change as a result.
fa1c114f
JS		 2699 *
2700 * XXX needed?
2701 */
2702/* ath5k_chan_change(sc, c); */
fa1c114f 2703
d7dc1003
JS		 2704 ath5k_beacon_config(sc);
2705 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2706
2707 return 0;
2708err:
2709 return ret;
2710}
2711
d7dc1003
JS		 2712static int
2713ath5k_reset_wake(struct ath5k_softc *sc)
2714{
2715 int ret;
2716
2717 ret = ath5k_reset(sc, true, true);
2718 if (!ret)
2719 ieee80211_wake_queues(sc->hw);
2720
2721 return ret;
2722}
2723
fa1c114f
JS		 2724static int ath5k_start(struct ieee80211_hw *hw)
2725{
8bdd5b9c 2726 return ath5k_init(hw->priv, false);
fa1c114f
JS		 2727}
2728
2729static void ath5k_stop(struct ieee80211_hw *hw)
2730{
8bdd5b9c 2731 ath5k_stop_hw(hw->priv, false);
fa1c114f
JS		 2732}
2733
2734static int ath5k_add_interface(struct ieee80211_hw *hw,
2735 struct ieee80211_if_init_conf *conf)
2736{
2737 struct ath5k_softc *sc = hw->priv;
2738 int ret;
2739
2740 mutex_lock(&sc->lock);
32bfd35d 2741 if (sc->vif) {
fa1c114f
JS		 2742 ret = 0;
2743 goto end;
2744 }
2745
32bfd35d 2746 sc->vif = conf->vif;
fa1c114f
JS		 2747
2748 switch (conf->type) {
05c914fe
JB		 2749 case NL80211_IFTYPE_STATION:
2750 case NL80211_IFTYPE_ADHOC:
2751 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2752 sc->opmode = conf->type;
2753 break;
2754 default:
2755 ret = -EOPNOTSUPP;
2756 goto end;
2757 }
67d2e2df
JS		 2758
2759 /* Set to a reasonable value. Note that this will
2760 * be set to mac80211's value at ath5k_config(). */
2761 sc->bintval = 1000;
2762
fa1c114f
JS		 2763 ret = 0;
2764end:
2765 mutex_unlock(&sc->lock);
2766 return ret;
2767}
2768
2769static void
2770ath5k_remove_interface(struct ieee80211_hw *hw,
2771 struct ieee80211_if_init_conf *conf)
2772{
2773 struct ath5k_softc *sc = hw->priv;
2774
2775 mutex_lock(&sc->lock);
32bfd35d 2776 if (sc->vif != conf->vif)
fa1c114f
JS		 2777 goto end;
2778
32bfd35d 2779 sc->vif = NULL;
fa1c114f
JS		 2780end:
2781 mutex_unlock(&sc->lock);
2782}
2783
d8ee398d
LR		 2784/*
2785 * TODO: Phy disable/diversity etc
2786 */
fa1c114f
JS		 2787static int
2788ath5k_config(struct ieee80211_hw *hw,
2789 struct ieee80211_conf *conf)
2790{
2791 struct ath5k_softc *sc = hw->priv;
2792
e535c1ac 2793 sc->bintval = conf->beacon_int;
d8ee398d 2794 sc->power_level = conf->power_level;
fa1c114f 2795
d8ee398d 2796 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2797}
2798
2799static int
32bfd35d 2800ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2801 struct ieee80211_if_conf *conf)
2802{
2803 struct ath5k_softc *sc = hw->priv;
2804 struct ath5k_hw *ah = sc->ah;
2805 int ret;
2806
fa1c114f 2807 mutex_lock(&sc->lock);
32bfd35d 2808 if (sc->vif != vif) {
fa1c114f
JS		 2809 ret = -EIO;
2810 goto unlock;
2811 }
2812 if (conf->bssid) {
2813 /* Cache for later use during resets */
2814 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2815 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2816 * a clean way of letting us retrieve this yet. */
2817 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2818 mmiowb();
fa1c114f 2819 }
9d139c81
JB		 2820
2821 if (conf->changed & IEEE80211_IFCC_BEACON &&
05c914fe 2822 vif->type == NL80211_IFTYPE_ADHOC) {
9d139c81
JB		 2823 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2824 if (!beacon) {
2825 ret = -ENOMEM;
2826 goto unlock;
2827 }
2828 /* call old handler for now */
2829 ath5k_beacon_update(hw, beacon);
2830 }
2831
fa1c114f
JS		 2832 mutex_unlock(&sc->lock);
2833
d7dc1003 2834 return ath5k_reset_wake(sc);
fa1c114f
JS		 2835unlock:
2836 mutex_unlock(&sc->lock);
2837 return ret;
2838}
2839
2840#define SUPPORTED_FIF_FLAGS \
2841 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2842 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2843 FIF_BCN_PRBRESP_PROMISC
2844/*
2845 * o always accept unicast, broadcast, and multicast traffic
2846 * o multicast traffic for all BSSIDs will be enabled if mac80211
2847 * says it should be
2848 * o maintain current state of phy ofdm or phy cck error reception.
2849 * If the hardware detects any of these type of errors then
2850 * ath5k_hw_get_rx_filter() will pass to us the respective
2851 * hardware filters to be able to receive these type of frames.
2852 * o probe request frames are accepted only when operating in
2853 * hostap, adhoc, or monitor modes
2854 * o enable promiscuous mode according to the interface state
2855 * o accept beacons:
2856 * - when operating in adhoc mode so the 802.11 layer creates
2857 * node table entries for peers,
2858 * - when operating in station mode for collecting rssi data when
2859 * the station is otherwise quiet, or
2860 * - when scanning
2861 */
2862static void ath5k_configure_filter(struct ieee80211_hw *hw,
2863 unsigned int changed_flags,
2864 unsigned int *new_flags,
2865 int mc_count, struct dev_mc_list *mclist)
2866{
2867 struct ath5k_softc *sc = hw->priv;
2868 struct ath5k_hw *ah = sc->ah;
2869 u32 mfilt[2], val, rfilt;
2870 u8 pos;
2871 int i;
2872
2873 mfilt[0] = 0;
2874 mfilt[1] = 0;
2875
2876 /* Only deal with supported flags */
2877 changed_flags &= SUPPORTED_FIF_FLAGS;
2878 *new_flags &= SUPPORTED_FIF_FLAGS;
2879
2880 /* If HW detects any phy or radar errors, leave those filters on.
2881 * Also, always enable Unicast, Broadcasts and Multicast
2882 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2883 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2884 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2885 AR5K_RX_FILTER_MCAST);
2886
2887 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2888 if (*new_flags & FIF_PROMISC_IN_BSS) {
2889 rfilt |= AR5K_RX_FILTER_PROM;
2890 __set_bit(ATH_STAT_PROMISC, sc->status);
2891 }
2892 else
2893 __clear_bit(ATH_STAT_PROMISC, sc->status);
2894 }
2895
2896 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2897 if (*new_flags & FIF_ALLMULTI) {
2898 mfilt[0] = ~0;
2899 mfilt[1] = ~0;
2900 } else {
2901 for (i = 0; i < mc_count; i++) {
2902 if (!mclist)
2903 break;
2904 /* calculate XOR of eight 6-bit values */
533dd1b0 2905 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2906 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2907 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2908 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2909 pos &= 0x3f;
2910 mfilt[pos / 32] |= (1 << (pos % 32));
2911 /* XXX: we might be able to just do this instead,
2912 * but not sure, needs testing, if we do use this we'd
2913 * neet to inform below to not reset the mcast */
2914 /* ath5k_hw_set_mcast_filterindex(ah,
2915 * mclist->dmi_addr[5]); */
2916 mclist = mclist->next;
2917 }
2918 }
2919
2920 /* This is the best we can do */
2921 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2922 rfilt |= AR5K_RX_FILTER_PHYERR;
2923
2924 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2925 * and probes for any BSSID, this needs testing */
2926 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2927 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2928
2929 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2930 * set we should only pass on control frames for this
2931 * station. This needs testing. I believe right now this
2932 * enables *all* control frames, which is OK.. but
2933 * but we should see if we can improve on granularity */
2934 if (*new_flags & FIF_CONTROL)
2935 rfilt |= AR5K_RX_FILTER_CONTROL;
2936
2937 /* Additional settings per mode -- this is per ath5k */
2938
2939 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2940
05c914fe 2941 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2942 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2943 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2944 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2945 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2946 if (sc->opmode != NL80211_IFTYPE_AP &&
2947 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2948 test_bit(ATH_STAT_PROMISC, sc->status))
2949 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2950 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
934f6c3f 2951 sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2952 rfilt |= AR5K_RX_FILTER_BEACON;
934f6c3f 2953 }
fa1c114f
JS		 2954
2955 /* Set filters */
2956 ath5k_hw_set_rx_filter(ah,rfilt);
2957
2958 /* Set multicast bits */
2959 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2960 /* Set the cached hw filter flags, this will alter actually
2961 * be set in HW */
2962 sc->filter_flags = rfilt;
2963}
2964
2965static int
2966ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2967 const u8 *local_addr, const u8 *addr,
2968 struct ieee80211_key_conf *key)
2969{
2970 struct ath5k_softc *sc = hw->priv;
2971 int ret = 0;
2972
2973 switch(key->alg) {
2974 case ALG_WEP:
6844e63a
LR		 2975 /* XXX: fix hardware encryption, its not working. For now
2976 * allow software encryption */
2977 /* break; */
fa1c114f
JS		 2978 case ALG_TKIP:
2979 case ALG_CCMP:
2980 return -EOPNOTSUPP;
2981 default:
2982 WARN_ON(1);
2983 return -EINVAL;
2984 }
2985
2986 mutex_lock(&sc->lock);
2987
2988 switch (cmd) {
2989 case SET_KEY:
2990 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2991 if (ret) {
2992 ATH5K_ERR(sc, "can't set the key\n");
2993 goto unlock;
2994 }
2995 __set_bit(key->keyidx, sc->keymap);
2996 key->hw_key_idx = key->keyidx;
2997 break;
2998 case DISABLE_KEY:
2999 ath5k_hw_reset_key(sc->ah, key->keyidx);
3000 __clear_bit(key->keyidx, sc->keymap);
3001 break;
3002 default:
3003 ret = -EINVAL;
3004 goto unlock;
3005 }
3006
3007unlock:
274c7c36 3008 mmiowb();
fa1c114f
JS		 3009 mutex_unlock(&sc->lock);
3010 return ret;
3011}
3012
3013static int
3014ath5k_get_stats(struct ieee80211_hw *hw,
3015 struct ieee80211_low_level_stats *stats)
3016{
3017 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3018 struct ath5k_hw *ah = sc->ah;
3019
3020 /* Force update */
3021 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3022
3023 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3024
3025 return 0;
3026}
3027
3028static int
3029ath5k_get_tx_stats(struct ieee80211_hw *hw,
3030 struct ieee80211_tx_queue_stats *stats)
3031{
3032 struct ath5k_softc *sc = hw->priv;
3033
3034 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3035
3036 return 0;
3037}
3038
3039static u64
3040ath5k_get_tsf(struct ieee80211_hw *hw)
3041{
3042 struct ath5k_softc *sc = hw->priv;
3043
3044 return ath5k_hw_get_tsf64(sc->ah);
3045}
3046
3047static void
3048ath5k_reset_tsf(struct ieee80211_hw *hw)
3049{
3050 struct ath5k_softc *sc = hw->priv;
3051
9804b98d
BR		 3052 /*
3053 * in IBSS mode we need to update the beacon timers too.
3054 * this will also reset the TSF if we call it with 0
3055 */
05c914fe 3056 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3057 ath5k_beacon_update_timers(sc, 0);
3058 else
3059 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3060}
3061
3062static int
e039fa4a 3063ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3064{
3065 struct ath5k_softc *sc = hw->priv;
00482973 3066 unsigned long flags;
fa1c114f
JS		 3067 int ret;
3068
3069 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3070
05c914fe 3071 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 3072 ret = -EIO;
3073 goto end;
3074 }
3075
00482973 3076 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3077 ath5k_txbuf_free(sc, sc->bbuf);
3078 sc->bbuf->skb = skb;
e039fa4a 3079 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3080 if (ret)
3081 sc->bbuf->skb = NULL;
00482973
JS		 3082 spin_unlock_irqrestore(&sc->block, flags);
3083 if (!ret) {
fa1c114f 3084 ath5k_beacon_config(sc);
274c7c36
JS		 3085 mmiowb();
3086 }
fa1c114f
JS		 3087
3088end:
fa1c114f
JS		 3089 return ret;
3090}
02969b38
MX		 3091static void
3092set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3093{
3094 struct ath5k_softc *sc = hw->priv;
3095 struct ath5k_hw *ah = sc->ah;
3096 u32 rfilt;
3097 rfilt = ath5k_hw_get_rx_filter(ah);
3098 if (enable)
3099 rfilt |= AR5K_RX_FILTER_BEACON;
3100 else
3101 rfilt &= ~AR5K_RX_FILTER_BEACON;
3102 ath5k_hw_set_rx_filter(ah, rfilt);
3103 sc->filter_flags = rfilt;
3104}
fa1c114f 3105
02969b38
MX		 3106static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3107 struct ieee80211_vif *vif,
3108 struct ieee80211_bss_conf *bss_conf,
3109 u32 changes)
3110{
3111 struct ath5k_softc *sc = hw->priv;
3112 if (changes & BSS_CHANGED_ASSOC) {
3113 mutex_lock(&sc->lock);
3114 sc->assoc = bss_conf->assoc;
3115 if (sc->opmode == NL80211_IFTYPE_STATION)
3116 set_beacon_filter(hw, sc->assoc);
3117 mutex_unlock(&sc->lock);
3118 }
3119}
Linux 6.x block layer and io_uring tree(s)