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wireless: replace uses of __constant_{endian}
[linux-block.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 242static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 243static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 244static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 245 struct sk_buff *skb);
02969b38
MX		 246static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
fa1c114f
JS		 250
251static struct ieee80211_ops ath5k_hw_ops = {
252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
313/* Queues setup */
314static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
315 int qtype, int subtype);
316static int ath5k_beaconq_setup(struct ath5k_hw *ah);
317static int ath5k_beaconq_config(struct ath5k_softc *sc);
318static void ath5k_txq_drainq(struct ath5k_softc *sc,
319 struct ath5k_txq *txq);
320static void ath5k_txq_cleanup(struct ath5k_softc *sc);
321static void ath5k_txq_release(struct ath5k_softc *sc);
322/* Rx handling */
323static int ath5k_rx_start(struct ath5k_softc *sc);
324static void ath5k_rx_stop(struct ath5k_softc *sc);
325static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
326 struct ath5k_desc *ds,
b47f407b
BR		 327 struct sk_buff *skb,
328 struct ath5k_rx_status *rs);
fa1c114f
JS		 329static void ath5k_tasklet_rx(unsigned long data);
330/* Tx handling */
331static void ath5k_tx_processq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_tasklet_tx(unsigned long data);
334/* Beacon handling */
335static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 336 struct ath5k_buf *bf);
fa1c114f
JS		 337static void ath5k_beacon_send(struct ath5k_softc *sc);
338static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 339static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 340
341static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
342{
343 u64 tsf = ath5k_hw_get_tsf64(ah);
344
345 if ((tsf & 0x7fff) < rstamp)
346 tsf -= 0x8000;
347
348 return (tsf & ~0x7fff) | rstamp;
349}
350
351/* Interrupt handling */
bb2becac 352static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 353static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 354static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 355static irqreturn_t ath5k_intr(int irq, void *dev_id);
356static void ath5k_tasklet_reset(unsigned long data);
357
358static void ath5k_calibrate(unsigned long data);
359/* LED functions */
3a078876
BC		 360static int ath5k_init_leds(struct ath5k_softc *sc);
361static void ath5k_led_enable(struct ath5k_softc *sc);
362static void ath5k_led_off(struct ath5k_softc *sc);
363static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 364
365/*
366 * Module init/exit functions
367 */
368static int __init
369init_ath5k_pci(void)
370{
371 int ret;
372
373 ath5k_debug_init();
374
04a9e451 375 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 376 if (ret) {
377 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
378 return ret;
379 }
380
381 return 0;
382}
383
384static void __exit
385exit_ath5k_pci(void)
386{
04a9e451 387 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 388
389 ath5k_debug_finish();
390}
391
392module_init(init_ath5k_pci);
393module_exit(exit_ath5k_pci);
394
395
396/********************\
397* PCI Initialization *
398\********************/
399
400static const char *
401ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
402{
403 const char *name = "xxxxx";
404 unsigned int i;
405
406 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
407 if (srev_names[i].sr_type != type)
408 continue;
75d0edb8
NK		 409
410 if ((val & 0xf0) == srev_names[i].sr_val)
411 name = srev_names[i].sr_name;
412
413 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 414 name = srev_names[i].sr_name;
415 break;
416 }
417 }
418
419 return name;
420}
421
422static int __devinit
423ath5k_pci_probe(struct pci_dev *pdev,
424 const struct pci_device_id *id)
425{
426 void __iomem *mem;
427 struct ath5k_softc *sc;
428 struct ieee80211_hw *hw;
429 int ret;
430 u8 csz;
431
432 ret = pci_enable_device(pdev);
433 if (ret) {
434 dev_err(&pdev->dev, "can't enable device\n");
435 goto err;
436 }
437
438 /* XXX 32-bit addressing only */
439 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
440 if (ret) {
441 dev_err(&pdev->dev, "32-bit DMA not available\n");
442 goto err_dis;
443 }
444
445 /*
446 * Cache line size is used to size and align various
447 * structures used to communicate with the hardware.
448 */
449 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
450 if (csz == 0) {
451 /*
452 * Linux 2.4.18 (at least) writes the cache line size
453 * register as a 16-bit wide register which is wrong.
454 * We must have this setup properly for rx buffer
455 * DMA to work so force a reasonable value here if it
456 * comes up zero.
457 */
458 csz = L1_CACHE_BYTES / sizeof(u32);
459 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
460 }
461 /*
462 * The default setting of latency timer yields poor results,
463 * set it to the value used by other systems. It may be worth
464 * tweaking this setting more.
465 */
466 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
467
468 /* Enable bus mastering */
469 pci_set_master(pdev);
470
471 /*
472 * Disable the RETRY_TIMEOUT register (0x41) to keep
473 * PCI Tx retries from interfering with C3 CPU state.
474 */
475 pci_write_config_byte(pdev, 0x41, 0);
476
477 ret = pci_request_region(pdev, 0, "ath5k");
478 if (ret) {
479 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
480 goto err_dis;
481 }
482
483 mem = pci_iomap(pdev, 0, 0);
484 if (!mem) {
485 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
486 ret = -EIO;
487 goto err_reg;
488 }
489
490 /*
491 * Allocate hw (mac80211 main struct)
492 * and hw->priv (driver private data)
493 */
494 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
495 if (hw == NULL) {
496 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
497 ret = -ENOMEM;
498 goto err_map;
499 }
500
501 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
502
503 /* Initialize driver private data */
504 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 505 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
506 IEEE80211_HW_SIGNAL_DBM |
507 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 508
509 hw->wiphy->interface_modes =
510 BIT(NL80211_IFTYPE_STATION) |
511 BIT(NL80211_IFTYPE_ADHOC) |
512 BIT(NL80211_IFTYPE_MESH_POINT);
513
fa1c114f
JS		 514 hw->extra_tx_headroom = 2;
515 hw->channel_change_time = 5000;
fa1c114f
JS		 516 sc = hw->priv;
517 sc->hw = hw;
518 sc->pdev = pdev;
519
520 ath5k_debug_init_device(sc);
521
522 /*
523 * Mark the device as detached to avoid processing
524 * interrupts until setup is complete.
525 */
526 __set_bit(ATH_STAT_INVALID, sc->status);
527
528 sc->iobase = mem; /* So we can unmap it on detach */
529 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 530 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 531 mutex_init(&sc->lock);
532 spin_lock_init(&sc->rxbuflock);
533 spin_lock_init(&sc->txbuflock);
00482973 534 spin_lock_init(&sc->block);
fa1c114f
JS		 535
536 /* Set private data */
537 pci_set_drvdata(pdev, hw);
538
fa1c114f
JS		 539 /* Setup interrupt handler */
540 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
541 if (ret) {
542 ATH5K_ERR(sc, "request_irq failed\n");
543 goto err_free;
544 }
545
546 /* Initialize device */
547 sc->ah = ath5k_hw_attach(sc, id->driver_data);
548 if (IS_ERR(sc->ah)) {
549 ret = PTR_ERR(sc->ah);
550 goto err_irq;
551 }
552
2f7fe870
FF		 553 /* set up multi-rate retry capabilities */
554 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 555 hw->max_rates = 4;
556 hw->max_rate_tries = 11;
2f7fe870
FF		 557 }
558
fa1c114f
JS		 559 /* Finish private driver data initialization */
560 ret = ath5k_attach(pdev, hw);
561 if (ret)
562 goto err_ah;
563
564 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 565 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 566 sc->ah->ah_mac_srev,
567 sc->ah->ah_phy_revision);
568
400ec45a 569 if (!sc->ah->ah_single_chip) {
fa1c114f 570 /* Single chip radio (!RF5111) */
400ec45a
LR		 571 if (sc->ah->ah_radio_5ghz_revision &&
572 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 573 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 574 if (!test_bit(AR5K_MODE_11A,
575 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 576 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 577 ath5k_chip_name(AR5K_VERSION_RAD,
578 sc->ah->ah_radio_5ghz_revision),
579 sc->ah->ah_radio_5ghz_revision);
580 /* No 2GHz support (5110 and some
581 * 5Ghz only cards) -> report 5Ghz radio */
582 } else if (!test_bit(AR5K_MODE_11B,
583 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 584 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 585 ath5k_chip_name(AR5K_VERSION_RAD,
586 sc->ah->ah_radio_5ghz_revision),
587 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 588 /* Multiband radio */
589 } else {
590 ATH5K_INFO(sc, "RF%s multiband radio found"
591 " (0x%x)\n",
400ec45a
LR		 592 ath5k_chip_name(AR5K_VERSION_RAD,
593 sc->ah->ah_radio_5ghz_revision),
594 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 595 }
596 }
400ec45a
LR		 597 /* Multi chip radio (RF5111 - RF2111) ->
598 * report both 2GHz/5GHz radios */
599 else if (sc->ah->ah_radio_5ghz_revision &&
600 sc->ah->ah_radio_2ghz_revision){
fa1c114f 601 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 602 ath5k_chip_name(AR5K_VERSION_RAD,
603 sc->ah->ah_radio_5ghz_revision),
604 sc->ah->ah_radio_5ghz_revision);
fa1c114f 605 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 606 ath5k_chip_name(AR5K_VERSION_RAD,
607 sc->ah->ah_radio_2ghz_revision),
608 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 609 }
610 }
611
612
613 /* ready to process interrupts */
614 __clear_bit(ATH_STAT_INVALID, sc->status);
615
616 return 0;
617err_ah:
618 ath5k_hw_detach(sc->ah);
619err_irq:
620 free_irq(pdev->irq, sc);
621err_free:
fa1c114f
JS		 622 ieee80211_free_hw(hw);
623err_map:
624 pci_iounmap(pdev, mem);
625err_reg:
626 pci_release_region(pdev, 0);
627err_dis:
628 pci_disable_device(pdev);
629err:
630 return ret;
631}
632
633static void __devexit
634ath5k_pci_remove(struct pci_dev *pdev)
635{
636 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
637 struct ath5k_softc *sc = hw->priv;
638
639 ath5k_debug_finish_device(sc);
640 ath5k_detach(pdev, hw);
641 ath5k_hw_detach(sc->ah);
642 free_irq(pdev->irq, sc);
fa1c114f
JS		 643 pci_iounmap(pdev, sc->iobase);
644 pci_release_region(pdev, 0);
645 pci_disable_device(pdev);
646 ieee80211_free_hw(hw);
647}
648
649#ifdef CONFIG_PM
650static int
651ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
652{
653 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
654 struct ath5k_softc *sc = hw->priv;
655
3a078876 656 ath5k_led_off(sc);
fa1c114f 657
3e4242b9 658 free_irq(pdev->irq, sc);
fa1c114f
JS		 659 pci_save_state(pdev);
660 pci_disable_device(pdev);
661 pci_set_power_state(pdev, PCI_D3hot);
662
663 return 0;
664}
665
666static int
667ath5k_pci_resume(struct pci_dev *pdev)
668{
669 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
670 struct ath5k_softc *sc = hw->priv;
bc1b32d6 671 int err;
fa1c114f 672
3e4242b9 673 pci_restore_state(pdev);
fa1c114f
JS		 674
675 err = pci_enable_device(pdev);
676 if (err)
677 return err;
678
fa1c114f
JS		 679 /*
680 * Suspend/Resume resets the PCI configuration space, so we have to
681 * re-disable the RETRY_TIMEOUT register (0x41) to keep
682 * PCI Tx retries from interfering with C3 CPU state
683 */
684 pci_write_config_byte(pdev, 0x41, 0);
685
3e4242b9
JS		 686 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
687 if (err) {
688 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 689 goto err_no_irq;
3e4242b9
JS		 690 }
691
3a078876 692 ath5k_led_enable(sc);
fa1c114f 693 return 0;
bb2becac 694
37465c8a 695err_no_irq:
3e4242b9
JS		 696 pci_disable_device(pdev);
697 return err;
fa1c114f
JS		 698}
699#endif /* CONFIG_PM */
700
701
fa1c114f
JS		 702/***********************\
703* Driver Initialization *
704\***********************/
705
706static int
707ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
708{
709 struct ath5k_softc *sc = hw->priv;
710 struct ath5k_hw *ah = sc->ah;
0e149cf5 711 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 712 int ret;
713
714 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
715
716 /*
717 * Check if the MAC has multi-rate retry support.
718 * We do this by trying to setup a fake extended
719 * descriptor. MAC's that don't have support will
720 * return false w/o doing anything. MAC's that do
721 * support it will return true w/o doing anything.
722 */
c6e387a2 723 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 724 if (ret < 0)
725 goto err;
726 if (ret > 0)
fa1c114f
JS		 727 __set_bit(ATH_STAT_MRRETRY, sc->status);
728
fa1c114f
JS		 729 /*
730 * Collect the channel list. The 802.11 layer
731 * is resposible for filtering this list based
732 * on settings like the phy mode and regulatory
733 * domain restrictions.
734 */
63266a65 735 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 736 if (ret) {
737 ATH5K_ERR(sc, "can't get channels\n");
738 goto err;
739 }
740
741 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 742 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
743 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 744 else
d8ee398d 745 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 746
747 /*
748 * Allocate tx+rx descriptors and populate the lists.
749 */
750 ret = ath5k_desc_alloc(sc, pdev);
751 if (ret) {
752 ATH5K_ERR(sc, "can't allocate descriptors\n");
753 goto err;
754 }
755
756 /*
757 * Allocate hardware transmit queues: one queue for
758 * beacon frames and one data queue for each QoS
759 * priority. Note that hw functions handle reseting
760 * these queues at the needed time.
761 */
762 ret = ath5k_beaconq_setup(ah);
763 if (ret < 0) {
764 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
765 goto err_desc;
766 }
767 sc->bhalq = ret;
768
769 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
770 if (IS_ERR(sc->txq)) {
771 ATH5K_ERR(sc, "can't setup xmit queue\n");
772 ret = PTR_ERR(sc->txq);
773 goto err_bhal;
774 }
775
776 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
777 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
778 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
779 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 780
0e149cf5
BC		 781 ret = ath5k_eeprom_read_mac(ah, mac);
782 if (ret) {
783 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
784 sc->pdev->device);
785 goto err_queues;
786 }
787
fa1c114f
JS		 788 SET_IEEE80211_PERM_ADDR(hw, mac);
789 /* All MAC address bits matter for ACKs */
790 memset(sc->bssidmask, 0xff, ETH_ALEN);
791 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
792
793 ret = ieee80211_register_hw(hw);
794 if (ret) {
795 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
796 goto err_queues;
797 }
798
3a078876
BC		 799 ath5k_init_leds(sc);
800
fa1c114f
JS		 801 return 0;
802err_queues:
803 ath5k_txq_release(sc);
804err_bhal:
805 ath5k_hw_release_tx_queue(ah, sc->bhalq);
806err_desc:
807 ath5k_desc_free(sc, pdev);
808err:
809 return ret;
810}
811
812static void
813ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
814{
815 struct ath5k_softc *sc = hw->priv;
816
817 /*
818 * NB: the order of these is important:
819 * o call the 802.11 layer before detaching ath5k_hw to
820 * insure callbacks into the driver to delete global
821 * key cache entries can be handled
822 * o reclaim the tx queue data structures after calling
823 * the 802.11 layer as we'll get called back to reclaim
824 * node state and potentially want to use them
825 * o to cleanup the tx queues the hal is called, so detach
826 * it last
827 * XXX: ??? detach ath5k_hw ???
828 * Other than that, it's straightforward...
829 */
830 ieee80211_unregister_hw(hw);
831 ath5k_desc_free(sc, pdev);
832 ath5k_txq_release(sc);
833 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 834 ath5k_unregister_leds(sc);
fa1c114f
JS		 835
836 /*
837 * NB: can't reclaim these until after ieee80211_ifdetach
838 * returns because we'll get called back to reclaim node
839 * state and potentially want to use them.
840 */
841}
842
843
844
845
846/********************\
847* Channel/mode setup *
848\********************/
849
850/*
851 * Convert IEEE channel number to MHz frequency.
852 */
853static inline short
854ath5k_ieee2mhz(short chan)
855{
856 if (chan <= 14 || chan >= 27)
857 return ieee80211chan2mhz(chan);
858 else
859 return 2212 + chan * 20;
860}
861
fa1c114f
JS		 862static unsigned int
863ath5k_copy_channels(struct ath5k_hw *ah,
864 struct ieee80211_channel *channels,
865 unsigned int mode,
866 unsigned int max)
867{
d8ee398d 868 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 869
870 if (!test_bit(mode, ah->ah_modes))
871 return 0;
872
fa1c114f 873 switch (mode) {
d8ee398d
LR		 874 case AR5K_MODE_11A:
875 case AR5K_MODE_11A_TURBO:
fa1c114f 876 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 877 size = 220 ;
fa1c114f
JS		 878 chfreq = CHANNEL_5GHZ;
879 break;
d8ee398d
LR		 880 case AR5K_MODE_11B:
881 case AR5K_MODE_11G:
882 case AR5K_MODE_11G_TURBO:
883 size = 26;
fa1c114f
JS		 884 chfreq = CHANNEL_2GHZ;
885 break;
886 default:
887 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
888 return 0;
889 }
890
891 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 892 ch = i + 1 ;
893 freq = ath5k_ieee2mhz(ch);
fa1c114f 894
d8ee398d
LR		 895 /* Check if channel is supported by the chipset */
896 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 897 continue;
898
d8ee398d
LR		 899 /* Write channel info and increment counter */
900 channels[count].center_freq = freq;
a3f4b914
LR		 901 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
902 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 903 switch (mode) {
904 case AR5K_MODE_11A:
905 case AR5K_MODE_11G:
906 channels[count].hw_value = chfreq | CHANNEL_OFDM;
907 break;
908 case AR5K_MODE_11A_TURBO:
909 case AR5K_MODE_11G_TURBO:
910 channels[count].hw_value = chfreq |
911 CHANNEL_OFDM | CHANNEL_TURBO;
912 break;
913 case AR5K_MODE_11B:
d8ee398d
LR		 914 channels[count].hw_value = CHANNEL_B;
915 }
fa1c114f 916
fa1c114f
JS		 917 count++;
918 max--;
919 }
920
921 return count;
922}
923
63266a65
BR		 924static void
925ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
926{
927 u8 i;
928
929 for (i = 0; i < AR5K_MAX_RATES; i++)
930 sc->rate_idx[b->band][i] = -1;
931
932 for (i = 0; i < b->n_bitrates; i++) {
933 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
934 if (b->bitrates[i].hw_value_short)
935 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
936 }
937}
938
d8ee398d 939static int
63266a65 940ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 941{
942 struct ath5k_softc *sc = hw->priv;
d8ee398d 943 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 944 struct ieee80211_supported_band *sband;
945 int max_c, count_c = 0;
946 int i;
fa1c114f 947
d8ee398d 948 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 949 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 950
951 /* 2GHz band */
63266a65
BR		 952 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
953 sband->band = IEEE80211_BAND_2GHZ;
954 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 955
63266a65
BR		 956 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
957 /* G mode */
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 12);
960 sband->n_bitrates = 12;
fa1c114f 961
d8ee398d 962 sband->channels = sc->channels;
d8ee398d 963 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 964 AR5K_MODE_11G, max_c);
fa1c114f 965
63266a65 966 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 967 count_c = sband->n_channels;
63266a65
BR		 968 max_c -= count_c;
969 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
970 /* B mode */
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 4);
973 sband->n_bitrates = 4;
974
975 /* 5211 only supports B rates and uses 4bit rate codes
976 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
977 * fix them up here:
978 */
979 if (ah->ah_version == AR5K_AR5211) {
980 for (i = 0; i < 4; i++) {
981 sband->bitrates[i].hw_value =
982 sband->bitrates[i].hw_value & 0xF;
983 sband->bitrates[i].hw_value_short =
984 sband->bitrates[i].hw_value_short & 0xF;
985 }
986 }
fa1c114f 987
63266a65
BR		 988 sband->channels = sc->channels;
989 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
990 AR5K_MODE_11B, max_c);
d8ee398d 991
63266a65
BR		 992 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
993 count_c = sband->n_channels;
d8ee398d 994 max_c -= count_c;
fa1c114f 995 }
63266a65 996 ath5k_setup_rate_idx(sc, sband);
fa1c114f 997
63266a65 998 /* 5GHz band, A mode */
400ec45a 999 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1000 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1001 sband->band = IEEE80211_BAND_5GHZ;
1002 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1003
63266a65
BR		 1004 memcpy(sband->bitrates, &ath5k_rates[4],
1005 sizeof(struct ieee80211_rate) * 8);
1006 sband->n_bitrates = 8;
fa1c114f 1007
63266a65 1008 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1009 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1010 AR5K_MODE_11A, max_c);
1011
d8ee398d
LR		 1012 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1013 }
63266a65 1014 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1015
b446197c 1016 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1017
1018 return 0;
fa1c114f
JS		 1019}
1020
1021/*
1022 * Set/change channels. If the channel is really being changed,
1023 * it's done by reseting the chip. To accomplish this we must
1024 * first cleanup any pending DMA, then restart stuff after a la
1025 * ath5k_init.
be009370
BC		 1026 *
1027 * Called with sc->lock.
fa1c114f
JS		 1028 */
1029static int
1030ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1031{
d8ee398d
LR		 1032 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1033 sc->curchan->center_freq, chan->center_freq);
1034
1035 if (chan->center_freq != sc->curchan->center_freq ||
1036 chan->hw_value != sc->curchan->hw_value) {
1037
1038 sc->curchan = chan;
1039 sc->curband = &sc->sbands[chan->band];
fa1c114f 1040
fa1c114f
JS		 1041 /*
1042 * To switch channels clear any pending DMA operations;
1043 * wait long enough for the RX fifo to drain, reset the
1044 * hardware at the new frequency, and then re-enable
1045 * the relevant bits of the h/w.
1046 */
d7dc1003 1047 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1048 }
1049
1050 return 0;
1051}
1052
1053static void
1054ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1055{
fa1c114f 1056 sc->curmode = mode;
d8ee398d 1057
400ec45a 1058 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1059 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1060 } else {
1061 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1062 }
fa1c114f
JS		 1063}
1064
1065static void
1066ath5k_mode_setup(struct ath5k_softc *sc)
1067{
1068 struct ath5k_hw *ah = sc->ah;
1069 u32 rfilt;
1070
1071 /* configure rx filter */
1072 rfilt = sc->filter_flags;
1073 ath5k_hw_set_rx_filter(ah, rfilt);
1074
1075 if (ath5k_hw_hasbssidmask(ah))
1076 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1077
1078 /* configure operational mode */
1079 ath5k_hw_set_opmode(ah);
1080
1081 ath5k_hw_set_mcast_filter(ah, 0, 0);
1082 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1083}
1084
d8ee398d 1085static inline int
63266a65
BR		 1086ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1087{
1088 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1089 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1090}
1091
fa1c114f
JS		 1092/***************\
1093* Buffers setup *
1094\***************/
1095
b6ea0356
BC		 1096static
1097struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1098{
1099 struct sk_buff *skb;
1100 unsigned int off;
1101
1102 /*
1103 * Allocate buffer with headroom_needed space for the
1104 * fake physical layer header at the start.
1105 */
1106 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1107
1108 if (!skb) {
1109 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1110 sc->rxbufsize + sc->cachelsz - 1);
1111 return NULL;
1112 }
1113 /*
1114 * Cache-line-align. This is important (for the
1115 * 5210 at least) as not doing so causes bogus data
1116 * in rx'd frames.
1117 */
1118 off = ((unsigned long)skb->data) % sc->cachelsz;
1119 if (off != 0)
1120 skb_reserve(skb, sc->cachelsz - off);
1121
1122 *skb_addr = pci_map_single(sc->pdev,
1123 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1124 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1125 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1126 dev_kfree_skb(skb);
1127 return NULL;
1128 }
1129 return skb;
1130}
1131
fa1c114f
JS		 1132static int
1133ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1134{
1135 struct ath5k_hw *ah = sc->ah;
1136 struct sk_buff *skb = bf->skb;
1137 struct ath5k_desc *ds;
1138
b6ea0356
BC		 1139 if (!skb) {
1140 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1141 if (!skb)
fa1c114f 1142 return -ENOMEM;
fa1c114f 1143 bf->skb = skb;
fa1c114f
JS		 1144 }
1145
1146 /*
1147 * Setup descriptors. For receive we always terminate
1148 * the descriptor list with a self-linked entry so we'll
1149 * not get overrun under high load (as can happen with a
1150 * 5212 when ANI processing enables PHY error frames).
1151 *
1152 * To insure the last descriptor is self-linked we create
1153 * each descriptor as self-linked and add it to the end. As
1154 * each additional descriptor is added the previous self-linked
1155 * entry is ``fixed'' naturally. This should be safe even
1156 * if DMA is happening. When processing RX interrupts we
1157 * never remove/process the last, self-linked, entry on the
1158 * descriptor list. This insures the hardware always has
1159 * someplace to write a new frame.
1160 */
1161 ds = bf->desc;
1162 ds->ds_link = bf->daddr; /* link to self */
1163 ds->ds_data = bf->skbaddr;
c6e387a2 1164 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1165 skb_tailroom(skb), /* buffer size */
1166 0);
1167
1168 if (sc->rxlink != NULL)
1169 *sc->rxlink = bf->daddr;
1170 sc->rxlink = &ds->ds_link;
1171 return 0;
1172}
1173
1174static int
e039fa4a 1175ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1176{
1177 struct ath5k_hw *ah = sc->ah;
1178 struct ath5k_txq *txq = sc->txq;
1179 struct ath5k_desc *ds = bf->desc;
1180 struct sk_buff *skb = bf->skb;
a888d52d 1181 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1182 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1183 struct ieee80211_rate *rate;
1184 unsigned int mrr_rate[3], mrr_tries[3];
1185 int i, ret;
8902ff4e 1186 u16 hw_rate;
07c1e852
BC		 1187 u16 cts_rate = 0;
1188 u16 duration = 0;
8902ff4e 1189 u8 rc_flags;
fa1c114f
JS		 1190
1191 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1192
fa1c114f
JS		 1193 /* XXX endianness */
1194 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1195 PCI_DMA_TODEVICE);
1196
8902ff4e
BC		 1197 rate = ieee80211_get_tx_rate(sc->hw, info);
1198
e039fa4a 1199 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1200 flags |= AR5K_TXDESC_NOACK;
1201
8902ff4e
BC		 1202 rc_flags = info->control.rates[0].flags;
1203 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1204 rate->hw_value_short : rate->hw_value;
1205
281c56dd 1206 pktlen = skb->len;
fa1c114f 1207
07c1e852
BC		 1208 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1209 flags |= AR5K_TXDESC_RTSENA;
1210 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1211 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1212 sc->vif, pktlen, info));
1213 }
1214 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1215 flags |= AR5K_TXDESC_CTSENA;
1216 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1217 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1218 sc->vif, pktlen, info));
1219 }
1220
d0f09804 1221 if (info->control.hw_key) {
e039fa4a 1222 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1223 pktlen += info->control.hw_key->icv_len;
fa1c114f 1224 }
fa1c114f
JS		 1225 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1226 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1227 (sc->power_level * 2),
8902ff4e 1228 hw_rate,
07c1e852
BC		 1229 info->control.rates[0].count, keyidx, 0, flags,
1230 cts_rate, duration);
fa1c114f
JS		 1231 if (ret)
1232 goto err_unmap;
1233
2f7fe870
FF		 1234 memset(mrr_rate, 0, sizeof(mrr_rate));
1235 memset(mrr_tries, 0, sizeof(mrr_tries));
1236 for (i = 0; i < 3; i++) {
1237 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1238 if (!rate)
1239 break;
1240
1241 mrr_rate[i] = rate->hw_value;
e6a9854b 1242 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1243 }
1244
1245 ah->ah_setup_mrr_tx_desc(ah, ds,
1246 mrr_rate[0], mrr_tries[0],
1247 mrr_rate[1], mrr_tries[1],
1248 mrr_rate[2], mrr_tries[2]);
1249
fa1c114f
JS		 1250 ds->ds_link = 0;
1251 ds->ds_data = bf->skbaddr;
1252
1253 spin_lock_bh(&txq->lock);
1254 list_add_tail(&bf->list, &txq->q);
57ffc589 1255 sc->tx_stats[txq->qnum].len++;
fa1c114f 1256 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1257 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1258 else /* no, so only link it */
1259 *txq->link = bf->daddr;
1260
1261 txq->link = &ds->ds_link;
c6e387a2 1262 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1263 mmiowb();
fa1c114f
JS		 1264 spin_unlock_bh(&txq->lock);
1265
1266 return 0;
1267err_unmap:
1268 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1269 return ret;
1270}
1271
1272/*******************\
1273* Descriptors setup *
1274\*******************/
1275
1276static int
1277ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1278{
1279 struct ath5k_desc *ds;
1280 struct ath5k_buf *bf;
1281 dma_addr_t da;
1282 unsigned int i;
1283 int ret;
1284
1285 /* allocate descriptors */
1286 sc->desc_len = sizeof(struct ath5k_desc) *
1287 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1288 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1289 if (sc->desc == NULL) {
1290 ATH5K_ERR(sc, "can't allocate descriptors\n");
1291 ret = -ENOMEM;
1292 goto err;
1293 }
1294 ds = sc->desc;
1295 da = sc->desc_daddr;
1296 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1297 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1298
1299 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1300 sizeof(struct ath5k_buf), GFP_KERNEL);
1301 if (bf == NULL) {
1302 ATH5K_ERR(sc, "can't allocate bufptr\n");
1303 ret = -ENOMEM;
1304 goto err_free;
1305 }
1306 sc->bufptr = bf;
1307
1308 INIT_LIST_HEAD(&sc->rxbuf);
1309 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1310 bf->desc = ds;
1311 bf->daddr = da;
1312 list_add_tail(&bf->list, &sc->rxbuf);
1313 }
1314
1315 INIT_LIST_HEAD(&sc->txbuf);
1316 sc->txbuf_len = ATH_TXBUF;
1317 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1318 da += sizeof(*ds)) {
1319 bf->desc = ds;
1320 bf->daddr = da;
1321 list_add_tail(&bf->list, &sc->txbuf);
1322 }
1323
1324 /* beacon buffer */
1325 bf->desc = ds;
1326 bf->daddr = da;
1327 sc->bbuf = bf;
1328
1329 return 0;
1330err_free:
1331 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1332err:
1333 sc->desc = NULL;
1334 return ret;
1335}
1336
1337static void
1338ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1339{
1340 struct ath5k_buf *bf;
1341
1342 ath5k_txbuf_free(sc, sc->bbuf);
1343 list_for_each_entry(bf, &sc->txbuf, list)
1344 ath5k_txbuf_free(sc, bf);
1345 list_for_each_entry(bf, &sc->rxbuf, list)
1346 ath5k_txbuf_free(sc, bf);
1347
1348 /* Free memory associated with all descriptors */
1349 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1350
1351 kfree(sc->bufptr);
1352 sc->bufptr = NULL;
1353}
1354
1355
1356
1357
1358
1359/**************\
1360* Queues setup *
1361\**************/
1362
1363static struct ath5k_txq *
1364ath5k_txq_setup(struct ath5k_softc *sc,
1365 int qtype, int subtype)
1366{
1367 struct ath5k_hw *ah = sc->ah;
1368 struct ath5k_txq *txq;
1369 struct ath5k_txq_info qi = {
1370 .tqi_subtype = subtype,
1371 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1372 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1373 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1374 };
1375 int qnum;
1376
1377 /*
1378 * Enable interrupts only for EOL and DESC conditions.
1379 * We mark tx descriptors to receive a DESC interrupt
1380 * when a tx queue gets deep; otherwise waiting for the
1381 * EOL to reap descriptors. Note that this is done to
1382 * reduce interrupt load and this only defers reaping
1383 * descriptors, never transmitting frames. Aside from
1384 * reducing interrupts this also permits more concurrency.
1385 * The only potential downside is if the tx queue backs
1386 * up in which case the top half of the kernel may backup
1387 * due to a lack of tx descriptors.
1388 */
1389 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1390 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1391 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1392 if (qnum < 0) {
1393 /*
1394 * NB: don't print a message, this happens
1395 * normally on parts with too few tx queues
1396 */
1397 return ERR_PTR(qnum);
1398 }
1399 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1400 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1401 qnum, ARRAY_SIZE(sc->txqs));
1402 ath5k_hw_release_tx_queue(ah, qnum);
1403 return ERR_PTR(-EINVAL);
1404 }
1405 txq = &sc->txqs[qnum];
1406 if (!txq->setup) {
1407 txq->qnum = qnum;
1408 txq->link = NULL;
1409 INIT_LIST_HEAD(&txq->q);
1410 spin_lock_init(&txq->lock);
1411 txq->setup = true;
1412 }
1413 return &sc->txqs[qnum];
1414}
1415
1416static int
1417ath5k_beaconq_setup(struct ath5k_hw *ah)
1418{
1419 struct ath5k_txq_info qi = {
1420 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1421 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1422 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1423 /* NB: for dynamic turbo, don't enable any other interrupts */
1424 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1425 };
1426
1427 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1428}
1429
1430static int
1431ath5k_beaconq_config(struct ath5k_softc *sc)
1432{
1433 struct ath5k_hw *ah = sc->ah;
1434 struct ath5k_txq_info qi;
1435 int ret;
1436
1437 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1438 if (ret)
1439 return ret;
05c914fe
JB		 1440 if (sc->opmode == NL80211_IFTYPE_AP ||
1441 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1442 /*
1443 * Always burst out beacon and CAB traffic
1444 * (aifs = cwmin = cwmax = 0)
1445 */
1446 qi.tqi_aifs = 0;
1447 qi.tqi_cw_min = 0;
1448 qi.tqi_cw_max = 0;
05c914fe 1449 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1450 /*
1451 * Adhoc mode; backoff between 0 and (2 * cw_min).
1452 */
1453 qi.tqi_aifs = 0;
1454 qi.tqi_cw_min = 0;
1455 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1456 }
1457
6d91e1d8
BR		 1458 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1459 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1460 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1461
c6e387a2 1462 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1463 if (ret) {
1464 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1465 "hardware queue!\n", __func__);
1466 return ret;
1467 }
1468
1469 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1470}
1471
1472static void
1473ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1474{
1475 struct ath5k_buf *bf, *bf0;
1476
1477 /*
1478 * NB: this assumes output has been stopped and
1479 * we do not need to block ath5k_tx_tasklet
1480 */
1481 spin_lock_bh(&txq->lock);
1482 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1483 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1484
1485 ath5k_txbuf_free(sc, bf);
1486
1487 spin_lock_bh(&sc->txbuflock);
57ffc589 1488 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1489 list_move_tail(&bf->list, &sc->txbuf);
1490 sc->txbuf_len++;
1491 spin_unlock_bh(&sc->txbuflock);
1492 }
1493 txq->link = NULL;
1494 spin_unlock_bh(&txq->lock);
1495}
1496
1497/*
1498 * Drain the transmit queues and reclaim resources.
1499 */
1500static void
1501ath5k_txq_cleanup(struct ath5k_softc *sc)
1502{
1503 struct ath5k_hw *ah = sc->ah;
1504 unsigned int i;
1505
1506 /* XXX return value */
1507 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1508 /* don't touch the hardware if marked invalid */
1509 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1510 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1511 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1512 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1513 if (sc->txqs[i].setup) {
1514 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1515 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1516 "link %p\n",
1517 sc->txqs[i].qnum,
c6e387a2 1518 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1519 sc->txqs[i].qnum),
1520 sc->txqs[i].link);
1521 }
1522 }
36d6825b 1523 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1524
1525 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1526 if (sc->txqs[i].setup)
1527 ath5k_txq_drainq(sc, &sc->txqs[i]);
1528}
1529
1530static void
1531ath5k_txq_release(struct ath5k_softc *sc)
1532{
1533 struct ath5k_txq *txq = sc->txqs;
1534 unsigned int i;
1535
1536 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1537 if (txq->setup) {
1538 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1539 txq->setup = false;
1540 }
1541}
1542
1543
1544
1545
1546/*************\
1547* RX Handling *
1548\*************/
1549
1550/*
1551 * Enable the receive h/w following a reset.
1552 */
1553static int
1554ath5k_rx_start(struct ath5k_softc *sc)
1555{
1556 struct ath5k_hw *ah = sc->ah;
1557 struct ath5k_buf *bf;
1558 int ret;
1559
1560 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1561
1562 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1563 sc->cachelsz, sc->rxbufsize);
1564
1565 sc->rxlink = NULL;
1566
1567 spin_lock_bh(&sc->rxbuflock);
1568 list_for_each_entry(bf, &sc->rxbuf, list) {
1569 ret = ath5k_rxbuf_setup(sc, bf);
1570 if (ret != 0) {
1571 spin_unlock_bh(&sc->rxbuflock);
1572 goto err;
1573 }
1574 }
1575 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1576 spin_unlock_bh(&sc->rxbuflock);
1577
c6e387a2
NK		 1578 ath5k_hw_set_rxdp(ah, bf->daddr);
1579 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1580 ath5k_mode_setup(sc); /* set filters, etc. */
1581 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1582
1583 return 0;
1584err:
1585 return ret;
1586}
1587
1588/*
1589 * Disable the receive h/w in preparation for a reset.
1590 */
1591static void
1592ath5k_rx_stop(struct ath5k_softc *sc)
1593{
1594 struct ath5k_hw *ah = sc->ah;
1595
c6e387a2 1596 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1597 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1598 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1599
1600 ath5k_debug_printrxbuffs(sc, ah);
1601
1602 sc->rxlink = NULL; /* just in case */
1603}
1604
1605static unsigned int
1606ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1607 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1608{
1609 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1610 unsigned int keyix, hlen;
fa1c114f 1611
b47f407b
BR		 1612 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1613 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1614 return RX_FLAG_DECRYPTED;
1615
1616 /* Apparently when a default key is used to decrypt the packet
1617 the hw does not set the index used to decrypt. In such cases
1618 get the index from the packet. */
798ee985 1619 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1620 if (ieee80211_has_protected(hdr->frame_control) &&
1621 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1622 skb->len >= hlen + 4) {
fa1c114f
JS		 1623 keyix = skb->data[hlen + 3] >> 6;
1624
1625 if (test_bit(keyix, sc->keymap))
1626 return RX_FLAG_DECRYPTED;
1627 }
1628
1629 return 0;
1630}
1631
036cd1ec
BR		 1632
1633static void
6ba81c2c
BR		 1634ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1635 struct ieee80211_rx_status *rxs)
036cd1ec 1636{
6ba81c2c 1637 u64 tsf, bc_tstamp;
036cd1ec
BR		 1638 u32 hw_tu;
1639 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1640
24b56e70 1641 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1642 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1643 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1644 /*
6ba81c2c
BR		 1645 * Received an IBSS beacon with the same BSSID. Hardware *must*
1646 * have updated the local TSF. We have to work around various
1647 * hardware bugs, though...
036cd1ec 1648 */
6ba81c2c
BR		 1649 tsf = ath5k_hw_get_tsf64(sc->ah);
1650 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1651 hw_tu = TSF_TO_TU(tsf);
1652
1653 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1654 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1655 (unsigned long long)bc_tstamp,
1656 (unsigned long long)rxs->mactime,
1657 (unsigned long long)(rxs->mactime - bc_tstamp),
1658 (unsigned long long)tsf);
6ba81c2c
BR		 1659
1660 /*
1661 * Sometimes the HW will give us a wrong tstamp in the rx
1662 * status, causing the timestamp extension to go wrong.
1663 * (This seems to happen especially with beacon frames bigger
1664 * than 78 byte (incl. FCS))
1665 * But we know that the receive timestamp must be later than the
1666 * timestamp of the beacon since HW must have synced to that.
1667 *
1668 * NOTE: here we assume mactime to be after the frame was
1669 * received, not like mac80211 which defines it at the start.
1670 */
1671 if (bc_tstamp > rxs->mactime) {
036cd1ec 1672 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1673 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1674 (unsigned long long)rxs->mactime,
1675 (unsigned long long)tsf);
6ba81c2c 1676 rxs->mactime = tsf;
036cd1ec 1677 }
6ba81c2c
BR		 1678
1679 /*
1680 * Local TSF might have moved higher than our beacon timers,
1681 * in that case we have to update them to continue sending
1682 * beacons. This also takes care of synchronizing beacon sending
1683 * times with other stations.
1684 */
1685 if (hw_tu >= sc->nexttbtt)
1686 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1687 }
1688}
1689
1690
fa1c114f
JS		 1691static void
1692ath5k_tasklet_rx(unsigned long data)
1693{
1694 struct ieee80211_rx_status rxs = {};
b47f407b 1695 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1696 struct sk_buff *skb, *next_skb;
1697 dma_addr_t next_skb_addr;
fa1c114f 1698 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1699 struct ath5k_buf *bf, *bf_last;
fa1c114f 1700 struct ath5k_desc *ds;
fa1c114f
JS		 1701 int ret;
1702 int hdrlen;
0fe45b1d 1703 int padsize;
fa1c114f
JS		 1704
1705 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1706 if (list_empty(&sc->rxbuf)) {
1707 ATH5K_WARN(sc, "empty rx buf pool\n");
1708 goto unlock;
1709 }
1710 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1711 do {
d6894b5b
BC		 1712 rxs.flag = 0;
1713
fa1c114f
JS		 1714 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1715 BUG_ON(bf->skb == NULL);
1716 skb = bf->skb;
1717 ds = bf->desc;
1718
3a0f2c87
JS		 1719 /*
1720 * last buffer must not be freed to ensure proper hardware
1721 * function. When the hardware finishes also a packet next to
1722 * it, we are sure, it doesn't use it anymore and we can go on.
1723 */
1724 if (bf_last == bf)
1725 bf->flags |= 1;
1726 if (bf->flags) {
1727 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1728 struct ath5k_buf, list);
1729 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1730 &rs);
1731 if (ret)
1732 break;
1733 bf->flags &= ~1;
1734 /* skip the overwritten one (even status is martian) */
1735 goto next;
1736 }
fa1c114f 1737
b47f407b 1738 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1739 if (unlikely(ret == -EINPROGRESS))
1740 break;
1741 else if (unlikely(ret)) {
1742 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1743 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1744 return;
1745 }
1746
b47f407b 1747 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1748 ATH5K_WARN(sc, "unsupported jumbo\n");
1749 goto next;
1750 }
1751
b47f407b
BR		 1752 if (unlikely(rs.rs_status)) {
1753 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1754 goto next;
b47f407b 1755 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1756 /*
1757 * Decrypt error. If the error occurred
1758 * because there was no hardware key, then
1759 * let the frame through so the upper layers
1760 * can process it. This is necessary for 5210
1761 * parts which have no way to setup a ``clear''
1762 * key cache entry.
1763 *
1764 * XXX do key cache faulting
1765 */
b47f407b
BR		 1766 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1767 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1768 goto accept;
1769 }
b47f407b 1770 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1771 rxs.flag |= RX_FLAG_MMIC_ERROR;
1772 goto accept;
1773 }
1774
1775 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1776 if ((rs.rs_status &
1777 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1778 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1779 goto next;
1780 }
1781accept:
b6ea0356
BC		 1782 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1783
1784 /*
1785 * If we can't replace bf->skb with a new skb under memory
1786 * pressure, just skip this packet
1787 */
1788 if (!next_skb)
1789 goto next;
1790
fa1c114f
JS		 1791 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1792 PCI_DMA_FROMDEVICE);
b47f407b 1793 skb_put(skb, rs.rs_datalen);
fa1c114f 1794
0fe45b1d
BP		 1795 /* The MAC header is padded to have 32-bit boundary if the
1796 * packet payload is non-zero. The general calculation for
1797 * padsize would take into account odd header lengths:
1798 * padsize = (4 - hdrlen % 4) % 4; However, since only
1799 * even-length headers are used, padding can only be 0 or 2
1800 * bytes and we can optimize this a bit. In addition, we must
1801 * not try to remove padding from short control frames that do
1802 * not have payload. */
fa1c114f 1803 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1804 padsize = ath5k_pad_size(hdrlen);
1805 if (padsize) {
0fe45b1d
BP		 1806 memmove(skb->data + padsize, skb->data, hdrlen);
1807 skb_pull(skb, padsize);
fa1c114f
JS		 1808 }
1809
c0e1899b
BR		 1810 /*
1811 * always extend the mac timestamp, since this information is
1812 * also needed for proper IBSS merging.
1813 *
1814 * XXX: it might be too late to do it here, since rs_tstamp is
1815 * 15bit only. that means TSF extension has to be done within
1816 * 32768usec (about 32ms). it might be necessary to move this to
1817 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1818 *
1819 * Unfortunately we don't know when the hardware takes the rx
1820 * timestamp (beginning of phy frame, data frame, end of rx?).
1821 * The only thing we know is that it is hardware specific...
1822 * On AR5213 it seems the rx timestamp is at the end of the
1823 * frame, but i'm not sure.
1824 *
1825 * NOTE: mac80211 defines mactime at the beginning of the first
1826 * data symbol. Since we don't have any time references it's
1827 * impossible to comply to that. This affects IBSS merge only
1828 * right now, so it's not too bad...
c0e1899b 1829 */
b47f407b 1830 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1831 rxs.flag |= RX_FLAG_TSFT;
1832
d8ee398d
LR		 1833 rxs.freq = sc->curchan->center_freq;
1834 rxs.band = sc->curband->band;
fa1c114f 1835
fa1c114f 1836 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1837 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1838
1839 /* An rssi of 35 indicates you should be able use
1840 * 54 Mbps reliably. A more elaborate scheme can be used
1841 * here but it requires a map of SNR/throughput for each
1842 * possible mode used */
1843 rxs.qual = rs.rs_rssi * 100 / 35;
1844
1845 /* rssi can be more than 35 though, anything above that
1846 * should be considered at 100% */
1847 if (rxs.qual > 100)
1848 rxs.qual = 100;
fa1c114f 1849
b47f407b
BR		 1850 rxs.antenna = rs.rs_antenna;
1851 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1852 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1853
06303352
BR		 1854 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1855 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1856 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1857
fa1c114f
JS		 1858 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1859
036cd1ec 1860 /* check beacons in IBSS mode */
05c914fe 1861 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1862 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1863
fa1c114f 1864 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1865
1866 bf->skb = next_skb;
1867 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1868next:
1869 list_move_tail(&bf->list, &sc->rxbuf);
1870 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1871unlock:
fa1c114f
JS		 1872 spin_unlock(&sc->rxbuflock);
1873}
1874
1875
1876
1877
1878/*************\
1879* TX Handling *
1880\*************/
1881
1882static void
1883ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1884{
b47f407b 1885 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1886 struct ath5k_buf *bf, *bf0;
1887 struct ath5k_desc *ds;
1888 struct sk_buff *skb;
e039fa4a 1889 struct ieee80211_tx_info *info;
2f7fe870 1890 int i, ret;
fa1c114f
JS		 1891
1892 spin_lock(&txq->lock);
1893 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1894 ds = bf->desc;
1895
b47f407b 1896 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1897 if (unlikely(ret == -EINPROGRESS))
1898 break;
1899 else if (unlikely(ret)) {
1900 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1901 ret, txq->qnum);
1902 break;
1903 }
1904
1905 skb = bf->skb;
a888d52d 1906 info = IEEE80211_SKB_CB(skb);
fa1c114f 1907 bf->skb = NULL;
e039fa4a 1908
fa1c114f
JS		 1909 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1910 PCI_DMA_TODEVICE);
1911
e6a9854b 1912 ieee80211_tx_info_clear_status(info);
2f7fe870 1913 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1914 struct ieee80211_tx_rate *r =
1915 &info->status.rates[i];
2f7fe870
FF		 1916
1917 if (ts.ts_rate[i]) {
e6a9854b
JB		 1918 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1919 r->count = ts.ts_retry[i];
2f7fe870 1920 } else {
e6a9854b
JB		 1921 r->idx = -1;
1922 r->count = 0;
2f7fe870
FF		 1923 }
1924 }
1925
e6a9854b
JB		 1926 /* count the successful attempt as well */
1927 info->status.rates[ts.ts_final_idx].count++;
1928
b47f407b 1929 if (unlikely(ts.ts_status)) {
fa1c114f 1930 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1931 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1932 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1933 } else {
e039fa4a
JB		 1934 info->flags |= IEEE80211_TX_STAT_ACK;
1935 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1936 }
1937
e039fa4a 1938 ieee80211_tx_status(sc->hw, skb);
57ffc589 1939 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1940
1941 spin_lock(&sc->txbuflock);
57ffc589 1942 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1943 list_move_tail(&bf->list, &sc->txbuf);
1944 sc->txbuf_len++;
1945 spin_unlock(&sc->txbuflock);
1946 }
1947 if (likely(list_empty(&txq->q)))
1948 txq->link = NULL;
1949 spin_unlock(&txq->lock);
1950 if (sc->txbuf_len > ATH_TXBUF / 5)
1951 ieee80211_wake_queues(sc->hw);
1952}
1953
1954static void
1955ath5k_tasklet_tx(unsigned long data)
1956{
1957 struct ath5k_softc *sc = (void *)data;
1958
1959 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1960}
1961
1962
fa1c114f
JS		 1963/*****************\
1964* Beacon handling *
1965\*****************/
1966
1967/*
1968 * Setup the beacon frame for transmit.
1969 */
1970static int
e039fa4a 1971ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1972{
1973 struct sk_buff *skb = bf->skb;
a888d52d 1974 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1975 struct ath5k_hw *ah = sc->ah;
1976 struct ath5k_desc *ds;
1977 int ret, antenna = 0;
1978 u32 flags;
1979
1980 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1981 PCI_DMA_TODEVICE);
1982 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1983 "skbaddr %llx\n", skb, skb->data, skb->len,
1984 (unsigned long long)bf->skbaddr);
8d8bb39b 1985 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1986 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1987 return -EIO;
1988 }
1989
1990 ds = bf->desc;
1991
1992 flags = AR5K_TXDESC_NOACK;
05c914fe 1993 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1994 ds->ds_link = bf->daddr; /* self-linked */
1995 flags |= AR5K_TXDESC_VEOL;
1996 /*
1997 * Let hardware handle antenna switching if txantenna is not set
1998 */
1999 } else {
2000 ds->ds_link = 0;
2001 /*
2002 * Switch antenna every 4 beacons if txantenna is not set
2003 * XXX assumes two antennas
2004 */
2005 if (antenna == 0)
2006 antenna = sc->bsent & 4 ? 2 : 1;
2007 }
2008
2009 ds->ds_data = bf->skbaddr;
281c56dd 2010 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2011 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2012 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2013 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2014 1, AR5K_TXKEYIX_INVALID,
400ec45a 2015 antenna, flags, 0, 0);
fa1c114f
JS		 2016 if (ret)
2017 goto err_unmap;
2018
2019 return 0;
2020err_unmap:
2021 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2022 return ret;
2023}
2024
2025/*
2026 * Transmit a beacon frame at SWBA. Dynamic updates to the
2027 * frame contents are done as needed and the slot time is
2028 * also adjusted based on current state.
2029 *
2030 * this is usually called from interrupt context (ath5k_intr())
2031 * but also from ath5k_beacon_config() in IBSS mode which in turn
2032 * can be called from a tasklet and user context
2033 */
2034static void
2035ath5k_beacon_send(struct ath5k_softc *sc)
2036{
2037 struct ath5k_buf *bf = sc->bbuf;
2038 struct ath5k_hw *ah = sc->ah;
2039
be9b7259 2040 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2041
05c914fe
JB		 2042 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2043 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2044 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2045 return;
2046 }
2047 /*
2048 * Check if the previous beacon has gone out. If
2049 * not don't don't try to post another, skip this
2050 * period and wait for the next. Missed beacons
2051 * indicate a problem and should not occur. If we
2052 * miss too many consecutive beacons reset the device.
2053 */
2054 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2055 sc->bmisscount++;
be9b7259 2056 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2057 "missed %u consecutive beacons\n", sc->bmisscount);
2058 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2059 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2060 "stuck beacon time (%u missed)\n",
2061 sc->bmisscount);
2062 tasklet_schedule(&sc->restq);
2063 }
2064 return;
2065 }
2066 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2067 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2068 "resume beacon xmit after %u misses\n",
2069 sc->bmisscount);
2070 sc->bmisscount = 0;
2071 }
2072
2073 /*
2074 * Stop any current dma and put the new frame on the queue.
2075 * This should never fail since we check above that no frames
2076 * are still pending on the queue.
2077 */
2078 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2079 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2080 /* NB: hw still stops DMA, so proceed */
2081 }
fa1c114f 2082
c6e387a2
NK		 2083 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2084 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2085 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2086 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2087
2088 sc->bsent++;
2089}
2090
2091
9804b98d
BR		 2092/**
2093 * ath5k_beacon_update_timers - update beacon timers
2094 *
2095 * @sc: struct ath5k_softc pointer we are operating on
2096 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2097 * beacon timer update based on the current HW TSF.
2098 *
2099 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2100 * of a received beacon or the current local hardware TSF and write it to the
2101 * beacon timer registers.
2102 *
2103 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2104 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2105 * when we otherwise know we have to update the timers, but we keep it in this
2106 * function to have it all together in one place.
2107 */
fa1c114f 2108static void
9804b98d 2109ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2110{
2111 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2112 u32 nexttbtt, intval, hw_tu, bc_tu;
2113 u64 hw_tsf;
fa1c114f
JS		 2114
2115 intval = sc->bintval & AR5K_BEACON_PERIOD;
2116 if (WARN_ON(!intval))
2117 return;
2118
9804b98d
BR		 2119 /* beacon TSF converted to TU */
2120 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2121
9804b98d
BR		 2122 /* current TSF converted to TU */
2123 hw_tsf = ath5k_hw_get_tsf64(ah);
2124 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2125
9804b98d
BR		 2126#define FUDGE 3
2127 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2128 if (bc_tsf == -1) {
2129 /*
2130 * no beacons received, called internally.
2131 * just need to refresh timers based on HW TSF.
2132 */
2133 nexttbtt = roundup(hw_tu + FUDGE, intval);
2134 } else if (bc_tsf == 0) {
2135 /*
2136 * no beacon received, probably called by ath5k_reset_tsf().
2137 * reset TSF to start with 0.
2138 */
2139 nexttbtt = intval;
2140 intval |= AR5K_BEACON_RESET_TSF;
2141 } else if (bc_tsf > hw_tsf) {
2142 /*
2143 * beacon received, SW merge happend but HW TSF not yet updated.
2144 * not possible to reconfigure timers yet, but next time we
2145 * receive a beacon with the same BSSID, the hardware will
2146 * automatically update the TSF and then we need to reconfigure
2147 * the timers.
2148 */
2149 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2150 "need to wait for HW TSF sync\n");
2151 return;
2152 } else {
2153 /*
2154 * most important case for beacon synchronization between STA.
2155 *
2156 * beacon received and HW TSF has been already updated by HW.
2157 * update next TBTT based on the TSF of the beacon, but make
2158 * sure it is ahead of our local TSF timer.
2159 */
2160 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2161 }
2162#undef FUDGE
fa1c114f 2163
036cd1ec
BR		 2164 sc->nexttbtt = nexttbtt;
2165
fa1c114f 2166 intval |= AR5K_BEACON_ENA;
fa1c114f 2167 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2168
2169 /*
2170 * debugging output last in order to preserve the time critical aspect
2171 * of this function
2172 */
2173 if (bc_tsf == -1)
2174 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2175 "reconfigured timers based on HW TSF\n");
2176 else if (bc_tsf == 0)
2177 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2178 "reset HW TSF and timers\n");
2179 else
2180 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2181 "updated timers based on beacon TSF\n");
2182
2183 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2184 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2185 (unsigned long long) bc_tsf,
2186 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2187 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2188 intval & AR5K_BEACON_PERIOD,
2189 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2190 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2191}
2192
2193
036cd1ec
BR		 2194/**
2195 * ath5k_beacon_config - Configure the beacon queues and interrupts
2196 *
2197 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2198 *
2199 * When operating in station mode we want to receive a BMISS interrupt when we
2200 * stop seeing beacons from the AP we've associated with so we can look for
2201 * another AP to associate with.
2202 *
036cd1ec 2203 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2204 * interrupts to detect TSF updates only.
fa1c114f
JS		 2205 */
2206static void
2207ath5k_beacon_config(struct ath5k_softc *sc)
2208{
2209 struct ath5k_hw *ah = sc->ah;
2210
c6e387a2 2211 ath5k_hw_set_imr(ah, 0);
fa1c114f 2212 sc->bmisscount = 0;
dc1968e7 2213 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2214
05c914fe 2215 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2216 sc->imask |= AR5K_INT_BMISS;
da966bca 2217 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2218 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2219 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2220 /*
036cd1ec
BR		 2221 * In IBSS mode we use a self-linked tx descriptor and let the
2222 * hardware send the beacons automatically. We have to load it
fa1c114f 2223 * only once here.
036cd1ec 2224 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2225 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2226 */
2227 ath5k_beaconq_config(sc);
fa1c114f 2228
036cd1ec
BR		 2229 sc->imask |= AR5K_INT_SWBA;
2230
da966bca
JS		 2231 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2232 if (ath5k_hw_hasveol(ah)) {
2233 spin_lock(&sc->block);
2234 ath5k_beacon_send(sc);
2235 spin_unlock(&sc->block);
2236 }
2237 } else
2238 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2239 }
fa1c114f 2240
c6e387a2 2241 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2242}
2243
2244
2245/********************\
2246* Interrupt handling *
2247\********************/
2248
2249static int
bb2becac 2250ath5k_init(struct ath5k_softc *sc)
fa1c114f 2251{
bc1b32d6
EO		 2252 struct ath5k_hw *ah = sc->ah;
2253 int ret, i;
fa1c114f
JS		 2254
2255 mutex_lock(&sc->lock);
2256
2257 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2258
2259 /*
2260 * Stop anything previously setup. This is safe
2261 * no matter this is the first time through or not.
2262 */
2263 ath5k_stop_locked(sc);
2264
2265 /*
2266 * The basic interface to setting the hardware in a good
2267 * state is ``reset''. On return the hardware is known to
2268 * be powered up and with interrupts disabled. This must
2269 * be followed by initialization of the appropriate bits
2270 * and then setup of the interrupt mask.
2271 */
d8ee398d
LR		 2272 sc->curchan = sc->hw->conf.channel;
2273 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2274 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2275 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2276 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
d7dc1003
JS		 2277 ret = ath5k_reset(sc, false, false);
2278 if (ret)
2279 goto done;
fa1c114f 2280
bc1b32d6
EO		 2281 /*
2282 * Reset the key cache since some parts do not reset the
2283 * contents on initial power up or resume from suspend.
2284 */
2285 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2286 ath5k_hw_reset_key(ah, i);
2287
fa1c114f 2288 /* Set ack to be sent at low bit-rates */
bc1b32d6 2289 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2290
2291 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2292 msecs_to_jiffies(ath5k_calinterval * 1000)));
2293
2294 ret = 0;
2295done:
274c7c36 2296 mmiowb();
fa1c114f
JS		 2297 mutex_unlock(&sc->lock);
2298 return ret;
2299}
2300
2301static int
2302ath5k_stop_locked(struct ath5k_softc *sc)
2303{
2304 struct ath5k_hw *ah = sc->ah;
2305
2306 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2307 test_bit(ATH_STAT_INVALID, sc->status));
2308
2309 /*
2310 * Shutdown the hardware and driver:
2311 * stop output from above
2312 * disable interrupts
2313 * turn off timers
2314 * turn off the radio
2315 * clear transmit machinery
2316 * clear receive machinery
2317 * drain and release tx queues
2318 * reclaim beacon resources
2319 * power down hardware
2320 *
2321 * Note that some of this work is not possible if the
2322 * hardware is gone (invalid).
2323 */
2324 ieee80211_stop_queues(sc->hw);
2325
2326 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2327 ath5k_led_off(sc);
c6e387a2 2328 ath5k_hw_set_imr(ah, 0);
274c7c36 2329 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2330 }
2331 ath5k_txq_cleanup(sc);
2332 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2333 ath5k_rx_stop(sc);
2334 ath5k_hw_phy_disable(ah);
2335 } else
2336 sc->rxlink = NULL;
2337
2338 return 0;
2339}
2340
2341/*
2342 * Stop the device, grabbing the top-level lock to protect
2343 * against concurrent entry through ath5k_init (which can happen
2344 * if another thread does a system call and the thread doing the
2345 * stop is preempted).
2346 */
2347static int
bb2becac 2348ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2349{
2350 int ret;
2351
2352 mutex_lock(&sc->lock);
2353 ret = ath5k_stop_locked(sc);
2354 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2355 /*
2356 * Set the chip in full sleep mode. Note that we are
2357 * careful to do this only when bringing the interface
2358 * completely to a stop. When the chip is in this state
2359 * it must be carefully woken up or references to
2360 * registers in the PCI clock domain may freeze the bus
2361 * (and system). This varies by chip and is mostly an
2362 * issue with newer parts that go to sleep more quickly.
2363 */
2364 if (sc->ah->ah_mac_srev >= 0x78) {
2365 /*
2366 * XXX
2367 * don't put newer MAC revisions > 7.8 to sleep because
2368 * of the above mentioned problems
2369 */
2370 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2371 "not putting device to sleep\n");
2372 } else {
2373 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2374 "putting device to full sleep\n");
2375 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2376 }
2377 }
2378 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2379
274c7c36 2380 mmiowb();
fa1c114f
JS		 2381 mutex_unlock(&sc->lock);
2382
2383 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2384 tasklet_kill(&sc->rxtq);
2385 tasklet_kill(&sc->txtq);
2386 tasklet_kill(&sc->restq);
fa1c114f
JS		 2387
2388 return ret;
2389}
2390
2391static irqreturn_t
2392ath5k_intr(int irq, void *dev_id)
2393{
2394 struct ath5k_softc *sc = dev_id;
2395 struct ath5k_hw *ah = sc->ah;
2396 enum ath5k_int status;
2397 unsigned int counter = 1000;
2398
2399 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2400 !ath5k_hw_is_intr_pending(ah)))
2401 return IRQ_NONE;
2402
2403 do {
2404 /*
2405 * Figure out the reason(s) for the interrupt. Note
2406 * that get_isr returns a pseudo-ISR that may include
2407 * bits we haven't explicitly enabled so we mask the
2408 * value to insure we only process bits we requested.
2409 */
2410 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2411 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2412 status, sc->imask);
2413 status &= sc->imask; /* discard unasked for bits */
2414 if (unlikely(status & AR5K_INT_FATAL)) {
2415 /*
2416 * Fatal errors are unrecoverable.
2417 * Typically these are caused by DMA errors.
2418 */
2419 tasklet_schedule(&sc->restq);
2420 } else if (unlikely(status & AR5K_INT_RXORN)) {
2421 tasklet_schedule(&sc->restq);
2422 } else {
2423 if (status & AR5K_INT_SWBA) {
2424 /*
2425 * Software beacon alert--time to send a beacon.
2426 * Handle beacon transmission directly; deferring
2427 * this is too slow to meet timing constraints
2428 * under load.
036cd1ec
BR		 2429 *
2430 * In IBSS mode we use this interrupt just to
2431 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2432 * transmission time) in order to detect wether
2433 * automatic TSF updates happened.
fa1c114f 2434 */
05c914fe 2435 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2436 /* XXX: only if VEOL suppported */
2437 u64 tsf = ath5k_hw_get_tsf64(ah);
2438 sc->nexttbtt += sc->bintval;
2439 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2440 "SWBA nexttbtt: %x hw_tu: %x "
2441 "TSF: %llx\n",
2442 sc->nexttbtt,
2443 TSF_TO_TU(tsf),
2444 (unsigned long long) tsf);
036cd1ec 2445 } else {
00482973 2446 spin_lock(&sc->block);
036cd1ec 2447 ath5k_beacon_send(sc);
00482973 2448 spin_unlock(&sc->block);
036cd1ec 2449 }
fa1c114f
JS		 2450 }
2451 if (status & AR5K_INT_RXEOL) {
2452 /*
2453 * NB: the hardware should re-read the link when
2454 * RXE bit is written, but it doesn't work at
2455 * least on older hardware revs.
2456 */
2457 sc->rxlink = NULL;
2458 }
2459 if (status & AR5K_INT_TXURN) {
2460 /* bump tx trigger level */
2461 ath5k_hw_update_tx_triglevel(ah, true);
2462 }
4c674c60 2463 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2464 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2465 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2466 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2467 tasklet_schedule(&sc->txtq);
2468 if (status & AR5K_INT_BMISS) {
2469 }
2470 if (status & AR5K_INT_MIB) {
194828a2
NK		 2471 /*
2472 * These stats are also used for ANI i think
2473 * so how about updating them more often ?
2474 */
2475 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2476 }
2477 }
2478 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2479
2480 if (unlikely(!counter))
2481 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2482
2483 return IRQ_HANDLED;
2484}
2485
2486static void
2487ath5k_tasklet_reset(unsigned long data)
2488{
2489 struct ath5k_softc *sc = (void *)data;
2490
d7dc1003 2491 ath5k_reset_wake(sc);
fa1c114f
JS		 2492}
2493
2494/*
2495 * Periodically recalibrate the PHY to account
2496 * for temperature/environment changes.
2497 */
2498static void
2499ath5k_calibrate(unsigned long data)
2500{
2501 struct ath5k_softc *sc = (void *)data;
2502 struct ath5k_hw *ah = sc->ah;
2503
2504 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2505 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2506 sc->curchan->hw_value);
fa1c114f
JS		 2507
2508 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2509 /*
2510 * Rfgain is out of bounds, reset the chip
2511 * to load new gain values.
2512 */
2513 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2514 ath5k_reset_wake(sc);
fa1c114f
JS		 2515 }
2516 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2517 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2518 ieee80211_frequency_to_channel(
2519 sc->curchan->center_freq));
fa1c114f
JS		 2520
2521 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2522 msecs_to_jiffies(ath5k_calinterval * 1000)));
2523}
2524
2525
2526
2527/***************\
2528* LED functions *
2529\***************/
2530
2531static void
3a078876 2532ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2533{
3a078876
BC		 2534 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2535 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2536 ath5k_led_off(sc);
fa1c114f
JS		 2537 }
2538}
2539
fa1c114f 2540static void
3a078876 2541ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2542{
3a078876
BC		 2543 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2544 return;
fa1c114f 2545 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2546}
2547
2548static void
3a078876 2549ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2550{
3a078876 2551 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2552 return;
3a078876
BC		 2553 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2554}
2555
2556static void
2557ath5k_led_brightness_set(struct led_classdev *led_dev,
2558 enum led_brightness brightness)
2559{
2560 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2561 led_dev);
2562
2563 if (brightness == LED_OFF)
2564 ath5k_led_off(led->sc);
2565 else
2566 ath5k_led_on(led->sc);
2567}
2568
2569static int
2570ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2571 const char *name, char *trigger)
2572{
2573 int err;
2574
2575 led->sc = sc;
2576 strncpy(led->name, name, sizeof(led->name));
2577 led->led_dev.name = led->name;
2578 led->led_dev.default_trigger = trigger;
2579 led->led_dev.brightness_set = ath5k_led_brightness_set;
2580
2581 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2582 if (err) {
3a078876
BC		 2583 ATH5K_WARN(sc, "could not register LED %s\n", name);
2584 led->sc = NULL;
fa1c114f 2585 }
3a078876 2586 return err;
fa1c114f
JS		 2587}
2588
3a078876
BC		 2589static void
2590ath5k_unregister_led(struct ath5k_led *led)
2591{
2592 if (!led->sc)
2593 return;
2594 led_classdev_unregister(&led->led_dev);
2595 ath5k_led_off(led->sc);
2596 led->sc = NULL;
2597}
2598
2599static void
2600ath5k_unregister_leds(struct ath5k_softc *sc)
2601{
2602 ath5k_unregister_led(&sc->rx_led);
2603 ath5k_unregister_led(&sc->tx_led);
2604}
2605
2606
2607static int
2608ath5k_init_leds(struct ath5k_softc *sc)
2609{
2610 int ret = 0;
2611 struct ieee80211_hw *hw = sc->hw;
2612 struct pci_dev *pdev = sc->pdev;
2613 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2614
3a078876
BC		 2615 /*
2616 * Auto-enable soft led processing for IBM cards and for
2617 * 5211 minipci cards.
2618 */
2619 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2620 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2621 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2622 sc->led_pin = 0;
734b5aa9 2623 sc->led_on = 0; /* active low */
3a078876
BC		 2624 }
2625 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2626 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2627 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2628 sc->led_pin = 1;
734b5aa9 2629 sc->led_on = 1; /* active high */
3a078876 2630 }
f677d770
TMQMF		 2631 /*
2632 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2633 * in emachines notebooks with AMBIT subsystem.
2634 */
2635 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2636 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
63649b6c
BC		 2637 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2638 sc->led_pin = 3;
2639 sc->led_on = 0; /* active low */
2640 }
2641
3a078876
BC		 2642 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2643 goto out;
2644
2645 ath5k_led_enable(sc);
2646
2647 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2648 ret = ath5k_register_led(sc, &sc->rx_led, name,
2649 ieee80211_get_rx_led_name(hw));
2650 if (ret)
2651 goto out;
2652
2653 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2654 ret = ath5k_register_led(sc, &sc->tx_led, name,
2655 ieee80211_get_tx_led_name(hw));
2656out:
2657 return ret;
2658}
fa1c114f
JS		 2659
2660
2661/********************\
2662* Mac80211 functions *
2663\********************/
2664
2665static int
e039fa4a 2666ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2667{
2668 struct ath5k_softc *sc = hw->priv;
2669 struct ath5k_buf *bf;
2670 unsigned long flags;
2671 int hdrlen;
0fe45b1d 2672 int padsize;
fa1c114f
JS		 2673
2674 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2675
05c914fe 2676 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2677 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2678
2679 /*
2680 * the hardware expects the header padded to 4 byte boundaries
2681 * if this is not the case we add the padding after the header
2682 */
2683 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2684 padsize = ath5k_pad_size(hdrlen);
2685 if (padsize) {
0fe45b1d
BP		 2686
2687 if (skb_headroom(skb) < padsize) {
fa1c114f 2688 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2689 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2690 return NETDEV_TX_BUSY;
fa1c114f 2691 }
0fe45b1d
BP		 2692 skb_push(skb, padsize);
2693 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2694 }
2695
fa1c114f
JS		 2696 spin_lock_irqsave(&sc->txbuflock, flags);
2697 if (list_empty(&sc->txbuf)) {
2698 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2699 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2700 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2701 return NETDEV_TX_BUSY;
fa1c114f
JS		 2702 }
2703 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2704 list_del(&bf->list);
2705 sc->txbuf_len--;
2706 if (list_empty(&sc->txbuf))
2707 ieee80211_stop_queues(hw);
2708 spin_unlock_irqrestore(&sc->txbuflock, flags);
2709
2710 bf->skb = skb;
2711
e039fa4a 2712 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2713 bf->skb = NULL;
2714 spin_lock_irqsave(&sc->txbuflock, flags);
2715 list_add_tail(&bf->list, &sc->txbuf);
2716 sc->txbuf_len++;
2717 spin_unlock_irqrestore(&sc->txbuflock, flags);
2718 dev_kfree_skb_any(skb);
71ef99c8 2719 return NETDEV_TX_OK;
fa1c114f
JS		 2720 }
2721
71ef99c8 2722 return NETDEV_TX_OK;
fa1c114f
JS		 2723}
2724
2725static int
d7dc1003 2726ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2727{
fa1c114f
JS		 2728 struct ath5k_hw *ah = sc->ah;
2729 int ret;
2730
2731 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2732
d7dc1003 2733 if (stop) {
c6e387a2 2734 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2735 ath5k_txq_cleanup(sc);
2736 ath5k_rx_stop(sc);
2737 }
fa1c114f 2738 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2739 if (ret) {
fa1c114f
JS		 2740 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2741 goto err;
2742 }
d7dc1003
JS		 2743
2744 /*
2745 * This is needed only to setup initial state
2746 * but it's best done after a reset.
2747 */
fa1c114f
JS		 2748 ath5k_hw_set_txpower_limit(sc->ah, 0);
2749
2750 ret = ath5k_rx_start(sc);
d7dc1003 2751 if (ret) {
fa1c114f
JS		 2752 ATH5K_ERR(sc, "can't start recv logic\n");
2753 goto err;
2754 }
d7dc1003 2755
fa1c114f 2756 /*
d7dc1003
JS		 2757 * Change channels and update the h/w rate map if we're switching;
2758 * e.g. 11a to 11b/g.
2759 *
2760 * We may be doing a reset in response to an ioctl that changes the
2761 * channel so update any state that might change as a result.
fa1c114f
JS		 2762 *
2763 * XXX needed?
2764 */
2765/* ath5k_chan_change(sc, c); */
fa1c114f 2766
d7dc1003
JS		 2767 ath5k_beacon_config(sc);
2768 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2769
2770 return 0;
2771err:
2772 return ret;
2773}
2774
d7dc1003
JS		 2775static int
2776ath5k_reset_wake(struct ath5k_softc *sc)
2777{
2778 int ret;
2779
2780 ret = ath5k_reset(sc, true, true);
2781 if (!ret)
2782 ieee80211_wake_queues(sc->hw);
2783
2784 return ret;
2785}
2786
fa1c114f
JS		 2787static int ath5k_start(struct ieee80211_hw *hw)
2788{
bb2becac 2789 return ath5k_init(hw->priv);
fa1c114f
JS		 2790}
2791
2792static void ath5k_stop(struct ieee80211_hw *hw)
2793{
bb2becac 2794 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2795}
2796
2797static int ath5k_add_interface(struct ieee80211_hw *hw,
2798 struct ieee80211_if_init_conf *conf)
2799{
2800 struct ath5k_softc *sc = hw->priv;
2801 int ret;
2802
2803 mutex_lock(&sc->lock);
32bfd35d 2804 if (sc->vif) {
fa1c114f
JS		 2805 ret = 0;
2806 goto end;
2807 }
2808
32bfd35d 2809 sc->vif = conf->vif;
fa1c114f
JS		 2810
2811 switch (conf->type) {
da966bca 2812 case NL80211_IFTYPE_AP:
05c914fe
JB		 2813 case NL80211_IFTYPE_STATION:
2814 case NL80211_IFTYPE_ADHOC:
b706e65b 2815 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2816 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2817 sc->opmode = conf->type;
2818 break;
2819 default:
2820 ret = -EOPNOTSUPP;
2821 goto end;
2822 }
67d2e2df
JS		 2823
2824 /* Set to a reasonable value. Note that this will
2825 * be set to mac80211's value at ath5k_config(). */
2826 sc->bintval = 1000;
0e149cf5 2827 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2828
fa1c114f
JS		 2829 ret = 0;
2830end:
2831 mutex_unlock(&sc->lock);
2832 return ret;
2833}
2834
2835static void
2836ath5k_remove_interface(struct ieee80211_hw *hw,
2837 struct ieee80211_if_init_conf *conf)
2838{
2839 struct ath5k_softc *sc = hw->priv;
0e149cf5 2840 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2841
2842 mutex_lock(&sc->lock);
32bfd35d 2843 if (sc->vif != conf->vif)
fa1c114f
JS		 2844 goto end;
2845
0e149cf5 2846 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2847 sc->vif = NULL;
fa1c114f
JS		 2848end:
2849 mutex_unlock(&sc->lock);
2850}
2851
d8ee398d
LR		 2852/*
2853 * TODO: Phy disable/diversity etc
2854 */
fa1c114f 2855static int
e8975581 2856ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2857{
2858 struct ath5k_softc *sc = hw->priv;
e8975581 2859 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2860 int ret;
2861
2862 mutex_lock(&sc->lock);
fa1c114f 2863
e535c1ac 2864 sc->bintval = conf->beacon_int;
d8ee398d 2865 sc->power_level = conf->power_level;
fa1c114f 2866
be009370
BC		 2867 ret = ath5k_chan_set(sc, conf->channel);
2868
2869 mutex_unlock(&sc->lock);
2870 return ret;
fa1c114f
JS		 2871}
2872
2873static int
32bfd35d 2874ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2875 struct ieee80211_if_conf *conf)
2876{
2877 struct ath5k_softc *sc = hw->priv;
2878 struct ath5k_hw *ah = sc->ah;
2879 int ret;
2880
fa1c114f 2881 mutex_lock(&sc->lock);
32bfd35d 2882 if (sc->vif != vif) {
fa1c114f
JS		 2883 ret = -EIO;
2884 goto unlock;
2885 }
da966bca 2886 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2887 /* Cache for later use during resets */
2888 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2889 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2890 * a clean way of letting us retrieve this yet. */
2891 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2892 mmiowb();
fa1c114f 2893 }
9d139c81 2894 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2895 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2896 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2897 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2898 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2899 if (!beacon) {
2900 ret = -ENOMEM;
2901 goto unlock;
2902 }
da966bca 2903 ath5k_beacon_update(sc, beacon);
9d139c81 2904 }
fa1c114f
JS		 2905 mutex_unlock(&sc->lock);
2906
d7dc1003 2907 return ath5k_reset_wake(sc);
fa1c114f
JS		 2908unlock:
2909 mutex_unlock(&sc->lock);
2910 return ret;
2911}
2912
2913#define SUPPORTED_FIF_FLAGS \
2914 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2915 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2916 FIF_BCN_PRBRESP_PROMISC
2917/*
2918 * o always accept unicast, broadcast, and multicast traffic
2919 * o multicast traffic for all BSSIDs will be enabled if mac80211
2920 * says it should be
2921 * o maintain current state of phy ofdm or phy cck error reception.
2922 * If the hardware detects any of these type of errors then
2923 * ath5k_hw_get_rx_filter() will pass to us the respective
2924 * hardware filters to be able to receive these type of frames.
2925 * o probe request frames are accepted only when operating in
2926 * hostap, adhoc, or monitor modes
2927 * o enable promiscuous mode according to the interface state
2928 * o accept beacons:
2929 * - when operating in adhoc mode so the 802.11 layer creates
2930 * node table entries for peers,
2931 * - when operating in station mode for collecting rssi data when
2932 * the station is otherwise quiet, or
2933 * - when scanning
2934 */
2935static void ath5k_configure_filter(struct ieee80211_hw *hw,
2936 unsigned int changed_flags,
2937 unsigned int *new_flags,
2938 int mc_count, struct dev_mc_list *mclist)
2939{
2940 struct ath5k_softc *sc = hw->priv;
2941 struct ath5k_hw *ah = sc->ah;
2942 u32 mfilt[2], val, rfilt;
2943 u8 pos;
2944 int i;
2945
2946 mfilt[0] = 0;
2947 mfilt[1] = 0;
2948
2949 /* Only deal with supported flags */
2950 changed_flags &= SUPPORTED_FIF_FLAGS;
2951 *new_flags &= SUPPORTED_FIF_FLAGS;
2952
2953 /* If HW detects any phy or radar errors, leave those filters on.
2954 * Also, always enable Unicast, Broadcasts and Multicast
2955 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2956 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2957 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2958 AR5K_RX_FILTER_MCAST);
2959
2960 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2961 if (*new_flags & FIF_PROMISC_IN_BSS) {
2962 rfilt |= AR5K_RX_FILTER_PROM;
2963 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2964 } else {
fa1c114f 2965 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2966 }
fa1c114f
JS		 2967 }
2968
2969 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2970 if (*new_flags & FIF_ALLMULTI) {
2971 mfilt[0] = ~0;
2972 mfilt[1] = ~0;
2973 } else {
2974 for (i = 0; i < mc_count; i++) {
2975 if (!mclist)
2976 break;
2977 /* calculate XOR of eight 6-bit values */
533dd1b0 2978 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2979 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2980 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2981 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2982 pos &= 0x3f;
2983 mfilt[pos / 32] |= (1 << (pos % 32));
2984 /* XXX: we might be able to just do this instead,
2985 * but not sure, needs testing, if we do use this we'd
2986 * neet to inform below to not reset the mcast */
2987 /* ath5k_hw_set_mcast_filterindex(ah,
2988 * mclist->dmi_addr[5]); */
2989 mclist = mclist->next;
2990 }
2991 }
2992
2993 /* This is the best we can do */
2994 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2995 rfilt |= AR5K_RX_FILTER_PHYERR;
2996
2997 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2998 * and probes for any BSSID, this needs testing */
2999 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3000 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3001
3002 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3003 * set we should only pass on control frames for this
3004 * station. This needs testing. I believe right now this
3005 * enables *all* control frames, which is OK.. but
3006 * but we should see if we can improve on granularity */
3007 if (*new_flags & FIF_CONTROL)
3008 rfilt |= AR5K_RX_FILTER_CONTROL;
3009
3010 /* Additional settings per mode -- this is per ath5k */
3011
3012 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3013
05c914fe 3014 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 3015 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3016 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 3017 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 3018 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 3019 if (sc->opmode != NL80211_IFTYPE_AP &&
3020 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 3021 test_bit(ATH_STAT_PROMISC, sc->status))
3022 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 3023 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 3024 sc->opmode == NL80211_IFTYPE_ADHOC ||
3025 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 3026 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 3027 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3028 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3029 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 3030
3031 /* Set filters */
0bbac08f 3032 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3033
3034 /* Set multicast bits */
3035 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3036 /* Set the cached hw filter flags, this will alter actually
3037 * be set in HW */
3038 sc->filter_flags = rfilt;
3039}
3040
3041static int
3042ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3043 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3044 struct ieee80211_key_conf *key)
fa1c114f
JS		 3045{
3046 struct ath5k_softc *sc = hw->priv;
3047 int ret = 0;
3048
9ad9a26e
BC		 3049 if (modparam_nohwcrypt)
3050 return -EOPNOTSUPP;
3051
0bbac08f 3052 switch (key->alg) {
fa1c114f 3053 case ALG_WEP:
fa1c114f 3054 case ALG_TKIP:
3f64b435 3055 break;
fa1c114f
JS		 3056 case ALG_CCMP:
3057 return -EOPNOTSUPP;
3058 default:
3059 WARN_ON(1);
3060 return -EINVAL;
3061 }
3062
3063 mutex_lock(&sc->lock);
3064
3065 switch (cmd) {
3066 case SET_KEY:
dc822b5d
JB		 3067 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3068 sta ? sta->addr : NULL);
fa1c114f
JS		 3069 if (ret) {
3070 ATH5K_ERR(sc, "can't set the key\n");
3071 goto unlock;
3072 }
3073 __set_bit(key->keyidx, sc->keymap);
3074 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3075 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3076 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3077 break;
3078 case DISABLE_KEY:
3079 ath5k_hw_reset_key(sc->ah, key->keyidx);
3080 __clear_bit(key->keyidx, sc->keymap);
3081 break;
3082 default:
3083 ret = -EINVAL;
3084 goto unlock;
3085 }
3086
3087unlock:
274c7c36 3088 mmiowb();
fa1c114f
JS		 3089 mutex_unlock(&sc->lock);
3090 return ret;
3091}
3092
3093static int
3094ath5k_get_stats(struct ieee80211_hw *hw,
3095 struct ieee80211_low_level_stats *stats)
3096{
3097 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3098 struct ath5k_hw *ah = sc->ah;
3099
3100 /* Force update */
3101 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3102
3103 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3104
3105 return 0;
3106}
3107
3108static int
3109ath5k_get_tx_stats(struct ieee80211_hw *hw,
3110 struct ieee80211_tx_queue_stats *stats)
3111{
3112 struct ath5k_softc *sc = hw->priv;
3113
3114 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3115
3116 return 0;
3117}
3118
3119static u64
3120ath5k_get_tsf(struct ieee80211_hw *hw)
3121{
3122 struct ath5k_softc *sc = hw->priv;
3123
3124 return ath5k_hw_get_tsf64(sc->ah);
3125}
3126
3b5d665b
AF		 3127static void
3128ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3129{
3130 struct ath5k_softc *sc = hw->priv;
3131
3132 ath5k_hw_set_tsf64(sc->ah, tsf);
3133}
3134
fa1c114f
JS		 3135static void
3136ath5k_reset_tsf(struct ieee80211_hw *hw)
3137{
3138 struct ath5k_softc *sc = hw->priv;
3139
9804b98d
BR		 3140 /*
3141 * in IBSS mode we need to update the beacon timers too.
3142 * this will also reset the TSF if we call it with 0
3143 */
05c914fe 3144 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3145 ath5k_beacon_update_timers(sc, 0);
3146 else
3147 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3148}
3149
3150static int
da966bca 3151ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3152{
00482973 3153 unsigned long flags;
fa1c114f
JS		 3154 int ret;
3155
3156 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3157
00482973 3158 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3159 ath5k_txbuf_free(sc, sc->bbuf);
3160 sc->bbuf->skb = skb;
e039fa4a 3161 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3162 if (ret)
3163 sc->bbuf->skb = NULL;
00482973
JS		 3164 spin_unlock_irqrestore(&sc->block, flags);
3165 if (!ret) {
fa1c114f 3166 ath5k_beacon_config(sc);
274c7c36
JS		 3167 mmiowb();
3168 }
fa1c114f 3169
fa1c114f
JS		 3170 return ret;
3171}
02969b38
MX		 3172static void
3173set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3174{
3175 struct ath5k_softc *sc = hw->priv;
3176 struct ath5k_hw *ah = sc->ah;
3177 u32 rfilt;
3178 rfilt = ath5k_hw_get_rx_filter(ah);
3179 if (enable)
3180 rfilt |= AR5K_RX_FILTER_BEACON;
3181 else
3182 rfilt &= ~AR5K_RX_FILTER_BEACON;
3183 ath5k_hw_set_rx_filter(ah, rfilt);
3184 sc->filter_flags = rfilt;
3185}
fa1c114f 3186
02969b38
MX		 3187static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3188 struct ieee80211_vif *vif,
3189 struct ieee80211_bss_conf *bss_conf,
3190 u32 changes)
3191{
3192 struct ath5k_softc *sc = hw->priv;
3193 if (changes & BSS_CHANGED_ASSOC) {
3194 mutex_lock(&sc->lock);
3195 sc->assoc = bss_conf->assoc;
3196 if (sc->opmode == NL80211_IFTYPE_STATION)
3197 set_beacon_filter(hw, sc->assoc);
3198 mutex_unlock(&sc->lock);
3199 }
3200}
Linux 6.x block layer and io_uring tree(s)