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mac80211: make wake/stop_queue_by_reason() functions static
[linux-block.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 const u8 *local_addr, const u8 *addr,
236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 243static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 244 struct sk_buff *skb);
02969b38
MX		 245static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif,
247 struct ieee80211_bss_conf *bss_conf,
248 u32 changes);
fa1c114f
JS		 249
250static struct ieee80211_ops ath5k_hw_ops = {
251 .tx = ath5k_tx,
252 .start = ath5k_start,
253 .stop = ath5k_stop,
254 .add_interface = ath5k_add_interface,
255 .remove_interface = ath5k_remove_interface,
256 .config = ath5k_config,
257 .config_interface = ath5k_config_interface,
258 .configure_filter = ath5k_configure_filter,
259 .set_key = ath5k_set_key,
260 .get_stats = ath5k_get_stats,
261 .conf_tx = NULL,
262 .get_tx_stats = ath5k_get_tx_stats,
263 .get_tsf = ath5k_get_tsf,
264 .reset_tsf = ath5k_reset_tsf,
02969b38 265 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 266};
267
268/*
269 * Prototypes - Internal functions
270 */
271/* Attach detach */
272static int ath5k_attach(struct pci_dev *pdev,
273 struct ieee80211_hw *hw);
274static void ath5k_detach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276/* Channel/mode setup */
277static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 278static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
279 struct ieee80211_channel *channels,
280 unsigned int mode,
281 unsigned int max);
63266a65 282static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 283static int ath5k_chan_set(struct ath5k_softc *sc,
284 struct ieee80211_channel *chan);
285static void ath5k_setcurmode(struct ath5k_softc *sc,
286 unsigned int mode);
287static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 288
fa1c114f
JS		 289/* Descriptor setup */
290static int ath5k_desc_alloc(struct ath5k_softc *sc,
291 struct pci_dev *pdev);
292static void ath5k_desc_free(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294/* Buffers setup */
295static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
296 struct ath5k_buf *bf);
297static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 298 struct ath5k_buf *bf);
fa1c114f
JS		 299static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
300 struct ath5k_buf *bf)
301{
302 BUG_ON(!bf);
303 if (!bf->skb)
304 return;
305 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
306 PCI_DMA_TODEVICE);
00482973 307 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 308 bf->skb = NULL;
309}
310
311/* Queues setup */
312static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
313 int qtype, int subtype);
314static int ath5k_beaconq_setup(struct ath5k_hw *ah);
315static int ath5k_beaconq_config(struct ath5k_softc *sc);
316static void ath5k_txq_drainq(struct ath5k_softc *sc,
317 struct ath5k_txq *txq);
318static void ath5k_txq_cleanup(struct ath5k_softc *sc);
319static void ath5k_txq_release(struct ath5k_softc *sc);
320/* Rx handling */
321static int ath5k_rx_start(struct ath5k_softc *sc);
322static void ath5k_rx_stop(struct ath5k_softc *sc);
323static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
324 struct ath5k_desc *ds,
b47f407b
BR		 325 struct sk_buff *skb,
326 struct ath5k_rx_status *rs);
fa1c114f
JS		 327static void ath5k_tasklet_rx(unsigned long data);
328/* Tx handling */
329static void ath5k_tx_processq(struct ath5k_softc *sc,
330 struct ath5k_txq *txq);
331static void ath5k_tasklet_tx(unsigned long data);
332/* Beacon handling */
333static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 334 struct ath5k_buf *bf);
fa1c114f
JS		 335static void ath5k_beacon_send(struct ath5k_softc *sc);
336static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 337static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 338
339static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
340{
341 u64 tsf = ath5k_hw_get_tsf64(ah);
342
343 if ((tsf & 0x7fff) < rstamp)
344 tsf -= 0x8000;
345
346 return (tsf & ~0x7fff) | rstamp;
347}
348
349/* Interrupt handling */
8bdd5b9c 350static int ath5k_init(struct ath5k_softc *sc, bool is_resume);
fa1c114f 351static int ath5k_stop_locked(struct ath5k_softc *sc);
8bdd5b9c 352static int ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
fa1c114f
JS		 353static irqreturn_t ath5k_intr(int irq, void *dev_id);
354static void ath5k_tasklet_reset(unsigned long data);
355
356static void ath5k_calibrate(unsigned long data);
357/* LED functions */
3a078876
BC		 358static int ath5k_init_leds(struct ath5k_softc *sc);
359static void ath5k_led_enable(struct ath5k_softc *sc);
360static void ath5k_led_off(struct ath5k_softc *sc);
361static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 362
363/*
364 * Module init/exit functions
365 */
366static int __init
367init_ath5k_pci(void)
368{
369 int ret;
370
371 ath5k_debug_init();
372
04a9e451 373 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 374 if (ret) {
375 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
376 return ret;
377 }
378
379 return 0;
380}
381
382static void __exit
383exit_ath5k_pci(void)
384{
04a9e451 385 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 386
387 ath5k_debug_finish();
388}
389
390module_init(init_ath5k_pci);
391module_exit(exit_ath5k_pci);
392
393
394/********************\
395* PCI Initialization *
396\********************/
397
398static const char *
399ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
400{
401 const char *name = "xxxxx";
402 unsigned int i;
403
404 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
405 if (srev_names[i].sr_type != type)
406 continue;
75d0edb8
NK		 407
408 if ((val & 0xf0) == srev_names[i].sr_val)
409 name = srev_names[i].sr_name;
410
411 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 412 name = srev_names[i].sr_name;
413 break;
414 }
415 }
416
417 return name;
418}
419
420static int __devinit
421ath5k_pci_probe(struct pci_dev *pdev,
422 const struct pci_device_id *id)
423{
424 void __iomem *mem;
425 struct ath5k_softc *sc;
426 struct ieee80211_hw *hw;
427 int ret;
428 u8 csz;
429
430 ret = pci_enable_device(pdev);
431 if (ret) {
432 dev_err(&pdev->dev, "can't enable device\n");
433 goto err;
434 }
435
436 /* XXX 32-bit addressing only */
437 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
438 if (ret) {
439 dev_err(&pdev->dev, "32-bit DMA not available\n");
440 goto err_dis;
441 }
442
443 /*
444 * Cache line size is used to size and align various
445 * structures used to communicate with the hardware.
446 */
447 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
448 if (csz == 0) {
449 /*
450 * Linux 2.4.18 (at least) writes the cache line size
451 * register as a 16-bit wide register which is wrong.
452 * We must have this setup properly for rx buffer
453 * DMA to work so force a reasonable value here if it
454 * comes up zero.
455 */
456 csz = L1_CACHE_BYTES / sizeof(u32);
457 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
458 }
459 /*
460 * The default setting of latency timer yields poor results,
461 * set it to the value used by other systems. It may be worth
462 * tweaking this setting more.
463 */
464 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
465
466 /* Enable bus mastering */
467 pci_set_master(pdev);
468
469 /*
470 * Disable the RETRY_TIMEOUT register (0x41) to keep
471 * PCI Tx retries from interfering with C3 CPU state.
472 */
473 pci_write_config_byte(pdev, 0x41, 0);
474
475 ret = pci_request_region(pdev, 0, "ath5k");
476 if (ret) {
477 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
478 goto err_dis;
479 }
480
481 mem = pci_iomap(pdev, 0, 0);
482 if (!mem) {
483 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
484 ret = -EIO;
485 goto err_reg;
486 }
487
488 /*
489 * Allocate hw (mac80211 main struct)
490 * and hw->priv (driver private data)
491 */
492 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
493 if (hw == NULL) {
494 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
495 ret = -ENOMEM;
496 goto err_map;
497 }
498
499 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
500
501 /* Initialize driver private data */
502 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 503 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
504 IEEE80211_HW_SIGNAL_DBM |
505 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 506
507 hw->wiphy->interface_modes =
508 BIT(NL80211_IFTYPE_STATION) |
509 BIT(NL80211_IFTYPE_ADHOC) |
510 BIT(NL80211_IFTYPE_MESH_POINT);
511
fa1c114f
JS		 512 hw->extra_tx_headroom = 2;
513 hw->channel_change_time = 5000;
fa1c114f
JS		 514 sc = hw->priv;
515 sc->hw = hw;
516 sc->pdev = pdev;
517
518 ath5k_debug_init_device(sc);
519
520 /*
521 * Mark the device as detached to avoid processing
522 * interrupts until setup is complete.
523 */
524 __set_bit(ATH_STAT_INVALID, sc->status);
525
526 sc->iobase = mem; /* So we can unmap it on detach */
527 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 528 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 529 mutex_init(&sc->lock);
530 spin_lock_init(&sc->rxbuflock);
531 spin_lock_init(&sc->txbuflock);
00482973 532 spin_lock_init(&sc->block);
fa1c114f
JS		 533
534 /* Set private data */
535 pci_set_drvdata(pdev, hw);
536
fa1c114f
JS		 537 /* Setup interrupt handler */
538 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
539 if (ret) {
540 ATH5K_ERR(sc, "request_irq failed\n");
541 goto err_free;
542 }
543
544 /* Initialize device */
545 sc->ah = ath5k_hw_attach(sc, id->driver_data);
546 if (IS_ERR(sc->ah)) {
547 ret = PTR_ERR(sc->ah);
548 goto err_irq;
549 }
550
2f7fe870
FF		 551 /* set up multi-rate retry capabilities */
552 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 553 hw->max_rates = 4;
554 hw->max_rate_tries = 11;
2f7fe870
FF		 555 }
556
fa1c114f
JS		 557 /* Finish private driver data initialization */
558 ret = ath5k_attach(pdev, hw);
559 if (ret)
560 goto err_ah;
561
562 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 563 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 564 sc->ah->ah_mac_srev,
565 sc->ah->ah_phy_revision);
566
400ec45a 567 if (!sc->ah->ah_single_chip) {
fa1c114f 568 /* Single chip radio (!RF5111) */
400ec45a
LR		 569 if (sc->ah->ah_radio_5ghz_revision &&
570 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 571 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 572 if (!test_bit(AR5K_MODE_11A,
573 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 574 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 575 ath5k_chip_name(AR5K_VERSION_RAD,
576 sc->ah->ah_radio_5ghz_revision),
577 sc->ah->ah_radio_5ghz_revision);
578 /* No 2GHz support (5110 and some
579 * 5Ghz only cards) -> report 5Ghz radio */
580 } else if (!test_bit(AR5K_MODE_11B,
581 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 582 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 583 ath5k_chip_name(AR5K_VERSION_RAD,
584 sc->ah->ah_radio_5ghz_revision),
585 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 586 /* Multiband radio */
587 } else {
588 ATH5K_INFO(sc, "RF%s multiband radio found"
589 " (0x%x)\n",
400ec45a
LR		 590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 593 }
594 }
400ec45a
LR		 595 /* Multi chip radio (RF5111 - RF2111) ->
596 * report both 2GHz/5GHz radios */
597 else if (sc->ah->ah_radio_5ghz_revision &&
598 sc->ah->ah_radio_2ghz_revision){
fa1c114f 599 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 600 ath5k_chip_name(AR5K_VERSION_RAD,
601 sc->ah->ah_radio_5ghz_revision),
602 sc->ah->ah_radio_5ghz_revision);
fa1c114f 603 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_2ghz_revision),
606 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 607 }
608 }
609
610
611 /* ready to process interrupts */
612 __clear_bit(ATH_STAT_INVALID, sc->status);
613
614 return 0;
615err_ah:
616 ath5k_hw_detach(sc->ah);
617err_irq:
618 free_irq(pdev->irq, sc);
619err_free:
fa1c114f
JS		 620 ieee80211_free_hw(hw);
621err_map:
622 pci_iounmap(pdev, mem);
623err_reg:
624 pci_release_region(pdev, 0);
625err_dis:
626 pci_disable_device(pdev);
627err:
628 return ret;
629}
630
631static void __devexit
632ath5k_pci_remove(struct pci_dev *pdev)
633{
634 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
635 struct ath5k_softc *sc = hw->priv;
636
637 ath5k_debug_finish_device(sc);
638 ath5k_detach(pdev, hw);
639 ath5k_hw_detach(sc->ah);
640 free_irq(pdev->irq, sc);
fa1c114f
JS		 641 pci_iounmap(pdev, sc->iobase);
642 pci_release_region(pdev, 0);
643 pci_disable_device(pdev);
644 ieee80211_free_hw(hw);
645}
646
647#ifdef CONFIG_PM
648static int
649ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
650{
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
653
3a078876 654 ath5k_led_off(sc);
fa1c114f 655
8bdd5b9c 656 ath5k_stop_hw(sc, true);
3e4242b9
JS		 657
658 free_irq(pdev->irq, sc);
fa1c114f
JS		 659 pci_save_state(pdev);
660 pci_disable_device(pdev);
661 pci_set_power_state(pdev, PCI_D3hot);
662
663 return 0;
664}
665
666static int
667ath5k_pci_resume(struct pci_dev *pdev)
668{
669 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
670 struct ath5k_softc *sc = hw->priv;
bc1b32d6 671 int err;
fa1c114f 672
3e4242b9 673 pci_restore_state(pdev);
fa1c114f
JS		 674
675 err = pci_enable_device(pdev);
676 if (err)
677 return err;
678
fa1c114f
JS		 679 /*
680 * Suspend/Resume resets the PCI configuration space, so we have to
681 * re-disable the RETRY_TIMEOUT register (0x41) to keep
682 * PCI Tx retries from interfering with C3 CPU state
683 */
684 pci_write_config_byte(pdev, 0x41, 0);
685
3e4242b9
JS		 686 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
687 if (err) {
688 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 689 goto err_no_irq;
3e4242b9
JS		 690 }
691
8bdd5b9c 692 err = ath5k_init(sc, true);
3e4242b9
JS		 693 if (err)
694 goto err_irq;
3a078876 695 ath5k_led_enable(sc);
fa1c114f
JS		 696
697 return 0;
3e4242b9
JS		 698err_irq:
699 free_irq(pdev->irq, sc);
37465c8a 700err_no_irq:
3e4242b9
JS		 701 pci_disable_device(pdev);
702 return err;
fa1c114f
JS		 703}
704#endif /* CONFIG_PM */
705
706
fa1c114f
JS		 707/***********************\
708* Driver Initialization *
709\***********************/
710
711static int
712ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
713{
714 struct ath5k_softc *sc = hw->priv;
715 struct ath5k_hw *ah = sc->ah;
0e149cf5 716 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 717 int ret;
718
719 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
720
721 /*
722 * Check if the MAC has multi-rate retry support.
723 * We do this by trying to setup a fake extended
724 * descriptor. MAC's that don't have support will
725 * return false w/o doing anything. MAC's that do
726 * support it will return true w/o doing anything.
727 */
c6e387a2 728 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 729 if (ret < 0)
730 goto err;
731 if (ret > 0)
fa1c114f
JS		 732 __set_bit(ATH_STAT_MRRETRY, sc->status);
733
fa1c114f
JS		 734 /*
735 * Collect the channel list. The 802.11 layer
736 * is resposible for filtering this list based
737 * on settings like the phy mode and regulatory
738 * domain restrictions.
739 */
63266a65 740 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 741 if (ret) {
742 ATH5K_ERR(sc, "can't get channels\n");
743 goto err;
744 }
745
746 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 747 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
748 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 749 else
d8ee398d 750 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 751
752 /*
753 * Allocate tx+rx descriptors and populate the lists.
754 */
755 ret = ath5k_desc_alloc(sc, pdev);
756 if (ret) {
757 ATH5K_ERR(sc, "can't allocate descriptors\n");
758 goto err;
759 }
760
761 /*
762 * Allocate hardware transmit queues: one queue for
763 * beacon frames and one data queue for each QoS
764 * priority. Note that hw functions handle reseting
765 * these queues at the needed time.
766 */
767 ret = ath5k_beaconq_setup(ah);
768 if (ret < 0) {
769 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
770 goto err_desc;
771 }
772 sc->bhalq = ret;
773
774 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
775 if (IS_ERR(sc->txq)) {
776 ATH5K_ERR(sc, "can't setup xmit queue\n");
777 ret = PTR_ERR(sc->txq);
778 goto err_bhal;
779 }
780
781 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
782 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
783 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
784 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 785
0e149cf5
BC		 786 ret = ath5k_eeprom_read_mac(ah, mac);
787 if (ret) {
788 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
789 sc->pdev->device);
790 goto err_queues;
791 }
792
fa1c114f
JS		 793 SET_IEEE80211_PERM_ADDR(hw, mac);
794 /* All MAC address bits matter for ACKs */
795 memset(sc->bssidmask, 0xff, ETH_ALEN);
796 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
797
798 ret = ieee80211_register_hw(hw);
799 if (ret) {
800 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
801 goto err_queues;
802 }
803
3a078876
BC		 804 ath5k_init_leds(sc);
805
fa1c114f
JS		 806 return 0;
807err_queues:
808 ath5k_txq_release(sc);
809err_bhal:
810 ath5k_hw_release_tx_queue(ah, sc->bhalq);
811err_desc:
812 ath5k_desc_free(sc, pdev);
813err:
814 return ret;
815}
816
817static void
818ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
819{
820 struct ath5k_softc *sc = hw->priv;
821
822 /*
823 * NB: the order of these is important:
824 * o call the 802.11 layer before detaching ath5k_hw to
825 * insure callbacks into the driver to delete global
826 * key cache entries can be handled
827 * o reclaim the tx queue data structures after calling
828 * the 802.11 layer as we'll get called back to reclaim
829 * node state and potentially want to use them
830 * o to cleanup the tx queues the hal is called, so detach
831 * it last
832 * XXX: ??? detach ath5k_hw ???
833 * Other than that, it's straightforward...
834 */
835 ieee80211_unregister_hw(hw);
836 ath5k_desc_free(sc, pdev);
837 ath5k_txq_release(sc);
838 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 839 ath5k_unregister_leds(sc);
fa1c114f
JS		 840
841 /*
842 * NB: can't reclaim these until after ieee80211_ifdetach
843 * returns because we'll get called back to reclaim node
844 * state and potentially want to use them.
845 */
846}
847
848
849
850
851/********************\
852* Channel/mode setup *
853\********************/
854
855/*
856 * Convert IEEE channel number to MHz frequency.
857 */
858static inline short
859ath5k_ieee2mhz(short chan)
860{
861 if (chan <= 14 || chan >= 27)
862 return ieee80211chan2mhz(chan);
863 else
864 return 2212 + chan * 20;
865}
866
fa1c114f
JS		 867static unsigned int
868ath5k_copy_channels(struct ath5k_hw *ah,
869 struct ieee80211_channel *channels,
870 unsigned int mode,
871 unsigned int max)
872{
d8ee398d 873 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 874
875 if (!test_bit(mode, ah->ah_modes))
876 return 0;
877
fa1c114f 878 switch (mode) {
d8ee398d
LR		 879 case AR5K_MODE_11A:
880 case AR5K_MODE_11A_TURBO:
fa1c114f 881 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 882 size = 220 ;
fa1c114f
JS		 883 chfreq = CHANNEL_5GHZ;
884 break;
d8ee398d
LR		 885 case AR5K_MODE_11B:
886 case AR5K_MODE_11G:
887 case AR5K_MODE_11G_TURBO:
888 size = 26;
fa1c114f
JS		 889 chfreq = CHANNEL_2GHZ;
890 break;
891 default:
892 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
893 return 0;
894 }
895
896 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 897 ch = i + 1 ;
898 freq = ath5k_ieee2mhz(ch);
fa1c114f 899
d8ee398d
LR		 900 /* Check if channel is supported by the chipset */
901 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 902 continue;
903
d8ee398d
LR		 904 /* Write channel info and increment counter */
905 channels[count].center_freq = freq;
a3f4b914
LR		 906 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
907 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 908 switch (mode) {
909 case AR5K_MODE_11A:
910 case AR5K_MODE_11G:
911 channels[count].hw_value = chfreq | CHANNEL_OFDM;
912 break;
913 case AR5K_MODE_11A_TURBO:
914 case AR5K_MODE_11G_TURBO:
915 channels[count].hw_value = chfreq |
916 CHANNEL_OFDM | CHANNEL_TURBO;
917 break;
918 case AR5K_MODE_11B:
d8ee398d
LR		 919 channels[count].hw_value = CHANNEL_B;
920 }
fa1c114f 921
fa1c114f
JS		 922 count++;
923 max--;
924 }
925
926 return count;
927}
928
63266a65
BR		 929static void
930ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
931{
932 u8 i;
933
934 for (i = 0; i < AR5K_MAX_RATES; i++)
935 sc->rate_idx[b->band][i] = -1;
936
937 for (i = 0; i < b->n_bitrates; i++) {
938 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
939 if (b->bitrates[i].hw_value_short)
940 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
941 }
942}
943
d8ee398d 944static int
63266a65 945ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 946{
947 struct ath5k_softc *sc = hw->priv;
d8ee398d 948 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 949 struct ieee80211_supported_band *sband;
950 int max_c, count_c = 0;
951 int i;
fa1c114f 952
d8ee398d 953 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 954 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 955
956 /* 2GHz band */
63266a65
BR		 957 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
958 sband->band = IEEE80211_BAND_2GHZ;
959 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 960
63266a65
BR		 961 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
962 /* G mode */
963 memcpy(sband->bitrates, &ath5k_rates[0],
964 sizeof(struct ieee80211_rate) * 12);
965 sband->n_bitrates = 12;
fa1c114f 966
d8ee398d 967 sband->channels = sc->channels;
d8ee398d 968 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 969 AR5K_MODE_11G, max_c);
fa1c114f 970
63266a65 971 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 972 count_c = sband->n_channels;
63266a65
BR		 973 max_c -= count_c;
974 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
975 /* B mode */
976 memcpy(sband->bitrates, &ath5k_rates[0],
977 sizeof(struct ieee80211_rate) * 4);
978 sband->n_bitrates = 4;
979
980 /* 5211 only supports B rates and uses 4bit rate codes
981 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
982 * fix them up here:
983 */
984 if (ah->ah_version == AR5K_AR5211) {
985 for (i = 0; i < 4; i++) {
986 sband->bitrates[i].hw_value =
987 sband->bitrates[i].hw_value & 0xF;
988 sband->bitrates[i].hw_value_short =
989 sband->bitrates[i].hw_value_short & 0xF;
990 }
991 }
fa1c114f 992
63266a65
BR		 993 sband->channels = sc->channels;
994 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
995 AR5K_MODE_11B, max_c);
d8ee398d 996
63266a65
BR		 997 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
998 count_c = sband->n_channels;
d8ee398d 999 max_c -= count_c;
fa1c114f 1000 }
63266a65 1001 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1002
63266a65 1003 /* 5GHz band, A mode */
400ec45a 1004 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1005 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1006 sband->band = IEEE80211_BAND_5GHZ;
1007 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1008
63266a65
BR		 1009 memcpy(sband->bitrates, &ath5k_rates[4],
1010 sizeof(struct ieee80211_rate) * 8);
1011 sband->n_bitrates = 8;
fa1c114f 1012
63266a65 1013 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1014 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1015 AR5K_MODE_11A, max_c);
1016
d8ee398d
LR		 1017 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1018 }
63266a65 1019 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1020
b446197c 1021 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1022
1023 return 0;
fa1c114f
JS		 1024}
1025
1026/*
1027 * Set/change channels. If the channel is really being changed,
1028 * it's done by reseting the chip. To accomplish this we must
1029 * first cleanup any pending DMA, then restart stuff after a la
1030 * ath5k_init.
1031 */
1032static int
1033ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034{
d8ee398d
LR		 1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1037
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1040
1041 sc->curchan = chan;
1042 sc->curband = &sc->sbands[chan->band];
fa1c114f 1043
fa1c114f
JS		 1044 /*
1045 * To switch channels clear any pending DMA operations;
1046 * wait long enough for the RX fifo to drain, reset the
1047 * hardware at the new frequency, and then re-enable
1048 * the relevant bits of the h/w.
1049 */
d7dc1003 1050 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1051 }
1052
1053 return 0;
1054}
1055
1056static void
1057ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1058{
fa1c114f 1059 sc->curmode = mode;
d8ee398d 1060
400ec45a 1061 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1062 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1063 } else {
1064 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1065 }
fa1c114f
JS		 1066}
1067
1068static void
1069ath5k_mode_setup(struct ath5k_softc *sc)
1070{
1071 struct ath5k_hw *ah = sc->ah;
1072 u32 rfilt;
1073
1074 /* configure rx filter */
1075 rfilt = sc->filter_flags;
1076 ath5k_hw_set_rx_filter(ah, rfilt);
1077
1078 if (ath5k_hw_hasbssidmask(ah))
1079 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1080
1081 /* configure operational mode */
1082 ath5k_hw_set_opmode(ah);
1083
1084 ath5k_hw_set_mcast_filter(ah, 0, 0);
1085 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1086}
1087
d8ee398d 1088static inline int
63266a65
BR		 1089ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1090{
1091 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1092 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1093}
1094
fa1c114f
JS		 1095/***************\
1096* Buffers setup *
1097\***************/
1098
1099static int
1100ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1101{
1102 struct ath5k_hw *ah = sc->ah;
1103 struct sk_buff *skb = bf->skb;
1104 struct ath5k_desc *ds;
1105
1106 if (likely(skb == NULL)) {
1107 unsigned int off;
1108
1109 /*
1110 * Allocate buffer with headroom_needed space for the
1111 * fake physical layer header at the start.
1112 */
1113 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1114 if (unlikely(skb == NULL)) {
1115 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1116 sc->rxbufsize + sc->cachelsz - 1);
1117 return -ENOMEM;
1118 }
1119 /*
1120 * Cache-line-align. This is important (for the
1121 * 5210 at least) as not doing so causes bogus data
1122 * in rx'd frames.
1123 */
1124 off = ((unsigned long)skb->data) % sc->cachelsz;
1125 if (off != 0)
1126 skb_reserve(skb, sc->cachelsz - off);
1127
1128 bf->skb = skb;
1129 bf->skbaddr = pci_map_single(sc->pdev,
1130 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1131 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1132 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1133 dev_kfree_skb(skb);
1134 bf->skb = NULL;
1135 return -ENOMEM;
1136 }
1137 }
1138
1139 /*
1140 * Setup descriptors. For receive we always terminate
1141 * the descriptor list with a self-linked entry so we'll
1142 * not get overrun under high load (as can happen with a
1143 * 5212 when ANI processing enables PHY error frames).
1144 *
1145 * To insure the last descriptor is self-linked we create
1146 * each descriptor as self-linked and add it to the end. As
1147 * each additional descriptor is added the previous self-linked
1148 * entry is ``fixed'' naturally. This should be safe even
1149 * if DMA is happening. When processing RX interrupts we
1150 * never remove/process the last, self-linked, entry on the
1151 * descriptor list. This insures the hardware always has
1152 * someplace to write a new frame.
1153 */
1154 ds = bf->desc;
1155 ds->ds_link = bf->daddr; /* link to self */
1156 ds->ds_data = bf->skbaddr;
c6e387a2 1157 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1158 skb_tailroom(skb), /* buffer size */
1159 0);
1160
1161 if (sc->rxlink != NULL)
1162 *sc->rxlink = bf->daddr;
1163 sc->rxlink = &ds->ds_link;
1164 return 0;
1165}
1166
1167static int
e039fa4a 1168ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1169{
1170 struct ath5k_hw *ah = sc->ah;
1171 struct ath5k_txq *txq = sc->txq;
1172 struct ath5k_desc *ds = bf->desc;
1173 struct sk_buff *skb = bf->skb;
a888d52d 1174 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1175 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1176 struct ieee80211_rate *rate;
1177 unsigned int mrr_rate[3], mrr_tries[3];
1178 int i, ret;
fa1c114f
JS		 1179
1180 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1181
fa1c114f
JS		 1182 /* XXX endianness */
1183 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1184 PCI_DMA_TODEVICE);
1185
e039fa4a 1186 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1187 flags |= AR5K_TXDESC_NOACK;
1188
281c56dd 1189 pktlen = skb->len;
fa1c114f 1190
d0f09804 1191 if (info->control.hw_key) {
e039fa4a 1192 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1193 pktlen += info->control.hw_key->icv_len;
fa1c114f 1194 }
fa1c114f
JS		 1195 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1196 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1197 (sc->power_level * 2),
e039fa4a 1198 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
e6a9854b 1199 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1200 if (ret)
1201 goto err_unmap;
1202
2f7fe870
FF		 1203 memset(mrr_rate, 0, sizeof(mrr_rate));
1204 memset(mrr_tries, 0, sizeof(mrr_tries));
1205 for (i = 0; i < 3; i++) {
1206 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1207 if (!rate)
1208 break;
1209
1210 mrr_rate[i] = rate->hw_value;
e6a9854b 1211 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1212 }
1213
1214 ah->ah_setup_mrr_tx_desc(ah, ds,
1215 mrr_rate[0], mrr_tries[0],
1216 mrr_rate[1], mrr_tries[1],
1217 mrr_rate[2], mrr_tries[2]);
1218
fa1c114f
JS		 1219 ds->ds_link = 0;
1220 ds->ds_data = bf->skbaddr;
1221
1222 spin_lock_bh(&txq->lock);
1223 list_add_tail(&bf->list, &txq->q);
57ffc589 1224 sc->tx_stats[txq->qnum].len++;
fa1c114f 1225 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1226 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1227 else /* no, so only link it */
1228 *txq->link = bf->daddr;
1229
1230 txq->link = &ds->ds_link;
c6e387a2 1231 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1232 mmiowb();
fa1c114f
JS		 1233 spin_unlock_bh(&txq->lock);
1234
1235 return 0;
1236err_unmap:
1237 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1238 return ret;
1239}
1240
1241/*******************\
1242* Descriptors setup *
1243\*******************/
1244
1245static int
1246ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1247{
1248 struct ath5k_desc *ds;
1249 struct ath5k_buf *bf;
1250 dma_addr_t da;
1251 unsigned int i;
1252 int ret;
1253
1254 /* allocate descriptors */
1255 sc->desc_len = sizeof(struct ath5k_desc) *
1256 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1257 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1258 if (sc->desc == NULL) {
1259 ATH5K_ERR(sc, "can't allocate descriptors\n");
1260 ret = -ENOMEM;
1261 goto err;
1262 }
1263 ds = sc->desc;
1264 da = sc->desc_daddr;
1265 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1266 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1267
1268 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1269 sizeof(struct ath5k_buf), GFP_KERNEL);
1270 if (bf == NULL) {
1271 ATH5K_ERR(sc, "can't allocate bufptr\n");
1272 ret = -ENOMEM;
1273 goto err_free;
1274 }
1275 sc->bufptr = bf;
1276
1277 INIT_LIST_HEAD(&sc->rxbuf);
1278 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1279 bf->desc = ds;
1280 bf->daddr = da;
1281 list_add_tail(&bf->list, &sc->rxbuf);
1282 }
1283
1284 INIT_LIST_HEAD(&sc->txbuf);
1285 sc->txbuf_len = ATH_TXBUF;
1286 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1287 da += sizeof(*ds)) {
1288 bf->desc = ds;
1289 bf->daddr = da;
1290 list_add_tail(&bf->list, &sc->txbuf);
1291 }
1292
1293 /* beacon buffer */
1294 bf->desc = ds;
1295 bf->daddr = da;
1296 sc->bbuf = bf;
1297
1298 return 0;
1299err_free:
1300 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1301err:
1302 sc->desc = NULL;
1303 return ret;
1304}
1305
1306static void
1307ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1308{
1309 struct ath5k_buf *bf;
1310
1311 ath5k_txbuf_free(sc, sc->bbuf);
1312 list_for_each_entry(bf, &sc->txbuf, list)
1313 ath5k_txbuf_free(sc, bf);
1314 list_for_each_entry(bf, &sc->rxbuf, list)
1315 ath5k_txbuf_free(sc, bf);
1316
1317 /* Free memory associated with all descriptors */
1318 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1319
1320 kfree(sc->bufptr);
1321 sc->bufptr = NULL;
1322}
1323
1324
1325
1326
1327
1328/**************\
1329* Queues setup *
1330\**************/
1331
1332static struct ath5k_txq *
1333ath5k_txq_setup(struct ath5k_softc *sc,
1334 int qtype, int subtype)
1335{
1336 struct ath5k_hw *ah = sc->ah;
1337 struct ath5k_txq *txq;
1338 struct ath5k_txq_info qi = {
1339 .tqi_subtype = subtype,
1340 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1341 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1342 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1343 };
1344 int qnum;
1345
1346 /*
1347 * Enable interrupts only for EOL and DESC conditions.
1348 * We mark tx descriptors to receive a DESC interrupt
1349 * when a tx queue gets deep; otherwise waiting for the
1350 * EOL to reap descriptors. Note that this is done to
1351 * reduce interrupt load and this only defers reaping
1352 * descriptors, never transmitting frames. Aside from
1353 * reducing interrupts this also permits more concurrency.
1354 * The only potential downside is if the tx queue backs
1355 * up in which case the top half of the kernel may backup
1356 * due to a lack of tx descriptors.
1357 */
1358 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1359 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1360 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1361 if (qnum < 0) {
1362 /*
1363 * NB: don't print a message, this happens
1364 * normally on parts with too few tx queues
1365 */
1366 return ERR_PTR(qnum);
1367 }
1368 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1369 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1370 qnum, ARRAY_SIZE(sc->txqs));
1371 ath5k_hw_release_tx_queue(ah, qnum);
1372 return ERR_PTR(-EINVAL);
1373 }
1374 txq = &sc->txqs[qnum];
1375 if (!txq->setup) {
1376 txq->qnum = qnum;
1377 txq->link = NULL;
1378 INIT_LIST_HEAD(&txq->q);
1379 spin_lock_init(&txq->lock);
1380 txq->setup = true;
1381 }
1382 return &sc->txqs[qnum];
1383}
1384
1385static int
1386ath5k_beaconq_setup(struct ath5k_hw *ah)
1387{
1388 struct ath5k_txq_info qi = {
1389 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1390 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1391 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1392 /* NB: for dynamic turbo, don't enable any other interrupts */
1393 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1394 };
1395
1396 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1397}
1398
1399static int
1400ath5k_beaconq_config(struct ath5k_softc *sc)
1401{
1402 struct ath5k_hw *ah = sc->ah;
1403 struct ath5k_txq_info qi;
1404 int ret;
1405
1406 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1407 if (ret)
1408 return ret;
05c914fe
JB		 1409 if (sc->opmode == NL80211_IFTYPE_AP ||
1410 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1411 /*
1412 * Always burst out beacon and CAB traffic
1413 * (aifs = cwmin = cwmax = 0)
1414 */
1415 qi.tqi_aifs = 0;
1416 qi.tqi_cw_min = 0;
1417 qi.tqi_cw_max = 0;
05c914fe 1418 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1419 /*
1420 * Adhoc mode; backoff between 0 and (2 * cw_min).
1421 */
1422 qi.tqi_aifs = 0;
1423 qi.tqi_cw_min = 0;
1424 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1425 }
1426
6d91e1d8
BR		 1427 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1428 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1429 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1430
c6e387a2 1431 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1432 if (ret) {
1433 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1434 "hardware queue!\n", __func__);
1435 return ret;
1436 }
1437
1438 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1439}
1440
1441static void
1442ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1443{
1444 struct ath5k_buf *bf, *bf0;
1445
1446 /*
1447 * NB: this assumes output has been stopped and
1448 * we do not need to block ath5k_tx_tasklet
1449 */
1450 spin_lock_bh(&txq->lock);
1451 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1452 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1453
1454 ath5k_txbuf_free(sc, bf);
1455
1456 spin_lock_bh(&sc->txbuflock);
57ffc589 1457 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1458 list_move_tail(&bf->list, &sc->txbuf);
1459 sc->txbuf_len++;
1460 spin_unlock_bh(&sc->txbuflock);
1461 }
1462 txq->link = NULL;
1463 spin_unlock_bh(&txq->lock);
1464}
1465
1466/*
1467 * Drain the transmit queues and reclaim resources.
1468 */
1469static void
1470ath5k_txq_cleanup(struct ath5k_softc *sc)
1471{
1472 struct ath5k_hw *ah = sc->ah;
1473 unsigned int i;
1474
1475 /* XXX return value */
1476 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1477 /* don't touch the hardware if marked invalid */
1478 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1479 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1480 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1481 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1482 if (sc->txqs[i].setup) {
1483 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1484 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1485 "link %p\n",
1486 sc->txqs[i].qnum,
c6e387a2 1487 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1488 sc->txqs[i].qnum),
1489 sc->txqs[i].link);
1490 }
1491 }
36d6825b 1492 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1493
1494 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1495 if (sc->txqs[i].setup)
1496 ath5k_txq_drainq(sc, &sc->txqs[i]);
1497}
1498
1499static void
1500ath5k_txq_release(struct ath5k_softc *sc)
1501{
1502 struct ath5k_txq *txq = sc->txqs;
1503 unsigned int i;
1504
1505 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1506 if (txq->setup) {
1507 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1508 txq->setup = false;
1509 }
1510}
1511
1512
1513
1514
1515/*************\
1516* RX Handling *
1517\*************/
1518
1519/*
1520 * Enable the receive h/w following a reset.
1521 */
1522static int
1523ath5k_rx_start(struct ath5k_softc *sc)
1524{
1525 struct ath5k_hw *ah = sc->ah;
1526 struct ath5k_buf *bf;
1527 int ret;
1528
1529 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1530
1531 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1532 sc->cachelsz, sc->rxbufsize);
1533
1534 sc->rxlink = NULL;
1535
1536 spin_lock_bh(&sc->rxbuflock);
1537 list_for_each_entry(bf, &sc->rxbuf, list) {
1538 ret = ath5k_rxbuf_setup(sc, bf);
1539 if (ret != 0) {
1540 spin_unlock_bh(&sc->rxbuflock);
1541 goto err;
1542 }
1543 }
1544 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1545 spin_unlock_bh(&sc->rxbuflock);
1546
c6e387a2
NK		 1547 ath5k_hw_set_rxdp(ah, bf->daddr);
1548 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1549 ath5k_mode_setup(sc); /* set filters, etc. */
1550 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1551
1552 return 0;
1553err:
1554 return ret;
1555}
1556
1557/*
1558 * Disable the receive h/w in preparation for a reset.
1559 */
1560static void
1561ath5k_rx_stop(struct ath5k_softc *sc)
1562{
1563 struct ath5k_hw *ah = sc->ah;
1564
c6e387a2 1565 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1566 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1567 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1568
1569 ath5k_debug_printrxbuffs(sc, ah);
1570
1571 sc->rxlink = NULL; /* just in case */
1572}
1573
1574static unsigned int
1575ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1576 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1577{
1578 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1579 unsigned int keyix, hlen;
fa1c114f 1580
b47f407b
BR		 1581 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1582 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1583 return RX_FLAG_DECRYPTED;
1584
1585 /* Apparently when a default key is used to decrypt the packet
1586 the hw does not set the index used to decrypt. In such cases
1587 get the index from the packet. */
798ee985 1588 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1589 if (ieee80211_has_protected(hdr->frame_control) &&
1590 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1591 skb->len >= hlen + 4) {
fa1c114f
JS		 1592 keyix = skb->data[hlen + 3] >> 6;
1593
1594 if (test_bit(keyix, sc->keymap))
1595 return RX_FLAG_DECRYPTED;
1596 }
1597
1598 return 0;
1599}
1600
036cd1ec
BR		 1601
1602static void
6ba81c2c
BR		 1603ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1604 struct ieee80211_rx_status *rxs)
036cd1ec 1605{
6ba81c2c 1606 u64 tsf, bc_tstamp;
036cd1ec
BR		 1607 u32 hw_tu;
1608 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1609
24b56e70 1610 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1611 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1612 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1613 /*
6ba81c2c
BR		 1614 * Received an IBSS beacon with the same BSSID. Hardware *must*
1615 * have updated the local TSF. We have to work around various
1616 * hardware bugs, though...
036cd1ec 1617 */
6ba81c2c
BR		 1618 tsf = ath5k_hw_get_tsf64(sc->ah);
1619 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1620 hw_tu = TSF_TO_TU(tsf);
1621
1622 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1623 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1624 (unsigned long long)bc_tstamp,
1625 (unsigned long long)rxs->mactime,
1626 (unsigned long long)(rxs->mactime - bc_tstamp),
1627 (unsigned long long)tsf);
6ba81c2c
BR		 1628
1629 /*
1630 * Sometimes the HW will give us a wrong tstamp in the rx
1631 * status, causing the timestamp extension to go wrong.
1632 * (This seems to happen especially with beacon frames bigger
1633 * than 78 byte (incl. FCS))
1634 * But we know that the receive timestamp must be later than the
1635 * timestamp of the beacon since HW must have synced to that.
1636 *
1637 * NOTE: here we assume mactime to be after the frame was
1638 * received, not like mac80211 which defines it at the start.
1639 */
1640 if (bc_tstamp > rxs->mactime) {
036cd1ec 1641 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1642 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1643 (unsigned long long)rxs->mactime,
1644 (unsigned long long)tsf);
6ba81c2c 1645 rxs->mactime = tsf;
036cd1ec 1646 }
6ba81c2c
BR		 1647
1648 /*
1649 * Local TSF might have moved higher than our beacon timers,
1650 * in that case we have to update them to continue sending
1651 * beacons. This also takes care of synchronizing beacon sending
1652 * times with other stations.
1653 */
1654 if (hw_tu >= sc->nexttbtt)
1655 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1656 }
1657}
1658
1659
fa1c114f
JS		 1660static void
1661ath5k_tasklet_rx(unsigned long data)
1662{
1663 struct ieee80211_rx_status rxs = {};
b47f407b 1664 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1665 struct sk_buff *skb;
1666 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1667 struct ath5k_buf *bf, *bf_last;
fa1c114f 1668 struct ath5k_desc *ds;
fa1c114f
JS		 1669 int ret;
1670 int hdrlen;
0fe45b1d 1671 int padsize;
fa1c114f
JS		 1672
1673 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1674 if (list_empty(&sc->rxbuf)) {
1675 ATH5K_WARN(sc, "empty rx buf pool\n");
1676 goto unlock;
1677 }
1678 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1679 do {
d6894b5b
BC		 1680 rxs.flag = 0;
1681
fa1c114f
JS		 1682 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1683 BUG_ON(bf->skb == NULL);
1684 skb = bf->skb;
1685 ds = bf->desc;
1686
3a0f2c87
JS		 1687 /*
1688 * last buffer must not be freed to ensure proper hardware
1689 * function. When the hardware finishes also a packet next to
1690 * it, we are sure, it doesn't use it anymore and we can go on.
1691 */
1692 if (bf_last == bf)
1693 bf->flags |= 1;
1694 if (bf->flags) {
1695 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1696 struct ath5k_buf, list);
1697 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1698 &rs);
1699 if (ret)
1700 break;
1701 bf->flags &= ~1;
1702 /* skip the overwritten one (even status is martian) */
1703 goto next;
1704 }
fa1c114f 1705
b47f407b 1706 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1707 if (unlikely(ret == -EINPROGRESS))
1708 break;
1709 else if (unlikely(ret)) {
1710 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1711 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1712 return;
1713 }
1714
b47f407b 1715 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1716 ATH5K_WARN(sc, "unsupported jumbo\n");
1717 goto next;
1718 }
1719
b47f407b
BR		 1720 if (unlikely(rs.rs_status)) {
1721 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1722 goto next;
b47f407b 1723 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1724 /*
1725 * Decrypt error. If the error occurred
1726 * because there was no hardware key, then
1727 * let the frame through so the upper layers
1728 * can process it. This is necessary for 5210
1729 * parts which have no way to setup a ``clear''
1730 * key cache entry.
1731 *
1732 * XXX do key cache faulting
1733 */
b47f407b
BR		 1734 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1735 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1736 goto accept;
1737 }
b47f407b 1738 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1739 rxs.flag |= RX_FLAG_MMIC_ERROR;
1740 goto accept;
1741 }
1742
1743 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1744 if ((rs.rs_status &
1745 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1746 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1747 goto next;
1748 }
1749accept:
fa1c114f
JS		 1750 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1751 PCI_DMA_FROMDEVICE);
1752 bf->skb = NULL;
1753
b47f407b 1754 skb_put(skb, rs.rs_datalen);
fa1c114f 1755
0fe45b1d
BP		 1756 /* The MAC header is padded to have 32-bit boundary if the
1757 * packet payload is non-zero. The general calculation for
1758 * padsize would take into account odd header lengths:
1759 * padsize = (4 - hdrlen % 4) % 4; However, since only
1760 * even-length headers are used, padding can only be 0 or 2
1761 * bytes and we can optimize this a bit. In addition, we must
1762 * not try to remove padding from short control frames that do
1763 * not have payload. */
fa1c114f 1764 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1765 padsize = ath5k_pad_size(hdrlen);
1766 if (padsize) {
0fe45b1d
BP		 1767 memmove(skb->data + padsize, skb->data, hdrlen);
1768 skb_pull(skb, padsize);
fa1c114f
JS		 1769 }
1770
c0e1899b
BR		 1771 /*
1772 * always extend the mac timestamp, since this information is
1773 * also needed for proper IBSS merging.
1774 *
1775 * XXX: it might be too late to do it here, since rs_tstamp is
1776 * 15bit only. that means TSF extension has to be done within
1777 * 32768usec (about 32ms). it might be necessary to move this to
1778 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1779 *
1780 * Unfortunately we don't know when the hardware takes the rx
1781 * timestamp (beginning of phy frame, data frame, end of rx?).
1782 * The only thing we know is that it is hardware specific...
1783 * On AR5213 it seems the rx timestamp is at the end of the
1784 * frame, but i'm not sure.
1785 *
1786 * NOTE: mac80211 defines mactime at the beginning of the first
1787 * data symbol. Since we don't have any time references it's
1788 * impossible to comply to that. This affects IBSS merge only
1789 * right now, so it's not too bad...
c0e1899b 1790 */
b47f407b 1791 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1792 rxs.flag |= RX_FLAG_TSFT;
1793
d8ee398d
LR		 1794 rxs.freq = sc->curchan->center_freq;
1795 rxs.band = sc->curband->band;
fa1c114f 1796
fa1c114f 1797 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1798 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1799
1800 /* An rssi of 35 indicates you should be able use
1801 * 54 Mbps reliably. A more elaborate scheme can be used
1802 * here but it requires a map of SNR/throughput for each
1803 * possible mode used */
1804 rxs.qual = rs.rs_rssi * 100 / 35;
1805
1806 /* rssi can be more than 35 though, anything above that
1807 * should be considered at 100% */
1808 if (rxs.qual > 100)
1809 rxs.qual = 100;
fa1c114f 1810
b47f407b
BR		 1811 rxs.antenna = rs.rs_antenna;
1812 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1813 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1814
06303352
BR		 1815 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1816 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1817 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1818
fa1c114f
JS		 1819 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1820
036cd1ec 1821 /* check beacons in IBSS mode */
05c914fe 1822 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1823 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1824
fa1c114f 1825 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1826next:
1827 list_move_tail(&bf->list, &sc->rxbuf);
1828 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1829unlock:
fa1c114f
JS		 1830 spin_unlock(&sc->rxbuflock);
1831}
1832
1833
1834
1835
1836/*************\
1837* TX Handling *
1838\*************/
1839
1840static void
1841ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1842{
b47f407b 1843 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1844 struct ath5k_buf *bf, *bf0;
1845 struct ath5k_desc *ds;
1846 struct sk_buff *skb;
e039fa4a 1847 struct ieee80211_tx_info *info;
2f7fe870 1848 int i, ret;
fa1c114f
JS		 1849
1850 spin_lock(&txq->lock);
1851 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1852 ds = bf->desc;
1853
b47f407b 1854 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1855 if (unlikely(ret == -EINPROGRESS))
1856 break;
1857 else if (unlikely(ret)) {
1858 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1859 ret, txq->qnum);
1860 break;
1861 }
1862
1863 skb = bf->skb;
a888d52d 1864 info = IEEE80211_SKB_CB(skb);
fa1c114f 1865 bf->skb = NULL;
e039fa4a 1866
fa1c114f
JS		 1867 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1868 PCI_DMA_TODEVICE);
1869
e6a9854b 1870 ieee80211_tx_info_clear_status(info);
2f7fe870 1871 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1872 struct ieee80211_tx_rate *r =
1873 &info->status.rates[i];
2f7fe870
FF		 1874
1875 if (ts.ts_rate[i]) {
e6a9854b
JB		 1876 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1877 r->count = ts.ts_retry[i];
2f7fe870 1878 } else {
e6a9854b
JB		 1879 r->idx = -1;
1880 r->count = 0;
2f7fe870
FF		 1881 }
1882 }
1883
e6a9854b
JB		 1884 /* count the successful attempt as well */
1885 info->status.rates[ts.ts_final_idx].count++;
1886
b47f407b 1887 if (unlikely(ts.ts_status)) {
fa1c114f 1888 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1889 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1890 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1891 } else {
e039fa4a
JB		 1892 info->flags |= IEEE80211_TX_STAT_ACK;
1893 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1894 }
1895
e039fa4a 1896 ieee80211_tx_status(sc->hw, skb);
57ffc589 1897 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1898
1899 spin_lock(&sc->txbuflock);
57ffc589 1900 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1901 list_move_tail(&bf->list, &sc->txbuf);
1902 sc->txbuf_len++;
1903 spin_unlock(&sc->txbuflock);
1904 }
1905 if (likely(list_empty(&txq->q)))
1906 txq->link = NULL;
1907 spin_unlock(&txq->lock);
1908 if (sc->txbuf_len > ATH_TXBUF / 5)
1909 ieee80211_wake_queues(sc->hw);
1910}
1911
1912static void
1913ath5k_tasklet_tx(unsigned long data)
1914{
1915 struct ath5k_softc *sc = (void *)data;
1916
1917 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1918}
1919
1920
fa1c114f
JS		 1921/*****************\
1922* Beacon handling *
1923\*****************/
1924
1925/*
1926 * Setup the beacon frame for transmit.
1927 */
1928static int
e039fa4a 1929ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1930{
1931 struct sk_buff *skb = bf->skb;
a888d52d 1932 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1933 struct ath5k_hw *ah = sc->ah;
1934 struct ath5k_desc *ds;
1935 int ret, antenna = 0;
1936 u32 flags;
1937
1938 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1939 PCI_DMA_TODEVICE);
1940 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1941 "skbaddr %llx\n", skb, skb->data, skb->len,
1942 (unsigned long long)bf->skbaddr);
8d8bb39b 1943 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1944 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1945 return -EIO;
1946 }
1947
1948 ds = bf->desc;
1949
1950 flags = AR5K_TXDESC_NOACK;
05c914fe 1951 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1952 ds->ds_link = bf->daddr; /* self-linked */
1953 flags |= AR5K_TXDESC_VEOL;
1954 /*
1955 * Let hardware handle antenna switching if txantenna is not set
1956 */
1957 } else {
1958 ds->ds_link = 0;
1959 /*
1960 * Switch antenna every 4 beacons if txantenna is not set
1961 * XXX assumes two antennas
1962 */
1963 if (antenna == 0)
1964 antenna = sc->bsent & 4 ? 2 : 1;
1965 }
1966
1967 ds->ds_data = bf->skbaddr;
281c56dd 1968 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1969 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1970 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1971 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1972 1, AR5K_TXKEYIX_INVALID,
400ec45a 1973 antenna, flags, 0, 0);
fa1c114f
JS		 1974 if (ret)
1975 goto err_unmap;
1976
1977 return 0;
1978err_unmap:
1979 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1980 return ret;
1981}
1982
1983/*
1984 * Transmit a beacon frame at SWBA. Dynamic updates to the
1985 * frame contents are done as needed and the slot time is
1986 * also adjusted based on current state.
1987 *
1988 * this is usually called from interrupt context (ath5k_intr())
1989 * but also from ath5k_beacon_config() in IBSS mode which in turn
1990 * can be called from a tasklet and user context
1991 */
1992static void
1993ath5k_beacon_send(struct ath5k_softc *sc)
1994{
1995 struct ath5k_buf *bf = sc->bbuf;
1996 struct ath5k_hw *ah = sc->ah;
1997
be9b7259 1998 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1999
05c914fe
JB		 2000 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2001 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2002 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2003 return;
2004 }
2005 /*
2006 * Check if the previous beacon has gone out. If
2007 * not don't don't try to post another, skip this
2008 * period and wait for the next. Missed beacons
2009 * indicate a problem and should not occur. If we
2010 * miss too many consecutive beacons reset the device.
2011 */
2012 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2013 sc->bmisscount++;
be9b7259 2014 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2015 "missed %u consecutive beacons\n", sc->bmisscount);
2016 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2017 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2018 "stuck beacon time (%u missed)\n",
2019 sc->bmisscount);
2020 tasklet_schedule(&sc->restq);
2021 }
2022 return;
2023 }
2024 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2025 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2026 "resume beacon xmit after %u misses\n",
2027 sc->bmisscount);
2028 sc->bmisscount = 0;
2029 }
2030
2031 /*
2032 * Stop any current dma and put the new frame on the queue.
2033 * This should never fail since we check above that no frames
2034 * are still pending on the queue.
2035 */
2036 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2037 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2038 /* NB: hw still stops DMA, so proceed */
2039 }
fa1c114f 2040
c6e387a2
NK		 2041 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2042 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2043 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2044 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2045
2046 sc->bsent++;
2047}
2048
2049
9804b98d
BR		 2050/**
2051 * ath5k_beacon_update_timers - update beacon timers
2052 *
2053 * @sc: struct ath5k_softc pointer we are operating on
2054 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2055 * beacon timer update based on the current HW TSF.
2056 *
2057 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2058 * of a received beacon or the current local hardware TSF and write it to the
2059 * beacon timer registers.
2060 *
2061 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2062 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2063 * when we otherwise know we have to update the timers, but we keep it in this
2064 * function to have it all together in one place.
2065 */
fa1c114f 2066static void
9804b98d 2067ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2068{
2069 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2070 u32 nexttbtt, intval, hw_tu, bc_tu;
2071 u64 hw_tsf;
fa1c114f
JS		 2072
2073 intval = sc->bintval & AR5K_BEACON_PERIOD;
2074 if (WARN_ON(!intval))
2075 return;
2076
9804b98d
BR		 2077 /* beacon TSF converted to TU */
2078 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2079
9804b98d
BR		 2080 /* current TSF converted to TU */
2081 hw_tsf = ath5k_hw_get_tsf64(ah);
2082 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2083
9804b98d
BR		 2084#define FUDGE 3
2085 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2086 if (bc_tsf == -1) {
2087 /*
2088 * no beacons received, called internally.
2089 * just need to refresh timers based on HW TSF.
2090 */
2091 nexttbtt = roundup(hw_tu + FUDGE, intval);
2092 } else if (bc_tsf == 0) {
2093 /*
2094 * no beacon received, probably called by ath5k_reset_tsf().
2095 * reset TSF to start with 0.
2096 */
2097 nexttbtt = intval;
2098 intval |= AR5K_BEACON_RESET_TSF;
2099 } else if (bc_tsf > hw_tsf) {
2100 /*
2101 * beacon received, SW merge happend but HW TSF not yet updated.
2102 * not possible to reconfigure timers yet, but next time we
2103 * receive a beacon with the same BSSID, the hardware will
2104 * automatically update the TSF and then we need to reconfigure
2105 * the timers.
2106 */
2107 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2108 "need to wait for HW TSF sync\n");
2109 return;
2110 } else {
2111 /*
2112 * most important case for beacon synchronization between STA.
2113 *
2114 * beacon received and HW TSF has been already updated by HW.
2115 * update next TBTT based on the TSF of the beacon, but make
2116 * sure it is ahead of our local TSF timer.
2117 */
2118 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2119 }
2120#undef FUDGE
fa1c114f 2121
036cd1ec
BR		 2122 sc->nexttbtt = nexttbtt;
2123
fa1c114f 2124 intval |= AR5K_BEACON_ENA;
fa1c114f 2125 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2126
2127 /*
2128 * debugging output last in order to preserve the time critical aspect
2129 * of this function
2130 */
2131 if (bc_tsf == -1)
2132 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133 "reconfigured timers based on HW TSF\n");
2134 else if (bc_tsf == 0)
2135 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2136 "reset HW TSF and timers\n");
2137 else
2138 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2139 "updated timers based on beacon TSF\n");
2140
2141 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2142 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2143 (unsigned long long) bc_tsf,
2144 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2145 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2146 intval & AR5K_BEACON_PERIOD,
2147 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2148 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2149}
2150
2151
036cd1ec
BR		 2152/**
2153 * ath5k_beacon_config - Configure the beacon queues and interrupts
2154 *
2155 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2156 *
2157 * When operating in station mode we want to receive a BMISS interrupt when we
2158 * stop seeing beacons from the AP we've associated with so we can look for
2159 * another AP to associate with.
2160 *
036cd1ec 2161 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2162 * interrupts to detect TSF updates only.
fa1c114f
JS		 2163 */
2164static void
2165ath5k_beacon_config(struct ath5k_softc *sc)
2166{
2167 struct ath5k_hw *ah = sc->ah;
2168
c6e387a2 2169 ath5k_hw_set_imr(ah, 0);
fa1c114f 2170 sc->bmisscount = 0;
dc1968e7 2171 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2172
05c914fe 2173 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2174 sc->imask |= AR5K_INT_BMISS;
da966bca 2175 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2176 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2177 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2178 /*
036cd1ec
BR		 2179 * In IBSS mode we use a self-linked tx descriptor and let the
2180 * hardware send the beacons automatically. We have to load it
fa1c114f 2181 * only once here.
036cd1ec 2182 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2183 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2184 */
2185 ath5k_beaconq_config(sc);
fa1c114f 2186
036cd1ec
BR		 2187 sc->imask |= AR5K_INT_SWBA;
2188
da966bca
JS		 2189 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2190 if (ath5k_hw_hasveol(ah)) {
2191 spin_lock(&sc->block);
2192 ath5k_beacon_send(sc);
2193 spin_unlock(&sc->block);
2194 }
2195 } else
2196 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2197 }
fa1c114f 2198
c6e387a2 2199 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2200}
2201
2202
2203/********************\
2204* Interrupt handling *
2205\********************/
2206
2207static int
8bdd5b9c 2208ath5k_init(struct ath5k_softc *sc, bool is_resume)
fa1c114f 2209{
bc1b32d6
EO		 2210 struct ath5k_hw *ah = sc->ah;
2211 int ret, i;
fa1c114f
JS		 2212
2213 mutex_lock(&sc->lock);
2214
8bdd5b9c
BC		 2215 if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2216 goto out_ok;
2217
2218 __clear_bit(ATH_STAT_STARTED, sc->status);
2219
fa1c114f
JS		 2220 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2221
2222 /*
2223 * Stop anything previously setup. This is safe
2224 * no matter this is the first time through or not.
2225 */
2226 ath5k_stop_locked(sc);
2227
2228 /*
2229 * The basic interface to setting the hardware in a good
2230 * state is ``reset''. On return the hardware is known to
2231 * be powered up and with interrupts disabled. This must
2232 * be followed by initialization of the appropriate bits
2233 * and then setup of the interrupt mask.
2234 */
d8ee398d
LR		 2235 sc->curchan = sc->hw->conf.channel;
2236 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2237 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2238 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2239 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
d7dc1003
JS		 2240 ret = ath5k_reset(sc, false, false);
2241 if (ret)
2242 goto done;
fa1c114f 2243
bc1b32d6
EO		 2244 /*
2245 * Reset the key cache since some parts do not reset the
2246 * contents on initial power up or resume from suspend.
2247 */
2248 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2249 ath5k_hw_reset_key(ah, i);
2250
8bdd5b9c
BC		 2251 __set_bit(ATH_STAT_STARTED, sc->status);
2252
fa1c114f 2253 /* Set ack to be sent at low bit-rates */
bc1b32d6 2254 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2255
2256 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2257 msecs_to_jiffies(ath5k_calinterval * 1000)));
2258
8bdd5b9c 2259out_ok:
fa1c114f
JS		 2260 ret = 0;
2261done:
274c7c36 2262 mmiowb();
fa1c114f
JS		 2263 mutex_unlock(&sc->lock);
2264 return ret;
2265}
2266
2267static int
2268ath5k_stop_locked(struct ath5k_softc *sc)
2269{
2270 struct ath5k_hw *ah = sc->ah;
2271
2272 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2273 test_bit(ATH_STAT_INVALID, sc->status));
2274
2275 /*
2276 * Shutdown the hardware and driver:
2277 * stop output from above
2278 * disable interrupts
2279 * turn off timers
2280 * turn off the radio
2281 * clear transmit machinery
2282 * clear receive machinery
2283 * drain and release tx queues
2284 * reclaim beacon resources
2285 * power down hardware
2286 *
2287 * Note that some of this work is not possible if the
2288 * hardware is gone (invalid).
2289 */
2290 ieee80211_stop_queues(sc->hw);
2291
2292 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2293 ath5k_led_off(sc);
c6e387a2 2294 ath5k_hw_set_imr(ah, 0);
274c7c36 2295 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2296 }
2297 ath5k_txq_cleanup(sc);
2298 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2299 ath5k_rx_stop(sc);
2300 ath5k_hw_phy_disable(ah);
2301 } else
2302 sc->rxlink = NULL;
2303
2304 return 0;
2305}
2306
2307/*
2308 * Stop the device, grabbing the top-level lock to protect
2309 * against concurrent entry through ath5k_init (which can happen
2310 * if another thread does a system call and the thread doing the
2311 * stop is preempted).
2312 */
2313static int
8bdd5b9c 2314ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
fa1c114f
JS		 2315{
2316 int ret;
2317
2318 mutex_lock(&sc->lock);
2319 ret = ath5k_stop_locked(sc);
2320 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2321 /*
2322 * Set the chip in full sleep mode. Note that we are
2323 * careful to do this only when bringing the interface
2324 * completely to a stop. When the chip is in this state
2325 * it must be carefully woken up or references to
2326 * registers in the PCI clock domain may freeze the bus
2327 * (and system). This varies by chip and is mostly an
2328 * issue with newer parts that go to sleep more quickly.
2329 */
2330 if (sc->ah->ah_mac_srev >= 0x78) {
2331 /*
2332 * XXX
2333 * don't put newer MAC revisions > 7.8 to sleep because
2334 * of the above mentioned problems
2335 */
2336 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2337 "not putting device to sleep\n");
2338 } else {
2339 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2340 "putting device to full sleep\n");
2341 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2342 }
2343 }
2344 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c
BC		 2345 if (!is_suspend)
2346 __clear_bit(ATH_STAT_STARTED, sc->status);
2347
274c7c36 2348 mmiowb();
fa1c114f
JS		 2349 mutex_unlock(&sc->lock);
2350
2351 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2352 tasklet_kill(&sc->rxtq);
2353 tasklet_kill(&sc->txtq);
2354 tasklet_kill(&sc->restq);
fa1c114f
JS		 2355
2356 return ret;
2357}
2358
2359static irqreturn_t
2360ath5k_intr(int irq, void *dev_id)
2361{
2362 struct ath5k_softc *sc = dev_id;
2363 struct ath5k_hw *ah = sc->ah;
2364 enum ath5k_int status;
2365 unsigned int counter = 1000;
2366
2367 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2368 !ath5k_hw_is_intr_pending(ah)))
2369 return IRQ_NONE;
2370
2371 do {
2372 /*
2373 * Figure out the reason(s) for the interrupt. Note
2374 * that get_isr returns a pseudo-ISR that may include
2375 * bits we haven't explicitly enabled so we mask the
2376 * value to insure we only process bits we requested.
2377 */
2378 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2379 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2380 status, sc->imask);
2381 status &= sc->imask; /* discard unasked for bits */
2382 if (unlikely(status & AR5K_INT_FATAL)) {
2383 /*
2384 * Fatal errors are unrecoverable.
2385 * Typically these are caused by DMA errors.
2386 */
2387 tasklet_schedule(&sc->restq);
2388 } else if (unlikely(status & AR5K_INT_RXORN)) {
2389 tasklet_schedule(&sc->restq);
2390 } else {
2391 if (status & AR5K_INT_SWBA) {
2392 /*
2393 * Software beacon alert--time to send a beacon.
2394 * Handle beacon transmission directly; deferring
2395 * this is too slow to meet timing constraints
2396 * under load.
036cd1ec
BR		 2397 *
2398 * In IBSS mode we use this interrupt just to
2399 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2400 * transmission time) in order to detect wether
2401 * automatic TSF updates happened.
fa1c114f 2402 */
05c914fe 2403 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2404 /* XXX: only if VEOL suppported */
2405 u64 tsf = ath5k_hw_get_tsf64(ah);
2406 sc->nexttbtt += sc->bintval;
2407 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2408 "SWBA nexttbtt: %x hw_tu: %x "
2409 "TSF: %llx\n",
2410 sc->nexttbtt,
2411 TSF_TO_TU(tsf),
2412 (unsigned long long) tsf);
036cd1ec 2413 } else {
00482973 2414 spin_lock(&sc->block);
036cd1ec 2415 ath5k_beacon_send(sc);
00482973 2416 spin_unlock(&sc->block);
036cd1ec 2417 }
fa1c114f
JS		 2418 }
2419 if (status & AR5K_INT_RXEOL) {
2420 /*
2421 * NB: the hardware should re-read the link when
2422 * RXE bit is written, but it doesn't work at
2423 * least on older hardware revs.
2424 */
2425 sc->rxlink = NULL;
2426 }
2427 if (status & AR5K_INT_TXURN) {
2428 /* bump tx trigger level */
2429 ath5k_hw_update_tx_triglevel(ah, true);
2430 }
4c674c60 2431 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2432 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2433 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2434 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2435 tasklet_schedule(&sc->txtq);
2436 if (status & AR5K_INT_BMISS) {
2437 }
2438 if (status & AR5K_INT_MIB) {
194828a2
NK		 2439 /*
2440 * These stats are also used for ANI i think
2441 * so how about updating them more often ?
2442 */
2443 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2444 }
2445 }
2446 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2447
2448 if (unlikely(!counter))
2449 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2450
2451 return IRQ_HANDLED;
2452}
2453
2454static void
2455ath5k_tasklet_reset(unsigned long data)
2456{
2457 struct ath5k_softc *sc = (void *)data;
2458
d7dc1003 2459 ath5k_reset_wake(sc);
fa1c114f
JS		 2460}
2461
2462/*
2463 * Periodically recalibrate the PHY to account
2464 * for temperature/environment changes.
2465 */
2466static void
2467ath5k_calibrate(unsigned long data)
2468{
2469 struct ath5k_softc *sc = (void *)data;
2470 struct ath5k_hw *ah = sc->ah;
2471
2472 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2473 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2474 sc->curchan->hw_value);
fa1c114f
JS		 2475
2476 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2477 /*
2478 * Rfgain is out of bounds, reset the chip
2479 * to load new gain values.
2480 */
2481 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2482 ath5k_reset_wake(sc);
fa1c114f
JS		 2483 }
2484 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2485 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2486 ieee80211_frequency_to_channel(
2487 sc->curchan->center_freq));
fa1c114f
JS		 2488
2489 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2490 msecs_to_jiffies(ath5k_calinterval * 1000)));
2491}
2492
2493
2494
2495/***************\
2496* LED functions *
2497\***************/
2498
2499static void
3a078876 2500ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2501{
3a078876
BC		 2502 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2503 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2504 ath5k_led_off(sc);
fa1c114f
JS		 2505 }
2506}
2507
fa1c114f 2508static void
3a078876 2509ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2510{
3a078876
BC		 2511 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2512 return;
fa1c114f 2513 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2514}
2515
2516static void
3a078876 2517ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2518{
3a078876 2519 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2520 return;
3a078876
BC		 2521 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2522}
2523
2524static void
2525ath5k_led_brightness_set(struct led_classdev *led_dev,
2526 enum led_brightness brightness)
2527{
2528 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2529 led_dev);
2530
2531 if (brightness == LED_OFF)
2532 ath5k_led_off(led->sc);
2533 else
2534 ath5k_led_on(led->sc);
2535}
2536
2537static int
2538ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2539 const char *name, char *trigger)
2540{
2541 int err;
2542
2543 led->sc = sc;
2544 strncpy(led->name, name, sizeof(led->name));
2545 led->led_dev.name = led->name;
2546 led->led_dev.default_trigger = trigger;
2547 led->led_dev.brightness_set = ath5k_led_brightness_set;
2548
2549 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2550 if (err) {
3a078876
BC		 2551 ATH5K_WARN(sc, "could not register LED %s\n", name);
2552 led->sc = NULL;
fa1c114f 2553 }
3a078876 2554 return err;
fa1c114f
JS		 2555}
2556
3a078876
BC		 2557static void
2558ath5k_unregister_led(struct ath5k_led *led)
2559{
2560 if (!led->sc)
2561 return;
2562 led_classdev_unregister(&led->led_dev);
2563 ath5k_led_off(led->sc);
2564 led->sc = NULL;
2565}
2566
2567static void
2568ath5k_unregister_leds(struct ath5k_softc *sc)
2569{
2570 ath5k_unregister_led(&sc->rx_led);
2571 ath5k_unregister_led(&sc->tx_led);
2572}
2573
2574
2575static int
2576ath5k_init_leds(struct ath5k_softc *sc)
2577{
2578 int ret = 0;
2579 struct ieee80211_hw *hw = sc->hw;
2580 struct pci_dev *pdev = sc->pdev;
2581 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2582
3a078876
BC		 2583 /*
2584 * Auto-enable soft led processing for IBM cards and for
2585 * 5211 minipci cards.
2586 */
2587 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2588 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2589 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2590 sc->led_pin = 0;
734b5aa9 2591 sc->led_on = 0; /* active low */
3a078876
BC		 2592 }
2593 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2594 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2595 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2596 sc->led_pin = 1;
734b5aa9 2597 sc->led_on = 1; /* active high */
3a078876
BC		 2598 }
2599 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2600 goto out;
2601
2602 ath5k_led_enable(sc);
2603
2604 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2605 ret = ath5k_register_led(sc, &sc->rx_led, name,
2606 ieee80211_get_rx_led_name(hw));
2607 if (ret)
2608 goto out;
2609
2610 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2611 ret = ath5k_register_led(sc, &sc->tx_led, name,
2612 ieee80211_get_tx_led_name(hw));
2613out:
2614 return ret;
2615}
fa1c114f
JS		 2616
2617
2618/********************\
2619* Mac80211 functions *
2620\********************/
2621
2622static int
e039fa4a 2623ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2624{
2625 struct ath5k_softc *sc = hw->priv;
2626 struct ath5k_buf *bf;
2627 unsigned long flags;
2628 int hdrlen;
0fe45b1d 2629 int padsize;
fa1c114f
JS		 2630
2631 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2632
05c914fe 2633 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2634 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2635
2636 /*
2637 * the hardware expects the header padded to 4 byte boundaries
2638 * if this is not the case we add the padding after the header
2639 */
2640 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2641 padsize = ath5k_pad_size(hdrlen);
2642 if (padsize) {
0fe45b1d
BP		 2643
2644 if (skb_headroom(skb) < padsize) {
fa1c114f 2645 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2646 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2647 return NETDEV_TX_BUSY;
fa1c114f 2648 }
0fe45b1d
BP		 2649 skb_push(skb, padsize);
2650 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2651 }
2652
fa1c114f
JS		 2653 spin_lock_irqsave(&sc->txbuflock, flags);
2654 if (list_empty(&sc->txbuf)) {
2655 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2656 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2657 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2658 return NETDEV_TX_BUSY;
fa1c114f
JS		 2659 }
2660 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2661 list_del(&bf->list);
2662 sc->txbuf_len--;
2663 if (list_empty(&sc->txbuf))
2664 ieee80211_stop_queues(hw);
2665 spin_unlock_irqrestore(&sc->txbuflock, flags);
2666
2667 bf->skb = skb;
2668
e039fa4a 2669 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2670 bf->skb = NULL;
2671 spin_lock_irqsave(&sc->txbuflock, flags);
2672 list_add_tail(&bf->list, &sc->txbuf);
2673 sc->txbuf_len++;
2674 spin_unlock_irqrestore(&sc->txbuflock, flags);
2675 dev_kfree_skb_any(skb);
71ef99c8 2676 return NETDEV_TX_OK;
fa1c114f
JS		 2677 }
2678
71ef99c8 2679 return NETDEV_TX_OK;
fa1c114f
JS		 2680}
2681
2682static int
d7dc1003 2683ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2684{
fa1c114f
JS		 2685 struct ath5k_hw *ah = sc->ah;
2686 int ret;
2687
2688 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2689
d7dc1003 2690 if (stop) {
c6e387a2 2691 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2692 ath5k_txq_cleanup(sc);
2693 ath5k_rx_stop(sc);
2694 }
fa1c114f 2695 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2696 if (ret) {
fa1c114f
JS		 2697 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2698 goto err;
2699 }
d7dc1003
JS		 2700
2701 /*
2702 * This is needed only to setup initial state
2703 * but it's best done after a reset.
2704 */
fa1c114f
JS		 2705 ath5k_hw_set_txpower_limit(sc->ah, 0);
2706
2707 ret = ath5k_rx_start(sc);
d7dc1003 2708 if (ret) {
fa1c114f
JS		 2709 ATH5K_ERR(sc, "can't start recv logic\n");
2710 goto err;
2711 }
d7dc1003 2712
fa1c114f 2713 /*
d7dc1003
JS		 2714 * Change channels and update the h/w rate map if we're switching;
2715 * e.g. 11a to 11b/g.
2716 *
2717 * We may be doing a reset in response to an ioctl that changes the
2718 * channel so update any state that might change as a result.
fa1c114f
JS		 2719 *
2720 * XXX needed?
2721 */
2722/* ath5k_chan_change(sc, c); */
fa1c114f 2723
d7dc1003
JS		 2724 ath5k_beacon_config(sc);
2725 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2726
2727 return 0;
2728err:
2729 return ret;
2730}
2731
d7dc1003
JS		 2732static int
2733ath5k_reset_wake(struct ath5k_softc *sc)
2734{
2735 int ret;
2736
2737 ret = ath5k_reset(sc, true, true);
2738 if (!ret)
2739 ieee80211_wake_queues(sc->hw);
2740
2741 return ret;
2742}
2743
fa1c114f
JS		 2744static int ath5k_start(struct ieee80211_hw *hw)
2745{
8bdd5b9c 2746 return ath5k_init(hw->priv, false);
fa1c114f
JS		 2747}
2748
2749static void ath5k_stop(struct ieee80211_hw *hw)
2750{
8bdd5b9c 2751 ath5k_stop_hw(hw->priv, false);
fa1c114f
JS		 2752}
2753
2754static int ath5k_add_interface(struct ieee80211_hw *hw,
2755 struct ieee80211_if_init_conf *conf)
2756{
2757 struct ath5k_softc *sc = hw->priv;
2758 int ret;
2759
2760 mutex_lock(&sc->lock);
32bfd35d 2761 if (sc->vif) {
fa1c114f
JS		 2762 ret = 0;
2763 goto end;
2764 }
2765
32bfd35d 2766 sc->vif = conf->vif;
fa1c114f
JS		 2767
2768 switch (conf->type) {
da966bca 2769 case NL80211_IFTYPE_AP:
05c914fe
JB		 2770 case NL80211_IFTYPE_STATION:
2771 case NL80211_IFTYPE_ADHOC:
b706e65b 2772 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2773 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2774 sc->opmode = conf->type;
2775 break;
2776 default:
2777 ret = -EOPNOTSUPP;
2778 goto end;
2779 }
67d2e2df
JS		 2780
2781 /* Set to a reasonable value. Note that this will
2782 * be set to mac80211's value at ath5k_config(). */
2783 sc->bintval = 1000;
0e149cf5 2784 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2785
fa1c114f
JS		 2786 ret = 0;
2787end:
2788 mutex_unlock(&sc->lock);
2789 return ret;
2790}
2791
2792static void
2793ath5k_remove_interface(struct ieee80211_hw *hw,
2794 struct ieee80211_if_init_conf *conf)
2795{
2796 struct ath5k_softc *sc = hw->priv;
0e149cf5 2797 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2798
2799 mutex_lock(&sc->lock);
32bfd35d 2800 if (sc->vif != conf->vif)
fa1c114f
JS		 2801 goto end;
2802
0e149cf5 2803 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2804 sc->vif = NULL;
fa1c114f
JS		 2805end:
2806 mutex_unlock(&sc->lock);
2807}
2808
d8ee398d
LR		 2809/*
2810 * TODO: Phy disable/diversity etc
2811 */
fa1c114f 2812static int
e8975581 2813ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2814{
2815 struct ath5k_softc *sc = hw->priv;
e8975581 2816 struct ieee80211_conf *conf = &hw->conf;
fa1c114f 2817
e535c1ac 2818 sc->bintval = conf->beacon_int;
d8ee398d 2819 sc->power_level = conf->power_level;
fa1c114f 2820
d8ee398d 2821 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2822}
2823
2824static int
32bfd35d 2825ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2826 struct ieee80211_if_conf *conf)
2827{
2828 struct ath5k_softc *sc = hw->priv;
2829 struct ath5k_hw *ah = sc->ah;
2830 int ret;
2831
fa1c114f 2832 mutex_lock(&sc->lock);
32bfd35d 2833 if (sc->vif != vif) {
fa1c114f
JS		 2834 ret = -EIO;
2835 goto unlock;
2836 }
da966bca 2837 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2838 /* Cache for later use during resets */
2839 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2840 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2841 * a clean way of letting us retrieve this yet. */
2842 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2843 mmiowb();
fa1c114f 2844 }
9d139c81 2845 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2846 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2847 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2848 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2849 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2850 if (!beacon) {
2851 ret = -ENOMEM;
2852 goto unlock;
2853 }
da966bca 2854 ath5k_beacon_update(sc, beacon);
9d139c81 2855 }
fa1c114f
JS		 2856 mutex_unlock(&sc->lock);
2857
d7dc1003 2858 return ath5k_reset_wake(sc);
fa1c114f
JS		 2859unlock:
2860 mutex_unlock(&sc->lock);
2861 return ret;
2862}
2863
2864#define SUPPORTED_FIF_FLAGS \
2865 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2866 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2867 FIF_BCN_PRBRESP_PROMISC
2868/*
2869 * o always accept unicast, broadcast, and multicast traffic
2870 * o multicast traffic for all BSSIDs will be enabled if mac80211
2871 * says it should be
2872 * o maintain current state of phy ofdm or phy cck error reception.
2873 * If the hardware detects any of these type of errors then
2874 * ath5k_hw_get_rx_filter() will pass to us the respective
2875 * hardware filters to be able to receive these type of frames.
2876 * o probe request frames are accepted only when operating in
2877 * hostap, adhoc, or monitor modes
2878 * o enable promiscuous mode according to the interface state
2879 * o accept beacons:
2880 * - when operating in adhoc mode so the 802.11 layer creates
2881 * node table entries for peers,
2882 * - when operating in station mode for collecting rssi data when
2883 * the station is otherwise quiet, or
2884 * - when scanning
2885 */
2886static void ath5k_configure_filter(struct ieee80211_hw *hw,
2887 unsigned int changed_flags,
2888 unsigned int *new_flags,
2889 int mc_count, struct dev_mc_list *mclist)
2890{
2891 struct ath5k_softc *sc = hw->priv;
2892 struct ath5k_hw *ah = sc->ah;
2893 u32 mfilt[2], val, rfilt;
2894 u8 pos;
2895 int i;
2896
2897 mfilt[0] = 0;
2898 mfilt[1] = 0;
2899
2900 /* Only deal with supported flags */
2901 changed_flags &= SUPPORTED_FIF_FLAGS;
2902 *new_flags &= SUPPORTED_FIF_FLAGS;
2903
2904 /* If HW detects any phy or radar errors, leave those filters on.
2905 * Also, always enable Unicast, Broadcasts and Multicast
2906 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2907 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2908 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2909 AR5K_RX_FILTER_MCAST);
2910
2911 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2912 if (*new_flags & FIF_PROMISC_IN_BSS) {
2913 rfilt |= AR5K_RX_FILTER_PROM;
2914 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2915 } else {
fa1c114f 2916 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2917 }
fa1c114f
JS		 2918 }
2919
2920 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2921 if (*new_flags & FIF_ALLMULTI) {
2922 mfilt[0] = ~0;
2923 mfilt[1] = ~0;
2924 } else {
2925 for (i = 0; i < mc_count; i++) {
2926 if (!mclist)
2927 break;
2928 /* calculate XOR of eight 6-bit values */
533dd1b0 2929 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2930 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2931 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2932 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2933 pos &= 0x3f;
2934 mfilt[pos / 32] |= (1 << (pos % 32));
2935 /* XXX: we might be able to just do this instead,
2936 * but not sure, needs testing, if we do use this we'd
2937 * neet to inform below to not reset the mcast */
2938 /* ath5k_hw_set_mcast_filterindex(ah,
2939 * mclist->dmi_addr[5]); */
2940 mclist = mclist->next;
2941 }
2942 }
2943
2944 /* This is the best we can do */
2945 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2946 rfilt |= AR5K_RX_FILTER_PHYERR;
2947
2948 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2949 * and probes for any BSSID, this needs testing */
2950 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2951 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2952
2953 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2954 * set we should only pass on control frames for this
2955 * station. This needs testing. I believe right now this
2956 * enables *all* control frames, which is OK.. but
2957 * but we should see if we can improve on granularity */
2958 if (*new_flags & FIF_CONTROL)
2959 rfilt |= AR5K_RX_FILTER_CONTROL;
2960
2961 /* Additional settings per mode -- this is per ath5k */
2962
2963 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2964
05c914fe 2965 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2966 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2967 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2968 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2969 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2970 if (sc->opmode != NL80211_IFTYPE_AP &&
2971 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2972 test_bit(ATH_STAT_PROMISC, sc->status))
2973 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2974 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2975 sc->opmode == NL80211_IFTYPE_ADHOC ||
2976 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2977 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2978 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2979 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2980 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2981
2982 /* Set filters */
0bbac08f 2983 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2984
2985 /* Set multicast bits */
2986 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2987 /* Set the cached hw filter flags, this will alter actually
2988 * be set in HW */
2989 sc->filter_flags = rfilt;
2990}
2991
2992static int
2993ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2994 const u8 *local_addr, const u8 *addr,
2995 struct ieee80211_key_conf *key)
2996{
2997 struct ath5k_softc *sc = hw->priv;
2998 int ret = 0;
2999
9ad9a26e
BC		 3000 if (modparam_nohwcrypt)
3001 return -EOPNOTSUPP;
3002
0bbac08f 3003 switch (key->alg) {
fa1c114f 3004 case ALG_WEP:
fa1c114f 3005 case ALG_TKIP:
3f64b435 3006 break;
fa1c114f
JS		 3007 case ALG_CCMP:
3008 return -EOPNOTSUPP;
3009 default:
3010 WARN_ON(1);
3011 return -EINVAL;
3012 }
3013
3014 mutex_lock(&sc->lock);
3015
3016 switch (cmd) {
3017 case SET_KEY:
3018 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
3019 if (ret) {
3020 ATH5K_ERR(sc, "can't set the key\n");
3021 goto unlock;
3022 }
3023 __set_bit(key->keyidx, sc->keymap);
3024 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3025 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3026 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3027 break;
3028 case DISABLE_KEY:
3029 ath5k_hw_reset_key(sc->ah, key->keyidx);
3030 __clear_bit(key->keyidx, sc->keymap);
3031 break;
3032 default:
3033 ret = -EINVAL;
3034 goto unlock;
3035 }
3036
3037unlock:
274c7c36 3038 mmiowb();
fa1c114f
JS		 3039 mutex_unlock(&sc->lock);
3040 return ret;
3041}
3042
3043static int
3044ath5k_get_stats(struct ieee80211_hw *hw,
3045 struct ieee80211_low_level_stats *stats)
3046{
3047 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3048 struct ath5k_hw *ah = sc->ah;
3049
3050 /* Force update */
3051 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3052
3053 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3054
3055 return 0;
3056}
3057
3058static int
3059ath5k_get_tx_stats(struct ieee80211_hw *hw,
3060 struct ieee80211_tx_queue_stats *stats)
3061{
3062 struct ath5k_softc *sc = hw->priv;
3063
3064 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3065
3066 return 0;
3067}
3068
3069static u64
3070ath5k_get_tsf(struct ieee80211_hw *hw)
3071{
3072 struct ath5k_softc *sc = hw->priv;
3073
3074 return ath5k_hw_get_tsf64(sc->ah);
3075}
3076
3077static void
3078ath5k_reset_tsf(struct ieee80211_hw *hw)
3079{
3080 struct ath5k_softc *sc = hw->priv;
3081
9804b98d
BR		 3082 /*
3083 * in IBSS mode we need to update the beacon timers too.
3084 * this will also reset the TSF if we call it with 0
3085 */
05c914fe 3086 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3087 ath5k_beacon_update_timers(sc, 0);
3088 else
3089 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3090}
3091
3092static int
da966bca 3093ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3094{
00482973 3095 unsigned long flags;
fa1c114f
JS		 3096 int ret;
3097
3098 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3099
00482973 3100 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3101 ath5k_txbuf_free(sc, sc->bbuf);
3102 sc->bbuf->skb = skb;
e039fa4a 3103 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3104 if (ret)
3105 sc->bbuf->skb = NULL;
00482973
JS		 3106 spin_unlock_irqrestore(&sc->block, flags);
3107 if (!ret) {
fa1c114f 3108 ath5k_beacon_config(sc);
274c7c36
JS		 3109 mmiowb();
3110 }
fa1c114f 3111
fa1c114f
JS		 3112 return ret;
3113}
02969b38
MX		 3114static void
3115set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3116{
3117 struct ath5k_softc *sc = hw->priv;
3118 struct ath5k_hw *ah = sc->ah;
3119 u32 rfilt;
3120 rfilt = ath5k_hw_get_rx_filter(ah);
3121 if (enable)
3122 rfilt |= AR5K_RX_FILTER_BEACON;
3123 else
3124 rfilt &= ~AR5K_RX_FILTER_BEACON;
3125 ath5k_hw_set_rx_filter(ah, rfilt);
3126 sc->filter_flags = rfilt;
3127}
fa1c114f 3128
02969b38
MX		 3129static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3130 struct ieee80211_vif *vif,
3131 struct ieee80211_bss_conf *bss_conf,
3132 u32 changes)
3133{
3134 struct ath5k_softc *sc = hw->priv;
3135 if (changes & BSS_CHANGED_ASSOC) {
3136 mutex_lock(&sc->lock);
3137 sc->assoc = bss_conf->assoc;
3138 if (sc->opmode == NL80211_IFTYPE_STATION)
3139 set_beacon_filter(hw, sc->assoc);
3140 mutex_unlock(&sc->lock);
3141 }
3142}
Linux 6.x block layer and io_uring tree(s)