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mac80211: use nl80211 interface types
[linux-block.git] / drivers / net / wireless / ath5k / ath5k.h
CommitLineData
fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
fa1c114f
JS		 38
39/* PCI IDs */
40#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
41#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
42#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
43#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
44#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
45#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
46#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
47#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
48#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
49#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
52#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
64#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
65#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
66#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
67#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
68
69/****************************\
70 GENERIC DRIVER DEFINITIONS
71\****************************/
72
73#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
74
75#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
76 printk(_level "ath5k %s: " _fmt, \
77 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
78 ##__VA_ARGS__)
79
80#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
81 if (net_ratelimit()) \
82 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
83 } while (0)
84
85#define ATH5K_INFO(_sc, _fmt, ...) \
86 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
87
88#define ATH5K_WARN(_sc, _fmt, ...) \
89 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
90
91#define ATH5K_ERR(_sc, _fmt, ...) \
92 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
93
c6e387a2
NK		 94/*
95 * AR5K REGISTER ACCESS
96 */
97
98/* Some macros to read/write fields */
99
100/* First shift, then mask */
101#define AR5K_REG_SM(_val, _flags) \
102 (((_val) << _flags##_S) & (_flags))
103
104/* First mask, then shift */
105#define AR5K_REG_MS(_val, _flags) \
106 (((_val) & (_flags)) >> _flags##_S)
107
108/* Some registers can hold multiple values of interest. For this
109 * reason when we want to write to these registers we must first
110 * retrieve the values which we do not want to clear (lets call this
111 * old_data) and then set the register with this and our new_value:
112 * ( old_data | new_value) */
113#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
114 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
115 (((_val) << _flags##_S) & (_flags)), _reg)
116
117#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
118 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
119 (_mask)) | (_flags), _reg)
120
121#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
122 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
123
124#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
125 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
126
127/* Access to PHY registers */
128#define AR5K_PHY_READ(ah, _reg) \
129 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
130
131#define AR5K_PHY_WRITE(ah, _reg, _val) \
132 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
133
134/* Access QCU registers per queue */
135#define AR5K_REG_READ_Q(ah, _reg, _queue) \
136 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
137
138#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
139 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
140
141#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
142 _reg |= 1 << _queue; \
143} while (0)
144
145#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
146 _reg &= ~(1 << _queue); \
147} while (0)
148
149/* Used while writing initvals */
150#define AR5K_REG_WAIT(_i) do { \
151 if (_i % 64) \
152 udelay(1); \
153} while (0)
154
155/* Register dumps are done per operation mode */
156#define AR5K_INI_RFGAIN_5GHZ 0
157#define AR5K_INI_RFGAIN_2GHZ 1
158
159/* TODO: Clean this up */
160#define AR5K_INI_VAL_11A 0
161#define AR5K_INI_VAL_11A_TURBO 1
162#define AR5K_INI_VAL_11B 2
163#define AR5K_INI_VAL_11G 3
164#define AR5K_INI_VAL_11G_TURBO 4
165#define AR5K_INI_VAL_XR 0
166#define AR5K_INI_VAL_MAX 5
167
168#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
169#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
170
171/* Used for BSSID etc manipulation */
172#define AR5K_LOW_ID(_a)( \
173(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
174)
175
176#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
177
fa1c114f
JS		 178/*
179 * Some tuneable values (these should be changeable by the user)
c6e387a2 180 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 181 */
182#define AR5K_TUNE_DMA_BEACON_RESP 2
183#define AR5K_TUNE_SW_BEACON_RESP 10
184#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
185#define AR5K_TUNE_RADAR_ALERT false
186#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
187#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
188#define AR5K_TUNE_REGISTER_TIMEOUT 20000
189/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
190 * be the max value. */
c6e387a2 191#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 192/* This must be set when setting the RSSI threshold otherwise it can
193 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
194 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
195 * track of it. Max value depends on harware. For AR5210 this is just 7.
196 * For AR5211+ this seems to be up to 255. */
c6e387a2 197#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 198#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
199#define AR5K_TUNE_BEACON_INTERVAL 100
200#define AR5K_TUNE_AIFS 2
201#define AR5K_TUNE_AIFS_11B 2
202#define AR5K_TUNE_AIFS_XR 0
203#define AR5K_TUNE_CWMIN 15
204#define AR5K_TUNE_CWMIN_11B 31
205#define AR5K_TUNE_CWMIN_XR 3
206#define AR5K_TUNE_CWMAX 1023
207#define AR5K_TUNE_CWMAX_11B 1023
208#define AR5K_TUNE_CWMAX_XR 7
209#define AR5K_TUNE_NOISE_FLOOR -72
210#define AR5K_TUNE_MAX_TXPOWER 60
211#define AR5K_TUNE_DEFAULT_TXPOWER 30
212#define AR5K_TUNE_TPC_TXPOWER true
213#define AR5K_TUNE_ANT_DIVERSITY true
214#define AR5K_TUNE_HWTXTRIES 4
215
c6e387a2
NK		 216#define AR5K_INIT_CARR_SENSE_EN 1
217
218/*Swap RX/TX Descriptor for big endian archs*/
219#if defined(__BIG_ENDIAN)
220#define AR5K_INIT_CFG ( \
221 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
222)
223#else
224#define AR5K_INIT_CFG 0x00000000
225#endif
226
227/* Initial values */
228#define AR5K_INIT_TX_LATENCY 502
229#define AR5K_INIT_USEC 39
230#define AR5K_INIT_USEC_TURBO 79
231#define AR5K_INIT_USEC_32 31
232#define AR5K_INIT_SLOT_TIME 396
233#define AR5K_INIT_SLOT_TIME_TURBO 480
234#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
235#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
236#define AR5K_INIT_PROG_IFS 920
237#define AR5K_INIT_PROG_IFS_TURBO 960
238#define AR5K_INIT_EIFS 3440
239#define AR5K_INIT_EIFS_TURBO 6880
240#define AR5K_INIT_SIFS 560
241#define AR5K_INIT_SIFS_TURBO 480
242#define AR5K_INIT_SH_RETRY 10
243#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
244#define AR5K_INIT_SSH_RETRY 32
245#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
246#define AR5K_INIT_TX_RETRY 10
247
248#define AR5K_INIT_TRANSMIT_LATENCY ( \
249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
250 (AR5K_INIT_USEC) \
251)
252#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
253 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
254 (AR5K_INIT_USEC_TURBO) \
255)
256#define AR5K_INIT_PROTO_TIME_CNTRL ( \
257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
258 (AR5K_INIT_PROG_IFS) \
259)
260#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
261 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
262 (AR5K_INIT_PROG_IFS_TURBO) \
263)
264
fa1c114f
JS		 265/* token to use for aifs, cwmin, cwmax in MadWiFi */
266#define AR5K_TXQ_USEDEFAULT ((u32) -1)
267
268/* GENERIC CHIPSET DEFINITIONS */
269
270/* MAC Chips */
271enum ath5k_version {
272 AR5K_AR5210 = 0,
273 AR5K_AR5211 = 1,
274 AR5K_AR5212 = 2,
275};
276
277/* PHY Chips */
278enum ath5k_radio {
279 AR5K_RF5110 = 0,
280 AR5K_RF5111 = 1,
281 AR5K_RF5112 = 2,
8daeef97
NK		 282 AR5K_RF2413 = 3,
283 AR5K_RF5413 = 4,
136bfc79 284 AR5K_RF2425 = 5,
fa1c114f
JS		 285};
286
287/*
288 * Common silicon revision/version values
289 */
290
291enum ath5k_srev_type {
292 AR5K_VERSION_VER,
293 AR5K_VERSION_RAD,
294};
295
296struct ath5k_srev_name {
297 const char *sr_name;
298 enum ath5k_srev_type sr_type;
299 u_int sr_val;
300};
301
302#define AR5K_SREV_UNKNOWN 0xffff
303
304#define AR5K_SREV_VER_AR5210 0x00
305#define AR5K_SREV_VER_AR5311 0x10
306#define AR5K_SREV_VER_AR5311A 0x20
307#define AR5K_SREV_VER_AR5311B 0x30
308#define AR5K_SREV_VER_AR5211 0x40
309#define AR5K_SREV_VER_AR5212 0x50
310#define AR5K_SREV_VER_AR5213 0x55
311#define AR5K_SREV_VER_AR5213A 0x59
8daeef97
NK		 312#define AR5K_SREV_VER_AR2413 0x78
313#define AR5K_SREV_VER_AR2414 0x79
56c9054f
NK		 314#define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
315#define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
fa1c114f
JS		 316#define AR5K_SREV_VER_AR5413 0xa4
317#define AR5K_SREV_VER_AR5414 0xa5
56c9054f
NK		 318#define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
319#define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
320#define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
fa1c114f
JS		 321
322#define AR5K_SREV_RAD_5110 0x00
323#define AR5K_SREV_RAD_5111 0x10
324#define AR5K_SREV_RAD_5111A 0x15
325#define AR5K_SREV_RAD_2111 0x20
326#define AR5K_SREV_RAD_5112 0x30
327#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 328#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 329#define AR5K_SREV_RAD_2112 0x40
330#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d
NK		 331#define AR5K_SREV_RAD_2112B 0x46
332#define AR5K_SREV_RAD_SC0 0x50 /* Found on 2413/2414 */
333#define AR5K_SREV_RAD_SC1 0x60 /* Found on 5413/5414 */
334#define AR5K_SREV_RAD_SC2 0xa0 /* Found on 2424-5/5424 */
fa1c114f
JS		 335#define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
336
337/* IEEE defs */
fa1c114f
JS		 338#define IEEE80211_MAX_LEN 2500
339
340/* TODO add support to mac80211 for vendor-specific rates and modes */
341
342/*
343 * Some of this information is based on Documentation from:
344 *
345 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
346 *
347 * Modulation for Atheros' eXtended Range - range enhancing extension that is
348 * supposed to double the distance an Atheros client device can keep a
349 * connection with an Atheros access point. This is achieved by increasing
350 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
351 * the 802.11 specifications demand. In addition, new (proprietary) data rates
352 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
353 *
354 * Please note that can you either use XR or TURBO but you cannot use both,
355 * they are exclusive.
356 *
357 */
358#define MODULATION_XR 0x00000200
359/*
360 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
361 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
362 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
363 * channels. To use this feature your Access Point must also suport it.
364 * There is also a distinction between "static" and "dynamic" turbo modes:
365 *
366 * - Static: is the dumb version: devices set to this mode stick to it until
367 * the mode is turned off.
368 * - Dynamic: is the intelligent version, the network decides itself if it
369 * is ok to use turbo. As soon as traffic is detected on adjacent channels
370 * (which would get used in turbo mode), or when a non-turbo station joins
371 * the network, turbo mode won't be used until the situation changes again.
372 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
373 * monitors the used radio band in order to decide whether turbo mode may
374 * be used or not.
375 *
376 * This article claims Super G sticks to bonding of channels 5 and 6 for
377 * USA:
378 *
379 * http://www.pcworld.com/article/id,113428-page,1/article.html
380 *
381 * The channel bonding seems to be driver specific though. In addition to
382 * deciding what channels will be used, these "Turbo" modes are accomplished
383 * by also enabling the following features:
384 *
385 * - Bursting: allows multiple frames to be sent at once, rather than pausing
386 * after each frame. Bursting is a standards-compliant feature that can be
387 * used with any Access Point.
388 * - Fast frames: increases the amount of information that can be sent per
389 * frame, also resulting in a reduction of transmission overhead. It is a
390 * proprietary feature that needs to be supported by the Access Point.
391 * - Compression: data frames are compressed in real time using a Lempel Ziv
392 * algorithm. This is done transparently. Once this feature is enabled,
393 * compression and decompression takes place inside the chipset, without
394 * putting additional load on the host CPU.
395 *
396 */
397#define MODULATION_TURBO 0x00000080
398
d8ee398d
LR		 399enum ath5k_driver_mode {
400 AR5K_MODE_11A = 0,
401 AR5K_MODE_11A_TURBO = 1,
402 AR5K_MODE_11B = 2,
403 AR5K_MODE_11G = 3,
404 AR5K_MODE_11G_TURBO = 4,
405 AR5K_MODE_XR = 0,
406 AR5K_MODE_MAX = 5
fa1c114f
JS		 407};
408
19fd6e55 409
fa1c114f
JS		 410/****************\
411 TX DEFINITIONS
412\****************/
413
414/*
c6e387a2 415 * TX Status descriptor
fa1c114f
JS		 416 */
417struct ath5k_tx_status {
418 u16 ts_seqnum;
419 u16 ts_tstamp;
420 u8 ts_status;
421 u8 ts_rate;
422 s8 ts_rssi;
423 u8 ts_shortretry;
424 u8 ts_longretry;
425 u8 ts_virtcol;
426 u8 ts_antenna;
427};
428
429#define AR5K_TXSTAT_ALTRATE 0x80
430#define AR5K_TXERR_XRETRY 0x01
431#define AR5K_TXERR_FILT 0x02
432#define AR5K_TXERR_FIFO 0x04
433
434/**
435 * enum ath5k_tx_queue - Queue types used to classify tx queues.
436 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
437 * @AR5K_TX_QUEUE_DATA: A normal data queue
438 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
439 * @AR5K_TX_QUEUE_BEACON: The beacon queue
440 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
441 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
442 */
443enum ath5k_tx_queue {
444 AR5K_TX_QUEUE_INACTIVE = 0,
445 AR5K_TX_QUEUE_DATA,
446 AR5K_TX_QUEUE_XR_DATA,
447 AR5K_TX_QUEUE_BEACON,
448 AR5K_TX_QUEUE_CAB,
449 AR5K_TX_QUEUE_UAPSD,
450};
451
452#define AR5K_NUM_TX_QUEUES 10
453#define AR5K_NUM_TX_QUEUES_NOQCU 2
454
455/*
456 * Queue syb-types to classify normal data queues.
457 * These are the 4 Access Categories as defined in
458 * WME spec. 0 is the lowest priority and 4 is the
459 * highest. Normal data that hasn't been classified
460 * goes to the Best Effort AC.
461 */
462enum ath5k_tx_queue_subtype {
463 AR5K_WME_AC_BK = 0, /*Background traffic*/
464 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
465 AR5K_WME_AC_VI, /*Video traffic*/
466 AR5K_WME_AC_VO, /*Voice traffic*/
467};
468
469/*
470 * Queue ID numbers as returned by the hw functions, each number
471 * represents a hw queue. If hw does not support hw queues
472 * (eg 5210) all data goes in one queue. These match
473 * d80211 definitions (net80211/MadWiFi don't use them).
474 */
475enum ath5k_tx_queue_id {
476 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
477 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
478 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
479 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
480 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
481 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
482 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
483 AR5K_TX_QUEUE_ID_UAPSD = 8,
484 AR5K_TX_QUEUE_ID_XR_DATA = 9,
485};
486
fa1c114f
JS		 487/*
488 * Flags to set hw queue's parameters...
489 */
490#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
491#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
492#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
493#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
494#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
495#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0020 /* Disable random post-backoff */
496#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040 /* Enable ready time expiry policy (?)*/
497#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080 /* Enable backoff while bursting */
498#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0100 /* Disable backoff while bursting */
499#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0200 /* Enable hw compression -not implemented-*/
500
501/*
502 * A struct to hold tx queue's parameters
503 */
504struct ath5k_txq_info {
505 enum ath5k_tx_queue tqi_type;
506 enum ath5k_tx_queue_subtype tqi_subtype;
507 u16 tqi_flags; /* Tx queue flags (see above) */
508 u32 tqi_aifs; /* Arbitrated Interframe Space */
509 s32 tqi_cw_min; /* Minimum Contention Window */
510 s32 tqi_cw_max; /* Maximum Contention Window */
511 u32 tqi_cbr_period; /* Constant bit rate period */
512 u32 tqi_cbr_overflow_limit;
513 u32 tqi_burst_time;
514 u32 tqi_ready_time; /* Not used */
515};
516
517/*
518 * Transmit packet types.
c6e387a2
NK		 519 * used on tx control descriptor
520 * TODO: Use them inside base.c corectly
fa1c114f
JS		 521 */
522enum ath5k_pkt_type {
523 AR5K_PKT_TYPE_NORMAL = 0,
524 AR5K_PKT_TYPE_ATIM = 1,
525 AR5K_PKT_TYPE_PSPOLL = 2,
526 AR5K_PKT_TYPE_BEACON = 3,
527 AR5K_PKT_TYPE_PROBE_RESP = 4,
528 AR5K_PKT_TYPE_PIFS = 5,
529};
530
531/*
532 * TX power and TPC settings
533 */
534#define AR5K_TXPOWER_OFDM(_r, _v) ( \
535 ((0 & 1) << ((_v) + 6)) | \
536 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
537)
538
539#define AR5K_TXPOWER_CCK(_r, _v) ( \
540 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
541)
542
543/*
544 * DMA size definitions (2^n+2)
545 */
546enum ath5k_dmasize {
547 AR5K_DMASIZE_4B = 0,
548 AR5K_DMASIZE_8B,
549 AR5K_DMASIZE_16B,
550 AR5K_DMASIZE_32B,
551 AR5K_DMASIZE_64B,
552 AR5K_DMASIZE_128B,
553 AR5K_DMASIZE_256B,
554 AR5K_DMASIZE_512B
555};
556
557
558/****************\
559 RX DEFINITIONS
560\****************/
561
562/*
c6e387a2 563 * RX Status descriptor
fa1c114f
JS		 564 */
565struct ath5k_rx_status {
566 u16 rs_datalen;
567 u16 rs_tstamp;
568 u8 rs_status;
569 u8 rs_phyerr;
570 s8 rs_rssi;
571 u8 rs_keyix;
572 u8 rs_rate;
573 u8 rs_antenna;
574 u8 rs_more;
575};
576
577#define AR5K_RXERR_CRC 0x01
578#define AR5K_RXERR_PHY 0x02
579#define AR5K_RXERR_FIFO 0x04
580#define AR5K_RXERR_DECRYPT 0x08
581#define AR5K_RXERR_MIC 0x10
582#define AR5K_RXKEYIX_INVALID ((u8) - 1)
583#define AR5K_TXKEYIX_INVALID ((u32) - 1)
584
fa1c114f 585
fa1c114f
JS		 586/**************************\
587 BEACON TIMERS DEFINITIONS
588\**************************/
589
590#define AR5K_BEACON_PERIOD 0x0000ffff
591#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
592#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
593
594#if 0
595/**
596 * struct ath5k_beacon_state - Per-station beacon timer state.
597 * @bs_interval: in TU's, can also include the above flags
598 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
599 * Point Coordination Function capable AP
600 */
601struct ath5k_beacon_state {
602 u32 bs_next_beacon;
603 u32 bs_next_dtim;
604 u32 bs_interval;
605 u8 bs_dtim_period;
606 u8 bs_cfp_period;
607 u16 bs_cfp_max_duration;
608 u16 bs_cfp_du_remain;
609 u16 bs_tim_offset;
610 u16 bs_sleep_duration;
611 u16 bs_bmiss_threshold;
612 u32 bs_cfp_next;
613};
614#endif
615
616
617/*
618 * TSF to TU conversion:
619 *
620 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 621 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
622 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 623 */
624#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
625
626
c6e387a2
NK		 627/*******************************\
628 GAIN OPTIMIZATION DEFINITIONS
629\*******************************/
630
631enum ath5k_rfgain {
632 AR5K_RFGAIN_INACTIVE = 0,
633 AR5K_RFGAIN_READ_REQUESTED,
634 AR5K_RFGAIN_NEED_CHANGE,
635};
636
637#define AR5K_GAIN_CRN_FIX_BITS_5111 4
638#define AR5K_GAIN_CRN_FIX_BITS_5112 7
639#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
640#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
641#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
642#define AR5K_GAIN_CCK_PROBE_CORR 5
643#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
644#define AR5K_GAIN_STEP_COUNT 10
645#define AR5K_GAIN_PARAM_TX_CLIP 0
646#define AR5K_GAIN_PARAM_PD_90 1
647#define AR5K_GAIN_PARAM_PD_84 2
648#define AR5K_GAIN_PARAM_GAIN_SEL 3
649#define AR5K_GAIN_PARAM_MIX_ORN 0
650#define AR5K_GAIN_PARAM_PD_138 1
651#define AR5K_GAIN_PARAM_PD_137 2
652#define AR5K_GAIN_PARAM_PD_136 3
653#define AR5K_GAIN_PARAM_PD_132 4
654#define AR5K_GAIN_PARAM_PD_131 5
655#define AR5K_GAIN_PARAM_PD_130 6
656#define AR5K_GAIN_CHECK_ADJUST(_g) \
657 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
658
659struct ath5k_gain_opt_step {
660 s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
661 s32 gos_gain;
662};
663
664struct ath5k_gain {
665 u32 g_step_idx;
666 u32 g_current;
667 u32 g_target;
668 u32 g_low;
669 u32 g_high;
670 u32 g_f_corr;
671 u32 g_active;
672 const struct ath5k_gain_opt_step *g_step;
673};
674
675
fa1c114f
JS		 676/********************\
677 COMMON DEFINITIONS
678\********************/
679
fa1c114f
JS		 680#define AR5K_SLOT_TIME_9 396
681#define AR5K_SLOT_TIME_20 880
682#define AR5K_SLOT_TIME_MAX 0xffff
683
684/* channel_flags */
685#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
686#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
687#define CHANNEL_CCK 0x0020 /* CCK channel */
688#define CHANNEL_OFDM 0x0040 /* OFDM channel */
689#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
690#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
691#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
692#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
693#define CHANNEL_XR 0x0800 /* XR channel */
694
695#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
696#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
697#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
698#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
699#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
700#define CHANNEL_108A CHANNEL_T
701#define CHANNEL_108G CHANNEL_TG
702#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
703
704#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
705 CHANNEL_TURBO)
706
707#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
708#define CHANNEL_MODES CHANNEL_ALL
709
710/*
c6e387a2
NK		 711 * Used internaly for reset_tx_queue).
712 * Also see struct struct ieee80211_channel.
fa1c114f 713 */
d8ee398d
LR		 714#define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
715#define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 716
717/*
c6e387a2 718 * The following structure is used to map 2GHz channels to
fa1c114f 719 * 5GHz Atheros channels.
c6e387a2 720 * TODO: Clean up
fa1c114f
JS		 721 */
722struct ath5k_athchan_2ghz {
723 u32 a2_flags;
724 u16 a2_athchan;
725};
726
63266a65 727
c6e387a2
NK		 728/******************\
729 RATE DEFINITIONS
730\******************/
fa1c114f 731
fa1c114f 732/**
63266a65 733 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 734 *
63266a65 735 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 736 * hardware descriptors. It is also used for internal modulation control
737 * and settings.
738 *
63266a65 739 * This is the hardware rate map we are aware of:
fa1c114f 740 *
63266a65 741 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 742 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
743 *
63266a65 744 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 745 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
746 *
747 * rate_code 17 18 19 20 21 22 23 24
748 * rate_kbps ? ? ? ? ? ? ? 11000
749 *
750 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 751 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
752 *
753 * "S" indicates CCK rates with short preamble.
fa1c114f 754 *
63266a65
BR		 755 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
756 * lowest 4 bits, so they are the same as below with a 0xF mask.
757 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
758 * We handle this in ath5k_setup_bands().
fa1c114f 759 */
63266a65 760#define AR5K_MAX_RATES 32
fa1c114f 761
63266a65
BR		 762/* B */
763#define ATH5K_RATE_CODE_1M 0x1B
764#define ATH5K_RATE_CODE_2M 0x1A
765#define ATH5K_RATE_CODE_5_5M 0x19
766#define ATH5K_RATE_CODE_11M 0x18
767/* A and G */
768#define ATH5K_RATE_CODE_6M 0x0B
769#define ATH5K_RATE_CODE_9M 0x0F
770#define ATH5K_RATE_CODE_12M 0x0A
771#define ATH5K_RATE_CODE_18M 0x0E
772#define ATH5K_RATE_CODE_24M 0x09
773#define ATH5K_RATE_CODE_36M 0x0D
774#define ATH5K_RATE_CODE_48M 0x08
775#define ATH5K_RATE_CODE_54M 0x0C
776/* XR */
777#define ATH5K_RATE_CODE_XR_500K 0x07
778#define ATH5K_RATE_CODE_XR_1M 0x02
779#define ATH5K_RATE_CODE_XR_2M 0x06
780#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 781
c6e387a2
NK		 782/* adding this flag to rate_code enables short preamble */
783#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 784
785/*
786 * Crypto definitions
787 */
788
789#define AR5K_KEYCACHE_SIZE 8
790
791/***********************\
792 HW RELATED DEFINITIONS
793\***********************/
794
795/*
796 * Misc definitions
797 */
798#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
799
800#define AR5K_ASSERT_ENTRY(_e, _s) do { \
801 if (_e >= _s) \
802 return (false); \
803} while (0)
804
fa1c114f
JS		 805enum ath5k_ant_setting {
806 AR5K_ANT_VARIABLE = 0, /* variable by programming */
807 AR5K_ANT_FIXED_A = 1, /* fixed to 11a frequencies */
808 AR5K_ANT_FIXED_B = 2, /* fixed to 11b frequencies */
809 AR5K_ANT_MAX = 3,
810};
811
812/*
813 * Hardware interrupt abstraction
814 */
815
816/**
817 * enum ath5k_int - Hardware interrupt masks helpers
818 *
819 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
820 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
821 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
822 * @AR5K_INT_RXNOFRM: No frame received (?)
823 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
824 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
825 * LinkPtr is NULL. For more details, refer to:
826 * http://www.freepatentsonline.com/20030225739.html
827 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
828 * Note that Rx overrun is not always fatal, on some chips we can continue
829 * operation without reseting the card, that's why int_fatal is not
830 * common for all chips.
831 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
832 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
833 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
834 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
835 * We currently do increments on interrupt by
836 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
837 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
838 * checked. We should do this with ath5k_hw_update_mib_counters() but
839 * it seems we should also then do some noise immunity work.
840 * @AR5K_INT_RXPHY: RX PHY Error
841 * @AR5K_INT_RXKCM: ??
842 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
843 * beacon that must be handled in software. The alternative is if you
844 * have VEOL support, in that case you let the hardware deal with things.
845 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
846 * beacons from the AP have associated with, we should probably try to
847 * reassociate. When in IBSS mode this might mean we have not received
848 * any beacons from any local stations. Note that every station in an
849 * IBSS schedules to send beacons at the Target Beacon Transmission Time
850 * (TBTT) with a random backoff.
851 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
852 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
853 * until properly handled
854 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
855 * errors. These types of errors we can enable seem to be of type
856 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
857 * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
858 * @AR5K_INT_NOCARD: signals the card has been removed
859 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
860 * bit value
861 *
862 * These are mapped to take advantage of some common bits
863 * between the MACs, to be able to set intr properties
864 * easier. Some of them are not used yet inside hw.c. Most map
865 * to the respective hw interrupt value as they are common amogst different
866 * MACs.
867 */
868enum ath5k_int {
869 AR5K_INT_RX = 0x00000001, /* Not common */
870 AR5K_INT_RXDESC = 0x00000002,
871 AR5K_INT_RXNOFRM = 0x00000008,
872 AR5K_INT_RXEOL = 0x00000010,
873 AR5K_INT_RXORN = 0x00000020,
874 AR5K_INT_TX = 0x00000040, /* Not common */
875 AR5K_INT_TXDESC = 0x00000080,
876 AR5K_INT_TXURN = 0x00000800,
877 AR5K_INT_MIB = 0x00001000,
878 AR5K_INT_RXPHY = 0x00004000,
879 AR5K_INT_RXKCM = 0x00008000,
880 AR5K_INT_SWBA = 0x00010000,
881 AR5K_INT_BMISS = 0x00040000,
882 AR5K_INT_BNR = 0x00100000, /* Not common */
883 AR5K_INT_GPIO = 0x01000000,
884 AR5K_INT_FATAL = 0x40000000, /* Not common */
885 AR5K_INT_GLOBAL = 0x80000000,
886
887 AR5K_INT_COMMON = AR5K_INT_RXNOFRM
888 | AR5K_INT_RXDESC
889 | AR5K_INT_RXEOL
890 | AR5K_INT_RXORN
891 | AR5K_INT_TXURN
892 | AR5K_INT_TXDESC
893 | AR5K_INT_MIB
894 | AR5K_INT_RXPHY
895 | AR5K_INT_RXKCM
896 | AR5K_INT_SWBA
897 | AR5K_INT_BMISS
898 | AR5K_INT_GPIO,
899 AR5K_INT_NOCARD = 0xffffffff
900};
901
902/*
903 * Power management
904 */
905enum ath5k_power_mode {
906 AR5K_PM_UNDEFINED = 0,
907 AR5K_PM_AUTO,
908 AR5K_PM_AWAKE,
909 AR5K_PM_FULL_SLEEP,
910 AR5K_PM_NETWORK_SLEEP,
911};
912
913/*
914 * These match net80211 definitions (not used in
c6e387a2
NK		 915 * mac80211).
916 * TODO: Clean this up
fa1c114f
JS		 917 */
918#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
919#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
920#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
921#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
922#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
923
924/* GPIO-controlled software LED */
925#define AR5K_SOFTLED_PIN 0
926#define AR5K_SOFTLED_ON 0
927#define AR5K_SOFTLED_OFF 1
928
929/*
930 * Chipset capabilities -see ath5k_hw_get_capability-
931 * get_capability function is not yet fully implemented
c6e387a2
NK		 932 * in ath5k so most of these don't work yet...
933 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 934 */
935enum ath5k_capability_type {
936 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
937 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
938 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
939 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
940 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
941 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
942 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
943 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
944 AR5K_CAP_BURST = 9, /* Supports packet bursting */
945 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
946 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
947 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
948 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
949 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
950 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
951 AR5K_CAP_XR = 16, /* Supports XR mode */
952 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
953 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
954 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
955 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
956};
957
400ec45a
LR		 958
959/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 960struct ath5k_capabilities {
961 /*
962 * Supported PHY modes
963 * (ie. CHANNEL_A, CHANNEL_B, ...)
964 */
d8ee398d 965 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 966
967 /*
968 * Frequency range (without regulation restrictions)
969 */
970 struct {
971 u16 range_2ghz_min;
972 u16 range_2ghz_max;
973 u16 range_5ghz_min;
974 u16 range_5ghz_max;
975 } cap_range;
976
fa1c114f
JS		 977 /*
978 * Values stored in the EEPROM (some of them...)
979 */
980 struct ath5k_eeprom_info cap_eeprom;
981
982 /*
983 * Queue information
984 */
985 struct {
986 u8 q_tx_num;
987 } cap_queues;
988};
989
990
991/***************************************\
992 HARDWARE ABSTRACTION LAYER STRUCTURE
993\***************************************/
994
995/*
996 * Misc defines
997 */
998
999#define AR5K_MAX_GPIO 10
1000#define AR5K_MAX_RF_BANKS 8
1001
c6e387a2 1002/* TODO: Clean up and merge with ath5k_softc */
fa1c114f
JS		 1003struct ath5k_hw {
1004 u32 ah_magic;
1005
1006 struct ath5k_softc *ah_sc;
1007 void __iomem *ah_iobase;
1008
1009 enum ath5k_int ah_imr;
1010
05c914fe 1011 enum nl80211_iftype ah_op_mode;
fa1c114f
JS		 1012 enum ath5k_power_mode ah_power_mode;
1013 struct ieee80211_channel ah_current_channel;
1014 bool ah_turbo;
1015 bool ah_calibration;
1016 bool ah_running;
1017 bool ah_single_chip;
1018 enum ath5k_rfgain ah_rf_gain;
1019
1020 u32 ah_mac_srev;
1021 u16 ah_mac_version;
1022 u16 ah_mac_revision;
1023 u16 ah_phy_revision;
1024 u16 ah_radio_5ghz_revision;
1025 u16 ah_radio_2ghz_revision;
0af22563 1026 u32 ah_phy_spending;
fa1c114f
JS		 1027
1028 enum ath5k_version ah_version;
1029 enum ath5k_radio ah_radio;
1030 u32 ah_phy;
1031
1032 bool ah_5ghz;
1033 bool ah_2ghz;
1034
1035#define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1036#define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1037#define ah_modes ah_capabilities.cap_mode
1038#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1039
1040 u32 ah_atim_window;
1041 u32 ah_aifs;
1042 u32 ah_cw_min;
1043 u32 ah_cw_max;
1044 bool ah_software_retry;
1045 u32 ah_limit_tx_retries;
1046
1047 u32 ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1048 bool ah_ant_diversity;
1049
1050 u8 ah_sta_id[ETH_ALEN];
1051
1052 /* Current BSSID we are trying to assoc to / creating.
1053 * This is passed by mac80211 on config_interface() and cached here for
1054 * use in resets */
1055 u8 ah_bssid[ETH_ALEN];
1056
1057 u32 ah_gpio[AR5K_MAX_GPIO];
1058 int ah_gpio_npins;
1059
1060 struct ath5k_capabilities ah_capabilities;
1061
1062 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1063 u32 ah_txq_status;
1064 u32 ah_txq_imr_txok;
1065 u32 ah_txq_imr_txerr;
1066 u32 ah_txq_imr_txurn;
1067 u32 ah_txq_imr_txdesc;
1068 u32 ah_txq_imr_txeol;
1069 u32 *ah_rf_banks;
1070 size_t ah_rf_banks_size;
1071 struct ath5k_gain ah_gain;
1072 u32 ah_offset[AR5K_MAX_RF_BANKS];
1073
1074 struct {
1075 u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1076 u16 txp_rates[AR5K_MAX_RATES];
1077 s16 txp_min;
1078 s16 txp_max;
1079 bool txp_tpc;
1080 s16 txp_ofdm;
1081 } ah_txpower;
1082
1083 struct {
1084 bool r_enabled;
1085 int r_last_alert;
1086 struct ieee80211_channel r_last_channel;
1087 } ah_radar;
1088
1089 /* noise floor from last periodic calibration */
1090 s32 ah_noise_floor;
1091
1092 /*
1093 * Function pointers
1094 */
c6e387a2
NK		 1095 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1096 u32 size, unsigned int flags);
fa1c114f
JS		 1097 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1098 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1099 unsigned int, unsigned int, unsigned int, unsigned int,
1100 unsigned int, unsigned int, unsigned int);
c6e387a2 1101 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
fa1c114f
JS		 1102 unsigned int, unsigned int, unsigned int, unsigned int,
1103 unsigned int, unsigned int);
b47f407b
BR		 1104 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1105 struct ath5k_tx_status *);
1106 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1107 struct ath5k_rx_status *);
fa1c114f
JS		 1108};
1109
1110/*
1111 * Prototypes
1112 */
1113
fa1c114f
JS		 1114/* Attach/Detach Functions */
1115extern struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version);
fa1c114f 1116extern void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1117
fa1c114f 1118/* Reset Functions */
c6e387a2 1119extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
05c914fe 1120extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
fa1c114f
JS		 1121/* Power management functions */
1122extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
c6e387a2 1123
fa1c114f 1124/* DMA Related Functions */
c6e387a2 1125extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
fa1c114f 1126extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
c6e387a2
NK		 1127extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1128extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1129extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1130extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
c6e387a2
NK		 1131extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1132extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1133 u32 phys_addr);
fa1c114f
JS		 1134extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1135/* Interrupt handling */
1136extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1137extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
c6e387a2
NK		 1138extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum
1139ath5k_int new_mask);
194828a2 1140extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct ieee80211_low_level_stats *stats);
c6e387a2 1141
fa1c114f 1142/* EEPROM access functions */
c6e387a2
NK		 1143extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1144extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1145
fa1c114f
JS		 1146/* Protocol Control Unit Functions */
1147extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1148/* BSSID Functions */
1149extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1150extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1151extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1152extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1153/* Receive start/stop functions */
1154extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
c6e387a2 1155extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f
JS		 1156/* RX Filter functions */
1157extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
c6e387a2 1158extern int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
fa1c114f
JS		 1159extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
1160extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1161extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1162/* Beacon control functions */
fa1c114f
JS		 1163extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
1164extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1165extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1166extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1167#if 0
1168extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct ath5k_beacon_state *state);
1169extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1170extern int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1171#endif
fa1c114f
JS		 1172/* ACK bit rate */
1173void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1174/* ACK/CTS Timeouts */
1175extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1176extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1177extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1178extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1179/* Key table (WEP) functions */
1180extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1181extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
1182extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct ieee80211_key_conf *key, const u8 *mac);
1183extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
c6e387a2 1184
fa1c114f 1185/* Queue Control Unit, DFS Control Unit Functions */
fa1c114f 1186extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct ath5k_txq_info *queue_info);
c6e387a2
NK		 1187extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1188 const struct ath5k_txq_info *queue_info);
1189extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1190 enum ath5k_tx_queue queue_type,
1191 struct ath5k_txq_info *queue_info);
1192extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
fa1c114f
JS		 1193extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1194extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
fa1c114f 1195extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
c6e387a2
NK		 1196extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1197
fa1c114f 1198/* Hardware Descriptor Functions */
c6e387a2
NK		 1199extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1200
fa1c114f
JS		 1201/* GPIO Functions */
1202extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
fa1c114f 1203extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
c6e387a2 1204extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
fa1c114f
JS		 1205extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1206extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1207extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
c6e387a2 1208
fa1c114f 1209/* Misc functions */
c6e387a2 1210int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
fa1c114f 1211extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
c6e387a2
NK		 1212extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1213extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1214
1215/* Initial register settings functions */
1216extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1217
fa1c114f
JS		 1218/* Initialize RF */
1219extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
1220extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
1221extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
1222extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
fa1c114f
JS		 1223/* PHY/RF channel functions */
1224extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1225extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1226/* PHY calibration */
1227extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct ieee80211_channel *channel);
c6e387a2 1228extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
fa1c114f
JS		 1229/* Misc PHY functions */
1230extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1231extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1232extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
c6e387a2 1233extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
fa1c114f
JS		 1234/* TX power setup */
1235extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int txpower);
1236extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
1237
c6e387a2
NK		 1238/*
1239 * Functions used internaly
1240 */
1241
1242/*
1243 * Translate usec to hw clock units
1244 */
1245static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
1246{
1247 return turbo ? (usec * 80) : (usec * 40);
1248}
fa1c114f 1249
c6e387a2
NK		 1250/*
1251 * Translate hw clock units to usec
1252 */
1253static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
1254{
1255 return turbo ? (clock / 80) : (clock / 40);
1256}
1257
1258/*
1259 * Read from a register
1260 */
fa1c114f
JS		 1261static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1262{
1263 return ioread32(ah->ah_iobase + reg);
1264}
1265
c6e387a2
NK		 1266/*
1267 * Write to a register
1268 */
fa1c114f
JS		 1269static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1270{
1271 iowrite32(val, ah->ah_iobase + reg);
1272}
1273
c6e387a2
NK		 1274#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1275/*
1276 * Check if a register write has been completed
1277 */
1278static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1279 u32 val, bool is_set)
1280{
1281 int i;
1282 u32 data;
1283
1284 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1285 data = ath5k_hw_reg_read(ah, reg);
1286 if (is_set && (data & flag))
1287 break;
1288 else if ((data & flag) == val)
1289 break;
1290 udelay(15);
1291 }
1292
1293 return (i <= 0) ? -EAGAIN : 0;
1294}
1295#endif
1296
1297static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1298{
1299 u32 retval = 0, bit, i;
1300
1301 for (i = 0; i < bits; i++) {
1302 bit = (val >> i) & 1;
1303 retval = (retval << 1) | bit;
1304 }
1305
1306 return retval;
1307}
1308
fa1c114f 1309#endif
Linux 6.x block layer and io_uring tree(s)