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mwifiex: fix decimal printf format specifiers prefixed with 0x
[linux-2.6-block.git] / drivers / net / wireless / ath / wil6210 / wil6210.h
CommitLineData
2be7d22f
VK		 1/*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef __WIL6210_H__
18#define __WIL6210_H__
19
20#include <linux/netdevice.h>
21#include <linux/wireless.h>
22#include <net/cfg80211.h>
7c0acf86 23#include <linux/timex.h>
2be7d22f 24
2be7d22f
VK		 25#define WIL_NAME "wil6210"
26
6508281b
VK		 27struct wil_board {
28 int board;
29#define WIL_BOARD_MARLON (1)
30#define WIL_BOARD_SPARROW (2)
31 const char * const name;
32};
33
2be7d22f
VK		 34/**
35 * extract bits [@b0:@b1] (inclusive) from the value @x
36 * it should be @b0 <= @b1, or result is incorrect
37 */
38static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
39{
40 return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
41}
42
43#define WIL6210_MEM_SIZE (2*1024*1024UL)
44
e0287c4a 45#define WIL6210_RX_RING_SIZE (128)
6c9ec5eb 46#define WIL6210_TX_RING_SIZE (512)
e0287c4a
VK		 47#define WIL6210_MAX_TX_RINGS (24) /* HW limit */
48#define WIL6210_MAX_CID (8) /* HW limit */
49#define WIL6210_NAPI_BUDGET (16) /* arbitrary */
83982cbe 50#define WIL6210_ITR_TRSH (10000) /* arbitrary - about 15 IRQs/msec */
fc219eed
VK		 51#define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */
52#define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000)
047e5d74 53#define WIL6210_SCAN_TO msecs_to_jiffies(10000)
2be7d22f
VK		 54
55/* Hardware definitions begin */
56
57/*
58 * Mapping
59 * RGF File | Host addr | FW addr
60 * | |
61 * user_rgf | 0x000000 | 0x880000
62 * dma_rgf | 0x001000 | 0x881000
63 * pcie_rgf | 0x002000 | 0x882000
64 * | |
65 */
66
67/* Where various structures placed in host address space */
68#define WIL6210_FW_HOST_OFF (0x880000UL)
69
70#define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF)
71
72/*
73 * Interrupt control registers block
74 *
75 * each interrupt controlled by the same bit in all registers
76 */
77struct RGF_ICR {
78 u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
79 u32 ICR; /* Cause, W1C/COR depending on ICC */
80 u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
81 u32 ICS; /* Cause Set, WO */
82 u32 IMV; /* Mask, RW+S/C */
83 u32 IMS; /* Mask Set, write 1 to set */
84 u32 IMC; /* Mask Clear, write 1 to clear */
85} __packed;
86
87/* registers - FW addresses */
b373de72 88#define RGF_USER_USAGE_1 (0x880004)
d28bcc30
VK		 89#define RGF_USER_HW_MACHINE_STATE (0x8801dc)
90 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
2be7d22f 91#define RGF_USER_USER_CPU_0 (0x8801e0)
17123991
VK		 92#define RGF_USER_MAC_CPU_0 (0x8801fc)
93#define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
94#define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
972072aa
VK		 95#define RGF_USER_CLKS_CTL_0 (0x880abc)
96 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
2be7d22f
VK		 97#define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
98#define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
99#define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
100#define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
17123991
VK		 101#define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
102#define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
103 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
6508281b 104#define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18)
2be7d22f
VK		 105
106#define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
107 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
108 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */
109#define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */
110 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0)
111#define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
112 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
113 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
7269494e 114 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */
2be7d22f
VK		 115
116/* Interrupt moderation control */
117#define RGF_DMA_ITR_CNT_TRSH (0x881c5c)
118#define RGF_DMA_ITR_CNT_DATA (0x881c60)
17123991 119#define RGF_DMA_ITR_CNT_CRL (0x881c64)
2be7d22f
VK		 120 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0)
121 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1)
122 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2)
123 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3)
124 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4)
125
17123991
VK		 126#define RGF_DMA_PSEUDO_CAUSE (0x881c68)
127#define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
128#define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70)
129 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0)
130 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
131 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
132
6508281b 133#define RGF_HP_CTRL (0x88265c)
17123991
VK		 134#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
135
2be7d22f
VK		 136/* popular locations */
137#define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
138#define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
139 offsetof(struct RGF_ICR, ICS))
140#define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
141
142/* ISR register bits */
7269494e
VK		 143#define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0)
144#define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1)
145#define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3)
2be7d22f
VK		 146
147/* Hardware definitions end */
b541d0a0
VK		 148struct fw_map {
149 u32 from; /* linker address - from, inclusive */
150 u32 to; /* linker address - to, exclusive */
151 u32 host; /* PCI/Host address - BAR0 + 0x880000 */
152 const char *name; /* for debugfs */
153};
154/* array size should be in sync with actual definition in the wmi.c */
72269146 155extern const struct fw_map fw_mapping[7];
2be7d22f 156
a70abea5
VK		 157/**
158 * mk_cidxtid - construct @cidxtid field
159 * @cid: CID value
160 * @tid: TID value
161 *
162 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
163 */
164static inline u8 mk_cidxtid(u8 cid, u8 tid)
165{
166 return ((tid & 0xf) << 4) | (cid & 0xf);
167}
168
169/**
170 * parse_cidxtid - parse @cidxtid field
171 * @cid: store CID value here
172 * @tid: store TID value here
173 *
174 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
175 */
176static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
177{
178 *cid = cidxtid & 0xf;
179 *tid = (cidxtid >> 4) & 0xf;
180}
181
2be7d22f
VK		 182struct wil6210_mbox_ring {
183 u32 base;
184 u16 entry_size; /* max. size of mbox entry, incl. all headers */
185 u16 size;
186 u32 tail;
187 u32 head;
188} __packed;
189
190struct wil6210_mbox_ring_desc {
191 __le32 sync;
192 __le32 addr;
193} __packed;
194
195/* at HOST_OFF_WIL6210_MBOX_CTL */
196struct wil6210_mbox_ctl {
197 struct wil6210_mbox_ring tx;
198 struct wil6210_mbox_ring rx;
199} __packed;
200
201struct wil6210_mbox_hdr {
202 __le16 seq;
203 __le16 len; /* payload, bytes after this header */
204 __le16 type;
205 u8 flags;
206 u8 reserved;
207} __packed;
208
209#define WIL_MBOX_HDR_TYPE_WMI (0)
210
211/* max. value for wil6210_mbox_hdr.len */
212#define MAX_MBOXITEM_SIZE (240)
213
f988b23f
VK		 214/**
215 * struct wil6210_mbox_hdr_wmi - WMI header
216 *
217 * @mid: MAC ID
218 * 00 - default, created by FW
219 * 01..0f - WiFi ports, driver to create
220 * 10..fe - debug
221 * ff - broadcast
222 * @id: command/event ID
223 * @timestamp: FW fills for events, free-running msec timer
224 */
2be7d22f 225struct wil6210_mbox_hdr_wmi {
f988b23f
VK		 226 u8 mid;
227 u8 reserved;
2be7d22f 228 __le16 id;
f988b23f 229 __le32 timestamp;
2be7d22f
VK		 230} __packed;
231
232struct pending_wmi_event {
233 struct list_head list;
234 struct {
235 struct wil6210_mbox_hdr hdr;
236 struct wil6210_mbox_hdr_wmi wmi;
237 u8 data[0];
238 } __packed event;
239};
240
2232abd5
VK		 241enum { /* for wil_ctx.mapped_as */
242 wil_mapped_as_none = 0,
243 wil_mapped_as_single = 1,
244 wil_mapped_as_page = 2,
245};
246
f88f113a
VK		 247/**
248 * struct wil_ctx - software context for Vring descriptor
249 */
250struct wil_ctx {
251 struct sk_buff *skb;
c236658f 252 u8 nr_frags;
2232abd5 253 u8 mapped_as;
f88f113a
VK		 254};
255
2be7d22f
VK		 256union vring_desc;
257
258struct vring {
259 dma_addr_t pa;
260 volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
261 u16 size; /* number of vring_desc elements */
262 u32 swtail;
263 u32 swhead;
264 u32 hwtail; /* write here to inform hw */
f88f113a 265 struct wil_ctx *ctx; /* ctx[size] - software context */
2be7d22f
VK		 266};
267
097638a0
VK		 268/**
269 * Additional data for Tx Vring
270 */
271struct vring_tx_data {
272 int enabled;
7c0acf86 273 cycles_t idle, last_idle, begin;
097638a0
VK		 274};
275
2be7d22f
VK		 276enum { /* for wil6210_priv.status */
277 wil_status_fwready = 0,
b338f74e 278 wil_status_fwconnecting,
2be7d22f
VK		 279 wil_status_fwconnected,
280 wil_status_dontscan,
55f7acdd 281 wil_status_reset_done,
2be7d22f 282 wil_status_irqen, /* FIXME: interrupts enabled - for debug */
0fef1818 283 wil_status_napi_en, /* NAPI enabled protected by wil->mutex */
2be7d22f
VK		 284};
285
286struct pci_dev;
287
b4490f42
VK		 288/**
289 * struct tid_ampdu_rx - TID aggregation information (Rx).
290 *
291 * @reorder_buf: buffer to reorder incoming aggregated MPDUs
292 * @reorder_time: jiffies when skb was added
293 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
294 * @reorder_timer: releases expired frames from the reorder buffer.
295 * @last_rx: jiffies of last rx activity
296 * @head_seq_num: head sequence number in reordering buffer.
297 * @stored_mpdu_num: number of MPDUs in reordering buffer
298 * @ssn: Starting Sequence Number expected to be aggregated.
299 * @buf_size: buffer size for incoming A-MPDUs
300 * @timeout: reset timer value (in TUs).
301 * @dialog_token: dialog token for aggregation session
302 * @rcu_head: RCU head used for freeing this struct
303 * @reorder_lock: serializes access to reorder buffer, see below.
304 *
305 * This structure's lifetime is managed by RCU, assignments to
306 * the array holding it must hold the aggregation mutex.
307 *
308 * The @reorder_lock is used to protect the members of this
309 * struct, except for @timeout, @buf_size and @dialog_token,
310 * which are constant across the lifetime of the struct (the
311 * dialog token being used only for debugging).
312 */
313struct wil_tid_ampdu_rx {
314 spinlock_t reorder_lock; /* see above */
315 struct sk_buff **reorder_buf;
316 unsigned long *reorder_time;
317 struct timer_list session_timer;
318 struct timer_list reorder_timer;
319 unsigned long last_rx;
320 u16 head_seq_num;
321 u16 stored_mpdu_num;
322 u16 ssn;
323 u16 buf_size;
324 u16 timeout;
d5b1c32f 325 u16 ssn_last_drop;
b4490f42 326 u8 dialog_token;
c888cdd4 327 bool first_time; /* is it 1-st time this buffer used? */
b4490f42
VK		 328};
329
2be7d22f
VK		 330struct wil6210_stats {
331 u64 tsf;
332 u32 snr;
333 u16 last_mcs_rx;
334 u16 bf_mcs; /* last BF, used for Tx */
335 u16 my_rx_sector;
336 u16 my_tx_sector;
337 u16 peer_rx_sector;
338 u16 peer_tx_sector;
339};
340
3df2cd36
VK		 341enum wil_sta_status {
342 wil_sta_unused = 0,
343 wil_sta_conn_pending = 1,
344 wil_sta_connected = 2,
345};
b4490f42
VK		 346
347#define WIL_STA_TID_NUM (16)
348
c8b78b5f
VK		 349struct wil_net_stats {
350 unsigned long rx_packets;
351 unsigned long tx_packets;
352 unsigned long rx_bytes;
353 unsigned long tx_bytes;
354 unsigned long tx_errors;
355 unsigned long rx_dropped;
356 u16 last_mcs_rx;
357};
358
3df2cd36
VK		 359/**
360 * struct wil_sta_info - data for peer
361 *
362 * Peer identified by its CID (connection ID)
363 * NIC performs beam forming for each peer;
364 * if no beam forming done, frame exchange is not
365 * possible.
366 */
367struct wil_sta_info {
368 u8 addr[ETH_ALEN];
369 enum wil_sta_status status;
c8b78b5f 370 struct wil_net_stats stats;
e58c9f70 371 bool data_port_open; /* can send any data, not only EAPOL */
b4490f42
VK		 372 /* Rx BACK */
373 struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
374 unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
375 unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
3df2cd36
VK		 376};
377
2be7d22f
VK		 378struct wil6210_priv {
379 struct pci_dev *pdev;
380 int n_msi;
381 struct wireless_dev *wdev;
382 void __iomem *csr;
383 ulong status;
b8023177 384 u32 fw_version;
36b10a72 385 u32 hw_version;
6508281b 386 struct wil_board *board;
b8023177 387 u8 n_mids; /* number of additional MIDs as reported by FW */
fc219eed
VK		 388 int recovery_count; /* num of FW recovery attempts in a short time */
389 unsigned long last_fw_recovery; /* jiffies of last fw recovery */
2be7d22f
VK		 390 /* profile */
391 u32 monitor_flags;
392 u32 secure_pcp; /* create secure PCP? */
393 int sinfo_gen;
394 /* cached ISR registers */
395 u32 isr_misc;
396 /* mailbox related */
397 struct mutex wmi_mutex;
398 struct wil6210_mbox_ctl mbox_ctl;
399 struct completion wmi_ready;
400 u16 wmi_seq;
401 u16 reply_id; /**< wait for this WMI event */
402 void *reply_buf;
403 u16 reply_size;
404 struct workqueue_struct *wmi_wq; /* for deferred calls */
405 struct work_struct wmi_event_worker;
406 struct workqueue_struct *wmi_wq_conn; /* for connect worker */
d81079f1 407 struct work_struct connect_worker;
2be7d22f 408 struct work_struct disconnect_worker;
ed6f9dc6 409 struct work_struct fw_error_worker; /* for FW error recovery */
2be7d22f 410 struct timer_list connect_timer;
047e5d74 411 struct timer_list scan_timer; /* detect scan timeout */
2be7d22f
VK		 412 int pending_connect_cid;
413 struct list_head pending_wmi_ev;
414 /*
415 * protect pending_wmi_ev
416 * - fill in IRQ from wil6210_irq_misc,
417 * - consumed in thread by wmi_event_worker
418 */
419 spinlock_t wmi_ev_lock;
e0287c4a
VK		 420 struct napi_struct napi_rx;
421 struct napi_struct napi_tx;
2be7d22f
VK		 422 /* DMA related */
423 struct vring vring_rx;
424 struct vring vring_tx[WIL6210_MAX_TX_RINGS];
097638a0 425 struct vring_tx_data vring_tx_data[WIL6210_MAX_TX_RINGS];
3df2cd36
VK		 426 u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
427 struct wil_sta_info sta[WIL6210_MAX_CID];
2be7d22f
VK		 428 /* scan */
429 struct cfg80211_scan_request *scan_request;
430
431 struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
432 /* statistics */
433 struct wil6210_stats stats;
be299858 434 atomic_t isr_count_rx, isr_count_tx;
2be7d22f
VK		 435 /* debugfs */
436 struct dentry *debug;
b541d0a0 437 struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
2be7d22f
VK		 438};
439
440#define wil_to_wiphy(i) (i->wdev->wiphy)
441#define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
442#define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
443#define wil_to_wdev(i) (i->wdev)
444#define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
445#define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
446#define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
447
98658095
VK		 448int wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
449int wil_err(struct wil6210_priv *wil, const char *fmt, ...);
450int wil_info(struct wil6210_priv *wil, const char *fmt, ...);
451#define wil_dbg(wil, fmt, arg...) do { \
452 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
453 wil_dbg_trace(wil, fmt, ##arg); \
454} while (0)
2be7d22f 455
7743882d
VK		 456#define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
457#define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
458#define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
459#define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
2be7d22f 460
7743882d 461#define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \
2be7d22f 462 groupsize, buf, len, ascii) \
3b0378a8 463 print_hex_dump_debug("DBG[TXRX]" prefix_str,\
2be7d22f
VK		 464 prefix_type, rowsize, \
465 groupsize, buf, len, ascii)
466
7743882d 467#define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \
2be7d22f 468 groupsize, buf, len, ascii) \
3b0378a8 469 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
2be7d22f
VK		 470 prefix_type, rowsize, \
471 groupsize, buf, len, ascii)
472
473void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
474 size_t count);
475void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
476 size_t count);
477
478void *wil_if_alloc(struct device *dev, void __iomem *csr);
479void wil_if_free(struct wil6210_priv *wil);
480int wil_if_add(struct wil6210_priv *wil);
481void wil_if_remove(struct wil6210_priv *wil);
482int wil_priv_init(struct wil6210_priv *wil);
483void wil_priv_deinit(struct wil6210_priv *wil);
484int wil_reset(struct wil6210_priv *wil);
ed6f9dc6 485void wil_fw_error_recovery(struct wil6210_priv *wil);
2be7d22f
VK		 486void wil_link_on(struct wil6210_priv *wil);
487void wil_link_off(struct wil6210_priv *wil);
488int wil_up(struct wil6210_priv *wil);
489int wil_down(struct wil6210_priv *wil);
490void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
3df2cd36 491int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
2be7d22f
VK		 492
493void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
494void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
495int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
496 struct wil6210_mbox_hdr *hdr);
497int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
498void wmi_recv_cmd(struct wil6210_priv *wil);
499int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
500 u16 reply_id, void *reply, u8 reply_size, int to_msec);
2be7d22f
VK		 501void wmi_event_worker(struct work_struct *work);
502void wmi_event_flush(struct wil6210_priv *wil);
503int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
504int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
505int wmi_set_channel(struct wil6210_priv *wil, int channel);
506int wmi_get_channel(struct wil6210_priv *wil, int *channel);
2be7d22f
VK		 507int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
508 const void *mac_addr);
509int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
510 const void *mac_addr, int key_len, const void *key);
511int wmi_echo(struct wil6210_priv *wil);
512int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
47e19af9 513int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
b8023177 514int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
1647f12f 515int wmi_rxon(struct wil6210_priv *wil, bool on);
1a2780e0 516int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
4d55a0a1 517int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
2be7d22f 518
f4b5a803 519void wil6210_clear_irq(struct wil6210_priv *wil);
2be7d22f
VK		 520int wil6210_init_irq(struct wil6210_priv *wil, int irq);
521void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
522void wil6210_disable_irq(struct wil6210_priv *wil);
523void wil6210_enable_irq(struct wil6210_priv *wil);
0b39aaf2
VK		 524int wil_cfg80211_mgmt_tx(struct wiphy *wiphy, struct wireless_dev *wdev,
525 struct cfg80211_mgmt_tx_params *params,
526 u64 *cookie);
2be7d22f
VK		 527
528int wil6210_debugfs_init(struct wil6210_priv *wil);
529void wil6210_debugfs_remove(struct wil6210_priv *wil);
9eb82d43
VK		 530int wil_cid_fill_sinfo(struct wil6210_priv *wil, int cid,
531 struct station_info *sinfo);
2be7d22f
VK		 532
533struct wireless_dev *wil_cfg80211_init(struct device *dev);
534void wil_wdev_free(struct wil6210_priv *wil);
535
536int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
b8023177
VK		 537int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan);
538int wmi_pcp_stop(struct wil6210_priv *wil);
3b3a0162 539void wil6210_disconnect(struct wil6210_priv *wil, const u8 *bssid);
2be7d22f
VK		 540
541int wil_rx_init(struct wil6210_priv *wil);
542void wil_rx_fini(struct wil6210_priv *wil);
543
544/* TX API */
545int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
546 int cid, int tid);
547void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
548
549netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
e0287c4a
VK		 550int wil_tx_complete(struct wil6210_priv *wil, int ringid);
551void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
2be7d22f
VK		 552
553/* RX API */
e0287c4a
VK		 554void wil_rx_handle(struct wil6210_priv *wil, int *quota);
555void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
2be7d22f
VK		 556
557int wil_iftype_nl2wmi(enum nl80211_iftype type);
558
559#endif /* __WIL6210_H__ */
Linux 6.x block layer and io_uring tree(s)