Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 | 61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 62 | struct ath_txq *txq, |
e8324357 S |
63 | struct list_head *bf_q, |
64 | int txok, int sendbar); | |
102e0572 | 65 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
66 | struct list_head *head); |
67 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 VT |
68 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
69 | int txok); | |
70 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, | |
8a92e2ee | 71 | int nbad, int txok, bool update_rc); |
c4288390 | 72 | |
e8324357 S |
73 | /*********************/ |
74 | /* Aggregation logic */ | |
75 | /*********************/ | |
f078f209 | 76 | |
e8324357 | 77 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 78 | { |
e8324357 | 79 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 80 | |
e8324357 S |
81 | if (tid->paused) |
82 | return; | |
ff37e337 | 83 | |
e8324357 S |
84 | if (tid->sched) |
85 | return; | |
ff37e337 | 86 | |
e8324357 S |
87 | tid->sched = true; |
88 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 89 | |
e8324357 S |
90 | if (ac->sched) |
91 | return; | |
f078f209 | 92 | |
e8324357 S |
93 | ac->sched = true; |
94 | list_add_tail(&ac->list, &txq->axq_acq); | |
95 | } | |
f078f209 | 96 | |
e8324357 S |
97 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
98 | { | |
99 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 100 | |
e8324357 S |
101 | spin_lock_bh(&txq->axq_lock); |
102 | tid->paused++; | |
103 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
104 | } |
105 | ||
e8324357 | 106 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 107 | { |
e8324357 | 108 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 109 | |
e8324357 S |
110 | ASSERT(tid->paused > 0); |
111 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 112 | |
e8324357 | 113 | tid->paused--; |
f078f209 | 114 | |
e8324357 S |
115 | if (tid->paused > 0) |
116 | goto unlock; | |
f078f209 | 117 | |
e8324357 S |
118 | if (list_empty(&tid->buf_q)) |
119 | goto unlock; | |
f078f209 | 120 | |
e8324357 S |
121 | ath_tx_queue_tid(txq, tid); |
122 | ath_txq_schedule(sc, txq); | |
123 | unlock: | |
124 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 125 | } |
f078f209 | 126 | |
e8324357 | 127 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 128 | { |
e8324357 S |
129 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
130 | struct ath_buf *bf; | |
131 | struct list_head bf_head; | |
132 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 133 | |
e8324357 S |
134 | ASSERT(tid->paused > 0); |
135 | spin_lock_bh(&txq->axq_lock); | |
e6a9854b | 136 | |
e8324357 | 137 | tid->paused--; |
f078f209 | 138 | |
e8324357 S |
139 | if (tid->paused > 0) { |
140 | spin_unlock_bh(&txq->axq_lock); | |
141 | return; | |
142 | } | |
f078f209 | 143 | |
e8324357 S |
144 | while (!list_empty(&tid->buf_q)) { |
145 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
146 | ASSERT(!bf_isretried(bf)); | |
d43f3015 | 147 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 148 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 149 | } |
f078f209 | 150 | |
e8324357 | 151 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 152 | } |
f078f209 | 153 | |
e8324357 S |
154 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
155 | int seqno) | |
528f0c6b | 156 | { |
e8324357 | 157 | int index, cindex; |
f078f209 | 158 | |
e8324357 S |
159 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
160 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 161 | |
e8324357 | 162 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 163 | |
e8324357 S |
164 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
165 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
166 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
167 | } | |
528f0c6b | 168 | } |
f078f209 | 169 | |
e8324357 S |
170 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
171 | struct ath_buf *bf) | |
528f0c6b | 172 | { |
e8324357 | 173 | int index, cindex; |
528f0c6b | 174 | |
e8324357 S |
175 | if (bf_isretried(bf)) |
176 | return; | |
528f0c6b | 177 | |
e8324357 S |
178 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
179 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 180 | |
e8324357 S |
181 | ASSERT(tid->tx_buf[cindex] == NULL); |
182 | tid->tx_buf[cindex] = bf; | |
f078f209 | 183 | |
e8324357 S |
184 | if (index >= ((tid->baw_tail - tid->baw_head) & |
185 | (ATH_TID_MAX_BUFS - 1))) { | |
186 | tid->baw_tail = cindex; | |
187 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 188 | } |
f078f209 LR |
189 | } |
190 | ||
191 | /* | |
e8324357 S |
192 | * TODO: For frame(s) that are in the retry state, we will reuse the |
193 | * sequence number(s) without setting the retry bit. The | |
194 | * alternative is to give up on these and BAR the receiver's window | |
195 | * forward. | |
f078f209 | 196 | */ |
e8324357 S |
197 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
198 | struct ath_atx_tid *tid) | |
f078f209 | 199 | |
f078f209 | 200 | { |
e8324357 S |
201 | struct ath_buf *bf; |
202 | struct list_head bf_head; | |
203 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 204 | |
e8324357 S |
205 | for (;;) { |
206 | if (list_empty(&tid->buf_q)) | |
207 | break; | |
f078f209 | 208 | |
d43f3015 S |
209 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
210 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 211 | |
e8324357 S |
212 | if (bf_isretried(bf)) |
213 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 214 | |
e8324357 | 215 | spin_unlock(&txq->axq_lock); |
fec247c0 | 216 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
e8324357 S |
217 | spin_lock(&txq->axq_lock); |
218 | } | |
f078f209 | 219 | |
e8324357 S |
220 | tid->seq_next = tid->seq_start; |
221 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
222 | } |
223 | ||
fec247c0 S |
224 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
225 | struct ath_buf *bf) | |
f078f209 | 226 | { |
e8324357 S |
227 | struct sk_buff *skb; |
228 | struct ieee80211_hdr *hdr; | |
f078f209 | 229 | |
e8324357 S |
230 | bf->bf_state.bf_type |= BUF_RETRY; |
231 | bf->bf_retries++; | |
fec247c0 | 232 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 233 | |
e8324357 S |
234 | skb = bf->bf_mpdu; |
235 | hdr = (struct ieee80211_hdr *)skb->data; | |
236 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
237 | } |
238 | ||
d43f3015 S |
239 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
240 | { | |
241 | struct ath_buf *tbf; | |
242 | ||
243 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
244 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
245 | spin_unlock_bh(&sc->tx.txbuflock); | |
246 | return NULL; | |
247 | } | |
d43f3015 S |
248 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
249 | list_del(&tbf->list); | |
250 | spin_unlock_bh(&sc->tx.txbuflock); | |
251 | ||
252 | ATH_TXBUF_RESET(tbf); | |
253 | ||
254 | tbf->bf_mpdu = bf->bf_mpdu; | |
255 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
256 | *(tbf->bf_desc) = *(bf->bf_desc); | |
257 | tbf->bf_state = bf->bf_state; | |
258 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
259 | ||
260 | return tbf; | |
261 | } | |
262 | ||
263 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
264 | struct ath_buf *bf, struct list_head *bf_q, | |
265 | int txok) | |
f078f209 | 266 | { |
e8324357 S |
267 | struct ath_node *an = NULL; |
268 | struct sk_buff *skb; | |
1286ec6d S |
269 | struct ieee80211_sta *sta; |
270 | struct ieee80211_hdr *hdr; | |
e8324357 | 271 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 272 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 273 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 274 | struct list_head bf_head, bf_pending; |
0934af23 | 275 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 276 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
277 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
278 | bool rc_update = true; | |
f078f209 | 279 | |
a22be22a | 280 | skb = bf->bf_mpdu; |
1286ec6d S |
281 | hdr = (struct ieee80211_hdr *)skb->data; |
282 | ||
283 | rcu_read_lock(); | |
f078f209 | 284 | |
1286ec6d S |
285 | sta = ieee80211_find_sta(sc->hw, hdr->addr1); |
286 | if (!sta) { | |
287 | rcu_read_unlock(); | |
288 | return; | |
f078f209 LR |
289 | } |
290 | ||
1286ec6d S |
291 | an = (struct ath_node *)sta->drv_priv; |
292 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
293 | ||
e8324357 | 294 | isaggr = bf_isaggr(bf); |
d43f3015 | 295 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 296 | |
d43f3015 S |
297 | if (isaggr && txok) { |
298 | if (ATH_DS_TX_BA(ds)) { | |
299 | seq_st = ATH_DS_BA_SEQ(ds); | |
300 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
301 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 302 | } else { |
d43f3015 S |
303 | /* |
304 | * AR5416 can become deaf/mute when BA | |
305 | * issue happens. Chip needs to be reset. | |
306 | * But AP code may have sychronization issues | |
307 | * when perform internal reset in this routine. | |
308 | * Only enable reset in STA mode for now. | |
309 | */ | |
2660b81a | 310 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 311 | needreset = 1; |
e8324357 | 312 | } |
f078f209 LR |
313 | } |
314 | ||
e8324357 S |
315 | INIT_LIST_HEAD(&bf_pending); |
316 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 317 | |
0934af23 | 318 | nbad = ath_tx_num_badfrms(sc, bf, txok); |
e8324357 S |
319 | while (bf) { |
320 | txfail = txpending = 0; | |
321 | bf_next = bf->bf_next; | |
f078f209 | 322 | |
e8324357 S |
323 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
324 | /* transmit completion, subframe is | |
325 | * acked by block ack */ | |
0934af23 | 326 | acked_cnt++; |
e8324357 S |
327 | } else if (!isaggr && txok) { |
328 | /* transmit completion */ | |
0934af23 | 329 | acked_cnt++; |
e8324357 | 330 | } else { |
e8324357 S |
331 | if (!(tid->state & AGGR_CLEANUP) && |
332 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
333 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
fec247c0 | 334 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
335 | txpending = 1; |
336 | } else { | |
337 | bf->bf_state.bf_type |= BUF_XRETRY; | |
338 | txfail = 1; | |
339 | sendbar = 1; | |
0934af23 | 340 | txfail_cnt++; |
e8324357 S |
341 | } |
342 | } else { | |
343 | /* | |
344 | * cleanup in progress, just fail | |
345 | * the un-acked sub-frames | |
346 | */ | |
347 | txfail = 1; | |
348 | } | |
349 | } | |
f078f209 | 350 | |
e8324357 | 351 | if (bf_next == NULL) { |
cbfe89c6 VT |
352 | /* |
353 | * Make sure the last desc is reclaimed if it | |
354 | * not a holding desc. | |
355 | */ | |
356 | if (!bf_last->bf_stale) | |
357 | list_move_tail(&bf->list, &bf_head); | |
358 | else | |
359 | INIT_LIST_HEAD(&bf_head); | |
e8324357 S |
360 | } else { |
361 | ASSERT(!list_empty(bf_q)); | |
d43f3015 | 362 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 363 | } |
f078f209 | 364 | |
e8324357 S |
365 | if (!txpending) { |
366 | /* | |
367 | * complete the acked-ones/xretried ones; update | |
368 | * block-ack window | |
369 | */ | |
370 | spin_lock_bh(&txq->axq_lock); | |
371 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
372 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 373 | |
8a92e2ee VT |
374 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
375 | ath_tx_rc_status(bf, ds, nbad, txok, true); | |
376 | rc_update = false; | |
377 | } else { | |
378 | ath_tx_rc_status(bf, ds, nbad, txok, false); | |
379 | } | |
380 | ||
fec247c0 | 381 | ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar); |
e8324357 | 382 | } else { |
d43f3015 | 383 | /* retry the un-acked ones */ |
a119cc49 | 384 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 385 | struct ath_buf *tbf; |
f078f209 | 386 | |
d43f3015 | 387 | tbf = ath_clone_txbuf(sc, bf_last); |
c41d92dc VT |
388 | /* |
389 | * Update tx baw and complete the frame with | |
390 | * failed status if we run out of tx buf | |
391 | */ | |
392 | if (!tbf) { | |
393 | spin_lock_bh(&txq->axq_lock); | |
394 | ath_tx_update_baw(sc, tid, | |
395 | bf->bf_seqno); | |
396 | spin_unlock_bh(&txq->axq_lock); | |
397 | ||
398 | bf->bf_state.bf_type |= BUF_XRETRY; | |
399 | ath_tx_rc_status(bf, ds, nbad, | |
400 | 0, false); | |
fec247c0 S |
401 | ath_tx_complete_buf(sc, bf, txq, |
402 | &bf_head, 0, 0); | |
8a46097a | 403 | break; |
c41d92dc VT |
404 | } |
405 | ||
d43f3015 | 406 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); |
e8324357 S |
407 | list_add_tail(&tbf->list, &bf_head); |
408 | } else { | |
409 | /* | |
410 | * Clear descriptor status words for | |
411 | * software retry | |
412 | */ | |
d43f3015 | 413 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
414 | } |
415 | ||
416 | /* | |
417 | * Put this buffer to the temporary pending | |
418 | * queue to retain ordering | |
419 | */ | |
420 | list_splice_tail_init(&bf_head, &bf_pending); | |
421 | } | |
422 | ||
423 | bf = bf_next; | |
f078f209 | 424 | } |
f078f209 | 425 | |
e8324357 | 426 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
427 | if (tid->baw_head == tid->baw_tail) { |
428 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 429 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 430 | |
e8324357 S |
431 | /* send buffered frames as singles */ |
432 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 433 | } |
1286ec6d | 434 | rcu_read_unlock(); |
e8324357 S |
435 | return; |
436 | } | |
f078f209 | 437 | |
d43f3015 | 438 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
439 | if (!list_empty(&bf_pending)) { |
440 | spin_lock_bh(&txq->axq_lock); | |
441 | list_splice(&bf_pending, &tid->buf_q); | |
442 | ath_tx_queue_tid(txq, tid); | |
443 | spin_unlock_bh(&txq->axq_lock); | |
444 | } | |
102e0572 | 445 | |
1286ec6d S |
446 | rcu_read_unlock(); |
447 | ||
e8324357 S |
448 | if (needreset) |
449 | ath_reset(sc, false); | |
e8324357 | 450 | } |
f078f209 | 451 | |
e8324357 S |
452 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
453 | struct ath_atx_tid *tid) | |
f078f209 | 454 | { |
4f0fc7c3 | 455 | const struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
456 | struct sk_buff *skb; |
457 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 458 | struct ieee80211_tx_rate *rates; |
e8324357 | 459 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 460 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 461 | u16 aggr_limit, legacy = 0; |
e8324357 | 462 | int i; |
528f0c6b | 463 | |
a22be22a | 464 | skb = bf->bf_mpdu; |
528f0c6b | 465 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 466 | rates = tx_info->control.rates; |
d43f3015 | 467 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 468 | |
e8324357 S |
469 | /* |
470 | * Find the lowest frame length among the rate series that will have a | |
471 | * 4ms transmit duration. | |
472 | * TODO - TXOP limit needs to be considered. | |
473 | */ | |
474 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 475 | |
e8324357 S |
476 | for (i = 0; i < 4; i++) { |
477 | if (rates[i].count) { | |
478 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
479 | legacy = 1; | |
480 | break; | |
481 | } | |
482 | ||
d43f3015 S |
483 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
484 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
485 | } |
486 | } | |
e63835b0 | 487 | |
f078f209 | 488 | /* |
e8324357 S |
489 | * limit aggregate size by the minimum rate if rate selected is |
490 | * not a probe rate, if rate selected is a probe rate then | |
491 | * avoid aggregation of this packet. | |
f078f209 | 492 | */ |
e8324357 S |
493 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
494 | return 0; | |
f078f209 | 495 | |
4ef70841 | 496 | aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX); |
f078f209 | 497 | |
e8324357 S |
498 | /* |
499 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
500 | * The IE, however can hold upto 65536, which shows up here | |
501 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 502 | */ |
4ef70841 S |
503 | if (tid->an->maxampdu) |
504 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 505 | |
e8324357 S |
506 | return aggr_limit; |
507 | } | |
f078f209 | 508 | |
e8324357 | 509 | /* |
d43f3015 | 510 | * Returns the number of delimiters to be added to |
e8324357 | 511 | * meet the minimum required mpdudensity. |
e8324357 S |
512 | */ |
513 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
514 | struct ath_buf *bf, u16 frmlen) | |
515 | { | |
4f0fc7c3 | 516 | const struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
517 | struct sk_buff *skb = bf->bf_mpdu; |
518 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 519 | u32 nsymbits, nsymbols; |
e8324357 S |
520 | u16 minlen; |
521 | u8 rc, flags, rix; | |
522 | int width, half_gi, ndelim, mindelim; | |
523 | ||
524 | /* Select standard number of delimiters based on frame length alone */ | |
525 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
526 | |
527 | /* | |
e8324357 S |
528 | * If encryption enabled, hardware requires some more padding between |
529 | * subframes. | |
530 | * TODO - this could be improved to be dependent on the rate. | |
531 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 532 | */ |
e8324357 S |
533 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
534 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 535 | |
e8324357 S |
536 | /* |
537 | * Convert desired mpdu density from microeconds to bytes based | |
538 | * on highest rate in rate series (i.e. first rate) to determine | |
539 | * required minimum length for subframe. Take into account | |
540 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 541 | * |
e8324357 S |
542 | * If there is no mpdu density restriction, no further calculation |
543 | * is needed. | |
544 | */ | |
4ef70841 S |
545 | |
546 | if (tid->an->mpdudensity == 0) | |
e8324357 | 547 | return ndelim; |
f078f209 | 548 | |
e8324357 S |
549 | rix = tx_info->control.rates[0].idx; |
550 | flags = tx_info->control.rates[0].flags; | |
551 | rc = rt->info[rix].ratecode; | |
552 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
553 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 554 | |
e8324357 | 555 | if (half_gi) |
4ef70841 | 556 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 557 | else |
4ef70841 | 558 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 559 | |
e8324357 S |
560 | if (nsymbols == 0) |
561 | nsymbols = 1; | |
f078f209 | 562 | |
e8324357 S |
563 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
564 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 565 | |
e8324357 | 566 | if (frmlen < minlen) { |
e8324357 S |
567 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
568 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
569 | } |
570 | ||
e8324357 | 571 | return ndelim; |
f078f209 LR |
572 | } |
573 | ||
e8324357 | 574 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 575 | struct ath_txq *txq, |
d43f3015 S |
576 | struct ath_atx_tid *tid, |
577 | struct list_head *bf_q) | |
f078f209 | 578 | { |
e8324357 | 579 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
580 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
581 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
582 | u16 aggr_limit = 0, al = 0, bpad = 0, |
583 | al_delta, h_baw = tid->baw_size / 2; | |
584 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 585 | |
e8324357 | 586 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 587 | |
e8324357 S |
588 | do { |
589 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 590 | |
d43f3015 | 591 | /* do not step over block-ack window */ |
e8324357 S |
592 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
593 | status = ATH_AGGR_BAW_CLOSED; | |
594 | break; | |
595 | } | |
f078f209 | 596 | |
e8324357 S |
597 | if (!rl) { |
598 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
599 | rl = 1; | |
600 | } | |
f078f209 | 601 | |
d43f3015 | 602 | /* do not exceed aggregation limit */ |
e8324357 | 603 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 604 | |
d43f3015 S |
605 | if (nframes && |
606 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
607 | status = ATH_AGGR_LIMITED; |
608 | break; | |
609 | } | |
f078f209 | 610 | |
d43f3015 S |
611 | /* do not exceed subframe limit */ |
612 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
613 | status = ATH_AGGR_LIMITED; |
614 | break; | |
615 | } | |
d43f3015 | 616 | nframes++; |
f078f209 | 617 | |
d43f3015 | 618 | /* add padding for previous frame to aggregation length */ |
e8324357 | 619 | al += bpad + al_delta; |
f078f209 | 620 | |
e8324357 S |
621 | /* |
622 | * Get the delimiters needed to meet the MPDU | |
623 | * density for this node. | |
624 | */ | |
625 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 626 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 627 | |
e8324357 | 628 | bf->bf_next = NULL; |
d43f3015 | 629 | bf->bf_desc->ds_link = 0; |
f078f209 | 630 | |
d43f3015 | 631 | /* link buffers of this frame to the aggregate */ |
e8324357 | 632 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
633 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
634 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
635 | if (bf_prev) { |
636 | bf_prev->bf_next = bf; | |
d43f3015 | 637 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
638 | } |
639 | bf_prev = bf; | |
fec247c0 | 640 | |
e8324357 | 641 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 642 | |
e8324357 S |
643 | bf_first->bf_al = al; |
644 | bf_first->bf_nframes = nframes; | |
d43f3015 | 645 | |
e8324357 S |
646 | return status; |
647 | #undef PADBYTES | |
648 | } | |
f078f209 | 649 | |
e8324357 S |
650 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
651 | struct ath_atx_tid *tid) | |
652 | { | |
d43f3015 | 653 | struct ath_buf *bf; |
e8324357 S |
654 | enum ATH_AGGR_STATUS status; |
655 | struct list_head bf_q; | |
f078f209 | 656 | |
e8324357 S |
657 | do { |
658 | if (list_empty(&tid->buf_q)) | |
659 | return; | |
f078f209 | 660 | |
e8324357 S |
661 | INIT_LIST_HEAD(&bf_q); |
662 | ||
fec247c0 | 663 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 664 | |
f078f209 | 665 | /* |
d43f3015 S |
666 | * no frames picked up to be aggregated; |
667 | * block-ack window is not open. | |
f078f209 | 668 | */ |
e8324357 S |
669 | if (list_empty(&bf_q)) |
670 | break; | |
f078f209 | 671 | |
e8324357 | 672 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 673 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 674 | |
d43f3015 | 675 | /* if only one frame, send as non-aggregate */ |
e8324357 | 676 | if (bf->bf_nframes == 1) { |
e8324357 | 677 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 678 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
679 | ath_buf_set_rate(sc, bf); |
680 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
681 | continue; | |
682 | } | |
f078f209 | 683 | |
d43f3015 | 684 | /* setup first desc of aggregate */ |
e8324357 S |
685 | bf->bf_state.bf_type |= BUF_AGGR; |
686 | ath_buf_set_rate(sc, bf); | |
687 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 688 | |
d43f3015 S |
689 | /* anchor last desc of aggregate */ |
690 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 691 | |
e8324357 | 692 | txq->axq_aggr_depth++; |
e8324357 | 693 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 694 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 695 | |
e8324357 S |
696 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
697 | status != ATH_AGGR_BAW_CLOSED); | |
698 | } | |
699 | ||
f83da965 S |
700 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
701 | u16 tid, u16 *ssn) | |
e8324357 S |
702 | { |
703 | struct ath_atx_tid *txtid; | |
704 | struct ath_node *an; | |
705 | ||
706 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
707 | txtid = ATH_AN_2_TID(an, tid); |
708 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
709 | ath_tx_pause_tid(sc, txtid); | |
710 | *ssn = txtid->seq_start; | |
e8324357 | 711 | } |
f078f209 | 712 | |
f83da965 | 713 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
714 | { |
715 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
716 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
717 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
718 | struct ath_buf *bf; | |
719 | struct list_head bf_head; | |
720 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 721 | |
e8324357 | 722 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 723 | return; |
f078f209 | 724 | |
e8324357 | 725 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 726 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 727 | return; |
e8324357 | 728 | } |
f078f209 | 729 | |
e8324357 S |
730 | ath_tx_pause_tid(sc, txtid); |
731 | ||
732 | /* drop all software retried frames and mark this TID */ | |
733 | spin_lock_bh(&txq->axq_lock); | |
734 | while (!list_empty(&txtid->buf_q)) { | |
735 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
736 | if (!bf_isretried(bf)) { | |
737 | /* | |
738 | * NB: it's based on the assumption that | |
739 | * software retried frame will always stay | |
740 | * at the head of software queue. | |
741 | */ | |
742 | break; | |
743 | } | |
d43f3015 | 744 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 745 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
fec247c0 | 746 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 | 747 | } |
d43f3015 | 748 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 749 | |
e8324357 | 750 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
751 | txtid->state |= AGGR_CLEANUP; |
752 | } else { | |
753 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 754 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 755 | } |
e8324357 | 756 | } |
f078f209 | 757 | |
e8324357 S |
758 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
759 | { | |
760 | struct ath_atx_tid *txtid; | |
761 | struct ath_node *an; | |
762 | ||
763 | an = (struct ath_node *)sta->drv_priv; | |
764 | ||
765 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
766 | txtid = ATH_AN_2_TID(an, tid); | |
767 | txtid->baw_size = | |
768 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
769 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
770 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
771 | ath_tx_resume_tid(sc, txtid); | |
772 | } | |
f078f209 LR |
773 | } |
774 | ||
e8324357 | 775 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 776 | { |
e8324357 | 777 | struct ath_atx_tid *txtid; |
c4288390 | 778 | |
e8324357 S |
779 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
780 | return false; | |
c4288390 | 781 | |
e8324357 S |
782 | txtid = ATH_AN_2_TID(an, tidno); |
783 | ||
c3d8f02e | 784 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 785 | return true; |
e8324357 | 786 | return false; |
c4288390 S |
787 | } |
788 | ||
e8324357 S |
789 | /********************/ |
790 | /* Queue Management */ | |
791 | /********************/ | |
f078f209 | 792 | |
e8324357 S |
793 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
794 | struct ath_txq *txq) | |
f078f209 | 795 | { |
e8324357 S |
796 | struct ath_atx_ac *ac, *ac_tmp; |
797 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 798 | |
e8324357 S |
799 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
800 | list_del(&ac->list); | |
801 | ac->sched = false; | |
802 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
803 | list_del(&tid->list); | |
804 | tid->sched = false; | |
805 | ath_tid_drain(sc, txq, tid); | |
806 | } | |
f078f209 LR |
807 | } |
808 | } | |
809 | ||
e8324357 | 810 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 811 | { |
cbe61d8a | 812 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
813 | struct ath9k_tx_queue_info qi; |
814 | int qnum; | |
f078f209 | 815 | |
e8324357 S |
816 | memset(&qi, 0, sizeof(qi)); |
817 | qi.tqi_subtype = subtype; | |
818 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
819 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
820 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
821 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
822 | |
823 | /* | |
e8324357 S |
824 | * Enable interrupts only for EOL and DESC conditions. |
825 | * We mark tx descriptors to receive a DESC interrupt | |
826 | * when a tx queue gets deep; otherwise waiting for the | |
827 | * EOL to reap descriptors. Note that this is done to | |
828 | * reduce interrupt load and this only defers reaping | |
829 | * descriptors, never transmitting frames. Aside from | |
830 | * reducing interrupts this also permits more concurrency. | |
831 | * The only potential downside is if the tx queue backs | |
832 | * up in which case the top half of the kernel may backup | |
833 | * due to a lack of tx descriptors. | |
834 | * | |
835 | * The UAPSD queue is an exception, since we take a desc- | |
836 | * based intr on the EOSP frames. | |
f078f209 | 837 | */ |
e8324357 S |
838 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
839 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
840 | else | |
841 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
842 | TXQ_FLAG_TXDESCINT_ENABLE; | |
843 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
844 | if (qnum == -1) { | |
f078f209 | 845 | /* |
e8324357 S |
846 | * NB: don't print a message, this happens |
847 | * normally on parts with too few tx queues | |
f078f209 | 848 | */ |
e8324357 | 849 | return NULL; |
f078f209 | 850 | } |
e8324357 S |
851 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
852 | DPRINTF(sc, ATH_DBG_FATAL, | |
853 | "qnum %u out of range, max %u!\n", | |
854 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
855 | ath9k_hw_releasetxqueue(ah, qnum); | |
856 | return NULL; | |
857 | } | |
858 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
859 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 860 | |
e8324357 S |
861 | txq->axq_qnum = qnum; |
862 | txq->axq_link = NULL; | |
863 | INIT_LIST_HEAD(&txq->axq_q); | |
864 | INIT_LIST_HEAD(&txq->axq_acq); | |
865 | spin_lock_init(&txq->axq_lock); | |
866 | txq->axq_depth = 0; | |
867 | txq->axq_aggr_depth = 0; | |
e8324357 | 868 | txq->axq_linkbuf = NULL; |
164ace38 | 869 | txq->axq_tx_inprogress = false; |
e8324357 S |
870 | sc->tx.txqsetup |= 1<<qnum; |
871 | } | |
872 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
873 | } |
874 | ||
e8324357 | 875 | static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 876 | { |
e8324357 | 877 | int qnum; |
f078f209 | 878 | |
e8324357 S |
879 | switch (qtype) { |
880 | case ATH9K_TX_QUEUE_DATA: | |
881 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
882 | DPRINTF(sc, ATH_DBG_FATAL, | |
883 | "HAL AC %u out of range, max %zu!\n", | |
884 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
885 | return -1; | |
886 | } | |
887 | qnum = sc->tx.hwq_map[haltype]; | |
888 | break; | |
889 | case ATH9K_TX_QUEUE_BEACON: | |
890 | qnum = sc->beacon.beaconq; | |
891 | break; | |
892 | case ATH9K_TX_QUEUE_CAB: | |
893 | qnum = sc->beacon.cabq->axq_qnum; | |
894 | break; | |
895 | default: | |
896 | qnum = -1; | |
897 | } | |
898 | return qnum; | |
899 | } | |
f078f209 | 900 | |
e8324357 S |
901 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
902 | { | |
903 | struct ath_txq *txq = NULL; | |
904 | int qnum; | |
f078f209 | 905 | |
e8324357 S |
906 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
907 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 908 | |
e8324357 S |
909 | spin_lock_bh(&txq->axq_lock); |
910 | ||
911 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c117fa0b | 912 | DPRINTF(sc, ATH_DBG_XMIT, |
e8324357 S |
913 | "TX queue: %d is full, depth: %d\n", |
914 | qnum, txq->axq_depth); | |
915 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); | |
916 | txq->stopped = 1; | |
917 | spin_unlock_bh(&txq->axq_lock); | |
918 | return NULL; | |
f078f209 LR |
919 | } |
920 | ||
e8324357 S |
921 | spin_unlock_bh(&txq->axq_lock); |
922 | ||
923 | return txq; | |
924 | } | |
925 | ||
926 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
927 | struct ath9k_tx_queue_info *qinfo) | |
928 | { | |
cbe61d8a | 929 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
930 | int error = 0; |
931 | struct ath9k_tx_queue_info qi; | |
932 | ||
933 | if (qnum == sc->beacon.beaconq) { | |
934 | /* | |
935 | * XXX: for beacon queue, we just save the parameter. | |
936 | * It will be picked up by ath_beaconq_config when | |
937 | * it's necessary. | |
938 | */ | |
939 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 940 | return 0; |
e8324357 | 941 | } |
f078f209 | 942 | |
e8324357 S |
943 | ASSERT(sc->tx.txq[qnum].axq_qnum == qnum); |
944 | ||
945 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
946 | qi.tqi_aifs = qinfo->tqi_aifs; | |
947 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
948 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
949 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
950 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
951 | ||
952 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
953 | DPRINTF(sc, ATH_DBG_FATAL, | |
954 | "Unable to update hardware queue %u!\n", qnum); | |
955 | error = -EIO; | |
956 | } else { | |
957 | ath9k_hw_resettxqueue(ah, qnum); | |
958 | } | |
959 | ||
960 | return error; | |
961 | } | |
962 | ||
963 | int ath_cabq_update(struct ath_softc *sc) | |
964 | { | |
965 | struct ath9k_tx_queue_info qi; | |
966 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 967 | |
e8324357 | 968 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 969 | /* |
e8324357 | 970 | * Ensure the readytime % is within the bounds. |
f078f209 | 971 | */ |
17d7904d S |
972 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
973 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
974 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
975 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 976 | |
57c4d7b4 | 977 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 978 | sc->config.cabqReadytime) / 100; |
e8324357 S |
979 | ath_txq_update(sc, qnum, &qi); |
980 | ||
981 | return 0; | |
f078f209 LR |
982 | } |
983 | ||
043a0405 S |
984 | /* |
985 | * Drain a given TX queue (could be Beacon or Data) | |
986 | * | |
987 | * This assumes output has been stopped and | |
988 | * we do not need to block ath_tx_tasklet. | |
989 | */ | |
990 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 991 | { |
e8324357 S |
992 | struct ath_buf *bf, *lastbf; |
993 | struct list_head bf_head; | |
f078f209 | 994 | |
e8324357 | 995 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 996 | |
e8324357 S |
997 | for (;;) { |
998 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 999 | |
e8324357 S |
1000 | if (list_empty(&txq->axq_q)) { |
1001 | txq->axq_link = NULL; | |
1002 | txq->axq_linkbuf = NULL; | |
1003 | spin_unlock_bh(&txq->axq_lock); | |
1004 | break; | |
1005 | } | |
f078f209 | 1006 | |
e8324357 | 1007 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1008 | |
a119cc49 | 1009 | if (bf->bf_stale) { |
e8324357 S |
1010 | list_del(&bf->list); |
1011 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1012 | |
e8324357 S |
1013 | spin_lock_bh(&sc->tx.txbuflock); |
1014 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1015 | spin_unlock_bh(&sc->tx.txbuflock); | |
1016 | continue; | |
1017 | } | |
f078f209 | 1018 | |
e8324357 S |
1019 | lastbf = bf->bf_lastbf; |
1020 | if (!retry_tx) | |
1021 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1022 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1023 | |
e8324357 S |
1024 | /* remove ath_buf's of the same mpdu from txq */ |
1025 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1026 | txq->axq_depth--; | |
f078f209 | 1027 | |
e8324357 S |
1028 | spin_unlock_bh(&txq->axq_lock); |
1029 | ||
1030 | if (bf_isampdu(bf)) | |
d43f3015 | 1031 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 | 1032 | else |
fec247c0 | 1033 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 LR |
1034 | } |
1035 | ||
164ace38 SB |
1036 | spin_lock_bh(&txq->axq_lock); |
1037 | txq->axq_tx_inprogress = false; | |
1038 | spin_unlock_bh(&txq->axq_lock); | |
1039 | ||
e8324357 S |
1040 | /* flush any pending frames if aggregation is enabled */ |
1041 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1042 | if (!retry_tx) { | |
1043 | spin_lock_bh(&txq->axq_lock); | |
1044 | ath_txq_drain_pending_buffers(sc, txq); | |
1045 | spin_unlock_bh(&txq->axq_lock); | |
1046 | } | |
1047 | } | |
f078f209 LR |
1048 | } |
1049 | ||
043a0405 | 1050 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1051 | { |
cbe61d8a | 1052 | struct ath_hw *ah = sc->sc_ah; |
043a0405 S |
1053 | struct ath_txq *txq; |
1054 | int i, npend = 0; | |
1055 | ||
1056 | if (sc->sc_flags & SC_OP_INVALID) | |
1057 | return; | |
1058 | ||
1059 | /* Stop beacon queue */ | |
1060 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1061 | ||
1062 | /* Stop data queues */ | |
1063 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1064 | if (ATH_TXQ_SETUP(sc, i)) { | |
1065 | txq = &sc->tx.txq[i]; | |
1066 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1067 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | if (npend) { | |
1072 | int r; | |
1073 | ||
1074 | DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); | |
1075 | ||
1076 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1077 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); |
043a0405 S |
1078 | if (r) |
1079 | DPRINTF(sc, ATH_DBG_FATAL, | |
6b45784f | 1080 | "Unable to reset hardware; reset status %d\n", |
043a0405 S |
1081 | r); |
1082 | spin_unlock_bh(&sc->sc_resetlock); | |
1083 | } | |
1084 | ||
1085 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1086 | if (ATH_TXQ_SETUP(sc, i)) | |
1087 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1088 | } | |
e8324357 | 1089 | } |
f078f209 | 1090 | |
043a0405 | 1091 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1092 | { |
043a0405 S |
1093 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1094 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1095 | } |
f078f209 | 1096 | |
e8324357 S |
1097 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1098 | { | |
1099 | struct ath_atx_ac *ac; | |
1100 | struct ath_atx_tid *tid; | |
f078f209 | 1101 | |
e8324357 S |
1102 | if (list_empty(&txq->axq_acq)) |
1103 | return; | |
f078f209 | 1104 | |
e8324357 S |
1105 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1106 | list_del(&ac->list); | |
1107 | ac->sched = false; | |
f078f209 | 1108 | |
e8324357 S |
1109 | do { |
1110 | if (list_empty(&ac->tid_q)) | |
1111 | return; | |
f078f209 | 1112 | |
e8324357 S |
1113 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1114 | list_del(&tid->list); | |
1115 | tid->sched = false; | |
f078f209 | 1116 | |
e8324357 S |
1117 | if (tid->paused) |
1118 | continue; | |
f078f209 | 1119 | |
164ace38 | 1120 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1121 | |
1122 | /* | |
e8324357 S |
1123 | * add tid to round-robin queue if more frames |
1124 | * are pending for the tid | |
f078f209 | 1125 | */ |
e8324357 S |
1126 | if (!list_empty(&tid->buf_q)) |
1127 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1128 | |
e8324357 S |
1129 | break; |
1130 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1131 | |
e8324357 S |
1132 | if (!list_empty(&ac->tid_q)) { |
1133 | if (!ac->sched) { | |
1134 | ac->sched = true; | |
1135 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1136 | } |
e8324357 S |
1137 | } |
1138 | } | |
f078f209 | 1139 | |
e8324357 S |
1140 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1141 | { | |
1142 | struct ath_txq *txq; | |
f078f209 | 1143 | |
e8324357 S |
1144 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
1145 | DPRINTF(sc, ATH_DBG_FATAL, | |
1146 | "HAL AC %u out of range, max %zu!\n", | |
1147 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
1148 | return 0; | |
1149 | } | |
1150 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1151 | if (txq != NULL) { | |
1152 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1153 | return 1; | |
1154 | } else | |
1155 | return 0; | |
f078f209 LR |
1156 | } |
1157 | ||
e8324357 S |
1158 | /***********/ |
1159 | /* TX, DMA */ | |
1160 | /***********/ | |
1161 | ||
f078f209 | 1162 | /* |
e8324357 S |
1163 | * Insert a chain of ath_buf (descriptors) on a txq and |
1164 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1165 | */ |
e8324357 S |
1166 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1167 | struct list_head *head) | |
f078f209 | 1168 | { |
cbe61d8a | 1169 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1170 | struct ath_buf *bf; |
f078f209 | 1171 | |
e8324357 S |
1172 | /* |
1173 | * Insert the frame on the outbound list and | |
1174 | * pass it on to the hardware. | |
1175 | */ | |
f078f209 | 1176 | |
e8324357 S |
1177 | if (list_empty(head)) |
1178 | return; | |
f078f209 | 1179 | |
e8324357 | 1180 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1181 | |
e8324357 S |
1182 | list_splice_tail_init(head, &txq->axq_q); |
1183 | txq->axq_depth++; | |
e8324357 | 1184 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); |
f078f209 | 1185 | |
e8324357 S |
1186 | DPRINTF(sc, ATH_DBG_QUEUE, |
1187 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1188 | |
e8324357 S |
1189 | if (txq->axq_link == NULL) { |
1190 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
1191 | DPRINTF(sc, ATH_DBG_XMIT, | |
1192 | "TXDP[%u] = %llx (%p)\n", | |
1193 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
1194 | } else { | |
1195 | *txq->axq_link = bf->bf_daddr; | |
1196 | DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", | |
1197 | txq->axq_qnum, txq->axq_link, | |
1198 | ito64(bf->bf_daddr), bf->bf_desc); | |
1199 | } | |
1200 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1201 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1202 | } | |
f078f209 | 1203 | |
e8324357 S |
1204 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1205 | { | |
1206 | struct ath_buf *bf = NULL; | |
f078f209 | 1207 | |
e8324357 | 1208 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1209 | |
e8324357 S |
1210 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1211 | spin_unlock_bh(&sc->tx.txbuflock); | |
1212 | return NULL; | |
1213 | } | |
f078f209 | 1214 | |
e8324357 S |
1215 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1216 | list_del(&bf->list); | |
f078f209 | 1217 | |
e8324357 | 1218 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1219 | |
e8324357 | 1220 | return bf; |
f078f209 LR |
1221 | } |
1222 | ||
e8324357 S |
1223 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1224 | struct list_head *bf_head, | |
1225 | struct ath_tx_control *txctl) | |
f078f209 LR |
1226 | { |
1227 | struct ath_buf *bf; | |
f078f209 | 1228 | |
e8324357 S |
1229 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1230 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1231 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1232 | |
e8324357 S |
1233 | /* |
1234 | * Do not queue to h/w when any of the following conditions is true: | |
1235 | * - there are pending frames in software queue | |
1236 | * - the TID is currently paused for ADDBA/BAR request | |
1237 | * - seqno is not within block-ack window | |
1238 | * - h/w queue depth exceeds low water mark | |
1239 | */ | |
1240 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1241 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1242 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1243 | /* |
e8324357 S |
1244 | * Add this frame to software queue for scheduling later |
1245 | * for aggregation. | |
f078f209 | 1246 | */ |
d43f3015 | 1247 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1248 | ath_tx_queue_tid(txctl->txq, tid); |
1249 | return; | |
1250 | } | |
1251 | ||
1252 | /* Add sub-frame to BAW */ | |
1253 | ath_tx_addto_baw(sc, tid, bf); | |
1254 | ||
1255 | /* Queue to h/w without aggregation */ | |
1256 | bf->bf_nframes = 1; | |
d43f3015 | 1257 | bf->bf_lastbf = bf; |
e8324357 S |
1258 | ath_buf_set_rate(sc, bf); |
1259 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1260 | } |
1261 | ||
c37452b0 S |
1262 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1263 | struct ath_atx_tid *tid, | |
1264 | struct list_head *bf_head) | |
e8324357 S |
1265 | { |
1266 | struct ath_buf *bf; | |
1267 | ||
e8324357 S |
1268 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1269 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1270 | ||
1271 | /* update starting sequence number for subsequent ADDBA request */ | |
1272 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1273 | ||
1274 | bf->bf_nframes = 1; | |
d43f3015 | 1275 | bf->bf_lastbf = bf; |
e8324357 S |
1276 | ath_buf_set_rate(sc, bf); |
1277 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1278 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1279 | } |
1280 | ||
c37452b0 S |
1281 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1282 | struct list_head *bf_head) | |
1283 | { | |
1284 | struct ath_buf *bf; | |
1285 | ||
1286 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1287 | ||
1288 | bf->bf_lastbf = bf; | |
1289 | bf->bf_nframes = 1; | |
1290 | ath_buf_set_rate(sc, bf); | |
1291 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1292 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1293 | } |
1294 | ||
e8324357 S |
1295 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1296 | { | |
1297 | struct ieee80211_hdr *hdr; | |
1298 | enum ath9k_pkt_type htype; | |
1299 | __le16 fc; | |
1300 | ||
1301 | hdr = (struct ieee80211_hdr *)skb->data; | |
1302 | fc = hdr->frame_control; | |
1303 | ||
1304 | if (ieee80211_is_beacon(fc)) | |
1305 | htype = ATH9K_PKT_TYPE_BEACON; | |
1306 | else if (ieee80211_is_probe_resp(fc)) | |
1307 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1308 | else if (ieee80211_is_atim(fc)) | |
1309 | htype = ATH9K_PKT_TYPE_ATIM; | |
1310 | else if (ieee80211_is_pspoll(fc)) | |
1311 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1312 | else | |
1313 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1314 | ||
1315 | return htype; | |
1316 | } | |
1317 | ||
1318 | static bool is_pae(struct sk_buff *skb) | |
1319 | { | |
1320 | struct ieee80211_hdr *hdr; | |
1321 | __le16 fc; | |
1322 | ||
1323 | hdr = (struct ieee80211_hdr *)skb->data; | |
1324 | fc = hdr->frame_control; | |
1325 | ||
1326 | if (ieee80211_is_data(fc)) { | |
1327 | if (ieee80211_is_nullfunc(fc) || | |
1328 | /* Port Access Entity (IEEE 802.1X) */ | |
1329 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1330 | return true; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | return false; | |
1335 | } | |
1336 | ||
1337 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1338 | { | |
1339 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1340 | ||
1341 | if (tx_info->control.hw_key) { | |
1342 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1343 | return ATH9K_KEY_TYPE_WEP; | |
1344 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1345 | return ATH9K_KEY_TYPE_TKIP; | |
1346 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1347 | return ATH9K_KEY_TYPE_AES; | |
1348 | } | |
1349 | ||
1350 | return ATH9K_KEY_TYPE_CLEAR; | |
1351 | } | |
1352 | ||
1353 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1354 | struct ath_buf *bf) | |
1355 | { | |
1356 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1357 | struct ieee80211_hdr *hdr; | |
1358 | struct ath_node *an; | |
1359 | struct ath_atx_tid *tid; | |
1360 | __le16 fc; | |
1361 | u8 *qc; | |
1362 | ||
1363 | if (!tx_info->control.sta) | |
1364 | return; | |
1365 | ||
1366 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1367 | hdr = (struct ieee80211_hdr *)skb->data; | |
1368 | fc = hdr->frame_control; | |
1369 | ||
1370 | if (ieee80211_is_data_qos(fc)) { | |
1371 | qc = ieee80211_get_qos_ctl(hdr); | |
1372 | bf->bf_tidno = qc[0] & 0xf; | |
1373 | } | |
1374 | ||
1375 | /* | |
1376 | * For HT capable stations, we save tidno for later use. | |
1377 | * We also override seqno set by upper layer with the one | |
1378 | * in tx aggregation state. | |
1379 | * | |
1380 | * If fragmentation is on, the sequence number is | |
1381 | * not overridden, since it has been | |
1382 | * incremented by the fragmentation routine. | |
1383 | * | |
1384 | * FIXME: check if the fragmentation threshold exceeds | |
1385 | * IEEE80211 max. | |
1386 | */ | |
1387 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1388 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1389 | IEEE80211_SEQ_SEQ_SHIFT); | |
1390 | bf->bf_seqno = tid->seq_next; | |
1391 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1392 | } | |
1393 | ||
1394 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1395 | struct ath_txq *txq) | |
1396 | { | |
1397 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1398 | int flags = 0; | |
1399 | ||
1400 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1401 | flags |= ATH9K_TXDESC_INTREQ; | |
1402 | ||
1403 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1404 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1405 | |
1406 | return flags; | |
1407 | } | |
1408 | ||
1409 | /* | |
1410 | * rix - rate index | |
1411 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1412 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1413 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1414 | */ | |
1415 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1416 | int width, int half_gi, bool shortPreamble) | |
1417 | { | |
4f0fc7c3 | 1418 | const struct ath_rate_table *rate_table = sc->cur_rate_table; |
e8324357 S |
1419 | u32 nbits, nsymbits, duration, nsymbols; |
1420 | u8 rc; | |
1421 | int streams, pktlen; | |
1422 | ||
1423 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1424 | rc = rate_table->info[rix].ratecode; | |
1425 | ||
1426 | /* for legacy rates, use old function to compute packet duration */ | |
1427 | if (!IS_HT_RATE(rc)) | |
1428 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1429 | rix, shortPreamble); | |
1430 | ||
1431 | /* find number of symbols: PLCP + data */ | |
1432 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1433 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1434 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1435 | ||
1436 | if (!half_gi) | |
1437 | duration = SYMBOL_TIME(nsymbols); | |
1438 | else | |
1439 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1440 | ||
1441 | /* addup duration for legacy/ht training and signal fields */ | |
1442 | streams = HT_RC_2_STREAMS(rc); | |
1443 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1444 | ||
1445 | return duration; | |
1446 | } | |
1447 | ||
1448 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1449 | { | |
4f0fc7c3 | 1450 | const struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
1451 | struct ath9k_11n_rate_series series[4]; |
1452 | struct sk_buff *skb; | |
1453 | struct ieee80211_tx_info *tx_info; | |
1454 | struct ieee80211_tx_rate *rates; | |
254ad0ff | 1455 | struct ieee80211_hdr *hdr; |
c89424df S |
1456 | int i, flags = 0; |
1457 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1458 | bool is_pspoll; |
e8324357 S |
1459 | |
1460 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1461 | ||
a22be22a | 1462 | skb = bf->bf_mpdu; |
e8324357 S |
1463 | tx_info = IEEE80211_SKB_CB(skb); |
1464 | rates = tx_info->control.rates; | |
254ad0ff S |
1465 | hdr = (struct ieee80211_hdr *)skb->data; |
1466 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1467 | |
e8324357 | 1468 | /* |
c89424df S |
1469 | * We check if Short Preamble is needed for the CTS rate by |
1470 | * checking the BSS's global flag. | |
1471 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1472 | */ |
c89424df S |
1473 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
1474 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | | |
1475 | rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; | |
1476 | else | |
1477 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; | |
e8324357 | 1478 | |
c89424df S |
1479 | /* |
1480 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1481 | * Check the first rate in the series to decide whether RTS/CTS | |
1482 | * or CTS-to-self has to be used. | |
e8324357 | 1483 | */ |
c89424df S |
1484 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1485 | flags = ATH9K_TXDESC_CTSENA; | |
1486 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1487 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1488 | |
c89424df | 1489 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1490 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1491 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1492 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1493 | } |
1494 | ||
1495 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1496 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1497 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1498 | ||
e8324357 S |
1499 | for (i = 0; i < 4; i++) { |
1500 | if (!rates[i].count || (rates[i].idx < 0)) | |
1501 | continue; | |
1502 | ||
1503 | rix = rates[i].idx; | |
e8324357 | 1504 | series[i].Tries = rates[i].count; |
17d7904d | 1505 | series[i].ChSel = sc->tx_chainmask; |
e8324357 | 1506 | |
c89424df S |
1507 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
1508 | series[i].Rate = rt->info[rix].ratecode | | |
1509 | rt->info[rix].short_preamble; | |
1510 | else | |
1511 | series[i].Rate = rt->info[rix].ratecode; | |
1512 | ||
1513 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1514 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1515 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1516 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1517 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1518 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 S |
1519 | |
1520 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1521 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1522 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
c89424df | 1523 | (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); |
f078f209 LR |
1524 | } |
1525 | ||
e8324357 | 1526 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1527 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1528 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1529 | !is_pspoll, ctsrate, |
c89424df | 1530 | 0, series, 4, flags); |
f078f209 | 1531 | |
17d7904d | 1532 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1533 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1534 | } |
1535 | ||
c52f33d0 | 1536 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1537 | struct sk_buff *skb, |
528f0c6b | 1538 | struct ath_tx_control *txctl) |
f078f209 | 1539 | { |
c52f33d0 JM |
1540 | struct ath_wiphy *aphy = hw->priv; |
1541 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1542 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1543 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1544 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1545 | int hdrlen; |
1546 | __le16 fc; | |
e022edbd | 1547 | |
c112d0c5 LR |
1548 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1549 | if (unlikely(!tx_info_priv)) | |
1550 | return -ENOMEM; | |
a8efee4f | 1551 | tx_info->rate_driver_data[0] = tx_info_priv; |
c52f33d0 | 1552 | tx_info_priv->aphy = aphy; |
f0ed85c6 | 1553 | tx_info_priv->frame_type = txctl->frame_type; |
528f0c6b S |
1554 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1555 | fc = hdr->frame_control; | |
f078f209 | 1556 | |
528f0c6b | 1557 | ATH_TXBUF_RESET(bf); |
f078f209 | 1558 | |
528f0c6b | 1559 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 | 1560 | |
c37452b0 | 1561 | if (conf_is_ht(&sc->hw->conf) && !is_pae(skb)) |
c656bbb5 | 1562 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1563 | |
1564 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1565 | ||
528f0c6b | 1566 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1567 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1568 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1569 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1570 | } else { | |
1571 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1572 | } | |
1573 | ||
d3a1db1c | 1574 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1575 | assign_aggr_tid_seqno(skb, bf); |
1576 | ||
f078f209 | 1577 | bf->bf_mpdu = skb; |
f8316df1 | 1578 | |
7da3c55c GJ |
1579 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1580 | skb->len, DMA_TO_DEVICE); | |
1581 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1582 | bf->bf_mpdu = NULL; |
675902ef S |
1583 | kfree(tx_info_priv); |
1584 | tx_info->rate_driver_data[0] = NULL; | |
1585 | DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1586 | return -ENOMEM; |
1587 | } | |
1588 | ||
528f0c6b | 1589 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1590 | return 0; |
528f0c6b S |
1591 | } |
1592 | ||
1593 | /* FIXME: tx power */ | |
1594 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1595 | struct ath_tx_control *txctl) |
1596 | { | |
a22be22a | 1597 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1598 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1599 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1600 | struct ath_node *an = NULL; |
1601 | struct list_head bf_head; | |
1602 | struct ath_desc *ds; | |
1603 | struct ath_atx_tid *tid; | |
cbe61d8a | 1604 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1605 | int frm_type; |
c37452b0 | 1606 | __le16 fc; |
528f0c6b | 1607 | |
528f0c6b | 1608 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1609 | fc = hdr->frame_control; |
528f0c6b S |
1610 | |
1611 | INIT_LIST_HEAD(&bf_head); | |
1612 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1613 | |
f078f209 LR |
1614 | ds = bf->bf_desc; |
1615 | ds->ds_link = 0; | |
1616 | ds->ds_data = bf->bf_buf_addr; | |
1617 | ||
528f0c6b S |
1618 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1619 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1620 | ||
1621 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1622 | skb->len, /* segment length */ |
1623 | true, /* first segment */ | |
1624 | true, /* last segment */ | |
1625 | ds); /* first descriptor */ | |
f078f209 | 1626 | |
528f0c6b | 1627 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1628 | |
f1617967 JL |
1629 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1630 | tx_info->control.sta) { | |
1631 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1632 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1633 | ||
c37452b0 S |
1634 | if (!ieee80211_is_data_qos(fc)) { |
1635 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1636 | goto tx_done; | |
1637 | } | |
1638 | ||
089e698d | 1639 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
f078f209 LR |
1640 | /* |
1641 | * Try aggregation if it's a unicast data frame | |
1642 | * and the destination is HT capable. | |
1643 | */ | |
528f0c6b | 1644 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1645 | } else { |
1646 | /* | |
528f0c6b S |
1647 | * Send this frame as regular when ADDBA |
1648 | * exchange is neither complete nor pending. | |
f078f209 | 1649 | */ |
c37452b0 S |
1650 | ath_tx_send_ht_normal(sc, txctl->txq, |
1651 | tid, &bf_head); | |
f078f209 LR |
1652 | } |
1653 | } else { | |
c37452b0 | 1654 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1655 | } |
528f0c6b | 1656 | |
c37452b0 | 1657 | tx_done: |
528f0c6b | 1658 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1659 | } |
1660 | ||
f8316df1 | 1661 | /* Upon failure caller should free skb */ |
c52f33d0 | 1662 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1663 | struct ath_tx_control *txctl) |
f078f209 | 1664 | { |
c52f33d0 JM |
1665 | struct ath_wiphy *aphy = hw->priv; |
1666 | struct ath_softc *sc = aphy->sc; | |
528f0c6b | 1667 | struct ath_buf *bf; |
f8316df1 | 1668 | int r; |
f078f209 | 1669 | |
528f0c6b S |
1670 | bf = ath_tx_get_buffer(sc); |
1671 | if (!bf) { | |
04bd4638 | 1672 | DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1673 | return -1; |
1674 | } | |
1675 | ||
c52f33d0 | 1676 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1677 | if (unlikely(r)) { |
c112d0c5 LR |
1678 | struct ath_txq *txq = txctl->txq; |
1679 | ||
f8316df1 | 1680 | DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1681 | |
1682 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1683 | * guarantee this will happen by knowing beforehand that | |
1684 | * we will at least have to run TX completionon one buffer | |
1685 | * on the queue */ | |
1686 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1687 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
c112d0c5 LR |
1688 | ieee80211_stop_queue(sc->hw, |
1689 | skb_get_queue_mapping(skb)); | |
1690 | txq->stopped = 1; | |
1691 | } | |
1692 | spin_unlock_bh(&txq->axq_lock); | |
1693 | ||
b77f483f S |
1694 | spin_lock_bh(&sc->tx.txbuflock); |
1695 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1696 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1697 | |
f8316df1 LR |
1698 | return r; |
1699 | } | |
1700 | ||
8f93b8b3 | 1701 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1702 | |
528f0c6b | 1703 | return 0; |
f078f209 LR |
1704 | } |
1705 | ||
c52f33d0 | 1706 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1707 | { |
c52f33d0 JM |
1708 | struct ath_wiphy *aphy = hw->priv; |
1709 | struct ath_softc *sc = aphy->sc; | |
e8324357 S |
1710 | int hdrlen, padsize; |
1711 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1712 | struct ath_tx_control txctl; | |
f078f209 | 1713 | |
e8324357 | 1714 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1715 | |
1716 | /* | |
e8324357 S |
1717 | * As a temporary workaround, assign seq# here; this will likely need |
1718 | * to be cleaned up to work better with Beacon transmission and virtual | |
1719 | * BSSes. | |
f078f209 | 1720 | */ |
e8324357 S |
1721 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1722 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1723 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1724 | sc->tx.seq_no += 0x10; | |
1725 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1726 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1727 | } |
f078f209 | 1728 | |
e8324357 S |
1729 | /* Add the padding after the header if this is not already done */ |
1730 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1731 | if (hdrlen & 3) { | |
1732 | padsize = hdrlen % 4; | |
1733 | if (skb_headroom(skb) < padsize) { | |
1734 | DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); | |
1735 | dev_kfree_skb_any(skb); | |
1736 | return; | |
1737 | } | |
1738 | skb_push(skb, padsize); | |
1739 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1740 | } |
f078f209 | 1741 | |
e8324357 | 1742 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1743 | |
e8324357 | 1744 | DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); |
f078f209 | 1745 | |
c52f33d0 | 1746 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
e8324357 S |
1747 | DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); |
1748 | goto exit; | |
f078f209 | 1749 | } |
f078f209 | 1750 | |
e8324357 S |
1751 | return; |
1752 | exit: | |
1753 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1754 | } |
1755 | ||
e8324357 S |
1756 | /*****************/ |
1757 | /* TX Completion */ | |
1758 | /*****************/ | |
528f0c6b | 1759 | |
e8324357 | 1760 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
6b2c4032 | 1761 | int tx_flags) |
528f0c6b | 1762 | { |
e8324357 S |
1763 | struct ieee80211_hw *hw = sc->hw; |
1764 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1765 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
1766 | int hdrlen, padsize; | |
f0ed85c6 | 1767 | int frame_type = ATH9K_NOT_INTERNAL; |
528f0c6b | 1768 | |
e8324357 | 1769 | DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1770 | |
f0ed85c6 | 1771 | if (tx_info_priv) { |
c52f33d0 | 1772 | hw = tx_info_priv->aphy->hw; |
f0ed85c6 JM |
1773 | frame_type = tx_info_priv->frame_type; |
1774 | } | |
c52f33d0 | 1775 | |
e8324357 S |
1776 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1777 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1778 | kfree(tx_info_priv); | |
1779 | tx_info->rate_driver_data[0] = NULL; | |
1780 | } | |
528f0c6b | 1781 | |
6b2c4032 | 1782 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1783 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1784 | |
6b2c4032 | 1785 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1786 | /* Frame was ACKed */ |
1787 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1788 | } |
1789 | ||
e8324357 S |
1790 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1791 | padsize = hdrlen & 3; | |
1792 | if (padsize && hdrlen >= 24) { | |
1793 | /* | |
1794 | * Remove MAC header padding before giving the frame back to | |
1795 | * mac80211. | |
1796 | */ | |
1797 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1798 | skb_pull(skb, padsize); | |
1799 | } | |
528f0c6b | 1800 | |
9a23f9ca JM |
1801 | if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { |
1802 | sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; | |
1803 | DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " | |
1804 | "received TX status (0x%x)\n", | |
1805 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | | |
1806 | SC_OP_WAIT_FOR_CAB | | |
1807 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
1808 | SC_OP_WAIT_FOR_TX_ACK)); | |
1809 | } | |
1810 | ||
f0ed85c6 JM |
1811 | if (frame_type == ATH9K_NOT_INTERNAL) |
1812 | ieee80211_tx_status(hw, skb); | |
1813 | else | |
1814 | ath9k_tx_status(hw, skb); | |
e8324357 | 1815 | } |
f078f209 | 1816 | |
e8324357 | 1817 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 1818 | struct ath_txq *txq, |
e8324357 S |
1819 | struct list_head *bf_q, |
1820 | int txok, int sendbar) | |
f078f209 | 1821 | { |
e8324357 | 1822 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1823 | unsigned long flags; |
6b2c4032 | 1824 | int tx_flags = 0; |
f078f209 | 1825 | |
e8324357 | 1826 | if (sendbar) |
6b2c4032 | 1827 | tx_flags = ATH_TX_BAR; |
f078f209 | 1828 | |
e8324357 | 1829 | if (!txok) { |
6b2c4032 | 1830 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1831 | |
e8324357 | 1832 | if (bf_isxretried(bf)) |
6b2c4032 | 1833 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1834 | } |
1835 | ||
e8324357 | 1836 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
6b2c4032 | 1837 | ath_tx_complete(sc, skb, tx_flags); |
fec247c0 | 1838 | ath_debug_stat_tx(sc, txq, bf); |
e8324357 S |
1839 | |
1840 | /* | |
1841 | * Return the list of ath_buf of this mpdu to free queue | |
1842 | */ | |
1843 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1844 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1845 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1846 | } |
1847 | ||
e8324357 S |
1848 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1849 | int txok) | |
f078f209 | 1850 | { |
e8324357 S |
1851 | struct ath_buf *bf_last = bf->bf_lastbf; |
1852 | struct ath_desc *ds = bf_last->bf_desc; | |
1853 | u16 seq_st = 0; | |
1854 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1855 | int ba_index; | |
1856 | int nbad = 0; | |
1857 | int isaggr = 0; | |
f078f209 | 1858 | |
e8324357 S |
1859 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1860 | return 0; | |
f078f209 | 1861 | |
e8324357 S |
1862 | isaggr = bf_isaggr(bf); |
1863 | if (isaggr) { | |
1864 | seq_st = ATH_DS_BA_SEQ(ds); | |
1865 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1866 | } | |
f078f209 | 1867 | |
e8324357 S |
1868 | while (bf) { |
1869 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1870 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1871 | nbad++; | |
1872 | ||
1873 | bf = bf->bf_next; | |
1874 | } | |
f078f209 | 1875 | |
e8324357 S |
1876 | return nbad; |
1877 | } | |
f078f209 | 1878 | |
95e4acb7 | 1879 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, |
8a92e2ee | 1880 | int nbad, int txok, bool update_rc) |
f078f209 | 1881 | { |
a22be22a | 1882 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1883 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 S |
1884 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1885 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
8a92e2ee VT |
1886 | struct ieee80211_hw *hw = tx_info_priv->aphy->hw; |
1887 | u8 i, tx_rateindex; | |
f078f209 | 1888 | |
95e4acb7 S |
1889 | if (txok) |
1890 | tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; | |
1891 | ||
8a92e2ee VT |
1892 | tx_rateindex = ds->ds_txstat.ts_rateindex; |
1893 | WARN_ON(tx_rateindex >= hw->max_rates); | |
1894 | ||
1895 | tx_info_priv->update_rc = update_rc; | |
e8324357 S |
1896 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1897 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1898 | |
e8324357 | 1899 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1900 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1901 | if (ieee80211_is_data(hdr->frame_control)) { |
e8324357 S |
1902 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, |
1903 | sizeof(tx_info_priv->tx)); | |
1904 | tx_info_priv->n_frames = bf->bf_nframes; | |
1905 | tx_info_priv->n_bad_frames = nbad; | |
e8324357 | 1906 | } |
f078f209 | 1907 | } |
8a92e2ee VT |
1908 | |
1909 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) | |
1910 | tx_info->status.rates[i].count = 0; | |
1911 | ||
1912 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1913 | } |
1914 | ||
059d806c S |
1915 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1916 | { | |
1917 | int qnum; | |
1918 | ||
1919 | spin_lock_bh(&txq->axq_lock); | |
1920 | if (txq->stopped && | |
f7a99e46 | 1921 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1922 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1923 | if (qnum != -1) { | |
1924 | ieee80211_wake_queue(sc->hw, qnum); | |
1925 | txq->stopped = 0; | |
1926 | } | |
1927 | } | |
1928 | spin_unlock_bh(&txq->axq_lock); | |
1929 | } | |
1930 | ||
e8324357 | 1931 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1932 | { |
cbe61d8a | 1933 | struct ath_hw *ah = sc->sc_ah; |
e8324357 | 1934 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1935 | struct list_head bf_head; |
e8324357 | 1936 | struct ath_desc *ds; |
0934af23 | 1937 | int txok; |
e8324357 | 1938 | int status; |
f078f209 | 1939 | |
e8324357 S |
1940 | DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1941 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1942 | txq->axq_link); | |
f078f209 | 1943 | |
f078f209 LR |
1944 | for (;;) { |
1945 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1946 | if (list_empty(&txq->axq_q)) { |
1947 | txq->axq_link = NULL; | |
1948 | txq->axq_linkbuf = NULL; | |
1949 | spin_unlock_bh(&txq->axq_lock); | |
1950 | break; | |
1951 | } | |
f078f209 LR |
1952 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1953 | ||
e8324357 S |
1954 | /* |
1955 | * There is a race condition that a BH gets scheduled | |
1956 | * after sw writes TxE and before hw re-load the last | |
1957 | * descriptor to get the newly chained one. | |
1958 | * Software must keep the last DONE descriptor as a | |
1959 | * holding descriptor - software does so by marking | |
1960 | * it with the STALE flag. | |
1961 | */ | |
1962 | bf_held = NULL; | |
a119cc49 | 1963 | if (bf->bf_stale) { |
e8324357 S |
1964 | bf_held = bf; |
1965 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 1966 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
1967 | break; |
1968 | } else { | |
1969 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1970 | struct ath_buf, list); |
e8324357 | 1971 | } |
f078f209 LR |
1972 | } |
1973 | ||
1974 | lastbf = bf->bf_lastbf; | |
e8324357 | 1975 | ds = lastbf->bf_desc; |
f078f209 | 1976 | |
e8324357 S |
1977 | status = ath9k_hw_txprocdesc(ah, ds); |
1978 | if (status == -EINPROGRESS) { | |
f078f209 | 1979 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 1980 | break; |
f078f209 | 1981 | } |
e8324357 S |
1982 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
1983 | txq->axq_lastdsWithCTS = NULL; | |
1984 | if (ds == txq->axq_gatingds) | |
1985 | txq->axq_gatingds = NULL; | |
f078f209 | 1986 | |
e8324357 S |
1987 | /* |
1988 | * Remove ath_buf's of the same transmit unit from txq, | |
1989 | * however leave the last descriptor back as the holding | |
1990 | * descriptor for hw. | |
1991 | */ | |
a119cc49 | 1992 | lastbf->bf_stale = true; |
e8324357 | 1993 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
1994 | if (!list_is_singular(&lastbf->list)) |
1995 | list_cut_position(&bf_head, | |
1996 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 1997 | |
e8324357 | 1998 | txq->axq_depth--; |
e8324357 S |
1999 | if (bf_isaggr(bf)) |
2000 | txq->axq_aggr_depth--; | |
f078f209 | 2001 | |
e8324357 | 2002 | txok = (ds->ds_txstat.ts_status == 0); |
164ace38 | 2003 | txq->axq_tx_inprogress = false; |
e8324357 | 2004 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2005 | |
e8324357 | 2006 | if (bf_held) { |
e8324357 | 2007 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2008 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2009 | spin_unlock_bh(&sc->tx.txbuflock); |
2010 | } | |
f078f209 | 2011 | |
e8324357 S |
2012 | if (!bf_isampdu(bf)) { |
2013 | /* | |
2014 | * This frame is sent out as a single frame. | |
2015 | * Use hardware retry status for this frame. | |
2016 | */ | |
2017 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2018 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2019 | bf->bf_state.bf_type |= BUF_XRETRY; | |
8a92e2ee | 2020 | ath_tx_rc_status(bf, ds, 0, txok, true); |
e8324357 | 2021 | } |
f078f209 | 2022 | |
e8324357 | 2023 | if (bf_isampdu(bf)) |
d43f3015 | 2024 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 | 2025 | else |
fec247c0 | 2026 | ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0); |
8469cdef | 2027 | |
059d806c | 2028 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2029 | |
059d806c | 2030 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2031 | if (sc->sc_flags & SC_OP_TXAGGR) |
2032 | ath_txq_schedule(sc, txq); | |
2033 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2034 | } |
2035 | } | |
2036 | ||
305fe47f | 2037 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2038 | { |
2039 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2040 | tx_complete_work.work); | |
2041 | struct ath_txq *txq; | |
2042 | int i; | |
2043 | bool needreset = false; | |
2044 | ||
2045 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2046 | if (ATH_TXQ_SETUP(sc, i)) { | |
2047 | txq = &sc->tx.txq[i]; | |
2048 | spin_lock_bh(&txq->axq_lock); | |
2049 | if (txq->axq_depth) { | |
2050 | if (txq->axq_tx_inprogress) { | |
2051 | needreset = true; | |
2052 | spin_unlock_bh(&txq->axq_lock); | |
2053 | break; | |
2054 | } else { | |
2055 | txq->axq_tx_inprogress = true; | |
2056 | } | |
2057 | } | |
2058 | spin_unlock_bh(&txq->axq_lock); | |
2059 | } | |
2060 | ||
2061 | if (needreset) { | |
2062 | DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); | |
2063 | ath_reset(sc, false); | |
2064 | } | |
2065 | ||
42935eca | 2066 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2067 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2068 | } | |
2069 | ||
2070 | ||
f078f209 | 2071 | |
e8324357 | 2072 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2073 | { |
e8324357 S |
2074 | int i; |
2075 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2076 | |
e8324357 | 2077 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2078 | |
e8324357 S |
2079 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2080 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2081 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2082 | } |
2083 | } | |
2084 | ||
e8324357 S |
2085 | /*****************/ |
2086 | /* Init, Cleanup */ | |
2087 | /*****************/ | |
f078f209 | 2088 | |
e8324357 | 2089 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2090 | { |
e8324357 | 2091 | int error = 0; |
f078f209 | 2092 | |
797fe5cb | 2093 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2094 | |
797fe5cb S |
2095 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2096 | "tx", nbufs, 1); | |
2097 | if (error != 0) { | |
2098 | DPRINTF(sc, ATH_DBG_FATAL, | |
2099 | "Failed to allocate tx descriptors: %d\n", error); | |
2100 | goto err; | |
2101 | } | |
f078f209 | 2102 | |
797fe5cb S |
2103 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2104 | "beacon", ATH_BCBUF, 1); | |
2105 | if (error != 0) { | |
2106 | DPRINTF(sc, ATH_DBG_FATAL, | |
2107 | "Failed to allocate beacon descriptors: %d\n", error); | |
2108 | goto err; | |
2109 | } | |
f078f209 | 2110 | |
164ace38 SB |
2111 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2112 | ||
797fe5cb | 2113 | err: |
e8324357 S |
2114 | if (error != 0) |
2115 | ath_tx_cleanup(sc); | |
f078f209 | 2116 | |
e8324357 | 2117 | return error; |
f078f209 LR |
2118 | } |
2119 | ||
797fe5cb | 2120 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2121 | { |
2122 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2123 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2124 | ||
2125 | if (sc->tx.txdma.dd_desc_len != 0) | |
2126 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2127 | } |
f078f209 LR |
2128 | |
2129 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2130 | { | |
c5170163 S |
2131 | struct ath_atx_tid *tid; |
2132 | struct ath_atx_ac *ac; | |
2133 | int tidno, acno; | |
f078f209 | 2134 | |
8ee5afbc | 2135 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2136 | tidno < WME_NUM_TID; |
2137 | tidno++, tid++) { | |
2138 | tid->an = an; | |
2139 | tid->tidno = tidno; | |
2140 | tid->seq_start = tid->seq_next = 0; | |
2141 | tid->baw_size = WME_MAX_BA; | |
2142 | tid->baw_head = tid->baw_tail = 0; | |
2143 | tid->sched = false; | |
e8324357 | 2144 | tid->paused = false; |
a37c2c79 | 2145 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2146 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2147 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2148 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2149 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2150 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2151 | } |
f078f209 | 2152 | |
8ee5afbc | 2153 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2154 | acno < WME_NUM_AC; acno++, ac++) { |
2155 | ac->sched = false; | |
2156 | INIT_LIST_HEAD(&ac->tid_q); | |
2157 | ||
2158 | switch (acno) { | |
2159 | case WME_AC_BE: | |
2160 | ac->qnum = ath_tx_get_qnum(sc, | |
2161 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2162 | break; | |
2163 | case WME_AC_BK: | |
2164 | ac->qnum = ath_tx_get_qnum(sc, | |
2165 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2166 | break; | |
2167 | case WME_AC_VI: | |
2168 | ac->qnum = ath_tx_get_qnum(sc, | |
2169 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2170 | break; | |
2171 | case WME_AC_VO: | |
2172 | ac->qnum = ath_tx_get_qnum(sc, | |
2173 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2174 | break; | |
f078f209 LR |
2175 | } |
2176 | } | |
2177 | } | |
2178 | ||
b5aa9bf9 | 2179 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2180 | { |
2181 | int i; | |
2182 | struct ath_atx_ac *ac, *ac_tmp; | |
2183 | struct ath_atx_tid *tid, *tid_tmp; | |
2184 | struct ath_txq *txq; | |
e8324357 | 2185 | |
f078f209 LR |
2186 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2187 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2188 | txq = &sc->tx.txq[i]; |
f078f209 | 2189 | |
b5aa9bf9 | 2190 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2191 | |
2192 | list_for_each_entry_safe(ac, | |
2193 | ac_tmp, &txq->axq_acq, list) { | |
2194 | tid = list_first_entry(&ac->tid_q, | |
2195 | struct ath_atx_tid, list); | |
2196 | if (tid && tid->an != an) | |
2197 | continue; | |
2198 | list_del(&ac->list); | |
2199 | ac->sched = false; | |
2200 | ||
2201 | list_for_each_entry_safe(tid, | |
2202 | tid_tmp, &ac->tid_q, list) { | |
2203 | list_del(&tid->list); | |
2204 | tid->sched = false; | |
b5aa9bf9 | 2205 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2206 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2207 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2208 | } |
2209 | } | |
2210 | ||
b5aa9bf9 | 2211 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2212 | } |
2213 | } | |
2214 | } |