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Merge remote-tracking branches 'regulator/topic/db8500', 'regulator/topic/gpio',...
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / xmit.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
b7f080cf 17#include <linux/dma-mapping.h>
394cf0a1 18#include "ath9k.h"
b622a720 19#include "ar9003_mac.h"
f078f209
LR		 20
21#define BITS_PER_BYTE 8
22#define OFDM_PLCP_BITS 22
f078f209
LR		 23#define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24#define L_STF 8
25#define L_LTF 8
26#define L_SIG 4
27#define HT_SIG 8
28#define HT_STF 4
29#define HT_LTF(_ns) (4 * (_ns))
30#define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
aa5955c3
FF		 32#define TIME_SYMBOLS(t) ((t) >> 2)
33#define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
f078f209
LR		 34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
f078f209 37
c6663876 38static u16 bits_per_symbol[][2] = {
f078f209
LR		 39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
f078f209
LR		 48};
49
50#define IS_HT_RATE(_rate) ((_rate) & 0x80)
51
82b873af 52static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c
FF		 53 struct ath_atx_tid *tid, struct sk_buff *skb);
54static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
55 int tx_flags, struct ath_txq *txq);
e8324357 56static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 57 struct ath_txq *txq, struct list_head *bf_q,
156369fa 58 struct ath_tx_status *ts, int txok);
102e0572 59static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 60 struct list_head *head, bool internal);
0cdd5c60
FF		 61static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
62 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 63 int txok);
90fa539c
FF		 64static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
65 int seqno);
44f1d26c
FF		 66static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
67 struct ath_txq *txq,
68 struct ath_atx_tid *tid,
249ee722 69 struct sk_buff *skb);
c4288390 70
545750d3 71enum {
0e668cde
FF		 72 MCS_HT20,
73 MCS_HT20_SGI,
545750d3
FF		 74 MCS_HT40,
75 MCS_HT40_SGI,
76};
77
e8324357
S		 78/*********************/
79/* Aggregation logic */
80/*********************/
f078f209 81
ef1b6cd9 82void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 83 __acquires(&txq->axq_lock)
23de5dc9
FF		 84{
85 spin_lock_bh(&txq->axq_lock);
86}
87
ef1b6cd9 88void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
1512a486 89 __releases(&txq->axq_lock)
23de5dc9
FF		 90{
91 spin_unlock_bh(&txq->axq_lock);
92}
93
ef1b6cd9 94void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
1512a486 95 __releases(&txq->axq_lock)
23de5dc9
FF		 96{
97 struct sk_buff_head q;
98 struct sk_buff *skb;
99
100 __skb_queue_head_init(&q);
101 skb_queue_splice_init(&txq->complete_q, &q);
102 spin_unlock_bh(&txq->axq_lock);
103
104 while ((skb = __skb_dequeue(&q)))
105 ieee80211_tx_status(sc->hw, skb);
106}
107
e8324357 108static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
ff37e337 109{
e8324357 110 struct ath_atx_ac *ac = tid->ac;
ff37e337 111
e8324357
S		 112 if (tid->paused)
113 return;
ff37e337 114
e8324357
S		 115 if (tid->sched)
116 return;
ff37e337 117
e8324357
S		 118 tid->sched = true;
119 list_add_tail(&tid->list, &ac->tid_q);
528f0c6b 120
e8324357
S		 121 if (ac->sched)
122 return;
f078f209 123
e8324357
S		 124 ac->sched = true;
125 list_add_tail(&ac->list, &txq->axq_acq);
126}
f078f209 127
2d42efc4 128static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
76e45221
FF		 129{
130 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4
FF		 131 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
132 sizeof(tx_info->rate_driver_data));
133 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
76e45221
FF		 134}
135
156369fa
FF		 136static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
137{
f89d1bc4
FF		 138 if (!tid->an->sta)
139 return;
140
156369fa
FF		 141 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
142 seqno << IEEE80211_SEQ_SEQ_SHIFT);
143}
144
79acac07
FF		 145static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
146 struct ath_buf *bf)
147{
148 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
149 ARRAY_SIZE(bf->rates));
150}
151
a4943ccb
FF		 152static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
153 struct sk_buff *skb)
154{
155 int q;
156
157 q = skb_get_queue_mapping(skb);
158 if (txq == sc->tx.uapsdq)
159 txq = sc->tx.txq_map[q];
160
161 if (txq != sc->tx.txq_map[q])
162 return;
163
164 if (WARN_ON(--txq->pending_frames < 0))
165 txq->pending_frames = 0;
166
167 if (txq->stopped &&
168 txq->pending_frames < sc->tx.txq_max_pending[q]) {
169 ieee80211_wake_queue(sc->hw, q);
170 txq->stopped = false;
171 }
172}
173
1803d02d
FF		 174static struct ath_atx_tid *
175ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
176{
177 struct ieee80211_hdr *hdr;
178 u8 tidno = 0;
179
180 hdr = (struct ieee80211_hdr *) skb->data;
181 if (ieee80211_is_data_qos(hdr->frame_control))
182 tidno = ieee80211_get_qos_ctl(hdr)[0];
183
184 tidno &= IEEE80211_QOS_CTL_TID_MASK;
185 return ATH_AN_2_TID(an, tidno);
186}
187
a7586ee4
FF		 188static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
189{
bb195ff6 190 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
a7586ee4
FF		 191}
192
193static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
194{
bb195ff6
FF		 195 struct sk_buff *skb;
196
197 skb = __skb_dequeue(&tid->retry_q);
198 if (!skb)
199 skb = __skb_dequeue(&tid->buf_q);
200
201 return skb;
a7586ee4
FF		 202}
203
2800e82b
FF		 204/*
205 * ath_tx_tid_change_state:
206 * - clears a-mpdu flag of previous session
207 * - force sequence number allocation to fix next BlockAck Window
208 */
209static void
210ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
211{
212 struct ath_txq *txq = tid->ac->txq;
213 struct ieee80211_tx_info *tx_info;
214 struct sk_buff *skb, *tskb;
215 struct ath_buf *bf;
216 struct ath_frame_info *fi;
217
218 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
219 fi = get_frame_info(skb);
220 bf = fi->bf;
221
222 tx_info = IEEE80211_SKB_CB(skb);
223 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
224
225 if (bf)
226 continue;
227
228 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
229 if (!bf) {
230 __skb_unlink(skb, &tid->buf_q);
231 ath_txq_skb_done(sc, txq, skb);
232 ieee80211_free_txskb(sc->hw, skb);
233 continue;
234 }
235 }
236
237}
238
08c96abd 239static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
528f0c6b 240{
066dae93 241 struct ath_txq *txq = tid->ac->txq;
56dc6336 242 struct sk_buff *skb;
e8324357
S		 243 struct ath_buf *bf;
244 struct list_head bf_head;
90fa539c 245 struct ath_tx_status ts;
2d42efc4 246 struct ath_frame_info *fi;
156369fa 247 bool sendbar = false;
f078f209 248
90fa539c 249 INIT_LIST_HEAD(&bf_head);
e6a9854b 250
90fa539c 251 memset(&ts, 0, sizeof(ts));
f078f209 252
2800e82b 253 while ((skb = __skb_dequeue(&tid->retry_q))) {
56dc6336
FF		 254 fi = get_frame_info(skb);
255 bf = fi->bf;
249ee722 256 if (!bf) {
2800e82b
FF		 257 ath_txq_skb_done(sc, txq, skb);
258 ieee80211_free_txskb(sc->hw, skb);
259 continue;
249ee722
FF		 260 }
261
8fed1408 262 if (fi->baw_tracked) {
6a0ddaef 263 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
156369fa 264 sendbar = true;
90fa539c 265 }
2800e82b
FF		 266
267 list_add_tail(&bf->list, &bf_head);
268 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
528f0c6b 269 }
f078f209 270
08c96abd 271 if (sendbar) {
23de5dc9 272 ath_txq_unlock(sc, txq);
156369fa 273 ath_send_bar(tid, tid->seq_start);
23de5dc9
FF		 274 ath_txq_lock(sc, txq);
275 }
528f0c6b 276}
f078f209 277
e8324357
S		 278static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
279 int seqno)
528f0c6b 280{
e8324357 281 int index, cindex;
f078f209 282
e8324357
S		 283 index = ATH_BA_INDEX(tid->seq_start, seqno);
284 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
f078f209 285
81ee13ba 286 __clear_bit(cindex, tid->tx_buf);
528f0c6b 287
81ee13ba 288 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
e8324357
S		 289 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
290 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
f9437543
FF		 291 if (tid->bar_index >= 0)
292 tid->bar_index--;
e8324357 293 }
528f0c6b 294}
f078f209 295
e8324357 296static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
8fed1408 297 struct ath_buf *bf)
528f0c6b 298{
8fed1408
FF		 299 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
300 u16 seqno = bf->bf_state.seqno;
e8324357 301 int index, cindex;
528f0c6b 302
2d3bcba0 303 index = ATH_BA_INDEX(tid->seq_start, seqno);
e8324357 304 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
81ee13ba 305 __set_bit(cindex, tid->tx_buf);
8fed1408 306 fi->baw_tracked = 1;
f078f209 307
e8324357
S		 308 if (index >= ((tid->baw_tail - tid->baw_head) &
309 (ATH_TID_MAX_BUFS - 1))) {
310 tid->baw_tail = cindex;
311 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
f078f209 312 }
f078f209
LR		 313}
314
e8324357
S		 315static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
316 struct ath_atx_tid *tid)
f078f209 317
f078f209 318{
56dc6336 319 struct sk_buff *skb;
e8324357
S		 320 struct ath_buf *bf;
321 struct list_head bf_head;
db1a052b 322 struct ath_tx_status ts;
2d42efc4 323 struct ath_frame_info *fi;
db1a052b
FF		 324
325 memset(&ts, 0, sizeof(ts));
e8324357 326 INIT_LIST_HEAD(&bf_head);
f078f209 327
a7586ee4 328 while ((skb = ath_tid_dequeue(tid))) {
56dc6336
FF		 329 fi = get_frame_info(skb);
330 bf = fi->bf;
f078f209 331
44f1d26c 332 if (!bf) {
44f1d26c 333 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
44f1d26c
FF		 334 continue;
335 }
336
56dc6336 337 list_add_tail(&bf->list, &bf_head);
156369fa 338 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
e8324357 339 }
f078f209
LR		 340}
341
fec247c0 342static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
da647626 343 struct sk_buff *skb, int count)
f078f209 344{
8b7f8532 345 struct ath_frame_info *fi = get_frame_info(skb);
f11cc949 346 struct ath_buf *bf = fi->bf;
e8324357 347 struct ieee80211_hdr *hdr;
da647626 348 int prev = fi->retries;
f078f209 349
fec247c0 350 TX_STAT_INC(txq->axq_qnum, a_retries);
da647626
FF		 351 fi->retries += count;
352
353 if (prev > 0)
2d42efc4 354 return;
f078f209 355
e8324357
S		 356 hdr = (struct ieee80211_hdr *)skb->data;
357 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
f11cc949
FF		 358 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
359 sizeof(*hdr), DMA_TO_DEVICE);
f078f209
LR		 360}
361
0a8cea84 362static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
d43f3015 363{
0a8cea84 364 struct ath_buf *bf = NULL;
d43f3015
S		 365
366 spin_lock_bh(&sc->tx.txbuflock);
0a8cea84
FF		 367
368 if (unlikely(list_empty(&sc->tx.txbuf))) {
8a46097a
VT		 369 spin_unlock_bh(&sc->tx.txbuflock);
370 return NULL;
371 }
0a8cea84
FF		 372
373 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
374 list_del(&bf->list);
375
d43f3015
S		 376 spin_unlock_bh(&sc->tx.txbuflock);
377
0a8cea84
FF		 378 return bf;
379}
380
381static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
382{
383 spin_lock_bh(&sc->tx.txbuflock);
384 list_add_tail(&bf->list, &sc->tx.txbuf);
385 spin_unlock_bh(&sc->tx.txbuflock);
386}
387
388static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
389{
390 struct ath_buf *tbf;
391
392 tbf = ath_tx_get_buffer(sc);
393 if (WARN_ON(!tbf))
394 return NULL;
395
d43f3015
S		 396 ATH_TXBUF_RESET(tbf);
397
398 tbf->bf_mpdu = bf->bf_mpdu;
399 tbf->bf_buf_addr = bf->bf_buf_addr;
d826c832 400 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
d43f3015 401 tbf->bf_state = bf->bf_state;
86c7d8d4 402 tbf->bf_state.stale = false;
d43f3015
S		 403
404 return tbf;
405}
406
b572d033
FF		 407static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
408 struct ath_tx_status *ts, int txok,
409 int *nframes, int *nbad)
410{
2d42efc4 411 struct ath_frame_info *fi;
b572d033
FF		 412 u16 seq_st = 0;
413 u32 ba[WME_BA_BMP_SIZE >> 5];
414 int ba_index;
415 int isaggr = 0;
416
417 *nbad = 0;
418 *nframes = 0;
419
b572d033
FF		 420 isaggr = bf_isaggr(bf);
421 if (isaggr) {
422 seq_st = ts->ts_seqnum;
423 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
424 }
425
426 while (bf) {
2d42efc4 427 fi = get_frame_info(bf->bf_mpdu);
6a0ddaef 428 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
b572d033
FF		 429
430 (*nframes)++;
431 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
432 (*nbad)++;
433
434 bf = bf->bf_next;
435 }
436}
437
438
d43f3015
S		 439static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
440 struct ath_buf *bf, struct list_head *bf_q,
1381559b 441 struct ath_tx_status *ts, int txok)
f078f209 442{
e8324357
S		 443 struct ath_node *an = NULL;
444 struct sk_buff *skb;
1286ec6d 445 struct ieee80211_sta *sta;
0cdd5c60 446 struct ieee80211_hw *hw = sc->hw;
1286ec6d 447 struct ieee80211_hdr *hdr;
76d5a9e8 448 struct ieee80211_tx_info *tx_info;
e8324357 449 struct ath_atx_tid *tid = NULL;
d43f3015 450 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
56dc6336
FF		 451 struct list_head bf_head;
452 struct sk_buff_head bf_pending;
156369fa 453 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
f078f209 454 u32 ba[WME_BA_BMP_SIZE >> 5];
0934af23 455 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
6fe7cc71 456 bool rc_update = true, isba;
78c4653a 457 struct ieee80211_tx_rate rates[4];
2d42efc4 458 struct ath_frame_info *fi;
ebd02287 459 int nframes;
daa5c408 460 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
da647626 461 int i, retries;
156369fa 462 int bar_index = -1;
f078f209 463
a22be22a 464 skb = bf->bf_mpdu;
1286ec6d
S		 465 hdr = (struct ieee80211_hdr *)skb->data;
466
76d5a9e8 467 tx_info = IEEE80211_SKB_CB(skb);
76d5a9e8 468
79acac07 469 memcpy(rates, bf->rates, sizeof(rates));
78c4653a 470
da647626
FF		 471 retries = ts->ts_longretry + 1;
472 for (i = 0; i < ts->ts_rateindex; i++)
473 retries += rates[i].count;
474
1286ec6d 475 rcu_read_lock();
f078f209 476
686b9cb9 477 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
1286ec6d
S		 478 if (!sta) {
479 rcu_read_unlock();
73e19463 480
31e79a59
FF		 481 INIT_LIST_HEAD(&bf_head);
482 while (bf) {
483 bf_next = bf->bf_next;
484
50676b81 485 if (!bf->bf_state.stale || bf_next != NULL)
31e79a59
FF		 486 list_move_tail(&bf->list, &bf_head);
487
156369fa 488 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
31e79a59
FF		 489
490 bf = bf_next;
491 }
1286ec6d 492 return;
f078f209
LR		 493 }
494
1286ec6d 495 an = (struct ath_node *)sta->drv_priv;
1803d02d 496 tid = ath_get_skb_tid(sc, an, skb);
156369fa 497 seq_first = tid->seq_start;
6fe7cc71 498 isba = ts->ts_flags & ATH9K_TX_BA;
1286ec6d 499
b11b160d
FF		 500 /*
501 * The hardware occasionally sends a tx status for the wrong TID.
502 * In this case, the BA status cannot be considered valid and all
503 * subframes need to be retransmitted
6fe7cc71
SE		 504 *
505 * Only BlockAcks have a TID and therefore normal Acks cannot be
506 * checked
b11b160d 507 */
1803d02d 508 if (isba && tid->tidno != ts->tid)
b11b160d
FF		 509 txok = false;
510
e8324357 511 isaggr = bf_isaggr(bf);
d43f3015 512 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
f078f209 513
d43f3015 514 if (isaggr && txok) {
db1a052b
FF		 515 if (ts->ts_flags & ATH9K_TX_BA) {
516 seq_st = ts->ts_seqnum;
517 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
e8324357 518 } else {
d43f3015
S		 519 /*
520 * AR5416 can become deaf/mute when BA
521 * issue happens. Chip needs to be reset.
522 * But AP code may have sychronization issues
523 * when perform internal reset in this routine.
524 * Only enable reset in STA mode for now.
525 */
2660b81a 526 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
d43f3015 527 needreset = 1;
e8324357 528 }
f078f209
LR		 529 }
530
56dc6336 531 __skb_queue_head_init(&bf_pending);
f078f209 532
b572d033 533 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
e8324357 534 while (bf) {
6a0ddaef
FF		 535 u16 seqno = bf->bf_state.seqno;
536
f0b8220c 537 txfail = txpending = sendbar = 0;
e8324357 538 bf_next = bf->bf_next;
f078f209 539
78c4653a
FF		 540 skb = bf->bf_mpdu;
541 tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 542 fi = get_frame_info(skb);
78c4653a 543
897d7fd9
FF		 544 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
545 !tid->active) {
08c96abd
FF		 546 /*
547 * Outside of the current BlockAck window,
548 * maybe part of a previous session
549 */
550 txfail = 1;
551 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
e8324357
S		 552 /* transmit completion, subframe is
553 * acked by block ack */
0934af23 554 acked_cnt++;
e8324357
S		 555 } else if (!isaggr && txok) {
556 /* transmit completion */
0934af23 557 acked_cnt++;
b0477013
FF		 558 } else if (flush) {
559 txpending = 1;
560 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
561 if (txok || !an->sleeping)
562 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
563 retries);
564
565 txpending = 1;
e8324357 566 } else {
b0477013
FF		 567 txfail = 1;
568 txfail_cnt++;
569 bar_index = max_t(int, bar_index,
570 ATH_BA_INDEX(seq_first, seqno));
e8324357 571 }
f078f209 572
fce041be
FF		 573 /*
574 * Make sure the last desc is reclaimed if it
575 * not a holding desc.
576 */
56dc6336 577 INIT_LIST_HEAD(&bf_head);
50676b81 578 if (bf_next != NULL || !bf_last->bf_state.stale)
d43f3015 579 list_move_tail(&bf->list, &bf_head);
f078f209 580
08c96abd 581 if (!txpending) {
e8324357
S		 582 /*
583 * complete the acked-ones/xretried ones; update
584 * block-ack window
585 */
6a0ddaef 586 ath_tx_update_baw(sc, tid, seqno);
f078f209 587
8a92e2ee 588 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
78c4653a 589 memcpy(tx_info->control.rates, rates, sizeof(rates));
3afd21e7 590 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
8a92e2ee 591 rc_update = false;
8a92e2ee
VT		 592 }
593
db1a052b 594 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
156369fa 595 !txfail);
e8324357 596 } else {
86a22acf
FF		 597 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
598 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
599 ieee80211_sta_eosp(sta);
600 }
d43f3015 601 /* retry the un-acked ones */
50676b81 602 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
b0477013
FF		 603 struct ath_buf *tbf;
604
605 tbf = ath_clone_txbuf(sc, bf_last);
606 /*
607 * Update tx baw and complete the
608 * frame with failed status if we
609 * run out of tx buf.
610 */
611 if (!tbf) {
b0477013 612 ath_tx_update_baw(sc, tid, seqno);
b0477013
FF		 613
614 ath_tx_complete_buf(sc, bf, txq,
615 &bf_head, ts, 0);
616 bar_index = max_t(int, bar_index,
617 ATH_BA_INDEX(seq_first, seqno));
618 break;
c41d92dc 619 }
b0477013
FF		 620
621 fi->bf = tbf;
e8324357
S		 622 }
623
624 /*
625 * Put this buffer to the temporary pending
626 * queue to retain ordering
627 */
56dc6336 628 __skb_queue_tail(&bf_pending, skb);
e8324357
S		 629 }
630
631 bf = bf_next;
f078f209 632 }
f078f209 633
4cee7861 634 /* prepend un-acked frames to the beginning of the pending frame queue */
56dc6336 635 if (!skb_queue_empty(&bf_pending)) {
5519541d 636 if (an->sleeping)
042ec453 637 ieee80211_sta_set_buffered(sta, tid->tidno, true);
5519541d 638
bb195ff6 639 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
26a64259 640 if (!an->sleeping) {
9af73cf7 641 ath_tx_queue_tid(txq, tid);
26a64259 642
adfbda62 643 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
26a64259
FF		 644 tid->ac->clear_ps_filter = true;
645 }
4cee7861
FF		 646 }
647
23de5dc9
FF		 648 if (bar_index >= 0) {
649 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
650
651 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
652 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
653
654 ath_txq_unlock(sc, txq);
655 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
656 ath_txq_lock(sc, txq);
657 }
658
1286ec6d
S		 659 rcu_read_unlock();
660
124b979b
RM		 661 if (needreset)
662 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
e8324357 663}
f078f209 664
81b51950
FF		 665static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
666{
667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
668 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
669}
670
671static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
672 struct ath_tx_status *ts, struct ath_buf *bf,
673 struct list_head *bf_head)
674{
0c585dda 675 struct ieee80211_tx_info *info;
81b51950
FF		 676 bool txok, flush;
677
678 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
679 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
680 txq->axq_tx_inprogress = false;
681
682 txq->axq_depth--;
683 if (bf_is_ampdu_not_probing(bf))
684 txq->axq_ampdu_depth--;
685
686 if (!bf_isampdu(bf)) {
0c585dda
FF		 687 if (!flush) {
688 info = IEEE80211_SKB_CB(bf->bf_mpdu);
689 memcpy(info->control.rates, bf->rates,
690 sizeof(info->control.rates));
81b51950 691 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
0c585dda 692 }
81b51950
FF		 693 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
694 } else
695 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
696
73364b0c 697 if (!flush)
81b51950
FF		 698 ath_txq_schedule(sc, txq);
699}
700
1a6e9d0f
RM		 701static bool ath_lookup_legacy(struct ath_buf *bf)
702{
703 struct sk_buff *skb;
704 struct ieee80211_tx_info *tx_info;
705 struct ieee80211_tx_rate *rates;
706 int i;
707
708 skb = bf->bf_mpdu;
709 tx_info = IEEE80211_SKB_CB(skb);
710 rates = tx_info->control.rates;
711
059ee09b
FF		 712 for (i = 0; i < 4; i++) {
713 if (!rates[i].count || rates[i].idx < 0)
714 break;
715
1a6e9d0f
RM		 716 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
717 return true;
718 }
719
720 return false;
721}
722
e8324357
S		 723static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
724 struct ath_atx_tid *tid)
f078f209 725{
528f0c6b
S		 726 struct sk_buff *skb;
727 struct ieee80211_tx_info *tx_info;
a8efee4f 728 struct ieee80211_tx_rate *rates;
d43f3015 729 u32 max_4ms_framelen, frmlen;
c0ac53fa 730 u16 aggr_limit, bt_aggr_limit, legacy = 0;
aa5955c3 731 int q = tid->ac->txq->mac80211_qnum;
e8324357 732 int i;
528f0c6b 733
a22be22a 734 skb = bf->bf_mpdu;
528f0c6b 735 tx_info = IEEE80211_SKB_CB(skb);
0c585dda 736 rates = bf->rates;
528f0c6b 737
e8324357
S		 738 /*
739 * Find the lowest frame length among the rate series that will have a
aa5955c3 740 * 4ms (or TXOP limited) transmit duration.
e8324357
S		 741 */
742 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
e63835b0 743
e8324357 744 for (i = 0; i < 4; i++) {
b0477013 745 int modeidx;
e8324357 746
b0477013
FF		 747 if (!rates[i].count)
748 continue;
545750d3 749
b0477013
FF		 750 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
751 legacy = 1;
752 break;
f078f209 753 }
b0477013
FF		 754
755 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
756 modeidx = MCS_HT40;
757 else
758 modeidx = MCS_HT20;
759
760 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
761 modeidx++;
762
aa5955c3 763 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
b0477013 764 max_4ms_framelen = min(max_4ms_framelen, frmlen);
f078f209 765 }
e63835b0 766
f078f209 767 /*
e8324357
S		 768 * limit aggregate size by the minimum rate if rate selected is
769 * not a probe rate, if rate selected is a probe rate then
770 * avoid aggregation of this packet.
f078f209 771 */
e8324357
S		 772 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
773 return 0;
f078f209 774
c0ac53fa
SM		 775 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
776
777 /*
778 * Override the default aggregation limit for BTCOEX.
779 */
780 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
781 if (bt_aggr_limit)
782 aggr_limit = bt_aggr_limit;
f078f209 783
e8324357 784 /*
25985edc
LDM		 785 * h/w can accept aggregates up to 16 bit lengths (65535).
786 * The IE, however can hold up to 65536, which shows up here
e8324357 787 * as zero. Ignore 65536 since we are constrained by hw.
f078f209 788 */
4ef70841
S		 789 if (tid->an->maxampdu)
790 aggr_limit = min(aggr_limit, tid->an->maxampdu);
f078f209 791
e8324357
S		 792 return aggr_limit;
793}
f078f209 794
e8324357 795/*
d43f3015 796 * Returns the number of delimiters to be added to
e8324357 797 * meet the minimum required mpdudensity.
e8324357
S		 798 */
799static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
7a12dfdb
RM		 800 struct ath_buf *bf, u16 frmlen,
801 bool first_subfrm)
e8324357 802{
7a12dfdb 803#define FIRST_DESC_NDELIMS 60
4ef70841 804 u32 nsymbits, nsymbols;
e8324357 805 u16 minlen;
545750d3 806 u8 flags, rix;
c6663876 807 int width, streams, half_gi, ndelim, mindelim;
2d42efc4 808 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
e8324357
S		 809
810 /* Select standard number of delimiters based on frame length alone */
811 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
f078f209
LR		 812
813 /*
e8324357
S		 814 * If encryption enabled, hardware requires some more padding between
815 * subframes.
816 * TODO - this could be improved to be dependent on the rate.
817 * The hardware can keep up at lower rates, but not higher rates
f078f209 818 */
4f6760b0
RM		 819 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
820 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
e8324357 821 ndelim += ATH_AGGR_ENCRYPTDELIM;
f078f209 822
7a12dfdb
RM		 823 /*
824 * Add delimiter when using RTS/CTS with aggregation
825 * and non enterprise AR9003 card
826 */
3459731a
FF		 827 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
828 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
7a12dfdb
RM		 829 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
830
e8324357
S		 831 /*
832 * Convert desired mpdu density from microeconds to bytes based
833 * on highest rate in rate series (i.e. first rate) to determine
834 * required minimum length for subframe. Take into account
835 * whether high rate is 20 or 40Mhz and half or full GI.
4ef70841 836 *
e8324357
S		 837 * If there is no mpdu density restriction, no further calculation
838 * is needed.
839 */
4ef70841
S		 840
841 if (tid->an->mpdudensity == 0)
e8324357 842 return ndelim;
f078f209 843
79acac07
FF		 844 rix = bf->rates[0].idx;
845 flags = bf->rates[0].flags;
e8324357
S		 846 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
847 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
f078f209 848
e8324357 849 if (half_gi)
4ef70841 850 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
e8324357 851 else
4ef70841 852 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
f078f209 853
e8324357
S		 854 if (nsymbols == 0)
855 nsymbols = 1;
f078f209 856
c6663876
FF		 857 streams = HT_RC_2_STREAMS(rix);
858 nsymbits = bits_per_symbol[rix % 8][width] * streams;
e8324357 859 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
f078f209 860
e8324357 861 if (frmlen < minlen) {
e8324357
S		 862 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
863 ndelim = max(mindelim, ndelim);
f078f209
LR		 864 }
865
e8324357 866 return ndelim;
f078f209
LR		 867}
868
86a22acf
FF		 869static struct ath_buf *
870ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
a7586ee4 871 struct ath_atx_tid *tid, struct sk_buff_head **q)
f078f209 872{
73364b0c 873 struct ieee80211_tx_info *tx_info;
2d42efc4 874 struct ath_frame_info *fi;
56dc6336 875 struct sk_buff *skb;
86a22acf 876 struct ath_buf *bf;
6a0ddaef 877 u16 seqno;
f078f209 878
86a22acf 879 while (1) {
bb195ff6
FF		 880 *q = &tid->retry_q;
881 if (skb_queue_empty(*q))
882 *q = &tid->buf_q;
883
a7586ee4 884 skb = skb_peek(*q);
86a22acf
FF		 885 if (!skb)
886 break;
887
56dc6336
FF		 888 fi = get_frame_info(skb);
889 bf = fi->bf;
44f1d26c 890 if (!fi->bf)
249ee722 891 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
563299d8
FF		 892 else
893 bf->bf_state.stale = false;
56dc6336 894
249ee722 895 if (!bf) {
a7586ee4 896 __skb_unlink(skb, *q);
a4943ccb 897 ath_txq_skb_done(sc, txq, skb);
249ee722 898 ieee80211_free_txskb(sc->hw, skb);
44f1d26c 899 continue;
249ee722 900 }
44f1d26c 901
73364b0c
FF		 902 bf->bf_next = NULL;
903 bf->bf_lastbf = bf;
904
905 tx_info = IEEE80211_SKB_CB(skb);
906 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
907 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
908 bf->bf_state.bf_type = 0;
909 return bf;
910 }
911
399c6489 912 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
44f1d26c 913 seqno = bf->bf_state.seqno;
f078f209 914
d43f3015 915 /* do not step over block-ack window */
86a22acf 916 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
e8324357 917 break;
f078f209 918
f9437543
FF		 919 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
920 struct ath_tx_status ts = {};
921 struct list_head bf_head;
922
923 INIT_LIST_HEAD(&bf_head);
924 list_add(&bf->list, &bf_head);
a7586ee4 925 __skb_unlink(skb, *q);
f9437543
FF		 926 ath_tx_update_baw(sc, tid, seqno);
927 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
928 continue;
929 }
930
86a22acf
FF		 931 return bf;
932 }
933
934 return NULL;
935}
936
2800e82b
FF		 937static bool
938ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
939 struct ath_atx_tid *tid, struct list_head *bf_q,
940 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
941 int *aggr_len)
86a22acf
FF		 942{
943#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
2800e82b 944 struct ath_buf *bf = bf_first, *bf_prev = NULL;
a1cd94d3 945 int nframes = 0, ndelim;
86a22acf 946 u16 aggr_limit = 0, al = 0, bpad = 0,
a1cd94d3 947 al_delta, h_baw = tid->baw_size / 2;
86a22acf
FF		 948 struct ieee80211_tx_info *tx_info;
949 struct ath_frame_info *fi;
950 struct sk_buff *skb;
2800e82b 951 bool closed = false;
86a22acf 952
2800e82b
FF		 953 bf = bf_first;
954 aggr_limit = ath_lookup_rate(sc, bf, tid);
86a22acf 955
2800e82b 956 do {
86a22acf
FF		 957 skb = bf->bf_mpdu;
958 fi = get_frame_info(skb);
959
d43f3015 960 /* do not exceed aggregation limit */
2d42efc4 961 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
a1cd94d3
FF		 962 if (nframes) {
963 if (aggr_limit < al + bpad + al_delta ||
2800e82b 964 ath_lookup_legacy(bf) || nframes >= h_baw)
a1cd94d3 965 break;
f078f209 966
a1cd94d3 967 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
2800e82b
FF		 968 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
969 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
a1cd94d3 970 break;
e8324357 971 }
f078f209 972
d43f3015 973 /* add padding for previous frame to aggregation length */
e8324357 974 al += bpad + al_delta;
f078f209 975
e8324357
S		 976 /*
977 * Get the delimiters needed to meet the MPDU
978 * density for this node.
979 */
7a12dfdb
RM		 980 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
981 !nframes);
e8324357 982 bpad = PADBYTES(al_delta) + (ndelim << 2);
f078f209 983
7a12dfdb 984 nframes++;
e8324357 985 bf->bf_next = NULL;
f078f209 986
d43f3015 987 /* link buffers of this frame to the aggregate */
8fed1408
FF		 988 if (!fi->baw_tracked)
989 ath_tx_addto_baw(sc, tid, bf);
399c6489 990 bf->bf_state.ndelim = ndelim;
56dc6336 991
a7586ee4 992 __skb_unlink(skb, tid_q);
56dc6336 993 list_add_tail(&bf->list, bf_q);
399c6489 994 if (bf_prev)
e8324357 995 bf_prev->bf_next = bf;
399c6489 996
e8324357 997 bf_prev = bf;
fec247c0 998
2800e82b
FF		 999 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1000 if (!bf) {
1001 closed = true;
1002 break;
1003 }
a7586ee4 1004 } while (ath_tid_has_buffered(tid));
f078f209 1005
2800e82b
FF		 1006 bf = bf_first;
1007 bf->bf_lastbf = bf_prev;
1008
1009 if (bf == bf_prev) {
1010 al = get_frame_info(bf->bf_mpdu)->framelen;
1011 bf->bf_state.bf_type = BUF_AMPDU;
1012 } else {
1013 TX_STAT_INC(txq->axq_qnum, a_aggr);
1014 }
1015
269c44bc 1016 *aggr_len = al;
d43f3015 1017
2800e82b 1018 return closed;
e8324357
S		 1019#undef PADBYTES
1020}
f078f209 1021
38dad7ba
FF		 1022/*
1023 * rix - rate index
1024 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1025 * width - 0 for 20 MHz, 1 for 40 MHz
1026 * half_gi - to use 4us v/s 3.6 us for symbol time
1027 */
1028static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1029 int width, int half_gi, bool shortPreamble)
1030{
1031 u32 nbits, nsymbits, duration, nsymbols;
1032 int streams;
1033
1034 /* find number of symbols: PLCP + data */
1035 streams = HT_RC_2_STREAMS(rix);
1036 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1037 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1038 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1039
1040 if (!half_gi)
1041 duration = SYMBOL_TIME(nsymbols);
1042 else
1043 duration = SYMBOL_TIME_HALFGI(nsymbols);
1044
1045 /* addup duration for legacy/ht training and signal fields */
1046 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1047
1048 return duration;
1049}
1050
aa5955c3
FF		 1051static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1052{
1053 int streams = HT_RC_2_STREAMS(mcs);
1054 int symbols, bits;
1055 int bytes = 0;
1056
1057 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1058 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1059 bits -= OFDM_PLCP_BITS;
1060 bytes = bits / 8;
1061 bytes -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1062 if (bytes > 65532)
1063 bytes = 65532;
1064
1065 return bytes;
1066}
1067
1068void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1069{
1070 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1071 int mcs;
1072
1073 /* 4ms is the default (and maximum) duration */
1074 if (!txop || txop > 4096)
1075 txop = 4096;
1076
1077 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1078 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1079 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1080 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1081 for (mcs = 0; mcs < 32; mcs++) {
1082 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1083 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1084 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1085 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1086 }
1087}
1088
493cf04f 1089static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
a3835e9f 1090 struct ath_tx_info *info, int len, bool rts)
38dad7ba
FF		 1091{
1092 struct ath_hw *ah = sc->sc_ah;
38dad7ba
FF		 1093 struct sk_buff *skb;
1094 struct ieee80211_tx_info *tx_info;
1095 struct ieee80211_tx_rate *rates;
1096 const struct ieee80211_rate *rate;
1097 struct ieee80211_hdr *hdr;
80b08a8d 1098 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
a3835e9f 1099 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
493cf04f
FF		 1100 int i;
1101 u8 rix = 0;
38dad7ba
FF		 1102
1103 skb = bf->bf_mpdu;
1104 tx_info = IEEE80211_SKB_CB(skb);
79acac07 1105 rates = bf->rates;
38dad7ba 1106 hdr = (struct ieee80211_hdr *)skb->data;
493cf04f
FF		 1107
1108 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1109 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
80b08a8d 1110 info->rtscts_rate = fi->rtscts_rate;
38dad7ba 1111
79acac07 1112 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
38dad7ba
FF		 1113 bool is_40, is_sgi, is_sp;
1114 int phy;
1115
1116 if (!rates[i].count || (rates[i].idx < 0))
1117 continue;
1118
1119 rix = rates[i].idx;
493cf04f 1120 info->rates[i].Tries = rates[i].count;
38dad7ba 1121
a3835e9f
SM		 1122 /*
1123 * Handle RTS threshold for unaggregated HT frames.
1124 */
1125 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1126 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1127 unlikely(rts_thresh != (u32) -1)) {
1128 if (!rts_thresh || (len > rts_thresh))
1129 rts = true;
1130 }
1131
1132 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
493cf04f
FF		 1133 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1134 info->flags |= ATH9K_TXDESC_RTSENA;
38dad7ba 1135 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
493cf04f
FF		 1136 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1137 info->flags |= ATH9K_TXDESC_CTSENA;
38dad7ba
FF		 1138 }
1139
1140 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
493cf04f 1141 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
38dad7ba 1142 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
493cf04f 1143 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
38dad7ba
FF		 1144
1145 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1146 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1147 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1148
1149 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1150 /* MCS rates */
493cf04f
FF		 1151 info->rates[i].Rate = rix | 0x80;
1152 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1153 ah->txchainmask, info->rates[i].Rate);
1154 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
38dad7ba
FF		 1155 is_40, is_sgi, is_sp);
1156 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
493cf04f 1157 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
38dad7ba
FF		 1158 continue;
1159 }
1160
1161 /* legacy rates */
76591bea 1162 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
38dad7ba
FF		 1163 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1164 !(rate->flags & IEEE80211_RATE_ERP_G))
1165 phy = WLAN_RC_PHY_CCK;
1166 else
1167 phy = WLAN_RC_PHY_OFDM;
1168
493cf04f 1169 info->rates[i].Rate = rate->hw_value;
38dad7ba
FF		 1170 if (rate->hw_value_short) {
1171 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
493cf04f 1172 info->rates[i].Rate |= rate->hw_value_short;
38dad7ba
FF		 1173 } else {
1174 is_sp = false;
1175 }
1176
1177 if (bf->bf_state.bfs_paprd)
493cf04f 1178 info->rates[i].ChSel = ah->txchainmask;
38dad7ba 1179 else
493cf04f
FF		 1180 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1181 ah->txchainmask, info->rates[i].Rate);
38dad7ba 1182
493cf04f 1183 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
38dad7ba
FF		 1184 phy, rate->bitrate * 100, len, rix, is_sp);
1185 }
1186
1187 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1188 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
493cf04f 1189 info->flags &= ~ATH9K_TXDESC_RTSENA;
38dad7ba
FF		 1190
1191 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
493cf04f
FF		 1192 if (info->flags & ATH9K_TXDESC_RTSENA)
1193 info->flags &= ~ATH9K_TXDESC_CTSENA;
1194}
38dad7ba 1195
493cf04f
FF		 1196static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1197{
1198 struct ieee80211_hdr *hdr;
1199 enum ath9k_pkt_type htype;
1200 __le16 fc;
1201
1202 hdr = (struct ieee80211_hdr *)skb->data;
1203 fc = hdr->frame_control;
38dad7ba 1204
493cf04f
FF		 1205 if (ieee80211_is_beacon(fc))
1206 htype = ATH9K_PKT_TYPE_BEACON;
1207 else if (ieee80211_is_probe_resp(fc))
1208 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1209 else if (ieee80211_is_atim(fc))
1210 htype = ATH9K_PKT_TYPE_ATIM;
1211 else if (ieee80211_is_pspoll(fc))
1212 htype = ATH9K_PKT_TYPE_PSPOLL;
1213 else
1214 htype = ATH9K_PKT_TYPE_NORMAL;
1215
1216 return htype;
38dad7ba
FF		 1217}
1218
493cf04f
FF		 1219static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1220 struct ath_txq *txq, int len)
399c6489
FF		 1221{
1222 struct ath_hw *ah = sc->sc_ah;
86a22acf 1223 struct ath_buf *bf_first = NULL;
493cf04f 1224 struct ath_tx_info info;
a3835e9f
SM		 1225 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1226 bool rts = false;
399c6489 1227
493cf04f
FF		 1228 memset(&info, 0, sizeof(info));
1229 info.is_first = true;
1230 info.is_last = true;
1231 info.txpower = MAX_RATE_POWER;
1232 info.qcu = txq->axq_qnum;
1233
399c6489 1234 while (bf) {
493cf04f 1235 struct sk_buff *skb = bf->bf_mpdu;
86a22acf 1236 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
493cf04f 1237 struct ath_frame_info *fi = get_frame_info(skb);
86a22acf 1238 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
493cf04f
FF		 1239
1240 info.type = get_hw_packet_type(skb);
399c6489 1241 if (bf->bf_next)
493cf04f 1242 info.link = bf->bf_next->bf_daddr;
399c6489 1243 else
89f927af 1244 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
493cf04f 1245
86a22acf
FF		 1246 if (!bf_first) {
1247 bf_first = bf;
1248
89f927af
LR		 1249 if (!sc->tx99_state)
1250 info.flags = ATH9K_TXDESC_INTREQ;
86a22acf
FF		 1251 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1252 txq == sc->tx.uapsdq)
1253 info.flags |= ATH9K_TXDESC_CLRDMASK;
1254
1255 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1256 info.flags |= ATH9K_TXDESC_NOACK;
1257 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1258 info.flags |= ATH9K_TXDESC_LDPC;
1259
1260 if (bf->bf_state.bfs_paprd)
1261 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1262 ATH9K_TXDESC_PAPRD_S;
1263
a3835e9f
SM		 1264 /*
1265 * mac80211 doesn't handle RTS threshold for HT because
1266 * the decision has to be taken based on AMPDU length
1267 * and aggregation is done entirely inside ath9k.
1268 * Set the RTS/CTS flag for the first subframe based
1269 * on the threshold.
1270 */
1271 if (aggr && (bf == bf_first) &&
1272 unlikely(rts_thresh != (u32) -1)) {
1273 /*
1274 * "len" is the size of the entire AMPDU.
1275 */
1276 if (!rts_thresh || (len > rts_thresh))
1277 rts = true;
1278 }
bbf807bc
FF		 1279
1280 if (!aggr)
1281 len = fi->framelen;
1282
a3835e9f 1283 ath_buf_set_rate(sc, bf, &info, len, rts);
86a22acf
FF		 1284 }
1285
42cecc34
JL		 1286 info.buf_addr[0] = bf->bf_buf_addr;
1287 info.buf_len[0] = skb->len;
493cf04f
FF		 1288 info.pkt_len = fi->framelen;
1289 info.keyix = fi->keyix;
1290 info.keytype = fi->keytype;
1291
1292 if (aggr) {
399c6489 1293 if (bf == bf_first)
493cf04f 1294 info.aggr = AGGR_BUF_FIRST;
86a22acf 1295 else if (bf == bf_first->bf_lastbf)
493cf04f
FF		 1296 info.aggr = AGGR_BUF_LAST;
1297 else
1298 info.aggr = AGGR_BUF_MIDDLE;
399c6489 1299
493cf04f
FF		 1300 info.ndelim = bf->bf_state.ndelim;
1301 info.aggr_len = len;
399c6489
FF		 1302 }
1303
86a22acf
FF		 1304 if (bf == bf_first->bf_lastbf)
1305 bf_first = NULL;
1306
493cf04f 1307 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
399c6489
FF		 1308 bf = bf->bf_next;
1309 }
1310}
1311
2800e82b
FF		 1312static void
1313ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1314 struct ath_atx_tid *tid, struct list_head *bf_q,
1315 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1316{
1317 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1318 struct sk_buff *skb;
1319 int nframes = 0;
1320
1321 do {
1322 struct ieee80211_tx_info *tx_info;
1323 skb = bf->bf_mpdu;
1324
1325 nframes++;
1326 __skb_unlink(skb, tid_q);
1327 list_add_tail(&bf->list, bf_q);
1328 if (bf_prev)
1329 bf_prev->bf_next = bf;
1330 bf_prev = bf;
1331
1332 if (nframes >= 2)
1333 break;
1334
1335 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1336 if (!bf)
1337 break;
1338
1339 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1340 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1341 break;
1342
1343 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1344 } while (1);
1345}
1346
020f20f6
FF		 1347static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1348 struct ath_atx_tid *tid, bool *stop)
e8324357 1349{
d43f3015 1350 struct ath_buf *bf;
399c6489 1351 struct ieee80211_tx_info *tx_info;
2800e82b 1352 struct sk_buff_head *tid_q;
e8324357 1353 struct list_head bf_q;
2800e82b
FF		 1354 int aggr_len = 0;
1355 bool aggr, last = true;
f078f209 1356
020f20f6
FF		 1357 if (!ath_tid_has_buffered(tid))
1358 return false;
f078f209 1359
020f20f6 1360 INIT_LIST_HEAD(&bf_q);
e8324357 1361
020f20f6
FF		 1362 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1363 if (!bf)
1364 return false;
f078f209 1365
020f20f6
FF		 1366 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1367 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1368 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1369 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1370 *stop = true;
1371 return false;
1372 }
2800e82b 1373
020f20f6
FF		 1374 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1375 if (aggr)
1376 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1377 tid_q, &aggr_len);
1378 else
1379 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
2800e82b 1380
020f20f6
FF		 1381 if (list_empty(&bf_q))
1382 return false;
f078f209 1383
f89d1bc4 1384 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
020f20f6
FF		 1385 tid->ac->clear_ps_filter = false;
1386 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1387 }
f078f209 1388
020f20f6
FF		 1389 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1390 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1391 return true;
e8324357
S		 1392}
1393
231c3a1f
FF		 1394int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1395 u16 tid, u16 *ssn)
e8324357
S		 1396{
1397 struct ath_atx_tid *txtid;
919123d2 1398 struct ath_txq *txq;
e8324357 1399 struct ath_node *an;
313eb87f 1400 u8 density;
e8324357
S		 1401
1402 an = (struct ath_node *)sta->drv_priv;
f83da965 1403 txtid = ATH_AN_2_TID(an, tid);
919123d2
FF		 1404 txq = txtid->ac->txq;
1405
1406 ath_txq_lock(sc, txq);
231c3a1f 1407
313eb87f
SE		 1408 /* update ampdu factor/density, they may have changed. This may happen
1409 * in HT IBSS when a beacon with HT-info is received after the station
1410 * has already been added.
1411 */
dd5ee59b 1412 if (sta->ht_cap.ht_supported) {
313eb87f
SE		 1413 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1414 sta->ht_cap.ampdu_factor);
1415 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1416 an->mpdudensity = density;
1417 }
1418
2800e82b
FF		 1419 /* force sequence number allocation for pending frames */
1420 ath_tx_tid_change_state(sc, txtid);
1421
08c96abd 1422 txtid->active = true;
75401849 1423 txtid->paused = true;
49447f2f 1424 *ssn = txtid->seq_start = txtid->seq_next;
f9437543 1425 txtid->bar_index = -1;
231c3a1f 1426
2ed72229
FF		 1427 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1428 txtid->baw_head = txtid->baw_tail = 0;
1429
919123d2
FF		 1430 ath_txq_unlock_complete(sc, txq);
1431
231c3a1f 1432 return 0;
e8324357 1433}
f078f209 1434
08c96abd 1435void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
e8324357
S		 1436{
1437 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1438 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
066dae93 1439 struct ath_txq *txq = txtid->ac->txq;
f078f209 1440
23de5dc9 1441 ath_txq_lock(sc, txq);
08c96abd 1442 txtid->active = false;
73364b0c 1443 txtid->paused = false;
08c96abd 1444 ath_tx_flush_tid(sc, txtid);
2800e82b 1445 ath_tx_tid_change_state(sc, txtid);
23de5dc9 1446 ath_txq_unlock_complete(sc, txq);
e8324357 1447}
f078f209 1448
042ec453
JB		 1449void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1450 struct ath_node *an)
5519541d
FF		 1451{
1452 struct ath_atx_tid *tid;
1453 struct ath_atx_ac *ac;
1454 struct ath_txq *txq;
042ec453 1455 bool buffered;
5519541d
FF		 1456 int tidno;
1457
1458 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1459 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d
FF		 1460
1461 if (!tid->sched)
1462 continue;
1463
1464 ac = tid->ac;
1465 txq = ac->txq;
1466
23de5dc9 1467 ath_txq_lock(sc, txq);
5519541d 1468
a7586ee4 1469 buffered = ath_tid_has_buffered(tid);
5519541d
FF		 1470
1471 tid->sched = false;
1472 list_del(&tid->list);
1473
1474 if (ac->sched) {
1475 ac->sched = false;
1476 list_del(&ac->list);
1477 }
1478
23de5dc9 1479 ath_txq_unlock(sc, txq);
5519541d 1480
042ec453
JB		 1481 ieee80211_sta_set_buffered(sta, tidno, buffered);
1482 }
5519541d
FF		 1483}
1484
1485void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1486{
1487 struct ath_atx_tid *tid;
1488 struct ath_atx_ac *ac;
1489 struct ath_txq *txq;
1490 int tidno;
1491
1492 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 1493 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
5519541d
FF		 1494
1495 ac = tid->ac;
1496 txq = ac->txq;
1497
23de5dc9 1498 ath_txq_lock(sc, txq);
5519541d
FF		 1499 ac->clear_ps_filter = true;
1500
a7586ee4 1501 if (!tid->paused && ath_tid_has_buffered(tid)) {
5519541d
FF		 1502 ath_tx_queue_tid(txq, tid);
1503 ath_txq_schedule(sc, txq);
1504 }
1505
23de5dc9 1506 ath_txq_unlock_complete(sc, txq);
5519541d
FF		 1507 }
1508}
1509
08c96abd
FF		 1510void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1511 u16 tidno)
e8324357 1512{
08c96abd 1513 struct ath_atx_tid *tid;
e8324357 1514 struct ath_node *an;
08c96abd 1515 struct ath_txq *txq;
e8324357
S		 1516
1517 an = (struct ath_node *)sta->drv_priv;
08c96abd
FF		 1518 tid = ATH_AN_2_TID(an, tidno);
1519 txq = tid->ac->txq;
e8324357 1520
08c96abd
FF		 1521 ath_txq_lock(sc, txq);
1522
1523 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1524 tid->paused = false;
1525
a7586ee4 1526 if (ath_tid_has_buffered(tid)) {
08c96abd
FF		 1527 ath_tx_queue_tid(txq, tid);
1528 ath_txq_schedule(sc, txq);
1529 }
1530
1531 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1532}
1533
86a22acf
FF		 1534void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1535 struct ieee80211_sta *sta,
1536 u16 tids, int nframes,
1537 enum ieee80211_frame_release_type reason,
1538 bool more_data)
1539{
1540 struct ath_softc *sc = hw->priv;
1541 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1542 struct ath_txq *txq = sc->tx.uapsdq;
1543 struct ieee80211_tx_info *info;
1544 struct list_head bf_q;
1545 struct ath_buf *bf_tail = NULL, *bf;
a7586ee4 1546 struct sk_buff_head *tid_q;
86a22acf
FF		 1547 int sent = 0;
1548 int i;
1549
1550 INIT_LIST_HEAD(&bf_q);
1551 for (i = 0; tids && nframes; i++, tids >>= 1) {
1552 struct ath_atx_tid *tid;
1553
1554 if (!(tids & 1))
1555 continue;
1556
1557 tid = ATH_AN_2_TID(an, i);
1558 if (tid->paused)
1559 continue;
1560
1561 ath_txq_lock(sc, tid->ac->txq);
a7586ee4
FF		 1562 while (nframes > 0) {
1563 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
86a22acf
FF		 1564 if (!bf)
1565 break;
1566
a7586ee4 1567 __skb_unlink(bf->bf_mpdu, tid_q);
86a22acf
FF		 1568 list_add_tail(&bf->list, &bf_q);
1569 ath_set_rates(tid->an->vif, tid->an->sta, bf);
20e6e55a
FF		 1570 if (bf_isampdu(bf)) {
1571 ath_tx_addto_baw(sc, tid, bf);
1572 bf->bf_state.bf_type &= ~BUF_AGGR;
1573 }
86a22acf
FF		 1574 if (bf_tail)
1575 bf_tail->bf_next = bf;
1576
1577 bf_tail = bf;
1578 nframes--;
1579 sent++;
1580 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1581
f89d1bc4 1582 if (an->sta && !ath_tid_has_buffered(tid))
86a22acf
FF		 1583 ieee80211_sta_set_buffered(an->sta, i, false);
1584 }
1585 ath_txq_unlock_complete(sc, tid->ac->txq);
1586 }
1587
1588 if (list_empty(&bf_q))
1589 return;
1590
1591 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1592 info->flags |= IEEE80211_TX_STATUS_EOSP;
1593
1594 bf = list_first_entry(&bf_q, struct ath_buf, list);
1595 ath_txq_lock(sc, txq);
1596 ath_tx_fill_desc(sc, bf, txq, 0);
1597 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1598 ath_txq_unlock(sc, txq);
1599}
1600
e8324357
S		 1601/********************/
1602/* Queue Management */
1603/********************/
f078f209 1604
e8324357 1605struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
f078f209 1606{
cbe61d8a 1607 struct ath_hw *ah = sc->sc_ah;
e8324357 1608 struct ath9k_tx_queue_info qi;
066dae93 1609 static const int subtype_txq_to_hwq[] = {
bea843c7
SM		 1610 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1611 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1612 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1613 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
066dae93 1614 };
60f2d1d5 1615 int axq_qnum, i;
f078f209 1616
e8324357 1617 memset(&qi, 0, sizeof(qi));
066dae93 1618 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
e8324357
S		 1619 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1620 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1621 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1622 qi.tqi_physCompBuf = 0;
f078f209
LR		 1623
1624 /*
e8324357
S		 1625 * Enable interrupts only for EOL and DESC conditions.
1626 * We mark tx descriptors to receive a DESC interrupt
1627 * when a tx queue gets deep; otherwise waiting for the
1628 * EOL to reap descriptors. Note that this is done to
1629 * reduce interrupt load and this only defers reaping
1630 * descriptors, never transmitting frames. Aside from
1631 * reducing interrupts this also permits more concurrency.
1632 * The only potential downside is if the tx queue backs
1633 * up in which case the top half of the kernel may backup
1634 * due to a lack of tx descriptors.
1635 *
1636 * The UAPSD queue is an exception, since we take a desc-
1637 * based intr on the EOSP frames.
f078f209 1638 */
afe754d6 1639 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
ce8fdf6e 1640 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
afe754d6
VT		 1641 } else {
1642 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1643 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1644 else
1645 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1646 TXQ_FLAG_TXDESCINT_ENABLE;
1647 }
60f2d1d5
BG		 1648 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1649 if (axq_qnum == -1) {
f078f209 1650 /*
e8324357
S		 1651 * NB: don't print a message, this happens
1652 * normally on parts with too few tx queues
f078f209 1653 */
e8324357 1654 return NULL;
f078f209 1655 }
60f2d1d5
BG		 1656 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1657 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
f078f209 1658
60f2d1d5
BG		 1659 txq->axq_qnum = axq_qnum;
1660 txq->mac80211_qnum = -1;
e8324357 1661 txq->axq_link = NULL;
23de5dc9 1662 __skb_queue_head_init(&txq->complete_q);
e8324357
S		 1663 INIT_LIST_HEAD(&txq->axq_q);
1664 INIT_LIST_HEAD(&txq->axq_acq);
1665 spin_lock_init(&txq->axq_lock);
1666 txq->axq_depth = 0;
4b3ba66a 1667 txq->axq_ampdu_depth = 0;
164ace38 1668 txq->axq_tx_inprogress = false;
60f2d1d5 1669 sc->tx.txqsetup |= 1<<axq_qnum;
e5003249
VT		 1670
1671 txq->txq_headidx = txq->txq_tailidx = 0;
1672 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1673 INIT_LIST_HEAD(&txq->txq_fifo[i]);
e8324357 1674 }
60f2d1d5 1675 return &sc->tx.txq[axq_qnum];
f078f209
LR		 1676}
1677
e8324357
S		 1678int ath_txq_update(struct ath_softc *sc, int qnum,
1679 struct ath9k_tx_queue_info *qinfo)
1680{
cbe61d8a 1681 struct ath_hw *ah = sc->sc_ah;
e8324357
S		 1682 int error = 0;
1683 struct ath9k_tx_queue_info qi;
1684
9680e8a3 1685 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
e8324357
S		 1686
1687 ath9k_hw_get_txq_props(ah, qnum, &qi);
1688 qi.tqi_aifs = qinfo->tqi_aifs;
1689 qi.tqi_cwmin = qinfo->tqi_cwmin;
1690 qi.tqi_cwmax = qinfo->tqi_cwmax;
1691 qi.tqi_burstTime = qinfo->tqi_burstTime;
1692 qi.tqi_readyTime = qinfo->tqi_readyTime;
1693
1694 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
3800276a
JP		 1695 ath_err(ath9k_hw_common(sc->sc_ah),
1696 "Unable to update hardware queue %u!\n", qnum);
e8324357
S		 1697 error = -EIO;
1698 } else {
1699 ath9k_hw_resettxqueue(ah, qnum);
1700 }
1701
1702 return error;
1703}
1704
1705int ath_cabq_update(struct ath_softc *sc)
1706{
1707 struct ath9k_tx_queue_info qi;
9814f6b3 1708 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
e8324357 1709 int qnum = sc->beacon.cabq->axq_qnum;
f078f209 1710
e8324357 1711 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
f078f209 1712
9814f6b3 1713 qi.tqi_readyTime = (cur_conf->beacon_interval *
7f329bbb 1714 ATH_CABQ_READY_TIME) / 100;
e8324357
S		 1715 ath_txq_update(sc, qnum, &qi);
1716
1717 return 0;
f078f209
LR		 1718}
1719
fce041be 1720static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1381559b 1721 struct list_head *list)
f078f209 1722{
e8324357
S		 1723 struct ath_buf *bf, *lastbf;
1724 struct list_head bf_head;
db1a052b
FF		 1725 struct ath_tx_status ts;
1726
1727 memset(&ts, 0, sizeof(ts));
daa5c408 1728 ts.ts_status = ATH9K_TX_FLUSH;
e8324357 1729 INIT_LIST_HEAD(&bf_head);
f078f209 1730
fce041be
FF		 1731 while (!list_empty(list)) {
1732 bf = list_first_entry(list, struct ath_buf, list);
f078f209 1733
50676b81 1734 if (bf->bf_state.stale) {
fce041be 1735 list_del(&bf->list);
f078f209 1736
fce041be
FF		 1737 ath_tx_return_buffer(sc, bf);
1738 continue;
e8324357 1739 }
f078f209 1740
e8324357 1741 lastbf = bf->bf_lastbf;
fce041be 1742 list_cut_position(&bf_head, list, &lastbf->list);
81b51950 1743 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
f078f209 1744 }
fce041be 1745}
f078f209 1746
fce041be
FF		 1747/*
1748 * Drain a given TX queue (could be Beacon or Data)
1749 *
1750 * This assumes output has been stopped and
1751 * we do not need to block ath_tx_tasklet.
1752 */
1381559b 1753void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
fce041be 1754{
23de5dc9
FF		 1755 ath_txq_lock(sc, txq);
1756
e5003249 1757 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
fce041be 1758 int idx = txq->txq_tailidx;
e5003249 1759
fce041be 1760 while (!list_empty(&txq->txq_fifo[idx])) {
1381559b 1761 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
fce041be
FF		 1762
1763 INCR(idx, ATH_TXFIFO_DEPTH);
e5003249 1764 }
fce041be 1765 txq->txq_tailidx = idx;
e5003249 1766 }
e609e2ea 1767
fce041be
FF		 1768 txq->axq_link = NULL;
1769 txq->axq_tx_inprogress = false;
1381559b 1770 ath_drain_txq_list(sc, txq, &txq->axq_q);
fce041be 1771
23de5dc9 1772 ath_txq_unlock_complete(sc, txq);
f078f209
LR		 1773}
1774
1381559b 1775bool ath_drain_all_txq(struct ath_softc *sc)
f078f209 1776{
cbe61d8a 1777 struct ath_hw *ah = sc->sc_ah;
c46917bb 1778 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
043a0405 1779 struct ath_txq *txq;
34d25810
FF		 1780 int i;
1781 u32 npend = 0;
043a0405 1782
781b14a3 1783 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
080e1a25 1784 return true;
043a0405 1785
0d51cccc 1786 ath9k_hw_abort_tx_dma(ah);
043a0405 1787
0d51cccc 1788 /* Check if any queue remains active */
043a0405 1789 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
0d51cccc
FF		 1790 if (!ATH_TXQ_SETUP(sc, i))
1791 continue;
1792
34d25810
FF		 1793 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1794 npend |= BIT(i);
043a0405
S		 1795 }
1796
080e1a25 1797 if (npend)
34d25810 1798 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
043a0405
S		 1799
1800 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
92460412
FF		 1801 if (!ATH_TXQ_SETUP(sc, i))
1802 continue;
1803
1804 /*
1805 * The caller will resume queues with ieee80211_wake_queues.
1806 * Mark the queue as not stopped to prevent ath_tx_complete
1807 * from waking the queue too early.
1808 */
1809 txq = &sc->tx.txq[i];
1810 txq->stopped = false;
1381559b 1811 ath_draintxq(sc, txq);
043a0405 1812 }
080e1a25
FF		 1813
1814 return !npend;
e8324357 1815}
f078f209 1816
043a0405 1817void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
e8324357 1818{
043a0405
S		 1819 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1820 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
e8324357 1821}
f078f209 1822
7755bad9
BG		 1823/* For each axq_acq entry, for each tid, try to schedule packets
1824 * for transmit until ampdu_depth has reached min Q depth.
1825 */
e8324357
S		 1826void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1827{
020f20f6 1828 struct ath_atx_ac *ac, *last_ac;
7755bad9 1829 struct ath_atx_tid *tid, *last_tid;
020f20f6 1830 bool sent = false;
f078f209 1831
124b979b 1832 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags) ||
020f20f6 1833 list_empty(&txq->axq_acq))
e8324357 1834 return;
f078f209 1835
23bc2021
FF		 1836 rcu_read_lock();
1837
7755bad9 1838 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
020f20f6
FF		 1839 while (!list_empty(&txq->axq_acq)) {
1840 bool stop = false;
f078f209 1841
020f20f6 1842 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
7755bad9
BG		 1843 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1844 list_del(&ac->list);
1845 ac->sched = false;
f078f209 1846
7755bad9 1847 while (!list_empty(&ac->tid_q)) {
020f20f6 1848
7755bad9
BG		 1849 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1850 list);
1851 list_del(&tid->list);
1852 tid->sched = false;
f078f209 1853
7755bad9
BG		 1854 if (tid->paused)
1855 continue;
f078f209 1856
020f20f6
FF		 1857 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1858 sent = true;
f078f209 1859
7755bad9
BG		 1860 /*
1861 * add tid to round-robin queue if more frames
1862 * are pending for the tid
1863 */
a7586ee4 1864 if (ath_tid_has_buffered(tid))
7755bad9 1865 ath_tx_queue_tid(txq, tid);
f078f209 1866
020f20f6 1867 if (stop || tid == last_tid)
7755bad9
BG		 1868 break;
1869 }
f078f209 1870
b0477013
FF		 1871 if (!list_empty(&ac->tid_q) && !ac->sched) {
1872 ac->sched = true;
1873 list_add_tail(&ac->list, &txq->axq_acq);
f078f209 1874 }
7755bad9 1875
020f20f6 1876 if (stop)
23bc2021 1877 break;
020f20f6
FF		 1878
1879 if (ac == last_ac) {
1880 if (!sent)
1881 break;
1882
1883 sent = false;
1884 last_ac = list_entry(txq->axq_acq.prev,
1885 struct ath_atx_ac, list);
1886 }
e8324357 1887 }
23bc2021
FF		 1888
1889 rcu_read_unlock();
e8324357 1890}
f078f209 1891
e8324357
S		 1892/***********/
1893/* TX, DMA */
1894/***********/
1895
f078f209 1896/*
e8324357
S		 1897 * Insert a chain of ath_buf (descriptors) on a txq and
1898 * assume the descriptors are already chained together by caller.
f078f209 1899 */
e8324357 1900static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
fce041be 1901 struct list_head *head, bool internal)
f078f209 1902{
cbe61d8a 1903 struct ath_hw *ah = sc->sc_ah;
c46917bb 1904 struct ath_common *common = ath9k_hw_common(ah);
fce041be
FF		 1905 struct ath_buf *bf, *bf_last;
1906 bool puttxbuf = false;
1907 bool edma;
f078f209 1908
e8324357
S		 1909 /*
1910 * Insert the frame on the outbound list and
1911 * pass it on to the hardware.
1912 */
f078f209 1913
e8324357
S		 1914 if (list_empty(head))
1915 return;
f078f209 1916
fce041be 1917 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
e8324357 1918 bf = list_first_entry(head, struct ath_buf, list);
fce041be 1919 bf_last = list_entry(head->prev, struct ath_buf, list);
f078f209 1920
d2182b69
JP		 1921 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1922 txq->axq_qnum, txq->axq_depth);
f078f209 1923
fce041be
FF		 1924 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1925 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
e5003249 1926 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
fce041be 1927 puttxbuf = true;
e8324357 1928 } else {
e5003249
VT		 1929 list_splice_tail_init(head, &txq->axq_q);
1930
fce041be
FF		 1931 if (txq->axq_link) {
1932 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
d2182b69 1933 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
226afe68
JP		 1934 txq->axq_qnum, txq->axq_link,
1935 ito64(bf->bf_daddr), bf->bf_desc);
fce041be
FF		 1936 } else if (!edma)
1937 puttxbuf = true;
1938
1939 txq->axq_link = bf_last->bf_desc;
1940 }
1941
1942 if (puttxbuf) {
1943 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1944 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
d2182b69 1945 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
fce041be
FF		 1946 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1947 }
1948
89f927af 1949 if (!edma || sc->tx99_state) {
8d8d3fdc 1950 TX_STAT_INC(txq->axq_qnum, txstart);
e5003249 1951 ath9k_hw_txstart(ah, txq->axq_qnum);
e8324357 1952 }
fce041be
FF		 1953
1954 if (!internal) {
f56e121d
FF		 1955 while (bf) {
1956 txq->axq_depth++;
1957 if (bf_is_ampdu_not_probing(bf))
1958 txq->axq_ampdu_depth++;
1959
440c1c87
FF		 1960 bf_last = bf->bf_lastbf;
1961 bf = bf_last->bf_next;
1962 bf_last->bf_next = NULL;
f56e121d 1963 }
fce041be 1964 }
e8324357 1965}
f078f209 1966
82b873af 1967static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
44f1d26c 1968 struct ath_atx_tid *tid, struct sk_buff *skb)
e8324357 1969{
f69727fd 1970 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
44f1d26c
FF		 1971 struct ath_frame_info *fi = get_frame_info(skb);
1972 struct list_head bf_head;
f69727fd 1973 struct ath_buf *bf = fi->bf;
44f1d26c
FF		 1974
1975 INIT_LIST_HEAD(&bf_head);
1976 list_add_tail(&bf->list, &bf_head);
399c6489 1977 bf->bf_state.bf_type = 0;
f69727fd
FF		 1978 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
1979 bf->bf_state.bf_type = BUF_AMPDU;
1980 ath_tx_addto_baw(sc, tid, bf);
1981 }
e8324357 1982
8c6e3093 1983 bf->bf_next = NULL;
d43f3015 1984 bf->bf_lastbf = bf;
493cf04f 1985 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
44f1d26c 1986 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
fec247c0 1987 TX_STAT_INC(txq->axq_qnum, queued);
e8324357
S		 1988}
1989
36323f81
TH		 1990static void setup_frame_info(struct ieee80211_hw *hw,
1991 struct ieee80211_sta *sta,
1992 struct sk_buff *skb,
2d42efc4 1993 int framelen)
e8324357
S		 1994{
1995 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2d42efc4 1996 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
6a0ddaef 1997 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
80b08a8d 1998 const struct ieee80211_rate *rate;
2d42efc4 1999 struct ath_frame_info *fi = get_frame_info(skb);
93ae2dd2 2000 struct ath_node *an = NULL;
2d42efc4 2001 enum ath9k_key_type keytype;
80b08a8d
FF		 2002 bool short_preamble = false;
2003
2004 /*
2005 * We check if Short Preamble is needed for the CTS rate by
2006 * checking the BSS's global flag.
2007 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2008 */
2009 if (tx_info->control.vif &&
2010 tx_info->control.vif->bss_conf.use_short_preamble)
2011 short_preamble = true;
e8324357 2012
80b08a8d 2013 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2d42efc4 2014 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
e8324357 2015
93ae2dd2
FF		 2016 if (sta)
2017 an = (struct ath_node *) sta->drv_priv;
2018
2d42efc4
FF		 2019 memset(fi, 0, sizeof(*fi));
2020 if (hw_key)
2021 fi->keyix = hw_key->hw_key_idx;
93ae2dd2
FF		 2022 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2023 fi->keyix = an->ps_key;
2d42efc4
FF		 2024 else
2025 fi->keyix = ATH9K_TXKEYIX_INVALID;
2026 fi->keytype = keytype;
2027 fi->framelen = framelen;
09b029b6
LR		 2028
2029 if (!rate)
2030 return;
80b08a8d
FF		 2031 fi->rtscts_rate = rate->hw_value;
2032 if (short_preamble)
2033 fi->rtscts_rate |= rate->hw_value_short;
e8324357
S		 2034}
2035
ea066d5a
MSS		 2036u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2037{
2038 struct ath_hw *ah = sc->sc_ah;
2039 struct ath9k_channel *curchan = ah->curchan;
365d2ebc 2040
8896934c 2041 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
d77bf3eb 2042 (chainmask == 0x7) && (rate < 0x90))
ea066d5a 2043 return 0x3;
365d2ebc
SM		 2044 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2045 IS_CCK_RATE(rate))
2046 return 0x2;
ea066d5a
MSS		 2047 else
2048 return chainmask;
2049}
2050
44f1d26c
FF		 2051/*
2052 * Assign a descriptor (and sequence number if necessary,
2053 * and map buffer for DMA. Frees skb on error
2054 */
fa05f87a 2055static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
04caf863 2056 struct ath_txq *txq,
fa05f87a 2057 struct ath_atx_tid *tid,
249ee722 2058 struct sk_buff *skb)
f078f209 2059{
82b873af 2060 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2d42efc4 2061 struct ath_frame_info *fi = get_frame_info(skb);
fa05f87a 2062 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
82b873af 2063 struct ath_buf *bf;
fd09c85f 2064 int fragno;
fa05f87a 2065 u16 seqno;
82b873af
FF		 2066
2067 bf = ath_tx_get_buffer(sc);
2068 if (!bf) {
d2182b69 2069 ath_dbg(common, XMIT, "TX buffers are full\n");
249ee722 2070 return NULL;
82b873af 2071 }
e022edbd 2072
528f0c6b 2073 ATH_TXBUF_RESET(bf);
f078f209 2074
fa05f87a 2075 if (tid) {
fd09c85f 2076 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
fa05f87a
FF		 2077 seqno = tid->seq_next;
2078 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
fd09c85f
SM		 2079
2080 if (fragno)
2081 hdr->seq_ctrl |= cpu_to_le16(fragno);
2082
2083 if (!ieee80211_has_morefrags(hdr->frame_control))
2084 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2085
fa05f87a
FF		 2086 bf->bf_state.seqno = seqno;
2087 }
2088
f078f209 2089 bf->bf_mpdu = skb;
f8316df1 2090
c1739eb3
BG		 2091 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2092 skb->len, DMA_TO_DEVICE);
2093 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
f8316df1 2094 bf->bf_mpdu = NULL;
6cf9e995 2095 bf->bf_buf_addr = 0;
3800276a
JP		 2096 ath_err(ath9k_hw_common(sc->sc_ah),
2097 "dma_mapping_error() on TX\n");
82b873af 2098 ath_tx_return_buffer(sc, bf);
249ee722 2099 return NULL;
f8316df1
LR		 2100 }
2101
56dc6336 2102 fi->bf = bf;
04caf863
FF		 2103
2104 return bf;
2105}
2106
59505c02
FF		 2107static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2108 struct ath_tx_control *txctl)
f078f209 2109{
28d16708
FF		 2110 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2111 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
36323f81 2112 struct ieee80211_sta *sta = txctl->sta;
f59a59fe 2113 struct ieee80211_vif *vif = info->control.vif;
f89d1bc4 2114 struct ath_vif *avp;
9ac58615 2115 struct ath_softc *sc = hw->priv;
04caf863 2116 int frmlen = skb->len + FCS_LEN;
59505c02 2117 int padpos, padsize;
f078f209 2118
a9927ba3
BG		 2119 /* NOTE: sta can be NULL according to net/mac80211.h */
2120 if (sta)
2121 txctl->an = (struct ath_node *)sta->drv_priv;
f89d1bc4
FF		 2122 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2123 avp = (void *)vif->drv_priv;
2124 txctl->an = &avp->mcast_node;
2125 }
a9927ba3 2126
04caf863
FF		 2127 if (info->control.hw_key)
2128 frmlen += info->control.hw_key->icv_len;
2129
f078f209 2130 /*
e8324357
S		 2131 * As a temporary workaround, assign seq# here; this will likely need
2132 * to be cleaned up to work better with Beacon transmission and virtual
2133 * BSSes.
f078f209 2134 */
e8324357 2135 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
e8324357
S		 2136 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2137 sc->tx.seq_no += 0x10;
2138 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2139 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
f078f209 2140 }
f078f209 2141
59505c02
FF		 2142 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2143 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2144 !ieee80211_is_data(hdr->frame_control))
2145 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2146
42cecc34 2147 /* Add the padding after the header if this is not already done */
c60c9929 2148 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2149 padsize = padpos & 3;
2150 if (padsize && skb->len > padpos) {
2151 if (skb_headroom(skb) < padsize)
2152 return -ENOMEM;
28d16708 2153
42cecc34
JL		 2154 skb_push(skb, padsize);
2155 memmove(skb->data, skb->data + padsize, padpos);
f078f209 2156 }
f078f209 2157
36323f81 2158 setup_frame_info(hw, sta, skb, frmlen);
59505c02
FF		 2159 return 0;
2160}
2161
2d42efc4 2162
59505c02
FF		 2163/* Upon failure caller should free skb */
2164int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2165 struct ath_tx_control *txctl)
2166{
2167 struct ieee80211_hdr *hdr;
2168 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2169 struct ieee80211_sta *sta = txctl->sta;
2170 struct ieee80211_vif *vif = info->control.vif;
2171 struct ath_softc *sc = hw->priv;
2172 struct ath_txq *txq = txctl->txq;
2173 struct ath_atx_tid *tid = NULL;
2174 struct ath_buf *bf;
59505c02
FF		 2175 int q;
2176 int ret;
2177
2178 ret = ath_tx_prepare(hw, skb, txctl);
2179 if (ret)
2180 return ret;
2181
2182 hdr = (struct ieee80211_hdr *) skb->data;
2d42efc4
FF		 2183 /*
2184 * At this point, the vif, hw_key and sta pointers in the tx control
2185 * info are no longer valid (overwritten by the ath_frame_info data.
2186 */
2187
28d16708 2188 q = skb_get_queue_mapping(skb);
23de5dc9
FF		 2189
2190 ath_txq_lock(sc, txq);
28d16708 2191 if (txq == sc->tx.txq_map[q] &&
7702e788
FF		 2192 ++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2193 !txq->stopped) {
7545daf4 2194 ieee80211_stop_queue(sc->hw, q);
3db1cd5c 2195 txq->stopped = true;
f078f209 2196 }
f078f209 2197
f2c7a793
FF		 2198 if (info->flags & IEEE80211_TX_CTL_PS_RESPONSE) {
2199 ath_txq_unlock(sc, txq);
2200 txq = sc->tx.uapsdq;
2201 ath_txq_lock(sc, txq);
2800e82b
FF		 2202 } else if (txctl->an &&
2203 ieee80211_is_data_present(hdr->frame_control)) {
1803d02d 2204 tid = ath_get_skb_tid(sc, txctl->an, skb);
bdc21457
FF		 2205
2206 WARN_ON(tid->ac->txq != txctl->txq);
bdc21457 2207
2800e82b
FF		 2208 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2209 tid->ac->clear_ps_filter = true;
2210
bdc21457 2211 /*
2800e82b
FF		 2212 * Add this frame to software queue for scheduling later
2213 * for aggregation.
bdc21457 2214 */
2800e82b
FF		 2215 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2216 __skb_queue_tail(&tid->buf_q, skb);
2217 if (!txctl->an->sleeping)
2218 ath_tx_queue_tid(txq, tid);
2219
2220 ath_txq_schedule(sc, txq);
bdc21457
FF		 2221 goto out;
2222 }
2223
f2c7a793 2224 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
bdc21457 2225 if (!bf) {
a4943ccb 2226 ath_txq_skb_done(sc, txq, skb);
bdc21457
FF		 2227 if (txctl->paprd)
2228 dev_kfree_skb_any(skb);
2229 else
2230 ieee80211_free_txskb(sc->hw, skb);
2231 goto out;
2232 }
2233
2234 bf->bf_state.bfs_paprd = txctl->paprd;
2235
2236 if (txctl->paprd)
2237 bf->bf_state.bfs_paprd_timestamp = jiffies;
2238
79acac07 2239 ath_set_rates(vif, sta, bf);
f2c7a793 2240 ath_tx_send_normal(sc, txq, tid, skb);
3ad29529 2241
bdc21457 2242out:
23de5dc9 2243 ath_txq_unlock(sc, txq);
3ad29529 2244
44f1d26c 2245 return 0;
f078f209
LR		 2246}
2247
59505c02
FF		 2248void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2249 struct sk_buff *skb)
2250{
2251 struct ath_softc *sc = hw->priv;
2252 struct ath_tx_control txctl = {
2253 .txq = sc->beacon.cabq
2254 };
2255 struct ath_tx_info info = {};
2256 struct ieee80211_hdr *hdr;
2257 struct ath_buf *bf_tail = NULL;
2258 struct ath_buf *bf;
2259 LIST_HEAD(bf_q);
2260 int duration = 0;
2261 int max_duration;
2262
2263 max_duration =
2264 sc->cur_beacon_conf.beacon_interval * 1000 *
2265 sc->cur_beacon_conf.dtim_period / ATH_BCBUF;
2266
2267 do {
2268 struct ath_frame_info *fi = get_frame_info(skb);
2269
2270 if (ath_tx_prepare(hw, skb, &txctl))
2271 break;
2272
2273 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2274 if (!bf)
2275 break;
2276
2277 bf->bf_lastbf = bf;
2278 ath_set_rates(vif, NULL, bf);
a3835e9f 2279 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
59505c02
FF		 2280 duration += info.rates[0].PktDuration;
2281 if (bf_tail)
2282 bf_tail->bf_next = bf;
2283
2284 list_add_tail(&bf->list, &bf_q);
2285 bf_tail = bf;
2286 skb = NULL;
2287
2288 if (duration > max_duration)
2289 break;
2290
2291 skb = ieee80211_get_buffered_bc(hw, vif);
2292 } while(skb);
2293
2294 if (skb)
2295 ieee80211_free_txskb(hw, skb);
2296
2297 if (list_empty(&bf_q))
2298 return;
2299
2300 bf = list_first_entry(&bf_q, struct ath_buf, list);
2301 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2302
2303 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2304 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2305 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2306 sizeof(*hdr), DMA_TO_DEVICE);
2307 }
2308
2309 ath_txq_lock(sc, txctl.txq);
2310 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2311 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2312 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2313 ath_txq_unlock(sc, txctl.txq);
2314}
2315
e8324357
S		 2316/*****************/
2317/* TX Completion */
2318/*****************/
528f0c6b 2319
e8324357 2320static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
0f9dc298 2321 int tx_flags, struct ath_txq *txq)
528f0c6b 2322{
e8324357 2323 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
c46917bb 2324 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4d91f9f3 2325 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
a4943ccb 2326 int padpos, padsize;
07c15a3f 2327 unsigned long flags;
528f0c6b 2328
d2182b69 2329 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
528f0c6b 2330
51dea9be 2331 if (sc->sc_ah->caldata)
4b9b42bf 2332 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
51dea9be 2333
55797b1a 2334 if (!(tx_flags & ATH_TX_ERROR))
e8324357
S		 2335 /* Frame was ACKed */
2336 tx_info->flags |= IEEE80211_TX_STAT_ACK;
528f0c6b 2337
c60c9929 2338 padpos = ieee80211_hdrlen(hdr->frame_control);
42cecc34
JL		 2339 padsize = padpos & 3;
2340 if (padsize && skb->len>padpos+padsize) {
2341 /*
2342 * Remove MAC header padding before giving the frame back to
2343 * mac80211.
2344 */
2345 memmove(skb->data + padsize, skb->data, padpos);
2346 skb_pull(skb, padsize);
e8324357 2347 }
528f0c6b 2348
07c15a3f 2349 spin_lock_irqsave(&sc->sc_pm_lock, flags);
c8e8868e 2350 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
1b04b930 2351 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
d2182b69 2352 ath_dbg(common, PS,
226afe68 2353 "Going back to sleep after having received TX status (0x%lx)\n",
1b04b930
S		 2354 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2355 PS_WAIT_FOR_CAB |
2356 PS_WAIT_FOR_PSPOLL_DATA |
2357 PS_WAIT_FOR_TX_ACK));
9a23f9ca 2358 }
07c15a3f 2359 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca 2360
f2c7a793 2361 __skb_queue_tail(&txq->complete_q, skb);
a4943ccb 2362 ath_txq_skb_done(sc, txq, skb);
e8324357 2363}
f078f209 2364
e8324357 2365static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
db1a052b 2366 struct ath_txq *txq, struct list_head *bf_q,
156369fa 2367 struct ath_tx_status *ts, int txok)
f078f209 2368{
e8324357 2369 struct sk_buff *skb = bf->bf_mpdu;
3afd21e7 2370 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
e8324357 2371 unsigned long flags;
6b2c4032 2372 int tx_flags = 0;
f078f209 2373
55797b1a 2374 if (!txok)
6b2c4032 2375 tx_flags |= ATH_TX_ERROR;
f078f209 2376
3afd21e7
FF		 2377 if (ts->ts_status & ATH9K_TXERR_FILT)
2378 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2379
c1739eb3 2380 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
6cf9e995 2381 bf->bf_buf_addr = 0;
89f927af
LR		 2382 if (sc->tx99_state)
2383 goto skip_tx_complete;
9f42c2b6
FF		 2384
2385 if (bf->bf_state.bfs_paprd) {
9cf04dcc
MSS		 2386 if (time_after(jiffies,
2387 bf->bf_state.bfs_paprd_timestamp +
2388 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
ca369eb4 2389 dev_kfree_skb_any(skb);
78a18172 2390 else
ca369eb4 2391 complete(&sc->paprd_complete);
9f42c2b6 2392 } else {
55797b1a 2393 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
0f9dc298 2394 ath_tx_complete(sc, skb, tx_flags, txq);
9f42c2b6 2395 }
89f927af 2396skip_tx_complete:
6cf9e995
BG		 2397 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2398 * accidentally reference it later.
2399 */
2400 bf->bf_mpdu = NULL;
e8324357
S		 2401
2402 /*
2403 * Return the list of ath_buf of this mpdu to free queue
2404 */
2405 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2406 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2407 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
f078f209
LR		 2408}
2409
0cdd5c60
FF		 2410static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2411 struct ath_tx_status *ts, int nframes, int nbad,
3afd21e7 2412 int txok)
f078f209 2413{
a22be22a 2414 struct sk_buff *skb = bf->bf_mpdu;
254ad0ff 2415 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
e8324357 2416 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
0cdd5c60 2417 struct ieee80211_hw *hw = sc->hw;
f0c255a0 2418 struct ath_hw *ah = sc->sc_ah;
8a92e2ee 2419 u8 i, tx_rateindex;
f078f209 2420
95e4acb7 2421 if (txok)
db1a052b 2422 tx_info->status.ack_signal = ts->ts_rssi;
95e4acb7 2423
db1a052b 2424 tx_rateindex = ts->ts_rateindex;
8a92e2ee
VT		 2425 WARN_ON(tx_rateindex >= hw->max_rates);
2426
3afd21e7 2427 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
d969847c 2428 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
f078f209 2429
b572d033 2430 BUG_ON(nbad > nframes);
ebd02287 2431 }
185d1589
RM		 2432 tx_info->status.ampdu_len = nframes;
2433 tx_info->status.ampdu_ack_len = nframes - nbad;
ebd02287 2434
db1a052b 2435 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
3afd21e7 2436 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
f0c255a0
FF		 2437 /*
2438 * If an underrun error is seen assume it as an excessive
2439 * retry only if max frame trigger level has been reached
2440 * (2 KB for single stream, and 4 KB for dual stream).
2441 * Adjust the long retry as if the frame was tried
2442 * hw->max_rate_tries times to affect how rate control updates
2443 * PER for the failed rate.
2444 * In case of congestion on the bus penalizing this type of
2445 * underruns should help hardware actually transmit new frames
2446 * successfully by eventually preferring slower rates.
2447 * This itself should also alleviate congestion on the bus.
2448 */
3afd21e7
FF		 2449 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2450 ATH9K_TX_DELIM_UNDERRUN)) &&
2451 ieee80211_is_data(hdr->frame_control) &&
83860c59 2452 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
f0c255a0
FF		 2453 tx_info->status.rates[tx_rateindex].count =
2454 hw->max_rate_tries;
f078f209 2455 }
8a92e2ee 2456
545750d3 2457 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
8a92e2ee 2458 tx_info->status.rates[i].count = 0;
545750d3
FF		 2459 tx_info->status.rates[i].idx = -1;
2460 }
8a92e2ee 2461
78c4653a 2462 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
f078f209
LR		 2463}
2464
e8324357 2465static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
f078f209 2466{
cbe61d8a 2467 struct ath_hw *ah = sc->sc_ah;
c46917bb 2468 struct ath_common *common = ath9k_hw_common(ah);
e8324357 2469 struct ath_buf *bf, *lastbf, *bf_held = NULL;
f078f209 2470 struct list_head bf_head;
e8324357 2471 struct ath_desc *ds;
29bffa96 2472 struct ath_tx_status ts;
e8324357 2473 int status;
f078f209 2474
d2182b69 2475 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
226afe68
JP		 2476 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2477 txq->axq_link);
f078f209 2478
23de5dc9 2479 ath_txq_lock(sc, txq);
f078f209 2480 for (;;) {
124b979b 2481 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2482 break;
2483
f078f209
LR		 2484 if (list_empty(&txq->axq_q)) {
2485 txq->axq_link = NULL;
73364b0c 2486 ath_txq_schedule(sc, txq);
f078f209
LR		 2487 break;
2488 }
f078f209
LR		 2489 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2490
e8324357
S		 2491 /*
2492 * There is a race condition that a BH gets scheduled
2493 * after sw writes TxE and before hw re-load the last
2494 * descriptor to get the newly chained one.
2495 * Software must keep the last DONE descriptor as a
2496 * holding descriptor - software does so by marking
2497 * it with the STALE flag.
2498 */
2499 bf_held = NULL;
50676b81 2500 if (bf->bf_state.stale) {
e8324357 2501 bf_held = bf;
fce041be 2502 if (list_is_last(&bf_held->list, &txq->axq_q))
e8324357 2503 break;
fce041be
FF		 2504
2505 bf = list_entry(bf_held->list.next, struct ath_buf,
2506 list);
f078f209
LR		 2507 }
2508
2509 lastbf = bf->bf_lastbf;
e8324357 2510 ds = lastbf->bf_desc;
f078f209 2511
29bffa96
FF		 2512 memset(&ts, 0, sizeof(ts));
2513 status = ath9k_hw_txprocdesc(ah, ds, &ts);
fce041be 2514 if (status == -EINPROGRESS)
e8324357 2515 break;
fce041be 2516
2dac4fb9 2517 TX_STAT_INC(txq->axq_qnum, txprocdesc);
f078f209 2518
e8324357
S		 2519 /*
2520 * Remove ath_buf's of the same transmit unit from txq,
2521 * however leave the last descriptor back as the holding
2522 * descriptor for hw.
2523 */
50676b81 2524 lastbf->bf_state.stale = true;
e8324357 2525 INIT_LIST_HEAD(&bf_head);
e8324357
S		 2526 if (!list_is_singular(&lastbf->list))
2527 list_cut_position(&bf_head,
2528 &txq->axq_q, lastbf->list.prev);
f078f209 2529
fce041be 2530 if (bf_held) {
0a8cea84 2531 list_del(&bf_held->list);
0a8cea84 2532 ath_tx_return_buffer(sc, bf_held);
e8324357 2533 }
f078f209 2534
fce041be 2535 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
8469cdef 2536 }
23de5dc9 2537 ath_txq_unlock_complete(sc, txq);
8469cdef
S		 2538}
2539
e8324357 2540void ath_tx_tasklet(struct ath_softc *sc)
f078f209 2541{
239c795d
FF		 2542 struct ath_hw *ah = sc->sc_ah;
2543 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
e8324357 2544 int i;
f078f209 2545
e8324357
S		 2546 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2547 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2548 ath_tx_processq(sc, &sc->tx.txq[i]);
f078f209
LR		 2549 }
2550}
2551
e5003249
VT		 2552void ath_tx_edma_tasklet(struct ath_softc *sc)
2553{
fce041be 2554 struct ath_tx_status ts;
e5003249
VT		 2555 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2556 struct ath_hw *ah = sc->sc_ah;
2557 struct ath_txq *txq;
2558 struct ath_buf *bf, *lastbf;
2559 struct list_head bf_head;
99ba6a46 2560 struct list_head *fifo_list;
e5003249 2561 int status;
e5003249
VT		 2562
2563 for (;;) {
124b979b 2564 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags))
236de514
FF		 2565 break;
2566
fce041be 2567 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
e5003249
VT		 2568 if (status == -EINPROGRESS)
2569 break;
2570 if (status == -EIO) {
d2182b69 2571 ath_dbg(common, XMIT, "Error processing tx status\n");
e5003249
VT		 2572 break;
2573 }
2574
4e0ad259
FF		 2575 /* Process beacon completions separately */
2576 if (ts.qid == sc->beacon.beaconq) {
2577 sc->beacon.tx_processed = true;
2578 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
d074e8d5
SW		 2579
2580 ath9k_csa_is_finished(sc);
e5003249 2581 continue;
4e0ad259 2582 }
e5003249 2583
fce041be 2584 txq = &sc->tx.txq[ts.qid];
e5003249 2585
23de5dc9 2586 ath_txq_lock(sc, txq);
fce041be 2587
78ef731c
SM		 2588 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2589
99ba6a46
FF		 2590 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2591 if (list_empty(fifo_list)) {
23de5dc9 2592 ath_txq_unlock(sc, txq);
e5003249
VT		 2593 return;
2594 }
2595
99ba6a46 2596 bf = list_first_entry(fifo_list, struct ath_buf, list);
50676b81 2597 if (bf->bf_state.stale) {
99ba6a46
FF		 2598 list_del(&bf->list);
2599 ath_tx_return_buffer(sc, bf);
2600 bf = list_first_entry(fifo_list, struct ath_buf, list);
2601 }
2602
e5003249
VT		 2603 lastbf = bf->bf_lastbf;
2604
2605 INIT_LIST_HEAD(&bf_head);
99ba6a46
FF		 2606 if (list_is_last(&lastbf->list, fifo_list)) {
2607 list_splice_tail_init(fifo_list, &bf_head);
fce041be 2608 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
e5003249 2609
fce041be
FF		 2610 if (!list_empty(&txq->axq_q)) {
2611 struct list_head bf_q;
60f2d1d5 2612
fce041be
FF		 2613 INIT_LIST_HEAD(&bf_q);
2614 txq->axq_link = NULL;
2615 list_splice_tail_init(&txq->axq_q, &bf_q);
2616 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2617 }
99ba6a46 2618 } else {
50676b81 2619 lastbf->bf_state.stale = true;
99ba6a46
FF		 2620 if (bf != lastbf)
2621 list_cut_position(&bf_head, fifo_list,
2622 lastbf->list.prev);
fce041be 2623 }
86271e46 2624
fce041be 2625 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
23de5dc9 2626 ath_txq_unlock_complete(sc, txq);
e5003249
VT		 2627 }
2628}
2629
e8324357
S		 2630/*****************/
2631/* Init, Cleanup */
2632/*****************/
f078f209 2633
5088c2f1
VT		 2634static int ath_txstatus_setup(struct ath_softc *sc, int size)
2635{
2636 struct ath_descdma *dd = &sc->txsdma;
2637 u8 txs_len = sc->sc_ah->caps.txs_len;
2638
2639 dd->dd_desc_len = size * txs_len;
b81950b1
FF		 2640 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2641 &dd->dd_desc_paddr, GFP_KERNEL);
5088c2f1
VT		 2642 if (!dd->dd_desc)
2643 return -ENOMEM;
2644
2645 return 0;
2646}
2647
2648static int ath_tx_edma_init(struct ath_softc *sc)
2649{
2650 int err;
2651
2652 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2653 if (!err)
2654 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2655 sc->txsdma.dd_desc_paddr,
2656 ATH_TXSTATUS_RING_SIZE);
2657
2658 return err;
2659}
2660
e8324357 2661int ath_tx_init(struct ath_softc *sc, int nbufs)
f078f209 2662{
c46917bb 2663 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8324357 2664 int error = 0;
f078f209 2665
797fe5cb 2666 spin_lock_init(&sc->tx.txbuflock);
f078f209 2667
797fe5cb 2668 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
4adfcded 2669 "tx", nbufs, 1, 1);
797fe5cb 2670 if (error != 0) {
3800276a
JP		 2671 ath_err(common,
2672 "Failed to allocate tx descriptors: %d\n", error);
b81950b1 2673 return error;
797fe5cb 2674 }
f078f209 2675
797fe5cb 2676 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
5088c2f1 2677 "beacon", ATH_BCBUF, 1, 1);
797fe5cb 2678 if (error != 0) {
3800276a
JP		 2679 ath_err(common,
2680 "Failed to allocate beacon descriptors: %d\n", error);
b81950b1 2681 return error;
797fe5cb 2682 }
f078f209 2683
164ace38
SB		 2684 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2685
b81950b1 2686 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
5088c2f1 2687 error = ath_tx_edma_init(sc);
f078f209 2688
e8324357 2689 return error;
f078f209
LR		 2690}
2691
f078f209
LR		 2692void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2693{
c5170163
S		 2694 struct ath_atx_tid *tid;
2695 struct ath_atx_ac *ac;
2696 int tidno, acno;
f078f209 2697
8ee5afbc 2698 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2699 tidno < IEEE80211_NUM_TIDS;
c5170163
S		 2700 tidno++, tid++) {
2701 tid->an = an;
2702 tid->tidno = tidno;
2703 tid->seq_start = tid->seq_next = 0;
2704 tid->baw_size = WME_MAX_BA;
2705 tid->baw_head = tid->baw_tail = 0;
2706 tid->sched = false;
e8324357 2707 tid->paused = false;
08c96abd 2708 tid->active = false;
56dc6336 2709 __skb_queue_head_init(&tid->buf_q);
bb195ff6 2710 __skb_queue_head_init(&tid->retry_q);
c5170163 2711 acno = TID_TO_WME_AC(tidno);
8ee5afbc 2712 tid->ac = &an->ac[acno];
c5170163 2713 }
f078f209 2714
8ee5afbc 2715 for (acno = 0, ac = &an->ac[acno];
bea843c7 2716 acno < IEEE80211_NUM_ACS; acno++, ac++) {
c5170163 2717 ac->sched = false;
026d5b07 2718 ac->clear_ps_filter = true;
066dae93 2719 ac->txq = sc->tx.txq_map[acno];
c5170163 2720 INIT_LIST_HEAD(&ac->tid_q);
f078f209
LR		 2721 }
2722}
2723
b5aa9bf9 2724void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
f078f209 2725{
2b40994c
FF		 2726 struct ath_atx_ac *ac;
2727 struct ath_atx_tid *tid;
f078f209 2728 struct ath_txq *txq;
066dae93 2729 int tidno;
e8324357 2730
2b40994c 2731 for (tidno = 0, tid = &an->tid[tidno];
de7b7604 2732 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
f078f209 2733
2b40994c 2734 ac = tid->ac;
066dae93 2735 txq = ac->txq;
f078f209 2736
23de5dc9 2737 ath_txq_lock(sc, txq);
2b40994c
FF		 2738
2739 if (tid->sched) {
2740 list_del(&tid->list);
2741 tid->sched = false;
2742 }
2743
2744 if (ac->sched) {
2745 list_del(&ac->list);
2746 tid->ac->sched = false;
f078f209 2747 }
2b40994c
FF		 2748
2749 ath_tid_drain(sc, txq, tid);
08c96abd 2750 tid->active = false;
2b40994c 2751
23de5dc9 2752 ath_txq_unlock(sc, txq);
f078f209
LR		 2753 }
2754}
89f927af
LR		 2755
2756int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2757 struct ath_tx_control *txctl)
2758{
2759 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2760 struct ath_frame_info *fi = get_frame_info(skb);
2761 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2762 struct ath_buf *bf;
2763 int padpos, padsize;
2764
2765 padpos = ieee80211_hdrlen(hdr->frame_control);
2766 padsize = padpos & 3;
2767
2768 if (padsize && skb->len > padpos) {
2769 if (skb_headroom(skb) < padsize) {
2770 ath_dbg(common, XMIT,
2771 "tx99 padding failed\n");
2772 return -EINVAL;
2773 }
2774
2775 skb_push(skb, padsize);
2776 memmove(skb->data, skb->data + padsize, padpos);
2777 }
2778
2779 fi->keyix = ATH9K_TXKEYIX_INVALID;
2780 fi->framelen = skb->len + FCS_LEN;
2781 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2782
2783 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2784 if (!bf) {
2785 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2786 return -EINVAL;
2787 }
2788
2789 ath_set_rates(sc->tx99_vif, NULL, bf);
2790
2791 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2792 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2793
2794 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2795
2796 return 0;
2797}
Linux 6.x block layer and io_uring tree(s)