Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 | 61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 62 | struct ath_txq *txq, |
e8324357 S |
63 | struct list_head *bf_q, |
64 | int txok, int sendbar); | |
102e0572 | 65 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
66 | struct list_head *head); |
67 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 VT |
68 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
69 | int txok); | |
70 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, | |
8a92e2ee | 71 | int nbad, int txok, bool update_rc); |
c4288390 | 72 | |
545750d3 FF |
73 | enum { |
74 | MCS_DEFAULT, | |
75 | MCS_HT40, | |
76 | MCS_HT40_SGI, | |
77 | }; | |
78 | ||
79 | static int ath_max_4ms_framelen[3][16] = { | |
80 | [MCS_DEFAULT] = { | |
81 | 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180, | |
82 | 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320, | |
83 | }, | |
84 | [MCS_HT40] = { | |
85 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840, | |
86 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600, | |
87 | }, | |
88 | [MCS_HT40_SGI] = { | |
89 | /* TODO: Only MCS 7 and 15 updated, recalculate the rest */ | |
90 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200, | |
91 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400, | |
92 | } | |
93 | }; | |
94 | ||
95 | ||
e8324357 S |
96 | /*********************/ |
97 | /* Aggregation logic */ | |
98 | /*********************/ | |
f078f209 | 99 | |
e8324357 | 100 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 101 | { |
e8324357 | 102 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 103 | |
e8324357 S |
104 | if (tid->paused) |
105 | return; | |
ff37e337 | 106 | |
e8324357 S |
107 | if (tid->sched) |
108 | return; | |
ff37e337 | 109 | |
e8324357 S |
110 | tid->sched = true; |
111 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 112 | |
e8324357 S |
113 | if (ac->sched) |
114 | return; | |
f078f209 | 115 | |
e8324357 S |
116 | ac->sched = true; |
117 | list_add_tail(&ac->list, &txq->axq_acq); | |
118 | } | |
f078f209 | 119 | |
e8324357 S |
120 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
121 | { | |
122 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 123 | |
e8324357 S |
124 | spin_lock_bh(&txq->axq_lock); |
125 | tid->paused++; | |
126 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
127 | } |
128 | ||
e8324357 | 129 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 130 | { |
e8324357 | 131 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 132 | |
9680e8a3 | 133 | BUG_ON(tid->paused <= 0); |
e8324357 | 134 | spin_lock_bh(&txq->axq_lock); |
f078f209 | 135 | |
e8324357 | 136 | tid->paused--; |
f078f209 | 137 | |
e8324357 S |
138 | if (tid->paused > 0) |
139 | goto unlock; | |
f078f209 | 140 | |
e8324357 S |
141 | if (list_empty(&tid->buf_q)) |
142 | goto unlock; | |
f078f209 | 143 | |
e8324357 S |
144 | ath_tx_queue_tid(txq, tid); |
145 | ath_txq_schedule(sc, txq); | |
146 | unlock: | |
147 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 148 | } |
f078f209 | 149 | |
e8324357 | 150 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 151 | { |
e8324357 S |
152 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
153 | struct ath_buf *bf; | |
154 | struct list_head bf_head; | |
155 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 156 | |
9680e8a3 | 157 | BUG_ON(tid->paused <= 0); |
e8324357 | 158 | spin_lock_bh(&txq->axq_lock); |
e6a9854b | 159 | |
e8324357 | 160 | tid->paused--; |
f078f209 | 161 | |
e8324357 S |
162 | if (tid->paused > 0) { |
163 | spin_unlock_bh(&txq->axq_lock); | |
164 | return; | |
165 | } | |
f078f209 | 166 | |
e8324357 S |
167 | while (!list_empty(&tid->buf_q)) { |
168 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
9680e8a3 | 169 | BUG_ON(bf_isretried(bf)); |
d43f3015 | 170 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 171 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 172 | } |
f078f209 | 173 | |
e8324357 | 174 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 175 | } |
f078f209 | 176 | |
e8324357 S |
177 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
178 | int seqno) | |
528f0c6b | 179 | { |
e8324357 | 180 | int index, cindex; |
f078f209 | 181 | |
e8324357 S |
182 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
183 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 184 | |
e8324357 | 185 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 186 | |
e8324357 S |
187 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
188 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
189 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
190 | } | |
528f0c6b | 191 | } |
f078f209 | 192 | |
e8324357 S |
193 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
194 | struct ath_buf *bf) | |
528f0c6b | 195 | { |
e8324357 | 196 | int index, cindex; |
528f0c6b | 197 | |
e8324357 S |
198 | if (bf_isretried(bf)) |
199 | return; | |
528f0c6b | 200 | |
e8324357 S |
201 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
202 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 203 | |
9680e8a3 | 204 | BUG_ON(tid->tx_buf[cindex] != NULL); |
e8324357 | 205 | tid->tx_buf[cindex] = bf; |
f078f209 | 206 | |
e8324357 S |
207 | if (index >= ((tid->baw_tail - tid->baw_head) & |
208 | (ATH_TID_MAX_BUFS - 1))) { | |
209 | tid->baw_tail = cindex; | |
210 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 211 | } |
f078f209 LR |
212 | } |
213 | ||
214 | /* | |
e8324357 S |
215 | * TODO: For frame(s) that are in the retry state, we will reuse the |
216 | * sequence number(s) without setting the retry bit. The | |
217 | * alternative is to give up on these and BAR the receiver's window | |
218 | * forward. | |
f078f209 | 219 | */ |
e8324357 S |
220 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
221 | struct ath_atx_tid *tid) | |
f078f209 | 222 | |
f078f209 | 223 | { |
e8324357 S |
224 | struct ath_buf *bf; |
225 | struct list_head bf_head; | |
226 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 227 | |
e8324357 S |
228 | for (;;) { |
229 | if (list_empty(&tid->buf_q)) | |
230 | break; | |
f078f209 | 231 | |
d43f3015 S |
232 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
233 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 234 | |
e8324357 S |
235 | if (bf_isretried(bf)) |
236 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 237 | |
e8324357 | 238 | spin_unlock(&txq->axq_lock); |
fec247c0 | 239 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
e8324357 S |
240 | spin_lock(&txq->axq_lock); |
241 | } | |
f078f209 | 242 | |
e8324357 S |
243 | tid->seq_next = tid->seq_start; |
244 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
245 | } |
246 | ||
fec247c0 S |
247 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
248 | struct ath_buf *bf) | |
f078f209 | 249 | { |
e8324357 S |
250 | struct sk_buff *skb; |
251 | struct ieee80211_hdr *hdr; | |
f078f209 | 252 | |
e8324357 S |
253 | bf->bf_state.bf_type |= BUF_RETRY; |
254 | bf->bf_retries++; | |
fec247c0 | 255 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 256 | |
e8324357 S |
257 | skb = bf->bf_mpdu; |
258 | hdr = (struct ieee80211_hdr *)skb->data; | |
259 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
260 | } |
261 | ||
d43f3015 S |
262 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
263 | { | |
264 | struct ath_buf *tbf; | |
265 | ||
266 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
267 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
268 | spin_unlock_bh(&sc->tx.txbuflock); | |
269 | return NULL; | |
270 | } | |
d43f3015 S |
271 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
272 | list_del(&tbf->list); | |
273 | spin_unlock_bh(&sc->tx.txbuflock); | |
274 | ||
275 | ATH_TXBUF_RESET(tbf); | |
276 | ||
827e69bf | 277 | tbf->aphy = bf->aphy; |
d43f3015 S |
278 | tbf->bf_mpdu = bf->bf_mpdu; |
279 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
280 | *(tbf->bf_desc) = *(bf->bf_desc); | |
281 | tbf->bf_state = bf->bf_state; | |
282 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
283 | ||
284 | return tbf; | |
285 | } | |
286 | ||
287 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
288 | struct ath_buf *bf, struct list_head *bf_q, | |
289 | int txok) | |
f078f209 | 290 | { |
e8324357 S |
291 | struct ath_node *an = NULL; |
292 | struct sk_buff *skb; | |
1286ec6d | 293 | struct ieee80211_sta *sta; |
76d5a9e8 | 294 | struct ieee80211_hw *hw; |
1286ec6d | 295 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 296 | struct ieee80211_tx_info *tx_info; |
e8324357 | 297 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 298 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 299 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 300 | struct list_head bf_head, bf_pending; |
0934af23 | 301 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 302 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
303 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
304 | bool rc_update = true; | |
f078f209 | 305 | |
a22be22a | 306 | skb = bf->bf_mpdu; |
1286ec6d S |
307 | hdr = (struct ieee80211_hdr *)skb->data; |
308 | ||
76d5a9e8 | 309 | tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 310 | hw = bf->aphy->hw; |
76d5a9e8 | 311 | |
1286ec6d | 312 | rcu_read_lock(); |
f078f209 | 313 | |
5ed176e1 | 314 | /* XXX: use ieee80211_find_sta! */ |
76d5a9e8 | 315 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr1); |
1286ec6d S |
316 | if (!sta) { |
317 | rcu_read_unlock(); | |
318 | return; | |
f078f209 LR |
319 | } |
320 | ||
1286ec6d S |
321 | an = (struct ath_node *)sta->drv_priv; |
322 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
323 | ||
e8324357 | 324 | isaggr = bf_isaggr(bf); |
d43f3015 | 325 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 326 | |
d43f3015 S |
327 | if (isaggr && txok) { |
328 | if (ATH_DS_TX_BA(ds)) { | |
329 | seq_st = ATH_DS_BA_SEQ(ds); | |
330 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
331 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 332 | } else { |
d43f3015 S |
333 | /* |
334 | * AR5416 can become deaf/mute when BA | |
335 | * issue happens. Chip needs to be reset. | |
336 | * But AP code may have sychronization issues | |
337 | * when perform internal reset in this routine. | |
338 | * Only enable reset in STA mode for now. | |
339 | */ | |
2660b81a | 340 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 341 | needreset = 1; |
e8324357 | 342 | } |
f078f209 LR |
343 | } |
344 | ||
e8324357 S |
345 | INIT_LIST_HEAD(&bf_pending); |
346 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 347 | |
0934af23 | 348 | nbad = ath_tx_num_badfrms(sc, bf, txok); |
e8324357 S |
349 | while (bf) { |
350 | txfail = txpending = 0; | |
351 | bf_next = bf->bf_next; | |
f078f209 | 352 | |
e8324357 S |
353 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
354 | /* transmit completion, subframe is | |
355 | * acked by block ack */ | |
0934af23 | 356 | acked_cnt++; |
e8324357 S |
357 | } else if (!isaggr && txok) { |
358 | /* transmit completion */ | |
0934af23 | 359 | acked_cnt++; |
e8324357 | 360 | } else { |
e8324357 S |
361 | if (!(tid->state & AGGR_CLEANUP) && |
362 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
363 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
fec247c0 | 364 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
365 | txpending = 1; |
366 | } else { | |
367 | bf->bf_state.bf_type |= BUF_XRETRY; | |
368 | txfail = 1; | |
369 | sendbar = 1; | |
0934af23 | 370 | txfail_cnt++; |
e8324357 S |
371 | } |
372 | } else { | |
373 | /* | |
374 | * cleanup in progress, just fail | |
375 | * the un-acked sub-frames | |
376 | */ | |
377 | txfail = 1; | |
378 | } | |
379 | } | |
f078f209 | 380 | |
e8324357 | 381 | if (bf_next == NULL) { |
cbfe89c6 VT |
382 | /* |
383 | * Make sure the last desc is reclaimed if it | |
384 | * not a holding desc. | |
385 | */ | |
386 | if (!bf_last->bf_stale) | |
387 | list_move_tail(&bf->list, &bf_head); | |
388 | else | |
389 | INIT_LIST_HEAD(&bf_head); | |
e8324357 | 390 | } else { |
9680e8a3 | 391 | BUG_ON(list_empty(bf_q)); |
d43f3015 | 392 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 393 | } |
f078f209 | 394 | |
e8324357 S |
395 | if (!txpending) { |
396 | /* | |
397 | * complete the acked-ones/xretried ones; update | |
398 | * block-ack window | |
399 | */ | |
400 | spin_lock_bh(&txq->axq_lock); | |
401 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
402 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 403 | |
8a92e2ee VT |
404 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
405 | ath_tx_rc_status(bf, ds, nbad, txok, true); | |
406 | rc_update = false; | |
407 | } else { | |
408 | ath_tx_rc_status(bf, ds, nbad, txok, false); | |
409 | } | |
410 | ||
fec247c0 | 411 | ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar); |
e8324357 | 412 | } else { |
d43f3015 | 413 | /* retry the un-acked ones */ |
a119cc49 | 414 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 415 | struct ath_buf *tbf; |
f078f209 | 416 | |
d43f3015 | 417 | tbf = ath_clone_txbuf(sc, bf_last); |
c41d92dc VT |
418 | /* |
419 | * Update tx baw and complete the frame with | |
420 | * failed status if we run out of tx buf | |
421 | */ | |
422 | if (!tbf) { | |
423 | spin_lock_bh(&txq->axq_lock); | |
424 | ath_tx_update_baw(sc, tid, | |
425 | bf->bf_seqno); | |
426 | spin_unlock_bh(&txq->axq_lock); | |
427 | ||
428 | bf->bf_state.bf_type |= BUF_XRETRY; | |
429 | ath_tx_rc_status(bf, ds, nbad, | |
430 | 0, false); | |
fec247c0 S |
431 | ath_tx_complete_buf(sc, bf, txq, |
432 | &bf_head, 0, 0); | |
8a46097a | 433 | break; |
c41d92dc VT |
434 | } |
435 | ||
d43f3015 | 436 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); |
e8324357 S |
437 | list_add_tail(&tbf->list, &bf_head); |
438 | } else { | |
439 | /* | |
440 | * Clear descriptor status words for | |
441 | * software retry | |
442 | */ | |
d43f3015 | 443 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
444 | } |
445 | ||
446 | /* | |
447 | * Put this buffer to the temporary pending | |
448 | * queue to retain ordering | |
449 | */ | |
450 | list_splice_tail_init(&bf_head, &bf_pending); | |
451 | } | |
452 | ||
453 | bf = bf_next; | |
f078f209 | 454 | } |
f078f209 | 455 | |
e8324357 | 456 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
457 | if (tid->baw_head == tid->baw_tail) { |
458 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 459 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 460 | |
e8324357 S |
461 | /* send buffered frames as singles */ |
462 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 463 | } |
1286ec6d | 464 | rcu_read_unlock(); |
e8324357 S |
465 | return; |
466 | } | |
f078f209 | 467 | |
d43f3015 | 468 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
469 | if (!list_empty(&bf_pending)) { |
470 | spin_lock_bh(&txq->axq_lock); | |
471 | list_splice(&bf_pending, &tid->buf_q); | |
472 | ath_tx_queue_tid(txq, tid); | |
473 | spin_unlock_bh(&txq->axq_lock); | |
474 | } | |
102e0572 | 475 | |
1286ec6d S |
476 | rcu_read_unlock(); |
477 | ||
e8324357 S |
478 | if (needreset) |
479 | ath_reset(sc, false); | |
e8324357 | 480 | } |
f078f209 | 481 | |
e8324357 S |
482 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
483 | struct ath_atx_tid *tid) | |
f078f209 | 484 | { |
528f0c6b S |
485 | struct sk_buff *skb; |
486 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 487 | struct ieee80211_tx_rate *rates; |
d43f3015 | 488 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 489 | u16 aggr_limit, legacy = 0; |
e8324357 | 490 | int i; |
528f0c6b | 491 | |
a22be22a | 492 | skb = bf->bf_mpdu; |
528f0c6b | 493 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 494 | rates = tx_info->control.rates; |
528f0c6b | 495 | |
e8324357 S |
496 | /* |
497 | * Find the lowest frame length among the rate series that will have a | |
498 | * 4ms transmit duration. | |
499 | * TODO - TXOP limit needs to be considered. | |
500 | */ | |
501 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 502 | |
e8324357 S |
503 | for (i = 0; i < 4; i++) { |
504 | if (rates[i].count) { | |
545750d3 FF |
505 | int modeidx; |
506 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { | |
e8324357 S |
507 | legacy = 1; |
508 | break; | |
509 | } | |
510 | ||
545750d3 FF |
511 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
512 | modeidx = MCS_HT40_SGI; | |
513 | else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
514 | modeidx = MCS_HT40; | |
515 | else | |
516 | modeidx = MCS_DEFAULT; | |
517 | ||
518 | frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; | |
d43f3015 | 519 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 LR |
520 | } |
521 | } | |
e63835b0 | 522 | |
f078f209 | 523 | /* |
e8324357 S |
524 | * limit aggregate size by the minimum rate if rate selected is |
525 | * not a probe rate, if rate selected is a probe rate then | |
526 | * avoid aggregation of this packet. | |
f078f209 | 527 | */ |
e8324357 S |
528 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
529 | return 0; | |
f078f209 | 530 | |
1773912b VT |
531 | if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) |
532 | aggr_limit = min((max_4ms_framelen * 3) / 8, | |
533 | (u32)ATH_AMPDU_LIMIT_MAX); | |
534 | else | |
535 | aggr_limit = min(max_4ms_framelen, | |
536 | (u32)ATH_AMPDU_LIMIT_MAX); | |
f078f209 | 537 | |
e8324357 S |
538 | /* |
539 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
540 | * The IE, however can hold upto 65536, which shows up here | |
541 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 542 | */ |
4ef70841 S |
543 | if (tid->an->maxampdu) |
544 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 545 | |
e8324357 S |
546 | return aggr_limit; |
547 | } | |
f078f209 | 548 | |
e8324357 | 549 | /* |
d43f3015 | 550 | * Returns the number of delimiters to be added to |
e8324357 | 551 | * meet the minimum required mpdudensity. |
e8324357 S |
552 | */ |
553 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
554 | struct ath_buf *bf, u16 frmlen) | |
555 | { | |
e8324357 S |
556 | struct sk_buff *skb = bf->bf_mpdu; |
557 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 558 | u32 nsymbits, nsymbols; |
e8324357 | 559 | u16 minlen; |
545750d3 | 560 | u8 flags, rix; |
e8324357 S |
561 | int width, half_gi, ndelim, mindelim; |
562 | ||
563 | /* Select standard number of delimiters based on frame length alone */ | |
564 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
565 | |
566 | /* | |
e8324357 S |
567 | * If encryption enabled, hardware requires some more padding between |
568 | * subframes. | |
569 | * TODO - this could be improved to be dependent on the rate. | |
570 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 571 | */ |
e8324357 S |
572 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
573 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 574 | |
e8324357 S |
575 | /* |
576 | * Convert desired mpdu density from microeconds to bytes based | |
577 | * on highest rate in rate series (i.e. first rate) to determine | |
578 | * required minimum length for subframe. Take into account | |
579 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 580 | * |
e8324357 S |
581 | * If there is no mpdu density restriction, no further calculation |
582 | * is needed. | |
583 | */ | |
4ef70841 S |
584 | |
585 | if (tid->an->mpdudensity == 0) | |
e8324357 | 586 | return ndelim; |
f078f209 | 587 | |
e8324357 S |
588 | rix = tx_info->control.rates[0].idx; |
589 | flags = tx_info->control.rates[0].flags; | |
e8324357 S |
590 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
591 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 592 | |
e8324357 | 593 | if (half_gi) |
4ef70841 | 594 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 595 | else |
4ef70841 | 596 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 597 | |
e8324357 S |
598 | if (nsymbols == 0) |
599 | nsymbols = 1; | |
f078f209 | 600 | |
545750d3 | 601 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 | 602 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 603 | |
e8324357 | 604 | if (frmlen < minlen) { |
e8324357 S |
605 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
606 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
607 | } |
608 | ||
e8324357 | 609 | return ndelim; |
f078f209 LR |
610 | } |
611 | ||
e8324357 | 612 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 613 | struct ath_txq *txq, |
d43f3015 S |
614 | struct ath_atx_tid *tid, |
615 | struct list_head *bf_q) | |
f078f209 | 616 | { |
e8324357 | 617 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
618 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
619 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
620 | u16 aggr_limit = 0, al = 0, bpad = 0, |
621 | al_delta, h_baw = tid->baw_size / 2; | |
622 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 623 | |
e8324357 | 624 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 625 | |
e8324357 S |
626 | do { |
627 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 628 | |
d43f3015 | 629 | /* do not step over block-ack window */ |
e8324357 S |
630 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
631 | status = ATH_AGGR_BAW_CLOSED; | |
632 | break; | |
633 | } | |
f078f209 | 634 | |
e8324357 S |
635 | if (!rl) { |
636 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
637 | rl = 1; | |
638 | } | |
f078f209 | 639 | |
d43f3015 | 640 | /* do not exceed aggregation limit */ |
e8324357 | 641 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 642 | |
d43f3015 S |
643 | if (nframes && |
644 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
645 | status = ATH_AGGR_LIMITED; |
646 | break; | |
647 | } | |
f078f209 | 648 | |
d43f3015 S |
649 | /* do not exceed subframe limit */ |
650 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
651 | status = ATH_AGGR_LIMITED; |
652 | break; | |
653 | } | |
d43f3015 | 654 | nframes++; |
f078f209 | 655 | |
d43f3015 | 656 | /* add padding for previous frame to aggregation length */ |
e8324357 | 657 | al += bpad + al_delta; |
f078f209 | 658 | |
e8324357 S |
659 | /* |
660 | * Get the delimiters needed to meet the MPDU | |
661 | * density for this node. | |
662 | */ | |
663 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 664 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 665 | |
e8324357 | 666 | bf->bf_next = NULL; |
d43f3015 | 667 | bf->bf_desc->ds_link = 0; |
f078f209 | 668 | |
d43f3015 | 669 | /* link buffers of this frame to the aggregate */ |
e8324357 | 670 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
671 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
672 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
673 | if (bf_prev) { |
674 | bf_prev->bf_next = bf; | |
d43f3015 | 675 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
676 | } |
677 | bf_prev = bf; | |
fec247c0 | 678 | |
e8324357 | 679 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 680 | |
e8324357 S |
681 | bf_first->bf_al = al; |
682 | bf_first->bf_nframes = nframes; | |
d43f3015 | 683 | |
e8324357 S |
684 | return status; |
685 | #undef PADBYTES | |
686 | } | |
f078f209 | 687 | |
e8324357 S |
688 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
689 | struct ath_atx_tid *tid) | |
690 | { | |
d43f3015 | 691 | struct ath_buf *bf; |
e8324357 S |
692 | enum ATH_AGGR_STATUS status; |
693 | struct list_head bf_q; | |
f078f209 | 694 | |
e8324357 S |
695 | do { |
696 | if (list_empty(&tid->buf_q)) | |
697 | return; | |
f078f209 | 698 | |
e8324357 S |
699 | INIT_LIST_HEAD(&bf_q); |
700 | ||
fec247c0 | 701 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 702 | |
f078f209 | 703 | /* |
d43f3015 S |
704 | * no frames picked up to be aggregated; |
705 | * block-ack window is not open. | |
f078f209 | 706 | */ |
e8324357 S |
707 | if (list_empty(&bf_q)) |
708 | break; | |
f078f209 | 709 | |
e8324357 | 710 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 711 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 712 | |
d43f3015 | 713 | /* if only one frame, send as non-aggregate */ |
e8324357 | 714 | if (bf->bf_nframes == 1) { |
e8324357 | 715 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 716 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
717 | ath_buf_set_rate(sc, bf); |
718 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
719 | continue; | |
720 | } | |
f078f209 | 721 | |
d43f3015 | 722 | /* setup first desc of aggregate */ |
e8324357 S |
723 | bf->bf_state.bf_type |= BUF_AGGR; |
724 | ath_buf_set_rate(sc, bf); | |
725 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 726 | |
d43f3015 S |
727 | /* anchor last desc of aggregate */ |
728 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 729 | |
e8324357 | 730 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 731 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 732 | |
e8324357 S |
733 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
734 | status != ATH_AGGR_BAW_CLOSED); | |
735 | } | |
736 | ||
f83da965 S |
737 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
738 | u16 tid, u16 *ssn) | |
e8324357 S |
739 | { |
740 | struct ath_atx_tid *txtid; | |
741 | struct ath_node *an; | |
742 | ||
743 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
744 | txtid = ATH_AN_2_TID(an, tid); |
745 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
746 | ath_tx_pause_tid(sc, txtid); | |
747 | *ssn = txtid->seq_start; | |
e8324357 | 748 | } |
f078f209 | 749 | |
f83da965 | 750 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
751 | { |
752 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
753 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
754 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
755 | struct ath_buf *bf; | |
756 | struct list_head bf_head; | |
757 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 758 | |
e8324357 | 759 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 760 | return; |
f078f209 | 761 | |
e8324357 | 762 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 763 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 764 | return; |
e8324357 | 765 | } |
f078f209 | 766 | |
e8324357 S |
767 | ath_tx_pause_tid(sc, txtid); |
768 | ||
769 | /* drop all software retried frames and mark this TID */ | |
770 | spin_lock_bh(&txq->axq_lock); | |
771 | while (!list_empty(&txtid->buf_q)) { | |
772 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
773 | if (!bf_isretried(bf)) { | |
774 | /* | |
775 | * NB: it's based on the assumption that | |
776 | * software retried frame will always stay | |
777 | * at the head of software queue. | |
778 | */ | |
779 | break; | |
780 | } | |
d43f3015 | 781 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 782 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
fec247c0 | 783 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 | 784 | } |
d43f3015 | 785 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 786 | |
e8324357 | 787 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
788 | txtid->state |= AGGR_CLEANUP; |
789 | } else { | |
790 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 791 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 792 | } |
e8324357 | 793 | } |
f078f209 | 794 | |
e8324357 S |
795 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
796 | { | |
797 | struct ath_atx_tid *txtid; | |
798 | struct ath_node *an; | |
799 | ||
800 | an = (struct ath_node *)sta->drv_priv; | |
801 | ||
802 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
803 | txtid = ATH_AN_2_TID(an, tid); | |
804 | txtid->baw_size = | |
805 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
806 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
807 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
808 | ath_tx_resume_tid(sc, txtid); | |
809 | } | |
f078f209 LR |
810 | } |
811 | ||
e8324357 | 812 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 813 | { |
e8324357 | 814 | struct ath_atx_tid *txtid; |
c4288390 | 815 | |
e8324357 S |
816 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
817 | return false; | |
c4288390 | 818 | |
e8324357 S |
819 | txtid = ATH_AN_2_TID(an, tidno); |
820 | ||
c3d8f02e | 821 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 822 | return true; |
e8324357 | 823 | return false; |
c4288390 S |
824 | } |
825 | ||
e8324357 S |
826 | /********************/ |
827 | /* Queue Management */ | |
828 | /********************/ | |
f078f209 | 829 | |
e8324357 S |
830 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
831 | struct ath_txq *txq) | |
f078f209 | 832 | { |
e8324357 S |
833 | struct ath_atx_ac *ac, *ac_tmp; |
834 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 835 | |
e8324357 S |
836 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
837 | list_del(&ac->list); | |
838 | ac->sched = false; | |
839 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
840 | list_del(&tid->list); | |
841 | tid->sched = false; | |
842 | ath_tid_drain(sc, txq, tid); | |
843 | } | |
f078f209 LR |
844 | } |
845 | } | |
846 | ||
e8324357 | 847 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 848 | { |
cbe61d8a | 849 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 850 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 S |
851 | struct ath9k_tx_queue_info qi; |
852 | int qnum; | |
f078f209 | 853 | |
e8324357 S |
854 | memset(&qi, 0, sizeof(qi)); |
855 | qi.tqi_subtype = subtype; | |
856 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
857 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
858 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
859 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
860 | |
861 | /* | |
e8324357 S |
862 | * Enable interrupts only for EOL and DESC conditions. |
863 | * We mark tx descriptors to receive a DESC interrupt | |
864 | * when a tx queue gets deep; otherwise waiting for the | |
865 | * EOL to reap descriptors. Note that this is done to | |
866 | * reduce interrupt load and this only defers reaping | |
867 | * descriptors, never transmitting frames. Aside from | |
868 | * reducing interrupts this also permits more concurrency. | |
869 | * The only potential downside is if the tx queue backs | |
870 | * up in which case the top half of the kernel may backup | |
871 | * due to a lack of tx descriptors. | |
872 | * | |
873 | * The UAPSD queue is an exception, since we take a desc- | |
874 | * based intr on the EOSP frames. | |
f078f209 | 875 | */ |
e8324357 S |
876 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
877 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
878 | else | |
879 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
880 | TXQ_FLAG_TXDESCINT_ENABLE; | |
881 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
882 | if (qnum == -1) { | |
f078f209 | 883 | /* |
e8324357 S |
884 | * NB: don't print a message, this happens |
885 | * normally on parts with too few tx queues | |
f078f209 | 886 | */ |
e8324357 | 887 | return NULL; |
f078f209 | 888 | } |
e8324357 | 889 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
c46917bb LR |
890 | ath_print(common, ATH_DBG_FATAL, |
891 | "qnum %u out of range, max %u!\n", | |
892 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
e8324357 S |
893 | ath9k_hw_releasetxqueue(ah, qnum); |
894 | return NULL; | |
895 | } | |
896 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
897 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 898 | |
e8324357 S |
899 | txq->axq_qnum = qnum; |
900 | txq->axq_link = NULL; | |
901 | INIT_LIST_HEAD(&txq->axq_q); | |
902 | INIT_LIST_HEAD(&txq->axq_acq); | |
903 | spin_lock_init(&txq->axq_lock); | |
904 | txq->axq_depth = 0; | |
164ace38 | 905 | txq->axq_tx_inprogress = false; |
e8324357 S |
906 | sc->tx.txqsetup |= 1<<qnum; |
907 | } | |
908 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
909 | } |
910 | ||
1773912b | 911 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 912 | { |
e8324357 | 913 | int qnum; |
f078f209 | 914 | |
e8324357 S |
915 | switch (qtype) { |
916 | case ATH9K_TX_QUEUE_DATA: | |
917 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
c46917bb LR |
918 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
919 | "HAL AC %u out of range, max %zu!\n", | |
920 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
e8324357 S |
921 | return -1; |
922 | } | |
923 | qnum = sc->tx.hwq_map[haltype]; | |
924 | break; | |
925 | case ATH9K_TX_QUEUE_BEACON: | |
926 | qnum = sc->beacon.beaconq; | |
927 | break; | |
928 | case ATH9K_TX_QUEUE_CAB: | |
929 | qnum = sc->beacon.cabq->axq_qnum; | |
930 | break; | |
931 | default: | |
932 | qnum = -1; | |
933 | } | |
934 | return qnum; | |
935 | } | |
f078f209 | 936 | |
e8324357 S |
937 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
938 | { | |
939 | struct ath_txq *txq = NULL; | |
f52de03b | 940 | u16 skb_queue = skb_get_queue_mapping(skb); |
e8324357 | 941 | int qnum; |
f078f209 | 942 | |
f52de03b | 943 | qnum = ath_get_hal_qnum(skb_queue, sc); |
e8324357 | 944 | txq = &sc->tx.txq[qnum]; |
f078f209 | 945 | |
e8324357 S |
946 | spin_lock_bh(&txq->axq_lock); |
947 | ||
948 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c46917bb LR |
949 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT, |
950 | "TX queue: %d is full, depth: %d\n", | |
951 | qnum, txq->axq_depth); | |
f52de03b | 952 | ath_mac80211_stop_queue(sc, skb_queue); |
e8324357 S |
953 | txq->stopped = 1; |
954 | spin_unlock_bh(&txq->axq_lock); | |
955 | return NULL; | |
f078f209 LR |
956 | } |
957 | ||
e8324357 S |
958 | spin_unlock_bh(&txq->axq_lock); |
959 | ||
960 | return txq; | |
961 | } | |
962 | ||
963 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
964 | struct ath9k_tx_queue_info *qinfo) | |
965 | { | |
cbe61d8a | 966 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
967 | int error = 0; |
968 | struct ath9k_tx_queue_info qi; | |
969 | ||
970 | if (qnum == sc->beacon.beaconq) { | |
971 | /* | |
972 | * XXX: for beacon queue, we just save the parameter. | |
973 | * It will be picked up by ath_beaconq_config when | |
974 | * it's necessary. | |
975 | */ | |
976 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 977 | return 0; |
e8324357 | 978 | } |
f078f209 | 979 | |
9680e8a3 | 980 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
981 | |
982 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
983 | qi.tqi_aifs = qinfo->tqi_aifs; | |
984 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
985 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
986 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
987 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
988 | ||
989 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
c46917bb LR |
990 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
991 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
992 | error = -EIO; |
993 | } else { | |
994 | ath9k_hw_resettxqueue(ah, qnum); | |
995 | } | |
996 | ||
997 | return error; | |
998 | } | |
999 | ||
1000 | int ath_cabq_update(struct ath_softc *sc) | |
1001 | { | |
1002 | struct ath9k_tx_queue_info qi; | |
1003 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 1004 | |
e8324357 | 1005 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1006 | /* |
e8324357 | 1007 | * Ensure the readytime % is within the bounds. |
f078f209 | 1008 | */ |
17d7904d S |
1009 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1010 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1011 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1012 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1013 | |
57c4d7b4 | 1014 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 1015 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1016 | ath_txq_update(sc, qnum, &qi); |
1017 | ||
1018 | return 0; | |
f078f209 LR |
1019 | } |
1020 | ||
043a0405 S |
1021 | /* |
1022 | * Drain a given TX queue (could be Beacon or Data) | |
1023 | * | |
1024 | * This assumes output has been stopped and | |
1025 | * we do not need to block ath_tx_tasklet. | |
1026 | */ | |
1027 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 1028 | { |
e8324357 S |
1029 | struct ath_buf *bf, *lastbf; |
1030 | struct list_head bf_head; | |
f078f209 | 1031 | |
e8324357 | 1032 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1033 | |
e8324357 S |
1034 | for (;;) { |
1035 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1036 | |
e8324357 S |
1037 | if (list_empty(&txq->axq_q)) { |
1038 | txq->axq_link = NULL; | |
e8324357 S |
1039 | spin_unlock_bh(&txq->axq_lock); |
1040 | break; | |
1041 | } | |
f078f209 | 1042 | |
e8324357 | 1043 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1044 | |
a119cc49 | 1045 | if (bf->bf_stale) { |
e8324357 S |
1046 | list_del(&bf->list); |
1047 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1048 | |
e8324357 S |
1049 | spin_lock_bh(&sc->tx.txbuflock); |
1050 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1051 | spin_unlock_bh(&sc->tx.txbuflock); | |
1052 | continue; | |
1053 | } | |
f078f209 | 1054 | |
e8324357 S |
1055 | lastbf = bf->bf_lastbf; |
1056 | if (!retry_tx) | |
1057 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1058 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1059 | |
e8324357 S |
1060 | /* remove ath_buf's of the same mpdu from txq */ |
1061 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1062 | txq->axq_depth--; | |
f078f209 | 1063 | |
e8324357 S |
1064 | spin_unlock_bh(&txq->axq_lock); |
1065 | ||
1066 | if (bf_isampdu(bf)) | |
d43f3015 | 1067 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 | 1068 | else |
fec247c0 | 1069 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 LR |
1070 | } |
1071 | ||
164ace38 SB |
1072 | spin_lock_bh(&txq->axq_lock); |
1073 | txq->axq_tx_inprogress = false; | |
1074 | spin_unlock_bh(&txq->axq_lock); | |
1075 | ||
e8324357 S |
1076 | /* flush any pending frames if aggregation is enabled */ |
1077 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1078 | if (!retry_tx) { | |
1079 | spin_lock_bh(&txq->axq_lock); | |
1080 | ath_txq_drain_pending_buffers(sc, txq); | |
1081 | spin_unlock_bh(&txq->axq_lock); | |
1082 | } | |
1083 | } | |
f078f209 LR |
1084 | } |
1085 | ||
043a0405 | 1086 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1087 | { |
cbe61d8a | 1088 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1089 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 S |
1090 | struct ath_txq *txq; |
1091 | int i, npend = 0; | |
1092 | ||
1093 | if (sc->sc_flags & SC_OP_INVALID) | |
1094 | return; | |
1095 | ||
1096 | /* Stop beacon queue */ | |
1097 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1098 | ||
1099 | /* Stop data queues */ | |
1100 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1101 | if (ATH_TXQ_SETUP(sc, i)) { | |
1102 | txq = &sc->tx.txq[i]; | |
1103 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1104 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1105 | } | |
1106 | } | |
1107 | ||
1108 | if (npend) { | |
1109 | int r; | |
1110 | ||
e8009e98 | 1111 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 1112 | "Unable to stop TxDMA. Reset HAL!\n"); |
043a0405 S |
1113 | |
1114 | spin_lock_bh(&sc->sc_resetlock); | |
e8009e98 | 1115 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
043a0405 | 1116 | if (r) |
c46917bb LR |
1117 | ath_print(common, ATH_DBG_FATAL, |
1118 | "Unable to reset hardware; reset status %d\n", | |
1119 | r); | |
043a0405 S |
1120 | spin_unlock_bh(&sc->sc_resetlock); |
1121 | } | |
1122 | ||
1123 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1124 | if (ATH_TXQ_SETUP(sc, i)) | |
1125 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1126 | } | |
e8324357 | 1127 | } |
f078f209 | 1128 | |
043a0405 | 1129 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1130 | { |
043a0405 S |
1131 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1132 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1133 | } |
f078f209 | 1134 | |
e8324357 S |
1135 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1136 | { | |
1137 | struct ath_atx_ac *ac; | |
1138 | struct ath_atx_tid *tid; | |
f078f209 | 1139 | |
e8324357 S |
1140 | if (list_empty(&txq->axq_acq)) |
1141 | return; | |
f078f209 | 1142 | |
e8324357 S |
1143 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1144 | list_del(&ac->list); | |
1145 | ac->sched = false; | |
f078f209 | 1146 | |
e8324357 S |
1147 | do { |
1148 | if (list_empty(&ac->tid_q)) | |
1149 | return; | |
f078f209 | 1150 | |
e8324357 S |
1151 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1152 | list_del(&tid->list); | |
1153 | tid->sched = false; | |
f078f209 | 1154 | |
e8324357 S |
1155 | if (tid->paused) |
1156 | continue; | |
f078f209 | 1157 | |
164ace38 | 1158 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1159 | |
1160 | /* | |
e8324357 S |
1161 | * add tid to round-robin queue if more frames |
1162 | * are pending for the tid | |
f078f209 | 1163 | */ |
e8324357 S |
1164 | if (!list_empty(&tid->buf_q)) |
1165 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1166 | |
e8324357 S |
1167 | break; |
1168 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1169 | |
e8324357 S |
1170 | if (!list_empty(&ac->tid_q)) { |
1171 | if (!ac->sched) { | |
1172 | ac->sched = true; | |
1173 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1174 | } |
e8324357 S |
1175 | } |
1176 | } | |
f078f209 | 1177 | |
e8324357 S |
1178 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1179 | { | |
1180 | struct ath_txq *txq; | |
f078f209 | 1181 | |
e8324357 | 1182 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
c46917bb LR |
1183 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1184 | "HAL AC %u out of range, max %zu!\n", | |
e8324357 S |
1185 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); |
1186 | return 0; | |
1187 | } | |
1188 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1189 | if (txq != NULL) { | |
1190 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1191 | return 1; | |
1192 | } else | |
1193 | return 0; | |
f078f209 LR |
1194 | } |
1195 | ||
e8324357 S |
1196 | /***********/ |
1197 | /* TX, DMA */ | |
1198 | /***********/ | |
1199 | ||
f078f209 | 1200 | /* |
e8324357 S |
1201 | * Insert a chain of ath_buf (descriptors) on a txq and |
1202 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1203 | */ |
e8324357 S |
1204 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1205 | struct list_head *head) | |
f078f209 | 1206 | { |
cbe61d8a | 1207 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1208 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1209 | struct ath_buf *bf; |
f078f209 | 1210 | |
e8324357 S |
1211 | /* |
1212 | * Insert the frame on the outbound list and | |
1213 | * pass it on to the hardware. | |
1214 | */ | |
f078f209 | 1215 | |
e8324357 S |
1216 | if (list_empty(head)) |
1217 | return; | |
f078f209 | 1218 | |
e8324357 | 1219 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1220 | |
e8324357 S |
1221 | list_splice_tail_init(head, &txq->axq_q); |
1222 | txq->axq_depth++; | |
f078f209 | 1223 | |
c46917bb LR |
1224 | ath_print(common, ATH_DBG_QUEUE, |
1225 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1226 | |
e8324357 S |
1227 | if (txq->axq_link == NULL) { |
1228 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
c46917bb LR |
1229 | ath_print(common, ATH_DBG_XMIT, |
1230 | "TXDP[%u] = %llx (%p)\n", | |
1231 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1232 | } else { |
1233 | *txq->axq_link = bf->bf_daddr; | |
c46917bb LR |
1234 | ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", |
1235 | txq->axq_qnum, txq->axq_link, | |
1236 | ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1237 | } |
1238 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1239 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1240 | } | |
f078f209 | 1241 | |
e8324357 S |
1242 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1243 | { | |
1244 | struct ath_buf *bf = NULL; | |
f078f209 | 1245 | |
e8324357 | 1246 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1247 | |
e8324357 S |
1248 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1249 | spin_unlock_bh(&sc->tx.txbuflock); | |
1250 | return NULL; | |
1251 | } | |
f078f209 | 1252 | |
e8324357 S |
1253 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1254 | list_del(&bf->list); | |
f078f209 | 1255 | |
e8324357 | 1256 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1257 | |
e8324357 | 1258 | return bf; |
f078f209 LR |
1259 | } |
1260 | ||
e8324357 S |
1261 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1262 | struct list_head *bf_head, | |
1263 | struct ath_tx_control *txctl) | |
f078f209 LR |
1264 | { |
1265 | struct ath_buf *bf; | |
f078f209 | 1266 | |
e8324357 S |
1267 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1268 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1269 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1270 | |
e8324357 S |
1271 | /* |
1272 | * Do not queue to h/w when any of the following conditions is true: | |
1273 | * - there are pending frames in software queue | |
1274 | * - the TID is currently paused for ADDBA/BAR request | |
1275 | * - seqno is not within block-ack window | |
1276 | * - h/w queue depth exceeds low water mark | |
1277 | */ | |
1278 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1279 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1280 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1281 | /* |
e8324357 S |
1282 | * Add this frame to software queue for scheduling later |
1283 | * for aggregation. | |
f078f209 | 1284 | */ |
d43f3015 | 1285 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1286 | ath_tx_queue_tid(txctl->txq, tid); |
1287 | return; | |
1288 | } | |
1289 | ||
1290 | /* Add sub-frame to BAW */ | |
1291 | ath_tx_addto_baw(sc, tid, bf); | |
1292 | ||
1293 | /* Queue to h/w without aggregation */ | |
1294 | bf->bf_nframes = 1; | |
d43f3015 | 1295 | bf->bf_lastbf = bf; |
e8324357 S |
1296 | ath_buf_set_rate(sc, bf); |
1297 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1298 | } |
1299 | ||
c37452b0 S |
1300 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1301 | struct ath_atx_tid *tid, | |
1302 | struct list_head *bf_head) | |
e8324357 S |
1303 | { |
1304 | struct ath_buf *bf; | |
1305 | ||
e8324357 S |
1306 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1307 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1308 | ||
1309 | /* update starting sequence number for subsequent ADDBA request */ | |
1310 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1311 | ||
1312 | bf->bf_nframes = 1; | |
d43f3015 | 1313 | bf->bf_lastbf = bf; |
e8324357 S |
1314 | ath_buf_set_rate(sc, bf); |
1315 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1316 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1317 | } |
1318 | ||
c37452b0 S |
1319 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1320 | struct list_head *bf_head) | |
1321 | { | |
1322 | struct ath_buf *bf; | |
1323 | ||
1324 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1325 | ||
1326 | bf->bf_lastbf = bf; | |
1327 | bf->bf_nframes = 1; | |
1328 | ath_buf_set_rate(sc, bf); | |
1329 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1330 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1331 | } |
1332 | ||
e8324357 S |
1333 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1334 | { | |
1335 | struct ieee80211_hdr *hdr; | |
1336 | enum ath9k_pkt_type htype; | |
1337 | __le16 fc; | |
1338 | ||
1339 | hdr = (struct ieee80211_hdr *)skb->data; | |
1340 | fc = hdr->frame_control; | |
1341 | ||
1342 | if (ieee80211_is_beacon(fc)) | |
1343 | htype = ATH9K_PKT_TYPE_BEACON; | |
1344 | else if (ieee80211_is_probe_resp(fc)) | |
1345 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1346 | else if (ieee80211_is_atim(fc)) | |
1347 | htype = ATH9K_PKT_TYPE_ATIM; | |
1348 | else if (ieee80211_is_pspoll(fc)) | |
1349 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1350 | else | |
1351 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1352 | ||
1353 | return htype; | |
1354 | } | |
1355 | ||
1356 | static bool is_pae(struct sk_buff *skb) | |
1357 | { | |
1358 | struct ieee80211_hdr *hdr; | |
1359 | __le16 fc; | |
1360 | ||
1361 | hdr = (struct ieee80211_hdr *)skb->data; | |
1362 | fc = hdr->frame_control; | |
1363 | ||
1364 | if (ieee80211_is_data(fc)) { | |
1365 | if (ieee80211_is_nullfunc(fc) || | |
1366 | /* Port Access Entity (IEEE 802.1X) */ | |
1367 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1368 | return true; | |
1369 | } | |
1370 | } | |
1371 | ||
1372 | return false; | |
1373 | } | |
1374 | ||
1375 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1376 | { | |
1377 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1378 | ||
1379 | if (tx_info->control.hw_key) { | |
1380 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1381 | return ATH9K_KEY_TYPE_WEP; | |
1382 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1383 | return ATH9K_KEY_TYPE_TKIP; | |
1384 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1385 | return ATH9K_KEY_TYPE_AES; | |
1386 | } | |
1387 | ||
1388 | return ATH9K_KEY_TYPE_CLEAR; | |
1389 | } | |
1390 | ||
1391 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1392 | struct ath_buf *bf) | |
1393 | { | |
1394 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1395 | struct ieee80211_hdr *hdr; | |
1396 | struct ath_node *an; | |
1397 | struct ath_atx_tid *tid; | |
1398 | __le16 fc; | |
1399 | u8 *qc; | |
1400 | ||
1401 | if (!tx_info->control.sta) | |
1402 | return; | |
1403 | ||
1404 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1405 | hdr = (struct ieee80211_hdr *)skb->data; | |
1406 | fc = hdr->frame_control; | |
1407 | ||
1408 | if (ieee80211_is_data_qos(fc)) { | |
1409 | qc = ieee80211_get_qos_ctl(hdr); | |
1410 | bf->bf_tidno = qc[0] & 0xf; | |
1411 | } | |
1412 | ||
1413 | /* | |
1414 | * For HT capable stations, we save tidno for later use. | |
1415 | * We also override seqno set by upper layer with the one | |
1416 | * in tx aggregation state. | |
e8324357 S |
1417 | */ |
1418 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
17b182e3 | 1419 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); |
e8324357 S |
1420 | bf->bf_seqno = tid->seq_next; |
1421 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1422 | } | |
1423 | ||
1424 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1425 | struct ath_txq *txq) | |
1426 | { | |
1427 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1428 | int flags = 0; | |
1429 | ||
1430 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1431 | flags |= ATH9K_TXDESC_INTREQ; | |
1432 | ||
1433 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1434 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1435 | |
1436 | return flags; | |
1437 | } | |
1438 | ||
1439 | /* | |
1440 | * rix - rate index | |
1441 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1442 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1443 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1444 | */ | |
1445 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1446 | int width, int half_gi, bool shortPreamble) | |
1447 | { | |
e8324357 | 1448 | u32 nbits, nsymbits, duration, nsymbols; |
e8324357 S |
1449 | int streams, pktlen; |
1450 | ||
1451 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
e8324357 S |
1452 | |
1453 | /* find number of symbols: PLCP + data */ | |
1454 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
545750d3 | 1455 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 S |
1456 | nsymbols = (nbits + nsymbits - 1) / nsymbits; |
1457 | ||
1458 | if (!half_gi) | |
1459 | duration = SYMBOL_TIME(nsymbols); | |
1460 | else | |
1461 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1462 | ||
1463 | /* addup duration for legacy/ht training and signal fields */ | |
545750d3 | 1464 | streams = HT_RC_2_STREAMS(rix); |
e8324357 S |
1465 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
1466 | ||
1467 | return duration; | |
1468 | } | |
1469 | ||
1470 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1471 | { | |
43c27613 | 1472 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1473 | struct ath9k_11n_rate_series series[4]; |
1474 | struct sk_buff *skb; | |
1475 | struct ieee80211_tx_info *tx_info; | |
1476 | struct ieee80211_tx_rate *rates; | |
545750d3 | 1477 | const struct ieee80211_rate *rate; |
254ad0ff | 1478 | struct ieee80211_hdr *hdr; |
c89424df S |
1479 | int i, flags = 0; |
1480 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1481 | bool is_pspoll; |
e8324357 S |
1482 | |
1483 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1484 | ||
a22be22a | 1485 | skb = bf->bf_mpdu; |
e8324357 S |
1486 | tx_info = IEEE80211_SKB_CB(skb); |
1487 | rates = tx_info->control.rates; | |
254ad0ff S |
1488 | hdr = (struct ieee80211_hdr *)skb->data; |
1489 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1490 | |
e8324357 | 1491 | /* |
c89424df S |
1492 | * We check if Short Preamble is needed for the CTS rate by |
1493 | * checking the BSS's global flag. | |
1494 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1495 | */ |
545750d3 FF |
1496 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); |
1497 | ctsrate = rate->hw_value; | |
c89424df | 1498 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
545750d3 | 1499 | ctsrate |= rate->hw_value_short; |
e8324357 | 1500 | |
c89424df S |
1501 | /* |
1502 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1503 | * Check the first rate in the series to decide whether RTS/CTS | |
1504 | * or CTS-to-self has to be used. | |
e8324357 | 1505 | */ |
c89424df S |
1506 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1507 | flags = ATH9K_TXDESC_CTSENA; | |
1508 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1509 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1510 | |
c89424df | 1511 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1512 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1513 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1514 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1515 | } |
1516 | ||
1517 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1518 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1519 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1520 | ||
e8324357 | 1521 | for (i = 0; i < 4; i++) { |
545750d3 FF |
1522 | bool is_40, is_sgi, is_sp; |
1523 | int phy; | |
1524 | ||
e8324357 S |
1525 | if (!rates[i].count || (rates[i].idx < 0)) |
1526 | continue; | |
1527 | ||
1528 | rix = rates[i].idx; | |
e8324357 | 1529 | series[i].Tries = rates[i].count; |
43c27613 | 1530 | series[i].ChSel = common->tx_chainmask; |
e8324357 | 1531 | |
c89424df S |
1532 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) |
1533 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1534 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1535 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1536 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1537 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 | 1538 | |
545750d3 FF |
1539 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); |
1540 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1541 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1542 | ||
1543 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1544 | /* MCS rates */ | |
1545 | series[i].Rate = rix | 0x80; | |
1546 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1547 | is_40, is_sgi, is_sp); | |
1548 | continue; | |
1549 | } | |
1550 | ||
1551 | /* legcay rates */ | |
1552 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | |
1553 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1554 | phy = WLAN_RC_PHY_CCK; | |
1555 | else | |
1556 | phy = WLAN_RC_PHY_OFDM; | |
1557 | ||
1558 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | |
1559 | series[i].Rate = rate->hw_value; | |
1560 | if (rate->hw_value_short) { | |
1561 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
1562 | series[i].Rate |= rate->hw_value_short; | |
1563 | } else { | |
1564 | is_sp = false; | |
1565 | } | |
1566 | ||
1567 | series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | |
1568 | phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp); | |
f078f209 LR |
1569 | } |
1570 | ||
e8324357 | 1571 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1572 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1573 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1574 | !is_pspoll, ctsrate, |
c89424df | 1575 | 0, series, 4, flags); |
f078f209 | 1576 | |
17d7904d | 1577 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1578 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1579 | } |
1580 | ||
c52f33d0 | 1581 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1582 | struct sk_buff *skb, |
528f0c6b | 1583 | struct ath_tx_control *txctl) |
f078f209 | 1584 | { |
c52f33d0 JM |
1585 | struct ath_wiphy *aphy = hw->priv; |
1586 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1587 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1588 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
528f0c6b S |
1589 | int hdrlen; |
1590 | __le16 fc; | |
1bc14880 | 1591 | int padpos, padsize; |
e022edbd | 1592 | |
827e69bf FF |
1593 | tx_info->pad[0] = 0; |
1594 | switch (txctl->frame_type) { | |
1595 | case ATH9K_NOT_INTERNAL: | |
1596 | break; | |
1597 | case ATH9K_INT_PAUSE: | |
1598 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE; | |
1599 | /* fall through */ | |
1600 | case ATH9K_INT_UNPAUSE: | |
1601 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL; | |
1602 | break; | |
1603 | } | |
528f0c6b S |
1604 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1605 | fc = hdr->frame_control; | |
f078f209 | 1606 | |
528f0c6b | 1607 | ATH_TXBUF_RESET(bf); |
f078f209 | 1608 | |
827e69bf | 1609 | bf->aphy = aphy; |
1bc14880 BP |
1610 | bf->bf_frmlen = skb->len + FCS_LEN; |
1611 | /* Remove the padding size from bf_frmlen, if any */ | |
1612 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1613 | padsize = padpos & 3; | |
1614 | if (padsize && skb->len>padpos+padsize) { | |
1615 | bf->bf_frmlen -= padsize; | |
1616 | } | |
cd3d39a6 | 1617 | |
6c8afef5 | 1618 | if (conf_is_ht(&hw->conf)) |
c656bbb5 | 1619 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1620 | |
1621 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1622 | ||
528f0c6b | 1623 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1624 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1625 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1626 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1627 | } else { | |
1628 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1629 | } | |
1630 | ||
17b182e3 S |
1631 | if (ieee80211_is_data_qos(fc) && bf_isht(bf) && |
1632 | (sc->sc_flags & SC_OP_TXAGGR)) | |
528f0c6b S |
1633 | assign_aggr_tid_seqno(skb, bf); |
1634 | ||
f078f209 | 1635 | bf->bf_mpdu = skb; |
f8316df1 | 1636 | |
7da3c55c GJ |
1637 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1638 | skb->len, DMA_TO_DEVICE); | |
1639 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1640 | bf->bf_mpdu = NULL; |
c46917bb LR |
1641 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1642 | "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1643 | return -ENOMEM; |
1644 | } | |
1645 | ||
528f0c6b | 1646 | bf->bf_buf_addr = bf->bf_dmacontext; |
e7824a50 LR |
1647 | |
1648 | /* tag if this is a nullfunc frame to enable PS when AP acks it */ | |
1649 | if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) { | |
1650 | bf->bf_isnullfunc = true; | |
1651 | sc->sc_flags &= ~SC_OP_NULLFUNC_COMPLETED; | |
1652 | } else | |
1653 | bf->bf_isnullfunc = false; | |
1654 | ||
f8316df1 | 1655 | return 0; |
528f0c6b S |
1656 | } |
1657 | ||
1658 | /* FIXME: tx power */ | |
1659 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1660 | struct ath_tx_control *txctl) |
1661 | { | |
a22be22a | 1662 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1663 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1664 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1665 | struct ath_node *an = NULL; |
1666 | struct list_head bf_head; | |
1667 | struct ath_desc *ds; | |
1668 | struct ath_atx_tid *tid; | |
cbe61d8a | 1669 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1670 | int frm_type; |
c37452b0 | 1671 | __le16 fc; |
528f0c6b | 1672 | |
528f0c6b | 1673 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1674 | fc = hdr->frame_control; |
528f0c6b S |
1675 | |
1676 | INIT_LIST_HEAD(&bf_head); | |
1677 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1678 | |
f078f209 LR |
1679 | ds = bf->bf_desc; |
1680 | ds->ds_link = 0; | |
1681 | ds->ds_data = bf->bf_buf_addr; | |
1682 | ||
528f0c6b S |
1683 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1684 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1685 | ||
1686 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1687 | skb->len, /* segment length */ |
1688 | true, /* first segment */ | |
1689 | true, /* last segment */ | |
1690 | ds); /* first descriptor */ | |
f078f209 | 1691 | |
528f0c6b | 1692 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1693 | |
f1617967 JL |
1694 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1695 | tx_info->control.sta) { | |
1696 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1697 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1698 | ||
c37452b0 S |
1699 | if (!ieee80211_is_data_qos(fc)) { |
1700 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1701 | goto tx_done; | |
1702 | } | |
1703 | ||
6c8afef5 | 1704 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && !is_pae(skb)) { |
f078f209 LR |
1705 | /* |
1706 | * Try aggregation if it's a unicast data frame | |
1707 | * and the destination is HT capable. | |
1708 | */ | |
528f0c6b | 1709 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1710 | } else { |
1711 | /* | |
528f0c6b S |
1712 | * Send this frame as regular when ADDBA |
1713 | * exchange is neither complete nor pending. | |
f078f209 | 1714 | */ |
c37452b0 S |
1715 | ath_tx_send_ht_normal(sc, txctl->txq, |
1716 | tid, &bf_head); | |
f078f209 LR |
1717 | } |
1718 | } else { | |
c37452b0 | 1719 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1720 | } |
528f0c6b | 1721 | |
c37452b0 | 1722 | tx_done: |
528f0c6b | 1723 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1724 | } |
1725 | ||
f8316df1 | 1726 | /* Upon failure caller should free skb */ |
c52f33d0 | 1727 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1728 | struct ath_tx_control *txctl) |
f078f209 | 1729 | { |
c52f33d0 JM |
1730 | struct ath_wiphy *aphy = hw->priv; |
1731 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1732 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1733 | struct ath_buf *bf; |
f8316df1 | 1734 | int r; |
f078f209 | 1735 | |
528f0c6b S |
1736 | bf = ath_tx_get_buffer(sc); |
1737 | if (!bf) { | |
c46917bb | 1738 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1739 | return -1; |
1740 | } | |
1741 | ||
c52f33d0 | 1742 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1743 | if (unlikely(r)) { |
c112d0c5 LR |
1744 | struct ath_txq *txq = txctl->txq; |
1745 | ||
c46917bb | 1746 | ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1747 | |
1748 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1749 | * guarantee this will happen by knowing beforehand that | |
1750 | * we will at least have to run TX completionon one buffer | |
1751 | * on the queue */ | |
1752 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1753 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
f52de03b | 1754 | ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb)); |
c112d0c5 LR |
1755 | txq->stopped = 1; |
1756 | } | |
1757 | spin_unlock_bh(&txq->axq_lock); | |
1758 | ||
b77f483f S |
1759 | spin_lock_bh(&sc->tx.txbuflock); |
1760 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1761 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1762 | |
f8316df1 LR |
1763 | return r; |
1764 | } | |
1765 | ||
8f93b8b3 | 1766 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1767 | |
528f0c6b | 1768 | return 0; |
f078f209 LR |
1769 | } |
1770 | ||
c52f33d0 | 1771 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1772 | { |
c52f33d0 JM |
1773 | struct ath_wiphy *aphy = hw->priv; |
1774 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1775 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1776 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1777 | int padpos, padsize; | |
e8324357 S |
1778 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1779 | struct ath_tx_control txctl; | |
f078f209 | 1780 | |
e8324357 | 1781 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1782 | |
1783 | /* | |
e8324357 S |
1784 | * As a temporary workaround, assign seq# here; this will likely need |
1785 | * to be cleaned up to work better with Beacon transmission and virtual | |
1786 | * BSSes. | |
f078f209 | 1787 | */ |
e8324357 | 1788 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1789 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1790 | sc->tx.seq_no += 0x10; | |
1791 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1792 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1793 | } |
f078f209 | 1794 | |
e8324357 | 1795 | /* Add the padding after the header if this is not already done */ |
4d91f9f3 BP |
1796 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1797 | padsize = padpos & 3; | |
1798 | if (padsize && skb->len>padpos) { | |
e8324357 | 1799 | if (skb_headroom(skb) < padsize) { |
c46917bb LR |
1800 | ath_print(common, ATH_DBG_XMIT, |
1801 | "TX CABQ padding failed\n"); | |
e8324357 S |
1802 | dev_kfree_skb_any(skb); |
1803 | return; | |
1804 | } | |
1805 | skb_push(skb, padsize); | |
4d91f9f3 | 1806 | memmove(skb->data, skb->data + padsize, padpos); |
f078f209 | 1807 | } |
f078f209 | 1808 | |
e8324357 | 1809 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1810 | |
c46917bb LR |
1811 | ath_print(common, ATH_DBG_XMIT, |
1812 | "transmitting CABQ packet, skb: %p\n", skb); | |
f078f209 | 1813 | |
c52f33d0 | 1814 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1815 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
e8324357 | 1816 | goto exit; |
f078f209 | 1817 | } |
f078f209 | 1818 | |
e8324357 S |
1819 | return; |
1820 | exit: | |
1821 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1822 | } |
1823 | ||
e8324357 S |
1824 | /*****************/ |
1825 | /* TX Completion */ | |
1826 | /*****************/ | |
528f0c6b | 1827 | |
e8324357 | 1828 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
827e69bf | 1829 | struct ath_wiphy *aphy, int tx_flags) |
528f0c6b | 1830 | { |
e8324357 S |
1831 | struct ieee80211_hw *hw = sc->hw; |
1832 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
c46917bb | 1833 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1834 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1835 | int padpos, padsize; | |
528f0c6b | 1836 | |
c46917bb | 1837 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1838 | |
827e69bf FF |
1839 | if (aphy) |
1840 | hw = aphy->hw; | |
528f0c6b | 1841 | |
6b2c4032 | 1842 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1843 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1844 | |
6b2c4032 | 1845 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1846 | /* Frame was ACKed */ |
1847 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1848 | } |
1849 | ||
4d91f9f3 BP |
1850 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1851 | padsize = padpos & 3; | |
1852 | if (padsize && skb->len>padpos+padsize) { | |
e8324357 S |
1853 | /* |
1854 | * Remove MAC header padding before giving the frame back to | |
1855 | * mac80211. | |
1856 | */ | |
4d91f9f3 | 1857 | memmove(skb->data + padsize, skb->data, padpos); |
e8324357 S |
1858 | skb_pull(skb, padsize); |
1859 | } | |
528f0c6b | 1860 | |
9a23f9ca JM |
1861 | if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { |
1862 | sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; | |
c46917bb LR |
1863 | ath_print(common, ATH_DBG_PS, |
1864 | "Going back to sleep after having " | |
1865 | "received TX status (0x%x)\n", | |
9a23f9ca JM |
1866 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
1867 | SC_OP_WAIT_FOR_CAB | | |
1868 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
1869 | SC_OP_WAIT_FOR_TX_ACK)); | |
1870 | } | |
1871 | ||
827e69bf | 1872 | if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL)) |
f0ed85c6 | 1873 | ath9k_tx_status(hw, skb); |
827e69bf FF |
1874 | else |
1875 | ieee80211_tx_status(hw, skb); | |
e8324357 | 1876 | } |
f078f209 | 1877 | |
e8324357 | 1878 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 1879 | struct ath_txq *txq, |
e8324357 S |
1880 | struct list_head *bf_q, |
1881 | int txok, int sendbar) | |
f078f209 | 1882 | { |
e8324357 | 1883 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1884 | unsigned long flags; |
6b2c4032 | 1885 | int tx_flags = 0; |
f078f209 | 1886 | |
e8324357 | 1887 | if (sendbar) |
6b2c4032 | 1888 | tx_flags = ATH_TX_BAR; |
f078f209 | 1889 | |
e8324357 | 1890 | if (!txok) { |
6b2c4032 | 1891 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1892 | |
e8324357 | 1893 | if (bf_isxretried(bf)) |
6b2c4032 | 1894 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1895 | } |
1896 | ||
e8324357 | 1897 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
827e69bf | 1898 | ath_tx_complete(sc, skb, bf->aphy, tx_flags); |
fec247c0 | 1899 | ath_debug_stat_tx(sc, txq, bf); |
e8324357 S |
1900 | |
1901 | /* | |
1902 | * Return the list of ath_buf of this mpdu to free queue | |
1903 | */ | |
1904 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1905 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1906 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1907 | } |
1908 | ||
e8324357 S |
1909 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1910 | int txok) | |
f078f209 | 1911 | { |
e8324357 S |
1912 | struct ath_buf *bf_last = bf->bf_lastbf; |
1913 | struct ath_desc *ds = bf_last->bf_desc; | |
1914 | u16 seq_st = 0; | |
1915 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1916 | int ba_index; | |
1917 | int nbad = 0; | |
1918 | int isaggr = 0; | |
f078f209 | 1919 | |
e8324357 S |
1920 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1921 | return 0; | |
f078f209 | 1922 | |
e8324357 S |
1923 | isaggr = bf_isaggr(bf); |
1924 | if (isaggr) { | |
1925 | seq_st = ATH_DS_BA_SEQ(ds); | |
1926 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1927 | } | |
f078f209 | 1928 | |
e8324357 S |
1929 | while (bf) { |
1930 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1931 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1932 | nbad++; | |
1933 | ||
1934 | bf = bf->bf_next; | |
1935 | } | |
f078f209 | 1936 | |
e8324357 S |
1937 | return nbad; |
1938 | } | |
f078f209 | 1939 | |
95e4acb7 | 1940 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, |
8a92e2ee | 1941 | int nbad, int txok, bool update_rc) |
f078f209 | 1942 | { |
a22be22a | 1943 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1944 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 1945 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 1946 | struct ieee80211_hw *hw = bf->aphy->hw; |
8a92e2ee | 1947 | u8 i, tx_rateindex; |
f078f209 | 1948 | |
95e4acb7 S |
1949 | if (txok) |
1950 | tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; | |
1951 | ||
8a92e2ee VT |
1952 | tx_rateindex = ds->ds_txstat.ts_rateindex; |
1953 | WARN_ON(tx_rateindex >= hw->max_rates); | |
1954 | ||
827e69bf FF |
1955 | if (update_rc) |
1956 | tx_info->pad[0] |= ATH_TX_INFO_UPDATE_RC; | |
e8324357 S |
1957 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1958 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1959 | |
e8324357 | 1960 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1961 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1962 | if (ieee80211_is_data(hdr->frame_control)) { |
827e69bf FF |
1963 | if (ds->ds_txstat.ts_flags & |
1964 | (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN)) | |
1965 | tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN; | |
1966 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) || | |
1967 | (ds->ds_txstat.ts_status & ATH9K_TXERR_FIFO)) | |
1968 | tx_info->pad[0] |= ATH_TX_INFO_XRETRY; | |
1969 | tx_info->status.ampdu_len = bf->bf_nframes; | |
1970 | tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad; | |
e8324357 | 1971 | } |
f078f209 | 1972 | } |
8a92e2ee | 1973 | |
545750d3 | 1974 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 1975 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
1976 | tx_info->status.rates[i].idx = -1; |
1977 | } | |
8a92e2ee VT |
1978 | |
1979 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1980 | } |
1981 | ||
059d806c S |
1982 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1983 | { | |
1984 | int qnum; | |
1985 | ||
1986 | spin_lock_bh(&txq->axq_lock); | |
1987 | if (txq->stopped && | |
f7a99e46 | 1988 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1989 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1990 | if (qnum != -1) { | |
f52de03b | 1991 | ath_mac80211_start_queue(sc, qnum); |
059d806c S |
1992 | txq->stopped = 0; |
1993 | } | |
1994 | } | |
1995 | spin_unlock_bh(&txq->axq_lock); | |
1996 | } | |
1997 | ||
e8324357 | 1998 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1999 | { |
cbe61d8a | 2000 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 2001 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 2002 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 2003 | struct list_head bf_head; |
e8324357 | 2004 | struct ath_desc *ds; |
0934af23 | 2005 | int txok; |
e8324357 | 2006 | int status; |
f078f209 | 2007 | |
c46917bb LR |
2008 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
2009 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
2010 | txq->axq_link); | |
f078f209 | 2011 | |
f078f209 LR |
2012 | for (;;) { |
2013 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
2014 | if (list_empty(&txq->axq_q)) { |
2015 | txq->axq_link = NULL; | |
f078f209 LR |
2016 | spin_unlock_bh(&txq->axq_lock); |
2017 | break; | |
2018 | } | |
f078f209 LR |
2019 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2020 | ||
e8324357 S |
2021 | /* |
2022 | * There is a race condition that a BH gets scheduled | |
2023 | * after sw writes TxE and before hw re-load the last | |
2024 | * descriptor to get the newly chained one. | |
2025 | * Software must keep the last DONE descriptor as a | |
2026 | * holding descriptor - software does so by marking | |
2027 | * it with the STALE flag. | |
2028 | */ | |
2029 | bf_held = NULL; | |
a119cc49 | 2030 | if (bf->bf_stale) { |
e8324357 S |
2031 | bf_held = bf; |
2032 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 2033 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
2034 | break; |
2035 | } else { | |
2036 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 2037 | struct ath_buf, list); |
e8324357 | 2038 | } |
f078f209 LR |
2039 | } |
2040 | ||
2041 | lastbf = bf->bf_lastbf; | |
e8324357 | 2042 | ds = lastbf->bf_desc; |
f078f209 | 2043 | |
e8324357 S |
2044 | status = ath9k_hw_txprocdesc(ah, ds); |
2045 | if (status == -EINPROGRESS) { | |
f078f209 | 2046 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2047 | break; |
f078f209 | 2048 | } |
f078f209 | 2049 | |
e7824a50 LR |
2050 | /* |
2051 | * We now know the nullfunc frame has been ACKed so we | |
2052 | * can disable RX. | |
2053 | */ | |
2054 | if (bf->bf_isnullfunc && | |
2055 | (ds->ds_txstat.ts_status & ATH9K_TX_ACKED)) { | |
2056 | if ((sc->sc_flags & SC_OP_PS_ENABLED)) { | |
2057 | sc->ps_enabled = true; | |
2058 | ath9k_hw_setrxabort(sc->sc_ah, 1); | |
2059 | } else | |
2060 | sc->sc_flags |= SC_OP_NULLFUNC_COMPLETED; | |
2061 | } | |
2062 | ||
e8324357 S |
2063 | /* |
2064 | * Remove ath_buf's of the same transmit unit from txq, | |
2065 | * however leave the last descriptor back as the holding | |
2066 | * descriptor for hw. | |
2067 | */ | |
a119cc49 | 2068 | lastbf->bf_stale = true; |
e8324357 | 2069 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2070 | if (!list_is_singular(&lastbf->list)) |
2071 | list_cut_position(&bf_head, | |
2072 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2073 | |
e8324357 | 2074 | txq->axq_depth--; |
5b479a07 | 2075 | txok = !(ds->ds_txstat.ts_status & ATH9K_TXERR_MASK); |
164ace38 | 2076 | txq->axq_tx_inprogress = false; |
e8324357 | 2077 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2078 | |
e8324357 | 2079 | if (bf_held) { |
e8324357 | 2080 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2081 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2082 | spin_unlock_bh(&sc->tx.txbuflock); |
2083 | } | |
f078f209 | 2084 | |
e8324357 S |
2085 | if (!bf_isampdu(bf)) { |
2086 | /* | |
2087 | * This frame is sent out as a single frame. | |
2088 | * Use hardware retry status for this frame. | |
2089 | */ | |
2090 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2091 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2092 | bf->bf_state.bf_type |= BUF_XRETRY; | |
8a92e2ee | 2093 | ath_tx_rc_status(bf, ds, 0, txok, true); |
e8324357 | 2094 | } |
f078f209 | 2095 | |
e8324357 | 2096 | if (bf_isampdu(bf)) |
d43f3015 | 2097 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 | 2098 | else |
fec247c0 | 2099 | ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0); |
8469cdef | 2100 | |
059d806c | 2101 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2102 | |
059d806c | 2103 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2104 | if (sc->sc_flags & SC_OP_TXAGGR) |
2105 | ath_txq_schedule(sc, txq); | |
2106 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2107 | } |
2108 | } | |
2109 | ||
305fe47f | 2110 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2111 | { |
2112 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2113 | tx_complete_work.work); | |
2114 | struct ath_txq *txq; | |
2115 | int i; | |
2116 | bool needreset = false; | |
2117 | ||
2118 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2119 | if (ATH_TXQ_SETUP(sc, i)) { | |
2120 | txq = &sc->tx.txq[i]; | |
2121 | spin_lock_bh(&txq->axq_lock); | |
2122 | if (txq->axq_depth) { | |
2123 | if (txq->axq_tx_inprogress) { | |
2124 | needreset = true; | |
2125 | spin_unlock_bh(&txq->axq_lock); | |
2126 | break; | |
2127 | } else { | |
2128 | txq->axq_tx_inprogress = true; | |
2129 | } | |
2130 | } | |
2131 | spin_unlock_bh(&txq->axq_lock); | |
2132 | } | |
2133 | ||
2134 | if (needreset) { | |
c46917bb LR |
2135 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2136 | "tx hung, resetting the chip\n"); | |
332c5566 | 2137 | ath9k_ps_wakeup(sc); |
164ace38 | 2138 | ath_reset(sc, false); |
332c5566 | 2139 | ath9k_ps_restore(sc); |
164ace38 SB |
2140 | } |
2141 | ||
42935eca | 2142 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2143 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2144 | } | |
2145 | ||
2146 | ||
f078f209 | 2147 | |
e8324357 | 2148 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2149 | { |
e8324357 S |
2150 | int i; |
2151 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2152 | |
e8324357 | 2153 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2154 | |
e8324357 S |
2155 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2156 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2157 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2158 | } |
2159 | } | |
2160 | ||
e8324357 S |
2161 | /*****************/ |
2162 | /* Init, Cleanup */ | |
2163 | /*****************/ | |
f078f209 | 2164 | |
e8324357 | 2165 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2166 | { |
c46917bb | 2167 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2168 | int error = 0; |
f078f209 | 2169 | |
797fe5cb | 2170 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2171 | |
797fe5cb S |
2172 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2173 | "tx", nbufs, 1); | |
2174 | if (error != 0) { | |
c46917bb LR |
2175 | ath_print(common, ATH_DBG_FATAL, |
2176 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2177 | goto err; |
2178 | } | |
f078f209 | 2179 | |
797fe5cb S |
2180 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2181 | "beacon", ATH_BCBUF, 1); | |
2182 | if (error != 0) { | |
c46917bb LR |
2183 | ath_print(common, ATH_DBG_FATAL, |
2184 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2185 | goto err; |
2186 | } | |
f078f209 | 2187 | |
164ace38 SB |
2188 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2189 | ||
797fe5cb | 2190 | err: |
e8324357 S |
2191 | if (error != 0) |
2192 | ath_tx_cleanup(sc); | |
f078f209 | 2193 | |
e8324357 | 2194 | return error; |
f078f209 LR |
2195 | } |
2196 | ||
797fe5cb | 2197 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2198 | { |
2199 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2200 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2201 | ||
2202 | if (sc->tx.txdma.dd_desc_len != 0) | |
2203 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2204 | } |
f078f209 LR |
2205 | |
2206 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2207 | { | |
c5170163 S |
2208 | struct ath_atx_tid *tid; |
2209 | struct ath_atx_ac *ac; | |
2210 | int tidno, acno; | |
f078f209 | 2211 | |
8ee5afbc | 2212 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2213 | tidno < WME_NUM_TID; |
2214 | tidno++, tid++) { | |
2215 | tid->an = an; | |
2216 | tid->tidno = tidno; | |
2217 | tid->seq_start = tid->seq_next = 0; | |
2218 | tid->baw_size = WME_MAX_BA; | |
2219 | tid->baw_head = tid->baw_tail = 0; | |
2220 | tid->sched = false; | |
e8324357 | 2221 | tid->paused = false; |
a37c2c79 | 2222 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2223 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2224 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2225 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2226 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2227 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2228 | } |
f078f209 | 2229 | |
8ee5afbc | 2230 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2231 | acno < WME_NUM_AC; acno++, ac++) { |
2232 | ac->sched = false; | |
2233 | INIT_LIST_HEAD(&ac->tid_q); | |
2234 | ||
2235 | switch (acno) { | |
2236 | case WME_AC_BE: | |
2237 | ac->qnum = ath_tx_get_qnum(sc, | |
2238 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2239 | break; | |
2240 | case WME_AC_BK: | |
2241 | ac->qnum = ath_tx_get_qnum(sc, | |
2242 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2243 | break; | |
2244 | case WME_AC_VI: | |
2245 | ac->qnum = ath_tx_get_qnum(sc, | |
2246 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2247 | break; | |
2248 | case WME_AC_VO: | |
2249 | ac->qnum = ath_tx_get_qnum(sc, | |
2250 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2251 | break; | |
f078f209 LR |
2252 | } |
2253 | } | |
2254 | } | |
2255 | ||
b5aa9bf9 | 2256 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2257 | { |
2258 | int i; | |
2259 | struct ath_atx_ac *ac, *ac_tmp; | |
2260 | struct ath_atx_tid *tid, *tid_tmp; | |
2261 | struct ath_txq *txq; | |
e8324357 | 2262 | |
f078f209 LR |
2263 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2264 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2265 | txq = &sc->tx.txq[i]; |
f078f209 | 2266 | |
b5aa9bf9 | 2267 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2268 | |
2269 | list_for_each_entry_safe(ac, | |
2270 | ac_tmp, &txq->axq_acq, list) { | |
2271 | tid = list_first_entry(&ac->tid_q, | |
2272 | struct ath_atx_tid, list); | |
2273 | if (tid && tid->an != an) | |
2274 | continue; | |
2275 | list_del(&ac->list); | |
2276 | ac->sched = false; | |
2277 | ||
2278 | list_for_each_entry_safe(tid, | |
2279 | tid_tmp, &ac->tid_q, list) { | |
2280 | list_del(&tid->list); | |
2281 | tid->sched = false; | |
b5aa9bf9 | 2282 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2283 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2284 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2285 | } |
2286 | } | |
2287 | ||
b5aa9bf9 | 2288 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2289 | } |
2290 | } | |
2291 | } |