Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 LR |
18 | |
19 | #define BITS_PER_BYTE 8 | |
20 | #define OFDM_PLCP_BITS 22 | |
21 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
22 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
23 | #define L_STF 8 | |
24 | #define L_LTF 8 | |
25 | #define L_SIG 4 | |
26 | #define HT_SIG 8 | |
27 | #define HT_STF 4 | |
28 | #define HT_LTF(_ns) (4 * (_ns)) | |
29 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
30 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
31 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
32 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
33 | ||
34 | #define OFDM_SIFS_TIME 16 | |
35 | ||
36 | static u32 bits_per_symbol[][2] = { | |
37 | /* 20MHz 40MHz */ | |
38 | { 26, 54 }, /* 0: BPSK */ | |
39 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
40 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
41 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
42 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
43 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
44 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
45 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
46 | { 52, 108 }, /* 8: BPSK */ | |
47 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
48 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
49 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
50 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
51 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
52 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
53 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
54 | }; | |
55 | ||
56 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
57 | ||
c37452b0 S |
58 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
59 | struct ath_atx_tid *tid, | |
60 | struct list_head *bf_head); | |
e8324357 | 61 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 62 | struct ath_txq *txq, |
e8324357 S |
63 | struct list_head *bf_q, |
64 | int txok, int sendbar); | |
102e0572 | 65 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
66 | struct list_head *head); |
67 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 VT |
68 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
69 | int txok); | |
70 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, | |
8a92e2ee | 71 | int nbad, int txok, bool update_rc); |
c4288390 | 72 | |
e8324357 S |
73 | /*********************/ |
74 | /* Aggregation logic */ | |
75 | /*********************/ | |
f078f209 | 76 | |
e8324357 | 77 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 78 | { |
e8324357 | 79 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 80 | |
e8324357 S |
81 | if (tid->paused) |
82 | return; | |
ff37e337 | 83 | |
e8324357 S |
84 | if (tid->sched) |
85 | return; | |
ff37e337 | 86 | |
e8324357 S |
87 | tid->sched = true; |
88 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 89 | |
e8324357 S |
90 | if (ac->sched) |
91 | return; | |
f078f209 | 92 | |
e8324357 S |
93 | ac->sched = true; |
94 | list_add_tail(&ac->list, &txq->axq_acq); | |
95 | } | |
f078f209 | 96 | |
e8324357 S |
97 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
98 | { | |
99 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 100 | |
e8324357 S |
101 | spin_lock_bh(&txq->axq_lock); |
102 | tid->paused++; | |
103 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
104 | } |
105 | ||
e8324357 | 106 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 107 | { |
e8324357 | 108 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 109 | |
9680e8a3 | 110 | BUG_ON(tid->paused <= 0); |
e8324357 | 111 | spin_lock_bh(&txq->axq_lock); |
f078f209 | 112 | |
e8324357 | 113 | tid->paused--; |
f078f209 | 114 | |
e8324357 S |
115 | if (tid->paused > 0) |
116 | goto unlock; | |
f078f209 | 117 | |
e8324357 S |
118 | if (list_empty(&tid->buf_q)) |
119 | goto unlock; | |
f078f209 | 120 | |
e8324357 S |
121 | ath_tx_queue_tid(txq, tid); |
122 | ath_txq_schedule(sc, txq); | |
123 | unlock: | |
124 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 125 | } |
f078f209 | 126 | |
e8324357 | 127 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 128 | { |
e8324357 S |
129 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
130 | struct ath_buf *bf; | |
131 | struct list_head bf_head; | |
132 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 133 | |
9680e8a3 | 134 | BUG_ON(tid->paused <= 0); |
e8324357 | 135 | spin_lock_bh(&txq->axq_lock); |
e6a9854b | 136 | |
e8324357 | 137 | tid->paused--; |
f078f209 | 138 | |
e8324357 S |
139 | if (tid->paused > 0) { |
140 | spin_unlock_bh(&txq->axq_lock); | |
141 | return; | |
142 | } | |
f078f209 | 143 | |
e8324357 S |
144 | while (!list_empty(&tid->buf_q)) { |
145 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
9680e8a3 | 146 | BUG_ON(bf_isretried(bf)); |
d43f3015 | 147 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 148 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 149 | } |
f078f209 | 150 | |
e8324357 | 151 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 152 | } |
f078f209 | 153 | |
e8324357 S |
154 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
155 | int seqno) | |
528f0c6b | 156 | { |
e8324357 | 157 | int index, cindex; |
f078f209 | 158 | |
e8324357 S |
159 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
160 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 161 | |
e8324357 | 162 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 163 | |
e8324357 S |
164 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
165 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
166 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
167 | } | |
528f0c6b | 168 | } |
f078f209 | 169 | |
e8324357 S |
170 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
171 | struct ath_buf *bf) | |
528f0c6b | 172 | { |
e8324357 | 173 | int index, cindex; |
528f0c6b | 174 | |
e8324357 S |
175 | if (bf_isretried(bf)) |
176 | return; | |
528f0c6b | 177 | |
e8324357 S |
178 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
179 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 180 | |
9680e8a3 | 181 | BUG_ON(tid->tx_buf[cindex] != NULL); |
e8324357 | 182 | tid->tx_buf[cindex] = bf; |
f078f209 | 183 | |
e8324357 S |
184 | if (index >= ((tid->baw_tail - tid->baw_head) & |
185 | (ATH_TID_MAX_BUFS - 1))) { | |
186 | tid->baw_tail = cindex; | |
187 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 188 | } |
f078f209 LR |
189 | } |
190 | ||
191 | /* | |
e8324357 S |
192 | * TODO: For frame(s) that are in the retry state, we will reuse the |
193 | * sequence number(s) without setting the retry bit. The | |
194 | * alternative is to give up on these and BAR the receiver's window | |
195 | * forward. | |
f078f209 | 196 | */ |
e8324357 S |
197 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
198 | struct ath_atx_tid *tid) | |
f078f209 | 199 | |
f078f209 | 200 | { |
e8324357 S |
201 | struct ath_buf *bf; |
202 | struct list_head bf_head; | |
203 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 204 | |
e8324357 S |
205 | for (;;) { |
206 | if (list_empty(&tid->buf_q)) | |
207 | break; | |
f078f209 | 208 | |
d43f3015 S |
209 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
210 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 211 | |
e8324357 S |
212 | if (bf_isretried(bf)) |
213 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 214 | |
e8324357 | 215 | spin_unlock(&txq->axq_lock); |
fec247c0 | 216 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
e8324357 S |
217 | spin_lock(&txq->axq_lock); |
218 | } | |
f078f209 | 219 | |
e8324357 S |
220 | tid->seq_next = tid->seq_start; |
221 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
222 | } |
223 | ||
fec247c0 S |
224 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
225 | struct ath_buf *bf) | |
f078f209 | 226 | { |
e8324357 S |
227 | struct sk_buff *skb; |
228 | struct ieee80211_hdr *hdr; | |
f078f209 | 229 | |
e8324357 S |
230 | bf->bf_state.bf_type |= BUF_RETRY; |
231 | bf->bf_retries++; | |
fec247c0 | 232 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 233 | |
e8324357 S |
234 | skb = bf->bf_mpdu; |
235 | hdr = (struct ieee80211_hdr *)skb->data; | |
236 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
237 | } |
238 | ||
d43f3015 S |
239 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
240 | { | |
241 | struct ath_buf *tbf; | |
242 | ||
243 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
244 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
245 | spin_unlock_bh(&sc->tx.txbuflock); | |
246 | return NULL; | |
247 | } | |
d43f3015 S |
248 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
249 | list_del(&tbf->list); | |
250 | spin_unlock_bh(&sc->tx.txbuflock); | |
251 | ||
252 | ATH_TXBUF_RESET(tbf); | |
253 | ||
254 | tbf->bf_mpdu = bf->bf_mpdu; | |
255 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
256 | *(tbf->bf_desc) = *(bf->bf_desc); | |
257 | tbf->bf_state = bf->bf_state; | |
258 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
259 | ||
260 | return tbf; | |
261 | } | |
262 | ||
263 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
264 | struct ath_buf *bf, struct list_head *bf_q, | |
265 | int txok) | |
f078f209 | 266 | { |
e8324357 S |
267 | struct ath_node *an = NULL; |
268 | struct sk_buff *skb; | |
1286ec6d | 269 | struct ieee80211_sta *sta; |
76d5a9e8 | 270 | struct ieee80211_hw *hw; |
1286ec6d | 271 | struct ieee80211_hdr *hdr; |
76d5a9e8 LR |
272 | struct ieee80211_tx_info *tx_info; |
273 | struct ath_tx_info_priv *tx_info_priv; | |
e8324357 | 274 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 275 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
f078f209 | 276 | struct ath_desc *ds = bf_last->bf_desc; |
e8324357 | 277 | struct list_head bf_head, bf_pending; |
0934af23 | 278 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 279 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
280 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
281 | bool rc_update = true; | |
f078f209 | 282 | |
a22be22a | 283 | skb = bf->bf_mpdu; |
1286ec6d S |
284 | hdr = (struct ieee80211_hdr *)skb->data; |
285 | ||
76d5a9e8 LR |
286 | tx_info = IEEE80211_SKB_CB(skb); |
287 | tx_info_priv = (struct ath_tx_info_priv *) tx_info->rate_driver_data[0]; | |
288 | hw = tx_info_priv->aphy->hw; | |
289 | ||
1286ec6d | 290 | rcu_read_lock(); |
f078f209 | 291 | |
5ed176e1 | 292 | /* XXX: use ieee80211_find_sta! */ |
76d5a9e8 | 293 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr1); |
1286ec6d S |
294 | if (!sta) { |
295 | rcu_read_unlock(); | |
296 | return; | |
f078f209 LR |
297 | } |
298 | ||
1286ec6d S |
299 | an = (struct ath_node *)sta->drv_priv; |
300 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
301 | ||
e8324357 | 302 | isaggr = bf_isaggr(bf); |
d43f3015 | 303 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 304 | |
d43f3015 S |
305 | if (isaggr && txok) { |
306 | if (ATH_DS_TX_BA(ds)) { | |
307 | seq_st = ATH_DS_BA_SEQ(ds); | |
308 | memcpy(ba, ATH_DS_BA_BITMAP(ds), | |
309 | WME_BA_BMP_SIZE >> 3); | |
e8324357 | 310 | } else { |
d43f3015 S |
311 | /* |
312 | * AR5416 can become deaf/mute when BA | |
313 | * issue happens. Chip needs to be reset. | |
314 | * But AP code may have sychronization issues | |
315 | * when perform internal reset in this routine. | |
316 | * Only enable reset in STA mode for now. | |
317 | */ | |
2660b81a | 318 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 319 | needreset = 1; |
e8324357 | 320 | } |
f078f209 LR |
321 | } |
322 | ||
e8324357 S |
323 | INIT_LIST_HEAD(&bf_pending); |
324 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 325 | |
0934af23 | 326 | nbad = ath_tx_num_badfrms(sc, bf, txok); |
e8324357 S |
327 | while (bf) { |
328 | txfail = txpending = 0; | |
329 | bf_next = bf->bf_next; | |
f078f209 | 330 | |
e8324357 S |
331 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
332 | /* transmit completion, subframe is | |
333 | * acked by block ack */ | |
0934af23 | 334 | acked_cnt++; |
e8324357 S |
335 | } else if (!isaggr && txok) { |
336 | /* transmit completion */ | |
0934af23 | 337 | acked_cnt++; |
e8324357 | 338 | } else { |
e8324357 S |
339 | if (!(tid->state & AGGR_CLEANUP) && |
340 | ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) { | |
341 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { | |
fec247c0 | 342 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
343 | txpending = 1; |
344 | } else { | |
345 | bf->bf_state.bf_type |= BUF_XRETRY; | |
346 | txfail = 1; | |
347 | sendbar = 1; | |
0934af23 | 348 | txfail_cnt++; |
e8324357 S |
349 | } |
350 | } else { | |
351 | /* | |
352 | * cleanup in progress, just fail | |
353 | * the un-acked sub-frames | |
354 | */ | |
355 | txfail = 1; | |
356 | } | |
357 | } | |
f078f209 | 358 | |
e8324357 | 359 | if (bf_next == NULL) { |
cbfe89c6 VT |
360 | /* |
361 | * Make sure the last desc is reclaimed if it | |
362 | * not a holding desc. | |
363 | */ | |
364 | if (!bf_last->bf_stale) | |
365 | list_move_tail(&bf->list, &bf_head); | |
366 | else | |
367 | INIT_LIST_HEAD(&bf_head); | |
e8324357 | 368 | } else { |
9680e8a3 | 369 | BUG_ON(list_empty(bf_q)); |
d43f3015 | 370 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 371 | } |
f078f209 | 372 | |
e8324357 S |
373 | if (!txpending) { |
374 | /* | |
375 | * complete the acked-ones/xretried ones; update | |
376 | * block-ack window | |
377 | */ | |
378 | spin_lock_bh(&txq->axq_lock); | |
379 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
380 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 381 | |
8a92e2ee VT |
382 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
383 | ath_tx_rc_status(bf, ds, nbad, txok, true); | |
384 | rc_update = false; | |
385 | } else { | |
386 | ath_tx_rc_status(bf, ds, nbad, txok, false); | |
387 | } | |
388 | ||
fec247c0 | 389 | ath_tx_complete_buf(sc, bf, txq, &bf_head, !txfail, sendbar); |
e8324357 | 390 | } else { |
d43f3015 | 391 | /* retry the un-acked ones */ |
a119cc49 | 392 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 393 | struct ath_buf *tbf; |
f078f209 | 394 | |
d43f3015 | 395 | tbf = ath_clone_txbuf(sc, bf_last); |
c41d92dc VT |
396 | /* |
397 | * Update tx baw and complete the frame with | |
398 | * failed status if we run out of tx buf | |
399 | */ | |
400 | if (!tbf) { | |
401 | spin_lock_bh(&txq->axq_lock); | |
402 | ath_tx_update_baw(sc, tid, | |
403 | bf->bf_seqno); | |
404 | spin_unlock_bh(&txq->axq_lock); | |
405 | ||
406 | bf->bf_state.bf_type |= BUF_XRETRY; | |
407 | ath_tx_rc_status(bf, ds, nbad, | |
408 | 0, false); | |
fec247c0 S |
409 | ath_tx_complete_buf(sc, bf, txq, |
410 | &bf_head, 0, 0); | |
8a46097a | 411 | break; |
c41d92dc VT |
412 | } |
413 | ||
d43f3015 | 414 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); |
e8324357 S |
415 | list_add_tail(&tbf->list, &bf_head); |
416 | } else { | |
417 | /* | |
418 | * Clear descriptor status words for | |
419 | * software retry | |
420 | */ | |
d43f3015 | 421 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
422 | } |
423 | ||
424 | /* | |
425 | * Put this buffer to the temporary pending | |
426 | * queue to retain ordering | |
427 | */ | |
428 | list_splice_tail_init(&bf_head, &bf_pending); | |
429 | } | |
430 | ||
431 | bf = bf_next; | |
f078f209 | 432 | } |
f078f209 | 433 | |
e8324357 | 434 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
435 | if (tid->baw_head == tid->baw_tail) { |
436 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 437 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 438 | |
e8324357 S |
439 | /* send buffered frames as singles */ |
440 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 441 | } |
1286ec6d | 442 | rcu_read_unlock(); |
e8324357 S |
443 | return; |
444 | } | |
f078f209 | 445 | |
d43f3015 | 446 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
447 | if (!list_empty(&bf_pending)) { |
448 | spin_lock_bh(&txq->axq_lock); | |
449 | list_splice(&bf_pending, &tid->buf_q); | |
450 | ath_tx_queue_tid(txq, tid); | |
451 | spin_unlock_bh(&txq->axq_lock); | |
452 | } | |
102e0572 | 453 | |
1286ec6d S |
454 | rcu_read_unlock(); |
455 | ||
e8324357 S |
456 | if (needreset) |
457 | ath_reset(sc, false); | |
e8324357 | 458 | } |
f078f209 | 459 | |
e8324357 S |
460 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
461 | struct ath_atx_tid *tid) | |
f078f209 | 462 | { |
4f0fc7c3 | 463 | const struct ath_rate_table *rate_table = sc->cur_rate_table; |
528f0c6b S |
464 | struct sk_buff *skb; |
465 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 466 | struct ieee80211_tx_rate *rates; |
e8324357 | 467 | struct ath_tx_info_priv *tx_info_priv; |
d43f3015 | 468 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 469 | u16 aggr_limit, legacy = 0; |
e8324357 | 470 | int i; |
528f0c6b | 471 | |
a22be22a | 472 | skb = bf->bf_mpdu; |
528f0c6b | 473 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 474 | rates = tx_info->control.rates; |
d43f3015 | 475 | tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0]; |
528f0c6b | 476 | |
e8324357 S |
477 | /* |
478 | * Find the lowest frame length among the rate series that will have a | |
479 | * 4ms transmit duration. | |
480 | * TODO - TXOP limit needs to be considered. | |
481 | */ | |
482 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 483 | |
e8324357 S |
484 | for (i = 0; i < 4; i++) { |
485 | if (rates[i].count) { | |
486 | if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) { | |
487 | legacy = 1; | |
488 | break; | |
489 | } | |
490 | ||
d43f3015 S |
491 | frmlen = rate_table->info[rates[i].idx].max_4ms_framelen; |
492 | max_4ms_framelen = min(max_4ms_framelen, frmlen); | |
f078f209 LR |
493 | } |
494 | } | |
e63835b0 | 495 | |
f078f209 | 496 | /* |
e8324357 S |
497 | * limit aggregate size by the minimum rate if rate selected is |
498 | * not a probe rate, if rate selected is a probe rate then | |
499 | * avoid aggregation of this packet. | |
f078f209 | 500 | */ |
e8324357 S |
501 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
502 | return 0; | |
f078f209 | 503 | |
1773912b VT |
504 | if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) |
505 | aggr_limit = min((max_4ms_framelen * 3) / 8, | |
506 | (u32)ATH_AMPDU_LIMIT_MAX); | |
507 | else | |
508 | aggr_limit = min(max_4ms_framelen, | |
509 | (u32)ATH_AMPDU_LIMIT_MAX); | |
f078f209 | 510 | |
e8324357 S |
511 | /* |
512 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
513 | * The IE, however can hold upto 65536, which shows up here | |
514 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 515 | */ |
4ef70841 S |
516 | if (tid->an->maxampdu) |
517 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 518 | |
e8324357 S |
519 | return aggr_limit; |
520 | } | |
f078f209 | 521 | |
e8324357 | 522 | /* |
d43f3015 | 523 | * Returns the number of delimiters to be added to |
e8324357 | 524 | * meet the minimum required mpdudensity. |
e8324357 S |
525 | */ |
526 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
527 | struct ath_buf *bf, u16 frmlen) | |
528 | { | |
4f0fc7c3 | 529 | const struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
530 | struct sk_buff *skb = bf->bf_mpdu; |
531 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 532 | u32 nsymbits, nsymbols; |
e8324357 S |
533 | u16 minlen; |
534 | u8 rc, flags, rix; | |
535 | int width, half_gi, ndelim, mindelim; | |
536 | ||
537 | /* Select standard number of delimiters based on frame length alone */ | |
538 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
539 | |
540 | /* | |
e8324357 S |
541 | * If encryption enabled, hardware requires some more padding between |
542 | * subframes. | |
543 | * TODO - this could be improved to be dependent on the rate. | |
544 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 545 | */ |
e8324357 S |
546 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
547 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 548 | |
e8324357 S |
549 | /* |
550 | * Convert desired mpdu density from microeconds to bytes based | |
551 | * on highest rate in rate series (i.e. first rate) to determine | |
552 | * required minimum length for subframe. Take into account | |
553 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 554 | * |
e8324357 S |
555 | * If there is no mpdu density restriction, no further calculation |
556 | * is needed. | |
557 | */ | |
4ef70841 S |
558 | |
559 | if (tid->an->mpdudensity == 0) | |
e8324357 | 560 | return ndelim; |
f078f209 | 561 | |
e8324357 S |
562 | rix = tx_info->control.rates[0].idx; |
563 | flags = tx_info->control.rates[0].flags; | |
564 | rc = rt->info[rix].ratecode; | |
565 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; | |
566 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 567 | |
e8324357 | 568 | if (half_gi) |
4ef70841 | 569 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 570 | else |
4ef70841 | 571 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 572 | |
e8324357 S |
573 | if (nsymbols == 0) |
574 | nsymbols = 1; | |
f078f209 | 575 | |
e8324357 S |
576 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; |
577 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; | |
f078f209 | 578 | |
e8324357 | 579 | if (frmlen < minlen) { |
e8324357 S |
580 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
581 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
582 | } |
583 | ||
e8324357 | 584 | return ndelim; |
f078f209 LR |
585 | } |
586 | ||
e8324357 | 587 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 588 | struct ath_txq *txq, |
d43f3015 S |
589 | struct ath_atx_tid *tid, |
590 | struct list_head *bf_q) | |
f078f209 | 591 | { |
e8324357 | 592 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
593 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
594 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
595 | u16 aggr_limit = 0, al = 0, bpad = 0, |
596 | al_delta, h_baw = tid->baw_size / 2; | |
597 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 598 | |
e8324357 | 599 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 600 | |
e8324357 S |
601 | do { |
602 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 603 | |
d43f3015 | 604 | /* do not step over block-ack window */ |
e8324357 S |
605 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
606 | status = ATH_AGGR_BAW_CLOSED; | |
607 | break; | |
608 | } | |
f078f209 | 609 | |
e8324357 S |
610 | if (!rl) { |
611 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
612 | rl = 1; | |
613 | } | |
f078f209 | 614 | |
d43f3015 | 615 | /* do not exceed aggregation limit */ |
e8324357 | 616 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 617 | |
d43f3015 S |
618 | if (nframes && |
619 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
620 | status = ATH_AGGR_LIMITED; |
621 | break; | |
622 | } | |
f078f209 | 623 | |
d43f3015 S |
624 | /* do not exceed subframe limit */ |
625 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
626 | status = ATH_AGGR_LIMITED; |
627 | break; | |
628 | } | |
d43f3015 | 629 | nframes++; |
f078f209 | 630 | |
d43f3015 | 631 | /* add padding for previous frame to aggregation length */ |
e8324357 | 632 | al += bpad + al_delta; |
f078f209 | 633 | |
e8324357 S |
634 | /* |
635 | * Get the delimiters needed to meet the MPDU | |
636 | * density for this node. | |
637 | */ | |
638 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 639 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 640 | |
e8324357 | 641 | bf->bf_next = NULL; |
d43f3015 | 642 | bf->bf_desc->ds_link = 0; |
f078f209 | 643 | |
d43f3015 | 644 | /* link buffers of this frame to the aggregate */ |
e8324357 | 645 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
646 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
647 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
648 | if (bf_prev) { |
649 | bf_prev->bf_next = bf; | |
d43f3015 | 650 | bf_prev->bf_desc->ds_link = bf->bf_daddr; |
e8324357 S |
651 | } |
652 | bf_prev = bf; | |
fec247c0 | 653 | |
e8324357 | 654 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 655 | |
e8324357 S |
656 | bf_first->bf_al = al; |
657 | bf_first->bf_nframes = nframes; | |
d43f3015 | 658 | |
e8324357 S |
659 | return status; |
660 | #undef PADBYTES | |
661 | } | |
f078f209 | 662 | |
e8324357 S |
663 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
664 | struct ath_atx_tid *tid) | |
665 | { | |
d43f3015 | 666 | struct ath_buf *bf; |
e8324357 S |
667 | enum ATH_AGGR_STATUS status; |
668 | struct list_head bf_q; | |
f078f209 | 669 | |
e8324357 S |
670 | do { |
671 | if (list_empty(&tid->buf_q)) | |
672 | return; | |
f078f209 | 673 | |
e8324357 S |
674 | INIT_LIST_HEAD(&bf_q); |
675 | ||
fec247c0 | 676 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 677 | |
f078f209 | 678 | /* |
d43f3015 S |
679 | * no frames picked up to be aggregated; |
680 | * block-ack window is not open. | |
f078f209 | 681 | */ |
e8324357 S |
682 | if (list_empty(&bf_q)) |
683 | break; | |
f078f209 | 684 | |
e8324357 | 685 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 686 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 687 | |
d43f3015 | 688 | /* if only one frame, send as non-aggregate */ |
e8324357 | 689 | if (bf->bf_nframes == 1) { |
e8324357 | 690 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 691 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
692 | ath_buf_set_rate(sc, bf); |
693 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
694 | continue; | |
695 | } | |
f078f209 | 696 | |
d43f3015 | 697 | /* setup first desc of aggregate */ |
e8324357 S |
698 | bf->bf_state.bf_type |= BUF_AGGR; |
699 | ath_buf_set_rate(sc, bf); | |
700 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 701 | |
d43f3015 S |
702 | /* anchor last desc of aggregate */ |
703 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 704 | |
e8324357 | 705 | txq->axq_aggr_depth++; |
e8324357 | 706 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 707 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 708 | |
e8324357 S |
709 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
710 | status != ATH_AGGR_BAW_CLOSED); | |
711 | } | |
712 | ||
f83da965 S |
713 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
714 | u16 tid, u16 *ssn) | |
e8324357 S |
715 | { |
716 | struct ath_atx_tid *txtid; | |
717 | struct ath_node *an; | |
718 | ||
719 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
720 | txtid = ATH_AN_2_TID(an, tid); |
721 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
722 | ath_tx_pause_tid(sc, txtid); | |
723 | *ssn = txtid->seq_start; | |
e8324357 | 724 | } |
f078f209 | 725 | |
f83da965 | 726 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
727 | { |
728 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
729 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
730 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
731 | struct ath_buf *bf; | |
732 | struct list_head bf_head; | |
733 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 734 | |
e8324357 | 735 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 736 | return; |
f078f209 | 737 | |
e8324357 | 738 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 739 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 740 | return; |
e8324357 | 741 | } |
f078f209 | 742 | |
e8324357 S |
743 | ath_tx_pause_tid(sc, txtid); |
744 | ||
745 | /* drop all software retried frames and mark this TID */ | |
746 | spin_lock_bh(&txq->axq_lock); | |
747 | while (!list_empty(&txtid->buf_q)) { | |
748 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
749 | if (!bf_isretried(bf)) { | |
750 | /* | |
751 | * NB: it's based on the assumption that | |
752 | * software retried frame will always stay | |
753 | * at the head of software queue. | |
754 | */ | |
755 | break; | |
756 | } | |
d43f3015 | 757 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 758 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
fec247c0 | 759 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 | 760 | } |
d43f3015 | 761 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 762 | |
e8324357 | 763 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
764 | txtid->state |= AGGR_CLEANUP; |
765 | } else { | |
766 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 767 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 768 | } |
e8324357 | 769 | } |
f078f209 | 770 | |
e8324357 S |
771 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
772 | { | |
773 | struct ath_atx_tid *txtid; | |
774 | struct ath_node *an; | |
775 | ||
776 | an = (struct ath_node *)sta->drv_priv; | |
777 | ||
778 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
779 | txtid = ATH_AN_2_TID(an, tid); | |
780 | txtid->baw_size = | |
781 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
782 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
783 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
784 | ath_tx_resume_tid(sc, txtid); | |
785 | } | |
f078f209 LR |
786 | } |
787 | ||
e8324357 | 788 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 789 | { |
e8324357 | 790 | struct ath_atx_tid *txtid; |
c4288390 | 791 | |
e8324357 S |
792 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
793 | return false; | |
c4288390 | 794 | |
e8324357 S |
795 | txtid = ATH_AN_2_TID(an, tidno); |
796 | ||
c3d8f02e | 797 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 798 | return true; |
e8324357 | 799 | return false; |
c4288390 S |
800 | } |
801 | ||
e8324357 S |
802 | /********************/ |
803 | /* Queue Management */ | |
804 | /********************/ | |
f078f209 | 805 | |
e8324357 S |
806 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
807 | struct ath_txq *txq) | |
f078f209 | 808 | { |
e8324357 S |
809 | struct ath_atx_ac *ac, *ac_tmp; |
810 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 811 | |
e8324357 S |
812 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
813 | list_del(&ac->list); | |
814 | ac->sched = false; | |
815 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
816 | list_del(&tid->list); | |
817 | tid->sched = false; | |
818 | ath_tid_drain(sc, txq, tid); | |
819 | } | |
f078f209 LR |
820 | } |
821 | } | |
822 | ||
e8324357 | 823 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 824 | { |
cbe61d8a | 825 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 826 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 S |
827 | struct ath9k_tx_queue_info qi; |
828 | int qnum; | |
f078f209 | 829 | |
e8324357 S |
830 | memset(&qi, 0, sizeof(qi)); |
831 | qi.tqi_subtype = subtype; | |
832 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
833 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
834 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
835 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
836 | |
837 | /* | |
e8324357 S |
838 | * Enable interrupts only for EOL and DESC conditions. |
839 | * We mark tx descriptors to receive a DESC interrupt | |
840 | * when a tx queue gets deep; otherwise waiting for the | |
841 | * EOL to reap descriptors. Note that this is done to | |
842 | * reduce interrupt load and this only defers reaping | |
843 | * descriptors, never transmitting frames. Aside from | |
844 | * reducing interrupts this also permits more concurrency. | |
845 | * The only potential downside is if the tx queue backs | |
846 | * up in which case the top half of the kernel may backup | |
847 | * due to a lack of tx descriptors. | |
848 | * | |
849 | * The UAPSD queue is an exception, since we take a desc- | |
850 | * based intr on the EOSP frames. | |
f078f209 | 851 | */ |
e8324357 S |
852 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
853 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
854 | else | |
855 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
856 | TXQ_FLAG_TXDESCINT_ENABLE; | |
857 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
858 | if (qnum == -1) { | |
f078f209 | 859 | /* |
e8324357 S |
860 | * NB: don't print a message, this happens |
861 | * normally on parts with too few tx queues | |
f078f209 | 862 | */ |
e8324357 | 863 | return NULL; |
f078f209 | 864 | } |
e8324357 | 865 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
c46917bb LR |
866 | ath_print(common, ATH_DBG_FATAL, |
867 | "qnum %u out of range, max %u!\n", | |
868 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
e8324357 S |
869 | ath9k_hw_releasetxqueue(ah, qnum); |
870 | return NULL; | |
871 | } | |
872 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
873 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 874 | |
e8324357 S |
875 | txq->axq_qnum = qnum; |
876 | txq->axq_link = NULL; | |
877 | INIT_LIST_HEAD(&txq->axq_q); | |
878 | INIT_LIST_HEAD(&txq->axq_acq); | |
879 | spin_lock_init(&txq->axq_lock); | |
880 | txq->axq_depth = 0; | |
881 | txq->axq_aggr_depth = 0; | |
e8324357 | 882 | txq->axq_linkbuf = NULL; |
164ace38 | 883 | txq->axq_tx_inprogress = false; |
e8324357 S |
884 | sc->tx.txqsetup |= 1<<qnum; |
885 | } | |
886 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
887 | } |
888 | ||
1773912b | 889 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 890 | { |
e8324357 | 891 | int qnum; |
f078f209 | 892 | |
e8324357 S |
893 | switch (qtype) { |
894 | case ATH9K_TX_QUEUE_DATA: | |
895 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
c46917bb LR |
896 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
897 | "HAL AC %u out of range, max %zu!\n", | |
898 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
e8324357 S |
899 | return -1; |
900 | } | |
901 | qnum = sc->tx.hwq_map[haltype]; | |
902 | break; | |
903 | case ATH9K_TX_QUEUE_BEACON: | |
904 | qnum = sc->beacon.beaconq; | |
905 | break; | |
906 | case ATH9K_TX_QUEUE_CAB: | |
907 | qnum = sc->beacon.cabq->axq_qnum; | |
908 | break; | |
909 | default: | |
910 | qnum = -1; | |
911 | } | |
912 | return qnum; | |
913 | } | |
f078f209 | 914 | |
e8324357 S |
915 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
916 | { | |
917 | struct ath_txq *txq = NULL; | |
918 | int qnum; | |
f078f209 | 919 | |
e8324357 S |
920 | qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc); |
921 | txq = &sc->tx.txq[qnum]; | |
f078f209 | 922 | |
e8324357 S |
923 | spin_lock_bh(&txq->axq_lock); |
924 | ||
925 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c46917bb LR |
926 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT, |
927 | "TX queue: %d is full, depth: %d\n", | |
928 | qnum, txq->axq_depth); | |
e8324357 S |
929 | ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); |
930 | txq->stopped = 1; | |
931 | spin_unlock_bh(&txq->axq_lock); | |
932 | return NULL; | |
f078f209 LR |
933 | } |
934 | ||
e8324357 S |
935 | spin_unlock_bh(&txq->axq_lock); |
936 | ||
937 | return txq; | |
938 | } | |
939 | ||
940 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
941 | struct ath9k_tx_queue_info *qinfo) | |
942 | { | |
cbe61d8a | 943 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
944 | int error = 0; |
945 | struct ath9k_tx_queue_info qi; | |
946 | ||
947 | if (qnum == sc->beacon.beaconq) { | |
948 | /* | |
949 | * XXX: for beacon queue, we just save the parameter. | |
950 | * It will be picked up by ath_beaconq_config when | |
951 | * it's necessary. | |
952 | */ | |
953 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 954 | return 0; |
e8324357 | 955 | } |
f078f209 | 956 | |
9680e8a3 | 957 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
958 | |
959 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
960 | qi.tqi_aifs = qinfo->tqi_aifs; | |
961 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
962 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
963 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
964 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
965 | ||
966 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
c46917bb LR |
967 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
968 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
969 | error = -EIO; |
970 | } else { | |
971 | ath9k_hw_resettxqueue(ah, qnum); | |
972 | } | |
973 | ||
974 | return error; | |
975 | } | |
976 | ||
977 | int ath_cabq_update(struct ath_softc *sc) | |
978 | { | |
979 | struct ath9k_tx_queue_info qi; | |
980 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 981 | |
e8324357 | 982 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 983 | /* |
e8324357 | 984 | * Ensure the readytime % is within the bounds. |
f078f209 | 985 | */ |
17d7904d S |
986 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
987 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
988 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
989 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 990 | |
57c4d7b4 | 991 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 992 | sc->config.cabqReadytime) / 100; |
e8324357 S |
993 | ath_txq_update(sc, qnum, &qi); |
994 | ||
995 | return 0; | |
f078f209 LR |
996 | } |
997 | ||
043a0405 S |
998 | /* |
999 | * Drain a given TX queue (could be Beacon or Data) | |
1000 | * | |
1001 | * This assumes output has been stopped and | |
1002 | * we do not need to block ath_tx_tasklet. | |
1003 | */ | |
1004 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 1005 | { |
e8324357 S |
1006 | struct ath_buf *bf, *lastbf; |
1007 | struct list_head bf_head; | |
f078f209 | 1008 | |
e8324357 | 1009 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1010 | |
e8324357 S |
1011 | for (;;) { |
1012 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1013 | |
e8324357 S |
1014 | if (list_empty(&txq->axq_q)) { |
1015 | txq->axq_link = NULL; | |
1016 | txq->axq_linkbuf = NULL; | |
1017 | spin_unlock_bh(&txq->axq_lock); | |
1018 | break; | |
1019 | } | |
f078f209 | 1020 | |
e8324357 | 1021 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1022 | |
a119cc49 | 1023 | if (bf->bf_stale) { |
e8324357 S |
1024 | list_del(&bf->list); |
1025 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1026 | |
e8324357 S |
1027 | spin_lock_bh(&sc->tx.txbuflock); |
1028 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1029 | spin_unlock_bh(&sc->tx.txbuflock); | |
1030 | continue; | |
1031 | } | |
f078f209 | 1032 | |
e8324357 S |
1033 | lastbf = bf->bf_lastbf; |
1034 | if (!retry_tx) | |
1035 | lastbf->bf_desc->ds_txstat.ts_flags = | |
1036 | ATH9K_TX_SW_ABORTED; | |
f078f209 | 1037 | |
e8324357 S |
1038 | /* remove ath_buf's of the same mpdu from txq */ |
1039 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1040 | txq->axq_depth--; | |
f078f209 | 1041 | |
e8324357 S |
1042 | spin_unlock_bh(&txq->axq_lock); |
1043 | ||
1044 | if (bf_isampdu(bf)) | |
d43f3015 | 1045 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0); |
e8324357 | 1046 | else |
fec247c0 | 1047 | ath_tx_complete_buf(sc, bf, txq, &bf_head, 0, 0); |
f078f209 LR |
1048 | } |
1049 | ||
164ace38 SB |
1050 | spin_lock_bh(&txq->axq_lock); |
1051 | txq->axq_tx_inprogress = false; | |
1052 | spin_unlock_bh(&txq->axq_lock); | |
1053 | ||
e8324357 S |
1054 | /* flush any pending frames if aggregation is enabled */ |
1055 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1056 | if (!retry_tx) { | |
1057 | spin_lock_bh(&txq->axq_lock); | |
1058 | ath_txq_drain_pending_buffers(sc, txq); | |
1059 | spin_unlock_bh(&txq->axq_lock); | |
1060 | } | |
1061 | } | |
f078f209 LR |
1062 | } |
1063 | ||
043a0405 | 1064 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1065 | { |
cbe61d8a | 1066 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1067 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 S |
1068 | struct ath_txq *txq; |
1069 | int i, npend = 0; | |
1070 | ||
1071 | if (sc->sc_flags & SC_OP_INVALID) | |
1072 | return; | |
1073 | ||
1074 | /* Stop beacon queue */ | |
1075 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1076 | ||
1077 | /* Stop data queues */ | |
1078 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1079 | if (ATH_TXQ_SETUP(sc, i)) { | |
1080 | txq = &sc->tx.txq[i]; | |
1081 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1082 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1083 | } | |
1084 | } | |
1085 | ||
1086 | if (npend) { | |
1087 | int r; | |
1088 | ||
c46917bb LR |
1089 | ath_print(common, ATH_DBG_XMIT, |
1090 | "Unable to stop TxDMA. Reset HAL!\n"); | |
043a0405 S |
1091 | |
1092 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 1093 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); |
043a0405 | 1094 | if (r) |
c46917bb LR |
1095 | ath_print(common, ATH_DBG_FATAL, |
1096 | "Unable to reset hardware; reset status %d\n", | |
1097 | r); | |
043a0405 S |
1098 | spin_unlock_bh(&sc->sc_resetlock); |
1099 | } | |
1100 | ||
1101 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1102 | if (ATH_TXQ_SETUP(sc, i)) | |
1103 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1104 | } | |
e8324357 | 1105 | } |
f078f209 | 1106 | |
043a0405 | 1107 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1108 | { |
043a0405 S |
1109 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1110 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1111 | } |
f078f209 | 1112 | |
e8324357 S |
1113 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1114 | { | |
1115 | struct ath_atx_ac *ac; | |
1116 | struct ath_atx_tid *tid; | |
f078f209 | 1117 | |
e8324357 S |
1118 | if (list_empty(&txq->axq_acq)) |
1119 | return; | |
f078f209 | 1120 | |
e8324357 S |
1121 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1122 | list_del(&ac->list); | |
1123 | ac->sched = false; | |
f078f209 | 1124 | |
e8324357 S |
1125 | do { |
1126 | if (list_empty(&ac->tid_q)) | |
1127 | return; | |
f078f209 | 1128 | |
e8324357 S |
1129 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1130 | list_del(&tid->list); | |
1131 | tid->sched = false; | |
f078f209 | 1132 | |
e8324357 S |
1133 | if (tid->paused) |
1134 | continue; | |
f078f209 | 1135 | |
164ace38 | 1136 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1137 | |
1138 | /* | |
e8324357 S |
1139 | * add tid to round-robin queue if more frames |
1140 | * are pending for the tid | |
f078f209 | 1141 | */ |
e8324357 S |
1142 | if (!list_empty(&tid->buf_q)) |
1143 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1144 | |
e8324357 S |
1145 | break; |
1146 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1147 | |
e8324357 S |
1148 | if (!list_empty(&ac->tid_q)) { |
1149 | if (!ac->sched) { | |
1150 | ac->sched = true; | |
1151 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1152 | } |
e8324357 S |
1153 | } |
1154 | } | |
f078f209 | 1155 | |
e8324357 S |
1156 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1157 | { | |
1158 | struct ath_txq *txq; | |
f078f209 | 1159 | |
e8324357 | 1160 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
c46917bb LR |
1161 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1162 | "HAL AC %u out of range, max %zu!\n", | |
e8324357 S |
1163 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); |
1164 | return 0; | |
1165 | } | |
1166 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1167 | if (txq != NULL) { | |
1168 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1169 | return 1; | |
1170 | } else | |
1171 | return 0; | |
f078f209 LR |
1172 | } |
1173 | ||
e8324357 S |
1174 | /***********/ |
1175 | /* TX, DMA */ | |
1176 | /***********/ | |
1177 | ||
f078f209 | 1178 | /* |
e8324357 S |
1179 | * Insert a chain of ath_buf (descriptors) on a txq and |
1180 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1181 | */ |
e8324357 S |
1182 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1183 | struct list_head *head) | |
f078f209 | 1184 | { |
cbe61d8a | 1185 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1186 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1187 | struct ath_buf *bf; |
f078f209 | 1188 | |
e8324357 S |
1189 | /* |
1190 | * Insert the frame on the outbound list and | |
1191 | * pass it on to the hardware. | |
1192 | */ | |
f078f209 | 1193 | |
e8324357 S |
1194 | if (list_empty(head)) |
1195 | return; | |
f078f209 | 1196 | |
e8324357 | 1197 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1198 | |
e8324357 S |
1199 | list_splice_tail_init(head, &txq->axq_q); |
1200 | txq->axq_depth++; | |
e8324357 | 1201 | txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); |
f078f209 | 1202 | |
c46917bb LR |
1203 | ath_print(common, ATH_DBG_QUEUE, |
1204 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1205 | |
e8324357 S |
1206 | if (txq->axq_link == NULL) { |
1207 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
c46917bb LR |
1208 | ath_print(common, ATH_DBG_XMIT, |
1209 | "TXDP[%u] = %llx (%p)\n", | |
1210 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1211 | } else { |
1212 | *txq->axq_link = bf->bf_daddr; | |
c46917bb LR |
1213 | ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", |
1214 | txq->axq_qnum, txq->axq_link, | |
1215 | ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1216 | } |
1217 | txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link); | |
1218 | ath9k_hw_txstart(ah, txq->axq_qnum); | |
1219 | } | |
f078f209 | 1220 | |
e8324357 S |
1221 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1222 | { | |
1223 | struct ath_buf *bf = NULL; | |
f078f209 | 1224 | |
e8324357 | 1225 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1226 | |
e8324357 S |
1227 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1228 | spin_unlock_bh(&sc->tx.txbuflock); | |
1229 | return NULL; | |
1230 | } | |
f078f209 | 1231 | |
e8324357 S |
1232 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1233 | list_del(&bf->list); | |
f078f209 | 1234 | |
e8324357 | 1235 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1236 | |
e8324357 | 1237 | return bf; |
f078f209 LR |
1238 | } |
1239 | ||
e8324357 S |
1240 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1241 | struct list_head *bf_head, | |
1242 | struct ath_tx_control *txctl) | |
f078f209 LR |
1243 | { |
1244 | struct ath_buf *bf; | |
f078f209 | 1245 | |
e8324357 S |
1246 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1247 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1248 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1249 | |
e8324357 S |
1250 | /* |
1251 | * Do not queue to h/w when any of the following conditions is true: | |
1252 | * - there are pending frames in software queue | |
1253 | * - the TID is currently paused for ADDBA/BAR request | |
1254 | * - seqno is not within block-ack window | |
1255 | * - h/w queue depth exceeds low water mark | |
1256 | */ | |
1257 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1258 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1259 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1260 | /* |
e8324357 S |
1261 | * Add this frame to software queue for scheduling later |
1262 | * for aggregation. | |
f078f209 | 1263 | */ |
d43f3015 | 1264 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1265 | ath_tx_queue_tid(txctl->txq, tid); |
1266 | return; | |
1267 | } | |
1268 | ||
1269 | /* Add sub-frame to BAW */ | |
1270 | ath_tx_addto_baw(sc, tid, bf); | |
1271 | ||
1272 | /* Queue to h/w without aggregation */ | |
1273 | bf->bf_nframes = 1; | |
d43f3015 | 1274 | bf->bf_lastbf = bf; |
e8324357 S |
1275 | ath_buf_set_rate(sc, bf); |
1276 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1277 | } |
1278 | ||
c37452b0 S |
1279 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1280 | struct ath_atx_tid *tid, | |
1281 | struct list_head *bf_head) | |
e8324357 S |
1282 | { |
1283 | struct ath_buf *bf; | |
1284 | ||
e8324357 S |
1285 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1286 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1287 | ||
1288 | /* update starting sequence number for subsequent ADDBA request */ | |
1289 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1290 | ||
1291 | bf->bf_nframes = 1; | |
d43f3015 | 1292 | bf->bf_lastbf = bf; |
e8324357 S |
1293 | ath_buf_set_rate(sc, bf); |
1294 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1295 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1296 | } |
1297 | ||
c37452b0 S |
1298 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1299 | struct list_head *bf_head) | |
1300 | { | |
1301 | struct ath_buf *bf; | |
1302 | ||
1303 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1304 | ||
1305 | bf->bf_lastbf = bf; | |
1306 | bf->bf_nframes = 1; | |
1307 | ath_buf_set_rate(sc, bf); | |
1308 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1309 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1310 | } |
1311 | ||
e8324357 S |
1312 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1313 | { | |
1314 | struct ieee80211_hdr *hdr; | |
1315 | enum ath9k_pkt_type htype; | |
1316 | __le16 fc; | |
1317 | ||
1318 | hdr = (struct ieee80211_hdr *)skb->data; | |
1319 | fc = hdr->frame_control; | |
1320 | ||
1321 | if (ieee80211_is_beacon(fc)) | |
1322 | htype = ATH9K_PKT_TYPE_BEACON; | |
1323 | else if (ieee80211_is_probe_resp(fc)) | |
1324 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1325 | else if (ieee80211_is_atim(fc)) | |
1326 | htype = ATH9K_PKT_TYPE_ATIM; | |
1327 | else if (ieee80211_is_pspoll(fc)) | |
1328 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1329 | else | |
1330 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1331 | ||
1332 | return htype; | |
1333 | } | |
1334 | ||
1335 | static bool is_pae(struct sk_buff *skb) | |
1336 | { | |
1337 | struct ieee80211_hdr *hdr; | |
1338 | __le16 fc; | |
1339 | ||
1340 | hdr = (struct ieee80211_hdr *)skb->data; | |
1341 | fc = hdr->frame_control; | |
1342 | ||
1343 | if (ieee80211_is_data(fc)) { | |
1344 | if (ieee80211_is_nullfunc(fc) || | |
1345 | /* Port Access Entity (IEEE 802.1X) */ | |
1346 | (skb->protocol == cpu_to_be16(ETH_P_PAE))) { | |
1347 | return true; | |
1348 | } | |
1349 | } | |
1350 | ||
1351 | return false; | |
1352 | } | |
1353 | ||
1354 | static int get_hw_crypto_keytype(struct sk_buff *skb) | |
1355 | { | |
1356 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1357 | ||
1358 | if (tx_info->control.hw_key) { | |
1359 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1360 | return ATH9K_KEY_TYPE_WEP; | |
1361 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1362 | return ATH9K_KEY_TYPE_TKIP; | |
1363 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1364 | return ATH9K_KEY_TYPE_AES; | |
1365 | } | |
1366 | ||
1367 | return ATH9K_KEY_TYPE_CLEAR; | |
1368 | } | |
1369 | ||
1370 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1371 | struct ath_buf *bf) | |
1372 | { | |
1373 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1374 | struct ieee80211_hdr *hdr; | |
1375 | struct ath_node *an; | |
1376 | struct ath_atx_tid *tid; | |
1377 | __le16 fc; | |
1378 | u8 *qc; | |
1379 | ||
1380 | if (!tx_info->control.sta) | |
1381 | return; | |
1382 | ||
1383 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1384 | hdr = (struct ieee80211_hdr *)skb->data; | |
1385 | fc = hdr->frame_control; | |
1386 | ||
1387 | if (ieee80211_is_data_qos(fc)) { | |
1388 | qc = ieee80211_get_qos_ctl(hdr); | |
1389 | bf->bf_tidno = qc[0] & 0xf; | |
1390 | } | |
1391 | ||
1392 | /* | |
1393 | * For HT capable stations, we save tidno for later use. | |
1394 | * We also override seqno set by upper layer with the one | |
1395 | * in tx aggregation state. | |
1396 | * | |
1397 | * If fragmentation is on, the sequence number is | |
1398 | * not overridden, since it has been | |
1399 | * incremented by the fragmentation routine. | |
1400 | * | |
1401 | * FIXME: check if the fragmentation threshold exceeds | |
1402 | * IEEE80211 max. | |
1403 | */ | |
1404 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1405 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << | |
1406 | IEEE80211_SEQ_SEQ_SHIFT); | |
1407 | bf->bf_seqno = tid->seq_next; | |
1408 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1409 | } | |
1410 | ||
1411 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1412 | struct ath_txq *txq) | |
1413 | { | |
1414 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1415 | int flags = 0; | |
1416 | ||
1417 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1418 | flags |= ATH9K_TXDESC_INTREQ; | |
1419 | ||
1420 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1421 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1422 | |
1423 | return flags; | |
1424 | } | |
1425 | ||
1426 | /* | |
1427 | * rix - rate index | |
1428 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1429 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1430 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1431 | */ | |
1432 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1433 | int width, int half_gi, bool shortPreamble) | |
1434 | { | |
4f0fc7c3 | 1435 | const struct ath_rate_table *rate_table = sc->cur_rate_table; |
e8324357 S |
1436 | u32 nbits, nsymbits, duration, nsymbols; |
1437 | u8 rc; | |
1438 | int streams, pktlen; | |
1439 | ||
1440 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
1441 | rc = rate_table->info[rix].ratecode; | |
1442 | ||
1443 | /* for legacy rates, use old function to compute packet duration */ | |
1444 | if (!IS_HT_RATE(rc)) | |
1445 | return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen, | |
1446 | rix, shortPreamble); | |
1447 | ||
1448 | /* find number of symbols: PLCP + data */ | |
1449 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
1450 | nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width]; | |
1451 | nsymbols = (nbits + nsymbits - 1) / nsymbits; | |
1452 | ||
1453 | if (!half_gi) | |
1454 | duration = SYMBOL_TIME(nsymbols); | |
1455 | else | |
1456 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1457 | ||
1458 | /* addup duration for legacy/ht training and signal fields */ | |
1459 | streams = HT_RC_2_STREAMS(rc); | |
1460 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); | |
1461 | ||
1462 | return duration; | |
1463 | } | |
1464 | ||
1465 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1466 | { | |
43c27613 | 1467 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4f0fc7c3 | 1468 | const struct ath_rate_table *rt = sc->cur_rate_table; |
e8324357 S |
1469 | struct ath9k_11n_rate_series series[4]; |
1470 | struct sk_buff *skb; | |
1471 | struct ieee80211_tx_info *tx_info; | |
1472 | struct ieee80211_tx_rate *rates; | |
254ad0ff | 1473 | struct ieee80211_hdr *hdr; |
c89424df S |
1474 | int i, flags = 0; |
1475 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1476 | bool is_pspoll; |
e8324357 S |
1477 | |
1478 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1479 | ||
a22be22a | 1480 | skb = bf->bf_mpdu; |
e8324357 S |
1481 | tx_info = IEEE80211_SKB_CB(skb); |
1482 | rates = tx_info->control.rates; | |
254ad0ff S |
1483 | hdr = (struct ieee80211_hdr *)skb->data; |
1484 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1485 | |
e8324357 | 1486 | /* |
c89424df S |
1487 | * We check if Short Preamble is needed for the CTS rate by |
1488 | * checking the BSS's global flag. | |
1489 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1490 | */ |
c89424df S |
1491 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
1492 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode | | |
1493 | rt->info[tx_info->control.rts_cts_rate_idx].short_preamble; | |
1494 | else | |
1495 | ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode; | |
e8324357 | 1496 | |
c89424df S |
1497 | /* |
1498 | * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. | |
1499 | * Check the first rate in the series to decide whether RTS/CTS | |
1500 | * or CTS-to-self has to be used. | |
e8324357 | 1501 | */ |
c89424df S |
1502 | if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) |
1503 | flags = ATH9K_TXDESC_CTSENA; | |
1504 | else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1505 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 | 1506 | |
c89424df | 1507 | /* FIXME: Handle aggregation protection */ |
17d7904d | 1508 | if (sc->config.ath_aggr_prot && |
e8324357 S |
1509 | (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) { |
1510 | flags = ATH9K_TXDESC_RTSENA; | |
e8324357 S |
1511 | } |
1512 | ||
1513 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ | |
2660b81a | 1514 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) |
e8324357 S |
1515 | flags &= ~(ATH9K_TXDESC_RTSENA); |
1516 | ||
e8324357 S |
1517 | for (i = 0; i < 4; i++) { |
1518 | if (!rates[i].count || (rates[i].idx < 0)) | |
1519 | continue; | |
1520 | ||
1521 | rix = rates[i].idx; | |
e8324357 | 1522 | series[i].Tries = rates[i].count; |
43c27613 | 1523 | series[i].ChSel = common->tx_chainmask; |
e8324357 | 1524 | |
c89424df S |
1525 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) |
1526 | series[i].Rate = rt->info[rix].ratecode | | |
1527 | rt->info[rix].short_preamble; | |
1528 | else | |
1529 | series[i].Rate = rt->info[rix].ratecode; | |
1530 | ||
1531 | if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) | |
1532 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1533 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
1534 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1535 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1536 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 S |
1537 | |
1538 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1539 | (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0, | |
1540 | (rates[i].flags & IEEE80211_TX_RC_SHORT_GI), | |
c89424df | 1541 | (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)); |
f078f209 LR |
1542 | } |
1543 | ||
e8324357 | 1544 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1545 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1546 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1547 | !is_pspoll, ctsrate, |
c89424df | 1548 | 0, series, 4, flags); |
f078f209 | 1549 | |
17d7904d | 1550 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1551 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1552 | } |
1553 | ||
c52f33d0 | 1554 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1555 | struct sk_buff *skb, |
528f0c6b | 1556 | struct ath_tx_control *txctl) |
f078f209 | 1557 | { |
c52f33d0 JM |
1558 | struct ath_wiphy *aphy = hw->priv; |
1559 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1560 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1561 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
f078f209 | 1562 | struct ath_tx_info_priv *tx_info_priv; |
528f0c6b S |
1563 | int hdrlen; |
1564 | __le16 fc; | |
e022edbd | 1565 | |
c112d0c5 LR |
1566 | tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC); |
1567 | if (unlikely(!tx_info_priv)) | |
1568 | return -ENOMEM; | |
a8efee4f | 1569 | tx_info->rate_driver_data[0] = tx_info_priv; |
c52f33d0 | 1570 | tx_info_priv->aphy = aphy; |
f0ed85c6 | 1571 | tx_info_priv->frame_type = txctl->frame_type; |
528f0c6b S |
1572 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1573 | fc = hdr->frame_control; | |
f078f209 | 1574 | |
528f0c6b | 1575 | ATH_TXBUF_RESET(bf); |
f078f209 | 1576 | |
528f0c6b | 1577 | bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3); |
cd3d39a6 | 1578 | |
5008f372 | 1579 | if (conf_is_ht(&hw->conf) && !is_pae(skb)) |
c656bbb5 | 1580 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1581 | |
1582 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1583 | ||
528f0c6b | 1584 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1585 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1586 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1587 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1588 | } else { | |
1589 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1590 | } | |
1591 | ||
d3a1db1c | 1592 | if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR)) |
528f0c6b S |
1593 | assign_aggr_tid_seqno(skb, bf); |
1594 | ||
f078f209 | 1595 | bf->bf_mpdu = skb; |
f8316df1 | 1596 | |
7da3c55c GJ |
1597 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1598 | skb->len, DMA_TO_DEVICE); | |
1599 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1600 | bf->bf_mpdu = NULL; |
675902ef S |
1601 | kfree(tx_info_priv); |
1602 | tx_info->rate_driver_data[0] = NULL; | |
c46917bb LR |
1603 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1604 | "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1605 | return -ENOMEM; |
1606 | } | |
1607 | ||
528f0c6b | 1608 | bf->bf_buf_addr = bf->bf_dmacontext; |
f8316df1 | 1609 | return 0; |
528f0c6b S |
1610 | } |
1611 | ||
1612 | /* FIXME: tx power */ | |
1613 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1614 | struct ath_tx_control *txctl) |
1615 | { | |
a22be22a | 1616 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1617 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1618 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1619 | struct ath_node *an = NULL; |
1620 | struct list_head bf_head; | |
1621 | struct ath_desc *ds; | |
1622 | struct ath_atx_tid *tid; | |
cbe61d8a | 1623 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1624 | int frm_type; |
c37452b0 | 1625 | __le16 fc; |
528f0c6b | 1626 | |
528f0c6b | 1627 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1628 | fc = hdr->frame_control; |
528f0c6b S |
1629 | |
1630 | INIT_LIST_HEAD(&bf_head); | |
1631 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1632 | |
f078f209 LR |
1633 | ds = bf->bf_desc; |
1634 | ds->ds_link = 0; | |
1635 | ds->ds_data = bf->bf_buf_addr; | |
1636 | ||
528f0c6b S |
1637 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1638 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1639 | ||
1640 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1641 | skb->len, /* segment length */ |
1642 | true, /* first segment */ | |
1643 | true, /* last segment */ | |
1644 | ds); /* first descriptor */ | |
f078f209 | 1645 | |
528f0c6b | 1646 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1647 | |
f1617967 JL |
1648 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1649 | tx_info->control.sta) { | |
1650 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1651 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1652 | ||
c37452b0 S |
1653 | if (!ieee80211_is_data_qos(fc)) { |
1654 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1655 | goto tx_done; | |
1656 | } | |
1657 | ||
089e698d | 1658 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
f078f209 LR |
1659 | /* |
1660 | * Try aggregation if it's a unicast data frame | |
1661 | * and the destination is HT capable. | |
1662 | */ | |
528f0c6b | 1663 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1664 | } else { |
1665 | /* | |
528f0c6b S |
1666 | * Send this frame as regular when ADDBA |
1667 | * exchange is neither complete nor pending. | |
f078f209 | 1668 | */ |
c37452b0 S |
1669 | ath_tx_send_ht_normal(sc, txctl->txq, |
1670 | tid, &bf_head); | |
f078f209 LR |
1671 | } |
1672 | } else { | |
c37452b0 | 1673 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1674 | } |
528f0c6b | 1675 | |
c37452b0 | 1676 | tx_done: |
528f0c6b | 1677 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1678 | } |
1679 | ||
f8316df1 | 1680 | /* Upon failure caller should free skb */ |
c52f33d0 | 1681 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1682 | struct ath_tx_control *txctl) |
f078f209 | 1683 | { |
c52f33d0 JM |
1684 | struct ath_wiphy *aphy = hw->priv; |
1685 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1686 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1687 | struct ath_buf *bf; |
f8316df1 | 1688 | int r; |
f078f209 | 1689 | |
528f0c6b S |
1690 | bf = ath_tx_get_buffer(sc); |
1691 | if (!bf) { | |
c46917bb | 1692 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1693 | return -1; |
1694 | } | |
1695 | ||
c52f33d0 | 1696 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1697 | if (unlikely(r)) { |
c112d0c5 LR |
1698 | struct ath_txq *txq = txctl->txq; |
1699 | ||
c46917bb | 1700 | ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1701 | |
1702 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1703 | * guarantee this will happen by knowing beforehand that | |
1704 | * we will at least have to run TX completionon one buffer | |
1705 | * on the queue */ | |
1706 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1707 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
c112d0c5 LR |
1708 | ieee80211_stop_queue(sc->hw, |
1709 | skb_get_queue_mapping(skb)); | |
1710 | txq->stopped = 1; | |
1711 | } | |
1712 | spin_unlock_bh(&txq->axq_lock); | |
1713 | ||
b77f483f S |
1714 | spin_lock_bh(&sc->tx.txbuflock); |
1715 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1716 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1717 | |
f8316df1 LR |
1718 | return r; |
1719 | } | |
1720 | ||
8f93b8b3 | 1721 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1722 | |
528f0c6b | 1723 | return 0; |
f078f209 LR |
1724 | } |
1725 | ||
c52f33d0 | 1726 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1727 | { |
c52f33d0 JM |
1728 | struct ath_wiphy *aphy = hw->priv; |
1729 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1730 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1731 | int hdrlen, padsize; |
1732 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
1733 | struct ath_tx_control txctl; | |
f078f209 | 1734 | |
e8324357 | 1735 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1736 | |
1737 | /* | |
e8324357 S |
1738 | * As a temporary workaround, assign seq# here; this will likely need |
1739 | * to be cleaned up to work better with Beacon transmission and virtual | |
1740 | * BSSes. | |
f078f209 | 1741 | */ |
e8324357 S |
1742 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
1743 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
1744 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) | |
1745 | sc->tx.seq_no += 0x10; | |
1746 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1747 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1748 | } |
f078f209 | 1749 | |
e8324357 S |
1750 | /* Add the padding after the header if this is not already done */ |
1751 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1752 | if (hdrlen & 3) { | |
1753 | padsize = hdrlen % 4; | |
1754 | if (skb_headroom(skb) < padsize) { | |
c46917bb LR |
1755 | ath_print(common, ATH_DBG_XMIT, |
1756 | "TX CABQ padding failed\n"); | |
e8324357 S |
1757 | dev_kfree_skb_any(skb); |
1758 | return; | |
1759 | } | |
1760 | skb_push(skb, padsize); | |
1761 | memmove(skb->data, skb->data + padsize, hdrlen); | |
f078f209 | 1762 | } |
f078f209 | 1763 | |
e8324357 | 1764 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1765 | |
c46917bb LR |
1766 | ath_print(common, ATH_DBG_XMIT, |
1767 | "transmitting CABQ packet, skb: %p\n", skb); | |
f078f209 | 1768 | |
c52f33d0 | 1769 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1770 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
e8324357 | 1771 | goto exit; |
f078f209 | 1772 | } |
f078f209 | 1773 | |
e8324357 S |
1774 | return; |
1775 | exit: | |
1776 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1777 | } |
1778 | ||
e8324357 S |
1779 | /*****************/ |
1780 | /* TX Completion */ | |
1781 | /*****************/ | |
528f0c6b | 1782 | |
e8324357 | 1783 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
6b2c4032 | 1784 | int tx_flags) |
528f0c6b | 1785 | { |
e8324357 S |
1786 | struct ieee80211_hw *hw = sc->hw; |
1787 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1788 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
c46917bb | 1789 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 1790 | int hdrlen, padsize; |
f0ed85c6 | 1791 | int frame_type = ATH9K_NOT_INTERNAL; |
528f0c6b | 1792 | |
c46917bb | 1793 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1794 | |
f0ed85c6 | 1795 | if (tx_info_priv) { |
c52f33d0 | 1796 | hw = tx_info_priv->aphy->hw; |
f0ed85c6 JM |
1797 | frame_type = tx_info_priv->frame_type; |
1798 | } | |
c52f33d0 | 1799 | |
e8324357 S |
1800 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK || |
1801 | tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) { | |
1802 | kfree(tx_info_priv); | |
1803 | tx_info->rate_driver_data[0] = NULL; | |
1804 | } | |
528f0c6b | 1805 | |
6b2c4032 | 1806 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1807 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1808 | |
6b2c4032 | 1809 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1810 | /* Frame was ACKed */ |
1811 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1812 | } |
1813 | ||
e8324357 S |
1814 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1815 | padsize = hdrlen & 3; | |
1816 | if (padsize && hdrlen >= 24) { | |
1817 | /* | |
1818 | * Remove MAC header padding before giving the frame back to | |
1819 | * mac80211. | |
1820 | */ | |
1821 | memmove(skb->data + padsize, skb->data, hdrlen); | |
1822 | skb_pull(skb, padsize); | |
1823 | } | |
528f0c6b | 1824 | |
9a23f9ca JM |
1825 | if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { |
1826 | sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; | |
c46917bb LR |
1827 | ath_print(common, ATH_DBG_PS, |
1828 | "Going back to sleep after having " | |
1829 | "received TX status (0x%x)\n", | |
9a23f9ca JM |
1830 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
1831 | SC_OP_WAIT_FOR_CAB | | |
1832 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
1833 | SC_OP_WAIT_FOR_TX_ACK)); | |
1834 | } | |
1835 | ||
f0ed85c6 JM |
1836 | if (frame_type == ATH9K_NOT_INTERNAL) |
1837 | ieee80211_tx_status(hw, skb); | |
1838 | else | |
1839 | ath9k_tx_status(hw, skb); | |
e8324357 | 1840 | } |
f078f209 | 1841 | |
e8324357 | 1842 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
fec247c0 | 1843 | struct ath_txq *txq, |
e8324357 S |
1844 | struct list_head *bf_q, |
1845 | int txok, int sendbar) | |
f078f209 | 1846 | { |
e8324357 | 1847 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1848 | unsigned long flags; |
6b2c4032 | 1849 | int tx_flags = 0; |
f078f209 | 1850 | |
e8324357 | 1851 | if (sendbar) |
6b2c4032 | 1852 | tx_flags = ATH_TX_BAR; |
f078f209 | 1853 | |
e8324357 | 1854 | if (!txok) { |
6b2c4032 | 1855 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1856 | |
e8324357 | 1857 | if (bf_isxretried(bf)) |
6b2c4032 | 1858 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1859 | } |
1860 | ||
e8324357 | 1861 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
6b2c4032 | 1862 | ath_tx_complete(sc, skb, tx_flags); |
fec247c0 | 1863 | ath_debug_stat_tx(sc, txq, bf); |
e8324357 S |
1864 | |
1865 | /* | |
1866 | * Return the list of ath_buf of this mpdu to free queue | |
1867 | */ | |
1868 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1869 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1870 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1871 | } |
1872 | ||
e8324357 S |
1873 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
1874 | int txok) | |
f078f209 | 1875 | { |
e8324357 S |
1876 | struct ath_buf *bf_last = bf->bf_lastbf; |
1877 | struct ath_desc *ds = bf_last->bf_desc; | |
1878 | u16 seq_st = 0; | |
1879 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1880 | int ba_index; | |
1881 | int nbad = 0; | |
1882 | int isaggr = 0; | |
f078f209 | 1883 | |
e8324357 S |
1884 | if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED) |
1885 | return 0; | |
f078f209 | 1886 | |
e8324357 S |
1887 | isaggr = bf_isaggr(bf); |
1888 | if (isaggr) { | |
1889 | seq_st = ATH_DS_BA_SEQ(ds); | |
1890 | memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3); | |
1891 | } | |
f078f209 | 1892 | |
e8324357 S |
1893 | while (bf) { |
1894 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1895 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1896 | nbad++; | |
1897 | ||
1898 | bf = bf->bf_next; | |
1899 | } | |
f078f209 | 1900 | |
e8324357 S |
1901 | return nbad; |
1902 | } | |
f078f209 | 1903 | |
95e4acb7 | 1904 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, |
8a92e2ee | 1905 | int nbad, int txok, bool update_rc) |
f078f209 | 1906 | { |
a22be22a | 1907 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1908 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 S |
1909 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1910 | struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info); | |
8a92e2ee VT |
1911 | struct ieee80211_hw *hw = tx_info_priv->aphy->hw; |
1912 | u8 i, tx_rateindex; | |
f078f209 | 1913 | |
95e4acb7 S |
1914 | if (txok) |
1915 | tx_info->status.ack_signal = ds->ds_txstat.ts_rssi; | |
1916 | ||
8a92e2ee VT |
1917 | tx_rateindex = ds->ds_txstat.ts_rateindex; |
1918 | WARN_ON(tx_rateindex >= hw->max_rates); | |
1919 | ||
1920 | tx_info_priv->update_rc = update_rc; | |
e8324357 S |
1921 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) |
1922 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
f078f209 | 1923 | |
e8324357 | 1924 | if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1925 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1926 | if (ieee80211_is_data(hdr->frame_control)) { |
e8324357 S |
1927 | memcpy(&tx_info_priv->tx, &ds->ds_txstat, |
1928 | sizeof(tx_info_priv->tx)); | |
1929 | tx_info_priv->n_frames = bf->bf_nframes; | |
1930 | tx_info_priv->n_bad_frames = nbad; | |
e8324357 | 1931 | } |
f078f209 | 1932 | } |
8a92e2ee VT |
1933 | |
1934 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) | |
1935 | tx_info->status.rates[i].count = 0; | |
1936 | ||
1937 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1938 | } |
1939 | ||
059d806c S |
1940 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1941 | { | |
1942 | int qnum; | |
1943 | ||
1944 | spin_lock_bh(&txq->axq_lock); | |
1945 | if (txq->stopped && | |
f7a99e46 | 1946 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1947 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1948 | if (qnum != -1) { | |
1949 | ieee80211_wake_queue(sc->hw, qnum); | |
1950 | txq->stopped = 0; | |
1951 | } | |
1952 | } | |
1953 | spin_unlock_bh(&txq->axq_lock); | |
1954 | } | |
1955 | ||
e8324357 | 1956 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1957 | { |
cbe61d8a | 1958 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1959 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1960 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1961 | struct list_head bf_head; |
e8324357 | 1962 | struct ath_desc *ds; |
0934af23 | 1963 | int txok; |
e8324357 | 1964 | int status; |
f078f209 | 1965 | |
c46917bb LR |
1966 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1967 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1968 | txq->axq_link); | |
f078f209 | 1969 | |
f078f209 LR |
1970 | for (;;) { |
1971 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1972 | if (list_empty(&txq->axq_q)) { |
1973 | txq->axq_link = NULL; | |
1974 | txq->axq_linkbuf = NULL; | |
1975 | spin_unlock_bh(&txq->axq_lock); | |
1976 | break; | |
1977 | } | |
f078f209 LR |
1978 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
1979 | ||
e8324357 S |
1980 | /* |
1981 | * There is a race condition that a BH gets scheduled | |
1982 | * after sw writes TxE and before hw re-load the last | |
1983 | * descriptor to get the newly chained one. | |
1984 | * Software must keep the last DONE descriptor as a | |
1985 | * holding descriptor - software does so by marking | |
1986 | * it with the STALE flag. | |
1987 | */ | |
1988 | bf_held = NULL; | |
a119cc49 | 1989 | if (bf->bf_stale) { |
e8324357 S |
1990 | bf_held = bf; |
1991 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 1992 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
1993 | break; |
1994 | } else { | |
1995 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 1996 | struct ath_buf, list); |
e8324357 | 1997 | } |
f078f209 LR |
1998 | } |
1999 | ||
2000 | lastbf = bf->bf_lastbf; | |
e8324357 | 2001 | ds = lastbf->bf_desc; |
f078f209 | 2002 | |
e8324357 S |
2003 | status = ath9k_hw_txprocdesc(ah, ds); |
2004 | if (status == -EINPROGRESS) { | |
f078f209 | 2005 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2006 | break; |
f078f209 | 2007 | } |
e8324357 S |
2008 | if (bf->bf_desc == txq->axq_lastdsWithCTS) |
2009 | txq->axq_lastdsWithCTS = NULL; | |
2010 | if (ds == txq->axq_gatingds) | |
2011 | txq->axq_gatingds = NULL; | |
f078f209 | 2012 | |
e8324357 S |
2013 | /* |
2014 | * Remove ath_buf's of the same transmit unit from txq, | |
2015 | * however leave the last descriptor back as the holding | |
2016 | * descriptor for hw. | |
2017 | */ | |
a119cc49 | 2018 | lastbf->bf_stale = true; |
e8324357 | 2019 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2020 | if (!list_is_singular(&lastbf->list)) |
2021 | list_cut_position(&bf_head, | |
2022 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2023 | |
e8324357 | 2024 | txq->axq_depth--; |
e8324357 S |
2025 | if (bf_isaggr(bf)) |
2026 | txq->axq_aggr_depth--; | |
f078f209 | 2027 | |
e8324357 | 2028 | txok = (ds->ds_txstat.ts_status == 0); |
164ace38 | 2029 | txq->axq_tx_inprogress = false; |
e8324357 | 2030 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2031 | |
e8324357 | 2032 | if (bf_held) { |
e8324357 | 2033 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2034 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2035 | spin_unlock_bh(&sc->tx.txbuflock); |
2036 | } | |
f078f209 | 2037 | |
e8324357 S |
2038 | if (!bf_isampdu(bf)) { |
2039 | /* | |
2040 | * This frame is sent out as a single frame. | |
2041 | * Use hardware retry status for this frame. | |
2042 | */ | |
2043 | bf->bf_retries = ds->ds_txstat.ts_longretry; | |
2044 | if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY) | |
2045 | bf->bf_state.bf_type |= BUF_XRETRY; | |
8a92e2ee | 2046 | ath_tx_rc_status(bf, ds, 0, txok, true); |
e8324357 | 2047 | } |
f078f209 | 2048 | |
e8324357 | 2049 | if (bf_isampdu(bf)) |
d43f3015 | 2050 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok); |
e8324357 | 2051 | else |
fec247c0 | 2052 | ath_tx_complete_buf(sc, bf, txq, &bf_head, txok, 0); |
8469cdef | 2053 | |
059d806c | 2054 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2055 | |
059d806c | 2056 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2057 | if (sc->sc_flags & SC_OP_TXAGGR) |
2058 | ath_txq_schedule(sc, txq); | |
2059 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2060 | } |
2061 | } | |
2062 | ||
305fe47f | 2063 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2064 | { |
2065 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2066 | tx_complete_work.work); | |
2067 | struct ath_txq *txq; | |
2068 | int i; | |
2069 | bool needreset = false; | |
2070 | ||
2071 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2072 | if (ATH_TXQ_SETUP(sc, i)) { | |
2073 | txq = &sc->tx.txq[i]; | |
2074 | spin_lock_bh(&txq->axq_lock); | |
2075 | if (txq->axq_depth) { | |
2076 | if (txq->axq_tx_inprogress) { | |
2077 | needreset = true; | |
2078 | spin_unlock_bh(&txq->axq_lock); | |
2079 | break; | |
2080 | } else { | |
2081 | txq->axq_tx_inprogress = true; | |
2082 | } | |
2083 | } | |
2084 | spin_unlock_bh(&txq->axq_lock); | |
2085 | } | |
2086 | ||
2087 | if (needreset) { | |
c46917bb LR |
2088 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2089 | "tx hung, resetting the chip\n"); | |
332c5566 | 2090 | ath9k_ps_wakeup(sc); |
164ace38 | 2091 | ath_reset(sc, false); |
332c5566 | 2092 | ath9k_ps_restore(sc); |
164ace38 SB |
2093 | } |
2094 | ||
42935eca | 2095 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2096 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2097 | } | |
2098 | ||
2099 | ||
f078f209 | 2100 | |
e8324357 | 2101 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2102 | { |
e8324357 S |
2103 | int i; |
2104 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2105 | |
e8324357 | 2106 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2107 | |
e8324357 S |
2108 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2109 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2110 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2111 | } |
2112 | } | |
2113 | ||
e8324357 S |
2114 | /*****************/ |
2115 | /* Init, Cleanup */ | |
2116 | /*****************/ | |
f078f209 | 2117 | |
e8324357 | 2118 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2119 | { |
c46917bb | 2120 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2121 | int error = 0; |
f078f209 | 2122 | |
797fe5cb | 2123 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2124 | |
797fe5cb S |
2125 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
2126 | "tx", nbufs, 1); | |
2127 | if (error != 0) { | |
c46917bb LR |
2128 | ath_print(common, ATH_DBG_FATAL, |
2129 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2130 | goto err; |
2131 | } | |
f078f209 | 2132 | |
797fe5cb S |
2133 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
2134 | "beacon", ATH_BCBUF, 1); | |
2135 | if (error != 0) { | |
c46917bb LR |
2136 | ath_print(common, ATH_DBG_FATAL, |
2137 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2138 | goto err; |
2139 | } | |
f078f209 | 2140 | |
164ace38 SB |
2141 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2142 | ||
797fe5cb | 2143 | err: |
e8324357 S |
2144 | if (error != 0) |
2145 | ath_tx_cleanup(sc); | |
f078f209 | 2146 | |
e8324357 | 2147 | return error; |
f078f209 LR |
2148 | } |
2149 | ||
797fe5cb | 2150 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2151 | { |
2152 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2153 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2154 | ||
2155 | if (sc->tx.txdma.dd_desc_len != 0) | |
2156 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2157 | } |
f078f209 LR |
2158 | |
2159 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2160 | { | |
c5170163 S |
2161 | struct ath_atx_tid *tid; |
2162 | struct ath_atx_ac *ac; | |
2163 | int tidno, acno; | |
f078f209 | 2164 | |
8ee5afbc | 2165 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2166 | tidno < WME_NUM_TID; |
2167 | tidno++, tid++) { | |
2168 | tid->an = an; | |
2169 | tid->tidno = tidno; | |
2170 | tid->seq_start = tid->seq_next = 0; | |
2171 | tid->baw_size = WME_MAX_BA; | |
2172 | tid->baw_head = tid->baw_tail = 0; | |
2173 | tid->sched = false; | |
e8324357 | 2174 | tid->paused = false; |
a37c2c79 | 2175 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2176 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2177 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2178 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2179 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2180 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2181 | } |
f078f209 | 2182 | |
8ee5afbc | 2183 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2184 | acno < WME_NUM_AC; acno++, ac++) { |
2185 | ac->sched = false; | |
2186 | INIT_LIST_HEAD(&ac->tid_q); | |
2187 | ||
2188 | switch (acno) { | |
2189 | case WME_AC_BE: | |
2190 | ac->qnum = ath_tx_get_qnum(sc, | |
2191 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2192 | break; | |
2193 | case WME_AC_BK: | |
2194 | ac->qnum = ath_tx_get_qnum(sc, | |
2195 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2196 | break; | |
2197 | case WME_AC_VI: | |
2198 | ac->qnum = ath_tx_get_qnum(sc, | |
2199 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2200 | break; | |
2201 | case WME_AC_VO: | |
2202 | ac->qnum = ath_tx_get_qnum(sc, | |
2203 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2204 | break; | |
f078f209 LR |
2205 | } |
2206 | } | |
2207 | } | |
2208 | ||
b5aa9bf9 | 2209 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2210 | { |
2211 | int i; | |
2212 | struct ath_atx_ac *ac, *ac_tmp; | |
2213 | struct ath_atx_tid *tid, *tid_tmp; | |
2214 | struct ath_txq *txq; | |
e8324357 | 2215 | |
f078f209 LR |
2216 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2217 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2218 | txq = &sc->tx.txq[i]; |
f078f209 | 2219 | |
b5aa9bf9 | 2220 | spin_lock(&txq->axq_lock); |
f078f209 LR |
2221 | |
2222 | list_for_each_entry_safe(ac, | |
2223 | ac_tmp, &txq->axq_acq, list) { | |
2224 | tid = list_first_entry(&ac->tid_q, | |
2225 | struct ath_atx_tid, list); | |
2226 | if (tid && tid->an != an) | |
2227 | continue; | |
2228 | list_del(&ac->list); | |
2229 | ac->sched = false; | |
2230 | ||
2231 | list_for_each_entry_safe(tid, | |
2232 | tid_tmp, &ac->tid_q, list) { | |
2233 | list_del(&tid->list); | |
2234 | tid->sched = false; | |
b5aa9bf9 | 2235 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2236 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2237 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2238 | } |
2239 | } | |
2240 | ||
b5aa9bf9 | 2241 | spin_unlock(&txq->axq_lock); |
f078f209 LR |
2242 | } |
2243 | } | |
2244 | } |