Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 LR |
19 | |
20 | #define BITS_PER_BYTE 8 | |
21 | #define OFDM_PLCP_BITS 22 | |
22 | #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f) | |
23 | #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1) | |
24 | #define L_STF 8 | |
25 | #define L_LTF 8 | |
26 | #define L_SIG 4 | |
27 | #define HT_SIG 8 | |
28 | #define HT_STF 4 | |
29 | #define HT_LTF(_ns) (4 * (_ns)) | |
30 | #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */ | |
31 | #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */ | |
32 | #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2) | |
33 | #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18) | |
34 | ||
35 | #define OFDM_SIFS_TIME 16 | |
36 | ||
37 | static u32 bits_per_symbol[][2] = { | |
38 | /* 20MHz 40MHz */ | |
39 | { 26, 54 }, /* 0: BPSK */ | |
40 | { 52, 108 }, /* 1: QPSK 1/2 */ | |
41 | { 78, 162 }, /* 2: QPSK 3/4 */ | |
42 | { 104, 216 }, /* 3: 16-QAM 1/2 */ | |
43 | { 156, 324 }, /* 4: 16-QAM 3/4 */ | |
44 | { 208, 432 }, /* 5: 64-QAM 2/3 */ | |
45 | { 234, 486 }, /* 6: 64-QAM 3/4 */ | |
46 | { 260, 540 }, /* 7: 64-QAM 5/6 */ | |
47 | { 52, 108 }, /* 8: BPSK */ | |
48 | { 104, 216 }, /* 9: QPSK 1/2 */ | |
49 | { 156, 324 }, /* 10: QPSK 3/4 */ | |
50 | { 208, 432 }, /* 11: 16-QAM 1/2 */ | |
51 | { 312, 648 }, /* 12: 16-QAM 3/4 */ | |
52 | { 416, 864 }, /* 13: 64-QAM 2/3 */ | |
53 | { 468, 972 }, /* 14: 64-QAM 3/4 */ | |
54 | { 520, 1080 }, /* 15: 64-QAM 5/6 */ | |
55 | }; | |
56 | ||
57 | #define IS_HT_RATE(_rate) ((_rate) & 0x80) | |
58 | ||
c37452b0 S |
59 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
60 | struct ath_atx_tid *tid, | |
61 | struct list_head *bf_head); | |
e8324357 | 62 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
63 | struct ath_txq *txq, struct list_head *bf_q, |
64 | struct ath_tx_status *ts, int txok, int sendbar); | |
102e0572 | 65 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
e8324357 S |
66 | struct list_head *head); |
67 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf); | |
0934af23 | 68 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
69 | struct ath_tx_status *ts, int txok); |
70 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, | |
8a92e2ee | 71 | int nbad, int txok, bool update_rc); |
c4288390 | 72 | |
545750d3 FF |
73 | enum { |
74 | MCS_DEFAULT, | |
75 | MCS_HT40, | |
76 | MCS_HT40_SGI, | |
77 | }; | |
78 | ||
79 | static int ath_max_4ms_framelen[3][16] = { | |
80 | [MCS_DEFAULT] = { | |
81 | 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180, | |
82 | 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320, | |
83 | }, | |
84 | [MCS_HT40] = { | |
85 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840, | |
86 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600, | |
87 | }, | |
88 | [MCS_HT40_SGI] = { | |
89 | /* TODO: Only MCS 7 and 15 updated, recalculate the rest */ | |
90 | 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200, | |
91 | 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400, | |
92 | } | |
93 | }; | |
94 | ||
95 | ||
e8324357 S |
96 | /*********************/ |
97 | /* Aggregation logic */ | |
98 | /*********************/ | |
f078f209 | 99 | |
e8324357 | 100 | static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid) |
ff37e337 | 101 | { |
e8324357 | 102 | struct ath_atx_ac *ac = tid->ac; |
ff37e337 | 103 | |
e8324357 S |
104 | if (tid->paused) |
105 | return; | |
ff37e337 | 106 | |
e8324357 S |
107 | if (tid->sched) |
108 | return; | |
ff37e337 | 109 | |
e8324357 S |
110 | tid->sched = true; |
111 | list_add_tail(&tid->list, &ac->tid_q); | |
528f0c6b | 112 | |
e8324357 S |
113 | if (ac->sched) |
114 | return; | |
f078f209 | 115 | |
e8324357 S |
116 | ac->sched = true; |
117 | list_add_tail(&ac->list, &txq->axq_acq); | |
118 | } | |
f078f209 | 119 | |
e8324357 S |
120 | static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
121 | { | |
122 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; | |
f078f209 | 123 | |
e8324357 S |
124 | spin_lock_bh(&txq->axq_lock); |
125 | tid->paused++; | |
126 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 LR |
127 | } |
128 | ||
e8324357 | 129 | static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
f078f209 | 130 | { |
e8324357 | 131 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
e6a9854b | 132 | |
9680e8a3 | 133 | BUG_ON(tid->paused <= 0); |
e8324357 | 134 | spin_lock_bh(&txq->axq_lock); |
f078f209 | 135 | |
e8324357 | 136 | tid->paused--; |
f078f209 | 137 | |
e8324357 S |
138 | if (tid->paused > 0) |
139 | goto unlock; | |
f078f209 | 140 | |
e8324357 S |
141 | if (list_empty(&tid->buf_q)) |
142 | goto unlock; | |
f078f209 | 143 | |
e8324357 S |
144 | ath_tx_queue_tid(txq, tid); |
145 | ath_txq_schedule(sc, txq); | |
146 | unlock: | |
147 | spin_unlock_bh(&txq->axq_lock); | |
528f0c6b | 148 | } |
f078f209 | 149 | |
e8324357 | 150 | static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid) |
528f0c6b | 151 | { |
e8324357 S |
152 | struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum]; |
153 | struct ath_buf *bf; | |
154 | struct list_head bf_head; | |
155 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 156 | |
9680e8a3 | 157 | BUG_ON(tid->paused <= 0); |
e8324357 | 158 | spin_lock_bh(&txq->axq_lock); |
e6a9854b | 159 | |
e8324357 | 160 | tid->paused--; |
f078f209 | 161 | |
e8324357 S |
162 | if (tid->paused > 0) { |
163 | spin_unlock_bh(&txq->axq_lock); | |
164 | return; | |
165 | } | |
f078f209 | 166 | |
e8324357 S |
167 | while (!list_empty(&tid->buf_q)) { |
168 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
9680e8a3 | 169 | BUG_ON(bf_isretried(bf)); |
d43f3015 | 170 | list_move_tail(&bf->list, &bf_head); |
c37452b0 | 171 | ath_tx_send_ht_normal(sc, txq, tid, &bf_head); |
528f0c6b | 172 | } |
f078f209 | 173 | |
e8324357 | 174 | spin_unlock_bh(&txq->axq_lock); |
528f0c6b | 175 | } |
f078f209 | 176 | |
e8324357 S |
177 | static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
178 | int seqno) | |
528f0c6b | 179 | { |
e8324357 | 180 | int index, cindex; |
f078f209 | 181 | |
e8324357 S |
182 | index = ATH_BA_INDEX(tid->seq_start, seqno); |
183 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 184 | |
e8324357 | 185 | tid->tx_buf[cindex] = NULL; |
528f0c6b | 186 | |
e8324357 S |
187 | while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) { |
188 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
189 | INCR(tid->baw_head, ATH_TID_MAX_BUFS); | |
190 | } | |
528f0c6b | 191 | } |
f078f209 | 192 | |
e8324357 S |
193 | static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid, |
194 | struct ath_buf *bf) | |
528f0c6b | 195 | { |
e8324357 | 196 | int index, cindex; |
528f0c6b | 197 | |
e8324357 S |
198 | if (bf_isretried(bf)) |
199 | return; | |
528f0c6b | 200 | |
e8324357 S |
201 | index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno); |
202 | cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1); | |
f078f209 | 203 | |
9680e8a3 | 204 | BUG_ON(tid->tx_buf[cindex] != NULL); |
e8324357 | 205 | tid->tx_buf[cindex] = bf; |
f078f209 | 206 | |
e8324357 S |
207 | if (index >= ((tid->baw_tail - tid->baw_head) & |
208 | (ATH_TID_MAX_BUFS - 1))) { | |
209 | tid->baw_tail = cindex; | |
210 | INCR(tid->baw_tail, ATH_TID_MAX_BUFS); | |
f078f209 | 211 | } |
f078f209 LR |
212 | } |
213 | ||
214 | /* | |
e8324357 S |
215 | * TODO: For frame(s) that are in the retry state, we will reuse the |
216 | * sequence number(s) without setting the retry bit. The | |
217 | * alternative is to give up on these and BAR the receiver's window | |
218 | * forward. | |
f078f209 | 219 | */ |
e8324357 S |
220 | static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq, |
221 | struct ath_atx_tid *tid) | |
f078f209 | 222 | |
f078f209 | 223 | { |
e8324357 S |
224 | struct ath_buf *bf; |
225 | struct list_head bf_head; | |
db1a052b FF |
226 | struct ath_tx_status ts; |
227 | ||
228 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 229 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 230 | |
e8324357 S |
231 | for (;;) { |
232 | if (list_empty(&tid->buf_q)) | |
233 | break; | |
f078f209 | 234 | |
d43f3015 S |
235 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); |
236 | list_move_tail(&bf->list, &bf_head); | |
f078f209 | 237 | |
e8324357 S |
238 | if (bf_isretried(bf)) |
239 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
f078f209 | 240 | |
e8324357 | 241 | spin_unlock(&txq->axq_lock); |
db1a052b | 242 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
e8324357 S |
243 | spin_lock(&txq->axq_lock); |
244 | } | |
f078f209 | 245 | |
e8324357 S |
246 | tid->seq_next = tid->seq_start; |
247 | tid->baw_tail = tid->baw_head; | |
f078f209 LR |
248 | } |
249 | ||
fec247c0 S |
250 | static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq, |
251 | struct ath_buf *bf) | |
f078f209 | 252 | { |
e8324357 S |
253 | struct sk_buff *skb; |
254 | struct ieee80211_hdr *hdr; | |
f078f209 | 255 | |
e8324357 S |
256 | bf->bf_state.bf_type |= BUF_RETRY; |
257 | bf->bf_retries++; | |
fec247c0 | 258 | TX_STAT_INC(txq->axq_qnum, a_retries); |
f078f209 | 259 | |
e8324357 S |
260 | skb = bf->bf_mpdu; |
261 | hdr = (struct ieee80211_hdr *)skb->data; | |
262 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY); | |
f078f209 LR |
263 | } |
264 | ||
d43f3015 S |
265 | static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf) |
266 | { | |
267 | struct ath_buf *tbf; | |
268 | ||
269 | spin_lock_bh(&sc->tx.txbuflock); | |
8a46097a VT |
270 | if (WARN_ON(list_empty(&sc->tx.txbuf))) { |
271 | spin_unlock_bh(&sc->tx.txbuflock); | |
272 | return NULL; | |
273 | } | |
d43f3015 S |
274 | tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
275 | list_del(&tbf->list); | |
276 | spin_unlock_bh(&sc->tx.txbuflock); | |
277 | ||
278 | ATH_TXBUF_RESET(tbf); | |
279 | ||
827e69bf | 280 | tbf->aphy = bf->aphy; |
d43f3015 S |
281 | tbf->bf_mpdu = bf->bf_mpdu; |
282 | tbf->bf_buf_addr = bf->bf_buf_addr; | |
d826c832 | 283 | memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len); |
d43f3015 S |
284 | tbf->bf_state = bf->bf_state; |
285 | tbf->bf_dmacontext = bf->bf_dmacontext; | |
286 | ||
287 | return tbf; | |
288 | } | |
289 | ||
290 | static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq, | |
291 | struct ath_buf *bf, struct list_head *bf_q, | |
db1a052b | 292 | struct ath_tx_status *ts, int txok) |
f078f209 | 293 | { |
e8324357 S |
294 | struct ath_node *an = NULL; |
295 | struct sk_buff *skb; | |
1286ec6d | 296 | struct ieee80211_sta *sta; |
76d5a9e8 | 297 | struct ieee80211_hw *hw; |
1286ec6d | 298 | struct ieee80211_hdr *hdr; |
76d5a9e8 | 299 | struct ieee80211_tx_info *tx_info; |
e8324357 | 300 | struct ath_atx_tid *tid = NULL; |
d43f3015 | 301 | struct ath_buf *bf_next, *bf_last = bf->bf_lastbf; |
e8324357 | 302 | struct list_head bf_head, bf_pending; |
0934af23 | 303 | u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0; |
f078f209 | 304 | u32 ba[WME_BA_BMP_SIZE >> 5]; |
0934af23 VT |
305 | int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0; |
306 | bool rc_update = true; | |
f078f209 | 307 | |
a22be22a | 308 | skb = bf->bf_mpdu; |
1286ec6d S |
309 | hdr = (struct ieee80211_hdr *)skb->data; |
310 | ||
76d5a9e8 | 311 | tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 312 | hw = bf->aphy->hw; |
76d5a9e8 | 313 | |
1286ec6d | 314 | rcu_read_lock(); |
f078f209 | 315 | |
5ed176e1 | 316 | /* XXX: use ieee80211_find_sta! */ |
76d5a9e8 | 317 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr1); |
1286ec6d S |
318 | if (!sta) { |
319 | rcu_read_unlock(); | |
320 | return; | |
f078f209 LR |
321 | } |
322 | ||
1286ec6d S |
323 | an = (struct ath_node *)sta->drv_priv; |
324 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
325 | ||
e8324357 | 326 | isaggr = bf_isaggr(bf); |
d43f3015 | 327 | memset(ba, 0, WME_BA_BMP_SIZE >> 3); |
f078f209 | 328 | |
d43f3015 | 329 | if (isaggr && txok) { |
db1a052b FF |
330 | if (ts->ts_flags & ATH9K_TX_BA) { |
331 | seq_st = ts->ts_seqnum; | |
332 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 333 | } else { |
d43f3015 S |
334 | /* |
335 | * AR5416 can become deaf/mute when BA | |
336 | * issue happens. Chip needs to be reset. | |
337 | * But AP code may have sychronization issues | |
338 | * when perform internal reset in this routine. | |
339 | * Only enable reset in STA mode for now. | |
340 | */ | |
2660b81a | 341 | if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) |
d43f3015 | 342 | needreset = 1; |
e8324357 | 343 | } |
f078f209 LR |
344 | } |
345 | ||
e8324357 S |
346 | INIT_LIST_HEAD(&bf_pending); |
347 | INIT_LIST_HEAD(&bf_head); | |
f078f209 | 348 | |
db1a052b | 349 | nbad = ath_tx_num_badfrms(sc, bf, ts, txok); |
e8324357 S |
350 | while (bf) { |
351 | txfail = txpending = 0; | |
352 | bf_next = bf->bf_next; | |
f078f209 | 353 | |
e8324357 S |
354 | if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) { |
355 | /* transmit completion, subframe is | |
356 | * acked by block ack */ | |
0934af23 | 357 | acked_cnt++; |
e8324357 S |
358 | } else if (!isaggr && txok) { |
359 | /* transmit completion */ | |
0934af23 | 360 | acked_cnt++; |
e8324357 | 361 | } else { |
e8324357 | 362 | if (!(tid->state & AGGR_CLEANUP) && |
6d913f7d | 363 | !bf_last->bf_tx_aborted) { |
e8324357 | 364 | if (bf->bf_retries < ATH_MAX_SW_RETRIES) { |
fec247c0 | 365 | ath_tx_set_retry(sc, txq, bf); |
e8324357 S |
366 | txpending = 1; |
367 | } else { | |
368 | bf->bf_state.bf_type |= BUF_XRETRY; | |
369 | txfail = 1; | |
370 | sendbar = 1; | |
0934af23 | 371 | txfail_cnt++; |
e8324357 S |
372 | } |
373 | } else { | |
374 | /* | |
375 | * cleanup in progress, just fail | |
376 | * the un-acked sub-frames | |
377 | */ | |
378 | txfail = 1; | |
379 | } | |
380 | } | |
f078f209 | 381 | |
e8324357 | 382 | if (bf_next == NULL) { |
cbfe89c6 VT |
383 | /* |
384 | * Make sure the last desc is reclaimed if it | |
385 | * not a holding desc. | |
386 | */ | |
387 | if (!bf_last->bf_stale) | |
388 | list_move_tail(&bf->list, &bf_head); | |
389 | else | |
390 | INIT_LIST_HEAD(&bf_head); | |
e8324357 | 391 | } else { |
9680e8a3 | 392 | BUG_ON(list_empty(bf_q)); |
d43f3015 | 393 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 394 | } |
f078f209 | 395 | |
e8324357 S |
396 | if (!txpending) { |
397 | /* | |
398 | * complete the acked-ones/xretried ones; update | |
399 | * block-ack window | |
400 | */ | |
401 | spin_lock_bh(&txq->axq_lock); | |
402 | ath_tx_update_baw(sc, tid, bf->bf_seqno); | |
403 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 404 | |
8a92e2ee | 405 | if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) { |
db1a052b | 406 | ath_tx_rc_status(bf, ts, nbad, txok, true); |
8a92e2ee VT |
407 | rc_update = false; |
408 | } else { | |
db1a052b | 409 | ath_tx_rc_status(bf, ts, nbad, txok, false); |
8a92e2ee VT |
410 | } |
411 | ||
db1a052b FF |
412 | ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, |
413 | !txfail, sendbar); | |
e8324357 | 414 | } else { |
d43f3015 | 415 | /* retry the un-acked ones */ |
a119cc49 | 416 | if (bf->bf_next == NULL && bf_last->bf_stale) { |
e8324357 | 417 | struct ath_buf *tbf; |
f078f209 | 418 | |
d43f3015 | 419 | tbf = ath_clone_txbuf(sc, bf_last); |
c41d92dc VT |
420 | /* |
421 | * Update tx baw and complete the frame with | |
422 | * failed status if we run out of tx buf | |
423 | */ | |
424 | if (!tbf) { | |
425 | spin_lock_bh(&txq->axq_lock); | |
426 | ath_tx_update_baw(sc, tid, | |
427 | bf->bf_seqno); | |
428 | spin_unlock_bh(&txq->axq_lock); | |
429 | ||
430 | bf->bf_state.bf_type |= BUF_XRETRY; | |
db1a052b | 431 | ath_tx_rc_status(bf, ts, nbad, |
c41d92dc | 432 | 0, false); |
fec247c0 | 433 | ath_tx_complete_buf(sc, bf, txq, |
db1a052b | 434 | &bf_head, ts, 0, 0); |
8a46097a | 435 | break; |
c41d92dc VT |
436 | } |
437 | ||
d43f3015 | 438 | ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc); |
e8324357 S |
439 | list_add_tail(&tbf->list, &bf_head); |
440 | } else { | |
441 | /* | |
442 | * Clear descriptor status words for | |
443 | * software retry | |
444 | */ | |
d43f3015 | 445 | ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc); |
e8324357 S |
446 | } |
447 | ||
448 | /* | |
449 | * Put this buffer to the temporary pending | |
450 | * queue to retain ordering | |
451 | */ | |
452 | list_splice_tail_init(&bf_head, &bf_pending); | |
453 | } | |
454 | ||
455 | bf = bf_next; | |
f078f209 | 456 | } |
f078f209 | 457 | |
e8324357 | 458 | if (tid->state & AGGR_CLEANUP) { |
e8324357 S |
459 | if (tid->baw_head == tid->baw_tail) { |
460 | tid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 461 | tid->state &= ~AGGR_CLEANUP; |
e63835b0 | 462 | |
e8324357 S |
463 | /* send buffered frames as singles */ |
464 | ath_tx_flush_tid(sc, tid); | |
d43f3015 | 465 | } |
1286ec6d | 466 | rcu_read_unlock(); |
e8324357 S |
467 | return; |
468 | } | |
f078f209 | 469 | |
d43f3015 | 470 | /* prepend un-acked frames to the beginning of the pending frame queue */ |
e8324357 S |
471 | if (!list_empty(&bf_pending)) { |
472 | spin_lock_bh(&txq->axq_lock); | |
473 | list_splice(&bf_pending, &tid->buf_q); | |
474 | ath_tx_queue_tid(txq, tid); | |
475 | spin_unlock_bh(&txq->axq_lock); | |
476 | } | |
102e0572 | 477 | |
1286ec6d S |
478 | rcu_read_unlock(); |
479 | ||
e8324357 S |
480 | if (needreset) |
481 | ath_reset(sc, false); | |
e8324357 | 482 | } |
f078f209 | 483 | |
e8324357 S |
484 | static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf, |
485 | struct ath_atx_tid *tid) | |
f078f209 | 486 | { |
528f0c6b S |
487 | struct sk_buff *skb; |
488 | struct ieee80211_tx_info *tx_info; | |
a8efee4f | 489 | struct ieee80211_tx_rate *rates; |
d43f3015 | 490 | u32 max_4ms_framelen, frmlen; |
4ef70841 | 491 | u16 aggr_limit, legacy = 0; |
e8324357 | 492 | int i; |
528f0c6b | 493 | |
a22be22a | 494 | skb = bf->bf_mpdu; |
528f0c6b | 495 | tx_info = IEEE80211_SKB_CB(skb); |
e63835b0 | 496 | rates = tx_info->control.rates; |
528f0c6b | 497 | |
e8324357 S |
498 | /* |
499 | * Find the lowest frame length among the rate series that will have a | |
500 | * 4ms transmit duration. | |
501 | * TODO - TXOP limit needs to be considered. | |
502 | */ | |
503 | max_4ms_framelen = ATH_AMPDU_LIMIT_MAX; | |
e63835b0 | 504 | |
e8324357 S |
505 | for (i = 0; i < 4; i++) { |
506 | if (rates[i].count) { | |
545750d3 FF |
507 | int modeidx; |
508 | if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) { | |
e8324357 S |
509 | legacy = 1; |
510 | break; | |
511 | } | |
512 | ||
545750d3 FF |
513 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) |
514 | modeidx = MCS_HT40_SGI; | |
515 | else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) | |
516 | modeidx = MCS_HT40; | |
517 | else | |
518 | modeidx = MCS_DEFAULT; | |
519 | ||
520 | frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx]; | |
d43f3015 | 521 | max_4ms_framelen = min(max_4ms_framelen, frmlen); |
f078f209 LR |
522 | } |
523 | } | |
e63835b0 | 524 | |
f078f209 | 525 | /* |
e8324357 S |
526 | * limit aggregate size by the minimum rate if rate selected is |
527 | * not a probe rate, if rate selected is a probe rate then | |
528 | * avoid aggregation of this packet. | |
f078f209 | 529 | */ |
e8324357 S |
530 | if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy) |
531 | return 0; | |
f078f209 | 532 | |
1773912b VT |
533 | if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED) |
534 | aggr_limit = min((max_4ms_framelen * 3) / 8, | |
535 | (u32)ATH_AMPDU_LIMIT_MAX); | |
536 | else | |
537 | aggr_limit = min(max_4ms_framelen, | |
538 | (u32)ATH_AMPDU_LIMIT_MAX); | |
f078f209 | 539 | |
e8324357 S |
540 | /* |
541 | * h/w can accept aggregates upto 16 bit lengths (65535). | |
542 | * The IE, however can hold upto 65536, which shows up here | |
543 | * as zero. Ignore 65536 since we are constrained by hw. | |
f078f209 | 544 | */ |
4ef70841 S |
545 | if (tid->an->maxampdu) |
546 | aggr_limit = min(aggr_limit, tid->an->maxampdu); | |
f078f209 | 547 | |
e8324357 S |
548 | return aggr_limit; |
549 | } | |
f078f209 | 550 | |
e8324357 | 551 | /* |
d43f3015 | 552 | * Returns the number of delimiters to be added to |
e8324357 | 553 | * meet the minimum required mpdudensity. |
e8324357 S |
554 | */ |
555 | static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid, | |
556 | struct ath_buf *bf, u16 frmlen) | |
557 | { | |
e8324357 S |
558 | struct sk_buff *skb = bf->bf_mpdu; |
559 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
4ef70841 | 560 | u32 nsymbits, nsymbols; |
e8324357 | 561 | u16 minlen; |
545750d3 | 562 | u8 flags, rix; |
e8324357 S |
563 | int width, half_gi, ndelim, mindelim; |
564 | ||
565 | /* Select standard number of delimiters based on frame length alone */ | |
566 | ndelim = ATH_AGGR_GET_NDELIM(frmlen); | |
f078f209 LR |
567 | |
568 | /* | |
e8324357 S |
569 | * If encryption enabled, hardware requires some more padding between |
570 | * subframes. | |
571 | * TODO - this could be improved to be dependent on the rate. | |
572 | * The hardware can keep up at lower rates, but not higher rates | |
f078f209 | 573 | */ |
e8324357 S |
574 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) |
575 | ndelim += ATH_AGGR_ENCRYPTDELIM; | |
f078f209 | 576 | |
e8324357 S |
577 | /* |
578 | * Convert desired mpdu density from microeconds to bytes based | |
579 | * on highest rate in rate series (i.e. first rate) to determine | |
580 | * required minimum length for subframe. Take into account | |
581 | * whether high rate is 20 or 40Mhz and half or full GI. | |
4ef70841 | 582 | * |
e8324357 S |
583 | * If there is no mpdu density restriction, no further calculation |
584 | * is needed. | |
585 | */ | |
4ef70841 S |
586 | |
587 | if (tid->an->mpdudensity == 0) | |
e8324357 | 588 | return ndelim; |
f078f209 | 589 | |
e8324357 S |
590 | rix = tx_info->control.rates[0].idx; |
591 | flags = tx_info->control.rates[0].flags; | |
e8324357 S |
592 | width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0; |
593 | half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0; | |
f078f209 | 594 | |
e8324357 | 595 | if (half_gi) |
4ef70841 | 596 | nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity); |
e8324357 | 597 | else |
4ef70841 | 598 | nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity); |
f078f209 | 599 | |
e8324357 S |
600 | if (nsymbols == 0) |
601 | nsymbols = 1; | |
f078f209 | 602 | |
545750d3 | 603 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 | 604 | minlen = (nsymbols * nsymbits) / BITS_PER_BYTE; |
f078f209 | 605 | |
e8324357 | 606 | if (frmlen < minlen) { |
e8324357 S |
607 | mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ; |
608 | ndelim = max(mindelim, ndelim); | |
f078f209 LR |
609 | } |
610 | ||
e8324357 | 611 | return ndelim; |
f078f209 LR |
612 | } |
613 | ||
e8324357 | 614 | static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc, |
fec247c0 | 615 | struct ath_txq *txq, |
d43f3015 S |
616 | struct ath_atx_tid *tid, |
617 | struct list_head *bf_q) | |
f078f209 | 618 | { |
e8324357 | 619 | #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4) |
d43f3015 S |
620 | struct ath_buf *bf, *bf_first, *bf_prev = NULL; |
621 | int rl = 0, nframes = 0, ndelim, prev_al = 0; | |
e8324357 S |
622 | u16 aggr_limit = 0, al = 0, bpad = 0, |
623 | al_delta, h_baw = tid->baw_size / 2; | |
624 | enum ATH_AGGR_STATUS status = ATH_AGGR_DONE; | |
f078f209 | 625 | |
e8324357 | 626 | bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list); |
f078f209 | 627 | |
e8324357 S |
628 | do { |
629 | bf = list_first_entry(&tid->buf_q, struct ath_buf, list); | |
f078f209 | 630 | |
d43f3015 | 631 | /* do not step over block-ack window */ |
e8324357 S |
632 | if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) { |
633 | status = ATH_AGGR_BAW_CLOSED; | |
634 | break; | |
635 | } | |
f078f209 | 636 | |
e8324357 S |
637 | if (!rl) { |
638 | aggr_limit = ath_lookup_rate(sc, bf, tid); | |
639 | rl = 1; | |
640 | } | |
f078f209 | 641 | |
d43f3015 | 642 | /* do not exceed aggregation limit */ |
e8324357 | 643 | al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen; |
f078f209 | 644 | |
d43f3015 S |
645 | if (nframes && |
646 | (aggr_limit < (al + bpad + al_delta + prev_al))) { | |
e8324357 S |
647 | status = ATH_AGGR_LIMITED; |
648 | break; | |
649 | } | |
f078f209 | 650 | |
d43f3015 S |
651 | /* do not exceed subframe limit */ |
652 | if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) { | |
e8324357 S |
653 | status = ATH_AGGR_LIMITED; |
654 | break; | |
655 | } | |
d43f3015 | 656 | nframes++; |
f078f209 | 657 | |
d43f3015 | 658 | /* add padding for previous frame to aggregation length */ |
e8324357 | 659 | al += bpad + al_delta; |
f078f209 | 660 | |
e8324357 S |
661 | /* |
662 | * Get the delimiters needed to meet the MPDU | |
663 | * density for this node. | |
664 | */ | |
665 | ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen); | |
e8324357 | 666 | bpad = PADBYTES(al_delta) + (ndelim << 2); |
f078f209 | 667 | |
e8324357 | 668 | bf->bf_next = NULL; |
87d5efbb | 669 | ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0); |
f078f209 | 670 | |
d43f3015 | 671 | /* link buffers of this frame to the aggregate */ |
e8324357 | 672 | ath_tx_addto_baw(sc, tid, bf); |
d43f3015 S |
673 | ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim); |
674 | list_move_tail(&bf->list, bf_q); | |
e8324357 S |
675 | if (bf_prev) { |
676 | bf_prev->bf_next = bf; | |
87d5efbb VT |
677 | ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc, |
678 | bf->bf_daddr); | |
e8324357 S |
679 | } |
680 | bf_prev = bf; | |
fec247c0 | 681 | |
e8324357 | 682 | } while (!list_empty(&tid->buf_q)); |
f078f209 | 683 | |
e8324357 S |
684 | bf_first->bf_al = al; |
685 | bf_first->bf_nframes = nframes; | |
d43f3015 | 686 | |
e8324357 S |
687 | return status; |
688 | #undef PADBYTES | |
689 | } | |
f078f209 | 690 | |
e8324357 S |
691 | static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq, |
692 | struct ath_atx_tid *tid) | |
693 | { | |
d43f3015 | 694 | struct ath_buf *bf; |
e8324357 S |
695 | enum ATH_AGGR_STATUS status; |
696 | struct list_head bf_q; | |
f078f209 | 697 | |
e8324357 S |
698 | do { |
699 | if (list_empty(&tid->buf_q)) | |
700 | return; | |
f078f209 | 701 | |
e8324357 S |
702 | INIT_LIST_HEAD(&bf_q); |
703 | ||
fec247c0 | 704 | status = ath_tx_form_aggr(sc, txq, tid, &bf_q); |
f078f209 | 705 | |
f078f209 | 706 | /* |
d43f3015 S |
707 | * no frames picked up to be aggregated; |
708 | * block-ack window is not open. | |
f078f209 | 709 | */ |
e8324357 S |
710 | if (list_empty(&bf_q)) |
711 | break; | |
f078f209 | 712 | |
e8324357 | 713 | bf = list_first_entry(&bf_q, struct ath_buf, list); |
d43f3015 | 714 | bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list); |
f078f209 | 715 | |
d43f3015 | 716 | /* if only one frame, send as non-aggregate */ |
e8324357 | 717 | if (bf->bf_nframes == 1) { |
e8324357 | 718 | bf->bf_state.bf_type &= ~BUF_AGGR; |
d43f3015 | 719 | ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc); |
e8324357 S |
720 | ath_buf_set_rate(sc, bf); |
721 | ath_tx_txqaddbuf(sc, txq, &bf_q); | |
722 | continue; | |
723 | } | |
f078f209 | 724 | |
d43f3015 | 725 | /* setup first desc of aggregate */ |
e8324357 S |
726 | bf->bf_state.bf_type |= BUF_AGGR; |
727 | ath_buf_set_rate(sc, bf); | |
728 | ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al); | |
f078f209 | 729 | |
d43f3015 S |
730 | /* anchor last desc of aggregate */ |
731 | ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc); | |
f078f209 | 732 | |
e8324357 | 733 | ath_tx_txqaddbuf(sc, txq, &bf_q); |
fec247c0 | 734 | TX_STAT_INC(txq->axq_qnum, a_aggr); |
f078f209 | 735 | |
e8324357 S |
736 | } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH && |
737 | status != ATH_AGGR_BAW_CLOSED); | |
738 | } | |
739 | ||
f83da965 S |
740 | void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
741 | u16 tid, u16 *ssn) | |
e8324357 S |
742 | { |
743 | struct ath_atx_tid *txtid; | |
744 | struct ath_node *an; | |
745 | ||
746 | an = (struct ath_node *)sta->drv_priv; | |
f83da965 S |
747 | txtid = ATH_AN_2_TID(an, tid); |
748 | txtid->state |= AGGR_ADDBA_PROGRESS; | |
749 | ath_tx_pause_tid(sc, txtid); | |
750 | *ssn = txtid->seq_start; | |
e8324357 | 751 | } |
f078f209 | 752 | |
f83da965 | 753 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
e8324357 S |
754 | { |
755 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
756 | struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid); | |
757 | struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum]; | |
db1a052b | 758 | struct ath_tx_status ts; |
e8324357 S |
759 | struct ath_buf *bf; |
760 | struct list_head bf_head; | |
db1a052b FF |
761 | |
762 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 763 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 764 | |
e8324357 | 765 | if (txtid->state & AGGR_CLEANUP) |
f83da965 | 766 | return; |
f078f209 | 767 | |
e8324357 | 768 | if (!(txtid->state & AGGR_ADDBA_COMPLETE)) { |
5eae6592 | 769 | txtid->state &= ~AGGR_ADDBA_PROGRESS; |
f83da965 | 770 | return; |
e8324357 | 771 | } |
f078f209 | 772 | |
e8324357 S |
773 | ath_tx_pause_tid(sc, txtid); |
774 | ||
775 | /* drop all software retried frames and mark this TID */ | |
776 | spin_lock_bh(&txq->axq_lock); | |
777 | while (!list_empty(&txtid->buf_q)) { | |
778 | bf = list_first_entry(&txtid->buf_q, struct ath_buf, list); | |
779 | if (!bf_isretried(bf)) { | |
780 | /* | |
781 | * NB: it's based on the assumption that | |
782 | * software retried frame will always stay | |
783 | * at the head of software queue. | |
784 | */ | |
785 | break; | |
786 | } | |
d43f3015 | 787 | list_move_tail(&bf->list, &bf_head); |
e8324357 | 788 | ath_tx_update_baw(sc, txtid, bf->bf_seqno); |
db1a052b | 789 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 | 790 | } |
d43f3015 | 791 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 792 | |
e8324357 | 793 | if (txtid->baw_head != txtid->baw_tail) { |
e8324357 S |
794 | txtid->state |= AGGR_CLEANUP; |
795 | } else { | |
796 | txtid->state &= ~AGGR_ADDBA_COMPLETE; | |
e8324357 | 797 | ath_tx_flush_tid(sc, txtid); |
f078f209 | 798 | } |
e8324357 | 799 | } |
f078f209 | 800 | |
e8324357 S |
801 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid) |
802 | { | |
803 | struct ath_atx_tid *txtid; | |
804 | struct ath_node *an; | |
805 | ||
806 | an = (struct ath_node *)sta->drv_priv; | |
807 | ||
808 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
809 | txtid = ATH_AN_2_TID(an, tid); | |
810 | txtid->baw_size = | |
811 | IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor; | |
812 | txtid->state |= AGGR_ADDBA_COMPLETE; | |
813 | txtid->state &= ~AGGR_ADDBA_PROGRESS; | |
814 | ath_tx_resume_tid(sc, txtid); | |
815 | } | |
f078f209 LR |
816 | } |
817 | ||
e8324357 | 818 | bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno) |
c4288390 | 819 | { |
e8324357 | 820 | struct ath_atx_tid *txtid; |
c4288390 | 821 | |
e8324357 S |
822 | if (!(sc->sc_flags & SC_OP_TXAGGR)) |
823 | return false; | |
c4288390 | 824 | |
e8324357 S |
825 | txtid = ATH_AN_2_TID(an, tidno); |
826 | ||
c3d8f02e | 827 | if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS))) |
e8324357 | 828 | return true; |
e8324357 | 829 | return false; |
c4288390 S |
830 | } |
831 | ||
e8324357 S |
832 | /********************/ |
833 | /* Queue Management */ | |
834 | /********************/ | |
f078f209 | 835 | |
e8324357 S |
836 | static void ath_txq_drain_pending_buffers(struct ath_softc *sc, |
837 | struct ath_txq *txq) | |
f078f209 | 838 | { |
e8324357 S |
839 | struct ath_atx_ac *ac, *ac_tmp; |
840 | struct ath_atx_tid *tid, *tid_tmp; | |
f078f209 | 841 | |
e8324357 S |
842 | list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) { |
843 | list_del(&ac->list); | |
844 | ac->sched = false; | |
845 | list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) { | |
846 | list_del(&tid->list); | |
847 | tid->sched = false; | |
848 | ath_tid_drain(sc, txq, tid); | |
849 | } | |
f078f209 LR |
850 | } |
851 | } | |
852 | ||
e8324357 | 853 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) |
f078f209 | 854 | { |
cbe61d8a | 855 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 856 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 S |
857 | struct ath9k_tx_queue_info qi; |
858 | int qnum; | |
f078f209 | 859 | |
e8324357 S |
860 | memset(&qi, 0, sizeof(qi)); |
861 | qi.tqi_subtype = subtype; | |
862 | qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT; | |
863 | qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT; | |
864 | qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT; | |
865 | qi.tqi_physCompBuf = 0; | |
f078f209 LR |
866 | |
867 | /* | |
e8324357 S |
868 | * Enable interrupts only for EOL and DESC conditions. |
869 | * We mark tx descriptors to receive a DESC interrupt | |
870 | * when a tx queue gets deep; otherwise waiting for the | |
871 | * EOL to reap descriptors. Note that this is done to | |
872 | * reduce interrupt load and this only defers reaping | |
873 | * descriptors, never transmitting frames. Aside from | |
874 | * reducing interrupts this also permits more concurrency. | |
875 | * The only potential downside is if the tx queue backs | |
876 | * up in which case the top half of the kernel may backup | |
877 | * due to a lack of tx descriptors. | |
878 | * | |
879 | * The UAPSD queue is an exception, since we take a desc- | |
880 | * based intr on the EOSP frames. | |
f078f209 | 881 | */ |
e8324357 S |
882 | if (qtype == ATH9K_TX_QUEUE_UAPSD) |
883 | qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; | |
884 | else | |
885 | qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | | |
886 | TXQ_FLAG_TXDESCINT_ENABLE; | |
887 | qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi); | |
888 | if (qnum == -1) { | |
f078f209 | 889 | /* |
e8324357 S |
890 | * NB: don't print a message, this happens |
891 | * normally on parts with too few tx queues | |
f078f209 | 892 | */ |
e8324357 | 893 | return NULL; |
f078f209 | 894 | } |
e8324357 | 895 | if (qnum >= ARRAY_SIZE(sc->tx.txq)) { |
c46917bb LR |
896 | ath_print(common, ATH_DBG_FATAL, |
897 | "qnum %u out of range, max %u!\n", | |
898 | qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); | |
e8324357 S |
899 | ath9k_hw_releasetxqueue(ah, qnum); |
900 | return NULL; | |
901 | } | |
902 | if (!ATH_TXQ_SETUP(sc, qnum)) { | |
903 | struct ath_txq *txq = &sc->tx.txq[qnum]; | |
f078f209 | 904 | |
e8324357 S |
905 | txq->axq_qnum = qnum; |
906 | txq->axq_link = NULL; | |
907 | INIT_LIST_HEAD(&txq->axq_q); | |
908 | INIT_LIST_HEAD(&txq->axq_acq); | |
909 | spin_lock_init(&txq->axq_lock); | |
910 | txq->axq_depth = 0; | |
164ace38 | 911 | txq->axq_tx_inprogress = false; |
e8324357 S |
912 | sc->tx.txqsetup |= 1<<qnum; |
913 | } | |
914 | return &sc->tx.txq[qnum]; | |
f078f209 LR |
915 | } |
916 | ||
1773912b | 917 | int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype) |
f078f209 | 918 | { |
e8324357 | 919 | int qnum; |
f078f209 | 920 | |
e8324357 S |
921 | switch (qtype) { |
922 | case ATH9K_TX_QUEUE_DATA: | |
923 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { | |
c46917bb LR |
924 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
925 | "HAL AC %u out of range, max %zu!\n", | |
926 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); | |
e8324357 S |
927 | return -1; |
928 | } | |
929 | qnum = sc->tx.hwq_map[haltype]; | |
930 | break; | |
931 | case ATH9K_TX_QUEUE_BEACON: | |
932 | qnum = sc->beacon.beaconq; | |
933 | break; | |
934 | case ATH9K_TX_QUEUE_CAB: | |
935 | qnum = sc->beacon.cabq->axq_qnum; | |
936 | break; | |
937 | default: | |
938 | qnum = -1; | |
939 | } | |
940 | return qnum; | |
941 | } | |
f078f209 | 942 | |
e8324357 S |
943 | struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb) |
944 | { | |
945 | struct ath_txq *txq = NULL; | |
f52de03b | 946 | u16 skb_queue = skb_get_queue_mapping(skb); |
e8324357 | 947 | int qnum; |
f078f209 | 948 | |
f52de03b | 949 | qnum = ath_get_hal_qnum(skb_queue, sc); |
e8324357 | 950 | txq = &sc->tx.txq[qnum]; |
f078f209 | 951 | |
e8324357 S |
952 | spin_lock_bh(&txq->axq_lock); |
953 | ||
954 | if (txq->axq_depth >= (ATH_TXBUF - 20)) { | |
c46917bb LR |
955 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT, |
956 | "TX queue: %d is full, depth: %d\n", | |
957 | qnum, txq->axq_depth); | |
f52de03b | 958 | ath_mac80211_stop_queue(sc, skb_queue); |
e8324357 S |
959 | txq->stopped = 1; |
960 | spin_unlock_bh(&txq->axq_lock); | |
961 | return NULL; | |
f078f209 LR |
962 | } |
963 | ||
e8324357 S |
964 | spin_unlock_bh(&txq->axq_lock); |
965 | ||
966 | return txq; | |
967 | } | |
968 | ||
969 | int ath_txq_update(struct ath_softc *sc, int qnum, | |
970 | struct ath9k_tx_queue_info *qinfo) | |
971 | { | |
cbe61d8a | 972 | struct ath_hw *ah = sc->sc_ah; |
e8324357 S |
973 | int error = 0; |
974 | struct ath9k_tx_queue_info qi; | |
975 | ||
976 | if (qnum == sc->beacon.beaconq) { | |
977 | /* | |
978 | * XXX: for beacon queue, we just save the parameter. | |
979 | * It will be picked up by ath_beaconq_config when | |
980 | * it's necessary. | |
981 | */ | |
982 | sc->beacon.beacon_qi = *qinfo; | |
f078f209 | 983 | return 0; |
e8324357 | 984 | } |
f078f209 | 985 | |
9680e8a3 | 986 | BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum); |
e8324357 S |
987 | |
988 | ath9k_hw_get_txq_props(ah, qnum, &qi); | |
989 | qi.tqi_aifs = qinfo->tqi_aifs; | |
990 | qi.tqi_cwmin = qinfo->tqi_cwmin; | |
991 | qi.tqi_cwmax = qinfo->tqi_cwmax; | |
992 | qi.tqi_burstTime = qinfo->tqi_burstTime; | |
993 | qi.tqi_readyTime = qinfo->tqi_readyTime; | |
994 | ||
995 | if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { | |
c46917bb LR |
996 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
997 | "Unable to update hardware queue %u!\n", qnum); | |
e8324357 S |
998 | error = -EIO; |
999 | } else { | |
1000 | ath9k_hw_resettxqueue(ah, qnum); | |
1001 | } | |
1002 | ||
1003 | return error; | |
1004 | } | |
1005 | ||
1006 | int ath_cabq_update(struct ath_softc *sc) | |
1007 | { | |
1008 | struct ath9k_tx_queue_info qi; | |
1009 | int qnum = sc->beacon.cabq->axq_qnum; | |
f078f209 | 1010 | |
e8324357 | 1011 | ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi); |
f078f209 | 1012 | /* |
e8324357 | 1013 | * Ensure the readytime % is within the bounds. |
f078f209 | 1014 | */ |
17d7904d S |
1015 | if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND) |
1016 | sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND; | |
1017 | else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND) | |
1018 | sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND; | |
f078f209 | 1019 | |
57c4d7b4 | 1020 | qi.tqi_readyTime = (sc->beacon_interval * |
fdbf7335 | 1021 | sc->config.cabqReadytime) / 100; |
e8324357 S |
1022 | ath_txq_update(sc, qnum, &qi); |
1023 | ||
1024 | return 0; | |
f078f209 LR |
1025 | } |
1026 | ||
043a0405 S |
1027 | /* |
1028 | * Drain a given TX queue (could be Beacon or Data) | |
1029 | * | |
1030 | * This assumes output has been stopped and | |
1031 | * we do not need to block ath_tx_tasklet. | |
1032 | */ | |
1033 | void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx) | |
f078f209 | 1034 | { |
e8324357 S |
1035 | struct ath_buf *bf, *lastbf; |
1036 | struct list_head bf_head; | |
db1a052b FF |
1037 | struct ath_tx_status ts; |
1038 | ||
1039 | memset(&ts, 0, sizeof(ts)); | |
e8324357 | 1040 | INIT_LIST_HEAD(&bf_head); |
f078f209 | 1041 | |
e8324357 S |
1042 | for (;;) { |
1043 | spin_lock_bh(&txq->axq_lock); | |
f078f209 | 1044 | |
e8324357 S |
1045 | if (list_empty(&txq->axq_q)) { |
1046 | txq->axq_link = NULL; | |
e8324357 S |
1047 | spin_unlock_bh(&txq->axq_lock); |
1048 | break; | |
1049 | } | |
f078f209 | 1050 | |
e8324357 | 1051 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
f078f209 | 1052 | |
a119cc49 | 1053 | if (bf->bf_stale) { |
e8324357 S |
1054 | list_del(&bf->list); |
1055 | spin_unlock_bh(&txq->axq_lock); | |
f078f209 | 1056 | |
e8324357 S |
1057 | spin_lock_bh(&sc->tx.txbuflock); |
1058 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1059 | spin_unlock_bh(&sc->tx.txbuflock); | |
1060 | continue; | |
1061 | } | |
f078f209 | 1062 | |
e8324357 | 1063 | lastbf = bf->bf_lastbf; |
6d913f7d VT |
1064 | if (!retry_tx) |
1065 | lastbf->bf_tx_aborted = true; | |
f078f209 | 1066 | |
e8324357 S |
1067 | /* remove ath_buf's of the same mpdu from txq */ |
1068 | list_cut_position(&bf_head, &txq->axq_q, &lastbf->list); | |
1069 | txq->axq_depth--; | |
f078f209 | 1070 | |
e8324357 S |
1071 | spin_unlock_bh(&txq->axq_lock); |
1072 | ||
1073 | if (bf_isampdu(bf)) | |
db1a052b | 1074 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0); |
e8324357 | 1075 | else |
db1a052b | 1076 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0); |
f078f209 LR |
1077 | } |
1078 | ||
164ace38 SB |
1079 | spin_lock_bh(&txq->axq_lock); |
1080 | txq->axq_tx_inprogress = false; | |
1081 | spin_unlock_bh(&txq->axq_lock); | |
1082 | ||
e8324357 S |
1083 | /* flush any pending frames if aggregation is enabled */ |
1084 | if (sc->sc_flags & SC_OP_TXAGGR) { | |
1085 | if (!retry_tx) { | |
1086 | spin_lock_bh(&txq->axq_lock); | |
1087 | ath_txq_drain_pending_buffers(sc, txq); | |
1088 | spin_unlock_bh(&txq->axq_lock); | |
1089 | } | |
1090 | } | |
f078f209 LR |
1091 | } |
1092 | ||
043a0405 | 1093 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx) |
f078f209 | 1094 | { |
cbe61d8a | 1095 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1096 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
043a0405 S |
1097 | struct ath_txq *txq; |
1098 | int i, npend = 0; | |
1099 | ||
1100 | if (sc->sc_flags & SC_OP_INVALID) | |
1101 | return; | |
1102 | ||
1103 | /* Stop beacon queue */ | |
1104 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1105 | ||
1106 | /* Stop data queues */ | |
1107 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1108 | if (ATH_TXQ_SETUP(sc, i)) { | |
1109 | txq = &sc->tx.txq[i]; | |
1110 | ath9k_hw_stoptxdma(ah, txq->axq_qnum); | |
1111 | npend += ath9k_hw_numtxpending(ah, txq->axq_qnum); | |
1112 | } | |
1113 | } | |
1114 | ||
1115 | if (npend) { | |
1116 | int r; | |
1117 | ||
e8009e98 | 1118 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 1119 | "Unable to stop TxDMA. Reset HAL!\n"); |
043a0405 S |
1120 | |
1121 | spin_lock_bh(&sc->sc_resetlock); | |
e8009e98 | 1122 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
043a0405 | 1123 | if (r) |
c46917bb LR |
1124 | ath_print(common, ATH_DBG_FATAL, |
1125 | "Unable to reset hardware; reset status %d\n", | |
1126 | r); | |
043a0405 S |
1127 | spin_unlock_bh(&sc->sc_resetlock); |
1128 | } | |
1129 | ||
1130 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1131 | if (ATH_TXQ_SETUP(sc, i)) | |
1132 | ath_draintxq(sc, &sc->tx.txq[i], retry_tx); | |
1133 | } | |
e8324357 | 1134 | } |
f078f209 | 1135 | |
043a0405 | 1136 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) |
e8324357 | 1137 | { |
043a0405 S |
1138 | ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum); |
1139 | sc->tx.txqsetup &= ~(1<<txq->axq_qnum); | |
e8324357 | 1140 | } |
f078f209 | 1141 | |
e8324357 S |
1142 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq) |
1143 | { | |
1144 | struct ath_atx_ac *ac; | |
1145 | struct ath_atx_tid *tid; | |
f078f209 | 1146 | |
e8324357 S |
1147 | if (list_empty(&txq->axq_acq)) |
1148 | return; | |
f078f209 | 1149 | |
e8324357 S |
1150 | ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list); |
1151 | list_del(&ac->list); | |
1152 | ac->sched = false; | |
f078f209 | 1153 | |
e8324357 S |
1154 | do { |
1155 | if (list_empty(&ac->tid_q)) | |
1156 | return; | |
f078f209 | 1157 | |
e8324357 S |
1158 | tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list); |
1159 | list_del(&tid->list); | |
1160 | tid->sched = false; | |
f078f209 | 1161 | |
e8324357 S |
1162 | if (tid->paused) |
1163 | continue; | |
f078f209 | 1164 | |
164ace38 | 1165 | ath_tx_sched_aggr(sc, txq, tid); |
f078f209 LR |
1166 | |
1167 | /* | |
e8324357 S |
1168 | * add tid to round-robin queue if more frames |
1169 | * are pending for the tid | |
f078f209 | 1170 | */ |
e8324357 S |
1171 | if (!list_empty(&tid->buf_q)) |
1172 | ath_tx_queue_tid(txq, tid); | |
f078f209 | 1173 | |
e8324357 S |
1174 | break; |
1175 | } while (!list_empty(&ac->tid_q)); | |
f078f209 | 1176 | |
e8324357 S |
1177 | if (!list_empty(&ac->tid_q)) { |
1178 | if (!ac->sched) { | |
1179 | ac->sched = true; | |
1180 | list_add_tail(&ac->list, &txq->axq_acq); | |
f078f209 | 1181 | } |
e8324357 S |
1182 | } |
1183 | } | |
f078f209 | 1184 | |
e8324357 S |
1185 | int ath_tx_setup(struct ath_softc *sc, int haltype) |
1186 | { | |
1187 | struct ath_txq *txq; | |
f078f209 | 1188 | |
e8324357 | 1189 | if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { |
c46917bb LR |
1190 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1191 | "HAL AC %u out of range, max %zu!\n", | |
e8324357 S |
1192 | haltype, ARRAY_SIZE(sc->tx.hwq_map)); |
1193 | return 0; | |
1194 | } | |
1195 | txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype); | |
1196 | if (txq != NULL) { | |
1197 | sc->tx.hwq_map[haltype] = txq->axq_qnum; | |
1198 | return 1; | |
1199 | } else | |
1200 | return 0; | |
f078f209 LR |
1201 | } |
1202 | ||
e8324357 S |
1203 | /***********/ |
1204 | /* TX, DMA */ | |
1205 | /***********/ | |
1206 | ||
f078f209 | 1207 | /* |
e8324357 S |
1208 | * Insert a chain of ath_buf (descriptors) on a txq and |
1209 | * assume the descriptors are already chained together by caller. | |
f078f209 | 1210 | */ |
e8324357 S |
1211 | static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq, |
1212 | struct list_head *head) | |
f078f209 | 1213 | { |
cbe61d8a | 1214 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1215 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1216 | struct ath_buf *bf; |
f078f209 | 1217 | |
e8324357 S |
1218 | /* |
1219 | * Insert the frame on the outbound list and | |
1220 | * pass it on to the hardware. | |
1221 | */ | |
f078f209 | 1222 | |
e8324357 S |
1223 | if (list_empty(head)) |
1224 | return; | |
f078f209 | 1225 | |
e8324357 | 1226 | bf = list_first_entry(head, struct ath_buf, list); |
f078f209 | 1227 | |
e8324357 S |
1228 | list_splice_tail_init(head, &txq->axq_q); |
1229 | txq->axq_depth++; | |
f078f209 | 1230 | |
c46917bb LR |
1231 | ath_print(common, ATH_DBG_QUEUE, |
1232 | "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); | |
f078f209 | 1233 | |
e8324357 S |
1234 | if (txq->axq_link == NULL) { |
1235 | ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); | |
c46917bb LR |
1236 | ath_print(common, ATH_DBG_XMIT, |
1237 | "TXDP[%u] = %llx (%p)\n", | |
1238 | txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 S |
1239 | } else { |
1240 | *txq->axq_link = bf->bf_daddr; | |
c46917bb LR |
1241 | ath_print(common, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", |
1242 | txq->axq_qnum, txq->axq_link, | |
1243 | ito64(bf->bf_daddr), bf->bf_desc); | |
e8324357 | 1244 | } |
5c3a338f | 1245 | ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc, &txq->axq_link); |
e8324357 S |
1246 | ath9k_hw_txstart(ah, txq->axq_qnum); |
1247 | } | |
f078f209 | 1248 | |
e8324357 S |
1249 | static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc) |
1250 | { | |
1251 | struct ath_buf *bf = NULL; | |
f078f209 | 1252 | |
e8324357 | 1253 | spin_lock_bh(&sc->tx.txbuflock); |
f078f209 | 1254 | |
e8324357 S |
1255 | if (unlikely(list_empty(&sc->tx.txbuf))) { |
1256 | spin_unlock_bh(&sc->tx.txbuflock); | |
1257 | return NULL; | |
1258 | } | |
f078f209 | 1259 | |
e8324357 S |
1260 | bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list); |
1261 | list_del(&bf->list); | |
f078f209 | 1262 | |
e8324357 | 1263 | spin_unlock_bh(&sc->tx.txbuflock); |
f078f209 | 1264 | |
e8324357 | 1265 | return bf; |
f078f209 LR |
1266 | } |
1267 | ||
e8324357 S |
1268 | static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid, |
1269 | struct list_head *bf_head, | |
1270 | struct ath_tx_control *txctl) | |
f078f209 LR |
1271 | { |
1272 | struct ath_buf *bf; | |
f078f209 | 1273 | |
e8324357 S |
1274 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1275 | bf->bf_state.bf_type |= BUF_AMPDU; | |
fec247c0 | 1276 | TX_STAT_INC(txctl->txq->axq_qnum, a_queued); |
f078f209 | 1277 | |
e8324357 S |
1278 | /* |
1279 | * Do not queue to h/w when any of the following conditions is true: | |
1280 | * - there are pending frames in software queue | |
1281 | * - the TID is currently paused for ADDBA/BAR request | |
1282 | * - seqno is not within block-ack window | |
1283 | * - h/w queue depth exceeds low water mark | |
1284 | */ | |
1285 | if (!list_empty(&tid->buf_q) || tid->paused || | |
1286 | !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) || | |
1287 | txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) { | |
f078f209 | 1288 | /* |
e8324357 S |
1289 | * Add this frame to software queue for scheduling later |
1290 | * for aggregation. | |
f078f209 | 1291 | */ |
d43f3015 | 1292 | list_move_tail(&bf->list, &tid->buf_q); |
e8324357 S |
1293 | ath_tx_queue_tid(txctl->txq, tid); |
1294 | return; | |
1295 | } | |
1296 | ||
1297 | /* Add sub-frame to BAW */ | |
1298 | ath_tx_addto_baw(sc, tid, bf); | |
1299 | ||
1300 | /* Queue to h/w without aggregation */ | |
1301 | bf->bf_nframes = 1; | |
d43f3015 | 1302 | bf->bf_lastbf = bf; |
e8324357 S |
1303 | ath_buf_set_rate(sc, bf); |
1304 | ath_tx_txqaddbuf(sc, txctl->txq, bf_head); | |
e8324357 S |
1305 | } |
1306 | ||
c37452b0 S |
1307 | static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq, |
1308 | struct ath_atx_tid *tid, | |
1309 | struct list_head *bf_head) | |
e8324357 S |
1310 | { |
1311 | struct ath_buf *bf; | |
1312 | ||
e8324357 S |
1313 | bf = list_first_entry(bf_head, struct ath_buf, list); |
1314 | bf->bf_state.bf_type &= ~BUF_AMPDU; | |
1315 | ||
1316 | /* update starting sequence number for subsequent ADDBA request */ | |
1317 | INCR(tid->seq_start, IEEE80211_SEQ_MAX); | |
1318 | ||
1319 | bf->bf_nframes = 1; | |
d43f3015 | 1320 | bf->bf_lastbf = bf; |
e8324357 S |
1321 | ath_buf_set_rate(sc, bf); |
1322 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1323 | TX_STAT_INC(txq->axq_qnum, queued); |
e8324357 S |
1324 | } |
1325 | ||
c37452b0 S |
1326 | static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq, |
1327 | struct list_head *bf_head) | |
1328 | { | |
1329 | struct ath_buf *bf; | |
1330 | ||
1331 | bf = list_first_entry(bf_head, struct ath_buf, list); | |
1332 | ||
1333 | bf->bf_lastbf = bf; | |
1334 | bf->bf_nframes = 1; | |
1335 | ath_buf_set_rate(sc, bf); | |
1336 | ath_tx_txqaddbuf(sc, txq, bf_head); | |
fec247c0 | 1337 | TX_STAT_INC(txq->axq_qnum, queued); |
c37452b0 S |
1338 | } |
1339 | ||
e8324357 S |
1340 | static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
1341 | { | |
1342 | struct ieee80211_hdr *hdr; | |
1343 | enum ath9k_pkt_type htype; | |
1344 | __le16 fc; | |
1345 | ||
1346 | hdr = (struct ieee80211_hdr *)skb->data; | |
1347 | fc = hdr->frame_control; | |
1348 | ||
1349 | if (ieee80211_is_beacon(fc)) | |
1350 | htype = ATH9K_PKT_TYPE_BEACON; | |
1351 | else if (ieee80211_is_probe_resp(fc)) | |
1352 | htype = ATH9K_PKT_TYPE_PROBE_RESP; | |
1353 | else if (ieee80211_is_atim(fc)) | |
1354 | htype = ATH9K_PKT_TYPE_ATIM; | |
1355 | else if (ieee80211_is_pspoll(fc)) | |
1356 | htype = ATH9K_PKT_TYPE_PSPOLL; | |
1357 | else | |
1358 | htype = ATH9K_PKT_TYPE_NORMAL; | |
1359 | ||
1360 | return htype; | |
1361 | } | |
1362 | ||
e8324357 S |
1363 | static int get_hw_crypto_keytype(struct sk_buff *skb) |
1364 | { | |
1365 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1366 | ||
1367 | if (tx_info->control.hw_key) { | |
1368 | if (tx_info->control.hw_key->alg == ALG_WEP) | |
1369 | return ATH9K_KEY_TYPE_WEP; | |
1370 | else if (tx_info->control.hw_key->alg == ALG_TKIP) | |
1371 | return ATH9K_KEY_TYPE_TKIP; | |
1372 | else if (tx_info->control.hw_key->alg == ALG_CCMP) | |
1373 | return ATH9K_KEY_TYPE_AES; | |
1374 | } | |
1375 | ||
1376 | return ATH9K_KEY_TYPE_CLEAR; | |
1377 | } | |
1378 | ||
1379 | static void assign_aggr_tid_seqno(struct sk_buff *skb, | |
1380 | struct ath_buf *bf) | |
1381 | { | |
1382 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1383 | struct ieee80211_hdr *hdr; | |
1384 | struct ath_node *an; | |
1385 | struct ath_atx_tid *tid; | |
1386 | __le16 fc; | |
1387 | u8 *qc; | |
1388 | ||
1389 | if (!tx_info->control.sta) | |
1390 | return; | |
1391 | ||
1392 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1393 | hdr = (struct ieee80211_hdr *)skb->data; | |
1394 | fc = hdr->frame_control; | |
1395 | ||
1396 | if (ieee80211_is_data_qos(fc)) { | |
1397 | qc = ieee80211_get_qos_ctl(hdr); | |
1398 | bf->bf_tidno = qc[0] & 0xf; | |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * For HT capable stations, we save tidno for later use. | |
1403 | * We also override seqno set by upper layer with the one | |
1404 | * in tx aggregation state. | |
e8324357 S |
1405 | */ |
1406 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
17b182e3 | 1407 | hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT); |
e8324357 S |
1408 | bf->bf_seqno = tid->seq_next; |
1409 | INCR(tid->seq_next, IEEE80211_SEQ_MAX); | |
1410 | } | |
1411 | ||
1412 | static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb, | |
1413 | struct ath_txq *txq) | |
1414 | { | |
1415 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
1416 | int flags = 0; | |
1417 | ||
1418 | flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */ | |
1419 | flags |= ATH9K_TXDESC_INTREQ; | |
1420 | ||
1421 | if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) | |
1422 | flags |= ATH9K_TXDESC_NOACK; | |
e8324357 S |
1423 | |
1424 | return flags; | |
1425 | } | |
1426 | ||
1427 | /* | |
1428 | * rix - rate index | |
1429 | * pktlen - total bytes (delims + data + fcs + pads + pad delims) | |
1430 | * width - 0 for 20 MHz, 1 for 40 MHz | |
1431 | * half_gi - to use 4us v/s 3.6 us for symbol time | |
1432 | */ | |
1433 | static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf, | |
1434 | int width, int half_gi, bool shortPreamble) | |
1435 | { | |
e8324357 | 1436 | u32 nbits, nsymbits, duration, nsymbols; |
e8324357 S |
1437 | int streams, pktlen; |
1438 | ||
1439 | pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen; | |
e8324357 S |
1440 | |
1441 | /* find number of symbols: PLCP + data */ | |
1442 | nbits = (pktlen << 3) + OFDM_PLCP_BITS; | |
545750d3 | 1443 | nsymbits = bits_per_symbol[rix][width]; |
e8324357 S |
1444 | nsymbols = (nbits + nsymbits - 1) / nsymbits; |
1445 | ||
1446 | if (!half_gi) | |
1447 | duration = SYMBOL_TIME(nsymbols); | |
1448 | else | |
1449 | duration = SYMBOL_TIME_HALFGI(nsymbols); | |
1450 | ||
1451 | /* addup duration for legacy/ht training and signal fields */ | |
545750d3 | 1452 | streams = HT_RC_2_STREAMS(rix); |
e8324357 S |
1453 | duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams); |
1454 | ||
1455 | return duration; | |
1456 | } | |
1457 | ||
1458 | static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf) | |
1459 | { | |
43c27613 | 1460 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 S |
1461 | struct ath9k_11n_rate_series series[4]; |
1462 | struct sk_buff *skb; | |
1463 | struct ieee80211_tx_info *tx_info; | |
1464 | struct ieee80211_tx_rate *rates; | |
545750d3 | 1465 | const struct ieee80211_rate *rate; |
254ad0ff | 1466 | struct ieee80211_hdr *hdr; |
c89424df S |
1467 | int i, flags = 0; |
1468 | u8 rix = 0, ctsrate = 0; | |
254ad0ff | 1469 | bool is_pspoll; |
e8324357 S |
1470 | |
1471 | memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4); | |
1472 | ||
a22be22a | 1473 | skb = bf->bf_mpdu; |
e8324357 S |
1474 | tx_info = IEEE80211_SKB_CB(skb); |
1475 | rates = tx_info->control.rates; | |
254ad0ff S |
1476 | hdr = (struct ieee80211_hdr *)skb->data; |
1477 | is_pspoll = ieee80211_is_pspoll(hdr->frame_control); | |
e8324357 | 1478 | |
e8324357 | 1479 | /* |
c89424df S |
1480 | * We check if Short Preamble is needed for the CTS rate by |
1481 | * checking the BSS's global flag. | |
1482 | * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used. | |
e8324357 | 1483 | */ |
545750d3 FF |
1484 | rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info); |
1485 | ctsrate = rate->hw_value; | |
c89424df | 1486 | if (sc->sc_flags & SC_OP_PREAMBLE_SHORT) |
545750d3 | 1487 | ctsrate |= rate->hw_value_short; |
e8324357 | 1488 | |
e8324357 | 1489 | for (i = 0; i < 4; i++) { |
545750d3 FF |
1490 | bool is_40, is_sgi, is_sp; |
1491 | int phy; | |
1492 | ||
e8324357 S |
1493 | if (!rates[i].count || (rates[i].idx < 0)) |
1494 | continue; | |
1495 | ||
1496 | rix = rates[i].idx; | |
e8324357 | 1497 | series[i].Tries = rates[i].count; |
43c27613 | 1498 | series[i].ChSel = common->tx_chainmask; |
e8324357 | 1499 | |
27032059 FF |
1500 | if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) || |
1501 | (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) { | |
c89424df | 1502 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; |
27032059 FF |
1503 | flags |= ATH9K_TXDESC_RTSENA; |
1504 | } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
1505 | series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS; | |
1506 | flags |= ATH9K_TXDESC_CTSENA; | |
1507 | } | |
1508 | ||
c89424df S |
1509 | if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) |
1510 | series[i].RateFlags |= ATH9K_RATESERIES_2040; | |
1511 | if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI) | |
1512 | series[i].RateFlags |= ATH9K_RATESERIES_HALFGI; | |
e8324357 | 1513 | |
545750d3 FF |
1514 | is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI); |
1515 | is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH); | |
1516 | is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE); | |
1517 | ||
1518 | if (rates[i].flags & IEEE80211_TX_RC_MCS) { | |
1519 | /* MCS rates */ | |
1520 | series[i].Rate = rix | 0x80; | |
1521 | series[i].PktDuration = ath_pkt_duration(sc, rix, bf, | |
1522 | is_40, is_sgi, is_sp); | |
1523 | continue; | |
1524 | } | |
1525 | ||
1526 | /* legcay rates */ | |
1527 | if ((tx_info->band == IEEE80211_BAND_2GHZ) && | |
1528 | !(rate->flags & IEEE80211_RATE_ERP_G)) | |
1529 | phy = WLAN_RC_PHY_CCK; | |
1530 | else | |
1531 | phy = WLAN_RC_PHY_OFDM; | |
1532 | ||
1533 | rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx]; | |
1534 | series[i].Rate = rate->hw_value; | |
1535 | if (rate->hw_value_short) { | |
1536 | if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) | |
1537 | series[i].Rate |= rate->hw_value_short; | |
1538 | } else { | |
1539 | is_sp = false; | |
1540 | } | |
1541 | ||
1542 | series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah, | |
1543 | phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp); | |
f078f209 LR |
1544 | } |
1545 | ||
27032059 FF |
1546 | /* For AR5416 - RTS cannot be followed by a frame larger than 8K */ |
1547 | if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit)) | |
1548 | flags &= ~ATH9K_TXDESC_RTSENA; | |
1549 | ||
1550 | /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */ | |
1551 | if (flags & ATH9K_TXDESC_RTSENA) | |
1552 | flags &= ~ATH9K_TXDESC_CTSENA; | |
1553 | ||
e8324357 | 1554 | /* set dur_update_en for l-sig computation except for PS-Poll frames */ |
c89424df S |
1555 | ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc, |
1556 | bf->bf_lastbf->bf_desc, | |
254ad0ff | 1557 | !is_pspoll, ctsrate, |
c89424df | 1558 | 0, series, 4, flags); |
f078f209 | 1559 | |
17d7904d | 1560 | if (sc->config.ath_aggr_prot && flags) |
c89424df | 1561 | ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192); |
f078f209 LR |
1562 | } |
1563 | ||
c52f33d0 | 1564 | static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf, |
8f93b8b3 | 1565 | struct sk_buff *skb, |
528f0c6b | 1566 | struct ath_tx_control *txctl) |
f078f209 | 1567 | { |
c52f33d0 JM |
1568 | struct ath_wiphy *aphy = hw->priv; |
1569 | struct ath_softc *sc = aphy->sc; | |
528f0c6b S |
1570 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
1571 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; | |
528f0c6b S |
1572 | int hdrlen; |
1573 | __le16 fc; | |
1bc14880 | 1574 | int padpos, padsize; |
e022edbd | 1575 | |
827e69bf FF |
1576 | tx_info->pad[0] = 0; |
1577 | switch (txctl->frame_type) { | |
c81494d5 | 1578 | case ATH9K_IFT_NOT_INTERNAL: |
827e69bf | 1579 | break; |
c81494d5 | 1580 | case ATH9K_IFT_PAUSE: |
827e69bf FF |
1581 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE; |
1582 | /* fall through */ | |
c81494d5 | 1583 | case ATH9K_IFT_UNPAUSE: |
827e69bf FF |
1584 | tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL; |
1585 | break; | |
1586 | } | |
528f0c6b S |
1587 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
1588 | fc = hdr->frame_control; | |
f078f209 | 1589 | |
528f0c6b | 1590 | ATH_TXBUF_RESET(bf); |
f078f209 | 1591 | |
827e69bf | 1592 | bf->aphy = aphy; |
1bc14880 BP |
1593 | bf->bf_frmlen = skb->len + FCS_LEN; |
1594 | /* Remove the padding size from bf_frmlen, if any */ | |
1595 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1596 | padsize = padpos & 3; | |
1597 | if (padsize && skb->len>padpos+padsize) { | |
1598 | bf->bf_frmlen -= padsize; | |
1599 | } | |
cd3d39a6 | 1600 | |
6c8afef5 | 1601 | if (conf_is_ht(&hw->conf)) |
c656bbb5 | 1602 | bf->bf_state.bf_type |= BUF_HT; |
528f0c6b S |
1603 | |
1604 | bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq); | |
1605 | ||
528f0c6b | 1606 | bf->bf_keytype = get_hw_crypto_keytype(skb); |
528f0c6b S |
1607 | if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) { |
1608 | bf->bf_frmlen += tx_info->control.hw_key->icv_len; | |
1609 | bf->bf_keyix = tx_info->control.hw_key->hw_key_idx; | |
1610 | } else { | |
1611 | bf->bf_keyix = ATH9K_TXKEYIX_INVALID; | |
1612 | } | |
1613 | ||
17b182e3 S |
1614 | if (ieee80211_is_data_qos(fc) && bf_isht(bf) && |
1615 | (sc->sc_flags & SC_OP_TXAGGR)) | |
528f0c6b S |
1616 | assign_aggr_tid_seqno(skb, bf); |
1617 | ||
f078f209 | 1618 | bf->bf_mpdu = skb; |
f8316df1 | 1619 | |
7da3c55c GJ |
1620 | bf->bf_dmacontext = dma_map_single(sc->dev, skb->data, |
1621 | skb->len, DMA_TO_DEVICE); | |
1622 | if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) { | |
f8316df1 | 1623 | bf->bf_mpdu = NULL; |
c46917bb LR |
1624 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
1625 | "dma_mapping_error() on TX\n"); | |
f8316df1 LR |
1626 | return -ENOMEM; |
1627 | } | |
1628 | ||
528f0c6b | 1629 | bf->bf_buf_addr = bf->bf_dmacontext; |
e7824a50 LR |
1630 | |
1631 | /* tag if this is a nullfunc frame to enable PS when AP acks it */ | |
1632 | if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) { | |
1633 | bf->bf_isnullfunc = true; | |
1b04b930 | 1634 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
1635 | } else |
1636 | bf->bf_isnullfunc = false; | |
1637 | ||
f8316df1 | 1638 | return 0; |
528f0c6b S |
1639 | } |
1640 | ||
1641 | /* FIXME: tx power */ | |
1642 | static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf, | |
528f0c6b S |
1643 | struct ath_tx_control *txctl) |
1644 | { | |
a22be22a | 1645 | struct sk_buff *skb = bf->bf_mpdu; |
528f0c6b | 1646 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
c37452b0 | 1647 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
528f0c6b S |
1648 | struct ath_node *an = NULL; |
1649 | struct list_head bf_head; | |
1650 | struct ath_desc *ds; | |
1651 | struct ath_atx_tid *tid; | |
cbe61d8a | 1652 | struct ath_hw *ah = sc->sc_ah; |
528f0c6b | 1653 | int frm_type; |
c37452b0 | 1654 | __le16 fc; |
528f0c6b | 1655 | |
528f0c6b | 1656 | frm_type = get_hw_packet_type(skb); |
c37452b0 | 1657 | fc = hdr->frame_control; |
528f0c6b S |
1658 | |
1659 | INIT_LIST_HEAD(&bf_head); | |
1660 | list_add_tail(&bf->list, &bf_head); | |
f078f209 | 1661 | |
f078f209 | 1662 | ds = bf->bf_desc; |
87d5efbb | 1663 | ath9k_hw_set_desc_link(ah, ds, 0); |
f078f209 | 1664 | |
528f0c6b S |
1665 | ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER, |
1666 | bf->bf_keyix, bf->bf_keytype, bf->bf_flags); | |
1667 | ||
1668 | ath9k_hw_filltxdesc(ah, ds, | |
8f93b8b3 S |
1669 | skb->len, /* segment length */ |
1670 | true, /* first segment */ | |
1671 | true, /* last segment */ | |
3f3a1c80 | 1672 | ds, /* first descriptor */ |
cc610ac0 VT |
1673 | bf->bf_buf_addr, |
1674 | txctl->txq->axq_qnum); | |
f078f209 | 1675 | |
528f0c6b | 1676 | spin_lock_bh(&txctl->txq->axq_lock); |
f078f209 | 1677 | |
f1617967 JL |
1678 | if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) && |
1679 | tx_info->control.sta) { | |
1680 | an = (struct ath_node *)tx_info->control.sta->drv_priv; | |
1681 | tid = ATH_AN_2_TID(an, bf->bf_tidno); | |
1682 | ||
c37452b0 S |
1683 | if (!ieee80211_is_data_qos(fc)) { |
1684 | ath_tx_send_normal(sc, txctl->txq, &bf_head); | |
1685 | goto tx_done; | |
1686 | } | |
1687 | ||
4fdec031 | 1688 | if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) { |
f078f209 LR |
1689 | /* |
1690 | * Try aggregation if it's a unicast data frame | |
1691 | * and the destination is HT capable. | |
1692 | */ | |
528f0c6b | 1693 | ath_tx_send_ampdu(sc, tid, &bf_head, txctl); |
f078f209 LR |
1694 | } else { |
1695 | /* | |
528f0c6b S |
1696 | * Send this frame as regular when ADDBA |
1697 | * exchange is neither complete nor pending. | |
f078f209 | 1698 | */ |
c37452b0 S |
1699 | ath_tx_send_ht_normal(sc, txctl->txq, |
1700 | tid, &bf_head); | |
f078f209 LR |
1701 | } |
1702 | } else { | |
c37452b0 | 1703 | ath_tx_send_normal(sc, txctl->txq, &bf_head); |
f078f209 | 1704 | } |
528f0c6b | 1705 | |
c37452b0 | 1706 | tx_done: |
528f0c6b | 1707 | spin_unlock_bh(&txctl->txq->axq_lock); |
f078f209 LR |
1708 | } |
1709 | ||
f8316df1 | 1710 | /* Upon failure caller should free skb */ |
c52f33d0 | 1711 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
528f0c6b | 1712 | struct ath_tx_control *txctl) |
f078f209 | 1713 | { |
c52f33d0 JM |
1714 | struct ath_wiphy *aphy = hw->priv; |
1715 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1716 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1717 | struct ath_buf *bf; |
f8316df1 | 1718 | int r; |
f078f209 | 1719 | |
528f0c6b S |
1720 | bf = ath_tx_get_buffer(sc); |
1721 | if (!bf) { | |
c46917bb | 1722 | ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n"); |
528f0c6b S |
1723 | return -1; |
1724 | } | |
1725 | ||
c52f33d0 | 1726 | r = ath_tx_setup_buffer(hw, bf, skb, txctl); |
f8316df1 | 1727 | if (unlikely(r)) { |
c112d0c5 LR |
1728 | struct ath_txq *txq = txctl->txq; |
1729 | ||
c46917bb | 1730 | ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n"); |
c112d0c5 LR |
1731 | |
1732 | /* upon ath_tx_processq() this TX queue will be resumed, we | |
1733 | * guarantee this will happen by knowing beforehand that | |
1734 | * we will at least have to run TX completionon one buffer | |
1735 | * on the queue */ | |
1736 | spin_lock_bh(&txq->axq_lock); | |
f7a99e46 | 1737 | if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) { |
f52de03b | 1738 | ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb)); |
c112d0c5 LR |
1739 | txq->stopped = 1; |
1740 | } | |
1741 | spin_unlock_bh(&txq->axq_lock); | |
1742 | ||
b77f483f S |
1743 | spin_lock_bh(&sc->tx.txbuflock); |
1744 | list_add_tail(&bf->list, &sc->tx.txbuf); | |
1745 | spin_unlock_bh(&sc->tx.txbuflock); | |
c112d0c5 | 1746 | |
f8316df1 LR |
1747 | return r; |
1748 | } | |
1749 | ||
8f93b8b3 | 1750 | ath_tx_start_dma(sc, bf, txctl); |
f078f209 | 1751 | |
528f0c6b | 1752 | return 0; |
f078f209 LR |
1753 | } |
1754 | ||
c52f33d0 | 1755 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb) |
f078f209 | 1756 | { |
c52f33d0 JM |
1757 | struct ath_wiphy *aphy = hw->priv; |
1758 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1759 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1760 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; |
1761 | int padpos, padsize; | |
e8324357 S |
1762 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
1763 | struct ath_tx_control txctl; | |
f078f209 | 1764 | |
e8324357 | 1765 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 LR |
1766 | |
1767 | /* | |
e8324357 S |
1768 | * As a temporary workaround, assign seq# here; this will likely need |
1769 | * to be cleaned up to work better with Beacon transmission and virtual | |
1770 | * BSSes. | |
f078f209 | 1771 | */ |
e8324357 | 1772 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { |
e8324357 S |
1773 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
1774 | sc->tx.seq_no += 0x10; | |
1775 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); | |
1776 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); | |
f078f209 | 1777 | } |
f078f209 | 1778 | |
e8324357 | 1779 | /* Add the padding after the header if this is not already done */ |
4d91f9f3 BP |
1780 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1781 | padsize = padpos & 3; | |
1782 | if (padsize && skb->len>padpos) { | |
e8324357 | 1783 | if (skb_headroom(skb) < padsize) { |
c46917bb LR |
1784 | ath_print(common, ATH_DBG_XMIT, |
1785 | "TX CABQ padding failed\n"); | |
e8324357 S |
1786 | dev_kfree_skb_any(skb); |
1787 | return; | |
1788 | } | |
1789 | skb_push(skb, padsize); | |
4d91f9f3 | 1790 | memmove(skb->data, skb->data + padsize, padpos); |
f078f209 | 1791 | } |
f078f209 | 1792 | |
e8324357 | 1793 | txctl.txq = sc->beacon.cabq; |
f078f209 | 1794 | |
c46917bb LR |
1795 | ath_print(common, ATH_DBG_XMIT, |
1796 | "transmitting CABQ packet, skb: %p\n", skb); | |
f078f209 | 1797 | |
c52f33d0 | 1798 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1799 | ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n"); |
e8324357 | 1800 | goto exit; |
f078f209 | 1801 | } |
f078f209 | 1802 | |
e8324357 S |
1803 | return; |
1804 | exit: | |
1805 | dev_kfree_skb_any(skb); | |
f078f209 LR |
1806 | } |
1807 | ||
e8324357 S |
1808 | /*****************/ |
1809 | /* TX Completion */ | |
1810 | /*****************/ | |
528f0c6b | 1811 | |
e8324357 | 1812 | static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb, |
827e69bf | 1813 | struct ath_wiphy *aphy, int tx_flags) |
528f0c6b | 1814 | { |
e8324357 S |
1815 | struct ieee80211_hw *hw = sc->hw; |
1816 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); | |
c46917bb | 1817 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
4d91f9f3 BP |
1818 | struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data; |
1819 | int padpos, padsize; | |
528f0c6b | 1820 | |
c46917bb | 1821 | ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); |
528f0c6b | 1822 | |
827e69bf FF |
1823 | if (aphy) |
1824 | hw = aphy->hw; | |
528f0c6b | 1825 | |
6b2c4032 | 1826 | if (tx_flags & ATH_TX_BAR) |
e8324357 | 1827 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; |
e8324357 | 1828 | |
6b2c4032 | 1829 | if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) { |
e8324357 S |
1830 | /* Frame was ACKed */ |
1831 | tx_info->flags |= IEEE80211_TX_STAT_ACK; | |
528f0c6b S |
1832 | } |
1833 | ||
4d91f9f3 BP |
1834 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1835 | padsize = padpos & 3; | |
1836 | if (padsize && skb->len>padpos+padsize) { | |
e8324357 S |
1837 | /* |
1838 | * Remove MAC header padding before giving the frame back to | |
1839 | * mac80211. | |
1840 | */ | |
4d91f9f3 | 1841 | memmove(skb->data + padsize, skb->data, padpos); |
e8324357 S |
1842 | skb_pull(skb, padsize); |
1843 | } | |
528f0c6b | 1844 | |
1b04b930 S |
1845 | if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) { |
1846 | sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK; | |
c46917bb LR |
1847 | ath_print(common, ATH_DBG_PS, |
1848 | "Going back to sleep after having " | |
f643e51d | 1849 | "received TX status (0x%lx)\n", |
1b04b930 S |
1850 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
1851 | PS_WAIT_FOR_CAB | | |
1852 | PS_WAIT_FOR_PSPOLL_DATA | | |
1853 | PS_WAIT_FOR_TX_ACK)); | |
9a23f9ca JM |
1854 | } |
1855 | ||
827e69bf | 1856 | if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL)) |
f0ed85c6 | 1857 | ath9k_tx_status(hw, skb); |
827e69bf FF |
1858 | else |
1859 | ieee80211_tx_status(hw, skb); | |
e8324357 | 1860 | } |
f078f209 | 1861 | |
e8324357 | 1862 | static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b FF |
1863 | struct ath_txq *txq, struct list_head *bf_q, |
1864 | struct ath_tx_status *ts, int txok, int sendbar) | |
f078f209 | 1865 | { |
e8324357 | 1866 | struct sk_buff *skb = bf->bf_mpdu; |
e8324357 | 1867 | unsigned long flags; |
6b2c4032 | 1868 | int tx_flags = 0; |
f078f209 | 1869 | |
e8324357 | 1870 | if (sendbar) |
6b2c4032 | 1871 | tx_flags = ATH_TX_BAR; |
f078f209 | 1872 | |
e8324357 | 1873 | if (!txok) { |
6b2c4032 | 1874 | tx_flags |= ATH_TX_ERROR; |
f078f209 | 1875 | |
e8324357 | 1876 | if (bf_isxretried(bf)) |
6b2c4032 | 1877 | tx_flags |= ATH_TX_XRETRY; |
f078f209 LR |
1878 | } |
1879 | ||
e8324357 | 1880 | dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE); |
827e69bf | 1881 | ath_tx_complete(sc, skb, bf->aphy, tx_flags); |
db1a052b | 1882 | ath_debug_stat_tx(sc, txq, bf, ts); |
e8324357 S |
1883 | |
1884 | /* | |
1885 | * Return the list of ath_buf of this mpdu to free queue | |
1886 | */ | |
1887 | spin_lock_irqsave(&sc->tx.txbuflock, flags); | |
1888 | list_splice_tail_init(bf_q, &sc->tx.txbuf); | |
1889 | spin_unlock_irqrestore(&sc->tx.txbuflock, flags); | |
f078f209 LR |
1890 | } |
1891 | ||
e8324357 | 1892 | static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf, |
db1a052b | 1893 | struct ath_tx_status *ts, int txok) |
f078f209 | 1894 | { |
e8324357 S |
1895 | u16 seq_st = 0; |
1896 | u32 ba[WME_BA_BMP_SIZE >> 5]; | |
1897 | int ba_index; | |
1898 | int nbad = 0; | |
1899 | int isaggr = 0; | |
f078f209 | 1900 | |
6d913f7d | 1901 | if (bf->bf_tx_aborted) |
e8324357 | 1902 | return 0; |
f078f209 | 1903 | |
e8324357 S |
1904 | isaggr = bf_isaggr(bf); |
1905 | if (isaggr) { | |
db1a052b FF |
1906 | seq_st = ts->ts_seqnum; |
1907 | memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3); | |
e8324357 | 1908 | } |
f078f209 | 1909 | |
e8324357 S |
1910 | while (bf) { |
1911 | ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno); | |
1912 | if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index))) | |
1913 | nbad++; | |
1914 | ||
1915 | bf = bf->bf_next; | |
1916 | } | |
f078f209 | 1917 | |
e8324357 S |
1918 | return nbad; |
1919 | } | |
f078f209 | 1920 | |
db1a052b | 1921 | static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts, |
8a92e2ee | 1922 | int nbad, int txok, bool update_rc) |
f078f209 | 1923 | { |
a22be22a | 1924 | struct sk_buff *skb = bf->bf_mpdu; |
254ad0ff | 1925 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
e8324357 | 1926 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
827e69bf | 1927 | struct ieee80211_hw *hw = bf->aphy->hw; |
8a92e2ee | 1928 | u8 i, tx_rateindex; |
f078f209 | 1929 | |
95e4acb7 | 1930 | if (txok) |
db1a052b | 1931 | tx_info->status.ack_signal = ts->ts_rssi; |
95e4acb7 | 1932 | |
db1a052b | 1933 | tx_rateindex = ts->ts_rateindex; |
8a92e2ee VT |
1934 | WARN_ON(tx_rateindex >= hw->max_rates); |
1935 | ||
db1a052b | 1936 | if (ts->ts_status & ATH9K_TXERR_FILT) |
e8324357 | 1937 | tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED; |
d969847c FF |
1938 | if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) |
1939 | tx_info->flags |= IEEE80211_TX_STAT_AMPDU; | |
f078f209 | 1940 | |
db1a052b | 1941 | if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 && |
8a92e2ee | 1942 | (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) { |
254ad0ff | 1943 | if (ieee80211_is_data(hdr->frame_control)) { |
db1a052b | 1944 | if (ts->ts_flags & |
827e69bf FF |
1945 | (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN)) |
1946 | tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN; | |
db1a052b FF |
1947 | if ((ts->ts_status & ATH9K_TXERR_XRETRY) || |
1948 | (ts->ts_status & ATH9K_TXERR_FIFO)) | |
827e69bf FF |
1949 | tx_info->pad[0] |= ATH_TX_INFO_XRETRY; |
1950 | tx_info->status.ampdu_len = bf->bf_nframes; | |
1951 | tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad; | |
e8324357 | 1952 | } |
f078f209 | 1953 | } |
8a92e2ee | 1954 | |
545750d3 | 1955 | for (i = tx_rateindex + 1; i < hw->max_rates; i++) { |
8a92e2ee | 1956 | tx_info->status.rates[i].count = 0; |
545750d3 FF |
1957 | tx_info->status.rates[i].idx = -1; |
1958 | } | |
8a92e2ee VT |
1959 | |
1960 | tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1; | |
f078f209 LR |
1961 | } |
1962 | ||
059d806c S |
1963 | static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq) |
1964 | { | |
1965 | int qnum; | |
1966 | ||
1967 | spin_lock_bh(&txq->axq_lock); | |
1968 | if (txq->stopped && | |
f7a99e46 | 1969 | sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) { |
059d806c S |
1970 | qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc); |
1971 | if (qnum != -1) { | |
f52de03b | 1972 | ath_mac80211_start_queue(sc, qnum); |
059d806c S |
1973 | txq->stopped = 0; |
1974 | } | |
1975 | } | |
1976 | spin_unlock_bh(&txq->axq_lock); | |
1977 | } | |
1978 | ||
e8324357 | 1979 | static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) |
f078f209 | 1980 | { |
cbe61d8a | 1981 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1982 | struct ath_common *common = ath9k_hw_common(ah); |
e8324357 | 1983 | struct ath_buf *bf, *lastbf, *bf_held = NULL; |
f078f209 | 1984 | struct list_head bf_head; |
e8324357 | 1985 | struct ath_desc *ds; |
29bffa96 | 1986 | struct ath_tx_status ts; |
0934af23 | 1987 | int txok; |
e8324357 | 1988 | int status; |
f078f209 | 1989 | |
c46917bb LR |
1990 | ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", |
1991 | txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), | |
1992 | txq->axq_link); | |
f078f209 | 1993 | |
f078f209 LR |
1994 | for (;;) { |
1995 | spin_lock_bh(&txq->axq_lock); | |
f078f209 LR |
1996 | if (list_empty(&txq->axq_q)) { |
1997 | txq->axq_link = NULL; | |
f078f209 LR |
1998 | spin_unlock_bh(&txq->axq_lock); |
1999 | break; | |
2000 | } | |
f078f209 LR |
2001 | bf = list_first_entry(&txq->axq_q, struct ath_buf, list); |
2002 | ||
e8324357 S |
2003 | /* |
2004 | * There is a race condition that a BH gets scheduled | |
2005 | * after sw writes TxE and before hw re-load the last | |
2006 | * descriptor to get the newly chained one. | |
2007 | * Software must keep the last DONE descriptor as a | |
2008 | * holding descriptor - software does so by marking | |
2009 | * it with the STALE flag. | |
2010 | */ | |
2011 | bf_held = NULL; | |
a119cc49 | 2012 | if (bf->bf_stale) { |
e8324357 S |
2013 | bf_held = bf; |
2014 | if (list_is_last(&bf_held->list, &txq->axq_q)) { | |
6ef9b13d | 2015 | spin_unlock_bh(&txq->axq_lock); |
e8324357 S |
2016 | break; |
2017 | } else { | |
2018 | bf = list_entry(bf_held->list.next, | |
6ef9b13d | 2019 | struct ath_buf, list); |
e8324357 | 2020 | } |
f078f209 LR |
2021 | } |
2022 | ||
2023 | lastbf = bf->bf_lastbf; | |
e8324357 | 2024 | ds = lastbf->bf_desc; |
f078f209 | 2025 | |
29bffa96 FF |
2026 | memset(&ts, 0, sizeof(ts)); |
2027 | status = ath9k_hw_txprocdesc(ah, ds, &ts); | |
e8324357 | 2028 | if (status == -EINPROGRESS) { |
f078f209 | 2029 | spin_unlock_bh(&txq->axq_lock); |
e8324357 | 2030 | break; |
f078f209 | 2031 | } |
f078f209 | 2032 | |
e7824a50 LR |
2033 | /* |
2034 | * We now know the nullfunc frame has been ACKed so we | |
2035 | * can disable RX. | |
2036 | */ | |
2037 | if (bf->bf_isnullfunc && | |
29bffa96 | 2038 | (ts.ts_status & ATH9K_TX_ACKED)) { |
3f7c5c10 SB |
2039 | if ((sc->ps_flags & PS_ENABLED)) |
2040 | ath9k_enable_ps(sc); | |
2041 | else | |
1b04b930 | 2042 | sc->ps_flags |= PS_NULLFUNC_COMPLETED; |
e7824a50 LR |
2043 | } |
2044 | ||
e8324357 S |
2045 | /* |
2046 | * Remove ath_buf's of the same transmit unit from txq, | |
2047 | * however leave the last descriptor back as the holding | |
2048 | * descriptor for hw. | |
2049 | */ | |
a119cc49 | 2050 | lastbf->bf_stale = true; |
e8324357 | 2051 | INIT_LIST_HEAD(&bf_head); |
e8324357 S |
2052 | if (!list_is_singular(&lastbf->list)) |
2053 | list_cut_position(&bf_head, | |
2054 | &txq->axq_q, lastbf->list.prev); | |
f078f209 | 2055 | |
e8324357 | 2056 | txq->axq_depth--; |
29bffa96 | 2057 | txok = !(ts.ts_status & ATH9K_TXERR_MASK); |
164ace38 | 2058 | txq->axq_tx_inprogress = false; |
e8324357 | 2059 | spin_unlock_bh(&txq->axq_lock); |
f078f209 | 2060 | |
e8324357 | 2061 | if (bf_held) { |
e8324357 | 2062 | spin_lock_bh(&sc->tx.txbuflock); |
6ef9b13d | 2063 | list_move_tail(&bf_held->list, &sc->tx.txbuf); |
e8324357 S |
2064 | spin_unlock_bh(&sc->tx.txbuflock); |
2065 | } | |
f078f209 | 2066 | |
e8324357 S |
2067 | if (!bf_isampdu(bf)) { |
2068 | /* | |
2069 | * This frame is sent out as a single frame. | |
2070 | * Use hardware retry status for this frame. | |
2071 | */ | |
29bffa96 FF |
2072 | bf->bf_retries = ts.ts_longretry; |
2073 | if (ts.ts_status & ATH9K_TXERR_XRETRY) | |
e8324357 | 2074 | bf->bf_state.bf_type |= BUF_XRETRY; |
29bffa96 | 2075 | ath_tx_rc_status(bf, &ts, 0, txok, true); |
e8324357 | 2076 | } |
f078f209 | 2077 | |
e8324357 | 2078 | if (bf_isampdu(bf)) |
29bffa96 | 2079 | ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok); |
e8324357 | 2080 | else |
29bffa96 | 2081 | ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0); |
8469cdef | 2082 | |
059d806c | 2083 | ath_wake_mac80211_queue(sc, txq); |
8469cdef | 2084 | |
059d806c | 2085 | spin_lock_bh(&txq->axq_lock); |
e8324357 S |
2086 | if (sc->sc_flags & SC_OP_TXAGGR) |
2087 | ath_txq_schedule(sc, txq); | |
2088 | spin_unlock_bh(&txq->axq_lock); | |
8469cdef S |
2089 | } |
2090 | } | |
2091 | ||
305fe47f | 2092 | static void ath_tx_complete_poll_work(struct work_struct *work) |
164ace38 SB |
2093 | { |
2094 | struct ath_softc *sc = container_of(work, struct ath_softc, | |
2095 | tx_complete_work.work); | |
2096 | struct ath_txq *txq; | |
2097 | int i; | |
2098 | bool needreset = false; | |
2099 | ||
2100 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) | |
2101 | if (ATH_TXQ_SETUP(sc, i)) { | |
2102 | txq = &sc->tx.txq[i]; | |
2103 | spin_lock_bh(&txq->axq_lock); | |
2104 | if (txq->axq_depth) { | |
2105 | if (txq->axq_tx_inprogress) { | |
2106 | needreset = true; | |
2107 | spin_unlock_bh(&txq->axq_lock); | |
2108 | break; | |
2109 | } else { | |
2110 | txq->axq_tx_inprogress = true; | |
2111 | } | |
2112 | } | |
2113 | spin_unlock_bh(&txq->axq_lock); | |
2114 | } | |
2115 | ||
2116 | if (needreset) { | |
c46917bb LR |
2117 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET, |
2118 | "tx hung, resetting the chip\n"); | |
332c5566 | 2119 | ath9k_ps_wakeup(sc); |
164ace38 | 2120 | ath_reset(sc, false); |
332c5566 | 2121 | ath9k_ps_restore(sc); |
164ace38 SB |
2122 | } |
2123 | ||
42935eca | 2124 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, |
164ace38 SB |
2125 | msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT)); |
2126 | } | |
2127 | ||
2128 | ||
f078f209 | 2129 | |
e8324357 | 2130 | void ath_tx_tasklet(struct ath_softc *sc) |
f078f209 | 2131 | { |
e8324357 S |
2132 | int i; |
2133 | u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1); | |
f078f209 | 2134 | |
e8324357 | 2135 | ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask); |
f078f209 | 2136 | |
e8324357 S |
2137 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2138 | if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i))) | |
2139 | ath_tx_processq(sc, &sc->tx.txq[i]); | |
f078f209 LR |
2140 | } |
2141 | } | |
2142 | ||
e8324357 S |
2143 | /*****************/ |
2144 | /* Init, Cleanup */ | |
2145 | /*****************/ | |
f078f209 | 2146 | |
e8324357 | 2147 | int ath_tx_init(struct ath_softc *sc, int nbufs) |
f078f209 | 2148 | { |
c46917bb | 2149 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8324357 | 2150 | int error = 0; |
f078f209 | 2151 | |
797fe5cb | 2152 | spin_lock_init(&sc->tx.txbuflock); |
f078f209 | 2153 | |
797fe5cb | 2154 | error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, |
4adfcded | 2155 | "tx", nbufs, 1, 1); |
797fe5cb | 2156 | if (error != 0) { |
c46917bb LR |
2157 | ath_print(common, ATH_DBG_FATAL, |
2158 | "Failed to allocate tx descriptors: %d\n", error); | |
797fe5cb S |
2159 | goto err; |
2160 | } | |
f078f209 | 2161 | |
797fe5cb | 2162 | error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, |
4adfcded | 2163 | "beacon", ATH_BCBUF, 1, 0); |
797fe5cb | 2164 | if (error != 0) { |
c46917bb LR |
2165 | ath_print(common, ATH_DBG_FATAL, |
2166 | "Failed to allocate beacon descriptors: %d\n", error); | |
797fe5cb S |
2167 | goto err; |
2168 | } | |
f078f209 | 2169 | |
164ace38 SB |
2170 | INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work); |
2171 | ||
797fe5cb | 2172 | err: |
e8324357 S |
2173 | if (error != 0) |
2174 | ath_tx_cleanup(sc); | |
f078f209 | 2175 | |
e8324357 | 2176 | return error; |
f078f209 LR |
2177 | } |
2178 | ||
797fe5cb | 2179 | void ath_tx_cleanup(struct ath_softc *sc) |
e8324357 S |
2180 | { |
2181 | if (sc->beacon.bdma.dd_desc_len != 0) | |
2182 | ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf); | |
2183 | ||
2184 | if (sc->tx.txdma.dd_desc_len != 0) | |
2185 | ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf); | |
e8324357 | 2186 | } |
f078f209 LR |
2187 | |
2188 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an) | |
2189 | { | |
c5170163 S |
2190 | struct ath_atx_tid *tid; |
2191 | struct ath_atx_ac *ac; | |
2192 | int tidno, acno; | |
f078f209 | 2193 | |
8ee5afbc | 2194 | for (tidno = 0, tid = &an->tid[tidno]; |
c5170163 S |
2195 | tidno < WME_NUM_TID; |
2196 | tidno++, tid++) { | |
2197 | tid->an = an; | |
2198 | tid->tidno = tidno; | |
2199 | tid->seq_start = tid->seq_next = 0; | |
2200 | tid->baw_size = WME_MAX_BA; | |
2201 | tid->baw_head = tid->baw_tail = 0; | |
2202 | tid->sched = false; | |
e8324357 | 2203 | tid->paused = false; |
a37c2c79 | 2204 | tid->state &= ~AGGR_CLEANUP; |
c5170163 | 2205 | INIT_LIST_HEAD(&tid->buf_q); |
c5170163 | 2206 | acno = TID_TO_WME_AC(tidno); |
8ee5afbc | 2207 | tid->ac = &an->ac[acno]; |
a37c2c79 S |
2208 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
2209 | tid->state &= ~AGGR_ADDBA_PROGRESS; | |
c5170163 | 2210 | } |
f078f209 | 2211 | |
8ee5afbc | 2212 | for (acno = 0, ac = &an->ac[acno]; |
c5170163 S |
2213 | acno < WME_NUM_AC; acno++, ac++) { |
2214 | ac->sched = false; | |
2215 | INIT_LIST_HEAD(&ac->tid_q); | |
2216 | ||
2217 | switch (acno) { | |
2218 | case WME_AC_BE: | |
2219 | ac->qnum = ath_tx_get_qnum(sc, | |
2220 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE); | |
2221 | break; | |
2222 | case WME_AC_BK: | |
2223 | ac->qnum = ath_tx_get_qnum(sc, | |
2224 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK); | |
2225 | break; | |
2226 | case WME_AC_VI: | |
2227 | ac->qnum = ath_tx_get_qnum(sc, | |
2228 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI); | |
2229 | break; | |
2230 | case WME_AC_VO: | |
2231 | ac->qnum = ath_tx_get_qnum(sc, | |
2232 | ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO); | |
2233 | break; | |
f078f209 LR |
2234 | } |
2235 | } | |
2236 | } | |
2237 | ||
b5aa9bf9 | 2238 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an) |
f078f209 LR |
2239 | { |
2240 | int i; | |
2241 | struct ath_atx_ac *ac, *ac_tmp; | |
2242 | struct ath_atx_tid *tid, *tid_tmp; | |
2243 | struct ath_txq *txq; | |
e8324357 | 2244 | |
f078f209 LR |
2245 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { |
2246 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f | 2247 | txq = &sc->tx.txq[i]; |
f078f209 | 2248 | |
a9f042cb | 2249 | spin_lock_bh(&txq->axq_lock); |
f078f209 LR |
2250 | |
2251 | list_for_each_entry_safe(ac, | |
2252 | ac_tmp, &txq->axq_acq, list) { | |
2253 | tid = list_first_entry(&ac->tid_q, | |
2254 | struct ath_atx_tid, list); | |
2255 | if (tid && tid->an != an) | |
2256 | continue; | |
2257 | list_del(&ac->list); | |
2258 | ac->sched = false; | |
2259 | ||
2260 | list_for_each_entry_safe(tid, | |
2261 | tid_tmp, &ac->tid_q, list) { | |
2262 | list_del(&tid->list); | |
2263 | tid->sched = false; | |
b5aa9bf9 | 2264 | ath_tid_drain(sc, txq, tid); |
a37c2c79 | 2265 | tid->state &= ~AGGR_ADDBA_COMPLETE; |
a37c2c79 | 2266 | tid->state &= ~AGGR_CLEANUP; |
f078f209 LR |
2267 | } |
2268 | } | |
2269 | ||
a9f042cb | 2270 | spin_unlock_bh(&txq->axq_lock); |
f078f209 LR |
2271 | } |
2272 | } | |
2273 | } |