Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 | 19 | |
b5c80475 FF |
20 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
21 | ||
102885a5 VT |
22 | static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta, |
23 | int mindelta, int main_rssi_avg, | |
24 | int alt_rssi_avg, int pkt_count) | |
25 | { | |
26 | return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
27 | (alt_rssi_avg > main_rssi_avg + maxdelta)) || | |
28 | (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50); | |
29 | } | |
30 | ||
ededf1f8 VT |
31 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
32 | { | |
33 | return sc->ps_enabled && | |
34 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
35 | } | |
36 | ||
f078f209 LR |
37 | /* |
38 | * Setup and link descriptors. | |
39 | * | |
40 | * 11N: we can no longer afford to self link the last descriptor. | |
41 | * MAC acknowledges BA status as long as it copies frames to host | |
42 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
43 | * to a sender if last desc is self-linked. | |
f078f209 | 44 | */ |
f078f209 LR |
45 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
46 | { | |
cbe61d8a | 47 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 48 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
49 | struct ath_desc *ds; |
50 | struct sk_buff *skb; | |
51 | ||
52 | ATH_RXBUF_RESET(bf); | |
53 | ||
54 | ds = bf->bf_desc; | |
be0418ad | 55 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
56 | ds->ds_data = bf->bf_buf_addr; |
57 | ||
be0418ad | 58 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 59 | skb = bf->bf_mpdu; |
9680e8a3 | 60 | BUG_ON(skb == NULL); |
f078f209 LR |
61 | ds->ds_vdata = skb->data; |
62 | ||
cc861f74 LR |
63 | /* |
64 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 65 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
66 | * to process |
67 | */ | |
b77f483f | 68 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 69 | common->rx_bufsize, |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | } |
79 | ||
ff37e337 S |
80 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
81 | { | |
82 | /* XXX block beacon interrupts */ | |
83 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
84 | sc->rx.defant = antenna; |
85 | sc->rx.rxotherant = 0; | |
ff37e337 S |
86 | } |
87 | ||
f078f209 LR |
88 | static void ath_opmode_init(struct ath_softc *sc) |
89 | { | |
cbe61d8a | 90 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
91 | struct ath_common *common = ath9k_hw_common(ah); |
92 | ||
f078f209 LR |
93 | u32 rfilt, mfilt[2]; |
94 | ||
95 | /* configure rx filter */ | |
96 | rfilt = ath_calcrxfilter(sc); | |
97 | ath9k_hw_setrxfilter(ah, rfilt); | |
98 | ||
99 | /* configure bssid mask */ | |
364734fa | 100 | ath_hw_setbssidmask(common); |
f078f209 LR |
101 | |
102 | /* configure operational mode */ | |
103 | ath9k_hw_setopmode(ah); | |
104 | ||
f078f209 LR |
105 | /* calculate and install multicast filter */ |
106 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 107 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
108 | } |
109 | ||
b5c80475 FF |
110 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
111 | enum ath9k_rx_qtype qtype) | |
f078f209 | 112 | { |
b5c80475 FF |
113 | struct ath_hw *ah = sc->sc_ah; |
114 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
115 | struct sk_buff *skb; |
116 | struct ath_buf *bf; | |
f078f209 | 117 | |
b5c80475 FF |
118 | rx_edma = &sc->rx.rx_edma[qtype]; |
119 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
120 | return false; | |
f078f209 | 121 | |
b5c80475 FF |
122 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
123 | list_del_init(&bf->list); | |
f078f209 | 124 | |
b5c80475 FF |
125 | skb = bf->bf_mpdu; |
126 | ||
127 | ATH_RXBUF_RESET(bf); | |
128 | memset(skb->data, 0, ah->caps.rx_status_len); | |
129 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
130 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 131 | |
b5c80475 FF |
132 | SKB_CB_ATHBUF(skb) = bf; |
133 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
134 | skb_queue_tail(&rx_edma->rx_fifo, skb); | |
f078f209 | 135 | |
b5c80475 FF |
136 | return true; |
137 | } | |
138 | ||
139 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
140 | enum ath9k_rx_qtype qtype, int size) | |
141 | { | |
b5c80475 FF |
142 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
143 | u32 nbuf = 0; | |
144 | ||
b5c80475 | 145 | if (list_empty(&sc->rx.rxbuf)) { |
226afe68 | 146 | ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n"); |
b5c80475 | 147 | return; |
797fe5cb | 148 | } |
f078f209 | 149 | |
b5c80475 FF |
150 | while (!list_empty(&sc->rx.rxbuf)) { |
151 | nbuf++; | |
152 | ||
153 | if (!ath_rx_edma_buf_link(sc, qtype)) | |
154 | break; | |
155 | ||
156 | if (nbuf >= size) | |
157 | break; | |
158 | } | |
159 | } | |
160 | ||
161 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
162 | enum ath9k_rx_qtype qtype) | |
163 | { | |
164 | struct ath_buf *bf; | |
165 | struct ath_rx_edma *rx_edma; | |
166 | struct sk_buff *skb; | |
167 | ||
168 | rx_edma = &sc->rx.rx_edma[qtype]; | |
169 | ||
170 | while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { | |
171 | bf = SKB_CB_ATHBUF(skb); | |
172 | BUG_ON(!bf); | |
173 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
174 | } | |
175 | } | |
176 | ||
177 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
178 | { | |
179 | struct ath_buf *bf; | |
180 | ||
181 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
182 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
183 | ||
797fe5cb | 184 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
b5c80475 FF |
185 | if (bf->bf_mpdu) |
186 | dev_kfree_skb_any(bf->bf_mpdu); | |
187 | } | |
188 | ||
189 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
190 | ||
191 | kfree(sc->rx.rx_bufptr); | |
192 | sc->rx.rx_bufptr = NULL; | |
193 | } | |
194 | ||
195 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
196 | { | |
197 | skb_queue_head_init(&rx_edma->rx_fifo); | |
198 | skb_queue_head_init(&rx_edma->rx_buffers); | |
199 | rx_edma->rx_fifo_hwsize = size; | |
200 | } | |
201 | ||
202 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
203 | { | |
204 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
205 | struct ath_hw *ah = sc->sc_ah; | |
206 | struct sk_buff *skb; | |
207 | struct ath_buf *bf; | |
208 | int error = 0, i; | |
209 | u32 size; | |
210 | ||
b5c80475 FF |
211 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
212 | ah->caps.rx_status_len); | |
213 | ||
214 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
215 | ah->caps.rx_lp_qdepth); | |
216 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
217 | ah->caps.rx_hp_qdepth); | |
218 | ||
219 | size = sizeof(struct ath_buf) * nbufs; | |
220 | bf = kzalloc(size, GFP_KERNEL); | |
221 | if (!bf) | |
222 | return -ENOMEM; | |
223 | ||
224 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
225 | sc->rx.rx_bufptr = bf; | |
226 | ||
227 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 228 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 229 | if (!skb) { |
797fe5cb | 230 | error = -ENOMEM; |
b5c80475 | 231 | goto rx_init_fail; |
f078f209 | 232 | } |
f078f209 | 233 | |
b5c80475 | 234 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 235 | bf->bf_mpdu = skb; |
b5c80475 | 236 | |
797fe5cb | 237 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 238 | common->rx_bufsize, |
b5c80475 | 239 | DMA_BIDIRECTIONAL); |
797fe5cb | 240 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
241 | bf->bf_buf_addr))) { |
242 | dev_kfree_skb_any(skb); | |
243 | bf->bf_mpdu = NULL; | |
6cf9e995 | 244 | bf->bf_buf_addr = 0; |
3800276a | 245 | ath_err(common, |
b5c80475 FF |
246 | "dma_mapping_error() on RX init\n"); |
247 | error = -ENOMEM; | |
248 | goto rx_init_fail; | |
249 | } | |
250 | ||
251 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
252 | } | |
253 | ||
254 | return 0; | |
255 | ||
256 | rx_init_fail: | |
257 | ath_rx_edma_cleanup(sc); | |
258 | return error; | |
259 | } | |
260 | ||
261 | static void ath_edma_start_recv(struct ath_softc *sc) | |
262 | { | |
263 | spin_lock_bh(&sc->rx.rxbuflock); | |
264 | ||
265 | ath9k_hw_rxena(sc->sc_ah); | |
266 | ||
267 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, | |
268 | sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); | |
269 | ||
270 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, | |
271 | sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); | |
272 | ||
b5c80475 FF |
273 | ath_opmode_init(sc); |
274 | ||
48a6a468 | 275 | ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
7583c550 LR |
276 | |
277 | spin_unlock_bh(&sc->rx.rxbuflock); | |
b5c80475 FF |
278 | } |
279 | ||
280 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
281 | { | |
b5c80475 FF |
282 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); |
283 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
b5c80475 FF |
284 | } |
285 | ||
286 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
287 | { | |
288 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
289 | struct sk_buff *skb; | |
290 | struct ath_buf *bf; | |
291 | int error = 0; | |
292 | ||
4bdd1e97 | 293 | spin_lock_init(&sc->sc_pcu_lock); |
b5c80475 FF |
294 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
295 | spin_lock_init(&sc->rx.rxbuflock); | |
296 | ||
0d95521e FF |
297 | common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 + |
298 | sc->sc_ah->caps.rx_status_len; | |
299 | ||
b5c80475 FF |
300 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
301 | return ath_rx_edma_init(sc, nbufs); | |
302 | } else { | |
226afe68 JP |
303 | ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
304 | common->cachelsz, common->rx_bufsize); | |
b5c80475 FF |
305 | |
306 | /* Initialize rx descriptors */ | |
307 | ||
308 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
4adfcded | 309 | "rx", nbufs, 1, 0); |
b5c80475 | 310 | if (error != 0) { |
3800276a JP |
311 | ath_err(common, |
312 | "failed to allocate rx descriptors: %d\n", | |
313 | error); | |
797fe5cb S |
314 | goto err; |
315 | } | |
b5c80475 FF |
316 | |
317 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
318 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
319 | GFP_KERNEL); | |
320 | if (skb == NULL) { | |
321 | error = -ENOMEM; | |
322 | goto err; | |
323 | } | |
324 | ||
325 | bf->bf_mpdu = skb; | |
326 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
327 | common->rx_bufsize, | |
328 | DMA_FROM_DEVICE); | |
329 | if (unlikely(dma_mapping_error(sc->dev, | |
330 | bf->bf_buf_addr))) { | |
331 | dev_kfree_skb_any(skb); | |
332 | bf->bf_mpdu = NULL; | |
6cf9e995 | 333 | bf->bf_buf_addr = 0; |
3800276a JP |
334 | ath_err(common, |
335 | "dma_mapping_error() on RX init\n"); | |
b5c80475 FF |
336 | error = -ENOMEM; |
337 | goto err; | |
338 | } | |
b5c80475 FF |
339 | } |
340 | sc->rx.rxlink = NULL; | |
797fe5cb | 341 | } |
f078f209 | 342 | |
797fe5cb | 343 | err: |
f078f209 LR |
344 | if (error) |
345 | ath_rx_cleanup(sc); | |
346 | ||
347 | return error; | |
348 | } | |
349 | ||
f078f209 LR |
350 | void ath_rx_cleanup(struct ath_softc *sc) |
351 | { | |
cc861f74 LR |
352 | struct ath_hw *ah = sc->sc_ah; |
353 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
354 | struct sk_buff *skb; |
355 | struct ath_buf *bf; | |
356 | ||
b5c80475 FF |
357 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
358 | ath_rx_edma_cleanup(sc); | |
359 | return; | |
360 | } else { | |
361 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
362 | skb = bf->bf_mpdu; | |
363 | if (skb) { | |
364 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
365 | common->rx_bufsize, | |
366 | DMA_FROM_DEVICE); | |
367 | dev_kfree_skb(skb); | |
6cf9e995 BG |
368 | bf->bf_buf_addr = 0; |
369 | bf->bf_mpdu = NULL; | |
b5c80475 | 370 | } |
051b9191 | 371 | } |
f078f209 | 372 | |
b5c80475 FF |
373 | if (sc->rx.rxdma.dd_desc_len != 0) |
374 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
375 | } | |
f078f209 LR |
376 | } |
377 | ||
378 | /* | |
379 | * Calculate the receive filter according to the | |
380 | * operating mode and state: | |
381 | * | |
382 | * o always accept unicast, broadcast, and multicast traffic | |
383 | * o maintain current state of phy error reception (the hal | |
384 | * may enable phy error frames for noise immunity work) | |
385 | * o probe request frames are accepted only when operating in | |
386 | * hostap, adhoc, or monitor modes | |
387 | * o enable promiscuous mode according to the interface state | |
388 | * o accept beacons: | |
389 | * - when operating in adhoc mode so the 802.11 layer creates | |
390 | * node table entries for peers, | |
391 | * - when operating in station mode for collecting rssi data when | |
392 | * the station is otherwise quiet, or | |
393 | * - when operating as a repeater so we see repeater-sta beacons | |
394 | * - when scanning | |
395 | */ | |
396 | ||
397 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
398 | { | |
399 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 400 | |
f078f209 LR |
401 | u32 rfilt; |
402 | ||
403 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
404 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
405 | | ATH9K_RX_FILTER_MCAST; | |
406 | ||
9c1d8e4a | 407 | if (sc->rx.rxfilter & FIF_PROBE_REQ) |
f078f209 LR |
408 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
409 | ||
217ba9da JM |
410 | /* |
411 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
412 | * mode interface or when in monitor mode. AP mode does not need this | |
413 | * since it receives all in-BSS frames anyway. | |
414 | */ | |
2e286947 | 415 | if (sc->sc_ah->is_monitoring) |
f078f209 | 416 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 417 | |
d42c6b71 S |
418 | if (sc->rx.rxfilter & FIF_CONTROL) |
419 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
420 | ||
dbaaa147 | 421 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
cfda6695 | 422 | (sc->nvifs <= 1) && |
dbaaa147 VT |
423 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) |
424 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
425 | else | |
f078f209 LR |
426 | rfilt |= ATH9K_RX_FILTER_BEACON; |
427 | ||
264bbec8 | 428 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
66afad01 | 429 | (sc->rx.rxfilter & FIF_PSPOLL)) |
dbaaa147 | 430 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 431 | |
7ea310be S |
432 | if (conf_is_ht(&sc->hw->conf)) |
433 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
434 | ||
7545daf4 | 435 | if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
5eb6ba83 JC |
436 | /* The following may also be needed for other older chips */ |
437 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
438 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
439 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
440 | } | |
441 | ||
f078f209 | 442 | return rfilt; |
7dcfdcd9 | 443 | |
f078f209 LR |
444 | #undef RX_FILTER_PRESERVE |
445 | } | |
446 | ||
f078f209 LR |
447 | int ath_startrecv(struct ath_softc *sc) |
448 | { | |
cbe61d8a | 449 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
450 | struct ath_buf *bf, *tbf; |
451 | ||
b5c80475 FF |
452 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
453 | ath_edma_start_recv(sc); | |
454 | return 0; | |
455 | } | |
456 | ||
b77f483f S |
457 | spin_lock_bh(&sc->rx.rxbuflock); |
458 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
459 | goto start_recv; |
460 | ||
b77f483f S |
461 | sc->rx.rxlink = NULL; |
462 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
463 | ath_rx_buf_link(sc, bf); |
464 | } | |
465 | ||
466 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 467 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
468 | goto start_recv; |
469 | ||
b77f483f | 470 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 471 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 472 | ath9k_hw_rxena(ah); |
f078f209 LR |
473 | |
474 | start_recv: | |
be0418ad | 475 | ath_opmode_init(sc); |
48a6a468 | 476 | ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL)); |
be0418ad | 477 | |
7583c550 LR |
478 | spin_unlock_bh(&sc->rx.rxbuflock); |
479 | ||
f078f209 LR |
480 | return 0; |
481 | } | |
482 | ||
f078f209 LR |
483 | bool ath_stoprecv(struct ath_softc *sc) |
484 | { | |
cbe61d8a | 485 | struct ath_hw *ah = sc->sc_ah; |
5882da02 | 486 | bool stopped, reset = false; |
f078f209 | 487 | |
1e450285 | 488 | spin_lock_bh(&sc->rx.rxbuflock); |
d47844a0 | 489 | ath9k_hw_abortpcurecv(ah); |
be0418ad | 490 | ath9k_hw_setrxfilter(ah, 0); |
5882da02 | 491 | stopped = ath9k_hw_stopdmarecv(ah, &reset); |
b5c80475 FF |
492 | |
493 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
494 | ath_edma_stop_recv(sc); | |
495 | else | |
496 | sc->rx.rxlink = NULL; | |
1e450285 | 497 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad | 498 | |
d584747b RM |
499 | if (!(ah->ah_flags & AH_UNPLUGGED) && |
500 | unlikely(!stopped)) { | |
d7fd1b50 BG |
501 | ath_err(ath9k_hw_common(sc->sc_ah), |
502 | "Could not stop RX, we could be " | |
503 | "confusing the DMA engine when we start RX up\n"); | |
504 | ATH_DBG_WARN_ON_ONCE(!stopped); | |
505 | } | |
2232d31b | 506 | return stopped && !reset; |
f078f209 LR |
507 | } |
508 | ||
f078f209 LR |
509 | void ath_flushrecv(struct ath_softc *sc) |
510 | { | |
98deeea0 | 511 | sc->sc_flags |= SC_OP_RXFLUSH; |
b5c80475 FF |
512 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
513 | ath_rx_tasklet(sc, 1, true); | |
514 | ath_rx_tasklet(sc, 1, false); | |
98deeea0 | 515 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
f078f209 LR |
516 | } |
517 | ||
cc65965c JM |
518 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
519 | { | |
520 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
521 | struct ieee80211_mgmt *mgmt; | |
522 | u8 *pos, *end, id, elen; | |
523 | struct ieee80211_tim_ie *tim; | |
524 | ||
525 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
526 | pos = mgmt->u.beacon.variable; | |
527 | end = skb->data + skb->len; | |
528 | ||
529 | while (pos + 2 < end) { | |
530 | id = *pos++; | |
531 | elen = *pos++; | |
532 | if (pos + elen > end) | |
533 | break; | |
534 | ||
535 | if (id == WLAN_EID_TIM) { | |
536 | if (elen < sizeof(*tim)) | |
537 | break; | |
538 | tim = (struct ieee80211_tim_ie *) pos; | |
539 | if (tim->dtim_count != 0) | |
540 | break; | |
541 | return tim->bitmap_ctrl & 0x01; | |
542 | } | |
543 | ||
544 | pos += elen; | |
545 | } | |
546 | ||
547 | return false; | |
548 | } | |
549 | ||
cc65965c JM |
550 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
551 | { | |
552 | struct ieee80211_mgmt *mgmt; | |
1510718d | 553 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
554 | |
555 | if (skb->len < 24 + 8 + 2 + 2) | |
556 | return; | |
557 | ||
558 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
4801416c BG |
559 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) { |
560 | /* TODO: This doesn't work well if you have stations | |
561 | * associated to two different APs because curbssid | |
562 | * is just the last AP that any of the stations associated | |
563 | * with. | |
564 | */ | |
cc65965c | 565 | return; /* not from our current AP */ |
4801416c | 566 | } |
cc65965c | 567 | |
1b04b930 | 568 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 569 | |
1b04b930 S |
570 | if (sc->ps_flags & PS_BEACON_SYNC) { |
571 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
226afe68 JP |
572 | ath_dbg(common, ATH_DBG_PS, |
573 | "Reconfigure Beacon timers based on timestamp from the AP\n"); | |
99e4d43a | 574 | ath_set_beacon(sc); |
deb75188 | 575 | sc->ps_flags &= ~PS_TSFOOR_SYNC; |
ccdfeab6 JM |
576 | } |
577 | ||
cc65965c JM |
578 | if (ath_beacon_dtim_pending_cab(skb)) { |
579 | /* | |
580 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
581 | * frames. If the last broadcast/multicast frame is not |
582 | * received properly, the next beacon frame will work as | |
583 | * a backup trigger for returning into NETWORK SLEEP state, | |
584 | * so we are waiting for it as well. | |
cc65965c | 585 | */ |
226afe68 JP |
586 | ath_dbg(common, ATH_DBG_PS, |
587 | "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n"); | |
1b04b930 | 588 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
589 | return; |
590 | } | |
591 | ||
1b04b930 | 592 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
593 | /* |
594 | * This can happen if a broadcast frame is dropped or the AP | |
595 | * fails to send a frame indicating that all CAB frames have | |
596 | * been delivered. | |
597 | */ | |
1b04b930 | 598 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
226afe68 JP |
599 | ath_dbg(common, ATH_DBG_PS, |
600 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 601 | } |
cc65965c JM |
602 | } |
603 | ||
604 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
605 | { | |
606 | struct ieee80211_hdr *hdr; | |
c46917bb | 607 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
608 | |
609 | hdr = (struct ieee80211_hdr *)skb->data; | |
610 | ||
611 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 VT |
612 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
613 | && ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c | 614 | ath_rx_ps_beacon(sc, skb); |
1b04b930 | 615 | else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
cc65965c JM |
616 | (ieee80211_is_data(hdr->frame_control) || |
617 | ieee80211_is_action(hdr->frame_control)) && | |
618 | is_multicast_ether_addr(hdr->addr1) && | |
619 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
620 | /* |
621 | * No more broadcast/multicast frames to be received at this | |
622 | * point. | |
623 | */ | |
3fac6dfd | 624 | sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON); |
226afe68 JP |
625 | ath_dbg(common, ATH_DBG_PS, |
626 | "All PS CAB frames received, back to sleep\n"); | |
1b04b930 | 627 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
628 | !is_multicast_ether_addr(hdr->addr1) && |
629 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 630 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
226afe68 JP |
631 | ath_dbg(common, ATH_DBG_PS, |
632 | "Going back to sleep after having received PS-Poll data (0x%lx)\n", | |
1b04b930 S |
633 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
634 | PS_WAIT_FOR_CAB | | |
635 | PS_WAIT_FOR_PSPOLL_DATA | | |
636 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
637 | } |
638 | } | |
639 | ||
b5c80475 FF |
640 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
641 | enum ath9k_rx_qtype qtype) | |
f078f209 | 642 | { |
b5c80475 FF |
643 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
644 | struct ath_hw *ah = sc->sc_ah; | |
645 | struct ath_common *common = ath9k_hw_common(ah); | |
646 | struct sk_buff *skb; | |
647 | struct ath_buf *bf; | |
648 | int ret; | |
649 | ||
650 | skb = skb_peek(&rx_edma->rx_fifo); | |
651 | if (!skb) | |
652 | return false; | |
653 | ||
654 | bf = SKB_CB_ATHBUF(skb); | |
655 | BUG_ON(!bf); | |
656 | ||
ce9426d1 | 657 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
658 | common->rx_bufsize, DMA_FROM_DEVICE); |
659 | ||
660 | ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data); | |
ce9426d1 ML |
661 | if (ret == -EINPROGRESS) { |
662 | /*let device gain the buffer again*/ | |
663 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
664 | common->rx_bufsize, DMA_FROM_DEVICE); | |
b5c80475 | 665 | return false; |
ce9426d1 | 666 | } |
b5c80475 FF |
667 | |
668 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
669 | if (ret == -EINVAL) { | |
670 | /* corrupt descriptor, skip this one and the following one */ | |
671 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
672 | ath_rx_edma_buf_link(sc, qtype); | |
673 | skb = skb_peek(&rx_edma->rx_fifo); | |
674 | if (!skb) | |
675 | return true; | |
676 | ||
677 | bf = SKB_CB_ATHBUF(skb); | |
678 | BUG_ON(!bf); | |
679 | ||
680 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
681 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
682 | ath_rx_edma_buf_link(sc, qtype); | |
083e3e8d | 683 | return true; |
b5c80475 FF |
684 | } |
685 | skb_queue_tail(&rx_edma->rx_buffers, skb); | |
686 | ||
687 | return true; | |
688 | } | |
f078f209 | 689 | |
b5c80475 FF |
690 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
691 | struct ath_rx_status *rs, | |
692 | enum ath9k_rx_qtype qtype) | |
693 | { | |
694 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; | |
695 | struct sk_buff *skb; | |
be0418ad | 696 | struct ath_buf *bf; |
b5c80475 FF |
697 | |
698 | while (ath_edma_get_buffers(sc, qtype)); | |
699 | skb = __skb_dequeue(&rx_edma->rx_buffers); | |
700 | if (!skb) | |
701 | return NULL; | |
702 | ||
703 | bf = SKB_CB_ATHBUF(skb); | |
704 | ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data); | |
705 | return bf; | |
706 | } | |
707 | ||
708 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
709 | struct ath_rx_status *rs) | |
710 | { | |
711 | struct ath_hw *ah = sc->sc_ah; | |
712 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 713 | struct ath_desc *ds; |
b5c80475 FF |
714 | struct ath_buf *bf; |
715 | int ret; | |
716 | ||
717 | if (list_empty(&sc->rx.rxbuf)) { | |
718 | sc->rx.rxlink = NULL; | |
719 | return NULL; | |
720 | } | |
721 | ||
722 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
723 | ds = bf->bf_desc; | |
724 | ||
725 | /* | |
726 | * Must provide the virtual address of the current | |
727 | * descriptor, the physical address, and the virtual | |
728 | * address of the next descriptor in the h/w chain. | |
729 | * This allows the HAL to look ahead to see if the | |
730 | * hardware is done with a descriptor by checking the | |
731 | * done bit in the following descriptor and the address | |
732 | * of the current descriptor the DMA engine is working | |
733 | * on. All this is necessary because of our use of | |
734 | * a self-linked list to avoid rx overruns. | |
735 | */ | |
736 | ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0); | |
737 | if (ret == -EINPROGRESS) { | |
738 | struct ath_rx_status trs; | |
739 | struct ath_buf *tbf; | |
740 | struct ath_desc *tds; | |
741 | ||
742 | memset(&trs, 0, sizeof(trs)); | |
743 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
744 | sc->rx.rxlink = NULL; | |
745 | return NULL; | |
746 | } | |
747 | ||
748 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
749 | ||
750 | /* | |
751 | * On some hardware the descriptor status words could | |
752 | * get corrupted, including the done bit. Because of | |
753 | * this, check if the next descriptor's done bit is | |
754 | * set or not. | |
755 | * | |
756 | * If the next descriptor's done bit is set, the current | |
757 | * descriptor has been corrupted. Force s/w to discard | |
758 | * this descriptor and continue... | |
759 | */ | |
760 | ||
761 | tds = tbf->bf_desc; | |
762 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0); | |
763 | if (ret == -EINPROGRESS) | |
764 | return NULL; | |
765 | } | |
766 | ||
767 | if (!bf->bf_mpdu) | |
768 | return bf; | |
769 | ||
770 | /* | |
771 | * Synchronize the DMA transfer with CPU before | |
772 | * 1. accessing the frame | |
773 | * 2. requeueing the same buffer to h/w | |
774 | */ | |
ce9426d1 | 775 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
b5c80475 FF |
776 | common->rx_bufsize, |
777 | DMA_FROM_DEVICE); | |
778 | ||
779 | return bf; | |
780 | } | |
781 | ||
d435700f S |
782 | /* Assumes you've already done the endian to CPU conversion */ |
783 | static bool ath9k_rx_accept(struct ath_common *common, | |
9f167f64 | 784 | struct ieee80211_hdr *hdr, |
d435700f S |
785 | struct ieee80211_rx_status *rxs, |
786 | struct ath_rx_status *rx_stats, | |
787 | bool *decrypt_error) | |
788 | { | |
38852b20 SB |
789 | #define is_mc_or_valid_tkip_keyix ((is_mc || \ |
790 | (rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID && \ | |
791 | test_bit(rx_stats->rs_keyix, common->tkip_keymap)))) | |
792 | ||
d435700f | 793 | struct ath_hw *ah = common->ah; |
d435700f | 794 | __le16 fc; |
b7b1b512 | 795 | u8 rx_status_len = ah->caps.rx_status_len; |
d435700f | 796 | |
d435700f S |
797 | fc = hdr->frame_control; |
798 | ||
799 | if (!rx_stats->rs_datalen) | |
800 | return false; | |
801 | /* | |
802 | * rs_status follows rs_datalen so if rs_datalen is too large | |
803 | * we can take a hint that hardware corrupted it, so ignore | |
804 | * those frames. | |
805 | */ | |
b7b1b512 | 806 | if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len)) |
d435700f S |
807 | return false; |
808 | ||
0d95521e | 809 | /* Only use error bits from the last fragment */ |
d435700f | 810 | if (rx_stats->rs_more) |
0d95521e | 811 | return true; |
d435700f S |
812 | |
813 | /* | |
814 | * The rx_stats->rs_status will not be set until the end of the | |
815 | * chained descriptors so it can be ignored if rs_more is set. The | |
816 | * rs_more will be false at the last element of the chained | |
817 | * descriptors. | |
818 | */ | |
819 | if (rx_stats->rs_status != 0) { | |
820 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
821 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; | |
822 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) | |
823 | return false; | |
824 | ||
825 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { | |
826 | *decrypt_error = true; | |
827 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { | |
38852b20 | 828 | bool is_mc; |
56363dde FF |
829 | /* |
830 | * The MIC error bit is only valid if the frame | |
831 | * is not a control frame or fragment, and it was | |
832 | * decrypted using a valid TKIP key. | |
833 | */ | |
38852b20 SB |
834 | is_mc = !!is_multicast_ether_addr(hdr->addr1); |
835 | ||
56363dde FF |
836 | if (!ieee80211_is_ctl(fc) && |
837 | !ieee80211_has_morefrags(fc) && | |
838 | !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) && | |
38852b20 | 839 | is_mc_or_valid_tkip_keyix) |
d435700f | 840 | rxs->flag |= RX_FLAG_MMIC_ERROR; |
56363dde FF |
841 | else |
842 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; | |
d435700f S |
843 | } |
844 | /* | |
845 | * Reject error frames with the exception of | |
846 | * decryption and MIC failures. For monitor mode, | |
847 | * we also ignore the CRC error. | |
848 | */ | |
5f841b41 | 849 | if (ah->is_monitoring) { |
d435700f S |
850 | if (rx_stats->rs_status & |
851 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
852 | ATH9K_RXERR_CRC)) | |
853 | return false; | |
854 | } else { | |
855 | if (rx_stats->rs_status & | |
856 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
857 | return false; | |
858 | } | |
859 | } | |
860 | } | |
861 | return true; | |
862 | } | |
863 | ||
864 | static int ath9k_process_rate(struct ath_common *common, | |
865 | struct ieee80211_hw *hw, | |
866 | struct ath_rx_status *rx_stats, | |
9f167f64 | 867 | struct ieee80211_rx_status *rxs) |
d435700f S |
868 | { |
869 | struct ieee80211_supported_band *sband; | |
870 | enum ieee80211_band band; | |
871 | unsigned int i = 0; | |
872 | ||
873 | band = hw->conf.channel->band; | |
874 | sband = hw->wiphy->bands[band]; | |
875 | ||
876 | if (rx_stats->rs_rate & 0x80) { | |
877 | /* HT rate */ | |
878 | rxs->flag |= RX_FLAG_HT; | |
879 | if (rx_stats->rs_flags & ATH9K_RX_2040) | |
880 | rxs->flag |= RX_FLAG_40MHZ; | |
881 | if (rx_stats->rs_flags & ATH9K_RX_GI) | |
882 | rxs->flag |= RX_FLAG_SHORT_GI; | |
883 | rxs->rate_idx = rx_stats->rs_rate & 0x7f; | |
884 | return 0; | |
885 | } | |
886 | ||
887 | for (i = 0; i < sband->n_bitrates; i++) { | |
888 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
889 | rxs->rate_idx = i; | |
890 | return 0; | |
891 | } | |
892 | if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) { | |
893 | rxs->flag |= RX_FLAG_SHORTPRE; | |
894 | rxs->rate_idx = i; | |
895 | return 0; | |
896 | } | |
897 | } | |
898 | ||
899 | /* | |
900 | * No valid hardware bitrate found -- we should not get here | |
901 | * because hardware has already validated this frame as OK. | |
902 | */ | |
226afe68 JP |
903 | ath_dbg(common, ATH_DBG_XMIT, |
904 | "unsupported hw bitrate detected 0x%02x using 1 Mbit\n", | |
905 | rx_stats->rs_rate); | |
d435700f S |
906 | |
907 | return -EINVAL; | |
908 | } | |
909 | ||
910 | static void ath9k_process_rssi(struct ath_common *common, | |
911 | struct ieee80211_hw *hw, | |
9f167f64 | 912 | struct ieee80211_hdr *hdr, |
d435700f S |
913 | struct ath_rx_status *rx_stats) |
914 | { | |
9ac58615 | 915 | struct ath_softc *sc = hw->priv; |
d435700f | 916 | struct ath_hw *ah = common->ah; |
9fa23e17 | 917 | int last_rssi; |
d435700f S |
918 | __le16 fc; |
919 | ||
9fa23e17 FF |
920 | if (ah->opmode != NL80211_IFTYPE_STATION) |
921 | return; | |
922 | ||
d435700f | 923 | fc = hdr->frame_control; |
9fa23e17 | 924 | if (!ieee80211_is_beacon(fc) || |
4801416c BG |
925 | compare_ether_addr(hdr->addr3, common->curbssid)) { |
926 | /* TODO: This doesn't work well if you have stations | |
927 | * associated to two different APs because curbssid | |
928 | * is just the last AP that any of the stations associated | |
929 | * with. | |
930 | */ | |
9fa23e17 | 931 | return; |
4801416c | 932 | } |
d435700f | 933 | |
9fa23e17 | 934 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr) |
9ac58615 | 935 | ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi); |
d435700f | 936 | |
9ac58615 | 937 | last_rssi = sc->last_rssi; |
d435700f S |
938 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) |
939 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, | |
940 | ATH_RSSI_EP_MULTIPLIER); | |
941 | if (rx_stats->rs_rssi < 0) | |
942 | rx_stats->rs_rssi = 0; | |
943 | ||
944 | /* Update Beacon RSSI, this is used by ANI. */ | |
9fa23e17 | 945 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
d435700f S |
946 | } |
947 | ||
948 | /* | |
949 | * For Decrypt or Demic errors, we only mark packet status here and always push | |
950 | * up the frame up to let mac80211 handle the actual error case, be it no | |
951 | * decryption key or real decryption error. This let us keep statistics there. | |
952 | */ | |
953 | static int ath9k_rx_skb_preprocess(struct ath_common *common, | |
954 | struct ieee80211_hw *hw, | |
9f167f64 | 955 | struct ieee80211_hdr *hdr, |
d435700f S |
956 | struct ath_rx_status *rx_stats, |
957 | struct ieee80211_rx_status *rx_status, | |
958 | bool *decrypt_error) | |
959 | { | |
d435700f S |
960 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
961 | ||
962 | /* | |
963 | * everything but the rate is checked here, the rate check is done | |
964 | * separately to avoid doing two lookups for a rate for each frame. | |
965 | */ | |
9f167f64 | 966 | if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error)) |
d435700f S |
967 | return -EINVAL; |
968 | ||
0d95521e FF |
969 | /* Only use status info from the last fragment */ |
970 | if (rx_stats->rs_more) | |
971 | return 0; | |
972 | ||
9f167f64 | 973 | ath9k_process_rssi(common, hw, hdr, rx_stats); |
d435700f | 974 | |
9f167f64 | 975 | if (ath9k_process_rate(common, hw, rx_stats, rx_status)) |
d435700f S |
976 | return -EINVAL; |
977 | ||
d435700f S |
978 | rx_status->band = hw->conf.channel->band; |
979 | rx_status->freq = hw->conf.channel->center_freq; | |
980 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; | |
981 | rx_status->antenna = rx_stats->rs_antenna; | |
6ebacbb7 | 982 | rx_status->flag |= RX_FLAG_MACTIME_MPDU; |
d435700f S |
983 | |
984 | return 0; | |
985 | } | |
986 | ||
987 | static void ath9k_rx_skb_postprocess(struct ath_common *common, | |
988 | struct sk_buff *skb, | |
989 | struct ath_rx_status *rx_stats, | |
990 | struct ieee80211_rx_status *rxs, | |
991 | bool decrypt_error) | |
992 | { | |
993 | struct ath_hw *ah = common->ah; | |
994 | struct ieee80211_hdr *hdr; | |
995 | int hdrlen, padpos, padsize; | |
996 | u8 keyix; | |
997 | __le16 fc; | |
998 | ||
999 | /* see if any padding is done by the hw and remove it */ | |
1000 | hdr = (struct ieee80211_hdr *) skb->data; | |
1001 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
1002 | fc = hdr->frame_control; | |
1003 | padpos = ath9k_cmn_padpos(hdr->frame_control); | |
1004 | ||
1005 | /* The MAC header is padded to have 32-bit boundary if the | |
1006 | * packet payload is non-zero. The general calculation for | |
1007 | * padsize would take into account odd header lengths: | |
1008 | * padsize = (4 - padpos % 4) % 4; However, since only | |
1009 | * even-length headers are used, padding can only be 0 or 2 | |
1010 | * bytes and we can optimize this a bit. In addition, we must | |
1011 | * not try to remove padding from short control frames that do | |
1012 | * not have payload. */ | |
1013 | padsize = padpos & 3; | |
1014 | if (padsize && skb->len>=padpos+padsize+FCS_LEN) { | |
1015 | memmove(skb->data + padsize, skb->data, padpos); | |
1016 | skb_pull(skb, padsize); | |
1017 | } | |
1018 | ||
1019 | keyix = rx_stats->rs_keyix; | |
1020 | ||
1021 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error && | |
1022 | ieee80211_has_protected(fc)) { | |
1023 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1024 | } else if (ieee80211_has_protected(fc) | |
1025 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
1026 | keyix = skb->data[hdrlen + 3] >> 6; | |
1027 | ||
1028 | if (test_bit(keyix, common->keymap)) | |
1029 | rxs->flag |= RX_FLAG_DECRYPTED; | |
1030 | } | |
1031 | if (ah->sw_mgmt_crypto && | |
1032 | (rxs->flag & RX_FLAG_DECRYPTED) && | |
1033 | ieee80211_is_mgmt(fc)) | |
1034 | /* Use software decrypt for management frames. */ | |
1035 | rxs->flag &= ~RX_FLAG_DECRYPTED; | |
1036 | } | |
b5c80475 | 1037 | |
102885a5 VT |
1038 | static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb, |
1039 | struct ath_hw_antcomb_conf ant_conf, | |
1040 | int main_rssi_avg) | |
1041 | { | |
1042 | antcomb->quick_scan_cnt = 0; | |
1043 | ||
1044 | if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2) | |
1045 | antcomb->rssi_lna2 = main_rssi_avg; | |
1046 | else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1) | |
1047 | antcomb->rssi_lna1 = main_rssi_avg; | |
1048 | ||
1049 | switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) { | |
1050 | case (0x10): /* LNA2 A-B */ | |
1051 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1052 | antcomb->first_quick_scan_conf = | |
1053 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1054 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1055 | break; | |
1056 | case (0x20): /* LNA1 A-B */ | |
1057 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1058 | antcomb->first_quick_scan_conf = | |
1059 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1060 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1061 | break; | |
1062 | case (0x21): /* LNA1 LNA2 */ | |
1063 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2; | |
1064 | antcomb->first_quick_scan_conf = | |
1065 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1066 | antcomb->second_quick_scan_conf = | |
1067 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1068 | break; | |
1069 | case (0x12): /* LNA2 LNA1 */ | |
1070 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1; | |
1071 | antcomb->first_quick_scan_conf = | |
1072 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1073 | antcomb->second_quick_scan_conf = | |
1074 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1075 | break; | |
1076 | case (0x13): /* LNA2 A+B */ | |
1077 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1078 | antcomb->first_quick_scan_conf = | |
1079 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1080 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1; | |
1081 | break; | |
1082 | case (0x23): /* LNA1 A+B */ | |
1083 | antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1084 | antcomb->first_quick_scan_conf = | |
1085 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1086 | antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2; | |
1087 | break; | |
1088 | default: | |
1089 | break; | |
1090 | } | |
1091 | } | |
1092 | ||
1093 | static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb, | |
1094 | struct ath_hw_antcomb_conf *div_ant_conf, | |
1095 | int main_rssi_avg, int alt_rssi_avg, | |
1096 | int alt_ratio) | |
1097 | { | |
1098 | /* alt_good */ | |
1099 | switch (antcomb->quick_scan_cnt) { | |
1100 | case 0: | |
1101 | /* set alt to main, and alt to first conf */ | |
1102 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1103 | div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf; | |
1104 | break; | |
1105 | case 1: | |
1106 | /* set alt to main, and alt to first conf */ | |
1107 | div_ant_conf->main_lna_conf = antcomb->main_conf; | |
1108 | div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf; | |
1109 | antcomb->rssi_first = main_rssi_avg; | |
1110 | antcomb->rssi_second = alt_rssi_avg; | |
1111 | ||
1112 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1113 | /* main is LNA1 */ | |
1114 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1115 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1116 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1117 | main_rssi_avg, alt_rssi_avg, | |
1118 | antcomb->total_pkt_count)) | |
1119 | antcomb->first_ratio = true; | |
1120 | else | |
1121 | antcomb->first_ratio = false; | |
1122 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1123 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1124 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1125 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1126 | main_rssi_avg, alt_rssi_avg, | |
1127 | antcomb->total_pkt_count)) | |
1128 | antcomb->first_ratio = true; | |
1129 | else | |
1130 | antcomb->first_ratio = false; | |
1131 | } else { | |
1132 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1133 | (alt_rssi_avg > main_rssi_avg + | |
1134 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1135 | (alt_rssi_avg > main_rssi_avg)) && | |
1136 | (antcomb->total_pkt_count > 50)) | |
1137 | antcomb->first_ratio = true; | |
1138 | else | |
1139 | antcomb->first_ratio = false; | |
1140 | } | |
1141 | break; | |
1142 | case 2: | |
1143 | antcomb->alt_good = false; | |
1144 | antcomb->scan_not_start = false; | |
1145 | antcomb->scan = false; | |
1146 | antcomb->rssi_first = main_rssi_avg; | |
1147 | antcomb->rssi_third = alt_rssi_avg; | |
1148 | ||
1149 | if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1) | |
1150 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1151 | else if (antcomb->second_quick_scan_conf == | |
1152 | ATH_ANT_DIV_COMB_LNA2) | |
1153 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1154 | else if (antcomb->second_quick_scan_conf == | |
1155 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) { | |
1156 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) | |
1157 | antcomb->rssi_lna2 = main_rssi_avg; | |
1158 | else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) | |
1159 | antcomb->rssi_lna1 = main_rssi_avg; | |
1160 | } | |
1161 | ||
1162 | if (antcomb->rssi_lna2 > antcomb->rssi_lna1 + | |
1163 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA) | |
1164 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1165 | else | |
1166 | div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1; | |
1167 | ||
1168 | if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) { | |
1169 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1170 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI, | |
1171 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1172 | main_rssi_avg, alt_rssi_avg, | |
1173 | antcomb->total_pkt_count)) | |
1174 | antcomb->second_ratio = true; | |
1175 | else | |
1176 | antcomb->second_ratio = false; | |
1177 | } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) { | |
1178 | if (ath_is_alt_ant_ratio_better(alt_ratio, | |
1179 | ATH_ANT_DIV_COMB_LNA1_DELTA_MID, | |
1180 | ATH_ANT_DIV_COMB_LNA1_DELTA_LOW, | |
1181 | main_rssi_avg, alt_rssi_avg, | |
1182 | antcomb->total_pkt_count)) | |
1183 | antcomb->second_ratio = true; | |
1184 | else | |
1185 | antcomb->second_ratio = false; | |
1186 | } else { | |
1187 | if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) && | |
1188 | (alt_rssi_avg > main_rssi_avg + | |
1189 | ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) || | |
1190 | (alt_rssi_avg > main_rssi_avg)) && | |
1191 | (antcomb->total_pkt_count > 50)) | |
1192 | antcomb->second_ratio = true; | |
1193 | else | |
1194 | antcomb->second_ratio = false; | |
1195 | } | |
1196 | ||
1197 | /* set alt to the conf with maximun ratio */ | |
1198 | if (antcomb->first_ratio && antcomb->second_ratio) { | |
1199 | if (antcomb->rssi_second > antcomb->rssi_third) { | |
1200 | /* first alt*/ | |
1201 | if ((antcomb->first_quick_scan_conf == | |
1202 | ATH_ANT_DIV_COMB_LNA1) || | |
1203 | (antcomb->first_quick_scan_conf == | |
1204 | ATH_ANT_DIV_COMB_LNA2)) | |
1205 | /* Set alt LNA1 or LNA2*/ | |
1206 | if (div_ant_conf->main_lna_conf == | |
1207 | ATH_ANT_DIV_COMB_LNA2) | |
1208 | div_ant_conf->alt_lna_conf = | |
1209 | ATH_ANT_DIV_COMB_LNA1; | |
1210 | else | |
1211 | div_ant_conf->alt_lna_conf = | |
1212 | ATH_ANT_DIV_COMB_LNA2; | |
1213 | else | |
1214 | /* Set alt to A+B or A-B */ | |
1215 | div_ant_conf->alt_lna_conf = | |
1216 | antcomb->first_quick_scan_conf; | |
1217 | } else if ((antcomb->second_quick_scan_conf == | |
1218 | ATH_ANT_DIV_COMB_LNA1) || | |
1219 | (antcomb->second_quick_scan_conf == | |
1220 | ATH_ANT_DIV_COMB_LNA2)) { | |
1221 | /* Set alt LNA1 or LNA2 */ | |
1222 | if (div_ant_conf->main_lna_conf == | |
1223 | ATH_ANT_DIV_COMB_LNA2) | |
1224 | div_ant_conf->alt_lna_conf = | |
1225 | ATH_ANT_DIV_COMB_LNA1; | |
1226 | else | |
1227 | div_ant_conf->alt_lna_conf = | |
1228 | ATH_ANT_DIV_COMB_LNA2; | |
1229 | } else { | |
1230 | /* Set alt to A+B or A-B */ | |
1231 | div_ant_conf->alt_lna_conf = | |
1232 | antcomb->second_quick_scan_conf; | |
1233 | } | |
1234 | } else if (antcomb->first_ratio) { | |
1235 | /* first alt */ | |
1236 | if ((antcomb->first_quick_scan_conf == | |
1237 | ATH_ANT_DIV_COMB_LNA1) || | |
1238 | (antcomb->first_quick_scan_conf == | |
1239 | ATH_ANT_DIV_COMB_LNA2)) | |
1240 | /* Set alt LNA1 or LNA2 */ | |
1241 | if (div_ant_conf->main_lna_conf == | |
1242 | ATH_ANT_DIV_COMB_LNA2) | |
1243 | div_ant_conf->alt_lna_conf = | |
1244 | ATH_ANT_DIV_COMB_LNA1; | |
1245 | else | |
1246 | div_ant_conf->alt_lna_conf = | |
1247 | ATH_ANT_DIV_COMB_LNA2; | |
1248 | else | |
1249 | /* Set alt to A+B or A-B */ | |
1250 | div_ant_conf->alt_lna_conf = | |
1251 | antcomb->first_quick_scan_conf; | |
1252 | } else if (antcomb->second_ratio) { | |
1253 | /* second alt */ | |
1254 | if ((antcomb->second_quick_scan_conf == | |
1255 | ATH_ANT_DIV_COMB_LNA1) || | |
1256 | (antcomb->second_quick_scan_conf == | |
1257 | ATH_ANT_DIV_COMB_LNA2)) | |
1258 | /* Set alt LNA1 or LNA2 */ | |
1259 | if (div_ant_conf->main_lna_conf == | |
1260 | ATH_ANT_DIV_COMB_LNA2) | |
1261 | div_ant_conf->alt_lna_conf = | |
1262 | ATH_ANT_DIV_COMB_LNA1; | |
1263 | else | |
1264 | div_ant_conf->alt_lna_conf = | |
1265 | ATH_ANT_DIV_COMB_LNA2; | |
1266 | else | |
1267 | /* Set alt to A+B or A-B */ | |
1268 | div_ant_conf->alt_lna_conf = | |
1269 | antcomb->second_quick_scan_conf; | |
1270 | } else { | |
1271 | /* main is largest */ | |
1272 | if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) || | |
1273 | (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)) | |
1274 | /* Set alt LNA1 or LNA2 */ | |
1275 | if (div_ant_conf->main_lna_conf == | |
1276 | ATH_ANT_DIV_COMB_LNA2) | |
1277 | div_ant_conf->alt_lna_conf = | |
1278 | ATH_ANT_DIV_COMB_LNA1; | |
1279 | else | |
1280 | div_ant_conf->alt_lna_conf = | |
1281 | ATH_ANT_DIV_COMB_LNA2; | |
1282 | else | |
1283 | /* Set alt to A+B or A-B */ | |
1284 | div_ant_conf->alt_lna_conf = antcomb->main_conf; | |
1285 | } | |
1286 | break; | |
1287 | default: | |
1288 | break; | |
1289 | } | |
1290 | } | |
1291 | ||
9bad82b8 | 1292 | static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf) |
102885a5 VT |
1293 | { |
1294 | /* Adjust the fast_div_bias based on main and alt lna conf */ | |
1295 | switch ((ant_conf->main_lna_conf << 4) | ant_conf->alt_lna_conf) { | |
1296 | case (0x01): /* A-B LNA2 */ | |
1297 | ant_conf->fast_div_bias = 0x3b; | |
1298 | break; | |
1299 | case (0x02): /* A-B LNA1 */ | |
1300 | ant_conf->fast_div_bias = 0x3d; | |
1301 | break; | |
1302 | case (0x03): /* A-B A+B */ | |
1303 | ant_conf->fast_div_bias = 0x1; | |
1304 | break; | |
1305 | case (0x10): /* LNA2 A-B */ | |
1306 | ant_conf->fast_div_bias = 0x7; | |
1307 | break; | |
1308 | case (0x12): /* LNA2 LNA1 */ | |
1309 | ant_conf->fast_div_bias = 0x2; | |
1310 | break; | |
1311 | case (0x13): /* LNA2 A+B */ | |
1312 | ant_conf->fast_div_bias = 0x7; | |
1313 | break; | |
1314 | case (0x20): /* LNA1 A-B */ | |
1315 | ant_conf->fast_div_bias = 0x6; | |
1316 | break; | |
1317 | case (0x21): /* LNA1 LNA2 */ | |
1318 | ant_conf->fast_div_bias = 0x0; | |
1319 | break; | |
1320 | case (0x23): /* LNA1 A+B */ | |
1321 | ant_conf->fast_div_bias = 0x6; | |
1322 | break; | |
1323 | case (0x30): /* A+B A-B */ | |
1324 | ant_conf->fast_div_bias = 0x1; | |
1325 | break; | |
1326 | case (0x31): /* A+B LNA2 */ | |
1327 | ant_conf->fast_div_bias = 0x3b; | |
1328 | break; | |
1329 | case (0x32): /* A+B LNA1 */ | |
1330 | ant_conf->fast_div_bias = 0x3d; | |
1331 | break; | |
1332 | default: | |
1333 | break; | |
1334 | } | |
1335 | } | |
1336 | ||
1337 | /* Antenna diversity and combining */ | |
1338 | static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs) | |
1339 | { | |
1340 | struct ath_hw_antcomb_conf div_ant_conf; | |
1341 | struct ath_ant_comb *antcomb = &sc->ant_comb; | |
1342 | int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set; | |
0ff2b5c0 | 1343 | int curr_main_set; |
102885a5 VT |
1344 | int main_rssi = rs->rs_rssi_ctl0; |
1345 | int alt_rssi = rs->rs_rssi_ctl1; | |
1346 | int rx_ant_conf, main_ant_conf; | |
1347 | bool short_scan = false; | |
1348 | ||
1349 | rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) & | |
1350 | ATH_ANT_RX_MASK; | |
1351 | main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) & | |
1352 | ATH_ANT_RX_MASK; | |
1353 | ||
1354 | /* Record packet only when alt_rssi is positive */ | |
1355 | if (alt_rssi > 0) { | |
1356 | antcomb->total_pkt_count++; | |
1357 | antcomb->main_total_rssi += main_rssi; | |
1358 | antcomb->alt_total_rssi += alt_rssi; | |
1359 | if (main_ant_conf == rx_ant_conf) | |
1360 | antcomb->main_recv_cnt++; | |
1361 | else | |
1362 | antcomb->alt_recv_cnt++; | |
1363 | } | |
1364 | ||
1365 | /* Short scan check */ | |
1366 | if (antcomb->scan && antcomb->alt_good) { | |
1367 | if (time_after(jiffies, antcomb->scan_start_time + | |
1368 | msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR))) | |
1369 | short_scan = true; | |
1370 | else | |
1371 | if (antcomb->total_pkt_count == | |
1372 | ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) { | |
1373 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1374 | antcomb->total_pkt_count); | |
1375 | if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO) | |
1376 | short_scan = true; | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) || | |
1381 | rs->rs_moreaggr) && !short_scan) | |
1382 | return; | |
1383 | ||
1384 | if (antcomb->total_pkt_count) { | |
1385 | alt_ratio = ((antcomb->alt_recv_cnt * 100) / | |
1386 | antcomb->total_pkt_count); | |
1387 | main_rssi_avg = (antcomb->main_total_rssi / | |
1388 | antcomb->total_pkt_count); | |
1389 | alt_rssi_avg = (antcomb->alt_total_rssi / | |
1390 | antcomb->total_pkt_count); | |
1391 | } | |
1392 | ||
1393 | ||
1394 | ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf); | |
1395 | curr_alt_set = div_ant_conf.alt_lna_conf; | |
1396 | curr_main_set = div_ant_conf.main_lna_conf; | |
102885a5 VT |
1397 | |
1398 | antcomb->count++; | |
1399 | ||
1400 | if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) { | |
1401 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { | |
1402 | ath_lnaconf_alt_good_scan(antcomb, div_ant_conf, | |
1403 | main_rssi_avg); | |
1404 | antcomb->alt_good = true; | |
1405 | } else { | |
1406 | antcomb->alt_good = false; | |
1407 | } | |
1408 | ||
1409 | antcomb->count = 0; | |
1410 | antcomb->scan = true; | |
1411 | antcomb->scan_not_start = true; | |
1412 | } | |
1413 | ||
1414 | if (!antcomb->scan) { | |
1415 | if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) { | |
1416 | if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) { | |
1417 | /* Switch main and alt LNA */ | |
1418 | div_ant_conf.main_lna_conf = | |
1419 | ATH_ANT_DIV_COMB_LNA2; | |
1420 | div_ant_conf.alt_lna_conf = | |
1421 | ATH_ANT_DIV_COMB_LNA1; | |
1422 | } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) { | |
1423 | div_ant_conf.main_lna_conf = | |
1424 | ATH_ANT_DIV_COMB_LNA1; | |
1425 | div_ant_conf.alt_lna_conf = | |
1426 | ATH_ANT_DIV_COMB_LNA2; | |
1427 | } | |
1428 | ||
1429 | goto div_comb_done; | |
1430 | } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) && | |
1431 | (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) { | |
1432 | /* Set alt to another LNA */ | |
1433 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) | |
1434 | div_ant_conf.alt_lna_conf = | |
1435 | ATH_ANT_DIV_COMB_LNA1; | |
1436 | else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) | |
1437 | div_ant_conf.alt_lna_conf = | |
1438 | ATH_ANT_DIV_COMB_LNA2; | |
1439 | ||
1440 | goto div_comb_done; | |
1441 | } | |
1442 | ||
1443 | if ((alt_rssi_avg < (main_rssi_avg + | |
1444 | ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA))) | |
1445 | goto div_comb_done; | |
1446 | } | |
1447 | ||
1448 | if (!antcomb->scan_not_start) { | |
1449 | switch (curr_alt_set) { | |
1450 | case ATH_ANT_DIV_COMB_LNA2: | |
1451 | antcomb->rssi_lna2 = alt_rssi_avg; | |
1452 | antcomb->rssi_lna1 = main_rssi_avg; | |
1453 | antcomb->scan = true; | |
1454 | /* set to A+B */ | |
1455 | div_ant_conf.main_lna_conf = | |
1456 | ATH_ANT_DIV_COMB_LNA1; | |
1457 | div_ant_conf.alt_lna_conf = | |
1458 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1459 | break; | |
1460 | case ATH_ANT_DIV_COMB_LNA1: | |
1461 | antcomb->rssi_lna1 = alt_rssi_avg; | |
1462 | antcomb->rssi_lna2 = main_rssi_avg; | |
1463 | antcomb->scan = true; | |
1464 | /* set to A+B */ | |
1465 | div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2; | |
1466 | div_ant_conf.alt_lna_conf = | |
1467 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1468 | break; | |
1469 | case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2: | |
1470 | antcomb->rssi_add = alt_rssi_avg; | |
1471 | antcomb->scan = true; | |
1472 | /* set to A-B */ | |
1473 | div_ant_conf.alt_lna_conf = | |
1474 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1475 | break; | |
1476 | case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2: | |
1477 | antcomb->rssi_sub = alt_rssi_avg; | |
1478 | antcomb->scan = false; | |
1479 | if (antcomb->rssi_lna2 > | |
1480 | (antcomb->rssi_lna1 + | |
1481 | ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) { | |
1482 | /* use LNA2 as main LNA */ | |
1483 | if ((antcomb->rssi_add > antcomb->rssi_lna1) && | |
1484 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1485 | /* set to A+B */ | |
1486 | div_ant_conf.main_lna_conf = | |
1487 | ATH_ANT_DIV_COMB_LNA2; | |
1488 | div_ant_conf.alt_lna_conf = | |
1489 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1490 | } else if (antcomb->rssi_sub > | |
1491 | antcomb->rssi_lna1) { | |
1492 | /* set to A-B */ | |
1493 | div_ant_conf.main_lna_conf = | |
1494 | ATH_ANT_DIV_COMB_LNA2; | |
1495 | div_ant_conf.alt_lna_conf = | |
1496 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1497 | } else { | |
1498 | /* set to LNA1 */ | |
1499 | div_ant_conf.main_lna_conf = | |
1500 | ATH_ANT_DIV_COMB_LNA2; | |
1501 | div_ant_conf.alt_lna_conf = | |
1502 | ATH_ANT_DIV_COMB_LNA1; | |
1503 | } | |
1504 | } else { | |
1505 | /* use LNA1 as main LNA */ | |
1506 | if ((antcomb->rssi_add > antcomb->rssi_lna2) && | |
1507 | (antcomb->rssi_add > antcomb->rssi_sub)) { | |
1508 | /* set to A+B */ | |
1509 | div_ant_conf.main_lna_conf = | |
1510 | ATH_ANT_DIV_COMB_LNA1; | |
1511 | div_ant_conf.alt_lna_conf = | |
1512 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2; | |
1513 | } else if (antcomb->rssi_sub > | |
1514 | antcomb->rssi_lna1) { | |
1515 | /* set to A-B */ | |
1516 | div_ant_conf.main_lna_conf = | |
1517 | ATH_ANT_DIV_COMB_LNA1; | |
1518 | div_ant_conf.alt_lna_conf = | |
1519 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2; | |
1520 | } else { | |
1521 | /* set to LNA2 */ | |
1522 | div_ant_conf.main_lna_conf = | |
1523 | ATH_ANT_DIV_COMB_LNA1; | |
1524 | div_ant_conf.alt_lna_conf = | |
1525 | ATH_ANT_DIV_COMB_LNA2; | |
1526 | } | |
1527 | } | |
1528 | break; | |
1529 | default: | |
1530 | break; | |
1531 | } | |
1532 | } else { | |
1533 | if (!antcomb->alt_good) { | |
1534 | antcomb->scan_not_start = false; | |
1535 | /* Set alt to another LNA */ | |
1536 | if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) { | |
1537 | div_ant_conf.main_lna_conf = | |
1538 | ATH_ANT_DIV_COMB_LNA2; | |
1539 | div_ant_conf.alt_lna_conf = | |
1540 | ATH_ANT_DIV_COMB_LNA1; | |
1541 | } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) { | |
1542 | div_ant_conf.main_lna_conf = | |
1543 | ATH_ANT_DIV_COMB_LNA1; | |
1544 | div_ant_conf.alt_lna_conf = | |
1545 | ATH_ANT_DIV_COMB_LNA2; | |
1546 | } | |
1547 | goto div_comb_done; | |
1548 | } | |
1549 | } | |
1550 | ||
1551 | ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf, | |
1552 | main_rssi_avg, alt_rssi_avg, | |
1553 | alt_ratio); | |
1554 | ||
1555 | antcomb->quick_scan_cnt++; | |
1556 | ||
1557 | div_comb_done: | |
1558 | ath_ant_div_conf_fast_divbias(&div_ant_conf); | |
1559 | ||
1560 | ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf); | |
1561 | ||
1562 | antcomb->scan_start_time = jiffies; | |
1563 | antcomb->total_pkt_count = 0; | |
1564 | antcomb->main_total_rssi = 0; | |
1565 | antcomb->alt_total_rssi = 0; | |
1566 | antcomb->main_recv_cnt = 0; | |
1567 | antcomb->alt_recv_cnt = 0; | |
1568 | } | |
1569 | ||
b5c80475 FF |
1570 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) |
1571 | { | |
1572 | struct ath_buf *bf; | |
0d95521e | 1573 | struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb; |
5ca42627 | 1574 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 1575 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 1576 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 | 1577 | /* |
cae6b74d | 1578 | * The hw can technically differ from common->hw when using ath9k |
b4afffc0 LR |
1579 | * virtual wiphy so to account for that we iterate over the active |
1580 | * wiphys and find the appropriate wiphy and therefore hw. | |
1581 | */ | |
7545daf4 | 1582 | struct ieee80211_hw *hw = sc->hw; |
be0418ad | 1583 | struct ieee80211_hdr *hdr; |
c9b14170 | 1584 | int retval; |
be0418ad | 1585 | bool decrypt_error = false; |
29bffa96 | 1586 | struct ath_rx_status rs; |
b5c80475 FF |
1587 | enum ath9k_rx_qtype qtype; |
1588 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
1589 | int dma_type; | |
5c6dd921 | 1590 | u8 rx_status_len = ah->caps.rx_status_len; |
a6d2055b FF |
1591 | u64 tsf = 0; |
1592 | u32 tsf_lower = 0; | |
8ab2cd09 | 1593 | unsigned long flags; |
be0418ad | 1594 | |
b5c80475 | 1595 | if (edma) |
b5c80475 | 1596 | dma_type = DMA_BIDIRECTIONAL; |
56824223 ML |
1597 | else |
1598 | dma_type = DMA_FROM_DEVICE; | |
b5c80475 FF |
1599 | |
1600 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
b77f483f | 1601 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 | 1602 | |
a6d2055b FF |
1603 | tsf = ath9k_hw_gettsf64(ah); |
1604 | tsf_lower = tsf & 0xffffffff; | |
1605 | ||
f078f209 LR |
1606 | do { |
1607 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 1608 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
1609 | break; |
1610 | ||
29bffa96 | 1611 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
1612 | if (edma) |
1613 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
1614 | else | |
1615 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 1616 | |
b5c80475 FF |
1617 | if (!bf) |
1618 | break; | |
f078f209 | 1619 | |
f078f209 | 1620 | skb = bf->bf_mpdu; |
be0418ad | 1621 | if (!skb) |
f078f209 | 1622 | continue; |
f078f209 | 1623 | |
0d95521e FF |
1624 | /* |
1625 | * Take frame header from the first fragment and RX status from | |
1626 | * the last one. | |
1627 | */ | |
1628 | if (sc->rx.frag) | |
1629 | hdr_skb = sc->rx.frag; | |
1630 | else | |
1631 | hdr_skb = skb; | |
1632 | ||
1633 | hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len); | |
1634 | rxs = IEEE80211_SKB_RXCB(hdr_skb); | |
5ca42627 | 1635 | |
29bffa96 | 1636 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 1637 | |
f078f209 | 1638 | /* |
be0418ad S |
1639 | * If we're asked to flush receive queue, directly |
1640 | * chain it back at the queue without processing it. | |
f078f209 | 1641 | */ |
be0418ad | 1642 | if (flush) |
0d95521e | 1643 | goto requeue_drop_frag; |
f078f209 | 1644 | |
c8f3b721 JF |
1645 | retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs, |
1646 | rxs, &decrypt_error); | |
1647 | if (retval) | |
0d95521e | 1648 | goto requeue_drop_frag; |
c8f3b721 | 1649 | |
a6d2055b FF |
1650 | rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp; |
1651 | if (rs.rs_tstamp > tsf_lower && | |
1652 | unlikely(rs.rs_tstamp - tsf_lower > 0x10000000)) | |
1653 | rxs->mactime -= 0x100000000ULL; | |
1654 | ||
1655 | if (rs.rs_tstamp < tsf_lower && | |
1656 | unlikely(tsf_lower - rs.rs_tstamp > 0x10000000)) | |
1657 | rxs->mactime += 0x100000000ULL; | |
1658 | ||
cb71d9ba LR |
1659 | /* Ensure we always have an skb to requeue once we are done |
1660 | * processing the current buffer's skb */ | |
cc861f74 | 1661 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
1662 | |
1663 | /* If there is no memory we ignore the current RX'd frame, | |
1664 | * tell hardware it can give us a new frame using the old | |
b77f483f | 1665 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
1666 | * processing. */ |
1667 | if (!requeue_skb) | |
0d95521e | 1668 | goto requeue_drop_frag; |
f078f209 | 1669 | |
9bf9fca8 | 1670 | /* Unmap the frame */ |
7da3c55c | 1671 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 1672 | common->rx_bufsize, |
b5c80475 | 1673 | dma_type); |
f078f209 | 1674 | |
b5c80475 FF |
1675 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
1676 | if (ah->caps.rx_status_len) | |
1677 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 1678 | |
0d95521e FF |
1679 | if (!rs.rs_more) |
1680 | ath9k_rx_skb_postprocess(common, hdr_skb, &rs, | |
1681 | rxs, decrypt_error); | |
be0418ad | 1682 | |
cb71d9ba LR |
1683 | /* We will now give hardware our shiny new allocated skb */ |
1684 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 1685 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 | 1686 | common->rx_bufsize, |
b5c80475 | 1687 | dma_type); |
7da3c55c | 1688 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
1689 | bf->bf_buf_addr))) { |
1690 | dev_kfree_skb_any(requeue_skb); | |
1691 | bf->bf_mpdu = NULL; | |
6cf9e995 | 1692 | bf->bf_buf_addr = 0; |
3800276a | 1693 | ath_err(common, "dma_mapping_error() on RX\n"); |
7545daf4 | 1694 | ieee80211_rx(hw, skb); |
f8316df1 LR |
1695 | break; |
1696 | } | |
f078f209 | 1697 | |
0d95521e FF |
1698 | if (rs.rs_more) { |
1699 | /* | |
1700 | * rs_more indicates chained descriptors which can be | |
1701 | * used to link buffers together for a sort of | |
1702 | * scatter-gather operation. | |
1703 | */ | |
1704 | if (sc->rx.frag) { | |
1705 | /* too many fragments - cannot handle frame */ | |
1706 | dev_kfree_skb_any(sc->rx.frag); | |
1707 | dev_kfree_skb_any(skb); | |
1708 | skb = NULL; | |
1709 | } | |
1710 | sc->rx.frag = skb; | |
1711 | goto requeue; | |
1712 | } | |
1713 | ||
1714 | if (sc->rx.frag) { | |
1715 | int space = skb->len - skb_tailroom(hdr_skb); | |
1716 | ||
1717 | sc->rx.frag = NULL; | |
1718 | ||
1719 | if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) { | |
1720 | dev_kfree_skb(skb); | |
1721 | goto requeue_drop_frag; | |
1722 | } | |
1723 | ||
1724 | skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len), | |
1725 | skb->len); | |
1726 | dev_kfree_skb_any(skb); | |
1727 | skb = hdr_skb; | |
1728 | } | |
1729 | ||
f078f209 LR |
1730 | /* |
1731 | * change the default rx antenna if rx diversity chooses the | |
1732 | * other antenna 3 times in a row. | |
1733 | */ | |
29bffa96 | 1734 | if (sc->rx.defant != rs.rs_antenna) { |
b77f483f | 1735 | if (++sc->rx.rxotherant >= 3) |
29bffa96 | 1736 | ath_setdefantenna(sc, rs.rs_antenna); |
f078f209 | 1737 | } else { |
b77f483f | 1738 | sc->rx.rxotherant = 0; |
f078f209 | 1739 | } |
3cbb5dd7 | 1740 | |
8ab2cd09 | 1741 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
aaef24b4 MSS |
1742 | |
1743 | if ((sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
ededf1f8 | 1744 | PS_WAIT_FOR_CAB | |
aaef24b4 | 1745 | PS_WAIT_FOR_PSPOLL_DATA)) || |
cedc7e3d | 1746 | ath9k_check_auto_sleep(sc)) |
cc65965c | 1747 | ath_rx_ps(sc, skb); |
8ab2cd09 | 1748 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); |
cc65965c | 1749 | |
102885a5 VT |
1750 | if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) |
1751 | ath_ant_comb_scan(sc, &rs); | |
1752 | ||
7545daf4 | 1753 | ieee80211_rx(hw, skb); |
cc65965c | 1754 | |
0d95521e FF |
1755 | requeue_drop_frag: |
1756 | if (sc->rx.frag) { | |
1757 | dev_kfree_skb_any(sc->rx.frag); | |
1758 | sc->rx.frag = NULL; | |
1759 | } | |
cb71d9ba | 1760 | requeue: |
b5c80475 FF |
1761 | if (edma) { |
1762 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
1763 | ath_rx_edma_buf_link(sc, qtype); | |
1764 | } else { | |
1765 | list_move_tail(&bf->list, &sc->rx.rxbuf); | |
1766 | ath_rx_buf_link(sc, bf); | |
95294973 | 1767 | ath9k_hw_rxena(ah); |
b5c80475 | 1768 | } |
be0418ad S |
1769 | } while (1); |
1770 | ||
b77f483f | 1771 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
1772 | |
1773 | return 0; | |
f078f209 | 1774 | } |