Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
51 | struct ath_desc *ds; |
52 | struct sk_buff *skb; | |
53 | ||
54 | ATH_RXBUF_RESET(bf); | |
55 | ||
56 | ds = bf->bf_desc; | |
be0418ad | 57 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
58 | ds->ds_data = bf->bf_buf_addr; |
59 | ||
be0418ad | 60 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 61 | skb = bf->bf_mpdu; |
9680e8a3 | 62 | BUG_ON(skb == NULL); |
f078f209 LR |
63 | ds->ds_vdata = skb->data; |
64 | ||
b77f483f | 65 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
66 | * how much data it can DMA to us and that we are prepared |
67 | * to process */ | |
b77f483f S |
68 | ath9k_hw_setuprxdesc(ah, ds, |
69 | sc->rx.bufsize, | |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
f078f209 | 89 | /* |
be0418ad S |
90 | * For Decrypt or Demic errors, we only mark packet status here and always push |
91 | * up the frame up to let mac80211 handle the actual error case, be it no | |
92 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 93 | */ |
712c13a8 LR |
94 | static int ath_rx_prepare(struct ath_common *common, |
95 | struct ieee80211_hw *hw, | |
26ab2645 | 96 | struct sk_buff *skb, struct ath_rx_status *rx_stats, |
712c13a8 LR |
97 | struct ieee80211_rx_status *rx_status, |
98 | bool *decrypt_error) | |
f078f209 | 99 | { |
712c13a8 | 100 | struct ath_hw *ah = common->ah; |
be0418ad | 101 | struct ieee80211_hdr *hdr; |
be0418ad S |
102 | u8 ratecode; |
103 | __le16 fc; | |
a59b5a5e SB |
104 | struct ieee80211_sta *sta; |
105 | struct ath_node *an; | |
106 | int last_rssi = ATH_RSSI_DUMMY_MARKER; | |
107 | ||
be0418ad S |
108 | hdr = (struct ieee80211_hdr *)skb->data; |
109 | fc = hdr->frame_control; | |
110 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
111 | ||
26ab2645 | 112 | if (rx_stats->rs_more) { |
be0418ad S |
113 | /* |
114 | * Frame spans multiple descriptors; this cannot happen yet | |
115 | * as we don't support jumbograms. If not in monitor mode, | |
116 | * discard the frame. Enable this if you want to see | |
117 | * error frames in Monitor mode. | |
118 | */ | |
712c13a8 | 119 | if (ah->opmode != NL80211_IFTYPE_MONITOR) |
be0418ad | 120 | goto rx_next; |
26ab2645 LR |
121 | } else if (rx_stats->rs_status != 0) { |
122 | if (rx_stats->rs_status & ATH9K_RXERR_CRC) | |
be0418ad | 123 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
26ab2645 | 124 | if (rx_stats->rs_status & ATH9K_RXERR_PHY) |
be0418ad | 125 | goto rx_next; |
f078f209 | 126 | |
26ab2645 | 127 | if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) { |
be0418ad | 128 | *decrypt_error = true; |
26ab2645 | 129 | } else if (rx_stats->rs_status & ATH9K_RXERR_MIC) { |
be0418ad S |
130 | if (ieee80211_is_ctl(fc)) |
131 | /* | |
132 | * Sometimes, we get invalid | |
133 | * MIC failures on valid control frames. | |
134 | * Remove these mic errors. | |
135 | */ | |
26ab2645 | 136 | rx_stats->rs_status &= ~ATH9K_RXERR_MIC; |
be0418ad S |
137 | else |
138 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
139 | } | |
140 | /* | |
141 | * Reject error frames with the exception of | |
142 | * decryption and MIC failures. For monitor mode, | |
143 | * we also ignore the CRC error. | |
144 | */ | |
712c13a8 | 145 | if (ah->opmode == NL80211_IFTYPE_MONITOR) { |
26ab2645 | 146 | if (rx_stats->rs_status & |
be0418ad S |
147 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | |
148 | ATH9K_RXERR_CRC)) | |
149 | goto rx_next; | |
150 | } else { | |
26ab2645 | 151 | if (rx_stats->rs_status & |
be0418ad S |
152 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { |
153 | goto rx_next; | |
154 | } | |
155 | } | |
f078f209 LR |
156 | } |
157 | ||
26ab2645 | 158 | ratecode = rx_stats->rs_rate; |
be0418ad | 159 | |
be0418ad | 160 | if (ratecode & 0x80) { |
baad1d92 JM |
161 | /* HT rate */ |
162 | rx_status->flag |= RX_FLAG_HT; | |
26ab2645 | 163 | if (rx_stats->rs_flags & ATH9K_RX_2040) |
baad1d92 | 164 | rx_status->flag |= RX_FLAG_40MHZ; |
26ab2645 | 165 | if (rx_stats->rs_flags & ATH9K_RX_GI) |
baad1d92 JM |
166 | rx_status->flag |= RX_FLAG_SHORT_GI; |
167 | rx_status->rate_idx = ratecode & 0x7f; | |
168 | } else { | |
712c13a8 LR |
169 | struct ieee80211_supported_band *sband; |
170 | unsigned int i = 0; | |
171 | enum ieee80211_band band; | |
baad1d92 | 172 | |
712c13a8 LR |
173 | band = hw->conf.channel->band; |
174 | sband = hw->wiphy->bands[band]; | |
baad1d92 | 175 | |
712c13a8 LR |
176 | for (i = 0; i < sband->n_bitrates; i++) { |
177 | if (sband->bitrates[i].hw_value == rx_stats->rs_rate) { | |
baad1d92 JM |
178 | rx_status->rate_idx = i; |
179 | break; | |
180 | } | |
712c13a8 LR |
181 | if (sband->bitrates[i].hw_value_short == |
182 | rx_stats->rs_rate) { | |
baad1d92 JM |
183 | rx_status->rate_idx = i; |
184 | rx_status->flag |= RX_FLAG_SHORTPRE; | |
185 | break; | |
186 | } | |
187 | } | |
be0418ad S |
188 | } |
189 | ||
a59b5a5e | 190 | rcu_read_lock(); |
5ed176e1 | 191 | /* XXX: use ieee80211_find_sta! */ |
cee71d6c | 192 | sta = ieee80211_find_sta_by_hw(hw, hdr->addr2); |
a59b5a5e SB |
193 | if (sta) { |
194 | an = (struct ath_node *) sta->drv_priv; | |
26ab2645 LR |
195 | if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && |
196 | !rx_stats->rs_moreaggr) | |
197 | ATH_RSSI_LPF(an->last_rssi, rx_stats->rs_rssi); | |
a59b5a5e SB |
198 | last_rssi = an->last_rssi; |
199 | } | |
200 | rcu_read_unlock(); | |
201 | ||
202 | if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER)) | |
26ab2645 LR |
203 | rx_stats->rs_rssi = ATH_EP_RND(last_rssi, |
204 | ATH_RSSI_EP_MULTIPLIER); | |
205 | if (rx_stats->rs_rssi < 0) | |
206 | rx_stats->rs_rssi = 0; | |
207 | else if (rx_stats->rs_rssi > 127) | |
208 | rx_stats->rs_rssi = 127; | |
a59b5a5e | 209 | |
5e32b1ed S |
210 | /* Update Beacon RSSI, this is used by ANI. */ |
211 | if (ieee80211_is_beacon(fc)) | |
712c13a8 | 212 | ah->stats.avgbrssi = rx_stats->rs_rssi; |
5e32b1ed | 213 | |
712c13a8 | 214 | rx_status->mactime = ath9k_hw_extend_tsf(ah, rx_stats->rs_tstamp); |
bce048d7 JM |
215 | rx_status->band = hw->conf.channel->band; |
216 | rx_status->freq = hw->conf.channel->center_freq; | |
3d536acf | 217 | rx_status->noise = common->ani.noise_floor; |
26ab2645 LR |
218 | rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi; |
219 | rx_status->antenna = rx_stats->rs_antenna; | |
be0418ad | 220 | |
7d5ca3b8 LR |
221 | /* |
222 | * Theory for reporting quality: | |
223 | * | |
224 | * At a hardware RSSI of 45 you will be able to use MCS 7 reliably. | |
225 | * At a hardware RSSI of 45 you will be able to use MCS 15 reliably. | |
226 | * At a hardware RSSI of 35 you should be able use 54 Mbps reliably. | |
227 | * | |
228 | * MCS 7 is the highets MCS index usable by a 1-stream device. | |
229 | * MCS 15 is the highest MCS index usable by a 2-stream device. | |
230 | * | |
231 | * All ath9k devices are either 1-stream or 2-stream. | |
232 | * | |
233 | * How many bars you see is derived from the qual reporting. | |
234 | * | |
235 | * A more elaborate scheme can be used here but it requires tables | |
236 | * of SNR/throughput for each possible mode used. For the MCS table | |
237 | * you can refer to the wireless wiki: | |
238 | * | |
239 | * http://wireless.kernel.org/en/developers/Documentation/ieee80211/802.11n | |
240 | * | |
241 | */ | |
242 | if (conf_is_ht(&hw->conf)) | |
26ab2645 | 243 | rx_status->qual = rx_stats->rs_rssi * 100 / 45; |
7d5ca3b8 | 244 | else |
26ab2645 | 245 | rx_status->qual = rx_stats->rs_rssi * 100 / 35; |
be0418ad S |
246 | |
247 | /* rssi can be more than 45 though, anything above that | |
248 | * should be considered at 100% */ | |
249 | if (rx_status->qual > 100) | |
250 | rx_status->qual = 100; | |
251 | ||
252 | rx_status->flag |= RX_FLAG_TSFT; | |
253 | ||
254 | return 1; | |
255 | rx_next: | |
256 | return 0; | |
f078f209 LR |
257 | } |
258 | ||
259 | static void ath_opmode_init(struct ath_softc *sc) | |
260 | { | |
cbe61d8a | 261 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
262 | struct ath_common *common = ath9k_hw_common(ah); |
263 | ||
f078f209 LR |
264 | u32 rfilt, mfilt[2]; |
265 | ||
266 | /* configure rx filter */ | |
267 | rfilt = ath_calcrxfilter(sc); | |
268 | ath9k_hw_setrxfilter(ah, rfilt); | |
269 | ||
270 | /* configure bssid mask */ | |
2660b81a | 271 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
13b81559 | 272 | ath_hw_setbssidmask(common); |
f078f209 LR |
273 | |
274 | /* configure operational mode */ | |
275 | ath9k_hw_setopmode(ah); | |
276 | ||
277 | /* Handle any link-level address change. */ | |
1510718d | 278 | ath9k_hw_setmac(ah, common->macaddr); |
f078f209 LR |
279 | |
280 | /* calculate and install multicast filter */ | |
281 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 282 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
283 | } |
284 | ||
285 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
286 | { | |
27c51f1a | 287 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
f078f209 LR |
288 | struct sk_buff *skb; |
289 | struct ath_buf *bf; | |
290 | int error = 0; | |
291 | ||
797fe5cb S |
292 | spin_lock_init(&sc->rx.rxflushlock); |
293 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
294 | spin_lock_init(&sc->rx.rxbuflock); | |
f078f209 | 295 | |
797fe5cb | 296 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
27c51f1a | 297 | min(common->cachelsz, (u16)64)); |
f078f209 | 298 | |
c46917bb LR |
299 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
300 | common->cachelsz, sc->rx.bufsize); | |
f078f209 | 301 | |
797fe5cb | 302 | /* Initialize rx descriptors */ |
f078f209 | 303 | |
797fe5cb S |
304 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
305 | "rx", nbufs, 1); | |
306 | if (error != 0) { | |
c46917bb LR |
307 | ath_print(common, ATH_DBG_FATAL, |
308 | "failed to allocate rx descriptors: %d\n", error); | |
797fe5cb S |
309 | goto err; |
310 | } | |
f078f209 | 311 | |
797fe5cb | 312 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
27c51f1a | 313 | skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_KERNEL); |
797fe5cb S |
314 | if (skb == NULL) { |
315 | error = -ENOMEM; | |
316 | goto err; | |
f078f209 | 317 | } |
f078f209 | 318 | |
797fe5cb S |
319 | bf->bf_mpdu = skb; |
320 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
321 | sc->rx.bufsize, | |
322 | DMA_FROM_DEVICE); | |
323 | if (unlikely(dma_mapping_error(sc->dev, | |
324 | bf->bf_buf_addr))) { | |
325 | dev_kfree_skb_any(skb); | |
326 | bf->bf_mpdu = NULL; | |
c46917bb LR |
327 | ath_print(common, ATH_DBG_FATAL, |
328 | "dma_mapping_error() on RX init\n"); | |
797fe5cb S |
329 | error = -ENOMEM; |
330 | goto err; | |
331 | } | |
332 | bf->bf_dmacontext = bf->bf_buf_addr; | |
333 | } | |
334 | sc->rx.rxlink = NULL; | |
f078f209 | 335 | |
797fe5cb | 336 | err: |
f078f209 LR |
337 | if (error) |
338 | ath_rx_cleanup(sc); | |
339 | ||
340 | return error; | |
341 | } | |
342 | ||
f078f209 LR |
343 | void ath_rx_cleanup(struct ath_softc *sc) |
344 | { | |
345 | struct sk_buff *skb; | |
346 | struct ath_buf *bf; | |
347 | ||
b77f483f | 348 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 | 349 | skb = bf->bf_mpdu; |
051b9191 | 350 | if (skb) { |
797fe5cb S |
351 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
352 | sc->rx.bufsize, DMA_FROM_DEVICE); | |
f078f209 | 353 | dev_kfree_skb(skb); |
051b9191 | 354 | } |
f078f209 LR |
355 | } |
356 | ||
b77f483f S |
357 | if (sc->rx.rxdma.dd_desc_len != 0) |
358 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
359 | } |
360 | ||
361 | /* | |
362 | * Calculate the receive filter according to the | |
363 | * operating mode and state: | |
364 | * | |
365 | * o always accept unicast, broadcast, and multicast traffic | |
366 | * o maintain current state of phy error reception (the hal | |
367 | * may enable phy error frames for noise immunity work) | |
368 | * o probe request frames are accepted only when operating in | |
369 | * hostap, adhoc, or monitor modes | |
370 | * o enable promiscuous mode according to the interface state | |
371 | * o accept beacons: | |
372 | * - when operating in adhoc mode so the 802.11 layer creates | |
373 | * node table entries for peers, | |
374 | * - when operating in station mode for collecting rssi data when | |
375 | * the station is otherwise quiet, or | |
376 | * - when operating as a repeater so we see repeater-sta beacons | |
377 | * - when scanning | |
378 | */ | |
379 | ||
380 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
381 | { | |
382 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 383 | |
f078f209 LR |
384 | u32 rfilt; |
385 | ||
386 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
387 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
388 | | ATH9K_RX_FILTER_MCAST; | |
389 | ||
390 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 391 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
392 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
393 | ||
217ba9da JM |
394 | /* |
395 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
396 | * mode interface or when in monitor mode. AP mode does not need this | |
397 | * since it receives all in-BSS frames anyway. | |
398 | */ | |
2660b81a | 399 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 400 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 401 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 402 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 403 | |
d42c6b71 S |
404 | if (sc->rx.rxfilter & FIF_CONTROL) |
405 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
406 | ||
dbaaa147 VT |
407 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
408 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
409 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
410 | else | |
f078f209 LR |
411 | rfilt |= ATH9K_RX_FILTER_BEACON; |
412 | ||
66afad01 SB |
413 | if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) || |
414 | AR_SREV_9285_10_OR_LATER(sc->sc_ah)) && | |
415 | (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && | |
416 | (sc->rx.rxfilter & FIF_PSPOLL)) | |
dbaaa147 | 417 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 418 | |
7ea310be S |
419 | if (conf_is_ht(&sc->hw->conf)) |
420 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
421 | ||
5eb6ba83 | 422 | if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
b93bce2a JM |
423 | /* TODO: only needed if more than one BSSID is in use in |
424 | * station/adhoc mode */ | |
5eb6ba83 JC |
425 | /* The following may also be needed for other older chips */ |
426 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
427 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
428 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
429 | } | |
430 | ||
f078f209 | 431 | return rfilt; |
7dcfdcd9 | 432 | |
f078f209 LR |
433 | #undef RX_FILTER_PRESERVE |
434 | } | |
435 | ||
f078f209 LR |
436 | int ath_startrecv(struct ath_softc *sc) |
437 | { | |
cbe61d8a | 438 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
439 | struct ath_buf *bf, *tbf; |
440 | ||
b77f483f S |
441 | spin_lock_bh(&sc->rx.rxbuflock); |
442 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
443 | goto start_recv; |
444 | ||
b77f483f S |
445 | sc->rx.rxlink = NULL; |
446 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
447 | ath_rx_buf_link(sc, bf); |
448 | } | |
449 | ||
450 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 451 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
452 | goto start_recv; |
453 | ||
b77f483f | 454 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 455 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 456 | ath9k_hw_rxena(ah); |
f078f209 LR |
457 | |
458 | start_recv: | |
b77f483f | 459 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
460 | ath_opmode_init(sc); |
461 | ath9k_hw_startpcureceive(ah); | |
462 | ||
f078f209 LR |
463 | return 0; |
464 | } | |
465 | ||
f078f209 LR |
466 | bool ath_stoprecv(struct ath_softc *sc) |
467 | { | |
cbe61d8a | 468 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
469 | bool stopped; |
470 | ||
be0418ad S |
471 | ath9k_hw_stoppcurecv(ah); |
472 | ath9k_hw_setrxfilter(ah, 0); | |
473 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 474 | sc->rx.rxlink = NULL; |
be0418ad | 475 | |
f078f209 LR |
476 | return stopped; |
477 | } | |
478 | ||
f078f209 LR |
479 | void ath_flushrecv(struct ath_softc *sc) |
480 | { | |
b77f483f | 481 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 482 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 483 | ath_rx_tasklet(sc, 1); |
98deeea0 | 484 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 485 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
486 | } |
487 | ||
cc65965c JM |
488 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
489 | { | |
490 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
491 | struct ieee80211_mgmt *mgmt; | |
492 | u8 *pos, *end, id, elen; | |
493 | struct ieee80211_tim_ie *tim; | |
494 | ||
495 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
496 | pos = mgmt->u.beacon.variable; | |
497 | end = skb->data + skb->len; | |
498 | ||
499 | while (pos + 2 < end) { | |
500 | id = *pos++; | |
501 | elen = *pos++; | |
502 | if (pos + elen > end) | |
503 | break; | |
504 | ||
505 | if (id == WLAN_EID_TIM) { | |
506 | if (elen < sizeof(*tim)) | |
507 | break; | |
508 | tim = (struct ieee80211_tim_ie *) pos; | |
509 | if (tim->dtim_count != 0) | |
510 | break; | |
511 | return tim->bitmap_ctrl & 0x01; | |
512 | } | |
513 | ||
514 | pos += elen; | |
515 | } | |
516 | ||
517 | return false; | |
518 | } | |
519 | ||
cc65965c JM |
520 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
521 | { | |
522 | struct ieee80211_mgmt *mgmt; | |
1510718d | 523 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
524 | |
525 | if (skb->len < 24 + 8 + 2 + 2) | |
526 | return; | |
527 | ||
528 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
1510718d | 529 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) |
cc65965c JM |
530 | return; /* not from our current AP */ |
531 | ||
293dc5df GJ |
532 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; |
533 | ||
ccdfeab6 JM |
534 | if (sc->sc_flags & SC_OP_BEACON_SYNC) { |
535 | sc->sc_flags &= ~SC_OP_BEACON_SYNC; | |
c46917bb LR |
536 | ath_print(common, ATH_DBG_PS, |
537 | "Reconfigure Beacon timers based on " | |
538 | "timestamp from the AP\n"); | |
ccdfeab6 JM |
539 | ath_beacon_config(sc, NULL); |
540 | } | |
541 | ||
cc65965c JM |
542 | if (ath_beacon_dtim_pending_cab(skb)) { |
543 | /* | |
544 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
545 | * frames. If the last broadcast/multicast frame is not |
546 | * received properly, the next beacon frame will work as | |
547 | * a backup trigger for returning into NETWORK SLEEP state, | |
548 | * so we are waiting for it as well. | |
cc65965c | 549 | */ |
c46917bb LR |
550 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " |
551 | "buffered broadcast/multicast frame(s)\n"); | |
58f5fffd | 552 | sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; |
cc65965c JM |
553 | return; |
554 | } | |
555 | ||
556 | if (sc->sc_flags & SC_OP_WAIT_FOR_CAB) { | |
557 | /* | |
558 | * This can happen if a broadcast frame is dropped or the AP | |
559 | * fails to send a frame indicating that all CAB frames have | |
560 | * been delivered. | |
561 | */ | |
293dc5df | 562 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
563 | ath_print(common, ATH_DBG_PS, |
564 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 565 | } |
cc65965c JM |
566 | } |
567 | ||
568 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
569 | { | |
570 | struct ieee80211_hdr *hdr; | |
c46917bb | 571 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
572 | |
573 | hdr = (struct ieee80211_hdr *)skb->data; | |
574 | ||
575 | /* Process Beacon and CAB receive in PS state */ | |
9a23f9ca JM |
576 | if ((sc->sc_flags & SC_OP_WAIT_FOR_BEACON) && |
577 | ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c JM |
578 | ath_rx_ps_beacon(sc, skb); |
579 | else if ((sc->sc_flags & SC_OP_WAIT_FOR_CAB) && | |
580 | (ieee80211_is_data(hdr->frame_control) || | |
581 | ieee80211_is_action(hdr->frame_control)) && | |
582 | is_multicast_ether_addr(hdr->addr1) && | |
583 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
584 | /* |
585 | * No more broadcast/multicast frames to be received at this | |
586 | * point. | |
587 | */ | |
293dc5df | 588 | sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; |
c46917bb LR |
589 | ath_print(common, ATH_DBG_PS, |
590 | "All PS CAB frames received, back to sleep\n"); | |
9a23f9ca JM |
591 | } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && |
592 | !is_multicast_ether_addr(hdr->addr1) && | |
593 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
594 | sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; | |
c46917bb LR |
595 | ath_print(common, ATH_DBG_PS, |
596 | "Going back to sleep after having received " | |
597 | "PS-Poll data (0x%x)\n", | |
9a23f9ca JM |
598 | sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
599 | SC_OP_WAIT_FOR_CAB | | |
600 | SC_OP_WAIT_FOR_PSPOLL_DATA | | |
601 | SC_OP_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
602 | } |
603 | } | |
604 | ||
b4afffc0 LR |
605 | static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, |
606 | struct ath_softc *sc, struct sk_buff *skb, | |
9d64a3cf JM |
607 | struct ieee80211_rx_status *rx_status) |
608 | { | |
609 | struct ieee80211_hdr *hdr; | |
610 | ||
611 | hdr = (struct ieee80211_hdr *)skb->data; | |
612 | ||
613 | /* Send the frame to mac80211 */ | |
614 | if (is_multicast_ether_addr(hdr->addr1)) { | |
615 | int i; | |
616 | /* | |
617 | * Deliver broadcast/multicast frames to all suitable | |
618 | * virtual wiphys. | |
619 | */ | |
620 | /* TODO: filter based on channel configuration */ | |
621 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
622 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
623 | struct sk_buff *nskb; | |
624 | if (aphy == NULL) | |
625 | continue; | |
626 | nskb = skb_copy(skb, GFP_ATOMIC); | |
f1d58c25 JB |
627 | if (nskb) { |
628 | memcpy(IEEE80211_SKB_RXCB(nskb), rx_status, | |
629 | sizeof(*rx_status)); | |
630 | ieee80211_rx(aphy->hw, nskb); | |
631 | } | |
9d64a3cf | 632 | } |
f1d58c25 JB |
633 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
634 | ieee80211_rx(sc->hw, skb); | |
9d64a3cf JM |
635 | } else { |
636 | /* Deliver unicast frames based on receiver address */ | |
f1d58c25 | 637 | memcpy(IEEE80211_SKB_RXCB(skb), rx_status, sizeof(*rx_status)); |
b4afffc0 | 638 | ieee80211_rx(hw, skb); |
9d64a3cf JM |
639 | } |
640 | } | |
641 | ||
f078f209 LR |
642 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
643 | { | |
644 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
645 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
646 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 647 | |
be0418ad | 648 | struct ath_buf *bf; |
f078f209 | 649 | struct ath_desc *ds; |
26ab2645 | 650 | struct ath_rx_status *rx_stats; |
cb71d9ba | 651 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 652 | struct ieee80211_rx_status rx_status; |
cbe61d8a | 653 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 654 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 LR |
655 | /* |
656 | * The hw can techncically differ from common->hw when using ath9k | |
657 | * virtual wiphy so to account for that we iterate over the active | |
658 | * wiphys and find the appropriate wiphy and therefore hw. | |
659 | */ | |
660 | struct ieee80211_hw *hw = NULL; | |
be0418ad S |
661 | struct ieee80211_hdr *hdr; |
662 | int hdrlen, padsize, retval; | |
663 | bool decrypt_error = false; | |
664 | u8 keyix; | |
853da11b | 665 | __le16 fc; |
be0418ad | 666 | |
b77f483f | 667 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
668 | |
669 | do { | |
670 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 671 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
672 | break; |
673 | ||
b77f483f S |
674 | if (list_empty(&sc->rx.rxbuf)) { |
675 | sc->rx.rxlink = NULL; | |
f078f209 LR |
676 | break; |
677 | } | |
678 | ||
b77f483f | 679 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 680 | ds = bf->bf_desc; |
f078f209 LR |
681 | |
682 | /* | |
683 | * Must provide the virtual address of the current | |
684 | * descriptor, the physical address, and the virtual | |
685 | * address of the next descriptor in the h/w chain. | |
686 | * This allows the HAL to look ahead to see if the | |
687 | * hardware is done with a descriptor by checking the | |
688 | * done bit in the following descriptor and the address | |
689 | * of the current descriptor the DMA engine is working | |
690 | * on. All this is necessary because of our use of | |
691 | * a self-linked list to avoid rx overruns. | |
692 | */ | |
be0418ad | 693 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
694 | bf->bf_daddr, |
695 | PA2DESC(sc, ds->ds_link), | |
696 | 0); | |
697 | if (retval == -EINPROGRESS) { | |
698 | struct ath_buf *tbf; | |
699 | struct ath_desc *tds; | |
700 | ||
b77f483f S |
701 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
702 | sc->rx.rxlink = NULL; | |
f078f209 LR |
703 | break; |
704 | } | |
705 | ||
706 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
707 | ||
708 | /* | |
709 | * On some hardware the descriptor status words could | |
710 | * get corrupted, including the done bit. Because of | |
711 | * this, check if the next descriptor's done bit is | |
712 | * set or not. | |
713 | * | |
714 | * If the next descriptor's done bit is set, the current | |
715 | * descriptor has been corrupted. Force s/w to discard | |
716 | * this descriptor and continue... | |
717 | */ | |
718 | ||
719 | tds = tbf->bf_desc; | |
be0418ad S |
720 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
721 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 722 | if (retval == -EINPROGRESS) { |
f078f209 LR |
723 | break; |
724 | } | |
725 | } | |
726 | ||
f078f209 | 727 | skb = bf->bf_mpdu; |
be0418ad | 728 | if (!skb) |
f078f209 | 729 | continue; |
f078f209 | 730 | |
9bf9fca8 VT |
731 | /* |
732 | * Synchronize the DMA transfer with CPU before | |
733 | * 1. accessing the frame | |
734 | * 2. requeueing the same buffer to h/w | |
735 | */ | |
7da3c55c | 736 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 737 | sc->rx.bufsize, |
7da3c55c | 738 | DMA_FROM_DEVICE); |
9bf9fca8 | 739 | |
b4afffc0 LR |
740 | hdr = (struct ieee80211_hdr *) skb->data; |
741 | hw = ath_get_virt_hw(sc, hdr); | |
26ab2645 | 742 | rx_stats = &ds->ds_rxstat; |
b4afffc0 | 743 | |
f078f209 | 744 | /* |
be0418ad S |
745 | * If we're asked to flush receive queue, directly |
746 | * chain it back at the queue without processing it. | |
f078f209 | 747 | */ |
be0418ad | 748 | if (flush) |
cb71d9ba | 749 | goto requeue; |
f078f209 | 750 | |
26ab2645 | 751 | if (!rx_stats->rs_datalen) |
cb71d9ba | 752 | goto requeue; |
f078f209 | 753 | |
be0418ad | 754 | /* The status portion of the descriptor could get corrupted. */ |
26ab2645 | 755 | if (sc->rx.bufsize < rx_stats->rs_datalen) |
cb71d9ba | 756 | goto requeue; |
f078f209 | 757 | |
712c13a8 LR |
758 | if (!ath_rx_prepare(common, hw, skb, rx_stats, |
759 | &rx_status, &decrypt_error)) | |
cb71d9ba LR |
760 | goto requeue; |
761 | ||
762 | /* Ensure we always have an skb to requeue once we are done | |
763 | * processing the current buffer's skb */ | |
27c51f1a | 764 | requeue_skb = ath_rxbuf_alloc(common, sc->rx.bufsize, GFP_ATOMIC); |
cb71d9ba LR |
765 | |
766 | /* If there is no memory we ignore the current RX'd frame, | |
767 | * tell hardware it can give us a new frame using the old | |
b77f483f | 768 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
769 | * processing. */ |
770 | if (!requeue_skb) | |
771 | goto requeue; | |
f078f209 | 772 | |
9bf9fca8 | 773 | /* Unmap the frame */ |
7da3c55c | 774 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 775 | sc->rx.bufsize, |
7da3c55c | 776 | DMA_FROM_DEVICE); |
f078f209 | 777 | |
26ab2645 | 778 | skb_put(skb, rx_stats->rs_datalen); |
be0418ad S |
779 | |
780 | /* see if any padding is done by the hw and remove it */ | |
be0418ad | 781 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); |
853da11b | 782 | fc = hdr->frame_control; |
be0418ad | 783 | |
9c5f89b3 JM |
784 | /* The MAC header is padded to have 32-bit boundary if the |
785 | * packet payload is non-zero. The general calculation for | |
786 | * padsize would take into account odd header lengths: | |
787 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
788 | * even-length headers are used, padding can only be 0 or 2 | |
789 | * bytes and we can optimize this a bit. In addition, we must | |
790 | * not try to remove padding from short control frames that do | |
791 | * not have payload. */ | |
792 | padsize = hdrlen & 3; | |
793 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
794 | memmove(skb->data + padsize, skb->data, hdrlen); |
795 | skb_pull(skb, padsize); | |
f078f209 LR |
796 | } |
797 | ||
26ab2645 | 798 | keyix = rx_stats->rs_keyix; |
f078f209 | 799 | |
be0418ad S |
800 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
801 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
9d64a3cf | 802 | } else if (ieee80211_has_protected(fc) |
be0418ad S |
803 | && !decrypt_error && skb->len >= hdrlen + 4) { |
804 | keyix = skb->data[hdrlen + 3] >> 6; | |
805 | ||
17d7904d | 806 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
807 | rx_status.flag |= RX_FLAG_DECRYPTED; |
808 | } | |
0ced0e17 JM |
809 | if (ah->sw_mgmt_crypto && |
810 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
9d64a3cf | 811 | ieee80211_is_mgmt(fc)) { |
0ced0e17 JM |
812 | /* Use software decrypt for management frames. */ |
813 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
814 | } | |
be0418ad | 815 | |
cb71d9ba LR |
816 | /* We will now give hardware our shiny new allocated skb */ |
817 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 818 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 819 | sc->rx.bufsize, |
7da3c55c GJ |
820 | DMA_FROM_DEVICE); |
821 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
822 | bf->bf_buf_addr))) { |
823 | dev_kfree_skb_any(requeue_skb); | |
824 | bf->bf_mpdu = NULL; | |
c46917bb LR |
825 | ath_print(common, ATH_DBG_FATAL, |
826 | "dma_mapping_error() on RX\n"); | |
b4afffc0 | 827 | ath_rx_send_to_mac80211(hw, sc, skb, &rx_status); |
f8316df1 LR |
828 | break; |
829 | } | |
cb71d9ba | 830 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
831 | |
832 | /* | |
833 | * change the default rx antenna if rx diversity chooses the | |
834 | * other antenna 3 times in a row. | |
835 | */ | |
b77f483f S |
836 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
837 | if (++sc->rx.rxotherant >= 3) | |
26ab2645 | 838 | ath_setdefantenna(sc, rx_stats->rs_antenna); |
f078f209 | 839 | } else { |
b77f483f | 840 | sc->rx.rxotherant = 0; |
f078f209 | 841 | } |
3cbb5dd7 | 842 | |
9a23f9ca | 843 | if (unlikely(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | |
f0e9a860 | 844 | SC_OP_WAIT_FOR_CAB | |
9a23f9ca | 845 | SC_OP_WAIT_FOR_PSPOLL_DATA))) |
cc65965c JM |
846 | ath_rx_ps(sc, skb); |
847 | ||
b4afffc0 | 848 | ath_rx_send_to_mac80211(hw, sc, skb, &rx_status); |
cc65965c | 849 | |
cb71d9ba | 850 | requeue: |
b77f483f | 851 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 852 | ath_rx_buf_link(sc, bf); |
be0418ad S |
853 | } while (1); |
854 | ||
b77f483f | 855 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
856 | |
857 | return 0; | |
858 | #undef PA2DESC | |
859 | } |