Commit | Line | Data |
---|---|---|
f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
b622a720 | 18 | #include "ar9003_mac.h" |
f078f209 | 19 | |
b5c80475 FF |
20 | #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb)) |
21 | ||
ededf1f8 VT |
22 | static inline bool ath9k_check_auto_sleep(struct ath_softc *sc) |
23 | { | |
24 | return sc->ps_enabled && | |
25 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); | |
26 | } | |
27 | ||
bce048d7 JM |
28 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
29 | struct ieee80211_hdr *hdr) | |
30 | { | |
c52f33d0 JM |
31 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
32 | int i; | |
33 | ||
34 | spin_lock_bh(&sc->wiphy_lock); | |
35 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
36 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
37 | if (aphy == NULL) | |
38 | continue; | |
39 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
40 | == 0) { | |
41 | hw = aphy->hw; | |
42 | break; | |
43 | } | |
44 | } | |
45 | spin_unlock_bh(&sc->wiphy_lock); | |
46 | return hw; | |
bce048d7 JM |
47 | } |
48 | ||
f078f209 LR |
49 | /* |
50 | * Setup and link descriptors. | |
51 | * | |
52 | * 11N: we can no longer afford to self link the last descriptor. | |
53 | * MAC acknowledges BA status as long as it copies frames to host | |
54 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
55 | * to a sender if last desc is self-linked. | |
f078f209 | 56 | */ |
f078f209 LR |
57 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
58 | { | |
cbe61d8a | 59 | struct ath_hw *ah = sc->sc_ah; |
cc861f74 | 60 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 LR |
61 | struct ath_desc *ds; |
62 | struct sk_buff *skb; | |
63 | ||
64 | ATH_RXBUF_RESET(bf); | |
65 | ||
66 | ds = bf->bf_desc; | |
be0418ad | 67 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
68 | ds->ds_data = bf->bf_buf_addr; |
69 | ||
be0418ad | 70 | /* virtual addr of the beginning of the buffer. */ |
f078f209 | 71 | skb = bf->bf_mpdu; |
9680e8a3 | 72 | BUG_ON(skb == NULL); |
f078f209 LR |
73 | ds->ds_vdata = skb->data; |
74 | ||
cc861f74 LR |
75 | /* |
76 | * setup rx descriptors. The rx_bufsize here tells the hardware | |
b4b6cda2 | 77 | * how much data it can DMA to us and that we are prepared |
cc861f74 LR |
78 | * to process |
79 | */ | |
b77f483f | 80 | ath9k_hw_setuprxdesc(ah, ds, |
cc861f74 | 81 | common->rx_bufsize, |
f078f209 LR |
82 | 0); |
83 | ||
b77f483f | 84 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
85 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
86 | else | |
b77f483f | 87 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 88 | |
b77f483f | 89 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
90 | ath9k_hw_rxena(ah); |
91 | } | |
92 | ||
ff37e337 S |
93 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
94 | { | |
95 | /* XXX block beacon interrupts */ | |
96 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
97 | sc->rx.defant = antenna; |
98 | sc->rx.rxotherant = 0; | |
ff37e337 S |
99 | } |
100 | ||
f078f209 LR |
101 | static void ath_opmode_init(struct ath_softc *sc) |
102 | { | |
cbe61d8a | 103 | struct ath_hw *ah = sc->sc_ah; |
1510718d LR |
104 | struct ath_common *common = ath9k_hw_common(ah); |
105 | ||
f078f209 LR |
106 | u32 rfilt, mfilt[2]; |
107 | ||
108 | /* configure rx filter */ | |
109 | rfilt = ath_calcrxfilter(sc); | |
110 | ath9k_hw_setrxfilter(ah, rfilt); | |
111 | ||
112 | /* configure bssid mask */ | |
2660b81a | 113 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
13b81559 | 114 | ath_hw_setbssidmask(common); |
f078f209 LR |
115 | |
116 | /* configure operational mode */ | |
117 | ath9k_hw_setopmode(ah); | |
118 | ||
119 | /* Handle any link-level address change. */ | |
1510718d | 120 | ath9k_hw_setmac(ah, common->macaddr); |
f078f209 LR |
121 | |
122 | /* calculate and install multicast filter */ | |
123 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 124 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
125 | } |
126 | ||
b5c80475 FF |
127 | static bool ath_rx_edma_buf_link(struct ath_softc *sc, |
128 | enum ath9k_rx_qtype qtype) | |
f078f209 | 129 | { |
b5c80475 FF |
130 | struct ath_hw *ah = sc->sc_ah; |
131 | struct ath_rx_edma *rx_edma; | |
f078f209 LR |
132 | struct sk_buff *skb; |
133 | struct ath_buf *bf; | |
f078f209 | 134 | |
b5c80475 FF |
135 | rx_edma = &sc->rx.rx_edma[qtype]; |
136 | if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize) | |
137 | return false; | |
f078f209 | 138 | |
b5c80475 FF |
139 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
140 | list_del_init(&bf->list); | |
f078f209 | 141 | |
b5c80475 FF |
142 | skb = bf->bf_mpdu; |
143 | ||
144 | ATH_RXBUF_RESET(bf); | |
145 | memset(skb->data, 0, ah->caps.rx_status_len); | |
146 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
147 | ah->caps.rx_status_len, DMA_TO_DEVICE); | |
f078f209 | 148 | |
b5c80475 FF |
149 | SKB_CB_ATHBUF(skb) = bf; |
150 | ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype); | |
151 | skb_queue_tail(&rx_edma->rx_fifo, skb); | |
f078f209 | 152 | |
b5c80475 FF |
153 | return true; |
154 | } | |
155 | ||
156 | static void ath_rx_addbuffer_edma(struct ath_softc *sc, | |
157 | enum ath9k_rx_qtype qtype, int size) | |
158 | { | |
b5c80475 FF |
159 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
160 | u32 nbuf = 0; | |
161 | ||
b5c80475 FF |
162 | if (list_empty(&sc->rx.rxbuf)) { |
163 | ath_print(common, ATH_DBG_QUEUE, "No free rx buf available\n"); | |
164 | return; | |
797fe5cb | 165 | } |
f078f209 | 166 | |
b5c80475 FF |
167 | while (!list_empty(&sc->rx.rxbuf)) { |
168 | nbuf++; | |
169 | ||
170 | if (!ath_rx_edma_buf_link(sc, qtype)) | |
171 | break; | |
172 | ||
173 | if (nbuf >= size) | |
174 | break; | |
175 | } | |
176 | } | |
177 | ||
178 | static void ath_rx_remove_buffer(struct ath_softc *sc, | |
179 | enum ath9k_rx_qtype qtype) | |
180 | { | |
181 | struct ath_buf *bf; | |
182 | struct ath_rx_edma *rx_edma; | |
183 | struct sk_buff *skb; | |
184 | ||
185 | rx_edma = &sc->rx.rx_edma[qtype]; | |
186 | ||
187 | while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) { | |
188 | bf = SKB_CB_ATHBUF(skb); | |
189 | BUG_ON(!bf); | |
190 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
191 | } | |
192 | } | |
193 | ||
194 | static void ath_rx_edma_cleanup(struct ath_softc *sc) | |
195 | { | |
196 | struct ath_buf *bf; | |
197 | ||
198 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
199 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
200 | ||
797fe5cb | 201 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
b5c80475 FF |
202 | if (bf->bf_mpdu) |
203 | dev_kfree_skb_any(bf->bf_mpdu); | |
204 | } | |
205 | ||
206 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
207 | ||
208 | kfree(sc->rx.rx_bufptr); | |
209 | sc->rx.rx_bufptr = NULL; | |
210 | } | |
211 | ||
212 | static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size) | |
213 | { | |
214 | skb_queue_head_init(&rx_edma->rx_fifo); | |
215 | skb_queue_head_init(&rx_edma->rx_buffers); | |
216 | rx_edma->rx_fifo_hwsize = size; | |
217 | } | |
218 | ||
219 | static int ath_rx_edma_init(struct ath_softc *sc, int nbufs) | |
220 | { | |
221 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
222 | struct ath_hw *ah = sc->sc_ah; | |
223 | struct sk_buff *skb; | |
224 | struct ath_buf *bf; | |
225 | int error = 0, i; | |
226 | u32 size; | |
227 | ||
228 | ||
229 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN + | |
230 | ah->caps.rx_status_len, | |
231 | min(common->cachelsz, (u16)64)); | |
232 | ||
233 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - | |
234 | ah->caps.rx_status_len); | |
235 | ||
236 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP], | |
237 | ah->caps.rx_lp_qdepth); | |
238 | ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP], | |
239 | ah->caps.rx_hp_qdepth); | |
240 | ||
241 | size = sizeof(struct ath_buf) * nbufs; | |
242 | bf = kzalloc(size, GFP_KERNEL); | |
243 | if (!bf) | |
244 | return -ENOMEM; | |
245 | ||
246 | INIT_LIST_HEAD(&sc->rx.rxbuf); | |
247 | sc->rx.rx_bufptr = bf; | |
248 | ||
249 | for (i = 0; i < nbufs; i++, bf++) { | |
cc861f74 | 250 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL); |
b5c80475 | 251 | if (!skb) { |
797fe5cb | 252 | error = -ENOMEM; |
b5c80475 | 253 | goto rx_init_fail; |
f078f209 | 254 | } |
f078f209 | 255 | |
b5c80475 | 256 | memset(skb->data, 0, common->rx_bufsize); |
797fe5cb | 257 | bf->bf_mpdu = skb; |
b5c80475 | 258 | |
797fe5cb | 259 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
cc861f74 | 260 | common->rx_bufsize, |
b5c80475 | 261 | DMA_BIDIRECTIONAL); |
797fe5cb | 262 | if (unlikely(dma_mapping_error(sc->dev, |
b5c80475 FF |
263 | bf->bf_buf_addr))) { |
264 | dev_kfree_skb_any(skb); | |
265 | bf->bf_mpdu = NULL; | |
266 | ath_print(common, ATH_DBG_FATAL, | |
267 | "dma_mapping_error() on RX init\n"); | |
268 | error = -ENOMEM; | |
269 | goto rx_init_fail; | |
270 | } | |
271 | ||
272 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
273 | } | |
274 | ||
275 | return 0; | |
276 | ||
277 | rx_init_fail: | |
278 | ath_rx_edma_cleanup(sc); | |
279 | return error; | |
280 | } | |
281 | ||
282 | static void ath_edma_start_recv(struct ath_softc *sc) | |
283 | { | |
284 | spin_lock_bh(&sc->rx.rxbuflock); | |
285 | ||
286 | ath9k_hw_rxena(sc->sc_ah); | |
287 | ||
288 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP, | |
289 | sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize); | |
290 | ||
291 | ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP, | |
292 | sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize); | |
293 | ||
294 | spin_unlock_bh(&sc->rx.rxbuflock); | |
295 | ||
296 | ath_opmode_init(sc); | |
297 | ||
298 | ath9k_hw_startpcureceive(sc->sc_ah); | |
299 | } | |
300 | ||
301 | static void ath_edma_stop_recv(struct ath_softc *sc) | |
302 | { | |
303 | spin_lock_bh(&sc->rx.rxbuflock); | |
304 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP); | |
305 | ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP); | |
306 | spin_unlock_bh(&sc->rx.rxbuflock); | |
307 | } | |
308 | ||
309 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
310 | { | |
311 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); | |
312 | struct sk_buff *skb; | |
313 | struct ath_buf *bf; | |
314 | int error = 0; | |
315 | ||
316 | spin_lock_init(&sc->rx.rxflushlock); | |
317 | sc->sc_flags &= ~SC_OP_RXFLUSH; | |
318 | spin_lock_init(&sc->rx.rxbuflock); | |
319 | ||
320 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { | |
321 | return ath_rx_edma_init(sc, nbufs); | |
322 | } else { | |
323 | common->rx_bufsize = roundup(IEEE80211_MAX_MPDU_LEN, | |
324 | min(common->cachelsz, (u16)64)); | |
325 | ||
326 | ath_print(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", | |
327 | common->cachelsz, common->rx_bufsize); | |
328 | ||
329 | /* Initialize rx descriptors */ | |
330 | ||
331 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, | |
4adfcded | 332 | "rx", nbufs, 1, 0); |
b5c80475 | 333 | if (error != 0) { |
c46917bb | 334 | ath_print(common, ATH_DBG_FATAL, |
b5c80475 FF |
335 | "failed to allocate rx descriptors: %d\n", |
336 | error); | |
797fe5cb S |
337 | goto err; |
338 | } | |
b5c80475 FF |
339 | |
340 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
341 | skb = ath_rxbuf_alloc(common, common->rx_bufsize, | |
342 | GFP_KERNEL); | |
343 | if (skb == NULL) { | |
344 | error = -ENOMEM; | |
345 | goto err; | |
346 | } | |
347 | ||
348 | bf->bf_mpdu = skb; | |
349 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, | |
350 | common->rx_bufsize, | |
351 | DMA_FROM_DEVICE); | |
352 | if (unlikely(dma_mapping_error(sc->dev, | |
353 | bf->bf_buf_addr))) { | |
354 | dev_kfree_skb_any(skb); | |
355 | bf->bf_mpdu = NULL; | |
356 | ath_print(common, ATH_DBG_FATAL, | |
357 | "dma_mapping_error() on RX init\n"); | |
358 | error = -ENOMEM; | |
359 | goto err; | |
360 | } | |
361 | bf->bf_dmacontext = bf->bf_buf_addr; | |
362 | } | |
363 | sc->rx.rxlink = NULL; | |
797fe5cb | 364 | } |
f078f209 | 365 | |
797fe5cb | 366 | err: |
f078f209 LR |
367 | if (error) |
368 | ath_rx_cleanup(sc); | |
369 | ||
370 | return error; | |
371 | } | |
372 | ||
f078f209 LR |
373 | void ath_rx_cleanup(struct ath_softc *sc) |
374 | { | |
cc861f74 LR |
375 | struct ath_hw *ah = sc->sc_ah; |
376 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 LR |
377 | struct sk_buff *skb; |
378 | struct ath_buf *bf; | |
379 | ||
b5c80475 FF |
380 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
381 | ath_rx_edma_cleanup(sc); | |
382 | return; | |
383 | } else { | |
384 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { | |
385 | skb = bf->bf_mpdu; | |
386 | if (skb) { | |
387 | dma_unmap_single(sc->dev, bf->bf_buf_addr, | |
388 | common->rx_bufsize, | |
389 | DMA_FROM_DEVICE); | |
390 | dev_kfree_skb(skb); | |
391 | } | |
051b9191 | 392 | } |
f078f209 | 393 | |
b5c80475 FF |
394 | if (sc->rx.rxdma.dd_desc_len != 0) |
395 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
396 | } | |
f078f209 LR |
397 | } |
398 | ||
399 | /* | |
400 | * Calculate the receive filter according to the | |
401 | * operating mode and state: | |
402 | * | |
403 | * o always accept unicast, broadcast, and multicast traffic | |
404 | * o maintain current state of phy error reception (the hal | |
405 | * may enable phy error frames for noise immunity work) | |
406 | * o probe request frames are accepted only when operating in | |
407 | * hostap, adhoc, or monitor modes | |
408 | * o enable promiscuous mode according to the interface state | |
409 | * o accept beacons: | |
410 | * - when operating in adhoc mode so the 802.11 layer creates | |
411 | * node table entries for peers, | |
412 | * - when operating in station mode for collecting rssi data when | |
413 | * the station is otherwise quiet, or | |
414 | * - when operating as a repeater so we see repeater-sta beacons | |
415 | * - when scanning | |
416 | */ | |
417 | ||
418 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
419 | { | |
420 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 421 | |
f078f209 LR |
422 | u32 rfilt; |
423 | ||
424 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
425 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
426 | | ATH9K_RX_FILTER_MCAST; | |
427 | ||
428 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 429 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
430 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
431 | ||
217ba9da JM |
432 | /* |
433 | * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station | |
434 | * mode interface or when in monitor mode. AP mode does not need this | |
435 | * since it receives all in-BSS frames anyway. | |
436 | */ | |
2660b81a | 437 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 438 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
217ba9da | 439 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) |
f078f209 | 440 | rfilt |= ATH9K_RX_FILTER_PROM; |
f078f209 | 441 | |
d42c6b71 S |
442 | if (sc->rx.rxfilter & FIF_CONTROL) |
443 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
444 | ||
dbaaa147 VT |
445 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
446 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
447 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
448 | else | |
f078f209 LR |
449 | rfilt |= ATH9K_RX_FILTER_BEACON; |
450 | ||
66afad01 SB |
451 | if ((AR_SREV_9280_10_OR_LATER(sc->sc_ah) || |
452 | AR_SREV_9285_10_OR_LATER(sc->sc_ah)) && | |
453 | (sc->sc_ah->opmode == NL80211_IFTYPE_AP) && | |
454 | (sc->rx.rxfilter & FIF_PSPOLL)) | |
dbaaa147 | 455 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 456 | |
7ea310be S |
457 | if (conf_is_ht(&sc->hw->conf)) |
458 | rfilt |= ATH9K_RX_FILTER_COMP_BAR; | |
459 | ||
5eb6ba83 | 460 | if (sc->sec_wiphy || (sc->rx.rxfilter & FIF_OTHER_BSS)) { |
b93bce2a JM |
461 | /* TODO: only needed if more than one BSSID is in use in |
462 | * station/adhoc mode */ | |
5eb6ba83 JC |
463 | /* The following may also be needed for other older chips */ |
464 | if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160) | |
465 | rfilt |= ATH9K_RX_FILTER_PROM; | |
b93bce2a JM |
466 | rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL; |
467 | } | |
468 | ||
f078f209 | 469 | return rfilt; |
7dcfdcd9 | 470 | |
f078f209 LR |
471 | #undef RX_FILTER_PRESERVE |
472 | } | |
473 | ||
f078f209 LR |
474 | int ath_startrecv(struct ath_softc *sc) |
475 | { | |
cbe61d8a | 476 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
477 | struct ath_buf *bf, *tbf; |
478 | ||
b5c80475 FF |
479 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
480 | ath_edma_start_recv(sc); | |
481 | return 0; | |
482 | } | |
483 | ||
b77f483f S |
484 | spin_lock_bh(&sc->rx.rxbuflock); |
485 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
486 | goto start_recv; |
487 | ||
b77f483f S |
488 | sc->rx.rxlink = NULL; |
489 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
490 | ath_rx_buf_link(sc, bf); |
491 | } | |
492 | ||
493 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 494 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
495 | goto start_recv; |
496 | ||
b77f483f | 497 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 498 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 499 | ath9k_hw_rxena(ah); |
f078f209 LR |
500 | |
501 | start_recv: | |
b77f483f | 502 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
503 | ath_opmode_init(sc); |
504 | ath9k_hw_startpcureceive(ah); | |
505 | ||
f078f209 LR |
506 | return 0; |
507 | } | |
508 | ||
f078f209 LR |
509 | bool ath_stoprecv(struct ath_softc *sc) |
510 | { | |
cbe61d8a | 511 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
512 | bool stopped; |
513 | ||
be0418ad S |
514 | ath9k_hw_stoppcurecv(ah); |
515 | ath9k_hw_setrxfilter(ah, 0); | |
516 | stopped = ath9k_hw_stopdmarecv(ah); | |
b5c80475 FF |
517 | |
518 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
519 | ath_edma_stop_recv(sc); | |
520 | else | |
521 | sc->rx.rxlink = NULL; | |
be0418ad | 522 | |
f078f209 LR |
523 | return stopped; |
524 | } | |
525 | ||
f078f209 LR |
526 | void ath_flushrecv(struct ath_softc *sc) |
527 | { | |
b77f483f | 528 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 529 | sc->sc_flags |= SC_OP_RXFLUSH; |
b5c80475 FF |
530 | if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
531 | ath_rx_tasklet(sc, 1, true); | |
532 | ath_rx_tasklet(sc, 1, false); | |
98deeea0 | 533 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 534 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
535 | } |
536 | ||
cc65965c JM |
537 | static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb) |
538 | { | |
539 | /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */ | |
540 | struct ieee80211_mgmt *mgmt; | |
541 | u8 *pos, *end, id, elen; | |
542 | struct ieee80211_tim_ie *tim; | |
543 | ||
544 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
545 | pos = mgmt->u.beacon.variable; | |
546 | end = skb->data + skb->len; | |
547 | ||
548 | while (pos + 2 < end) { | |
549 | id = *pos++; | |
550 | elen = *pos++; | |
551 | if (pos + elen > end) | |
552 | break; | |
553 | ||
554 | if (id == WLAN_EID_TIM) { | |
555 | if (elen < sizeof(*tim)) | |
556 | break; | |
557 | tim = (struct ieee80211_tim_ie *) pos; | |
558 | if (tim->dtim_count != 0) | |
559 | break; | |
560 | return tim->bitmap_ctrl & 0x01; | |
561 | } | |
562 | ||
563 | pos += elen; | |
564 | } | |
565 | ||
566 | return false; | |
567 | } | |
568 | ||
cc65965c JM |
569 | static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb) |
570 | { | |
571 | struct ieee80211_mgmt *mgmt; | |
1510718d | 572 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
573 | |
574 | if (skb->len < 24 + 8 + 2 + 2) | |
575 | return; | |
576 | ||
577 | mgmt = (struct ieee80211_mgmt *)skb->data; | |
1510718d | 578 | if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) |
cc65965c JM |
579 | return; /* not from our current AP */ |
580 | ||
1b04b930 | 581 | sc->ps_flags &= ~PS_WAIT_FOR_BEACON; |
293dc5df | 582 | |
1b04b930 S |
583 | if (sc->ps_flags & PS_BEACON_SYNC) { |
584 | sc->ps_flags &= ~PS_BEACON_SYNC; | |
c46917bb LR |
585 | ath_print(common, ATH_DBG_PS, |
586 | "Reconfigure Beacon timers based on " | |
587 | "timestamp from the AP\n"); | |
ccdfeab6 JM |
588 | ath_beacon_config(sc, NULL); |
589 | } | |
590 | ||
cc65965c JM |
591 | if (ath_beacon_dtim_pending_cab(skb)) { |
592 | /* | |
593 | * Remain awake waiting for buffered broadcast/multicast | |
58f5fffd GJ |
594 | * frames. If the last broadcast/multicast frame is not |
595 | * received properly, the next beacon frame will work as | |
596 | * a backup trigger for returning into NETWORK SLEEP state, | |
597 | * so we are waiting for it as well. | |
cc65965c | 598 | */ |
c46917bb LR |
599 | ath_print(common, ATH_DBG_PS, "Received DTIM beacon indicating " |
600 | "buffered broadcast/multicast frame(s)\n"); | |
1b04b930 | 601 | sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON; |
cc65965c JM |
602 | return; |
603 | } | |
604 | ||
1b04b930 | 605 | if (sc->ps_flags & PS_WAIT_FOR_CAB) { |
cc65965c JM |
606 | /* |
607 | * This can happen if a broadcast frame is dropped or the AP | |
608 | * fails to send a frame indicating that all CAB frames have | |
609 | * been delivered. | |
610 | */ | |
1b04b930 | 611 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
c46917bb LR |
612 | ath_print(common, ATH_DBG_PS, |
613 | "PS wait for CAB frames timed out\n"); | |
cc65965c | 614 | } |
cc65965c JM |
615 | } |
616 | ||
617 | static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb) | |
618 | { | |
619 | struct ieee80211_hdr *hdr; | |
c46917bb | 620 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
cc65965c JM |
621 | |
622 | hdr = (struct ieee80211_hdr *)skb->data; | |
623 | ||
624 | /* Process Beacon and CAB receive in PS state */ | |
ededf1f8 VT |
625 | if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc)) |
626 | && ieee80211_is_beacon(hdr->frame_control)) | |
cc65965c | 627 | ath_rx_ps_beacon(sc, skb); |
1b04b930 | 628 | else if ((sc->ps_flags & PS_WAIT_FOR_CAB) && |
cc65965c JM |
629 | (ieee80211_is_data(hdr->frame_control) || |
630 | ieee80211_is_action(hdr->frame_control)) && | |
631 | is_multicast_ether_addr(hdr->addr1) && | |
632 | !ieee80211_has_moredata(hdr->frame_control)) { | |
cc65965c JM |
633 | /* |
634 | * No more broadcast/multicast frames to be received at this | |
635 | * point. | |
636 | */ | |
1b04b930 | 637 | sc->ps_flags &= ~PS_WAIT_FOR_CAB; |
c46917bb LR |
638 | ath_print(common, ATH_DBG_PS, |
639 | "All PS CAB frames received, back to sleep\n"); | |
1b04b930 | 640 | } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) && |
9a23f9ca JM |
641 | !is_multicast_ether_addr(hdr->addr1) && |
642 | !ieee80211_has_morefrags(hdr->frame_control)) { | |
1b04b930 | 643 | sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA; |
c46917bb LR |
644 | ath_print(common, ATH_DBG_PS, |
645 | "Going back to sleep after having received " | |
f643e51d | 646 | "PS-Poll data (0x%lx)\n", |
1b04b930 S |
647 | sc->ps_flags & (PS_WAIT_FOR_BEACON | |
648 | PS_WAIT_FOR_CAB | | |
649 | PS_WAIT_FOR_PSPOLL_DATA | | |
650 | PS_WAIT_FOR_TX_ACK)); | |
cc65965c JM |
651 | } |
652 | } | |
653 | ||
b4afffc0 LR |
654 | static void ath_rx_send_to_mac80211(struct ieee80211_hw *hw, |
655 | struct ath_softc *sc, struct sk_buff *skb, | |
5ca42627 | 656 | struct ieee80211_rx_status *rxs) |
9d64a3cf JM |
657 | { |
658 | struct ieee80211_hdr *hdr; | |
659 | ||
660 | hdr = (struct ieee80211_hdr *)skb->data; | |
661 | ||
662 | /* Send the frame to mac80211 */ | |
663 | if (is_multicast_ether_addr(hdr->addr1)) { | |
664 | int i; | |
665 | /* | |
666 | * Deliver broadcast/multicast frames to all suitable | |
667 | * virtual wiphys. | |
668 | */ | |
669 | /* TODO: filter based on channel configuration */ | |
670 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
671 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
672 | struct sk_buff *nskb; | |
673 | if (aphy == NULL) | |
674 | continue; | |
675 | nskb = skb_copy(skb, GFP_ATOMIC); | |
5ca42627 LR |
676 | if (!nskb) |
677 | continue; | |
678 | ieee80211_rx(aphy->hw, nskb); | |
9d64a3cf | 679 | } |
f1d58c25 | 680 | ieee80211_rx(sc->hw, skb); |
5ca42627 | 681 | } else |
9d64a3cf | 682 | /* Deliver unicast frames based on receiver address */ |
b4afffc0 | 683 | ieee80211_rx(hw, skb); |
9d64a3cf JM |
684 | } |
685 | ||
b5c80475 FF |
686 | static bool ath_edma_get_buffers(struct ath_softc *sc, |
687 | enum ath9k_rx_qtype qtype) | |
f078f209 | 688 | { |
b5c80475 FF |
689 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; |
690 | struct ath_hw *ah = sc->sc_ah; | |
691 | struct ath_common *common = ath9k_hw_common(ah); | |
692 | struct sk_buff *skb; | |
693 | struct ath_buf *bf; | |
694 | int ret; | |
695 | ||
696 | skb = skb_peek(&rx_edma->rx_fifo); | |
697 | if (!skb) | |
698 | return false; | |
699 | ||
700 | bf = SKB_CB_ATHBUF(skb); | |
701 | BUG_ON(!bf); | |
702 | ||
703 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
704 | common->rx_bufsize, DMA_FROM_DEVICE); | |
705 | ||
706 | ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data); | |
707 | if (ret == -EINPROGRESS) | |
708 | return false; | |
709 | ||
710 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
711 | if (ret == -EINVAL) { | |
712 | /* corrupt descriptor, skip this one and the following one */ | |
713 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
714 | ath_rx_edma_buf_link(sc, qtype); | |
715 | skb = skb_peek(&rx_edma->rx_fifo); | |
716 | if (!skb) | |
717 | return true; | |
718 | ||
719 | bf = SKB_CB_ATHBUF(skb); | |
720 | BUG_ON(!bf); | |
721 | ||
722 | __skb_unlink(skb, &rx_edma->rx_fifo); | |
723 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
724 | ath_rx_edma_buf_link(sc, qtype); | |
083e3e8d | 725 | return true; |
b5c80475 FF |
726 | } |
727 | skb_queue_tail(&rx_edma->rx_buffers, skb); | |
728 | ||
729 | return true; | |
730 | } | |
f078f209 | 731 | |
b5c80475 FF |
732 | static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc, |
733 | struct ath_rx_status *rs, | |
734 | enum ath9k_rx_qtype qtype) | |
735 | { | |
736 | struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype]; | |
737 | struct sk_buff *skb; | |
be0418ad | 738 | struct ath_buf *bf; |
b5c80475 FF |
739 | |
740 | while (ath_edma_get_buffers(sc, qtype)); | |
741 | skb = __skb_dequeue(&rx_edma->rx_buffers); | |
742 | if (!skb) | |
743 | return NULL; | |
744 | ||
745 | bf = SKB_CB_ATHBUF(skb); | |
746 | ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data); | |
747 | return bf; | |
748 | } | |
749 | ||
750 | static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc, | |
751 | struct ath_rx_status *rs) | |
752 | { | |
753 | struct ath_hw *ah = sc->sc_ah; | |
754 | struct ath_common *common = ath9k_hw_common(ah); | |
f078f209 | 755 | struct ath_desc *ds; |
b5c80475 FF |
756 | struct ath_buf *bf; |
757 | int ret; | |
758 | ||
759 | if (list_empty(&sc->rx.rxbuf)) { | |
760 | sc->rx.rxlink = NULL; | |
761 | return NULL; | |
762 | } | |
763 | ||
764 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); | |
765 | ds = bf->bf_desc; | |
766 | ||
767 | /* | |
768 | * Must provide the virtual address of the current | |
769 | * descriptor, the physical address, and the virtual | |
770 | * address of the next descriptor in the h/w chain. | |
771 | * This allows the HAL to look ahead to see if the | |
772 | * hardware is done with a descriptor by checking the | |
773 | * done bit in the following descriptor and the address | |
774 | * of the current descriptor the DMA engine is working | |
775 | * on. All this is necessary because of our use of | |
776 | * a self-linked list to avoid rx overruns. | |
777 | */ | |
778 | ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0); | |
779 | if (ret == -EINPROGRESS) { | |
780 | struct ath_rx_status trs; | |
781 | struct ath_buf *tbf; | |
782 | struct ath_desc *tds; | |
783 | ||
784 | memset(&trs, 0, sizeof(trs)); | |
785 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { | |
786 | sc->rx.rxlink = NULL; | |
787 | return NULL; | |
788 | } | |
789 | ||
790 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
791 | ||
792 | /* | |
793 | * On some hardware the descriptor status words could | |
794 | * get corrupted, including the done bit. Because of | |
795 | * this, check if the next descriptor's done bit is | |
796 | * set or not. | |
797 | * | |
798 | * If the next descriptor's done bit is set, the current | |
799 | * descriptor has been corrupted. Force s/w to discard | |
800 | * this descriptor and continue... | |
801 | */ | |
802 | ||
803 | tds = tbf->bf_desc; | |
804 | ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0); | |
805 | if (ret == -EINPROGRESS) | |
806 | return NULL; | |
807 | } | |
808 | ||
809 | if (!bf->bf_mpdu) | |
810 | return bf; | |
811 | ||
812 | /* | |
813 | * Synchronize the DMA transfer with CPU before | |
814 | * 1. accessing the frame | |
815 | * 2. requeueing the same buffer to h/w | |
816 | */ | |
817 | dma_sync_single_for_device(sc->dev, bf->bf_buf_addr, | |
818 | common->rx_bufsize, | |
819 | DMA_FROM_DEVICE); | |
820 | ||
821 | return bf; | |
822 | } | |
823 | ||
824 | ||
825 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp) | |
826 | { | |
827 | struct ath_buf *bf; | |
cb71d9ba | 828 | struct sk_buff *skb = NULL, *requeue_skb; |
5ca42627 | 829 | struct ieee80211_rx_status *rxs; |
cbe61d8a | 830 | struct ath_hw *ah = sc->sc_ah; |
27c51f1a | 831 | struct ath_common *common = ath9k_hw_common(ah); |
b4afffc0 LR |
832 | /* |
833 | * The hw can techncically differ from common->hw when using ath9k | |
834 | * virtual wiphy so to account for that we iterate over the active | |
835 | * wiphys and find the appropriate wiphy and therefore hw. | |
836 | */ | |
837 | struct ieee80211_hw *hw = NULL; | |
be0418ad | 838 | struct ieee80211_hdr *hdr; |
c9b14170 | 839 | int retval; |
be0418ad | 840 | bool decrypt_error = false; |
29bffa96 | 841 | struct ath_rx_status rs; |
b5c80475 FF |
842 | enum ath9k_rx_qtype qtype; |
843 | bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA); | |
844 | int dma_type; | |
be0418ad | 845 | |
b5c80475 FF |
846 | if (edma) |
847 | dma_type = DMA_FROM_DEVICE; | |
848 | else | |
849 | dma_type = DMA_BIDIRECTIONAL; | |
850 | ||
851 | qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP; | |
b77f483f | 852 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
853 | |
854 | do { | |
855 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 856 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
857 | break; |
858 | ||
29bffa96 | 859 | memset(&rs, 0, sizeof(rs)); |
b5c80475 FF |
860 | if (edma) |
861 | bf = ath_edma_get_next_rx_buf(sc, &rs, qtype); | |
862 | else | |
863 | bf = ath_get_next_rx_buf(sc, &rs); | |
f078f209 | 864 | |
b5c80475 FF |
865 | if (!bf) |
866 | break; | |
f078f209 | 867 | |
f078f209 | 868 | skb = bf->bf_mpdu; |
be0418ad | 869 | if (!skb) |
f078f209 | 870 | continue; |
f078f209 | 871 | |
b4afffc0 | 872 | hdr = (struct ieee80211_hdr *) skb->data; |
5ca42627 LR |
873 | rxs = IEEE80211_SKB_RXCB(skb); |
874 | ||
b4afffc0 LR |
875 | hw = ath_get_virt_hw(sc, hdr); |
876 | ||
29bffa96 | 877 | ath_debug_stat_rx(sc, &rs); |
1395d3f0 | 878 | |
f078f209 | 879 | /* |
be0418ad S |
880 | * If we're asked to flush receive queue, directly |
881 | * chain it back at the queue without processing it. | |
f078f209 | 882 | */ |
be0418ad | 883 | if (flush) |
cb71d9ba | 884 | goto requeue; |
f078f209 | 885 | |
29bffa96 | 886 | retval = ath9k_cmn_rx_skb_preprocess(common, hw, skb, &rs, |
db86f07e | 887 | rxs, &decrypt_error); |
1e875e9f | 888 | if (retval) |
cb71d9ba LR |
889 | goto requeue; |
890 | ||
891 | /* Ensure we always have an skb to requeue once we are done | |
892 | * processing the current buffer's skb */ | |
cc861f74 | 893 | requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC); |
cb71d9ba LR |
894 | |
895 | /* If there is no memory we ignore the current RX'd frame, | |
896 | * tell hardware it can give us a new frame using the old | |
b77f483f | 897 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
898 | * processing. */ |
899 | if (!requeue_skb) | |
900 | goto requeue; | |
f078f209 | 901 | |
9bf9fca8 | 902 | /* Unmap the frame */ |
7da3c55c | 903 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
cc861f74 | 904 | common->rx_bufsize, |
b5c80475 | 905 | dma_type); |
f078f209 | 906 | |
b5c80475 FF |
907 | skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len); |
908 | if (ah->caps.rx_status_len) | |
909 | skb_pull(skb, ah->caps.rx_status_len); | |
be0418ad | 910 | |
29bffa96 | 911 | ath9k_cmn_rx_skb_postprocess(common, skb, &rs, |
db86f07e | 912 | rxs, decrypt_error); |
be0418ad | 913 | |
cb71d9ba LR |
914 | /* We will now give hardware our shiny new allocated skb */ |
915 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 916 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
cc861f74 | 917 | common->rx_bufsize, |
b5c80475 | 918 | dma_type); |
7da3c55c | 919 | if (unlikely(dma_mapping_error(sc->dev, |
f8316df1 LR |
920 | bf->bf_buf_addr))) { |
921 | dev_kfree_skb_any(requeue_skb); | |
922 | bf->bf_mpdu = NULL; | |
c46917bb LR |
923 | ath_print(common, ATH_DBG_FATAL, |
924 | "dma_mapping_error() on RX\n"); | |
5ca42627 | 925 | ath_rx_send_to_mac80211(hw, sc, skb, rxs); |
f8316df1 LR |
926 | break; |
927 | } | |
cb71d9ba | 928 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
929 | |
930 | /* | |
931 | * change the default rx antenna if rx diversity chooses the | |
932 | * other antenna 3 times in a row. | |
933 | */ | |
29bffa96 | 934 | if (sc->rx.defant != rs.rs_antenna) { |
b77f483f | 935 | if (++sc->rx.rxotherant >= 3) |
29bffa96 | 936 | ath_setdefantenna(sc, rs.rs_antenna); |
f078f209 | 937 | } else { |
b77f483f | 938 | sc->rx.rxotherant = 0; |
f078f209 | 939 | } |
3cbb5dd7 | 940 | |
ededf1f8 VT |
941 | if (unlikely(ath9k_check_auto_sleep(sc) || |
942 | (sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
943 | PS_WAIT_FOR_CAB | | |
944 | PS_WAIT_FOR_PSPOLL_DATA)))) | |
cc65965c JM |
945 | ath_rx_ps(sc, skb); |
946 | ||
5ca42627 | 947 | ath_rx_send_to_mac80211(hw, sc, skb, rxs); |
cc65965c | 948 | |
cb71d9ba | 949 | requeue: |
b5c80475 FF |
950 | if (edma) { |
951 | list_add_tail(&bf->list, &sc->rx.rxbuf); | |
952 | ath_rx_edma_buf_link(sc, qtype); | |
953 | } else { | |
954 | list_move_tail(&bf->list, &sc->rx.rxbuf); | |
955 | ath_rx_buf_link(sc, bf); | |
956 | } | |
be0418ad S |
957 | } while (1); |
958 | ||
b77f483f | 959 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
960 | |
961 | return 0; | |
f078f209 | 962 | } |