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ath9k: stop ani when the STA gets disconnected.
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
ff37e337
S		 247/*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251*/
0e2dedf9
JM		 252int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
ff37e337 254{
cbe61d8a 255 struct ath_hw *ah = sc->sc_ah;
ff37e337 256 bool fastcc = true, stopped;
ae8d2858
LR		 257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
ff37e337
S		 259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
3cbb5dd7
VN		 263 ath9k_ps_wakeup(sc);
264
c0d7c7af
LR		 265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
043a0405 275 ath_drain_all_txq(sc, false);
c0d7c7af 276 stopped = ath_stoprecv(sc);
ff37e337 277
c0d7c7af
LR		 278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
ff37e337 281
c0d7c7af
LR		 282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 287 sc->sc_ah->curchan->channel,
c0d7c7af 288 channel->center_freq, sc->tx_chan_width);
ff37e337 289
c0d7c7af
LR		 290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
6b45784f 296 "reset status %d\n",
c0d7c7af
LR		 297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
3989279c 299 goto ps_restore;
ff37e337 300 }
c0d7c7af
LR		 301 spin_unlock_bh(&sc->sc_resetlock);
302
c0d7c7af
LR		 303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
3989279c
GJ		 308 r = -EIO;
309 goto ps_restore;
c0d7c7af
LR		 310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
17d7904d 314 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 315
316 ps_restore:
3cbb5dd7 317 ath9k_ps_restore(sc);
3989279c 318 return r;
ff37e337
S		 319}
320
321/*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328static void ath_ani_calibrate(unsigned long data)
329{
20977d3e
S		 330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 336 u32 cal_interval, short_cal_interval;
ff37e337 337
20977d3e
S		 338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
0c98de65 345 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 346 goto set_timer;
ff37e337 347
1ffc1c61
JM		 348 /* Only calibrate if awake */
349 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
350 goto set_timer;
351
352 ath9k_ps_wakeup(sc);
353
ff37e337 354 /* Long calibration runs independently of short calibration. */
17d7904d 355 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 356 longcal = true;
04bd4638 357 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 358 sc->ani.longcal_timer = timestamp;
ff37e337
S		 359 }
360
17d7904d
S		 361 /* Short calibration applies only while caldone is false */
362 if (!sc->ani.caldone) {
20977d3e 363 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 364 shortcal = true;
04bd4638 365 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 366 sc->ani.shortcal_timer = timestamp;
367 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 368 }
369 } else {
17d7904d 370 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 371 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 372 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
373 if (sc->ani.caldone)
374 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 375 }
376 }
377
378 /* Verify whether we must check ANI */
20977d3e 379 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 380 aniflag = true;
17d7904d 381 sc->ani.checkani_timer = timestamp;
ff37e337
S		 382 }
383
384 /* Skip all processing if there's nothing to do. */
385 if (longcal || shortcal || aniflag) {
386 /* Call ANI routine if necessary */
387 if (aniflag)
20977d3e 388 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 389
390 /* Perform calibration if necessary */
391 if (longcal || shortcal) {
379f0440
S		 392 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
393 sc->rx_chainmask, longcal);
394
395 if (longcal)
396 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
397 ah->curchan);
398
399 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
400 ah->curchan->channel, ah->curchan->channelFlags,
401 sc->ani.noise_floor);
ff37e337
S		 402 }
403 }
404
1ffc1c61
JM		 405 ath9k_ps_restore(sc);
406
20977d3e 407set_timer:
ff37e337
S		 408 /*
409 * Set timer interval based on previous results.
410 * The interval must be the shortest necessary to satisfy ANI,
411 * short calibration and long calibration.
412 */
aac9207e 413 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 414 if (sc->sc_ah->config.enable_ani)
aac9207e 415 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 416 if (!sc->ani.caldone)
20977d3e 417 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 418
17d7904d 419 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 420}
421
415f738e
S		 422static void ath_start_ani(struct ath_softc *sc)
423{
424 unsigned long timestamp = jiffies_to_msecs(jiffies);
425
426 sc->ani.longcal_timer = timestamp;
427 sc->ani.shortcal_timer = timestamp;
428 sc->ani.checkani_timer = timestamp;
429
430 mod_timer(&sc->ani.timer,
431 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
432}
433
ff37e337
S		 434/*
435 * Update tx/rx chainmask. For legacy association,
436 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 437 * the chainmask configuration, for bt coexistence, use
438 * the chainmask configuration even in legacy mode.
ff37e337 439 */
0e2dedf9 440void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 441{
c97c92d9 442 if (is_ht ||
2660b81a
S		 443 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
444 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
445 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 446 } else {
17d7904d
S		 447 sc->tx_chainmask = 1;
448 sc->rx_chainmask = 1;
ff37e337
S		 449 }
450
04bd4638 451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 452 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 453}
454
455static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
456{
457 struct ath_node *an;
458
459 an = (struct ath_node *)sta->drv_priv;
460
87792efc 461 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 462 ath_tx_node_init(sc, an);
87792efc
S		 463 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
464 sta->ht_cap.ampdu_factor);
465 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
466 }
ff37e337
S		 467}
468
469static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
470{
471 struct ath_node *an = (struct ath_node *)sta->drv_priv;
472
473 if (sc->sc_flags & SC_OP_TXAGGR)
474 ath_tx_node_cleanup(sc, an);
475}
476
477static void ath9k_tasklet(unsigned long data)
478{
479 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 480 u32 status = sc->intrstatus;
ff37e337 481
153e080d
VT		 482 ath9k_ps_wakeup(sc);
483
ff37e337 484 if (status & ATH9K_INT_FATAL) {
ff37e337 485 ath_reset(sc, false);
153e080d 486 ath9k_ps_restore(sc);
ff37e337 487 return;
063d8be3 488 }
ff37e337 489
063d8be3
S		 490 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
491 spin_lock_bh(&sc->rx.rxflushlock);
492 ath_rx_tasklet(sc, 0);
493 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 494 }
495
063d8be3
S		 496 if (status & ATH9K_INT_TX)
497 ath_tx_tasklet(sc);
498
54ce846e
JM		 499 if ((status & ATH9K_INT_TSFOOR) &&
500 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
501 /*
502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon.
504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 507 }
508
ff37e337 509 /* re-enable hardware interrupt */
17d7904d 510 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 511 ath9k_ps_restore(sc);
ff37e337
S		 512}
513
6baff7f9 514irqreturn_t ath_isr(int irq, void *dev)
ff37e337 515{
063d8be3
S		 516#define SCHED_INTR ( \
517 ATH9K_INT_FATAL | \
518 ATH9K_INT_RXORN | \
519 ATH9K_INT_RXEOL | \
520 ATH9K_INT_RX | \
521 ATH9K_INT_TX | \
522 ATH9K_INT_BMISS | \
523 ATH9K_INT_CST | \
524 ATH9K_INT_TSFOOR)
525
ff37e337 526 struct ath_softc *sc = dev;
cbe61d8a 527 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 528 enum ath9k_int status;
529 bool sched = false;
530
063d8be3
S		 531 /*
532 * The hardware is not ready/present, don't
533 * touch anything. Note this can happen early
534 * on if the IRQ is shared.
535 */
536 if (sc->sc_flags & SC_OP_INVALID)
537 return IRQ_NONE;
ff37e337 538
063d8be3
S		 539
540 /* shared irq, not for us */
541
153e080d 542 if (!ath9k_hw_intrpend(ah))
063d8be3 543 return IRQ_NONE;
063d8be3
S		 544
545 /*
546 * Figure out the reason(s) for the interrupt. Note
547 * that the hal returns a pseudo-ISR that may include
548 * bits we haven't explicitly enabled so we mask the
549 * value to insure we only process bits we requested.
550 */
551 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
552 status &= sc->imask; /* discard unasked-for bits */
ff37e337 553
063d8be3
S		 554 /*
555 * If there are no status bits set, then this interrupt was not
556 * for me (should have been caught above).
557 */
153e080d 558 if (!status)
063d8be3 559 return IRQ_NONE;
ff37e337 560
063d8be3
S		 561 /* Cache the status */
562 sc->intrstatus = status;
563
564 if (status & SCHED_INTR)
565 sched = true;
566
567 /*
568 * If a FATAL or RXORN interrupt is received, we have to reset the
569 * chip immediately.
570 */
571 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
572 goto chip_reset;
573
574 if (status & ATH9K_INT_SWBA)
575 tasklet_schedule(&sc->bcon_tasklet);
576
577 if (status & ATH9K_INT_TXURN)
578 ath9k_hw_updatetxtriglevel(ah, true);
579
580 if (status & ATH9K_INT_MIB) {
ff37e337 581 /*
063d8be3
S		 582 * Disable interrupts until we service the MIB
583 * interrupt; otherwise it will continue to
584 * fire.
ff37e337 585 */
063d8be3
S		 586 ath9k_hw_set_interrupts(ah, 0);
587 /*
588 * Let the hal handle the event. We assume
589 * it will clear whatever condition caused
590 * the interrupt.
591 */
592 ath9k_hw_procmibevent(ah, &sc->nodestats);
593 ath9k_hw_set_interrupts(ah, sc->imask);
594 }
ff37e337 595
153e080d
VT		 596 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
597 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 598 /* Clear RxAbort bit so that we can
599 * receive frames */
600 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 601 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 602 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 603 }
063d8be3
S		 604
605chip_reset:
ff37e337 606
817e11de
S		 607 ath_debug_stat_interrupt(sc, status);
608
ff37e337
S		 609 if (sched) {
610 /* turn off every interrupt except SWBA */
17d7904d 611 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 612 tasklet_schedule(&sc->intr_tq);
613 }
614
615 return IRQ_HANDLED;
063d8be3
S		 616
617#undef SCHED_INTR
ff37e337
S		 618}
619
f078f209 620static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 621 struct ieee80211_channel *chan,
094d05dc 622 enum nl80211_channel_type channel_type)
f078f209
LR		 623{
624 u32 chanmode = 0;
f078f209
LR		 625
626 switch (chan->band) {
627 case IEEE80211_BAND_2GHZ:
094d05dc
S		 628 switch(channel_type) {
629 case NL80211_CHAN_NO_HT:
630 case NL80211_CHAN_HT20:
f078f209 631 chanmode = CHANNEL_G_HT20;
094d05dc
S		 632 break;
633 case NL80211_CHAN_HT40PLUS:
f078f209 634 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40MINUS:
f078f209 637 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 638 break;
639 }
f078f209
LR		 640 break;
641 case IEEE80211_BAND_5GHZ:
094d05dc
S		 642 switch(channel_type) {
643 case NL80211_CHAN_NO_HT:
644 case NL80211_CHAN_HT20:
f078f209 645 chanmode = CHANNEL_A_HT20;
094d05dc
S		 646 break;
647 case NL80211_CHAN_HT40PLUS:
f078f209 648 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40MINUS:
f078f209 651 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 652 break;
653 }
f078f209
LR		 654 break;
655 default:
656 break;
657 }
658
659 return chanmode;
660}
661
6ace2891 662static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 663 struct ath9k_keyval *hk, const u8 *addr,
664 bool authenticator)
f078f209 665{
6ace2891
JM		 666 const u8 *key_rxmic;
667 const u8 *key_txmic;
f078f209 668
6ace2891
JM		 669 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
670 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 671
672 if (addr == NULL) {
d216aaa6
JM		 673 /*
674 * Group key installation - only two key cache entries are used
675 * regardless of splitmic capability since group key is only
676 * used either for TX or RX.
677 */
3f53dd64
JM		 678 if (authenticator) {
679 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
680 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
681 } else {
682 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
684 }
d216aaa6 685 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 686 }
17d7904d 687 if (!sc->splitmic) {
d216aaa6 688 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 689 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
690 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 691 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 692 }
d216aaa6
JM		 693
694 /* Separate key cache entries for TX and RX */
695
696 /* TX key goes at first index, RX key at +32. */
f078f209 697 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 698 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
699 /* TX MIC entry failed. No need to proceed further */
d8baa939 700 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 701 "Setting TX MIC Key Failed\n");
f078f209
LR		 702 return 0;
703 }
704
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 /* XXX delete tx key on failure? */
d216aaa6 707 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 708}
709
710static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
711{
712 int i;
713
17d7904d
S		 714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
715 if (test_bit(i, sc->keymap) ||
716 test_bit(i + 64, sc->keymap))
6ace2891 717 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 718 if (sc->splitmic &&
719 (test_bit(i + 32, sc->keymap) ||
720 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 721 continue; /* At least one part of TKIP key allocated */
722
723 /* Found a free slot for a TKIP key */
724 return i;
725 }
726 return -1;
727}
728
729static int ath_reserve_key_cache_slot(struct ath_softc *sc)
730{
731 int i;
732
733 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 734 if (sc->splitmic) {
735 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
736 if (!test_bit(i, sc->keymap) &&
737 (test_bit(i + 32, sc->keymap) ||
738 test_bit(i + 64, sc->keymap) ||
739 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 740 return i;
17d7904d
S		 741 if (!test_bit(i + 32, sc->keymap) &&
742 (test_bit(i, sc->keymap) ||
743 test_bit(i + 64, sc->keymap) ||
744 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 745 return i + 32;
17d7904d
S		 746 if (!test_bit(i + 64, sc->keymap) &&
747 (test_bit(i , sc->keymap) ||
748 test_bit(i + 32, sc->keymap) ||
749 test_bit(i + 64 + 32, sc->keymap)))
ea612132 750 return i + 64;
17d7904d
S		 751 if (!test_bit(i + 64 + 32, sc->keymap) &&
752 (test_bit(i, sc->keymap) ||
753 test_bit(i + 32, sc->keymap) ||
754 test_bit(i + 64, sc->keymap)))
ea612132 755 return i + 64 + 32;
6ace2891
JM		 756 }
757 } else {
17d7904d
S		 758 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
759 if (!test_bit(i, sc->keymap) &&
760 test_bit(i + 64, sc->keymap))
6ace2891 761 return i;
17d7904d
S		 762 if (test_bit(i, sc->keymap) &&
763 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 764 return i + 64;
765 }
766 }
767
768 /* No partially used TKIP slots, pick any available slot */
17d7904d 769 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 770 /* Do not allow slots that could be needed for TKIP group keys
771 * to be used. This limitation could be removed if we know that
772 * TKIP will not be used. */
773 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
774 continue;
17d7904d 775 if (sc->splitmic) {
be2864cf
JM		 776 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
777 continue;
778 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
779 continue;
780 }
781
17d7904d 782 if (!test_bit(i, sc->keymap))
6ace2891
JM		 783 return i; /* Found a free slot for a key */
784 }
785
786 /* No free slot found */
787 return -1;
f078f209
LR		 788}
789
790static int ath_key_config(struct ath_softc *sc,
3f53dd64 791 struct ieee80211_vif *vif,
dc822b5d 792 struct ieee80211_sta *sta,
f078f209
LR		 793 struct ieee80211_key_conf *key)
794{
f078f209
LR		 795 struct ath9k_keyval hk;
796 const u8 *mac = NULL;
797 int ret = 0;
6ace2891 798 int idx;
f078f209
LR		 799
800 memset(&hk, 0, sizeof(hk));
801
802 switch (key->alg) {
803 case ALG_WEP:
804 hk.kv_type = ATH9K_CIPHER_WEP;
805 break;
806 case ALG_TKIP:
807 hk.kv_type = ATH9K_CIPHER_TKIP;
808 break;
809 case ALG_CCMP:
810 hk.kv_type = ATH9K_CIPHER_AES_CCM;
811 break;
812 default:
ca470b29 813 return -EOPNOTSUPP;
f078f209
LR		 814 }
815
6ace2891 816 hk.kv_len = key->keylen;
f078f209
LR		 817 memcpy(hk.kv_val, key->key, key->keylen);
818
6ace2891
JM		 819 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
820 /* For now, use the default keys for broadcast keys. This may
821 * need to change with virtual interfaces. */
822 idx = key->keyidx;
823 } else if (key->keyidx) {
dc822b5d
JB		 824 if (WARN_ON(!sta))
825 return -EOPNOTSUPP;
826 mac = sta->addr;
827
6ace2891
JM		 828 if (vif->type != NL80211_IFTYPE_AP) {
829 /* Only keyidx 0 should be used with unicast key, but
830 * allow this for client mode for now. */
831 idx = key->keyidx;
832 } else
833 return -EIO;
f078f209 834 } else {
dc822b5d
JB		 835 if (WARN_ON(!sta))
836 return -EOPNOTSUPP;
837 mac = sta->addr;
838
6ace2891
JM		 839 if (key->alg == ALG_TKIP)
840 idx = ath_reserve_key_cache_slot_tkip(sc);
841 else
842 idx = ath_reserve_key_cache_slot(sc);
843 if (idx < 0)
ca470b29 844 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 845 }
846
847 if (key->alg == ALG_TKIP)
3f53dd64
JM		 848 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
849 vif->type == NL80211_IFTYPE_AP);
f078f209 850 else
d216aaa6 851 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 852
853 if (!ret)
854 return -EIO;
855
17d7904d 856 set_bit(idx, sc->keymap);
6ace2891 857 if (key->alg == ALG_TKIP) {
17d7904d
S		 858 set_bit(idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 set_bit(idx + 32, sc->keymap);
861 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 862 }
863 }
864
865 return idx;
f078f209
LR		 866}
867
868static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
869{
6ace2891
JM		 870 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
871 if (key->hw_key_idx < IEEE80211_WEP_NKID)
872 return;
873
17d7904d 874 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 875 if (key->alg != ALG_TKIP)
876 return;
f078f209 877
17d7904d
S		 878 clear_bit(key->hw_key_idx + 64, sc->keymap);
879 if (sc->splitmic) {
880 clear_bit(key->hw_key_idx + 32, sc->keymap);
881 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 882 }
f078f209
LR		 883}
884
eb2599ca
S		 885static void setup_ht_cap(struct ath_softc *sc,
886 struct ieee80211_sta_ht_cap *ht_info)
f078f209 887{
60653678
S		 888#define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
889#define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
f078f209 890
d9fe60de
JB		 891 ht_info->ht_supported = true;
892 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
893 IEEE80211_HT_CAP_SM_PS |
894 IEEE80211_HT_CAP_SGI_40 |
895 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 896
60653678
S		 897 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
898 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
eb2599ca 899
d9fe60de
JB		 900 /* set up supported mcs set */
901 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
eb2599ca 902
17d7904d 903 switch(sc->rx_chainmask) {
eb2599ca
S		 904 case 1:
905 ht_info->mcs.rx_mask[0] = 0xff;
906 break;
3c457265 907 case 3:
eb2599ca
S		 908 case 5:
909 case 7:
910 default:
911 ht_info->mcs.rx_mask[0] = 0xff;
912 ht_info->mcs.rx_mask[1] = 0xff;
913 break;
914 }
915
d9fe60de 916 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 917}
918
8feceb67 919static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 920 struct ieee80211_vif *vif,
8feceb67 921 struct ieee80211_bss_conf *bss_conf)
f078f209 922{
f078f209 923
8feceb67 924 if (bss_conf->assoc) {
094d05dc 925 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 926 bss_conf->aid, sc->curbssid);
f078f209 927
8feceb67 928 /* New association, store aid */
2664f201
SB		 929 sc->curaid = bss_conf->aid;
930 ath9k_hw_write_associd(sc);
931
932 /*
933 * Request a re-configuration of Beacon related timers
934 * on the receipt of the first Beacon frame (i.e.,
935 * after time sync with the AP).
936 */
937 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 938
8feceb67 939 /* Configure the beacon */
2c3db3d5 940 ath_beacon_config(sc, vif);
f078f209 941
8feceb67 942 /* Reset rssi stats */
17d7904d
S		 943 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
944 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
945 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
946 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 947
415f738e 948 ath_start_ani(sc);
8feceb67 949 } else {
1ffb0610 950 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 951 sc->curaid = 0;
f38faa31
SB		 952 /* Stop ANI */
953 del_timer_sync(&sc->ani.timer);
f078f209 954 }
8feceb67 955}
f078f209 956
8feceb67
VT		 957/********************************/
958/* LED functions */
959/********************************/
f078f209 960
f2bffa7e
VT		 961static void ath_led_blink_work(struct work_struct *work)
962{
963 struct ath_softc *sc = container_of(work, struct ath_softc,
964 ath_led_blink_work.work);
965
966 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
967 return;
85067c06
VT		 968
969 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
970 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
971 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
972 else
973 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
974 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 975
976 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
977 (sc->sc_flags & SC_OP_LED_ON) ?
978 msecs_to_jiffies(sc->led_off_duration) :
979 msecs_to_jiffies(sc->led_on_duration));
980
85067c06
VT		 981 sc->led_on_duration = sc->led_on_cnt ?
982 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
983 ATH_LED_ON_DURATION_IDLE;
984 sc->led_off_duration = sc->led_off_cnt ?
985 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
986 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 987 sc->led_on_cnt = sc->led_off_cnt = 0;
988 if (sc->sc_flags & SC_OP_LED_ON)
989 sc->sc_flags &= ~SC_OP_LED_ON;
990 else
991 sc->sc_flags |= SC_OP_LED_ON;
992}
993
8feceb67
VT		 994static void ath_led_brightness(struct led_classdev *led_cdev,
995 enum led_brightness brightness)
996{
997 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
998 struct ath_softc *sc = led->sc;
f078f209 999
8feceb67
VT		 1000 switch (brightness) {
1001 case LED_OFF:
1002 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1003 led->led_type == ATH_LED_RADIO) {
1004 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1005 (led->led_type == ATH_LED_RADIO));
8feceb67 1006 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1007 if (led->led_type == ATH_LED_RADIO)
1008 sc->sc_flags &= ~SC_OP_LED_ON;
1009 } else {
1010 sc->led_off_cnt++;
1011 }
8feceb67
VT		 1012 break;
1013 case LED_FULL:
f2bffa7e 1014 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1015 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1016 queue_delayed_work(sc->hw->workqueue,
1017 &sc->ath_led_blink_work, 0);
1018 } else if (led->led_type == ATH_LED_RADIO) {
1019 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1020 sc->sc_flags |= SC_OP_LED_ON;
1021 } else {
1022 sc->led_on_cnt++;
1023 }
8feceb67
VT		 1024 break;
1025 default:
1026 break;
f078f209 1027 }
8feceb67 1028}
f078f209 1029
8feceb67
VT		 1030static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1031 char *trigger)
1032{
1033 int ret;
f078f209 1034
8feceb67
VT		 1035 led->sc = sc;
1036 led->led_cdev.name = led->name;
1037 led->led_cdev.default_trigger = trigger;
1038 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1039
8feceb67
VT		 1040 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1041 if (ret)
1042 DPRINTF(sc, ATH_DBG_FATAL,
1043 "Failed to register led:%s", led->name);
1044 else
1045 led->registered = 1;
1046 return ret;
1047}
f078f209 1048
8feceb67
VT		 1049static void ath_unregister_led(struct ath_led *led)
1050{
1051 if (led->registered) {
1052 led_classdev_unregister(&led->led_cdev);
1053 led->registered = 0;
f078f209 1054 }
f078f209
LR		 1055}
1056
8feceb67 1057static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1058{
f2bffa7e 1059 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1060 ath_unregister_led(&sc->assoc_led);
1061 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1062 ath_unregister_led(&sc->tx_led);
1063 ath_unregister_led(&sc->rx_led);
1064 ath_unregister_led(&sc->radio_led);
1065 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1066}
f078f209 1067
8feceb67
VT		 1068static void ath_init_leds(struct ath_softc *sc)
1069{
1070 char *trigger;
1071 int ret;
f078f209 1072
8feceb67
VT		 1073 /* Configure gpio 1 for output */
1074 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1075 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1076 /* LED off, active low */
1077 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1078
f2bffa7e
VT		 1079 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1080
8feceb67
VT		 1081 trigger = ieee80211_get_radio_led_name(sc->hw);
1082 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1083 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1084 ret = ath_register_led(sc, &sc->radio_led, trigger);
1085 sc->radio_led.led_type = ATH_LED_RADIO;
1086 if (ret)
1087 goto fail;
7dcfdcd9 1088
8feceb67
VT		 1089 trigger = ieee80211_get_assoc_led_name(sc->hw);
1090 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1091 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1092 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1093 sc->assoc_led.led_type = ATH_LED_ASSOC;
1094 if (ret)
1095 goto fail;
f078f209 1096
8feceb67
VT		 1097 trigger = ieee80211_get_tx_led_name(sc->hw);
1098 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1099 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1100 ret = ath_register_led(sc, &sc->tx_led, trigger);
1101 sc->tx_led.led_type = ATH_LED_TX;
1102 if (ret)
1103 goto fail;
f078f209 1104
8feceb67
VT		 1105 trigger = ieee80211_get_rx_led_name(sc->hw);
1106 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1107 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1108 ret = ath_register_led(sc, &sc->rx_led, trigger);
1109 sc->rx_led.led_type = ATH_LED_RX;
1110 if (ret)
1111 goto fail;
f078f209 1112
8feceb67
VT		 1113 return;
1114
1115fail:
1116 ath_deinit_leds(sc);
f078f209
LR		 1117}
1118
7ec3e514 1119void ath_radio_enable(struct ath_softc *sc)
500c064d 1120{
cbe61d8a 1121 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1122 struct ieee80211_channel *channel = sc->hw->conf.channel;
1123 int r;
500c064d 1124
3cbb5dd7 1125 ath9k_ps_wakeup(sc);
d2f5b3a6 1126 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1127
159cd468
VT		 1128 if (!ah->curchan)
1129 ah->curchan = ath_get_curchannel(sc, sc->hw);
1130
d2f5b3a6 1131 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1132 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1133 if (r) {
500c064d 1134 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1135 "Unable to reset channel %u (%uMhz) ",
6b45784f 1136 "reset status %d\n",
ae8d2858 1137 channel->center_freq, r);
500c064d
VT		 1138 }
1139 spin_unlock_bh(&sc->sc_resetlock);
1140
1141 ath_update_txpow(sc);
1142 if (ath_startrecv(sc) != 0) {
1143 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1144 "Unable to restart recv logic\n");
500c064d
VT		 1145 return;
1146 }
1147
1148 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1149 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1150
1151 /* Re-Enable interrupts */
17d7904d 1152 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1153
1154 /* Enable LED */
1155 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1156 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1157 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1158
1159 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1160 ath9k_ps_restore(sc);
500c064d
VT		 1161}
1162
7ec3e514 1163void ath_radio_disable(struct ath_softc *sc)
500c064d 1164{
cbe61d8a 1165 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1166 struct ieee80211_channel *channel = sc->hw->conf.channel;
1167 int r;
500c064d 1168
3cbb5dd7 1169 ath9k_ps_wakeup(sc);
500c064d
VT		 1170 ieee80211_stop_queues(sc->hw);
1171
1172 /* Disable LED */
1173 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1174 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1175
1176 /* Disable interrupts */
1177 ath9k_hw_set_interrupts(ah, 0);
1178
043a0405 1179 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1180 ath_stoprecv(sc); /* turn off frame recv */
1181 ath_flushrecv(sc); /* flush recv queue */
1182
159cd468
VT		 1183 if (!ah->curchan)
1184 ah->curchan = ath_get_curchannel(sc, sc->hw);
1185
500c064d 1186 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1187 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1188 if (r) {
500c064d 1189 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1190 "Unable to reset channel %u (%uMhz) "
6b45784f 1191 "reset status %d\n",
ae8d2858 1192 channel->center_freq, r);
500c064d
VT		 1193 }
1194 spin_unlock_bh(&sc->sc_resetlock);
1195
1196 ath9k_hw_phy_disable(ah);
d2f5b3a6 1197 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1198 ath9k_ps_restore(sc);
38ab422e 1199 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1200}
1201
5077fd35
GJ		 1202/*******************/
1203/* Rfkill */
1204/*******************/
1205
500c064d
VT		 1206static bool ath_is_rfkill_set(struct ath_softc *sc)
1207{
cbe61d8a 1208 struct ath_hw *ah = sc->sc_ah;
500c064d 1209
2660b81a
S		 1210 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1211 ah->rfkill_polarity;
500c064d
VT		 1212}
1213
3b319aae 1214static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1215{
3b319aae
JB		 1216 struct ath_wiphy *aphy = hw->priv;
1217 struct ath_softc *sc = aphy->sc;
19d337df 1218 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1219
3b319aae
JB		 1220 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1221
1222 if (blocked)
19d337df
JB		 1223 ath_radio_disable(sc);
1224 else
1225 ath_radio_enable(sc);
500c064d
VT		 1226}
1227
3b319aae 1228static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1229{
3b319aae 1230 struct ath_hw *ah = sc->sc_ah;
9c84b797 1231
3b319aae
JB		 1232 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1233 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1234}
500c064d 1235
6baff7f9 1236void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1237{
1238 ath_detach(sc);
1239 free_irq(sc->irq, sc);
1240 ath_bus_cleanup(sc);
c52f33d0 1241 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1242 ieee80211_free_hw(sc->hw);
1243}
1244
6baff7f9 1245void ath_detach(struct ath_softc *sc)
f078f209 1246{
8feceb67 1247 struct ieee80211_hw *hw = sc->hw;
9c84b797 1248 int i = 0;
f078f209 1249
3cbb5dd7
VN		 1250 ath9k_ps_wakeup(sc);
1251
04bd4638 1252 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1253
3fcdfb4b 1254 ath_deinit_leds(sc);
0e2dedf9 1255 cancel_work_sync(&sc->chan_work);
f98c3bd2 1256 cancel_delayed_work_sync(&sc->wiphy_work);
3fcdfb4b 1257
c52f33d0
JM		 1258 for (i = 0; i < sc->num_sec_wiphy; i++) {
1259 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1260 if (aphy == NULL)
1261 continue;
1262 sc->sec_wiphy[i] = NULL;
1263 ieee80211_unregister_hw(aphy->hw);
1264 ieee80211_free_hw(aphy->hw);
1265 }
3fcdfb4b 1266 ieee80211_unregister_hw(hw);
8feceb67
VT		 1267 ath_rx_cleanup(sc);
1268 ath_tx_cleanup(sc);
f078f209 1269
9c84b797
S		 1270 tasklet_kill(&sc->intr_tq);
1271 tasklet_kill(&sc->bcon_tasklet);
f078f209 1272
9c84b797
S		 1273 if (!(sc->sc_flags & SC_OP_INVALID))
1274 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1275
9c84b797
S		 1276 /* cleanup tx queues */
1277 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1278 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1279 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1280
1281 ath9k_hw_detach(sc->sc_ah);
826d2680 1282 ath9k_exit_debug(sc);
3cbb5dd7 1283 ath9k_ps_restore(sc);
f078f209
LR		 1284}
1285
e3bb249b
BC		 1286static int ath9k_reg_notifier(struct wiphy *wiphy,
1287 struct regulatory_request *request)
1288{
1289 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1290 struct ath_wiphy *aphy = hw->priv;
1291 struct ath_softc *sc = aphy->sc;
1292 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1293
1294 return ath_reg_notifier_apply(wiphy, request, reg);
1295}
1296
ff37e337
S		 1297static int ath_init(u16 devid, struct ath_softc *sc)
1298{
cbe61d8a 1299 struct ath_hw *ah = NULL;
ff37e337
S		 1300 int status;
1301 int error = 0, i;
1302 int csz = 0;
1303
1304 /* XXX: hardware will not be ready until ath_open() being called */
1305 sc->sc_flags |= SC_OP_INVALID;
88b126af 1306
826d2680
S		 1307 if (ath9k_init_debug(sc) < 0)
1308 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1309
c52f33d0 1310 spin_lock_init(&sc->wiphy_lock);
ff37e337 1311 spin_lock_init(&sc->sc_resetlock);
6158425b 1312 spin_lock_init(&sc->sc_serial_rw);
aa33de09 1313 mutex_init(&sc->mutex);
ff37e337 1314 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1315 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1316 (unsigned long)sc);
1317
1318 /*
1319 * Cache line size is used to size and align various
1320 * structures used to communicate with the hardware.
1321 */
88d15707 1322 ath_read_cachesize(sc, &csz);
ff37e337 1323 /* XXX assert csz is non-zero */
17d7904d 1324 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1325
cbe61d8a 1326 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1327 if (ah == NULL) {
1328 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1329 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1330 error = -ENXIO;
1331 goto bad;
1332 }
1333 sc->sc_ah = ah;
1334
1335 /* Get the hardware key cache size. */
2660b81a 1336 sc->keymax = ah->caps.keycache_size;
17d7904d 1337 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1338 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1339 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1340 ATH_KEYMAX, sc->keymax);
1341 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1342 }
1343
1344 /*
1345 * Reset the key cache since some parts do not
1346 * reset the contents on initial power up.
1347 */
17d7904d 1348 for (i = 0; i < sc->keymax; i++)
ff37e337 1349 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1350
85efc86e 1351 if (error)
ff37e337
S		 1352 goto bad;
1353
1354 /* default to MONITOR mode */
2660b81a 1355 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1356
ff37e337
S		 1357 /* Setup rate tables */
1358
1359 ath_rate_attach(sc);
1360 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1361 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1362
1363 /*
1364 * Allocate hardware transmit queues: one queue for
1365 * beacon frames and one data queue for each QoS
1366 * priority. Note that the hal handles reseting
1367 * these queues at the needed time.
1368 */
b77f483f
S		 1369 sc->beacon.beaconq = ath_beaconq_setup(ah);
1370 if (sc->beacon.beaconq == -1) {
ff37e337 1371 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1372 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1373 error = -EIO;
1374 goto bad2;
1375 }
b77f483f
S		 1376 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1377 if (sc->beacon.cabq == NULL) {
ff37e337 1378 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1379 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1380 error = -EIO;
1381 goto bad2;
1382 }
1383
17d7904d 1384 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1385 ath_cabq_update(sc);
1386
b77f483f
S		 1387 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1388 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1389
1390 /* Setup data queues */
1391 /* NB: ensure BK queue is the lowest priority h/w queue */
1392 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1393 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1394 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1395 error = -EIO;
1396 goto bad2;
1397 }
1398
1399 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1400 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1401 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1402 error = -EIO;
1403 goto bad2;
1404 }
1405 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1406 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1407 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1408 error = -EIO;
1409 goto bad2;
1410 }
1411 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1412 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1413 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1414 error = -EIO;
1415 goto bad2;
1416 }
1417
1418 /* Initializes the noise floor to a reasonable default value.
1419 * Later on this will be updated during ANI processing. */
1420
17d7904d
S		 1421 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1422 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1423
1424 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1425 ATH9K_CIPHER_TKIP, NULL)) {
1426 /*
1427 * Whether we should enable h/w TKIP MIC.
1428 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1429 * report WMM capable, so it's always safe to turn on
1430 * TKIP MIC in this case.
1431 */
1432 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1433 0, 1, NULL);
1434 }
1435
1436 /*
1437 * Check whether the separate key cache entries
1438 * are required to handle both tx+rx MIC keys.
1439 * With split mic keys the number of stations is limited
1440 * to 27 otherwise 59.
1441 */
1442 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1443 ATH9K_CIPHER_TKIP, NULL)
1444 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1445 ATH9K_CIPHER_MIC, NULL)
1446 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1447 0, NULL))
17d7904d 1448 sc->splitmic = 1;
ff37e337
S		 1449
1450 /* turn on mcast key search if possible */
1451 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1452 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1453 1, NULL);
1454
17d7904d 1455 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1456
1457 /* 11n Capabilities */
2660b81a 1458 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1459 sc->sc_flags |= SC_OP_TXAGGR;
1460 sc->sc_flags |= SC_OP_RXAGGR;
1461 }
1462
2660b81a
S		 1463 sc->tx_chainmask = ah->caps.tx_chainmask;
1464 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1465
1466 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1467 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1468
8ca21f01 1469 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1470 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1471
b77f483f 1472 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1473
1474 /* initialize beacon slots */
c52f33d0 1475 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1476 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1477 sc->beacon.bslot_aphy[i] = NULL;
1478 }
ff37e337 1479
ff37e337
S		 1480 /* setup channels and rates */
1481
5f8e077c 1482 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1483 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1484 sc->rates[IEEE80211_BAND_2GHZ];
1485 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1486 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1487 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1488
2660b81a 1489 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1490 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1491 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1492 sc->rates[IEEE80211_BAND_5GHZ];
1493 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1494 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1495 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1496 }
1497
2660b81a 1498 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1499 ath9k_hw_btcoex_enable(sc->sc_ah);
1500
ff37e337
S		 1501 return 0;
1502bad2:
1503 /* cleanup tx queues */
1504 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1505 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1506 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1507bad:
1508 if (ah)
1509 ath9k_hw_detach(ah);
40b130a9 1510 ath9k_exit_debug(sc);
ff37e337
S		 1511
1512 return error;
1513}
1514
c52f33d0 1515void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1516{
9c84b797
S		 1517 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1518 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1519 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1520 IEEE80211_HW_AMPDU_AGGREGATION |
1521 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1522 IEEE80211_HW_PS_NULLFUNC_STACK |
1523 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1524
b3bd89ce 1525 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1526 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1527
9c84b797
S		 1528 hw->wiphy->interface_modes =
1529 BIT(NL80211_IFTYPE_AP) |
1530 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1531 BIT(NL80211_IFTYPE_ADHOC) |
1532 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1533
8feceb67 1534 hw->queues = 4;
e63835b0 1535 hw->max_rates = 4;
171387ef 1536 hw->channel_change_time = 5000;
465ca84d 1537 hw->max_listen_interval = 10;
e63835b0 1538 hw->max_rate_tries = ATH_11N_TXMAXTRY;
528f0c6b 1539 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1540 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1541
8feceb67 1542 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1543
c52f33d0
JM		 1544 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1545 &sc->sbands[IEEE80211_BAND_2GHZ];
1546 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1547 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1548 &sc->sbands[IEEE80211_BAND_5GHZ];
1549}
1550
1551int ath_attach(u16 devid, struct ath_softc *sc)
1552{
1553 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1554 int error = 0, i;
3a702e49 1555 struct ath_regulatory *reg;
c52f33d0
JM		 1556
1557 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1558
1559 error = ath_init(devid, sc);
1560 if (error != 0)
1561 return error;
1562
1563 /* get mac address from hardware and set in mac80211 */
1564
1565 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1566
1567 ath_set_hw_capab(sc, hw);
1568
c26c2e57
LR		 1569 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1570 ath9k_reg_notifier);
1571 if (error)
1572 return error;
1573
1574 reg = &sc->sc_ah->regulatory;
1575
2660b81a 1576 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1577 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1578 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1579 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1580 }
1581
db93e7b5
SB		 1582 /* initialize tx/rx engine */
1583 error = ath_tx_init(sc, ATH_TXBUF);
1584 if (error != 0)
40b130a9 1585 goto error_attach;
8feceb67 1586
db93e7b5
SB		 1587 error = ath_rx_init(sc, ATH_RXBUF);
1588 if (error != 0)
40b130a9 1589 goto error_attach;
8feceb67 1590
0e2dedf9 1591 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1592 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1593 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1594
db93e7b5 1595 error = ieee80211_register_hw(hw);
8feceb67 1596
3a702e49 1597 if (!ath_is_world_regd(reg)) {
c02cf373 1598 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1599 if (error)
1600 goto error_attach;
1601 }
5f8e077c 1602
db93e7b5
SB		 1603 /* Initialize LED control */
1604 ath_init_leds(sc);
8feceb67 1605
3b319aae 1606 ath_start_rfkill_poll(sc);
5f8e077c 1607
8feceb67 1608 return 0;
40b130a9
VT		 1609
1610error_attach:
1611 /* cleanup tx queues */
1612 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1613 if (ATH_TXQ_SETUP(sc, i))
1614 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1615
1616 ath9k_hw_detach(sc->sc_ah);
1617 ath9k_exit_debug(sc);
1618
8feceb67 1619 return error;
f078f209
LR		 1620}
1621
ff37e337
S		 1622int ath_reset(struct ath_softc *sc, bool retry_tx)
1623{
cbe61d8a 1624 struct ath_hw *ah = sc->sc_ah;
030bb495 1625 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1626 int r;
ff37e337
S		 1627
1628 ath9k_hw_set_interrupts(ah, 0);
043a0405 1629 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1630 ath_stoprecv(sc);
1631 ath_flushrecv(sc);
1632
1633 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1634 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1635 if (r)
ff37e337 1636 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1637 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1638 spin_unlock_bh(&sc->sc_resetlock);
1639
1640 if (ath_startrecv(sc) != 0)
04bd4638 1641 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1642
1643 /*
1644 * We may be doing a reset in response to a request
1645 * that changes the channel so update any state that
1646 * might change as a result.
1647 */
ce111bad 1648 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1649
1650 ath_update_txpow(sc);
1651
1652 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1653 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1654
17d7904d 1655 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1656
1657 if (retry_tx) {
1658 int i;
1659 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1660 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1661 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1662 ath_txq_schedule(sc, &sc->tx.txq[i]);
1663 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1664 }
1665 }
1666 }
1667
ae8d2858 1668 return r;
ff37e337
S		 1669}
1670
1671/*
1672 * This function will allocate both the DMA descriptor structure, and the
1673 * buffers it contains. These are used to contain the descriptors used
1674 * by the system.
1675*/
1676int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1677 struct list_head *head, const char *name,
1678 int nbuf, int ndesc)
1679{
1680#define DS2PHYS(_dd, _ds) \
1681 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1682#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1683#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1684
1685 struct ath_desc *ds;
1686 struct ath_buf *bf;
1687 int i, bsize, error;
1688
04bd4638
S		 1689 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1690 name, nbuf, ndesc);
ff37e337 1691
b03a9db9 1692 INIT_LIST_HEAD(head);
ff37e337
S		 1693 /* ath_desc must be a multiple of DWORDs */
1694 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1695 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1696 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1697 error = -ENOMEM;
1698 goto fail;
1699 }
1700
ff37e337
S		 1701 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1702
1703 /*
1704 * Need additional DMA memory because we can't use
1705 * descriptors that cross the 4K page boundary. Assume
1706 * one skipped descriptor per 4K page.
1707 */
2660b81a 1708 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1709 u32 ndesc_skipped =
1710 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1711 u32 dma_len;
1712
1713 while (ndesc_skipped) {
1714 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1715 dd->dd_desc_len += dma_len;
1716
1717 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1718 };
1719 }
1720
1721 /* allocate descriptors */
7da3c55c 1722 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1723 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1724 if (dd->dd_desc == NULL) {
1725 error = -ENOMEM;
1726 goto fail;
1727 }
1728 ds = dd->dd_desc;
04bd4638 1729 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1730 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1731 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1732
1733 /* allocate buffers */
1734 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1735 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1736 if (bf == NULL) {
1737 error = -ENOMEM;
1738 goto fail2;
1739 }
ff37e337
S		 1740 dd->dd_bufptr = bf;
1741
ff37e337
S		 1742 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1743 bf->bf_desc = ds;
1744 bf->bf_daddr = DS2PHYS(dd, ds);
1745
2660b81a 1746 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1747 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1748 /*
1749 * Skip descriptor addresses which can cause 4KB
1750 * boundary crossing (addr + length) with a 32 dword
1751 * descriptor fetch.
1752 */
1753 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1754 ASSERT((caddr_t) bf->bf_desc <
1755 ((caddr_t) dd->dd_desc +
1756 dd->dd_desc_len));
1757
1758 ds += ndesc;
1759 bf->bf_desc = ds;
1760 bf->bf_daddr = DS2PHYS(dd, ds);
1761 }
1762 }
1763 list_add_tail(&bf->list, head);
1764 }
1765 return 0;
1766fail2:
7da3c55c
GJ		 1767 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1768 dd->dd_desc_paddr);
ff37e337
S		 1769fail:
1770 memset(dd, 0, sizeof(*dd));
1771 return error;
1772#undef ATH_DESC_4KB_BOUND_CHECK
1773#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1774#undef DS2PHYS
1775}
1776
1777void ath_descdma_cleanup(struct ath_softc *sc,
1778 struct ath_descdma *dd,
1779 struct list_head *head)
1780{
7da3c55c
GJ		 1781 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1782 dd->dd_desc_paddr);
ff37e337
S		 1783
1784 INIT_LIST_HEAD(head);
1785 kfree(dd->dd_bufptr);
1786 memset(dd, 0, sizeof(*dd));
1787}
1788
1789int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1790{
1791 int qnum;
1792
1793 switch (queue) {
1794 case 0:
b77f483f 1795 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1796 break;
1797 case 1:
b77f483f 1798 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1799 break;
1800 case 2:
b77f483f 1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1802 break;
1803 case 3:
b77f483f 1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1805 break;
1806 default:
b77f483f 1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1808 break;
1809 }
1810
1811 return qnum;
1812}
1813
1814int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1815{
1816 int qnum;
1817
1818 switch (queue) {
1819 case ATH9K_WME_AC_VO:
1820 qnum = 0;
1821 break;
1822 case ATH9K_WME_AC_VI:
1823 qnum = 1;
1824 break;
1825 case ATH9K_WME_AC_BE:
1826 qnum = 2;
1827 break;
1828 case ATH9K_WME_AC_BK:
1829 qnum = 3;
1830 break;
1831 default:
1832 qnum = -1;
1833 break;
1834 }
1835
1836 return qnum;
1837}
1838
5f8e077c
LR		 1839/* XXX: Remove me once we don't depend on ath9k_channel for all
1840 * this redundant data */
0e2dedf9
JM		 1841void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1842 struct ath9k_channel *ichan)
5f8e077c 1843{
5f8e077c
LR		 1844 struct ieee80211_channel *chan = hw->conf.channel;
1845 struct ieee80211_conf *conf = &hw->conf;
1846
1847 ichan->channel = chan->center_freq;
1848 ichan->chan = chan;
1849
1850 if (chan->band == IEEE80211_BAND_2GHZ) {
1851 ichan->chanmode = CHANNEL_G;
1852 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1853 } else {
1854 ichan->chanmode = CHANNEL_A;
1855 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1856 }
1857
1858 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1859
1860 if (conf_is_ht(conf)) {
1861 if (conf_is_ht40(conf))
1862 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1863
1864 ichan->chanmode = ath_get_extchanmode(sc, chan,
1865 conf->channel_type);
1866 }
1867}
1868
ff37e337
S		 1869/**********************/
1870/* mac80211 callbacks */
1871/**********************/
1872
8feceb67 1873static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1874{
bce048d7
JM		 1875 struct ath_wiphy *aphy = hw->priv;
1876 struct ath_softc *sc = aphy->sc;
8feceb67 1877 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1878 struct ath9k_channel *init_channel;
82880a7c 1879 int r;
f078f209 1880
04bd4638
S		 1881 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1882 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1883
141b38b6
S		 1884 mutex_lock(&sc->mutex);
1885
9580a222
JM		 1886 if (ath9k_wiphy_started(sc)) {
1887 if (sc->chan_idx == curchan->hw_value) {
1888 /*
1889 * Already on the operational channel, the new wiphy
1890 * can be marked active.
1891 */
1892 aphy->state = ATH_WIPHY_ACTIVE;
1893 ieee80211_wake_queues(hw);
1894 } else {
1895 /*
1896 * Another wiphy is on another channel, start the new
1897 * wiphy in paused state.
1898 */
1899 aphy->state = ATH_WIPHY_PAUSED;
1900 ieee80211_stop_queues(hw);
1901 }
1902 mutex_unlock(&sc->mutex);
1903 return 0;
1904 }
1905 aphy->state = ATH_WIPHY_ACTIVE;
1906
8feceb67 1907 /* setup initial channel */
f078f209 1908
82880a7c 1909 sc->chan_idx = curchan->hw_value;
f078f209 1910
82880a7c 1911 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1912
1913 /* Reset SERDES registers */
1914 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1915
1916 /*
1917 * The basic interface to setting the hardware in a good
1918 * state is ``reset''. On return the hardware is known to
1919 * be powered up and with interrupts disabled. This must
1920 * be followed by initialization of the appropriate bits
1921 * and then setup of the interrupt mask.
1922 */
1923 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1924 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1925 if (r) {
ff37e337 1926 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1927 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1928 "(freq %u MHz)\n", r,
1929 curchan->center_freq);
ff37e337 1930 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1931 goto mutex_unlock;
ff37e337
S		 1932 }
1933 spin_unlock_bh(&sc->sc_resetlock);
1934
1935 /*
1936 * This is needed only to setup initial state
1937 * but it's best done after a reset.
1938 */
1939 ath_update_txpow(sc);
8feceb67 1940
ff37e337
S		 1941 /*
1942 * Setup the hardware after reset:
1943 * The receive engine is set going.
1944 * Frame transmit is handled entirely
1945 * in the frame output path; there's nothing to do
1946 * here except setup the interrupt mask.
1947 */
1948 if (ath_startrecv(sc) != 0) {
1ffb0610 1949 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1950 r = -EIO;
1951 goto mutex_unlock;
f078f209 1952 }
8feceb67 1953
ff37e337 1954 /* Setup our intr mask. */
17d7904d 1955 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1956 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1957 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1958
2660b81a 1959 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1960 sc->imask |= ATH9K_INT_GTT;
ff37e337 1961
2660b81a 1962 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1963 sc->imask |= ATH9K_INT_CST;
ff37e337 1964
ce111bad 1965 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1966
1967 sc->sc_flags &= ~SC_OP_INVALID;
1968
1969 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1970 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1971 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1972
bce048d7 1973 ieee80211_wake_queues(hw);
ff37e337 1974
141b38b6
S		 1975mutex_unlock:
1976 mutex_unlock(&sc->mutex);
1977
ae8d2858 1978 return r;
f078f209
LR		 1979}
1980
8feceb67
VT		 1981static int ath9k_tx(struct ieee80211_hw *hw,
1982 struct sk_buff *skb)
f078f209 1983{
528f0c6b 1984 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1985 struct ath_wiphy *aphy = hw->priv;
1986 struct ath_softc *sc = aphy->sc;
528f0c6b 1987 struct ath_tx_control txctl;
8feceb67 1988 int hdrlen, padsize;
528f0c6b 1989
8089cc47 1990 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 1991 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
1992 "%d\n", wiphy_name(hw->wiphy), aphy->state);
1993 goto exit;
1994 }
1995
dc8c4585
JM		 1996 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
1997 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1998 /*
1999 * mac80211 does not set PM field for normal data frames, so we
2000 * need to update that based on the current PS mode.
2001 */
2002 if (ieee80211_is_data(hdr->frame_control) &&
2003 !ieee80211_is_nullfunc(hdr->frame_control) &&
2004 !ieee80211_has_pm(hdr->frame_control)) {
2005 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2006 "while in PS mode\n");
2007 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2008 }
2009 }
2010
9a23f9ca
JM		 2011 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2012 /*
2013 * We are using PS-Poll and mac80211 can request TX while in
2014 * power save mode. Need to wake up hardware for the TX to be
2015 * completed and if needed, also for RX of buffered frames.
2016 */
2017 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2018 ath9k_ps_wakeup(sc);
2019 ath9k_hw_setrxabort(sc->sc_ah, 0);
2020 if (ieee80211_is_pspoll(hdr->frame_control)) {
2021 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2022 "buffered frame\n");
2023 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2024 } else {
2025 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2026 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2027 }
2028 /*
2029 * The actual restore operation will happen only after
2030 * the sc_flags bit is cleared. We are just dropping
2031 * the ps_usecount here.
2032 */
2033 ath9k_ps_restore(sc);
2034 }
2035
528f0c6b 2036 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2037
8feceb67
VT		 2038 /*
2039 * As a temporary workaround, assign seq# here; this will likely need
2040 * to be cleaned up to work better with Beacon transmission and virtual
2041 * BSSes.
2042 */
2043 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2044 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2045 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2046 sc->tx.seq_no += 0x10;
8feceb67 2047 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2048 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2049 }
f078f209 2050
8feceb67
VT		 2051 /* Add the padding after the header if this is not already done */
2052 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2053 if (hdrlen & 3) {
2054 padsize = hdrlen % 4;
2055 if (skb_headroom(skb) < padsize)
2056 return -1;
2057 skb_push(skb, padsize);
2058 memmove(skb->data, skb->data + padsize, hdrlen);
2059 }
2060
528f0c6b
S		 2061 /* Check if a tx queue is available */
2062
2063 txctl.txq = ath_test_get_txq(sc, skb);
2064 if (!txctl.txq)
2065 goto exit;
2066
04bd4638 2067 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2068
c52f33d0 2069 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2070 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2071 goto exit;
8feceb67
VT		 2072 }
2073
528f0c6b
S		 2074 return 0;
2075exit:
2076 dev_kfree_skb_any(skb);
8feceb67 2077 return 0;
f078f209
LR		 2078}
2079
8feceb67 2080static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2081{
bce048d7
JM		 2082 struct ath_wiphy *aphy = hw->priv;
2083 struct ath_softc *sc = aphy->sc;
f078f209 2084
9580a222
JM		 2085 aphy->state = ATH_WIPHY_INACTIVE;
2086
9c84b797 2087 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2088 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2089 return;
2090 }
8feceb67 2091
141b38b6 2092 mutex_lock(&sc->mutex);
ff37e337 2093
bce048d7 2094 ieee80211_stop_queues(hw);
ff37e337 2095
9580a222
JM		 2096 if (ath9k_wiphy_started(sc)) {
2097 mutex_unlock(&sc->mutex);
2098 return; /* another wiphy still in use */
2099 }
2100
ff37e337
S		 2101 /* make sure h/w will not generate any interrupt
2102 * before setting the invalid flag. */
2103 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2104
2105 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2106 ath_drain_all_txq(sc, false);
ff37e337
S		 2107 ath_stoprecv(sc);
2108 ath9k_hw_phy_disable(sc->sc_ah);
2109 } else
b77f483f 2110 sc->rx.rxlink = NULL;
ff37e337 2111
3b319aae 2112 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2113
ff37e337
S		 2114 /* disable HAL and put h/w to sleep */
2115 ath9k_hw_disable(sc->sc_ah);
2116 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2117
2118 sc->sc_flags |= SC_OP_INVALID;
500c064d 2119
141b38b6
S		 2120 mutex_unlock(&sc->mutex);
2121
04bd4638 2122 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2123}
2124
8feceb67
VT		 2125static int ath9k_add_interface(struct ieee80211_hw *hw,
2126 struct ieee80211_if_init_conf *conf)
f078f209 2127{
bce048d7
JM		 2128 struct ath_wiphy *aphy = hw->priv;
2129 struct ath_softc *sc = aphy->sc;
17d7904d 2130 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2131 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2132 int ret = 0;
8feceb67 2133
141b38b6
S		 2134 mutex_lock(&sc->mutex);
2135
8ca21f01
JM		 2136 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2137 sc->nvifs > 0) {
2138 ret = -ENOBUFS;
2139 goto out;
2140 }
2141
8feceb67 2142 switch (conf->type) {
05c914fe 2143 case NL80211_IFTYPE_STATION:
d97809db 2144 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2145 break;
05c914fe 2146 case NL80211_IFTYPE_ADHOC:
05c914fe 2147 case NL80211_IFTYPE_AP:
9cb5412b 2148 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2149 if (sc->nbcnvifs >= ATH_BCBUF) {
2150 ret = -ENOBUFS;
2151 goto out;
2152 }
9cb5412b 2153 ic_opmode = conf->type;
f078f209
LR		 2154 break;
2155 default:
2156 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2157 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2158 ret = -EOPNOTSUPP;
2159 goto out;
f078f209
LR		 2160 }
2161
17d7904d 2162 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2163
17d7904d 2164 /* Set the VIF opmode */
5640b08e
S		 2165 avp->av_opmode = ic_opmode;
2166 avp->av_bslot = -1;
2167
2c3db3d5 2168 sc->nvifs++;
8ca21f01
JM		 2169
2170 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2171 ath9k_set_bssid_mask(hw);
2172
2c3db3d5
JM		 2173 if (sc->nvifs > 1)
2174 goto out; /* skip global settings for secondary vif */
2175
b238e90e 2176 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2177 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2178 sc->sc_flags |= SC_OP_TSF_RESET;
2179 }
5640b08e 2180
5640b08e 2181 /* Set the device opmode */
2660b81a 2182 sc->sc_ah->opmode = ic_opmode;
5640b08e 2183
4e30ffa2
VN		 2184 /*
2185 * Enable MIB interrupts when there are hardware phy counters.
2186 * Note we only do this (at the moment) for station mode.
2187 */
4af9cf4f 2188 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2189 (conf->type == NL80211_IFTYPE_ADHOC) ||
2190 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2191 if (ath9k_hw_phycounters(sc->sc_ah))
2192 sc->imask |= ATH9K_INT_MIB;
2193 sc->imask |= ATH9K_INT_TSFOOR;
2194 }
2195
17d7904d 2196 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2197
f38faa31
SB		 2198 if (conf->type == NL80211_IFTYPE_AP ||
2199 conf->type == NL80211_IFTYPE_ADHOC ||
2200 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2201 ath_start_ani(sc);
6f255425 2202
2c3db3d5 2203out:
141b38b6 2204 mutex_unlock(&sc->mutex);
2c3db3d5 2205 return ret;
f078f209
LR		 2206}
2207
8feceb67
VT		 2208static void ath9k_remove_interface(struct ieee80211_hw *hw,
2209 struct ieee80211_if_init_conf *conf)
f078f209 2210{
bce048d7
JM		 2211 struct ath_wiphy *aphy = hw->priv;
2212 struct ath_softc *sc = aphy->sc;
17d7904d 2213 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2214 int i;
f078f209 2215
04bd4638 2216 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2217
141b38b6
S		 2218 mutex_lock(&sc->mutex);
2219
6f255425 2220 /* Stop ANI */
17d7904d 2221 del_timer_sync(&sc->ani.timer);
580f0b8a 2222
8feceb67 2223 /* Reclaim beacon resources */
9cb5412b
PE		 2224 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2225 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2226 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2227 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2228 ath_beacon_return(sc, avp);
580f0b8a 2229 }
f078f209 2230
8feceb67 2231 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2232
2c3db3d5
JM		 2233 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2234 if (sc->beacon.bslot[i] == conf->vif) {
2235 printk(KERN_DEBUG "%s: vif had allocated beacon "
2236 "slot\n", __func__);
2237 sc->beacon.bslot[i] = NULL;
c52f33d0 2238 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2239 }
2240 }
2241
17d7904d 2242 sc->nvifs--;
141b38b6
S		 2243
2244 mutex_unlock(&sc->mutex);
f078f209
LR		 2245}
2246
e8975581 2247static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2248{
bce048d7
JM		 2249 struct ath_wiphy *aphy = hw->priv;
2250 struct ath_softc *sc = aphy->sc;
e8975581 2251 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2252 struct ath_hw *ah = sc->sc_ah;
f078f209 2253
aa33de09 2254 mutex_lock(&sc->mutex);
141b38b6 2255
3cbb5dd7
VN		 2256 if (changed & IEEE80211_CONF_CHANGE_PS) {
2257 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2258 if (!(ah->caps.hw_caps &
2259 ATH9K_HW_CAP_AUTOSLEEP)) {
2260 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2261 sc->imask |= ATH9K_INT_TIM_TIMER;
2262 ath9k_hw_set_interrupts(sc->sc_ah,
2263 sc->imask);
2264 }
2265 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2266 }
3cbb5dd7
VN		 2267 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2268 } else {
2269 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2270 if (!(ah->caps.hw_caps &
2271 ATH9K_HW_CAP_AUTOSLEEP)) {
2272 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2273 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2274 SC_OP_WAIT_FOR_CAB |
2275 SC_OP_WAIT_FOR_PSPOLL_DATA |
2276 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2277 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2278 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2279 ath9k_hw_set_interrupts(sc->sc_ah,
2280 sc->imask);
2281 }
3cbb5dd7
VN		 2282 }
2283 }
2284 }
2285
4797938c 2286 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2287 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2288 int pos = curchan->hw_value;
ae5eb026 2289
0e2dedf9
JM		 2290 aphy->chan_idx = pos;
2291 aphy->chan_is_ht = conf_is_ht(conf);
2292
8089cc47
JM		 2293 if (aphy->state == ATH_WIPHY_SCAN ||
2294 aphy->state == ATH_WIPHY_ACTIVE)
2295 ath9k_wiphy_pause_all_forced(sc, aphy);
2296 else {
2297 /*
2298 * Do not change operational channel based on a paused
2299 * wiphy changes.
2300 */
2301 goto skip_chan_change;
2302 }
0e2dedf9 2303
04bd4638
S		 2304 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2305 curchan->center_freq);
f078f209 2306
5f8e077c 2307 /* XXX: remove me eventualy */
0e2dedf9 2308 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2309
ecf70441 2310 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2311
0e2dedf9 2312 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2313 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2314 mutex_unlock(&sc->mutex);
e11602b7
S		 2315 return -EINVAL;
2316 }
094d05dc 2317 }
f078f209 2318
8089cc47 2319skip_chan_change:
5c020dc6 2320 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2321 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2322
aa33de09 2323 mutex_unlock(&sc->mutex);
141b38b6 2324
f078f209
LR		 2325 return 0;
2326}
2327
8feceb67
VT		 2328#define SUPPORTED_FILTERS \
2329 (FIF_PROMISC_IN_BSS | \
2330 FIF_ALLMULTI | \
2331 FIF_CONTROL | \
2332 FIF_OTHER_BSS | \
2333 FIF_BCN_PRBRESP_PROMISC | \
2334 FIF_FCSFAIL)
c83be688 2335
8feceb67
VT		 2336/* FIXME: sc->sc_full_reset ? */
2337static void ath9k_configure_filter(struct ieee80211_hw *hw,
2338 unsigned int changed_flags,
2339 unsigned int *total_flags,
2340 int mc_count,
2341 struct dev_mc_list *mclist)
2342{
bce048d7
JM		 2343 struct ath_wiphy *aphy = hw->priv;
2344 struct ath_softc *sc = aphy->sc;
8feceb67 2345 u32 rfilt;
f078f209 2346
8feceb67
VT		 2347 changed_flags &= SUPPORTED_FILTERS;
2348 *total_flags &= SUPPORTED_FILTERS;
f078f209 2349
b77f483f 2350 sc->rx.rxfilter = *total_flags;
aa68aeaa 2351 ath9k_ps_wakeup(sc);
8feceb67
VT		 2352 rfilt = ath_calcrxfilter(sc);
2353 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2354 ath9k_ps_restore(sc);
f078f209 2355
b77f483f 2356 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2357}
f078f209 2358
8feceb67
VT		 2359static void ath9k_sta_notify(struct ieee80211_hw *hw,
2360 struct ieee80211_vif *vif,
2361 enum sta_notify_cmd cmd,
17741cdc 2362 struct ieee80211_sta *sta)
8feceb67 2363{
bce048d7
JM		 2364 struct ath_wiphy *aphy = hw->priv;
2365 struct ath_softc *sc = aphy->sc;
f078f209 2366
8feceb67
VT		 2367 switch (cmd) {
2368 case STA_NOTIFY_ADD:
5640b08e 2369 ath_node_attach(sc, sta);
8feceb67
VT		 2370 break;
2371 case STA_NOTIFY_REMOVE:
b5aa9bf9 2372 ath_node_detach(sc, sta);
8feceb67
VT		 2373 break;
2374 default:
2375 break;
2376 }
f078f209
LR		 2377}
2378
141b38b6 2379static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2380 const struct ieee80211_tx_queue_params *params)
f078f209 2381{
bce048d7
JM		 2382 struct ath_wiphy *aphy = hw->priv;
2383 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2384 struct ath9k_tx_queue_info qi;
2385 int ret = 0, qnum;
f078f209 2386
8feceb67
VT		 2387 if (queue >= WME_NUM_AC)
2388 return 0;
f078f209 2389
141b38b6
S		 2390 mutex_lock(&sc->mutex);
2391
1ffb0610
S		 2392 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2393
8feceb67
VT		 2394 qi.tqi_aifs = params->aifs;
2395 qi.tqi_cwmin = params->cw_min;
2396 qi.tqi_cwmax = params->cw_max;
2397 qi.tqi_burstTime = params->txop;
2398 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2399
8feceb67 2400 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2401 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2402 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2403 queue, qnum, params->aifs, params->cw_min,
2404 params->cw_max, params->txop);
f078f209 2405
8feceb67
VT		 2406 ret = ath_txq_update(sc, qnum, &qi);
2407 if (ret)
04bd4638 2408 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2409
141b38b6
S		 2410 mutex_unlock(&sc->mutex);
2411
8feceb67
VT		 2412 return ret;
2413}
f078f209 2414
8feceb67
VT		 2415static int ath9k_set_key(struct ieee80211_hw *hw,
2416 enum set_key_cmd cmd,
dc822b5d
JB		 2417 struct ieee80211_vif *vif,
2418 struct ieee80211_sta *sta,
8feceb67
VT		 2419 struct ieee80211_key_conf *key)
2420{
bce048d7
JM		 2421 struct ath_wiphy *aphy = hw->priv;
2422 struct ath_softc *sc = aphy->sc;
8feceb67 2423 int ret = 0;
f078f209 2424
b3bd89ce
JM		 2425 if (modparam_nohwcrypt)
2426 return -ENOSPC;
2427
141b38b6 2428 mutex_lock(&sc->mutex);
3cbb5dd7 2429 ath9k_ps_wakeup(sc);
d8baa939 2430 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2431
8feceb67
VT		 2432 switch (cmd) {
2433 case SET_KEY:
3f53dd64 2434 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2435 if (ret >= 0) {
2436 key->hw_key_idx = ret;
8feceb67
VT		 2437 /* push IV and Michael MIC generation to stack */
2438 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2439 if (key->alg == ALG_TKIP)
2440 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2441 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2442 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2443 ret = 0;
8feceb67
VT		 2444 }
2445 break;
2446 case DISABLE_KEY:
2447 ath_key_delete(sc, key);
8feceb67
VT		 2448 break;
2449 default:
2450 ret = -EINVAL;
2451 }
f078f209 2452
3cbb5dd7 2453 ath9k_ps_restore(sc);
141b38b6
S		 2454 mutex_unlock(&sc->mutex);
2455
8feceb67
VT		 2456 return ret;
2457}
f078f209 2458
8feceb67
VT		 2459static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2460 struct ieee80211_vif *vif,
2461 struct ieee80211_bss_conf *bss_conf,
2462 u32 changed)
2463{
bce048d7
JM		 2464 struct ath_wiphy *aphy = hw->priv;
2465 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2466 struct ath_hw *ah = sc->sc_ah;
2467 struct ath_vif *avp = (void *)vif->drv_priv;
2468 u32 rfilt = 0;
2469 int error, i;
f078f209 2470
141b38b6
S		 2471 mutex_lock(&sc->mutex);
2472
2d0ddec5
JB		 2473 /*
2474 * TODO: Need to decide which hw opmode to use for
2475 * multi-interface cases
2476 * XXX: This belongs into add_interface!
2477 */
2478 if (vif->type == NL80211_IFTYPE_AP &&
2479 ah->opmode != NL80211_IFTYPE_AP) {
2480 ah->opmode = NL80211_IFTYPE_STATION;
2481 ath9k_hw_setopmode(ah);
2482 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2483 sc->curaid = 0;
2484 ath9k_hw_write_associd(sc);
2485 /* Request full reset to get hw opmode changed properly */
2486 sc->sc_flags |= SC_OP_FULL_RESET;
2487 }
2488
2489 if ((changed & BSS_CHANGED_BSSID) &&
2490 !is_zero_ether_addr(bss_conf->bssid)) {
2491 switch (vif->type) {
2492 case NL80211_IFTYPE_STATION:
2493 case NL80211_IFTYPE_ADHOC:
2494 case NL80211_IFTYPE_MESH_POINT:
2495 /* Set BSSID */
2496 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2497 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2498 sc->curaid = 0;
2499 ath9k_hw_write_associd(sc);
2500
2501 /* Set aggregation protection mode parameters */
2502 sc->config.ath_aggr_prot = 0;
2503
2504 DPRINTF(sc, ATH_DBG_CONFIG,
2505 "RX filter 0x%x bssid %pM aid 0x%x\n",
2506 rfilt, sc->curbssid, sc->curaid);
2507
2508 /* need to reconfigure the beacon */
2509 sc->sc_flags &= ~SC_OP_BEACONS ;
2510
2511 break;
2512 default:
2513 break;
2514 }
2515 }
2516
2517 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2518 (vif->type == NL80211_IFTYPE_AP) ||
2519 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2520 if ((changed & BSS_CHANGED_BEACON) ||
2521 (changed & BSS_CHANGED_BEACON_ENABLED &&
2522 bss_conf->enable_beacon)) {
2523 /*
2524 * Allocate and setup the beacon frame.
2525 *
2526 * Stop any previous beacon DMA. This may be
2527 * necessary, for example, when an ibss merge
2528 * causes reconfiguration; we may be called
2529 * with beacon transmission active.
2530 */
2531 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2532
2533 error = ath_beacon_alloc(aphy, vif);
2534 if (!error)
2535 ath_beacon_config(sc, vif);
2536 }
2537 }
2538
2539 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2540 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2541 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2542 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2543 ath9k_hw_keysetmac(sc->sc_ah,
2544 (u16)i,
2545 sc->curbssid);
2546 }
2547
2548 /* Only legacy IBSS for now */
2549 if (vif->type == NL80211_IFTYPE_ADHOC)
2550 ath_update_chainmask(sc, 0);
2551
8feceb67 2552 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2553 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2554 bss_conf->use_short_preamble);
2555 if (bss_conf->use_short_preamble)
2556 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2557 else
2558 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2559 }
f078f209 2560
8feceb67 2561 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2562 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2563 bss_conf->use_cts_prot);
2564 if (bss_conf->use_cts_prot &&
2565 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2566 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2567 else
2568 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2569 }
f078f209 2570
8feceb67 2571 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2572 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2573 bss_conf->assoc);
5640b08e 2574 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2575 }
141b38b6 2576
57c4d7b4
JB		 2577 /*
2578 * The HW TSF has to be reset when the beacon interval changes.
2579 * We set the flag here, and ath_beacon_config_ap() would take this
2580 * into account when it gets called through the subsequent
2581 * config_interface() call - with IFCC_BEACON in the changed field.
2582 */
2583
2584 if (changed & BSS_CHANGED_BEACON_INT) {
2585 sc->sc_flags |= SC_OP_TSF_RESET;
2586 sc->beacon_interval = bss_conf->beacon_int;
2587 }
2588
141b38b6 2589 mutex_unlock(&sc->mutex);
8feceb67 2590}
f078f209 2591
8feceb67
VT		 2592static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2593{
2594 u64 tsf;
bce048d7
JM		 2595 struct ath_wiphy *aphy = hw->priv;
2596 struct ath_softc *sc = aphy->sc;
f078f209 2597
141b38b6
S		 2598 mutex_lock(&sc->mutex);
2599 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2600 mutex_unlock(&sc->mutex);
f078f209 2601
8feceb67
VT		 2602 return tsf;
2603}
f078f209 2604
3b5d665b
AF		 2605static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2606{
bce048d7
JM		 2607 struct ath_wiphy *aphy = hw->priv;
2608 struct ath_softc *sc = aphy->sc;
3b5d665b 2609
141b38b6
S		 2610 mutex_lock(&sc->mutex);
2611 ath9k_hw_settsf64(sc->sc_ah, tsf);
2612 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2613}
2614
8feceb67
VT		 2615static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2616{
bce048d7
JM		 2617 struct ath_wiphy *aphy = hw->priv;
2618 struct ath_softc *sc = aphy->sc;
c83be688 2619
141b38b6
S		 2620 mutex_lock(&sc->mutex);
2621 ath9k_hw_reset_tsf(sc->sc_ah);
2622 mutex_unlock(&sc->mutex);
8feceb67 2623}
f078f209 2624
8feceb67 2625static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2626 enum ieee80211_ampdu_mlme_action action,
2627 struct ieee80211_sta *sta,
2628 u16 tid, u16 *ssn)
8feceb67 2629{
bce048d7
JM		 2630 struct ath_wiphy *aphy = hw->priv;
2631 struct ath_softc *sc = aphy->sc;
8feceb67 2632 int ret = 0;
f078f209 2633
8feceb67
VT		 2634 switch (action) {
2635 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2636 if (!(sc->sc_flags & SC_OP_RXAGGR))
2637 ret = -ENOTSUPP;
8feceb67
VT		 2638 break;
2639 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2640 break;
2641 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2642 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2643 if (ret < 0)
2644 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2645 "Unable to start TX aggregation\n");
8feceb67 2646 else
17741cdc 2647 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2648 break;
2649 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2650 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2651 if (ret < 0)
2652 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2653 "Unable to stop TX aggregation\n");
f078f209 2654
17741cdc 2655 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2656 break;
b1720231 2657 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2658 ath_tx_aggr_resume(sc, sta, tid);
2659 break;
8feceb67 2660 default:
04bd4638 2661 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2662 }
2663
2664 return ret;
f078f209
LR		 2665}
2666
0c98de65
S		 2667static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2668{
bce048d7
JM		 2669 struct ath_wiphy *aphy = hw->priv;
2670 struct ath_softc *sc = aphy->sc;
0c98de65 2671
8089cc47
JM		 2672 if (ath9k_wiphy_scanning(sc)) {
2673 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2674 "same time\n");
2675 /*
2676 * Do not allow the concurrent scanning state for now. This
2677 * could be improved with scanning control moved into ath9k.
2678 */
2679 return;
2680 }
2681
2682 aphy->state = ATH_WIPHY_SCAN;
2683 ath9k_wiphy_pause_all_forced(sc, aphy);
2684
0c98de65
S		 2685 mutex_lock(&sc->mutex);
2686 sc->sc_flags |= SC_OP_SCANNING;
2687 mutex_unlock(&sc->mutex);
2688}
2689
2690static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2691{
bce048d7
JM		 2692 struct ath_wiphy *aphy = hw->priv;
2693 struct ath_softc *sc = aphy->sc;
0c98de65
S		 2694
2695 mutex_lock(&sc->mutex);
8089cc47 2696 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2697 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2698 sc->sc_flags |= SC_OP_FULL_RESET;
0c98de65
S		 2699 mutex_unlock(&sc->mutex);
2700}
2701
6baff7f9 2702struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2703 .tx = ath9k_tx,
2704 .start = ath9k_start,
2705 .stop = ath9k_stop,
2706 .add_interface = ath9k_add_interface,
2707 .remove_interface = ath9k_remove_interface,
2708 .config = ath9k_config,
8feceb67 2709 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2710 .sta_notify = ath9k_sta_notify,
2711 .conf_tx = ath9k_conf_tx,
8feceb67 2712 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2713 .set_key = ath9k_set_key,
8feceb67 2714 .get_tsf = ath9k_get_tsf,
3b5d665b 2715 .set_tsf = ath9k_set_tsf,
8feceb67 2716 .reset_tsf = ath9k_reset_tsf,
4233df6b 2717 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2718 .sw_scan_start = ath9k_sw_scan_start,
2719 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2720 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2721};
2722
392dff83
BP		 2723static struct {
2724 u32 version;
2725 const char * name;
2726} ath_mac_bb_names[] = {
2727 { AR_SREV_VERSION_5416_PCI, "5416" },
2728 { AR_SREV_VERSION_5416_PCIE, "5418" },
2729 { AR_SREV_VERSION_9100, "9100" },
2730 { AR_SREV_VERSION_9160, "9160" },
2731 { AR_SREV_VERSION_9280, "9280" },
2732 { AR_SREV_VERSION_9285, "9285" }
2733};
2734
2735static struct {
2736 u16 version;
2737 const char * name;
2738} ath_rf_names[] = {
2739 { 0, "5133" },
2740 { AR_RAD5133_SREV_MAJOR, "5133" },
2741 { AR_RAD5122_SREV_MAJOR, "5122" },
2742 { AR_RAD2133_SREV_MAJOR, "2133" },
2743 { AR_RAD2122_SREV_MAJOR, "2122" }
2744};
2745
2746/*
2747 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2748 */
6baff7f9 2749const char *
392dff83
BP		 2750ath_mac_bb_name(u32 mac_bb_version)
2751{
2752 int i;
2753
2754 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2755 if (ath_mac_bb_names[i].version == mac_bb_version) {
2756 return ath_mac_bb_names[i].name;
2757 }
2758 }
2759
2760 return "????";
2761}
2762
2763/*
2764 * Return the RF name. "????" is returned if the RF is unknown.
2765 */
6baff7f9 2766const char *
392dff83
BP		 2767ath_rf_name(u16 rf_version)
2768{
2769 int i;
2770
2771 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2772 if (ath_rf_names[i].version == rf_version) {
2773 return ath_rf_names[i].name;
2774 }
2775 }
2776
2777 return "????";
2778}
2779
6baff7f9 2780static int __init ath9k_init(void)
f078f209 2781{
ca8a8560
VT		 2782 int error;
2783
ca8a8560
VT		 2784 /* Register rate control algorithm */
2785 error = ath_rate_control_register();
2786 if (error != 0) {
2787 printk(KERN_ERR
b51bb3cd
LR		 2788 "ath9k: Unable to register rate control "
2789 "algorithm: %d\n",
ca8a8560 2790 error);
6baff7f9 2791 goto err_out;
ca8a8560
VT		 2792 }
2793
19d8bc22
GJ		 2794 error = ath9k_debug_create_root();
2795 if (error) {
2796 printk(KERN_ERR
2797 "ath9k: Unable to create debugfs root: %d\n",
2798 error);
2799 goto err_rate_unregister;
2800 }
2801
6baff7f9
GJ		 2802 error = ath_pci_init();
2803 if (error < 0) {
f078f209 2804 printk(KERN_ERR
b51bb3cd 2805 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2806 error = -ENODEV;
19d8bc22 2807 goto err_remove_root;
f078f209
LR		 2808 }
2809
09329d37
GJ		 2810 error = ath_ahb_init();
2811 if (error < 0) {
2812 error = -ENODEV;
2813 goto err_pci_exit;
2814 }
2815
f078f209 2816 return 0;
6baff7f9 2817
09329d37
GJ		 2818 err_pci_exit:
2819 ath_pci_exit();
2820
19d8bc22
GJ		 2821 err_remove_root:
2822 ath9k_debug_remove_root();
6baff7f9
GJ		 2823 err_rate_unregister:
2824 ath_rate_control_unregister();
2825 err_out:
2826 return error;
f078f209 2827}
6baff7f9 2828module_init(ath9k_init);
f078f209 2829
6baff7f9 2830static void __exit ath9k_exit(void)
f078f209 2831{
09329d37 2832 ath_ahb_exit();
6baff7f9 2833 ath_pci_exit();
19d8bc22 2834 ath9k_debug_remove_root();
ca8a8560 2835 ath_rate_control_unregister();
04bd4638 2836 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2837}
6baff7f9 2838module_exit(ath9k_exit);
Linux 6.x block layer and io_uring tree(s)