ath9k: move ath9k_spectral_scan_ from main.c to spectral.c
[linux-2.6-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
313eb87f 22u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S
23{
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55}
56
e2d389b5
SM
57static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
69081624
VT
59{
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
b7367285 64 if (txq->axq_depth) {
69081624 65 pending = true;
b7367285
SM
66 goto out;
67 }
69081624 68
e2d389b5
SM
69 if (!sw_pending)
70 goto out;
71
0453531e
FF
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
b7367285 79out:
69081624
VT
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82}
83
6d79cb4c 84static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
85{
86 unsigned long flags;
87 bool ret;
88
9ecdef4b
LR
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
92
93 return ret;
94}
95
bf3dac5a
FF
96void ath_ps_full_sleep(unsigned long data)
97{
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110}
111
a91d75ae
LR
112void ath9k_ps_wakeup(struct ath_softc *sc)
113{
898c914a 114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 115 unsigned long flags;
fbb078fc 116 enum ath9k_power_mode power_mode;
a91d75ae
LR
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
bf3dac5a 122 del_timer_sync(&sc->sleep_timer);
fbb078fc 123 power_mode = sc->sc_ah->power_mode;
9ecdef4b 124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 125
898c914a
FF
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
fbb078fc
FF
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF
136 spin_unlock(&common->cc_lock);
137 }
898c914a 138
a91d75ae
LR
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141}
142
143void ath9k_ps_restore(struct ath_softc *sc)
144{
898c914a 145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 146 enum ath9k_power_mode mode;
a91d75ae
LR
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
ad128860 153 if (sc->ps_idle) {
bf3dac5a
FF
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
ad128860
SM
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
c6c539f0 164 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
ad128860 167 } else {
c6c539f0 168 goto unlock;
ad128860 169 }
c6c539f0
FF
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
1a8f0d39 175 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179}
180
9adcf440 181static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 182{
5ee08656 183 cancel_work_sync(&sc->paprd_work);
5ee08656 184 cancel_delayed_work_sync(&sc->tx_complete_work);
181fb18d 185 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 186
bf52592f 187#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
bf52592f 190#endif
9adcf440 191}
5ee08656 192
e60001e7 193void ath_cancel_work(struct ath_softc *sc)
9adcf440
FF
194{
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197}
3cbb5dd7 198
e60001e7 199void ath_restart_work(struct ath_softc *sc)
af68abad 200{
af68abad
SM
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
19c36160 203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
af68abad
SM
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
da0d45f7 207 ath_start_ani(sc);
af68abad
SM
208}
209
9ebea382 210static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF
211{
212 struct ath_hw *ah = sc->sc_ah;
ceea2a51 213 bool ret = true;
6a6733f2 214
9adcf440 215 ieee80211_stop_queues(sc->hw);
da0d45f7 216 ath_stop_ani(sc);
9adcf440 217 ath9k_hw_disable_interrupts(ah);
8b3f4616 218
1381559b 219 if (!ath_drain_all_txq(sc))
9adcf440 220 ret = false;
c0d7c7af 221
0a62acb1 222 if (!ath_stoprecv(sc))
ceea2a51
FF
223 ret = false;
224
9adcf440
FF
225 return ret;
226}
ff37e337 227
9adcf440
FF
228static bool ath_complete_reset(struct ath_softc *sc, bool start)
229{
230 struct ath_hw *ah = sc->sc_ah;
231 struct ath_common *common = ath9k_hw_common(ah);
196fb860 232 unsigned long flags;
c0d7c7af 233
9019f646 234 ath9k_calculate_summary_state(sc, sc->cur_chan);
19ec477f 235 ath_startrecv(sc);
d385c5c2
FF
236 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
237 sc->cur_chan->txpower,
238 &sc->cur_chan->cur_txpower);
eefa01dd 239 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
3989279c 240
fbbcd146 241 if (!sc->cur_chan->offchannel && start) {
8d7e09dd
FF
242 /* restore per chanctx TSF timer */
243 if (sc->cur_chan->tsf_val) {
244 u32 offset;
245
246 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
247 NULL);
248 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
249 }
250
251
eefa01dd 252 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
196fb860
SM
253 goto work;
254
196fb860 255 if (ah->opmode == NL80211_IFTYPE_STATION &&
eefa01dd 256 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
196fb860
SM
257 spin_lock_irqsave(&sc->sc_pm_lock, flags);
258 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
259 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
a6768280
SM
260 } else {
261 ath9k_set_beacon(sc);
196fb860
SM
262 }
263 work:
af68abad 264 ath_restart_work(sc);
0453531e 265 ath_txq_schedule_all(sc);
5ee08656
FF
266 }
267
071aa9a8 268 sc->gtt_cnt = 0;
9a9c4fbc
RM
269
270 ath9k_hw_set_interrupts(ah);
271 ath9k_hw_enable_interrupts(ah);
5ba8d9d2 272 ieee80211_wake_queues(sc->hw);
d463af4a
FF
273 ath9k_p2p_ps_timer(sc);
274
9adcf440
FF
275 return true;
276}
277
5555c955 278static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF
279{
280 struct ath_hw *ah = sc->sc_ah;
281 struct ath_common *common = ath9k_hw_common(ah);
282 struct ath9k_hw_cal_data *caldata = NULL;
283 bool fastcc = true;
9adcf440
FF
284 int r;
285
286 __ath_cancel_work(sc);
287
4668cce5 288 tasklet_disable(&sc->intr_tq);
eaf04a69 289 tasklet_disable(&sc->bcon_tasklet);
9adcf440 290 spin_lock_bh(&sc->sc_pcu_lock);
92460412 291
fbbcd146 292 if (!sc->cur_chan->offchannel) {
9adcf440 293 fastcc = false;
b01459e8 294 caldata = &sc->cur_chan->caldata;
9adcf440
FF
295 }
296
297 if (!hchan) {
298 fastcc = false;
9adcf440
FF
299 hchan = ah->curchan;
300 }
301
9ebea382 302 if (!ath_prepare_reset(sc))
9adcf440
FF
303 fastcc = false;
304
9ea3598b
SM
305 if (ath9k_is_chanctx_enabled())
306 fastcc = false;
307
d6067f0e
RM
308 spin_lock_bh(&sc->chan_lock);
309 sc->cur_chandef = sc->cur_chan->chandef;
310 spin_unlock_bh(&sc->chan_lock);
bff11766 311
d2182b69 312 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 313 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF
314
315 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
316 if (r) {
317 ath_err(common,
318 "Unable to reset channel, reset status %d\n", r);
f50b1cd3
RS
319
320 ath9k_hw_enable_interrupts(ah);
321 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
322
9adcf440
FF
323 goto out;
324 }
325
e82cb03f 326 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
fbbcd146 327 sc->cur_chan->offchannel)
e82cb03f
RM
328 ath9k_mci_set_txpower(sc, true, false);
329
9adcf440
FF
330 if (!ath_complete_reset(sc, true))
331 r = -EIO;
332
333out:
6a6733f2 334 spin_unlock_bh(&sc->sc_pcu_lock);
eaf04a69 335 tasklet_enable(&sc->bcon_tasklet);
4668cce5
FF
336 tasklet_enable(&sc->intr_tq);
337
9adcf440
FF
338 return r;
339}
340
7e1e3864
BG
341static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
342 struct ieee80211_vif *vif)
ff37e337
S
343{
344 struct ath_node *an;
ff37e337
S
345 an = (struct ath_node *)sta->drv_priv;
346
a145daf7 347 an->sc = sc;
7f010c93 348 an->sta = sta;
7e1e3864 349 an->vif = vif;
4bbf4414 350 memset(&an->key_idx, 0, sizeof(an->key_idx));
3d4e20f2 351
dd5ee59b 352 ath_tx_node_init(sc, an);
44b47a7d
LB
353
354 ath_dynack_node_init(sc->sc_ah, an);
ff37e337
S
355}
356
357static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
358{
359 struct ath_node *an = (struct ath_node *)sta->drv_priv;
dd5ee59b 360 ath_tx_node_cleanup(sc, an);
44b47a7d
LB
361
362 ath_dynack_node_deinit(sc->sc_ah, an);
ff37e337
S
363}
364
55624204 365void ath9k_tasklet(unsigned long data)
ff37e337
S
366{
367 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 368 struct ath_hw *ah = sc->sc_ah;
c46917bb 369 struct ath_common *common = ath9k_hw_common(ah);
124b979b 370 enum ath_reset_type type;
07c15a3f 371 unsigned long flags;
17d7904d 372 u32 status = sc->intrstatus;
b5c80475 373 u32 rxmask;
ff37e337 374
e3927007
FF
375 ath9k_ps_wakeup(sc);
376 spin_lock(&sc->sc_pcu_lock);
377
6549a860
SM
378 if (status & ATH9K_INT_FATAL) {
379 type = RESET_TYPE_FATAL_INT;
124b979b 380 ath9k_queue_reset(sc, type);
c6cc47b1
SM
381
382 /*
383 * Increment the ref. counter here so that
384 * interrupts are enabled in the reset routine.
385 */
386 atomic_inc(&ah->intr_ref_cnt);
affad456 387 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
e3927007 388 goto out;
063d8be3 389 }
ff37e337 390
6549a860
SM
391 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
392 (status & ATH9K_INT_BB_WATCHDOG)) {
0c759977
SM
393 spin_lock(&common->cc_lock);
394 ath_hw_cycle_counters_update(common);
395 ar9003_hw_bb_watchdog_dbg_info(ah);
396 spin_unlock(&common->cc_lock);
397
6549a860
SM
398 if (ar9003_hw_bb_watchdog_check(ah)) {
399 type = RESET_TYPE_BB_WATCHDOG;
400 ath9k_queue_reset(sc, type);
401
402 /*
403 * Increment the ref. counter here so that
404 * interrupts are enabled in the reset routine.
405 */
406 atomic_inc(&ah->intr_ref_cnt);
affad456 407 ath_dbg(common, RESET,
6549a860
SM
408 "BB_WATCHDOG: Skipping interrupts\n");
409 goto out;
410 }
411 }
412
071aa9a8
SM
413 if (status & ATH9K_INT_GTT) {
414 sc->gtt_cnt++;
415
416 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
417 type = RESET_TYPE_TX_GTT;
418 ath9k_queue_reset(sc, type);
419 atomic_inc(&ah->intr_ref_cnt);
affad456 420 ath_dbg(common, RESET,
071aa9a8
SM
421 "GTT: Skipping interrupts\n");
422 goto out;
423 }
424 }
425
07c15a3f 426 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM
427 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
428 /*
429 * TSF sync does not look correct; remain awake to sync with
430 * the next Beacon.
431 */
d2182b69 432 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 433 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 434 }
07c15a3f 435 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 436
b5c80475
FF
437 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
438 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
439 ATH9K_INT_RXORN);
440 else
441 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
442
443 if (status & rxmask) {
b5c80475
FF
444 /* Check for high priority Rx first */
445 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
446 (status & ATH9K_INT_RXHP))
447 ath_rx_tasklet(sc, 0, true);
448
449 ath_rx_tasklet(sc, 0, false);
ff37e337
S
450 }
451
e5003249 452 if (status & ATH9K_INT_TX) {
071aa9a8
SM
453 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
454 /*
455 * For EDMA chips, TX completion is enabled for the
456 * beacon queue, so if a beacon has been transmitted
457 * successfully after a GTT interrupt, the GTT counter
458 * gets reset to zero here.
459 */
3b745c7b 460 sc->gtt_cnt = 0;
071aa9a8 461
e5003249 462 ath_tx_edma_tasklet(sc);
071aa9a8 463 } else {
e5003249 464 ath_tx_tasklet(sc);
071aa9a8 465 }
10e23181
FF
466
467 wake_up(&sc->tx_wait);
e5003249 468 }
063d8be3 469
c67ce339
FF
470 if (status & ATH9K_INT_GENTIMER)
471 ath_gen_timer_isr(sc->sc_ah);
472
56ca0dba 473 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 474
ff37e337 475 /* re-enable hardware interrupt */
4df3071e 476 ath9k_hw_enable_interrupts(ah);
c6cc47b1 477out:
52671e43 478 spin_unlock(&sc->sc_pcu_lock);
153e080d 479 ath9k_ps_restore(sc);
ff37e337
S
480}
481
6baff7f9 482irqreturn_t ath_isr(int irq, void *dev)
ff37e337 483{
063d8be3
S
484#define SCHED_INTR ( \
485 ATH9K_INT_FATAL | \
a4d86d95 486 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S
487 ATH9K_INT_RXORN | \
488 ATH9K_INT_RXEOL | \
489 ATH9K_INT_RX | \
b5c80475
FF
490 ATH9K_INT_RXLP | \
491 ATH9K_INT_RXHP | \
063d8be3
S
492 ATH9K_INT_TX | \
493 ATH9K_INT_BMISS | \
494 ATH9K_INT_CST | \
071aa9a8 495 ATH9K_INT_GTT | \
ebb8e1d7 496 ATH9K_INT_TSFOOR | \
40dc5392
MSS
497 ATH9K_INT_GENTIMER | \
498 ATH9K_INT_MCI)
063d8be3 499
ff37e337 500 struct ath_softc *sc = dev;
cbe61d8a 501 struct ath_hw *ah = sc->sc_ah;
eefa01dd 502 struct ath_common *common = ath9k_hw_common(ah);
ff37e337 503 enum ath9k_int status;
78c8a950 504 u32 sync_cause = 0;
ff37e337
S
505 bool sched = false;
506
063d8be3
S
507 /*
508 * The hardware is not ready/present, don't
509 * touch anything. Note this can happen early
510 * on if the IRQ is shared.
511 */
2ba7d144 512 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
063d8be3 513 return IRQ_NONE;
ff37e337 514
063d8be3
S
515 /* shared irq, not for us */
516
153e080d 517 if (!ath9k_hw_intrpend(ah))
063d8be3 518 return IRQ_NONE;
063d8be3 519
eefa01dd 520 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
f41a9b3b 521 ath9k_hw_kill_interrupts(ah);
b74713d0 522 return IRQ_HANDLED;
f41a9b3b 523 }
b74713d0 524
063d8be3
S
525 /*
526 * Figure out the reason(s) for the interrupt. Note
527 * that the hal returns a pseudo-ISR that may include
528 * bits we haven't explicitly enabled so we mask the
529 * value to insure we only process bits we requested.
530 */
6a4d05dc
FF
531 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
532 ath9k_debug_sync_cause(sc, sync_cause);
3069168c 533 status &= ah->imask; /* discard unasked-for bits */
ff37e337 534
063d8be3
S
535 /*
536 * If there are no status bits set, then this interrupt was not
537 * for me (should have been caught above).
538 */
153e080d 539 if (!status)
063d8be3 540 return IRQ_NONE;
ff37e337 541
063d8be3
S
542 /* Cache the status */
543 sc->intrstatus = status;
544
545 if (status & SCHED_INTR)
546 sched = true;
547
548 /*
3b580144
FF
549 * If a FATAL interrupt is received, we have to reset the chip
550 * immediately.
063d8be3 551 */
3b580144 552 if (status & ATH9K_INT_FATAL)
063d8be3
S
553 goto chip_reset;
554
a6bb860b 555 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0c759977 556 (status & ATH9K_INT_BB_WATCHDOG))
08578b8f 557 goto chip_reset;
e60001e7
SM
558
559#ifdef CONFIG_ATH9K_WOW
ca90ef44
RM
560 if (status & ATH9K_INT_BMISS) {
561 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
ca90ef44
RM
562 atomic_inc(&sc->wow_got_bmiss_intr);
563 atomic_dec(&sc->wow_sleep_proc_intr);
564 }
565 }
566#endif
e60001e7 567
063d8be3
S
568 if (status & ATH9K_INT_SWBA)
569 tasklet_schedule(&sc->bcon_tasklet);
570
571 if (status & ATH9K_INT_TXURN)
572 ath9k_hw_updatetxtriglevel(ah, true);
573
0682c9b5
RM
574 if (status & ATH9K_INT_RXEOL) {
575 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 576 ath9k_hw_set_interrupts(ah);
b5c80475
FF
577 }
578
153e080d
VT
579 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
580 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR
581 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
582 goto chip_reset;
063d8be3
S
583 /* Clear RxAbort bit so that we can
584 * receive frames */
9ecdef4b 585 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 586 spin_lock(&sc->sc_pm_lock);
153e080d 587 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 588 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 589 spin_unlock(&sc->sc_pm_lock);
ff37e337 590 }
063d8be3
S
591
592chip_reset:
ff37e337 593
817e11de
S
594 ath_debug_stat_interrupt(sc, status);
595
ff37e337 596 if (sched) {
4df3071e
FF
597 /* turn off every interrupt */
598 ath9k_hw_disable_interrupts(ah);
ff37e337
S
599 tasklet_schedule(&sc->intr_tq);
600 }
601
602 return IRQ_HANDLED;
063d8be3
S
603
604#undef SCHED_INTR
ff37e337
S
605}
606
ae2ff239
SM
607/*
608 * This function is called when a HW reset cannot be deferred
609 * and has to be immediate.
610 */
5555c955 611int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
ff37e337 612{
ae2ff239 613 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ec30326e 614 int r;
ff37e337 615
ae2ff239
SM
616 set_bit(ATH_OP_HW_RESET, &common->op_flags);
617
783cd01e 618 ath9k_ps_wakeup(sc);
5555c955 619 r = ath_reset_internal(sc, hchan);
783cd01e 620 ath9k_ps_restore(sc);
2ab81d4a 621
ae8d2858 622 return r;
ff37e337
S
623}
624
ae2ff239
SM
625/*
626 * When a HW reset can be deferred, it is added to the
627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
628 * queueing.
629 */
124b979b
RM
630void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
631{
eefa01dd 632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
124b979b
RM
633#ifdef CONFIG_ATH9K_DEBUGFS
634 RESET_STAT_INC(sc, type);
635#endif
eefa01dd 636 set_bit(ATH_OP_HW_RESET, &common->op_flags);
124b979b
RM
637 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
638}
639
236de514
FF
640void ath_reset_work(struct work_struct *work)
641{
642 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
643
5555c955
SM
644 ath9k_ps_wakeup(sc);
645 ath_reset_internal(sc, NULL);
646 ath9k_ps_restore(sc);
236de514
FF
647}
648
ff37e337
S
649/**********************/
650/* mac80211 callbacks */
651/**********************/
652
8feceb67 653static int ath9k_start(struct ieee80211_hw *hw)
f078f209 654{
9ac58615 655 struct ath_softc *sc = hw->priv;
af03abec 656 struct ath_hw *ah = sc->sc_ah;
c46917bb 657 struct ath_common *common = ath9k_hw_common(ah);
39305635 658 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
fbbcd146 659 struct ath_chanctx *ctx = sc->cur_chan;
ff37e337 660 struct ath9k_channel *init_channel;
82880a7c 661 int r;
f078f209 662
d2182b69 663 ath_dbg(common, CONFIG,
226afe68
JP
664 "Starting driver with initial channel: %d MHz\n",
665 curchan->center_freq);
f078f209 666
f62d816f 667 ath9k_ps_wakeup(sc);
141b38b6
S
668 mutex_lock(&sc->mutex);
669
fbbcd146 670 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
bff11766 671 sc->cur_chandef = hw->conf.chandef;
ff37e337
S
672
673 /* Reset SERDES registers */
84c87dc8 674 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S
675
676 /*
677 * The basic interface to setting the hardware in a good
678 * state is ``reset''. On return the hardware is known to
679 * be powered up and with interrupts disabled. This must
680 * be followed by initialization of the appropriate bits
681 * and then setup of the interrupt mask.
682 */
4bdd1e97 683 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF
684
685 atomic_set(&ah->intr_ref_cnt, -1);
686
20bd2a09 687 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 688 if (r) {
3800276a
JP
689 ath_err(common,
690 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
691 r, curchan->center_freq);
ceb26a60 692 ah->reset_power_on = false;
ff37e337 693 }
ff37e337 694
ff37e337 695 /* Setup our intr mask. */
b5c80475
FF
696 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
697 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
698 ATH9K_INT_GLOBAL;
699
700 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f 701 ah->imask |= ATH9K_INT_RXHP |
a6bb860b 702 ATH9K_INT_RXLP;
b5c80475
FF
703 else
704 ah->imask |= ATH9K_INT_RX;
ff37e337 705
a6bb860b
SM
706 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
707 ah->imask |= ATH9K_INT_BB_WATCHDOG;
708
071aa9a8
SM
709 /*
710 * Enable GTT interrupts only for AR9003/AR9004 chips
711 * for now.
712 */
713 if (AR_SREV_9300_20_OR_LATER(ah))
714 ah->imask |= ATH9K_INT_GTT;
ff37e337 715
af03abec 716 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 717 ah->imask |= ATH9K_INT_CST;
ff37e337 718
e270e776 719 ath_mci_enable(sc);
40dc5392 720
eefa01dd 721 clear_bit(ATH_OP_INVALID, &common->op_flags);
5f841b41 722 sc->sc_ah->is_monitoring = false;
ff37e337 723
ceb26a60
FF
724 if (!ath_complete_reset(sc, false))
725 ah->reset_power_on = false;
ff37e337 726
c0c11741
FF
727 if (ah->led_pin >= 0) {
728 ath9k_hw_cfg_output(ah, ah->led_pin,
729 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
730 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
731 }
732
733 /*
734 * Reset key cache to sane defaults (all entries cleared) instead of
735 * semi-random values after suspend/resume.
736 */
737 ath9k_cmn_init_crypto(sc->sc_ah);
738
a35051ce
FF
739 ath9k_hw_reset_tsf(ah);
740
9adcf440 741 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 742
141b38b6
S
743 mutex_unlock(&sc->mutex);
744
f62d816f
FF
745 ath9k_ps_restore(sc);
746
ceb26a60 747 return 0;
f078f209
LR
748}
749
36323f81
TH
750static void ath9k_tx(struct ieee80211_hw *hw,
751 struct ieee80211_tx_control *control,
752 struct sk_buff *skb)
f078f209 753{
9ac58615 754 struct ath_softc *sc = hw->priv;
c46917bb 755 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 756 struct ath_tx_control txctl;
1bc14880 757 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 758 unsigned long flags;
528f0c6b 759
96148326 760 if (sc->ps_enabled) {
dc8c4585
JM
761 /*
762 * mac80211 does not set PM field for normal data frames, so we
763 * need to update that based on the current PS mode.
764 */
765 if (ieee80211_is_data(hdr->frame_control) &&
766 !ieee80211_is_nullfunc(hdr->frame_control) &&
767 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 768 ath_dbg(common, PS,
226afe68 769 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM
770 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
771 }
772 }
773
ad128860 774 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM
775 /*
776 * We are using PS-Poll and mac80211 can request TX while in
777 * power save mode. Need to wake up hardware for the TX to be
778 * completed and if needed, also for RX of buffered frames.
779 */
9a23f9ca 780 ath9k_ps_wakeup(sc);
07c15a3f 781 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT
782 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
783 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 784 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 785 ath_dbg(common, PS,
226afe68 786 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 787 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 788 } else {
d2182b69 789 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 790 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
791 }
792 /*
793 * The actual restore operation will happen only after
ad128860 794 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM
795 * the ps_usecount here.
796 */
07c15a3f 797 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM
798 ath9k_ps_restore(sc);
799 }
800
ad128860
SM
801 /*
802 * Cannot tx while the hardware is in full sleep, it first needs a full
803 * chip reset to recover from that
804 */
805 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
806 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
807 goto exit;
808 }
809
528f0c6b 810 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 811 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 812 txctl.sta = control->sta;
528f0c6b 813
d2182b69 814 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 815
c52f33d0 816 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 817 ath_dbg(common, XMIT, "TX failed\n");
a5a0bca1 818 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
528f0c6b 819 goto exit;
8feceb67
VT
820 }
821
7bb45683 822 return;
528f0c6b 823exit:
249ee722 824 ieee80211_free_txskb(hw, skb);
f078f209
LR
825}
826
8feceb67 827static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 828{
9ac58615 829 struct ath_softc *sc = hw->priv;
af03abec 830 struct ath_hw *ah = sc->sc_ah;
c46917bb 831 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 832 bool prev_idle;
f078f209 833
ea22df29
SM
834 ath9k_deinit_channel_context(sc);
835
4c483817
S
836 mutex_lock(&sc->mutex);
837
9adcf440 838 ath_cancel_work(sc);
c94dbff7 839
eefa01dd 840 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 841 ath_dbg(common, ANY, "Device not present\n");
4c483817 842 mutex_unlock(&sc->mutex);
9c84b797
S
843 return;
844 }
8feceb67 845
3867cf6a
S
846 /* Ensure HW is awake when we try to shut it down. */
847 ath9k_ps_wakeup(sc);
848
6a6733f2
LR
849 spin_lock_bh(&sc->sc_pcu_lock);
850
203043f5
SG
851 /* prevent tasklets to enable interrupts once we disable them */
852 ah->imask &= ~ATH9K_INT_GLOBAL;
853
ff37e337
S
854 /* make sure h/w will not generate any interrupt
855 * before setting the invalid flag. */
4df3071e 856 ath9k_hw_disable_interrupts(ah);
ff37e337 857
c0c11741
FF
858 spin_unlock_bh(&sc->sc_pcu_lock);
859
860 /* we can now sync irq and kill any running tasklets, since we already
861 * disabled interrupts and not holding a spin lock */
862 synchronize_irq(sc->irq);
863 tasklet_kill(&sc->intr_tq);
864 tasklet_kill(&sc->bcon_tasklet);
865
866 prev_idle = sc->ps_idle;
867 sc->ps_idle = true;
868
869 spin_lock_bh(&sc->sc_pcu_lock);
870
871 if (ah->led_pin >= 0) {
872 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
873 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
874 }
875
9ebea382 876 ath_prepare_reset(sc);
ff37e337 877
0d95521e
FF
878 if (sc->rx.frag) {
879 dev_kfree_skb_any(sc->rx.frag);
880 sc->rx.frag = NULL;
881 }
882
c0c11741 883 if (!ah->curchan)
fbbcd146
FF
884 ah->curchan = ath9k_cmn_get_channel(hw, ah,
885 &sc->cur_chan->chandef);
6a6733f2 886
c0c11741
FF
887 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
888 ath9k_hw_phy_disable(ah);
6a6733f2 889
c0c11741 890 ath9k_hw_configpcipowersave(ah, true);
203043f5 891
c0c11741 892 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 893
c0c11741 894 ath9k_ps_restore(sc);
ff37e337 895
eefa01dd 896 set_bit(ATH_OP_INVALID, &common->op_flags);
c0c11741 897 sc->ps_idle = prev_idle;
500c064d 898
141b38b6
S
899 mutex_unlock(&sc->mutex);
900
d2182b69 901 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR
902}
903
c648ecb0 904static bool ath9k_uses_beacons(int type)
4801416c
BG
905{
906 switch (type) {
907 case NL80211_IFTYPE_AP:
908 case NL80211_IFTYPE_ADHOC:
909 case NL80211_IFTYPE_MESH_POINT:
910 return true;
911 default:
912 return false;
913 }
914}
915
4b93fd29
SM
916static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
917 u8 *mac, struct ieee80211_vif *vif)
4801416c 918{
cb35582a 919 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
4801416c
BG
920 int i;
921
ab11bb28 922 if (iter_data->has_hw_macaddr) {
4801416c
BG
923 for (i = 0; i < ETH_ALEN; i++)
924 iter_data->mask[i] &=
925 ~(iter_data->hw_macaddr[i] ^ mac[i]);
ab11bb28
FF
926 } else {
927 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
928 iter_data->has_hw_macaddr = true;
929 }
141b38b6 930
9a9c4fbc
RM
931 if (!vif->bss_conf.use_short_slot)
932 iter_data->slottime = ATH9K_SLOT_TIME_20;
933
1ed32e4f 934 switch (vif->type) {
4801416c
BG
935 case NL80211_IFTYPE_AP:
936 iter_data->naps++;
f078f209 937 break;
4801416c
BG
938 case NL80211_IFTYPE_STATION:
939 iter_data->nstations++;
cb35582a 940 if (avp->assoc && !iter_data->primary_sta)
9a9c4fbc 941 iter_data->primary_sta = vif;
e51f3eff 942 break;
05c914fe 943 case NL80211_IFTYPE_ADHOC:
4801416c 944 iter_data->nadhocs++;
9a9c4fbc
RM
945 if (vif->bss_conf.enable_beacon)
946 iter_data->beacons = true;
4801416c 947 break;
9cb5412b 948 case NL80211_IFTYPE_MESH_POINT:
4801416c 949 iter_data->nmeshes++;
9a9c4fbc
RM
950 if (vif->bss_conf.enable_beacon)
951 iter_data->beacons = true;
4801416c
BG
952 break;
953 case NL80211_IFTYPE_WDS:
954 iter_data->nwds++;
f078f209
LR
955 break;
956 default:
4801416c 957 break;
f078f209 958 }
4801416c 959}
f078f209 960
2ce73c02
SM
961static void ath9k_update_bssid_mask(struct ath_softc *sc,
962 struct ath_chanctx *ctx,
963 struct ath9k_vif_iter_data *iter_data)
964{
965 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
966 struct ath_vif *avp;
967 int i;
968
969 if (!ath9k_is_chanctx_enabled())
970 return;
971
972 list_for_each_entry(avp, &ctx->vifs, list) {
973 if (ctx->nvifs_assigned != 1)
974 continue;
975
976 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
977 continue;
978
979 ether_addr_copy(common->curbssid, avp->bssid);
980
981 /* perm_addr will be used as the p2p device address. */
982 for (i = 0; i < ETH_ALEN; i++)
983 iter_data->mask[i] &=
984 ~(iter_data->hw_macaddr[i] ^
985 sc->hw->wiphy->perm_addr[i]);
986 }
987}
988
4801416c 989/* Called with sc->mutex held. */
9a9c4fbc
RM
990void ath9k_calculate_iter_data(struct ath_softc *sc,
991 struct ath_chanctx *ctx,
4801416c
BG
992 struct ath9k_vif_iter_data *iter_data)
993{
9a9c4fbc 994 struct ath_vif *avp;
8feceb67 995
4801416c 996 /*
657eb17d
MV
997 * Pick the MAC address of the first interface as the new hardware
998 * MAC address. The hardware will use it together with the BSSID mask
999 * when matching addresses.
4801416c
BG
1000 */
1001 memset(iter_data, 0, sizeof(*iter_data));
4801416c 1002 memset(&iter_data->mask, 0xff, ETH_ALEN);
9a9c4fbc
RM
1003 iter_data->slottime = ATH9K_SLOT_TIME_9;
1004
1005 list_for_each_entry(avp, &ctx->vifs, list)
1006 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
2ce73c02
SM
1007
1008 ath9k_update_bssid_mask(sc, ctx, iter_data);
9a9c4fbc
RM
1009}
1010
1011static void ath9k_set_assoc_state(struct ath_softc *sc,
1012 struct ieee80211_vif *vif, bool changed)
1013{
1014 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cb35582a 1015 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
9a9c4fbc
RM
1016 unsigned long flags;
1017
1018 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
9a9c4fbc 1019
cb35582a
SM
1020 ether_addr_copy(common->curbssid, avp->bssid);
1021 common->curaid = avp->aid;
9a9c4fbc
RM
1022 ath9k_hw_write_associd(sc->sc_ah);
1023
1024 if (changed) {
1025 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1026 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
5640b08e 1027
9a9c4fbc
RM
1028 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1029 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1030 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1031 }
4801416c 1032
9a9c4fbc
RM
1033 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1034 ath9k_mci_update_wlan_channels(sc, false);
ab11bb28 1035
9a9c4fbc
RM
1036 ath_dbg(common, CONFIG,
1037 "Primary Station interface: %pM, BSSID: %pM\n",
1038 vif->addr, common->curbssid);
4801416c 1039}
8ca21f01 1040
4ee26de1
SM
1041#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1042static void ath9k_set_offchannel_state(struct ath_softc *sc)
1043{
1044 struct ath_hw *ah = sc->sc_ah;
1045 struct ath_common *common = ath9k_hw_common(ah);
1046 struct ieee80211_vif *vif = NULL;
1047
1048 ath9k_ps_wakeup(sc);
1049
1050 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1051 vif = sc->offchannel.scan_vif;
1052 else
1053 vif = sc->offchannel.roc_vif;
1054
1055 if (WARN_ON(!vif))
1056 goto exit;
1057
1058 eth_zero_addr(common->curbssid);
1059 eth_broadcast_addr(common->bssidmask);
62ae1aef 1060 memcpy(common->macaddr, vif->addr, ETH_ALEN);
4ee26de1
SM
1061 common->curaid = 0;
1062 ah->opmode = vif->type;
1063 ah->imask &= ~ATH9K_INT_SWBA;
1064 ah->imask &= ~ATH9K_INT_TSFOOR;
1065 ah->slottime = ATH9K_SLOT_TIME_9;
1066
1067 ath_hw_setbssidmask(common);
1068 ath9k_hw_setopmode(ah);
1069 ath9k_hw_write_associd(sc->sc_ah);
1070 ath9k_hw_set_interrupts(ah);
1071 ath9k_hw_init_global_settings(ah);
1072
1073exit:
1074 ath9k_ps_restore(sc);
1075}
1076#endif
1077
4801416c 1078/* Called with sc->mutex held. */
9a9c4fbc
RM
1079void ath9k_calculate_summary_state(struct ath_softc *sc,
1080 struct ath_chanctx *ctx)
4801416c 1081{
4801416c
BG
1082 struct ath_hw *ah = sc->sc_ah;
1083 struct ath_common *common = ath9k_hw_common(ah);
1084 struct ath9k_vif_iter_data iter_data;
9bf30ff9 1085 struct ath_beacon_config *cur_conf;
8ca21f01 1086
9a9c4fbc
RM
1087 ath_chanctx_check_active(sc, ctx);
1088
1089 if (ctx != sc->cur_chan)
1090 return;
1091
4ee26de1
SM
1092#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1093 if (ctx == &sc->offchannel.chan)
1094 return ath9k_set_offchannel_state(sc);
1095#endif
1096
9a9c4fbc
RM
1097 ath9k_ps_wakeup(sc);
1098 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1099
1100 if (iter_data.has_hw_macaddr)
62ae1aef 1101 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
2c3db3d5 1102
4801416c
BG
1103 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1104 ath_hw_setbssidmask(common);
1105
4801416c 1106 if (iter_data.naps > 0) {
9bf30ff9 1107 cur_conf = &ctx->beacon;
60ca9f87 1108 ath9k_hw_set_tsfadjust(ah, true);
4801416c 1109 ah->opmode = NL80211_IFTYPE_AP;
9bf30ff9
SM
1110 if (cur_conf->enable_beacon)
1111 iter_data.beacons = true;
4801416c 1112 } else {
60ca9f87 1113 ath9k_hw_set_tsfadjust(ah, false);
5640b08e 1114
fd5999cf
JC
1115 if (iter_data.nmeshes)
1116 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1117 else if (iter_data.nwds)
4801416c
BG
1118 ah->opmode = NL80211_IFTYPE_AP;
1119 else if (iter_data.nadhocs)
1120 ah->opmode = NL80211_IFTYPE_ADHOC;
1121 else
1122 ah->opmode = NL80211_IFTYPE_STATION;
1123 }
5640b08e 1124
df35d29e
SM
1125 ath9k_hw_setopmode(ah);
1126
748299f2 1127 ctx->switch_after_beacon = false;
198823fd 1128 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 1129 ah->imask |= ATH9K_INT_TSFOOR;
748299f2 1130 else {
4801416c 1131 ah->imask &= ~ATH9K_INT_TSFOOR;
748299f2
FF
1132 if (iter_data.naps == 1 && iter_data.beacons)
1133 ctx->switch_after_beacon = true;
1134 }
4af9cf4f 1135
9a9c4fbc
RM
1136 ah->imask &= ~ATH9K_INT_SWBA;
1137 if (ah->opmode == NL80211_IFTYPE_STATION) {
1138 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1139
9a9c4fbc 1140 if (iter_data.primary_sta) {
602607b6 1141 iter_data.beacons = true;
9a9c4fbc
RM
1142 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1143 changed);
1030f9fe 1144 ctx->primary_sta = iter_data.primary_sta;
9a9c4fbc
RM
1145 } else {
1146 ctx->primary_sta = NULL;
1147 memset(common->curbssid, 0, ETH_ALEN);
1148 common->curaid = 0;
1149 ath9k_hw_write_associd(sc->sc_ah);
1150 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1151 ath9k_mci_update_wlan_channels(sc, true);
1152 }
1153 } else if (iter_data.beacons) {
1154 ah->imask |= ATH9K_INT_SWBA;
1155 }
72d874c6 1156 ath9k_hw_set_interrupts(ah);
6dcc3444 1157
9a9c4fbc
RM
1158 if (iter_data.beacons)
1159 set_bit(ATH_OP_BEACONS, &common->op_flags);
1160 else
1161 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1162
1163 if (ah->slottime != iter_data.slottime) {
1164 ah->slottime = iter_data.slottime;
1165 ath9k_hw_init_global_settings(ah);
6dcc3444 1166 }
9a9c4fbc
RM
1167
1168 if (iter_data.primary_sta)
1169 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1170 else
1171 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1172
2ce73c02
SM
1173 ath_dbg(common, CONFIG,
1174 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1175 common->macaddr, common->curbssid, common->bssidmask);
1176
9a9c4fbc 1177 ath9k_ps_restore(sc);
4801416c 1178}
6f255425 1179
a4027644
SM
1180static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1181 struct ieee80211_vif *vif)
1182{
1183 int i;
1184
1185 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1186 vif->hw_queue[i] = i;
1187
1188 if (vif->type == NL80211_IFTYPE_AP)
1189 vif->cab_queue = hw->queues - 2;
1190 else
1191 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1192}
1193
4801416c
BG
1194static int ath9k_add_interface(struct ieee80211_hw *hw,
1195 struct ieee80211_vif *vif)
6b3b991d 1196{
9ac58615 1197 struct ath_softc *sc = hw->priv;
4801416c
BG
1198 struct ath_hw *ah = sc->sc_ah;
1199 struct ath_common *common = ath9k_hw_common(ah);
f89d1bc4
FF
1200 struct ath_vif *avp = (void *)vif->drv_priv;
1201 struct ath_node *an = &avp->mcast_node;
6b3b991d 1202
4801416c 1203 mutex_lock(&sc->mutex);
6b3b991d 1204
89f927af 1205 if (config_enabled(CONFIG_ATH9K_TX99)) {
ca529c93 1206 if (sc->cur_chan->nvifs >= 1) {
89f927af
LR
1207 mutex_unlock(&sc->mutex);
1208 return -EOPNOTSUPP;
1209 }
1210 sc->tx99_vif = vif;
1211 }
1212
d2182b69 1213 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
ca529c93 1214 sc->cur_chan->nvifs++;
4801416c 1215
130ef6e9
SM
1216 if (ath9k_uses_beacons(vif->type))
1217 ath9k_beacon_assign_slot(sc, vif);
1218
d463af4a 1219 avp->vif = vif;
499afacc 1220 if (!ath9k_is_chanctx_enabled()) {
39305635 1221 avp->chanctx = sc->cur_chan;
9a9c4fbc
RM
1222 list_add_tail(&avp->list, &avp->chanctx->vifs);
1223 }
a4027644
SM
1224
1225 ath9k_assign_hw_queues(hw, vif);
0453531e 1226
f89d1bc4
FF
1227 an->sc = sc;
1228 an->sta = NULL;
1229 an->vif = vif;
1230 an->no_ps_filter = true;
1231 ath_tx_node_init(sc, an);
1232
4801416c 1233 mutex_unlock(&sc->mutex);
327967cb 1234 return 0;
6b3b991d
RM
1235}
1236
1237static int ath9k_change_interface(struct ieee80211_hw *hw,
1238 struct ieee80211_vif *vif,
1239 enum nl80211_iftype new_type,
1240 bool p2p)
1241{
9ac58615 1242 struct ath_softc *sc = hw->priv;
6b3b991d 1243 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c083ce99 1244 struct ath_vif *avp = (void *)vif->drv_priv;
6b3b991d 1245
6b3b991d 1246 mutex_lock(&sc->mutex);
4801416c 1247
89f927af
LR
1248 if (config_enabled(CONFIG_ATH9K_TX99)) {
1249 mutex_unlock(&sc->mutex);
1250 return -EOPNOTSUPP;
1251 }
1252
1253 ath_dbg(common, CONFIG, "Change Interface\n");
1254
4801416c 1255 if (ath9k_uses_beacons(vif->type))
130ef6e9 1256 ath9k_beacon_remove_slot(sc, vif);
4801416c 1257
6b3b991d
RM
1258 vif->type = new_type;
1259 vif->p2p = p2p;
1260
130ef6e9
SM
1261 if (ath9k_uses_beacons(vif->type))
1262 ath9k_beacon_assign_slot(sc, vif);
9a9c4fbc 1263
a4027644 1264 ath9k_assign_hw_queues(hw, vif);
9a9c4fbc 1265 ath9k_calculate_summary_state(sc, avp->chanctx);
130ef6e9 1266
6b3b991d 1267 mutex_unlock(&sc->mutex);
327967cb 1268 return 0;
6b3b991d
RM
1269}
1270
8feceb67 1271static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1272 struct ieee80211_vif *vif)
f078f209 1273{
9ac58615 1274 struct ath_softc *sc = hw->priv;
c46917bb 1275 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f89d1bc4 1276 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1277
d2182b69 1278 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1279
141b38b6
S
1280 mutex_lock(&sc->mutex);
1281
c7dd40c9 1282 ath9k_p2p_remove_vif(sc, vif);
d463af4a 1283
ca529c93 1284 sc->cur_chan->nvifs--;
89f927af 1285 sc->tx99_vif = NULL;
499afacc 1286 if (!ath9k_is_chanctx_enabled())
9a9c4fbc 1287 list_del(&avp->list);
580f0b8a 1288
4801416c 1289 if (ath9k_uses_beacons(vif->type))
130ef6e9 1290 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1291
f89d1bc4
FF
1292 ath_tx_node_cleanup(sc, &avp->mcast_node);
1293
141b38b6 1294 mutex_unlock(&sc->mutex);
f078f209
LR
1295}
1296
fbab7390 1297static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1298{
3069168c 1299 struct ath_hw *ah = sc->sc_ah;
ad128860 1300 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1301
89f927af
LR
1302 if (config_enabled(CONFIG_ATH9K_TX99))
1303 return;
1304
3f7c5c10 1305 sc->ps_enabled = true;
3069168c
PR
1306 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1307 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1308 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1309 ath9k_hw_set_interrupts(ah);
3f7c5c10 1310 }
fdf76622 1311 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1312 }
ad128860 1313 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB
1314}
1315
845d708e
SB
1316static void ath9k_disable_ps(struct ath_softc *sc)
1317{
1318 struct ath_hw *ah = sc->sc_ah;
ad128860 1319 struct ath_common *common = ath9k_hw_common(ah);
845d708e 1320
89f927af
LR
1321 if (config_enabled(CONFIG_ATH9K_TX99))
1322 return;
1323
845d708e
SB
1324 sc->ps_enabled = false;
1325 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1326 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1327 ath9k_hw_setrxabort(ah, 0);
1328 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1329 PS_WAIT_FOR_CAB |
1330 PS_WAIT_FOR_PSPOLL_DATA |
1331 PS_WAIT_FOR_TX_ACK);
1332 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1333 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1334 ath9k_hw_set_interrupts(ah);
845d708e
SB
1335 }
1336 }
ad128860 1337 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB
1338}
1339
e8975581 1340static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1341{
9ac58615 1342 struct ath_softc *sc = hw->priv;
3430098a
FF
1343 struct ath_hw *ah = sc->sc_ah;
1344 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1345 struct ieee80211_conf *conf = &hw->conf;
fbbcd146 1346 struct ath_chanctx *ctx = sc->cur_chan;
f078f209 1347
c0c11741 1348 ath9k_ps_wakeup(sc);
aa33de09 1349 mutex_lock(&sc->mutex);
141b38b6 1350
daa1b6ee 1351 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1352 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1353 if (sc->ps_idle) {
daa1b6ee 1354 ath_cancel_work(sc);
b73f3e78
RM
1355 ath9k_stop_btcoex(sc);
1356 } else {
1357 ath9k_start_btcoex(sc);
75600abf
FF
1358 /*
1359 * The chip needs a reset to properly wake up from
1360 * full sleep
1361 */
39305635 1362 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
b73f3e78 1363 }
daa1b6ee 1364 }
64839170 1365
e7824a50
LR
1366 /*
1367 * We just prepare to enable PS. We have to wait until our AP has
1368 * ACK'd our null data frame to disable RX otherwise we'll ignore
1369 * those ACKs and end up retransmitting the same null data frames.
1370 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1371 */
3cbb5dd7 1372 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1373 unsigned long flags;
1374 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB
1375 if (conf->flags & IEEE80211_CONF_PS)
1376 ath9k_enable_ps(sc);
845d708e
SB
1377 else
1378 ath9k_disable_ps(sc);
8ab2cd09 1379 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1380 }
1381
199afd9d
S
1382 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1383 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1384 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM
1385 sc->sc_ah->is_monitoring = true;
1386 } else {
d2182b69 1387 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1388 sc->sc_ah->is_monitoring = false;
199afd9d
S
1389 }
1390 }
1391
499afacc 1392 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
fbbcd146 1393 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
bff11766 1394 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
094d05dc 1395 }
f078f209 1396
c9f6a656 1397 if (changed & IEEE80211_CONF_CHANGE_POWER) {
d2182b69 1398 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
bc7e1be7 1399 sc->cur_chan->txpower = 2 * conf->power_level;
d385c5c2
FF
1400 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
1401 sc->cur_chan->txpower,
1402 &sc->cur_chan->cur_txpower);
64839170
LR
1403 }
1404
aa33de09 1405 mutex_unlock(&sc->mutex);
c0c11741 1406 ath9k_ps_restore(sc);
141b38b6 1407
f078f209
LR
1408 return 0;
1409}
1410
8feceb67
VT
1411#define SUPPORTED_FILTERS \
1412 (FIF_PROMISC_IN_BSS | \
1413 FIF_ALLMULTI | \
1414 FIF_CONTROL | \
af6a3fc7 1415 FIF_PSPOLL | \
8feceb67
VT
1416 FIF_OTHER_BSS | \
1417 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1418 FIF_PROBE_REQ | \
8feceb67 1419 FIF_FCSFAIL)
c83be688 1420
8feceb67
VT
1421/* FIXME: sc->sc_full_reset ? */
1422static void ath9k_configure_filter(struct ieee80211_hw *hw,
1423 unsigned int changed_flags,
1424 unsigned int *total_flags,
3ac64bee 1425 u64 multicast)
8feceb67 1426{
9ac58615 1427 struct ath_softc *sc = hw->priv;
8feceb67 1428 u32 rfilt;
f078f209 1429
8feceb67
VT
1430 changed_flags &= SUPPORTED_FILTERS;
1431 *total_flags &= SUPPORTED_FILTERS;
f078f209 1432
fce34430
SM
1433 spin_lock_bh(&sc->chan_lock);
1434 sc->cur_chan->rxfilter = *total_flags;
1435 spin_unlock_bh(&sc->chan_lock);
1436
aa68aeaa 1437 ath9k_ps_wakeup(sc);
8feceb67
VT
1438 rfilt = ath_calcrxfilter(sc);
1439 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1440 ath9k_ps_restore(sc);
f078f209 1441
d2182b69
JP
1442 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1443 rfilt);
8feceb67 1444}
f078f209 1445
4ca77860
JB
1446static int ath9k_sta_add(struct ieee80211_hw *hw,
1447 struct ieee80211_vif *vif,
1448 struct ieee80211_sta *sta)
8feceb67 1449{
9ac58615 1450 struct ath_softc *sc = hw->priv;
93ae2dd2
FF
1451 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1452 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1453 struct ieee80211_key_conf ps_key = { };
4ef69d03 1454 int key;
f078f209 1455
7e1e3864 1456 ath_node_attach(sc, sta, vif);
f59a59fe
FF
1457
1458 if (vif->type != NL80211_IFTYPE_AP &&
1459 vif->type != NL80211_IFTYPE_AP_VLAN)
1460 return 0;
1461
4ef69d03 1462 key = ath_key_config(common, vif, sta, &ps_key);
4bbf4414 1463 if (key > 0) {
4ef69d03 1464 an->ps_key = key;
4bbf4414
RM
1465 an->key_idx[0] = key;
1466 }
4ca77860
JB
1467
1468 return 0;
1469}
1470
93ae2dd2
FF
1471static void ath9k_del_ps_key(struct ath_softc *sc,
1472 struct ieee80211_vif *vif,
1473 struct ieee80211_sta *sta)
1474{
1475 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1476 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1477 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1478
1479 if (!an->ps_key)
1480 return;
1481
1482 ath_key_delete(common, &ps_key);
4ef69d03 1483 an->ps_key = 0;
4bbf4414 1484 an->key_idx[0] = 0;
93ae2dd2
FF
1485}
1486
4ca77860
JB
1487static int ath9k_sta_remove(struct ieee80211_hw *hw,
1488 struct ieee80211_vif *vif,
1489 struct ieee80211_sta *sta)
1490{
9ac58615 1491 struct ath_softc *sc = hw->priv;
4ca77860 1492
93ae2dd2 1493 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB
1494 ath_node_detach(sc, sta);
1495
1496 return 0;
f078f209
LR
1497}
1498
df3c6eb3
SM
1499static int ath9k_sta_state(struct ieee80211_hw *hw,
1500 struct ieee80211_vif *vif,
1501 struct ieee80211_sta *sta,
1502 enum ieee80211_sta_state old_state,
1503 enum ieee80211_sta_state new_state)
1504{
1505 struct ath_softc *sc = hw->priv;
1506 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1507 int ret = 0;
1508
1509 if (old_state == IEEE80211_STA_AUTH &&
1510 new_state == IEEE80211_STA_ASSOC) {
1511 ret = ath9k_sta_add(hw, vif, sta);
1512 ath_dbg(common, CONFIG,
1513 "Add station: %pM\n", sta->addr);
1514 } else if (old_state == IEEE80211_STA_ASSOC &&
1515 new_state == IEEE80211_STA_AUTH) {
1516 ret = ath9k_sta_remove(hw, vif, sta);
1517 ath_dbg(common, CONFIG,
1518 "Remove station: %pM\n", sta->addr);
1519 }
1520
b8f9279b 1521 if (ath9k_is_chanctx_enabled()) {
91e6ceb3
SM
1522 if (vif->type == NL80211_IFTYPE_STATION) {
1523 if (old_state == IEEE80211_STA_ASSOC &&
1524 new_state == IEEE80211_STA_AUTHORIZED)
1525 ath_chanctx_event(sc, vif,
1526 ATH_CHANCTX_EVENT_AUTHORIZED);
1527 }
b8f9279b
SM
1528 }
1529
df3c6eb3
SM
1530 return ret;
1531}
1532
4bbf4414
RM
1533static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1534 struct ath_node *an,
1535 bool set)
1536{
1537 int i;
1538
1539 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1540 if (!an->key_idx[i])
1541 continue;
1542 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1543 }
1544}
1545
5519541d
FF
1546static void ath9k_sta_notify(struct ieee80211_hw *hw,
1547 struct ieee80211_vif *vif,
1548 enum sta_notify_cmd cmd,
1549 struct ieee80211_sta *sta)
1550{
1551 struct ath_softc *sc = hw->priv;
1552 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1553
1554 switch (cmd) {
1555 case STA_NOTIFY_SLEEP:
1556 an->sleeping = true;
042ec453 1557 ath_tx_aggr_sleep(sta, sc, an);
4bbf4414 1558 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
5519541d
FF
1559 break;
1560 case STA_NOTIFY_AWAKE:
4bbf4414 1561 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
5519541d
FF
1562 an->sleeping = false;
1563 ath_tx_aggr_wakeup(sc, an);
1564 break;
1565 }
1566}
1567
8a3a3c85
EP
1568static int ath9k_conf_tx(struct ieee80211_hw *hw,
1569 struct ieee80211_vif *vif, u16 queue,
8feceb67 1570 const struct ieee80211_tx_queue_params *params)
f078f209 1571{
9ac58615 1572 struct ath_softc *sc = hw->priv;
c46917bb 1573 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1574 struct ath_txq *txq;
8feceb67 1575 struct ath9k_tx_queue_info qi;
066dae93 1576 int ret = 0;
f078f209 1577
bea843c7 1578 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1579 return 0;
f078f209 1580
066dae93
FF
1581 txq = sc->tx.txq_map[queue];
1582
96f372c9 1583 ath9k_ps_wakeup(sc);
141b38b6
S
1584 mutex_lock(&sc->mutex);
1585
1ffb0610
S
1586 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1587
8feceb67
VT
1588 qi.tqi_aifs = params->aifs;
1589 qi.tqi_cwmin = params->cw_min;
1590 qi.tqi_cwmax = params->cw_max;
531bd079 1591 qi.tqi_burstTime = params->txop * 32;
f078f209 1592
d2182b69 1593 ath_dbg(common, CONFIG,
226afe68
JP
1594 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1595 queue, txq->axq_qnum, params->aifs, params->cw_min,
1596 params->cw_max, params->txop);
f078f209 1597
aa5955c3 1598 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1599 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1600 if (ret)
3800276a 1601 ath_err(common, "TXQ Update failed\n");
f078f209 1602
141b38b6 1603 mutex_unlock(&sc->mutex);
96f372c9 1604 ath9k_ps_restore(sc);
141b38b6 1605
8feceb67
VT
1606 return ret;
1607}
f078f209 1608
8feceb67
VT
1609static int ath9k_set_key(struct ieee80211_hw *hw,
1610 enum set_key_cmd cmd,
dc822b5d
JB
1611 struct ieee80211_vif *vif,
1612 struct ieee80211_sta *sta,
8feceb67
VT
1613 struct ieee80211_key_conf *key)
1614{
9ac58615 1615 struct ath_softc *sc = hw->priv;
c46917bb 1616 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4bbf4414
RM
1617 struct ath_node *an = NULL;
1618 int ret = 0, i;
f078f209 1619
3e6109c5 1620 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM
1621 return -ENOSPC;
1622
5bd5e9a6
CYY
1623 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1624 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM
1625 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1626 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1627 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1628 /*
1629 * For now, disable hw crypto for the RSN IBSS group keys. This
1630 * could be optimized in the future to use a modified key cache
1631 * design to support per-STA RX GTK, but until that gets
1632 * implemented, use of software crypto for group addressed
1633 * frames is a acceptable to allow RSN IBSS to be used.
1634 */
1635 return -EOPNOTSUPP;
1636 }
1637
141b38b6 1638 mutex_lock(&sc->mutex);
3cbb5dd7 1639 ath9k_ps_wakeup(sc);
4bbf4414
RM
1640 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1641 if (sta)
1642 an = (struct ath_node *)sta->drv_priv;
f078f209 1643
8feceb67
VT
1644 switch (cmd) {
1645 case SET_KEY:
93ae2dd2
FF
1646 if (sta)
1647 ath9k_del_ps_key(sc, vif, sta);
1648
4bbf4414 1649 key->hw_key_idx = 0;
040e539e 1650 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1651 if (ret >= 0) {
1652 key->hw_key_idx = ret;
8feceb67
VT
1653 /* push IV and Michael MIC generation to stack */
1654 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1655 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1656 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1657 if (sc->sc_ah->sw_mgmt_crypto &&
1658 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1659 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1660 ret = 0;
8feceb67 1661 }
4bbf4414
RM
1662 if (an && key->hw_key_idx) {
1663 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1664 if (an->key_idx[i])
1665 continue;
1666 an->key_idx[i] = key->hw_key_idx;
1667 break;
1668 }
1669 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1670 }
8feceb67
VT
1671 break;
1672 case DISABLE_KEY:
040e539e 1673 ath_key_delete(common, key);
4bbf4414
RM
1674 if (an) {
1675 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1676 if (an->key_idx[i] != key->hw_key_idx)
1677 continue;
1678 an->key_idx[i] = 0;
1679 break;
1680 }
1681 }
1682 key->hw_key_idx = 0;
8feceb67
VT
1683 break;
1684 default:
1685 ret = -EINVAL;
1686 }
f078f209 1687
3cbb5dd7 1688 ath9k_ps_restore(sc);
141b38b6
S
1689 mutex_unlock(&sc->mutex);
1690
8feceb67
VT
1691 return ret;
1692}
6c43c090 1693
8feceb67
VT
1694static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1695 struct ieee80211_vif *vif,
1696 struct ieee80211_bss_conf *bss_conf,
1697 u32 changed)
1698{
da0d45f7
SM
1699#define CHECK_ANI \
1700 (BSS_CHANGED_ASSOC | \
1701 BSS_CHANGED_IBSS | \
1702 BSS_CHANGED_BEACON_ENABLED)
1703
9ac58615 1704 struct ath_softc *sc = hw->priv;
2d0ddec5 1705 struct ath_hw *ah = sc->sc_ah;
1510718d 1706 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1707 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1708 int slottime;
f078f209 1709
96f372c9 1710 ath9k_ps_wakeup(sc);
141b38b6
S
1711 mutex_lock(&sc->mutex);
1712
9f61903c 1713 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM
1714 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1715 bss_conf->bssid, bss_conf->assoc);
1716
62ae1aef 1717 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
cb35582a
SM
1718 avp->aid = bss_conf->aid;
1719 avp->assoc = bss_conf->assoc;
1720
9a9c4fbc 1721 ath9k_calculate_summary_state(sc, avp->chanctx);
c6089ccc 1722 }
2d0ddec5 1723
2e5ef459 1724 if (changed & BSS_CHANGED_IBSS) {
2e5ef459
RM
1725 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1726 common->curaid = bss_conf->aid;
1727 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM
1728 }
1729
ef4ad633 1730 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
9198cf4a
RM
1731 (changed & BSS_CHANGED_BEACON_INT) ||
1732 (changed & BSS_CHANGED_BEACON_INFO)) {
9bf30ff9 1733 ath9k_beacon_config(sc, vif, changed);
9a9c4fbc
RM
1734 if (changed & BSS_CHANGED_BEACON_ENABLED)
1735 ath9k_calculate_summary_state(sc, avp->chanctx);
9a9c4fbc 1736 }
0005baf4 1737
9a9c4fbc
RM
1738 if ((avp->chanctx == sc->cur_chan) &&
1739 (changed & BSS_CHANGED_ERP_SLOT)) {
0005baf4
FF
1740 if (bss_conf->use_short_slot)
1741 slottime = 9;
1742 else
1743 slottime = 20;
1744 if (vif->type == NL80211_IFTYPE_AP) {
1745 /*
1746 * Defer update, so that connected stations can adjust
1747 * their settings at the same time.
1748 * See beacon.c for more details
1749 */
1750 sc->beacon.slottime = slottime;
1751 sc->beacon.updateslot = UPDATE;
1752 } else {
1753 ah->slottime = slottime;
1754 ath9k_hw_init_global_settings(ah);
1755 }
2d0ddec5
JB
1756 }
1757
c7dd40c9
SM
1758 if (changed & BSS_CHANGED_P2P_PS)
1759 ath9k_p2p_bss_info_changed(sc, vif);
d463af4a 1760
da0d45f7
SM
1761 if (changed & CHECK_ANI)
1762 ath_check_ani(sc);
1763
141b38b6 1764 mutex_unlock(&sc->mutex);
96f372c9 1765 ath9k_ps_restore(sc);
da0d45f7
SM
1766
1767#undef CHECK_ANI
8feceb67 1768}
f078f209 1769
37a41b4a 1770static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1771{
9ac58615 1772 struct ath_softc *sc = hw->priv;
8feceb67 1773 u64 tsf;
f078f209 1774
141b38b6 1775 mutex_lock(&sc->mutex);
9abbfb27 1776 ath9k_ps_wakeup(sc);
141b38b6 1777 tsf = ath9k_hw_gettsf64(sc->sc_ah);
9abbfb27 1778 ath9k_ps_restore(sc);
141b38b6 1779 mutex_unlock(&sc->mutex);
f078f209 1780
8feceb67
VT
1781 return tsf;
1782}
f078f209 1783
37a41b4a
EP
1784static void ath9k_set_tsf(struct ieee80211_hw *hw,
1785 struct ieee80211_vif *vif,
1786 u64 tsf)
3b5d665b 1787{
9ac58615 1788 struct ath_softc *sc = hw->priv;
3b5d665b 1789
141b38b6 1790 mutex_lock(&sc->mutex);
9abbfb27 1791 ath9k_ps_wakeup(sc);
141b38b6 1792 ath9k_hw_settsf64(sc->sc_ah, tsf);
9abbfb27 1793 ath9k_ps_restore(sc);
141b38b6 1794 mutex_unlock(&sc->mutex);
3b5d665b
AF
1795}
1796
37a41b4a 1797static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1798{
9ac58615 1799 struct ath_softc *sc = hw->priv;
c83be688 1800
141b38b6 1801 mutex_lock(&sc->mutex);
21526d57
LR
1802
1803 ath9k_ps_wakeup(sc);
141b38b6 1804 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1805 ath9k_ps_restore(sc);
1806
141b38b6 1807 mutex_unlock(&sc->mutex);
8feceb67 1808}
f078f209 1809
8feceb67 1810static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1811 struct ieee80211_vif *vif,
141b38b6
S
1812 enum ieee80211_ampdu_mlme_action action,
1813 struct ieee80211_sta *sta,
0b01f030 1814 u16 tid, u16 *ssn, u8 buf_size)
8feceb67 1815{
9ac58615 1816 struct ath_softc *sc = hw->priv;
1e929d3e 1817 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
16e23428 1818 bool flush = false;
8feceb67 1819 int ret = 0;
f078f209 1820
7ca7c776 1821 mutex_lock(&sc->mutex);
85ad181e 1822
8feceb67
VT
1823 switch (action) {
1824 case IEEE80211_AMPDU_RX_START:
8feceb67
VT
1825 break;
1826 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1827 break;
1828 case IEEE80211_AMPDU_TX_START:
1e929d3e
SM
1829 if (ath9k_is_chanctx_enabled()) {
1830 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1831 ret = -EBUSY;
1832 break;
1833 }
1834 }
8b685ba9 1835 ath9k_ps_wakeup(sc);
231c3a1f
FF
1836 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1837 if (!ret)
1838 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1839 ath9k_ps_restore(sc);
8feceb67 1840 break;
18b559d5
JB
1841 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1842 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
16e23428
FF
1843 flush = true;
1844 case IEEE80211_AMPDU_TX_STOP_CONT:
8b685ba9 1845 ath9k_ps_wakeup(sc);
f83da965 1846 ath_tx_aggr_stop(sc, sta, tid);
08c96abd 1847 if (!flush)
16e23428 1848 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1849 ath9k_ps_restore(sc);
8feceb67 1850 break;
b1720231 1851 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1852 ath9k_ps_wakeup(sc);
8469cdef 1853 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1854 ath9k_ps_restore(sc);
8469cdef 1855 break;
8feceb67 1856 default:
3800276a 1857 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT
1858 }
1859
7ca7c776 1860 mutex_unlock(&sc->mutex);
85ad181e 1861
8feceb67 1862 return ret;
f078f209
LR
1863}
1864
62dad5b0
BP
1865static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1866 struct survey_info *survey)
1867{
9ac58615 1868 struct ath_softc *sc = hw->priv;
3430098a 1869 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 1870 struct ieee80211_supported_band *sband;
3430098a 1871 struct ieee80211_channel *chan;
3430098a
FF
1872 int pos;
1873
89f927af
LR
1874 if (config_enabled(CONFIG_ATH9K_TX99))
1875 return -EOPNOTSUPP;
1876
b7cc9b97 1877 spin_lock_bh(&common->cc_lock);
3430098a
FF
1878 if (idx == 0)
1879 ath_update_survey_stats(sc);
39162dbe
FF
1880
1881 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1882 if (sband && idx >= sband->n_channels) {
1883 idx -= sband->n_channels;
1884 sband = NULL;
1885 }
62dad5b0 1886
39162dbe
FF
1887 if (!sband)
1888 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
62dad5b0 1889
3430098a 1890 if (!sband || idx >= sband->n_channels) {
b7cc9b97 1891 spin_unlock_bh(&common->cc_lock);
3430098a 1892 return -ENOENT;
4f1a5a4b 1893 }
62dad5b0 1894
3430098a
FF
1895 chan = &sband->channels[idx];
1896 pos = chan->hw_value;
1897 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1898 survey->channel = chan;
b7cc9b97 1899 spin_unlock_bh(&common->cc_lock);
3430098a 1900
62dad5b0
BP
1901 return 0;
1902}
1903
24a1936b
LB
1904static void ath9k_enable_dynack(struct ath_softc *sc)
1905{
1906#ifdef CONFIG_ATH9K_DYNACK
1907 u32 rfilt;
1908 struct ath_hw *ah = sc->sc_ah;
1909
1910 ath_dynack_reset(ah);
1911
1912 ah->dynack.enabled = true;
1913 rfilt = ath_calcrxfilter(sc);
1914 ath9k_hw_setrxfilter(ah, rfilt);
1915#endif
1916}
1917
a4bcaf55
LB
1918static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1919 s16 coverage_class)
e239d859 1920{
9ac58615 1921 struct ath_softc *sc = hw->priv;
e239d859
FF
1922 struct ath_hw *ah = sc->sc_ah;
1923
89f927af
LR
1924 if (config_enabled(CONFIG_ATH9K_TX99))
1925 return;
1926
e239d859 1927 mutex_lock(&sc->mutex);
8b2a3827 1928
24a1936b
LB
1929 if (coverage_class >= 0) {
1930 ah->coverage_class = coverage_class;
1931 if (ah->dynack.enabled) {
1932 u32 rfilt;
1933
1934 ah->dynack.enabled = false;
1935 rfilt = ath_calcrxfilter(sc);
1936 ath9k_hw_setrxfilter(ah, rfilt);
1937 }
1938 ath9k_ps_wakeup(sc);
1939 ath9k_hw_init_global_settings(ah);
1940 ath9k_ps_restore(sc);
1941 } else if (!ah->dynack.enabled) {
1942 ath9k_enable_dynack(sc);
1943 }
8b2a3827 1944
e239d859
FF
1945 mutex_unlock(&sc->mutex);
1946}
1947
e2d389b5
SM
1948static bool ath9k_has_tx_pending(struct ath_softc *sc,
1949 bool sw_pending)
10e23181 1950{
f7838073 1951 int i, npend = 0;
10e23181
FF
1952
1953 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1954 if (!ATH_TXQ_SETUP(sc, i))
1955 continue;
1956
e2d389b5
SM
1957 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
1958 sw_pending);
10e23181
FF
1959 if (npend)
1960 break;
1961 }
1962
1963 return !!npend;
1964}
1965
77be2c54
EG
1966static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1967 u32 queues, bool drop)
bff11766
FF
1968{
1969 struct ath_softc *sc = hw->priv;
25f3bc7d
SM
1970 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1971
1972 if (ath9k_is_chanctx_enabled()) {
1973 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
1974 goto flush;
bff11766 1975
25f3bc7d
SM
1976 /*
1977 * If MCC is active, extend the flush timeout
1978 * and wait for the HW/SW queues to become
1979 * empty. This needs to be done outside the
1980 * sc->mutex lock to allow the channel scheduler
1981 * to switch channel contexts.
1982 *
1983 * The vif queues have been stopped in mac80211,
1984 * so there won't be any incoming frames.
1985 */
1986 __ath9k_flush(hw, queues, drop, true, true);
1987 return;
1988 }
1989flush:
bff11766 1990 mutex_lock(&sc->mutex);
25f3bc7d 1991 __ath9k_flush(hw, queues, drop, true, false);
bff11766
FF
1992 mutex_unlock(&sc->mutex);
1993}
1994
e2d389b5 1995void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
25f3bc7d 1996 bool sw_pending, bool timeout_override)
69081624 1997{
69081624 1998 struct ath_softc *sc = hw->priv;
99aa55b6
MSS
1999 struct ath_hw *ah = sc->sc_ah;
2000 struct ath_common *common = ath9k_hw_common(ah);
2fae0d9f 2001 int timeout;
2f6fc351 2002 bool drain_txq;
69081624 2003
69081624
VT
2004 cancel_delayed_work_sync(&sc->tx_complete_work);
2005
6a6b3f3e 2006 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 2007 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS
2008 return;
2009 }
2010
eefa01dd 2011 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 2012 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS
2013 return;
2014 }
2015
2fae0d9f 2016 spin_lock_bh(&sc->chan_lock);
25f3bc7d
SM
2017 if (timeout_override)
2018 timeout = HZ / 5;
2019 else
2020 timeout = sc->cur_chan->flush_timeout;
2fae0d9f
SM
2021 spin_unlock_bh(&sc->chan_lock);
2022
2023 ath_dbg(common, CHAN_CTX,
2024 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2025
e2d389b5 2026 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
10e23181
FF
2027 timeout) > 0)
2028 drop = false;
69081624 2029
9df0d6a2
FF
2030 if (drop) {
2031 ath9k_ps_wakeup(sc);
2032 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 2033 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 2034 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 2035
9df0d6a2 2036 if (!drain_txq)
5555c955 2037 ath_reset(sc, NULL);
9adcf440 2038
9df0d6a2 2039 ath9k_ps_restore(sc);
9df0d6a2 2040 }
d78f4b3e 2041
69081624 2042 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
69081624
VT
2043}
2044
15b91e83
VN
2045static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2046{
2047 struct ath_softc *sc = hw->priv;
15b91e83 2048
e2d389b5 2049 return ath9k_has_tx_pending(sc, true);
15b91e83
VN
2050}
2051
5595f119 2052static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF
2053{
2054 struct ath_softc *sc = hw->priv;
2055 struct ath_hw *ah = sc->sc_ah;
2056 struct ieee80211_vif *vif;
2057 struct ath_vif *avp;
2058 struct ath_buf *bf;
2059 struct ath_tx_status ts;
4286df60 2060 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF
2061 int status;
2062
2063 vif = sc->beacon.bslot[0];
2064 if (!vif)
2065 return 0;
2066
aa45fe96 2067 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF
2068 return 0;
2069
aa45fe96
SM
2070 avp = (void *)vif->drv_priv;
2071
4286df60 2072 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF
2073 tasklet_disable(&sc->bcon_tasklet);
2074
2075 bf = avp->av_bcbuf;
2076 if (!bf || !bf->bf_mpdu)
2077 goto skip;
2078
2079 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2080 if (status == -EINPROGRESS)
2081 goto skip;
2082
2083 sc->beacon.tx_processed = true;
2084 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2085
2086skip:
2087 tasklet_enable(&sc->bcon_tasklet);
2088 }
2089
2090 return sc->beacon.tx_last;
2091}
2092
52c94f41
MSS
2093static int ath9k_get_stats(struct ieee80211_hw *hw,
2094 struct ieee80211_low_level_stats *stats)
2095{
2096 struct ath_softc *sc = hw->priv;
2097 struct ath_hw *ah = sc->sc_ah;
2098 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2099
2100 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2101 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2102 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2103 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2104 return 0;
2105}
2106
43c35284
FF
2107static u32 fill_chainmask(u32 cap, u32 new)
2108{
2109 u32 filled = 0;
2110 int i;
2111
2112 for (i = 0; cap && new; i++, cap >>= 1) {
2113 if (!(cap & BIT(0)))
2114 continue;
2115
2116 if (new & BIT(0))
2117 filled |= BIT(i);
2118
2119 new >>= 1;
2120 }
2121
2122 return filled;
2123}
2124
5d9c7e3c
FF
2125static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2126{
fea92cbf
FF
2127 if (AR_SREV_9300_20_OR_LATER(ah))
2128 return true;
2129
5d9c7e3c
FF
2130 switch (val & 0x7) {
2131 case 0x1:
2132 case 0x3:
2133 case 0x7:
2134 return true;
2135 case 0x2:
2136 return (ah->caps.rx_chainmask == 1);
2137 default:
2138 return false;
2139 }
2140}
2141
43c35284
FF
2142static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2143{
2144 struct ath_softc *sc = hw->priv;
2145 struct ath_hw *ah = sc->sc_ah;
2146
5d9c7e3c
FF
2147 if (ah->caps.rx_chainmask != 1)
2148 rx_ant |= tx_ant;
2149
2150 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF
2151 return -EINVAL;
2152
2153 sc->ant_rx = rx_ant;
2154 sc->ant_tx = tx_ant;
2155
2156 if (ah->caps.rx_chainmask == 1)
2157 return 0;
2158
2159 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2160 if (AR_SREV_9100(ah))
2161 ah->rxchainmask = 0x7;
2162 else
2163 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2164
2165 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
b57ba3b2 2166 ath9k_cmn_reload_chainmask(ah);
43c35284
FF
2167
2168 return 0;
2169}
2170
2171static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2172{
2173 struct ath_softc *sc = hw->priv;
2174
2175 *tx_ant = sc->ant_tx;
2176 *rx_ant = sc->ant_rx;
2177 return 0;
2178}
2179
e93d083f
SW
2180static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2181{
2182 struct ath_softc *sc = hw->priv;
eefa01dd
OR
2183 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2184 set_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f
SW
2185}
2186
2187static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2188{
2189 struct ath_softc *sc = hw->priv;
eefa01dd
OR
2190 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2191 clear_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f 2192}
b11e640a 2193
499afacc
SM
2194#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2195
78b21949 2196static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
855df36d 2197 struct ieee80211_scan_request *hw_req)
78b21949 2198{
855df36d 2199 struct cfg80211_scan_request *req = &hw_req->req;
78b21949
FF
2200 struct ath_softc *sc = hw->priv;
2201 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2202 int ret = 0;
2203
2204 mutex_lock(&sc->mutex);
2205
2206 if (WARN_ON(sc->offchannel.scan_req)) {
2207 ret = -EBUSY;
2208 goto out;
2209 }
2210
2211 ath9k_ps_wakeup(sc);
2212 set_bit(ATH_OP_SCANNING, &common->op_flags);
2213 sc->offchannel.scan_vif = vif;
2214 sc->offchannel.scan_req = req;
2215 sc->offchannel.scan_idx = 0;
78b21949 2216
bc81d43a
SM
2217 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2218 vif->addr);
2219
2220 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2221 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
405393cf 2222 ath_offchannel_next(sc);
bc81d43a 2223 }
78b21949
FF
2224
2225out:
2226 mutex_unlock(&sc->mutex);
2227
2228 return ret;
2229}
2230
2231static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2232 struct ieee80211_vif *vif)
2233{
2234 struct ath_softc *sc = hw->priv;
bc81d43a
SM
2235 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2236
2237 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
78b21949
FF
2238
2239 mutex_lock(&sc->mutex);
2240 del_timer_sync(&sc->offchannel.timer);
2241 ath_scan_complete(sc, true);
2242 mutex_unlock(&sc->mutex);
2243}
2244
405393cf
FF
2245static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2246 struct ieee80211_vif *vif,
2247 struct ieee80211_channel *chan, int duration,
2248 enum ieee80211_roc_type type)
2249{
2250 struct ath_softc *sc = hw->priv;
bc81d43a 2251 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF
2252 int ret = 0;
2253
2254 mutex_lock(&sc->mutex);
2255
2256 if (WARN_ON(sc->offchannel.roc_vif)) {
2257 ret = -EBUSY;
2258 goto out;
2259 }
2260
2261 ath9k_ps_wakeup(sc);
2262 sc->offchannel.roc_vif = vif;
2263 sc->offchannel.roc_chan = chan;
2264 sc->offchannel.roc_duration = duration;
2265
bc81d43a
SM
2266 ath_dbg(common, CHAN_CTX,
2267 "RoC request on vif: %pM, type: %d duration: %d\n",
2268 vif->addr, type, duration);
2269
2270 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2271 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
405393cf 2272 ath_offchannel_next(sc);
bc81d43a 2273 }
405393cf
FF
2274
2275out:
2276 mutex_unlock(&sc->mutex);
2277
2278 return ret;
2279}
2280
2281static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2282{
2283 struct ath_softc *sc = hw->priv;
bc81d43a 2284 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF
2285
2286 mutex_lock(&sc->mutex);
2287
bc81d43a 2288 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
405393cf
FF
2289 del_timer_sync(&sc->offchannel.timer);
2290
2291 if (sc->offchannel.roc_vif) {
2292 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2293 ath_roc_complete(sc, true);
2294 }
2295
2296 mutex_unlock(&sc->mutex);
2297
2298 return 0;
2299}
2300
39305635
FF
2301static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2302 struct ieee80211_chanctx_conf *conf)
2303{
2304 struct ath_softc *sc = hw->priv;
bc81d43a 2305 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635 2306 struct ath_chanctx *ctx, **ptr;
3ad9c386 2307 int pos;
39305635
FF
2308
2309 mutex_lock(&sc->mutex);
c4dc0d04
RM
2310
2311 ath_for_each_chanctx(sc, ctx) {
2312 if (ctx->assigned)
2313 continue;
2314
2315 ptr = (void *) conf->drv_priv;
2316 *ptr = ctx;
2317 ctx->assigned = true;
3ad9c386
RM
2318 pos = ctx - &sc->chanctx[0];
2319 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
bc81d43a
SM
2320
2321 ath_dbg(common, CHAN_CTX,
2322 "Add channel context: %d MHz\n",
2323 conf->def.chan->center_freq);
2324
c4dc0d04 2325 ath_chanctx_set_channel(sc, ctx, &conf->def);
4c7e9aee 2326
39305635 2327 mutex_unlock(&sc->mutex);
c4dc0d04 2328 return 0;
39305635 2329 }
bc81d43a 2330
39305635 2331 mutex_unlock(&sc->mutex);
c4dc0d04 2332 return -ENOSPC;
39305635
FF
2333}
2334
2335
2336static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2337 struct ieee80211_chanctx_conf *conf)
2338{
2339 struct ath_softc *sc = hw->priv;
bc81d43a 2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2341 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2342
2343 mutex_lock(&sc->mutex);
bc81d43a
SM
2344
2345 ath_dbg(common, CHAN_CTX,
2346 "Remove channel context: %d MHz\n",
2347 conf->def.chan->center_freq);
2348
39305635 2349 ctx->assigned = false;
b18111d9 2350 ctx->hw_queue_base = 0;
73fa2f26 2351 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
bc81d43a 2352
39305635
FF
2353 mutex_unlock(&sc->mutex);
2354}
2355
2356static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2357 struct ieee80211_chanctx_conf *conf,
2358 u32 changed)
2359{
2360 struct ath_softc *sc = hw->priv;
bc81d43a 2361 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2362 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2363
2364 mutex_lock(&sc->mutex);
bc81d43a
SM
2365 ath_dbg(common, CHAN_CTX,
2366 "Change channel context: %d MHz\n",
2367 conf->def.chan->center_freq);
39305635
FF
2368 ath_chanctx_set_channel(sc, ctx, &conf->def);
2369 mutex_unlock(&sc->mutex);
2370}
2371
2372static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2373 struct ieee80211_vif *vif,
2374 struct ieee80211_chanctx_conf *conf)
2375{
2376 struct ath_softc *sc = hw->priv;
bc81d43a 2377 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2378 struct ath_vif *avp = (void *)vif->drv_priv;
2379 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2380 int i;
39305635
FF
2381
2382 mutex_lock(&sc->mutex);
bc81d43a
SM
2383
2384 ath_dbg(common, CHAN_CTX,
2385 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2386 vif->addr, vif->type, vif->p2p,
2387 conf->def.chan->center_freq);
2388
39305635 2389 avp->chanctx = ctx;
2ce73c02 2390 ctx->nvifs_assigned++;
39305635 2391 list_add_tail(&avp->list, &ctx->vifs);
9a9c4fbc 2392 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM
2393 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2394 vif->hw_queue[i] = ctx->hw_queue_base + i;
bc81d43a 2395
39305635
FF
2396 mutex_unlock(&sc->mutex);
2397
2398 return 0;
2399}
2400
2401static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2402 struct ieee80211_vif *vif,
2403 struct ieee80211_chanctx_conf *conf)
2404{
2405 struct ath_softc *sc = hw->priv;
bc81d43a 2406 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF
2407 struct ath_vif *avp = (void *)vif->drv_priv;
2408 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2409 int ac;
39305635
FF
2410
2411 mutex_lock(&sc->mutex);
bc81d43a
SM
2412
2413 ath_dbg(common, CHAN_CTX,
2414 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2415 vif->addr, vif->type, vif->p2p,
2416 conf->def.chan->center_freq);
2417
39305635 2418 avp->chanctx = NULL;
2ce73c02 2419 ctx->nvifs_assigned--;
39305635 2420 list_del(&avp->list);
9a9c4fbc 2421 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM
2422 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2423 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
bc81d43a 2424
39305635
FF
2425 mutex_unlock(&sc->mutex);
2426}
2427
e20a854e
SM
2428static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2429 struct ieee80211_vif *vif)
2430{
2431 struct ath_softc *sc = hw->priv;
2432 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2433 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
c6500ea2
SM
2434 struct ath_beacon_config *cur_conf;
2435 struct ath_chanctx *go_ctx;
2436 unsigned long timeout;
e20a854e 2437 bool changed = false;
c6500ea2 2438 u32 beacon_int;
e20a854e
SM
2439
2440 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2441 return;
2442
2443 if (!avp->chanctx)
2444 return;
2445
2446 mutex_lock(&sc->mutex);
2447
2448 spin_lock_bh(&sc->chan_lock);
c6500ea2 2449 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
e20a854e 2450 changed = true;
c6500ea2
SM
2451 spin_unlock_bh(&sc->chan_lock);
2452
2453 if (!changed)
2454 goto out;
2455
23aab0c2
SM
2456 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2457 ath_dbg(common, CHAN_CTX,
2458 "%s: Aborting HW scan\n", __func__);
2459
2460 mutex_unlock(&sc->mutex);
2461
2462 del_timer_sync(&sc->offchannel.timer);
2463 ath_scan_complete(sc, true);
2464 flush_work(&sc->chanctx_work);
2465
2466 mutex_lock(&sc->mutex);
2467 }
2468
c6500ea2
SM
2469 go_ctx = ath_is_go_chanctx_present(sc);
2470
2471 if (go_ctx) {
2472 /*
2473 * Wait till the GO interface gets a chance
2474 * to send out an NoA.
2475 */
2476 spin_lock_bh(&sc->chan_lock);
2477 sc->sched.mgd_prepare_tx = true;
2478 cur_conf = &go_ctx->beacon;
2479 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2480 spin_unlock_bh(&sc->chan_lock);
2481
2482 timeout = usecs_to_jiffies(beacon_int);
2483 init_completion(&sc->go_beacon);
2484
2485 if (wait_for_completion_timeout(&sc->go_beacon,
2486 timeout) == 0)
2487 ath_dbg(common, CHAN_CTX,
2488 "Failed to send new NoA\n");
e20a854e 2489 }
c6500ea2 2490
878066e7 2491 ath_dbg(common, CHAN_CTX,
c6500ea2
SM
2492 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2493 __func__, vif->addr);
2494
2495 spin_lock_bh(&sc->chan_lock);
2496 sc->next_chan = avp->chanctx;
e20a854e
SM
2497 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2498 spin_unlock_bh(&sc->chan_lock);
2499
c6500ea2
SM
2500 ath_chanctx_set_next(sc, true);
2501out:
e20a854e
SM
2502 mutex_unlock(&sc->mutex);
2503}
2504
78b21949
FF
2505void ath9k_fill_chanctx_ops(void)
2506{
499afacc 2507 if (!ath9k_is_chanctx_enabled())
78b21949
FF
2508 return;
2509
bc81d43a
SM
2510 ath9k_ops.hw_scan = ath9k_hw_scan;
2511 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2512 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
405393cf 2513 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
bc81d43a
SM
2514 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2515 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2516 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2517 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2518 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
e20a854e 2519 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
78b21949
FF
2520}
2521
499afacc
SM
2522#endif
2523
d385c5c2
FF
2524static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2525 int *dbm)
2526{
2527 struct ath_softc *sc = hw->priv;
2528 struct ath_vif *avp = (void *)vif->drv_priv;
2529
2530 mutex_lock(&sc->mutex);
2531 if (avp->chanctx)
2532 *dbm = avp->chanctx->cur_txpower;
2533 else
2534 *dbm = sc->cur_chan->cur_txpower;
2535 mutex_unlock(&sc->mutex);
2536
2537 *dbm /= 2;
2538
2539 return 0;
2540}
2541
6baff7f9 2542struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2543 .tx = ath9k_tx,
2544 .start = ath9k_start,
2545 .stop = ath9k_stop,
2546 .add_interface = ath9k_add_interface,
6b3b991d 2547 .change_interface = ath9k_change_interface,
8feceb67
VT
2548 .remove_interface = ath9k_remove_interface,
2549 .config = ath9k_config,
8feceb67 2550 .configure_filter = ath9k_configure_filter,
df3c6eb3 2551 .sta_state = ath9k_sta_state,
5519541d 2552 .sta_notify = ath9k_sta_notify,
8feceb67 2553 .conf_tx = ath9k_conf_tx,
8feceb67 2554 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2555 .set_key = ath9k_set_key,
8feceb67 2556 .get_tsf = ath9k_get_tsf,
3b5d665b 2557 .set_tsf = ath9k_set_tsf,
8feceb67 2558 .reset_tsf = ath9k_reset_tsf,
4233df6b 2559 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2560 .get_survey = ath9k_get_survey,
3b319aae 2561 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2562 .set_coverage_class = ath9k_set_coverage_class,
69081624 2563 .flush = ath9k_flush,
15b91e83 2564 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41 2565 .tx_last_beacon = ath9k_tx_last_beacon,
86a22acf 2566 .release_buffered_frames = ath9k_release_buffered_frames,
52c94f41 2567 .get_stats = ath9k_get_stats,
43c35284
FF
2568 .set_antenna = ath9k_set_antenna,
2569 .get_antenna = ath9k_get_antenna,
b90bd9d1 2570
e60001e7 2571#ifdef CONFIG_ATH9K_WOW
b11e640a
MSS
2572 .suspend = ath9k_suspend,
2573 .resume = ath9k_resume,
2574 .set_wakeup = ath9k_set_wakeup,
2575#endif
2576
b90bd9d1
BG
2577#ifdef CONFIG_ATH9K_DEBUGFS
2578 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM
2579 .get_et_stats = ath9k_get_et_stats,
2580 .get_et_strings = ath9k_get_et_strings,
2581#endif
2582
1cdbaf0d 2583#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
a145daf7 2584 .sta_add_debugfs = ath9k_sta_add_debugfs,
b90bd9d1 2585#endif
e93d083f
SW
2586 .sw_scan_start = ath9k_sw_scan_start,
2587 .sw_scan_complete = ath9k_sw_scan_complete,
d385c5c2 2588 .get_txpower = ath9k_get_txpower,
8feceb67 2589};