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Merge tag 'x86_kdump_for_v5.19_rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-block.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
5b68138e 2 * Copyright (c) 2008-2011 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
69081624 18#include <linux/delay.h>
394cf0a1 19#include "ath9k.h"
af03abec 20#include "btcoex.h"
f078f209 21
4bad3a20
AW		 22static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
23 u32 queues, bool drop);
24
313eb87f 25u8 ath9k_parse_mpdudensity(u8 mpdudensity)
ff37e337
S		 26{
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58}
59
e2d389b5
SM		 60static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
61 bool sw_pending)
69081624
VT		 62{
63 bool pending = false;
64
65 spin_lock_bh(&txq->axq_lock);
66
b7367285 67 if (txq->axq_depth) {
69081624 68 pending = true;
b7367285
SM		 69 goto out;
70 }
69081624 71
e2d389b5
SM		 72 if (!sw_pending)
73 goto out;
74
0453531e 75 if (txq->mac80211_qnum >= 0) {
63fefa05 76 struct ath_acq *acq;
0453531e 77
63fefa05
THJ		 78 acq = &sc->cur_chan->acq[txq->mac80211_qnum];
79 if (!list_empty(&acq->acq_new) || !list_empty(&acq->acq_old))
0453531e
FF		 80 pending = true;
81 }
b7367285 82out:
69081624
VT		 83 spin_unlock_bh(&txq->axq_lock);
84 return pending;
85}
86
6d79cb4c 87static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR		 88{
89 unsigned long flags;
90 bool ret;
91
9ecdef4b
LR		 92 spin_lock_irqsave(&sc->sc_pm_lock, flags);
93 ret = ath9k_hw_setpower(sc->sc_ah, mode);
94 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR		 95
96 return ret;
97}
98
7ac76764 99void ath_ps_full_sleep(struct timer_list *t)
bf3dac5a 100{
7ac76764 101 struct ath_softc *sc = from_timer(sc, t, sleep_timer);
bf3dac5a 102 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ba24d63d 103 unsigned long flags;
bf3dac5a
FF		 104 bool reset;
105
ba24d63d 106 spin_lock_irqsave(&common->cc_lock, flags);
bf3dac5a 107 ath_hw_cycle_counters_update(common);
ba24d63d 108 spin_unlock_irqrestore(&common->cc_lock, flags);
bf3dac5a
FF		 109
110 ath9k_hw_setrxabort(sc->sc_ah, 1);
111 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
112
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
114}
115
a91d75ae
LR		 116void ath9k_ps_wakeup(struct ath_softc *sc)
117{
898c914a 118 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
a91d75ae 119 unsigned long flags;
fbb078fc 120 enum ath9k_power_mode power_mode;
a91d75ae
LR		 121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (++sc->ps_usecount != 1)
124 goto unlock;
125
bf3dac5a 126 del_timer_sync(&sc->sleep_timer);
fbb078fc 127 power_mode = sc->sc_ah->power_mode;
9ecdef4b 128 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae 129
898c914a
FF		 130 /*
131 * While the hardware is asleep, the cycle counters contain no
132 * useful data. Better clear them now so that they don't mess up
133 * survey data results.
134 */
fbb078fc
FF		 135 if (power_mode != ATH9K_PM_AWAKE) {
136 spin_lock(&common->cc_lock);
137 ath_hw_cycle_counters_update(common);
138 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
c9ae6ab4 139 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
fbb078fc
FF		 140 spin_unlock(&common->cc_lock);
141 }
898c914a 142
a91d75ae
LR		 143 unlock:
144 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
145}
146
147void ath9k_ps_restore(struct ath_softc *sc)
148{
898c914a 149 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c6c539f0 150 enum ath9k_power_mode mode;
a91d75ae
LR		 151 unsigned long flags;
152
153 spin_lock_irqsave(&sc->sc_pm_lock, flags);
154 if (--sc->ps_usecount != 0)
155 goto unlock;
156
ad128860 157 if (sc->ps_idle) {
bf3dac5a
FF		 158 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
159 goto unlock;
160 }
161
162 if (sc->ps_enabled &&
ad128860
SM		 163 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
164 PS_WAIT_FOR_CAB |
165 PS_WAIT_FOR_PSPOLL_DATA |
424749c7
RM		 166 PS_WAIT_FOR_TX_ACK |
167 PS_WAIT_FOR_ANI))) {
c6c539f0 168 mode = ATH9K_PM_NETWORK_SLEEP;
08d4df41
RM		 169 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
170 ath9k_btcoex_stop_gen_timer(sc);
ad128860 171 } else {
c6c539f0 172 goto unlock;
ad128860 173 }
c6c539f0
FF		 174
175 spin_lock(&common->cc_lock);
176 ath_hw_cycle_counters_update(common);
177 spin_unlock(&common->cc_lock);
178
1a8f0d39 179 ath9k_hw_setpower(sc->sc_ah, mode);
a91d75ae
LR		 180
181 unlock:
182 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
183}
184
9adcf440 185static void __ath_cancel_work(struct ath_softc *sc)
ff37e337 186{
5ee08656 187 cancel_work_sync(&sc->paprd_work);
d63ffc45 188 cancel_delayed_work_sync(&sc->hw_check_work);
181fb18d 189 cancel_delayed_work_sync(&sc->hw_pll_work);
fad29cd2 190
bf52592f 191#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
fad29cd2
SM		 192 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
193 cancel_work_sync(&sc->mci_work);
bf52592f 194#endif
9adcf440 195}
5ee08656 196
e60001e7 197void ath_cancel_work(struct ath_softc *sc)
9adcf440
FF		 198{
199 __ath_cancel_work(sc);
200 cancel_work_sync(&sc->hw_reset_work);
201}
3cbb5dd7 202
e60001e7 203void ath_restart_work(struct ath_softc *sc)
af68abad 204{
d63ffc45
FF		 205 ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work,
206 ATH_HW_CHECK_POLL_INT);
af68abad 207
19c36160 208 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
af68abad
SM		 209 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
210 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
211
da0d45f7 212 ath_start_ani(sc);
af68abad
SM		 213}
214
9ebea382 215static bool ath_prepare_reset(struct ath_softc *sc)
9adcf440
FF		 216{
217 struct ath_hw *ah = sc->sc_ah;
ceea2a51 218 bool ret = true;
6a6733f2 219
9adcf440 220 ieee80211_stop_queues(sc->hw);
da0d45f7 221 ath_stop_ani(sc);
9adcf440 222 ath9k_hw_disable_interrupts(ah);
8b3f4616 223
300f77c0
FF		 224 if (AR_SREV_9300_20_OR_LATER(ah)) {
225 ret &= ath_stoprecv(sc);
226 ret &= ath_drain_all_txq(sc);
227 } else {
228 ret &= ath_drain_all_txq(sc);
229 ret &= ath_stoprecv(sc);
230 }
ceea2a51 231
9adcf440
FF		 232 return ret;
233}
ff37e337 234
9adcf440
FF		 235static bool ath_complete_reset(struct ath_softc *sc, bool start)
236{
237 struct ath_hw *ah = sc->sc_ah;
238 struct ath_common *common = ath9k_hw_common(ah);
196fb860 239 unsigned long flags;
c0d7c7af 240
9019f646 241 ath9k_calculate_summary_state(sc, sc->cur_chan);
19ec477f 242 ath_startrecv(sc);
d385c5c2
FF		 243 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
244 sc->cur_chan->txpower,
245 &sc->cur_chan->cur_txpower);
eefa01dd 246 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
3989279c 247
fbbcd146 248 if (!sc->cur_chan->offchannel && start) {
8d7e09dd
FF		 249 /* restore per chanctx TSF timer */
250 if (sc->cur_chan->tsf_val) {
251 u32 offset;
252
253 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
254 NULL);
255 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
256 }
257
258
eefa01dd 259 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
196fb860
SM		 260 goto work;
261
196fb860 262 if (ah->opmode == NL80211_IFTYPE_STATION &&
eefa01dd 263 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
196fb860
SM		 264 spin_lock_irqsave(&sc->sc_pm_lock, flags);
265 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
266 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
a6768280
SM		 267 } else {
268 ath9k_set_beacon(sc);
196fb860
SM		 269 }
270 work:
af68abad 271 ath_restart_work(sc);
0453531e 272 ath_txq_schedule_all(sc);
5ee08656
FF		 273 }
274
071aa9a8 275 sc->gtt_cnt = 0;
9a9c4fbc
RM		 276
277 ath9k_hw_set_interrupts(ah);
278 ath9k_hw_enable_interrupts(ah);
5ba8d9d2 279 ieee80211_wake_queues(sc->hw);
d463af4a
FF		 280 ath9k_p2p_ps_timer(sc);
281
9adcf440
FF		 282 return true;
283}
284
5555c955 285static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
9adcf440
FF		 286{
287 struct ath_hw *ah = sc->sc_ah;
288 struct ath_common *common = ath9k_hw_common(ah);
289 struct ath9k_hw_cal_data *caldata = NULL;
290 bool fastcc = true;
9adcf440
FF		 291 int r;
292
293 __ath_cancel_work(sc);
294
e3f31175 295 disable_irq(sc->irq);
4668cce5 296 tasklet_disable(&sc->intr_tq);
eaf04a69 297 tasklet_disable(&sc->bcon_tasklet);
9adcf440 298 spin_lock_bh(&sc->sc_pcu_lock);
92460412 299
fbbcd146 300 if (!sc->cur_chan->offchannel) {
9adcf440 301 fastcc = false;
b01459e8 302 caldata = &sc->cur_chan->caldata;
9adcf440
FF		 303 }
304
305 if (!hchan) {
306 fastcc = false;
9adcf440
FF		 307 hchan = ah->curchan;
308 }
309
fb312ac5
PR		 310 if (!hchan) {
311 fastcc = false;
312 hchan = ath9k_cmn_get_channel(sc->hw, ah, &sc->cur_chan->chandef);
313 }
314
9ebea382 315 if (!ath_prepare_reset(sc))
9adcf440
FF		 316 fastcc = false;
317
9ea3598b
SM		 318 if (ath9k_is_chanctx_enabled())
319 fastcc = false;
320
d6067f0e
RM		 321 spin_lock_bh(&sc->chan_lock);
322 sc->cur_chandef = sc->cur_chan->chandef;
323 spin_unlock_bh(&sc->chan_lock);
bff11766 324
d2182b69 325 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
feced201 326 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
9adcf440
FF		 327
328 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
329 if (r) {
330 ath_err(common,
331 "Unable to reset channel, reset status %d\n", r);
f50b1cd3
RS		 332
333 ath9k_hw_enable_interrupts(ah);
334 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
335
9adcf440
FF		 336 goto out;
337 }
338
e82cb03f 339 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
fbbcd146 340 sc->cur_chan->offchannel)
e82cb03f
RM		 341 ath9k_mci_set_txpower(sc, true, false);
342
9adcf440
FF		 343 if (!ath_complete_reset(sc, true))
344 r = -EIO;
345
346out:
e3f31175 347 enable_irq(sc->irq);
6a6733f2 348 spin_unlock_bh(&sc->sc_pcu_lock);
eaf04a69 349 tasklet_enable(&sc->bcon_tasklet);
4668cce5
FF		 350 tasklet_enable(&sc->intr_tq);
351
9adcf440
FF		 352 return r;
353}
354
7e1e3864
BG		 355static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
356 struct ieee80211_vif *vif)
ff37e337
S		 357{
358 struct ath_node *an;
ff37e337
S		 359 an = (struct ath_node *)sta->drv_priv;
360
a145daf7 361 an->sc = sc;
7f010c93 362 an->sta = sta;
7e1e3864 363 an->vif = vif;
4bbf4414 364 memset(&an->key_idx, 0, sizeof(an->key_idx));
3d4e20f2 365
dd5ee59b 366 ath_tx_node_init(sc, an);
44b47a7d
LB		 367
368 ath_dynack_node_init(sc->sc_ah, an);
ff37e337
S		 369}
370
371static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
372{
373 struct ath_node *an = (struct ath_node *)sta->drv_priv;
dd5ee59b 374 ath_tx_node_cleanup(sc, an);
44b47a7d
LB		 375
376 ath_dynack_node_deinit(sc->sc_ah, an);
ff37e337
S		 377}
378
f91a35b4 379void ath9k_tasklet(struct tasklet_struct *t)
ff37e337 380{
f91a35b4 381 struct ath_softc *sc = from_tasklet(sc, t, intr_tq);
af03abec 382 struct ath_hw *ah = sc->sc_ah;
c46917bb 383 struct ath_common *common = ath9k_hw_common(ah);
124b979b 384 enum ath_reset_type type;
07c15a3f 385 unsigned long flags;
3a5e969b 386 u32 status;
b5c80475 387 u32 rxmask;
ff37e337 388
3a5e969b
FF		 389 spin_lock_irqsave(&sc->intr_lock, flags);
390 status = sc->intrstatus;
391 sc->intrstatus = 0;
392 spin_unlock_irqrestore(&sc->intr_lock, flags);
393
e3927007
FF		 394 ath9k_ps_wakeup(sc);
395 spin_lock(&sc->sc_pcu_lock);
396
6549a860
SM		 397 if (status & ATH9K_INT_FATAL) {
398 type = RESET_TYPE_FATAL_INT;
124b979b 399 ath9k_queue_reset(sc, type);
affad456 400 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
e3927007 401 goto out;
063d8be3 402 }
ff37e337 403
6549a860
SM		 404 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
405 (status & ATH9K_INT_BB_WATCHDOG)) {
ba24d63d 406 spin_lock_irqsave(&common->cc_lock, flags);
0c759977
SM		 407 ath_hw_cycle_counters_update(common);
408 ar9003_hw_bb_watchdog_dbg_info(ah);
ba24d63d 409 spin_unlock_irqrestore(&common->cc_lock, flags);
0c759977 410
6549a860
SM		 411 if (ar9003_hw_bb_watchdog_check(ah)) {
412 type = RESET_TYPE_BB_WATCHDOG;
413 ath9k_queue_reset(sc, type);
414
affad456 415 ath_dbg(common, RESET,
6549a860
SM		 416 "BB_WATCHDOG: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
071aa9a8
SM		 421 if (status & ATH9K_INT_GTT) {
422 sc->gtt_cnt++;
423
424 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
425 type = RESET_TYPE_TX_GTT;
426 ath9k_queue_reset(sc, type);
affad456 427 ath_dbg(common, RESET,
071aa9a8
SM		 428 "GTT: Skipping interrupts\n");
429 goto out;
430 }
431 }
432
07c15a3f 433 spin_lock_irqsave(&sc->sc_pm_lock, flags);
4105f807
RM		 434 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
435 /*
436 * TSF sync does not look correct; remain awake to sync with
437 * the next Beacon.
438 */
d2182b69 439 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
e8fe7336 440 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
4105f807 441 }
07c15a3f 442 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
4105f807 443
b5c80475
FF		 444 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
445 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
446 ATH9K_INT_RXORN);
447 else
448 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
449
450 if (status & rxmask) {
b5c80475
FF		 451 /* Check for high priority Rx first */
452 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
453 (status & ATH9K_INT_RXHP))
454 ath_rx_tasklet(sc, 0, true);
455
456 ath_rx_tasklet(sc, 0, false);
ff37e337
S		 457 }
458
e5003249 459 if (status & ATH9K_INT_TX) {
071aa9a8
SM		 460 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
461 /*
462 * For EDMA chips, TX completion is enabled for the
463 * beacon queue, so if a beacon has been transmitted
464 * successfully after a GTT interrupt, the GTT counter
465 * gets reset to zero here.
466 */
3b745c7b 467 sc->gtt_cnt = 0;
071aa9a8 468
e5003249 469 ath_tx_edma_tasklet(sc);
071aa9a8 470 } else {
e5003249 471 ath_tx_tasklet(sc);
071aa9a8 472 }
10e23181
FF		 473
474 wake_up(&sc->tx_wait);
e5003249 475 }
063d8be3 476
c67ce339
FF		 477 if (status & ATH9K_INT_GENTIMER)
478 ath_gen_timer_isr(sc->sc_ah);
479
56ca0dba 480 ath9k_btcoex_handle_interrupt(sc, status);
19686ddf 481
ff37e337 482 /* re-enable hardware interrupt */
3a5e969b 483 ath9k_hw_resume_interrupts(ah);
c6cc47b1 484out:
52671e43 485 spin_unlock(&sc->sc_pcu_lock);
153e080d 486 ath9k_ps_restore(sc);
ff37e337
S		 487}
488
6baff7f9 489irqreturn_t ath_isr(int irq, void *dev)
ff37e337 490{
063d8be3
S		 491#define SCHED_INTR ( \
492 ATH9K_INT_FATAL | \
a4d86d95 493 ATH9K_INT_BB_WATCHDOG | \
063d8be3
S		 494 ATH9K_INT_RXORN | \
495 ATH9K_INT_RXEOL | \
496 ATH9K_INT_RX | \
b5c80475
FF		 497 ATH9K_INT_RXLP | \
498 ATH9K_INT_RXHP | \
063d8be3
S		 499 ATH9K_INT_TX | \
500 ATH9K_INT_BMISS | \
501 ATH9K_INT_CST | \
071aa9a8 502 ATH9K_INT_GTT | \
ebb8e1d7 503 ATH9K_INT_TSFOOR | \
40dc5392
MSS		 504 ATH9K_INT_GENTIMER | \
505 ATH9K_INT_MCI)
063d8be3 506
ff37e337 507 struct ath_softc *sc = dev;
cbe61d8a 508 struct ath_hw *ah = sc->sc_ah;
eefa01dd 509 struct ath_common *common = ath9k_hw_common(ah);
ff37e337 510 enum ath9k_int status;
78c8a950 511 u32 sync_cause = 0;
ff37e337
S		 512 bool sched = false;
513
063d8be3
S		 514 /*
515 * The hardware is not ready/present, don't
516 * touch anything. Note this can happen early
517 * on if the IRQ is shared.
518 */
2ba7d144 519 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
063d8be3 520 return IRQ_NONE;
ff37e337 521
872b5d81 522 /* shared irq, not for us */
153e080d 523 if (!ath9k_hw_intrpend(ah))
063d8be3 524 return IRQ_NONE;
063d8be3
S		 525
526 /*
527 * Figure out the reason(s) for the interrupt. Note
528 * that the hal returns a pseudo-ISR that may include
529 * bits we haven't explicitly enabled so we mask the
530 * value to insure we only process bits we requested.
531 */
6a4d05dc
FF		 532 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
533 ath9k_debug_sync_cause(sc, sync_cause);
3069168c 534 status &= ah->imask; /* discard unasked-for bits */
ff37e337 535
4925642d
LL		 536 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
537 ath9k_hw_kill_interrupts(sc->sc_ah);
872b5d81 538 return IRQ_HANDLED;
4925642d 539 }
872b5d81 540
063d8be3
S		 541 /*
542 * If there are no status bits set, then this interrupt was not
543 * for me (should have been caught above).
544 */
153e080d 545 if (!status)
063d8be3 546 return IRQ_NONE;
ff37e337 547
063d8be3 548 /* Cache the status */
3a5e969b
FF		 549 spin_lock(&sc->intr_lock);
550 sc->intrstatus |= status;
551 spin_unlock(&sc->intr_lock);
063d8be3
S		 552
553 if (status & SCHED_INTR)
554 sched = true;
555
556 /*
3b580144
FF		 557 * If a FATAL interrupt is received, we have to reset the chip
558 * immediately.
063d8be3 559 */
3b580144 560 if (status & ATH9K_INT_FATAL)
063d8be3
S		 561 goto chip_reset;
562
a6bb860b 563 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
0c759977 564 (status & ATH9K_INT_BB_WATCHDOG))
08578b8f 565 goto chip_reset;
e60001e7 566
063d8be3
S		 567 if (status & ATH9K_INT_SWBA)
568 tasklet_schedule(&sc->bcon_tasklet);
569
570 if (status & ATH9K_INT_TXURN)
571 ath9k_hw_updatetxtriglevel(ah, true);
572
0682c9b5
RM		 573 if (status & ATH9K_INT_RXEOL) {
574 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
72d874c6 575 ath9k_hw_set_interrupts(ah);
b5c80475
FF		 576 }
577
153e080d
VT		 578 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
579 if (status & ATH9K_INT_TIM_TIMER) {
ff9f0b63
LR		 580 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
581 goto chip_reset;
063d8be3
S		 582 /* Clear RxAbort bit so that we can
583 * receive frames */
9ecdef4b 584 ath9k_setpower(sc, ATH9K_PM_AWAKE);
07c15a3f 585 spin_lock(&sc->sc_pm_lock);
153e080d 586 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 587 sc->ps_flags |= PS_WAIT_FOR_BEACON;
07c15a3f 588 spin_unlock(&sc->sc_pm_lock);
ff37e337 589 }
063d8be3
S		 590
591chip_reset:
ff37e337 592
817e11de
S		 593 ath_debug_stat_interrupt(sc, status);
594
ff37e337 595 if (sched) {
4df3071e 596 /* turn off every interrupt */
3a5e969b 597 ath9k_hw_kill_interrupts(ah);
ff37e337
S		 598 tasklet_schedule(&sc->intr_tq);
599 }
600
601 return IRQ_HANDLED;
063d8be3
S		 602
603#undef SCHED_INTR
ff37e337
S		 604}
605
ae2ff239
SM		 606/*
607 * This function is called when a HW reset cannot be deferred
608 * and has to be immediate.
609 */
5555c955 610int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
ff37e337 611{
ae2ff239 612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ec30326e 613 int r;
ff37e337 614
872b5d81 615 ath9k_hw_kill_interrupts(sc->sc_ah);
ae2ff239
SM		 616 set_bit(ATH_OP_HW_RESET, &common->op_flags);
617
783cd01e 618 ath9k_ps_wakeup(sc);
5555c955 619 r = ath_reset_internal(sc, hchan);
783cd01e 620 ath9k_ps_restore(sc);
2ab81d4a 621
ae8d2858 622 return r;
ff37e337
S		 623}
624
ae2ff239
SM		 625/*
626 * When a HW reset can be deferred, it is added to the
627 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
628 * queueing.
629 */
124b979b
RM		 630void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
631{
eefa01dd 632 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
124b979b
RM		 633#ifdef CONFIG_ATH9K_DEBUGFS
634 RESET_STAT_INC(sc, type);
635#endif
872b5d81 636 ath9k_hw_kill_interrupts(sc->sc_ah);
eefa01dd 637 set_bit(ATH_OP_HW_RESET, &common->op_flags);
124b979b
RM		 638 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
639}
640
236de514
FF		 641void ath_reset_work(struct work_struct *work)
642{
643 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
644
5555c955
SM		 645 ath9k_ps_wakeup(sc);
646 ath_reset_internal(sc, NULL);
647 ath9k_ps_restore(sc);
236de514
FF		 648}
649
ff37e337
S		 650/**********************/
651/* mac80211 callbacks */
652/**********************/
653
8feceb67 654static int ath9k_start(struct ieee80211_hw *hw)
f078f209 655{
9ac58615 656 struct ath_softc *sc = hw->priv;
af03abec 657 struct ath_hw *ah = sc->sc_ah;
c46917bb 658 struct ath_common *common = ath9k_hw_common(ah);
39305635 659 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
fbbcd146 660 struct ath_chanctx *ctx = sc->cur_chan;
ff37e337 661 struct ath9k_channel *init_channel;
82880a7c 662 int r;
f078f209 663
d2182b69 664 ath_dbg(common, CONFIG,
226afe68
JP		 665 "Starting driver with initial channel: %d MHz\n",
666 curchan->center_freq);
f078f209 667
f62d816f 668 ath9k_ps_wakeup(sc);
141b38b6
S		 669 mutex_lock(&sc->mutex);
670
fbbcd146 671 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
bff11766 672 sc->cur_chandef = hw->conf.chandef;
ff37e337
S		 673
674 /* Reset SERDES registers */
84c87dc8 675 ath9k_hw_configpcipowersave(ah, false);
ff37e337
S		 676
677 /*
678 * The basic interface to setting the hardware in a good
679 * state is ``reset''. On return the hardware is known to
680 * be powered up and with interrupts disabled. This must
681 * be followed by initialization of the appropriate bits
682 * and then setup of the interrupt mask.
683 */
4bdd1e97 684 spin_lock_bh(&sc->sc_pcu_lock);
c0c11741
FF		 685
686 atomic_set(&ah->intr_ref_cnt, -1);
687
20bd2a09 688 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 689 if (r) {
3800276a
JP		 690 ath_err(common,
691 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
692 r, curchan->center_freq);
ceb26a60 693 ah->reset_power_on = false;
ff37e337 694 }
ff37e337 695
ff37e337 696 /* Setup our intr mask. */
b5c80475
FF		 697 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
698 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
699 ATH9K_INT_GLOBAL;
700
701 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f 702 ah->imask |= ATH9K_INT_RXHP |
a6bb860b 703 ATH9K_INT_RXLP;
b5c80475
FF		 704 else
705 ah->imask |= ATH9K_INT_RX;
ff37e337 706
a6bb860b
SM		 707 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
708 ah->imask |= ATH9K_INT_BB_WATCHDOG;
709
071aa9a8
SM		 710 /*
711 * Enable GTT interrupts only for AR9003/AR9004 chips
712 * for now.
713 */
714 if (AR_SREV_9300_20_OR_LATER(ah))
715 ah->imask |= ATH9K_INT_GTT;
ff37e337 716
af03abec 717 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 718 ah->imask |= ATH9K_INT_CST;
ff37e337 719
e270e776 720 ath_mci_enable(sc);
40dc5392 721
eefa01dd 722 clear_bit(ATH_OP_INVALID, &common->op_flags);
5f841b41 723 sc->sc_ah->is_monitoring = false;
ff37e337 724
ceb26a60
FF		 725 if (!ath_complete_reset(sc, false))
726 ah->reset_power_on = false;
ff37e337 727
e34f2ff4 728 if (ah->led_pin >= 0) {
aeeb2065
SM		 729 ath9k_hw_set_gpio(ah, ah->led_pin,
730 (ah->config.led_active_high) ? 1 : 0);
e34f2ff4
GS		 731 ath9k_hw_gpio_request_out(ah, ah->led_pin, NULL,
732 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
733 }
c0c11741
FF		 734
735 /*
736 * Reset key cache to sane defaults (all entries cleared) instead of
737 * semi-random values after suspend/resume.
738 */
739 ath9k_cmn_init_crypto(sc->sc_ah);
740
a35051ce
FF		 741 ath9k_hw_reset_tsf(ah);
742
9adcf440 743 spin_unlock_bh(&sc->sc_pcu_lock);
164ace38 744
f23cdfb3
MP		 745 ath9k_rng_start(sc);
746
141b38b6
S		 747 mutex_unlock(&sc->mutex);
748
f62d816f
FF		 749 ath9k_ps_restore(sc);
750
ceb26a60 751 return 0;
f078f209
LR		 752}
753
36323f81
TH		 754static void ath9k_tx(struct ieee80211_hw *hw,
755 struct ieee80211_tx_control *control,
756 struct sk_buff *skb)
f078f209 757{
9ac58615 758 struct ath_softc *sc = hw->priv;
c46917bb 759 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 760 struct ath_tx_control txctl;
1bc14880 761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
07c15a3f 762 unsigned long flags;
528f0c6b 763
96148326 764 if (sc->ps_enabled) {
dc8c4585
JM		 765 /*
766 * mac80211 does not set PM field for normal data frames, so we
767 * need to update that based on the current PS mode.
768 */
769 if (ieee80211_is_data(hdr->frame_control) &&
770 !ieee80211_is_nullfunc(hdr->frame_control) &&
771 !ieee80211_has_pm(hdr->frame_control)) {
d2182b69 772 ath_dbg(common, PS,
226afe68 773 "Add PM=1 for a TX frame while in PS mode\n");
dc8c4585
JM		 774 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
775 }
776 }
777
ad128860 778 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
9a23f9ca
JM		 779 /*
780 * We are using PS-Poll and mac80211 can request TX while in
781 * power save mode. Need to wake up hardware for the TX to be
782 * completed and if needed, also for RX of buffered frames.
783 */
9a23f9ca 784 ath9k_ps_wakeup(sc);
07c15a3f 785 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fdf76622
VT		 786 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
787 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 788 if (ieee80211_is_pspoll(hdr->frame_control)) {
d2182b69 789 ath_dbg(common, PS,
226afe68 790 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 791 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 792 } else {
d2182b69 793 ath_dbg(common, PS, "Wake up to complete TX\n");
1b04b930 794 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM		 795 }
796 /*
797 * The actual restore operation will happen only after
ad128860 798 * the ps_flags bit is cleared. We are just dropping
9a23f9ca
JM		 799 * the ps_usecount here.
800 */
07c15a3f 801 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
9a23f9ca
JM		 802 ath9k_ps_restore(sc);
803 }
804
ad128860
SM		 805 /*
806 * Cannot tx while the hardware is in full sleep, it first needs a full
807 * chip reset to recover from that
808 */
809 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
810 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
811 goto exit;
812 }
813
528f0c6b 814 memset(&txctl, 0, sizeof(struct ath_tx_control));
066dae93 815 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
36323f81 816 txctl.sta = control->sta;
528f0c6b 817
d2182b69 818 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 819
c52f33d0 820 if (ath_tx_start(hw, skb, &txctl) != 0) {
d2182b69 821 ath_dbg(common, XMIT, "TX failed\n");
72569b7b 822 TX_STAT_INC(sc, txctl.txq->axq_qnum, txfailed);
528f0c6b 823 goto exit;
8feceb67
VT		 824 }
825
7bb45683 826 return;
528f0c6b 827exit:
249ee722 828 ieee80211_free_txskb(hw, skb);
f078f209
LR		 829}
830
ca284802
JM		 831static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix)
832{
833 struct ath_buf *bf;
834 struct ieee80211_tx_info *txinfo;
835 struct ath_frame_info *fi;
836
837 list_for_each_entry(bf, txq_list, list) {
838 if (bf->bf_state.stale || !bf->bf_mpdu)
839 continue;
840
841 txinfo = IEEE80211_SKB_CB(bf->bf_mpdu);
5a6b06f5 842 fi = (struct ath_frame_info *)&txinfo->status.status_driver_data[0];
ca284802
JM		 843 if (fi->keyix == keyix)
844 return true;
845 }
846
847 return false;
848}
849
850static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix)
851{
852 struct ath_hw *ah = sc->sc_ah;
853 int i;
854 struct ath_txq *txq;
855 bool key_in_use = false;
856
857 for (i = 0; !key_in_use && i < ATH9K_NUM_TX_QUEUES; i++) {
858 if (!ATH_TXQ_SETUP(sc, i))
859 continue;
860 txq = &sc->tx.txq[i];
861 if (!txq->axq_depth)
862 continue;
863 if (!ath9k_hw_numtxpending(ah, txq->axq_qnum))
864 continue;
865
866 ath_txq_lock(sc, txq);
867 key_in_use = ath9k_txq_list_has_key(&txq->axq_q, keyix);
868 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
869 int idx = txq->txq_tailidx;
870
871 while (!key_in_use &&
872 !list_empty(&txq->txq_fifo[idx])) {
873 key_in_use = ath9k_txq_list_has_key(
874 &txq->txq_fifo[idx], keyix);
875 INCR(idx, ATH_TXFIFO_DEPTH);
876 }
877 }
878 ath_txq_unlock(sc, txq);
879 }
880
881 return key_in_use;
882}
883
884static void ath9k_pending_key_del(struct ath_softc *sc, u8 keyix)
885{
886 struct ath_hw *ah = sc->sc_ah;
887 struct ath_common *common = ath9k_hw_common(ah);
888
889 if (!test_bit(keyix, ah->pending_del_keymap) ||
890 ath9k_txq_has_key(sc, keyix))
891 return;
892
893 /* No more TXQ frames point to this key cache entry, so delete it. */
894 clear_bit(keyix, ah->pending_del_keymap);
895 ath_key_delete(common, keyix);
896}
897
8feceb67 898static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 899{
9ac58615 900 struct ath_softc *sc = hw->priv;
af03abec 901 struct ath_hw *ah = sc->sc_ah;
c46917bb 902 struct ath_common *common = ath9k_hw_common(ah);
c0c11741 903 bool prev_idle;
ca284802 904 int i;
f078f209 905
ea22df29
SM		 906 ath9k_deinit_channel_context(sc);
907
4c483817
S		 908 mutex_lock(&sc->mutex);
909
f23cdfb3
MP		 910 ath9k_rng_stop(sc);
911
9adcf440 912 ath_cancel_work(sc);
c94dbff7 913
eefa01dd 914 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 915 ath_dbg(common, ANY, "Device not present\n");
4c483817 916 mutex_unlock(&sc->mutex);
9c84b797
S		 917 return;
918 }
8feceb67 919
3867cf6a
S		 920 /* Ensure HW is awake when we try to shut it down. */
921 ath9k_ps_wakeup(sc);
922
6a6733f2
LR		 923 spin_lock_bh(&sc->sc_pcu_lock);
924
203043f5
SG		 925 /* prevent tasklets to enable interrupts once we disable them */
926 ah->imask &= ~ATH9K_INT_GLOBAL;
927
ff37e337
S		 928 /* make sure h/w will not generate any interrupt
929 * before setting the invalid flag. */
4df3071e 930 ath9k_hw_disable_interrupts(ah);
ff37e337 931
c0c11741
FF		 932 spin_unlock_bh(&sc->sc_pcu_lock);
933
934 /* we can now sync irq and kill any running tasklets, since we already
935 * disabled interrupts and not holding a spin lock */
936 synchronize_irq(sc->irq);
937 tasklet_kill(&sc->intr_tq);
938 tasklet_kill(&sc->bcon_tasklet);
939
940 prev_idle = sc->ps_idle;
941 sc->ps_idle = true;
942
943 spin_lock_bh(&sc->sc_pcu_lock);
944
e34f2ff4 945 if (ah->led_pin >= 0) {
aeeb2065
SM		 946 ath9k_hw_set_gpio(ah, ah->led_pin,
947 (ah->config.led_active_high) ? 0 : 1);
e34f2ff4
GS		 948 ath9k_hw_gpio_request_in(ah, ah->led_pin, NULL);
949 }
c0c11741 950
9ebea382 951 ath_prepare_reset(sc);
ff37e337 952
0d95521e
FF		 953 if (sc->rx.frag) {
954 dev_kfree_skb_any(sc->rx.frag);
955 sc->rx.frag = NULL;
956 }
957
c0c11741 958 if (!ah->curchan)
fbbcd146
FF		 959 ah->curchan = ath9k_cmn_get_channel(hw, ah,
960 &sc->cur_chan->chandef);
6a6733f2 961
c0c11741 962 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ef739ab6
FF		 963
964 set_bit(ATH_OP_INVALID, &common->op_flags);
965
c0c11741 966 ath9k_hw_phy_disable(ah);
6a6733f2 967
c0c11741 968 ath9k_hw_configpcipowersave(ah, true);
203043f5 969
c0c11741 970 spin_unlock_bh(&sc->sc_pcu_lock);
3867cf6a 971
ca284802
JM		 972 for (i = 0; i < ATH_KEYMAX; i++)
973 ath9k_pending_key_del(sc, i);
974
73488cb2
JM		 975 /* Clear key cache entries explicitly to get rid of any potentially
976 * remaining keys.
977 */
978 ath9k_cmn_init_crypto(sc->sc_ah);
979
c0c11741 980 ath9k_ps_restore(sc);
ff37e337 981
c0c11741 982 sc->ps_idle = prev_idle;
500c064d 983
141b38b6
S		 984 mutex_unlock(&sc->mutex);
985
d2182b69 986 ath_dbg(common, CONFIG, "Driver halt\n");
f078f209
LR		 987}
988
c648ecb0 989static bool ath9k_uses_beacons(int type)
4801416c
BG		 990{
991 switch (type) {
992 case NL80211_IFTYPE_AP:
993 case NL80211_IFTYPE_ADHOC:
994 case NL80211_IFTYPE_MESH_POINT:
995 return true;
996 default:
997 return false;
998 }
999}
1000
cfda2d8e
BB		 1001static void ath9k_vif_iter_set_beacon(struct ath9k_vif_iter_data *iter_data,
1002 struct ieee80211_vif *vif)
1003{
1004 /* Use the first (configured) interface, but prefering AP interfaces. */
1005 if (!iter_data->primary_beacon_vif) {
1006 iter_data->primary_beacon_vif = vif;
1007 } else {
1008 if (iter_data->primary_beacon_vif->type != NL80211_IFTYPE_AP &&
1009 vif->type == NL80211_IFTYPE_AP)
4c51e7db 1010 iter_data->primary_beacon_vif = vif;
cfda2d8e
BB		 1011 }
1012
1013 iter_data->beacons = true;
1014 iter_data->nbcnvifs += 1;
1015}
1016
4b93fd29
SM		 1017static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
1018 u8 *mac, struct ieee80211_vif *vif)
4801416c 1019{
cb35582a 1020 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
4801416c
BG		 1021 int i;
1022
ab11bb28 1023 if (iter_data->has_hw_macaddr) {
4801416c
BG		 1024 for (i = 0; i < ETH_ALEN; i++)
1025 iter_data->mask[i] &=
1026 ~(iter_data->hw_macaddr[i] ^ mac[i]);
ab11bb28
FF		 1027 } else {
1028 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
1029 iter_data->has_hw_macaddr = true;
1030 }
141b38b6 1031
9a9c4fbc 1032 if (!vif->bss_conf.use_short_slot)
11b0ac2e 1033 iter_data->slottime = 20;
9a9c4fbc 1034
1ed32e4f 1035 switch (vif->type) {
4801416c
BG		 1036 case NL80211_IFTYPE_AP:
1037 iter_data->naps++;
cfda2d8e
BB		 1038 if (vif->bss_conf.enable_beacon)
1039 ath9k_vif_iter_set_beacon(iter_data, vif);
f078f209 1040 break;
4801416c
BG		 1041 case NL80211_IFTYPE_STATION:
1042 iter_data->nstations++;
cb35582a 1043 if (avp->assoc && !iter_data->primary_sta)
9a9c4fbc 1044 iter_data->primary_sta = vif;
e51f3eff 1045 break;
862a336c
JK		 1046 case NL80211_IFTYPE_OCB:
1047 iter_data->nocbs++;
1048 break;
05c914fe 1049 case NL80211_IFTYPE_ADHOC:
4801416c 1050 iter_data->nadhocs++;
9a9c4fbc 1051 if (vif->bss_conf.enable_beacon)
cfda2d8e 1052 ath9k_vif_iter_set_beacon(iter_data, vif);
4801416c 1053 break;
9cb5412b 1054 case NL80211_IFTYPE_MESH_POINT:
4801416c 1055 iter_data->nmeshes++;
9a9c4fbc 1056 if (vif->bss_conf.enable_beacon)
cfda2d8e 1057 ath9k_vif_iter_set_beacon(iter_data, vif);
4801416c 1058 break;
f078f209 1059 default:
4801416c 1060 break;
f078f209 1061 }
4801416c 1062}
f078f209 1063
2ce73c02
SM		 1064static void ath9k_update_bssid_mask(struct ath_softc *sc,
1065 struct ath_chanctx *ctx,
1066 struct ath9k_vif_iter_data *iter_data)
1067{
1068 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1069 struct ath_vif *avp;
1070 int i;
1071
1072 if (!ath9k_is_chanctx_enabled())
1073 return;
1074
1075 list_for_each_entry(avp, &ctx->vifs, list) {
1076 if (ctx->nvifs_assigned != 1)
1077 continue;
1078
b9a9693f 1079 if (!iter_data->has_hw_macaddr)
2ce73c02
SM		 1080 continue;
1081
1082 ether_addr_copy(common->curbssid, avp->bssid);
1083
1084 /* perm_addr will be used as the p2p device address. */
1085 for (i = 0; i < ETH_ALEN; i++)
1086 iter_data->mask[i] &=
1087 ~(iter_data->hw_macaddr[i] ^
1088 sc->hw->wiphy->perm_addr[i]);
1089 }
1090}
1091
4801416c 1092/* Called with sc->mutex held. */
9a9c4fbc
RM		 1093void ath9k_calculate_iter_data(struct ath_softc *sc,
1094 struct ath_chanctx *ctx,
4801416c
BG		 1095 struct ath9k_vif_iter_data *iter_data)
1096{
9a9c4fbc 1097 struct ath_vif *avp;
8feceb67 1098
4801416c 1099 /*
daad1660
BG		 1100 * The hardware will use primary station addr together with the
1101 * BSSID mask when matching addresses.
4801416c
BG		 1102 */
1103 memset(iter_data, 0, sizeof(*iter_data));
93803b33 1104 eth_broadcast_addr(iter_data->mask);
11b0ac2e 1105 iter_data->slottime = 9;
9a9c4fbc
RM		 1106
1107 list_for_each_entry(avp, &ctx->vifs, list)
1108 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
2ce73c02
SM		 1109
1110 ath9k_update_bssid_mask(sc, ctx, iter_data);
9a9c4fbc
RM		 1111}
1112
1113static void ath9k_set_assoc_state(struct ath_softc *sc,
1114 struct ieee80211_vif *vif, bool changed)
1115{
1116 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
cb35582a 1117 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
9a9c4fbc
RM		 1118 unsigned long flags;
1119
1120 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
9a9c4fbc 1121
cb35582a
SM		 1122 ether_addr_copy(common->curbssid, avp->bssid);
1123 common->curaid = avp->aid;
9a9c4fbc
RM		 1124 ath9k_hw_write_associd(sc->sc_ah);
1125
1126 if (changed) {
1127 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1128 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
5640b08e 1129
9a9c4fbc
RM		 1130 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1131 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1132 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1133 }
4801416c 1134
9a9c4fbc
RM		 1135 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1136 ath9k_mci_update_wlan_channels(sc, false);
ab11bb28 1137
9a9c4fbc
RM		 1138 ath_dbg(common, CONFIG,
1139 "Primary Station interface: %pM, BSSID: %pM\n",
1140 vif->addr, common->curbssid);
4801416c 1141}
8ca21f01 1142
4ee26de1
SM		 1143#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1144static void ath9k_set_offchannel_state(struct ath_softc *sc)
1145{
1146 struct ath_hw *ah = sc->sc_ah;
1147 struct ath_common *common = ath9k_hw_common(ah);
1148 struct ieee80211_vif *vif = NULL;
1149
1150 ath9k_ps_wakeup(sc);
1151
1152 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1153 vif = sc->offchannel.scan_vif;
1154 else
1155 vif = sc->offchannel.roc_vif;
1156
1157 if (WARN_ON(!vif))
1158 goto exit;
1159
1160 eth_zero_addr(common->curbssid);
1161 eth_broadcast_addr(common->bssidmask);
62ae1aef 1162 memcpy(common->macaddr, vif->addr, ETH_ALEN);
4ee26de1
SM		 1163 common->curaid = 0;
1164 ah->opmode = vif->type;
1165 ah->imask &= ~ATH9K_INT_SWBA;
1166 ah->imask &= ~ATH9K_INT_TSFOOR;
11b0ac2e 1167 ah->slottime = 9;
4ee26de1
SM		 1168
1169 ath_hw_setbssidmask(common);
1170 ath9k_hw_setopmode(ah);
1171 ath9k_hw_write_associd(sc->sc_ah);
1172 ath9k_hw_set_interrupts(ah);
1173 ath9k_hw_init_global_settings(ah);
1174
1175exit:
1176 ath9k_ps_restore(sc);
1177}
1178#endif
1179
4801416c 1180/* Called with sc->mutex held. */
9a9c4fbc
RM		 1181void ath9k_calculate_summary_state(struct ath_softc *sc,
1182 struct ath_chanctx *ctx)
4801416c 1183{
4801416c
BG		 1184 struct ath_hw *ah = sc->sc_ah;
1185 struct ath_common *common = ath9k_hw_common(ah);
1186 struct ath9k_vif_iter_data iter_data;
8ca21f01 1187
9a9c4fbc
RM		 1188 ath_chanctx_check_active(sc, ctx);
1189
1190 if (ctx != sc->cur_chan)
1191 return;
1192
4ee26de1
SM		 1193#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1194 if (ctx == &sc->offchannel.chan)
1195 return ath9k_set_offchannel_state(sc);
1196#endif
1197
9a9c4fbc
RM		 1198 ath9k_ps_wakeup(sc);
1199 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1200
1201 if (iter_data.has_hw_macaddr)
62ae1aef 1202 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
2c3db3d5 1203
4801416c
BG		 1204 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1205 ath_hw_setbssidmask(common);
1206
4801416c 1207 if (iter_data.naps > 0) {
60ca9f87 1208 ath9k_hw_set_tsfadjust(ah, true);
4801416c
BG		 1209 ah->opmode = NL80211_IFTYPE_AP;
1210 } else {
60ca9f87 1211 ath9k_hw_set_tsfadjust(ah, false);
cfda2d8e
BB		 1212 if (iter_data.beacons)
1213 ath9k_beacon_ensure_primary_slot(sc);
5640b08e 1214
fd5999cf
JC		 1215 if (iter_data.nmeshes)
1216 ah->opmode = NL80211_IFTYPE_MESH_POINT;
862a336c
JK		 1217 else if (iter_data.nocbs)
1218 ah->opmode = NL80211_IFTYPE_OCB;
4801416c
BG		 1219 else if (iter_data.nadhocs)
1220 ah->opmode = NL80211_IFTYPE_ADHOC;
1221 else
1222 ah->opmode = NL80211_IFTYPE_STATION;
1223 }
5640b08e 1224
df35d29e
SM		 1225 ath9k_hw_setopmode(ah);
1226
748299f2 1227 ctx->switch_after_beacon = false;
198823fd 1228 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
3069168c 1229 ah->imask |= ATH9K_INT_TSFOOR;
748299f2 1230 else {
4801416c 1231 ah->imask &= ~ATH9K_INT_TSFOOR;
748299f2
FF		 1232 if (iter_data.naps == 1 && iter_data.beacons)
1233 ctx->switch_after_beacon = true;
1234 }
4af9cf4f 1235
9a9c4fbc
RM		 1236 if (ah->opmode == NL80211_IFTYPE_STATION) {
1237 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1238
9a9c4fbc 1239 if (iter_data.primary_sta) {
05860bed 1240 iter_data.primary_beacon_vif = iter_data.primary_sta;
602607b6 1241 iter_data.beacons = true;
9a9c4fbc
RM		 1242 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1243 changed);
1030f9fe 1244 ctx->primary_sta = iter_data.primary_sta;
9a9c4fbc
RM		 1245 } else {
1246 ctx->primary_sta = NULL;
93803b33 1247 eth_zero_addr(common->curbssid);
9a9c4fbc
RM		 1248 common->curaid = 0;
1249 ath9k_hw_write_associd(sc->sc_ah);
1250 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1251 ath9k_mci_update_wlan_channels(sc, true);
1252 }
9a9c4fbc 1253 }
cfda2d8e
BB		 1254 sc->nbcnvifs = iter_data.nbcnvifs;
1255 ath9k_beacon_config(sc, iter_data.primary_beacon_vif,
1256 iter_data.beacons);
72d874c6 1257 ath9k_hw_set_interrupts(ah);
6dcc3444 1258
9a9c4fbc
RM		 1259 if (ah->slottime != iter_data.slottime) {
1260 ah->slottime = iter_data.slottime;
1261 ath9k_hw_init_global_settings(ah);
6dcc3444 1262 }
9a9c4fbc
RM		 1263
1264 if (iter_data.primary_sta)
1265 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1266 else
1267 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1268
2ce73c02
SM		 1269 ath_dbg(common, CONFIG,
1270 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1271 common->macaddr, common->curbssid, common->bssidmask);
1272
9a9c4fbc 1273 ath9k_ps_restore(sc);
4801416c 1274}
6f255425 1275
283dd119
LB		 1276static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1277{
50c8cd44 1278 int *power = data;
283dd119 1279
db6d9e9e
BG		 1280 if (vif->bss_conf.txpower == INT_MIN)
1281 return;
1282
283dd119
LB		 1283 if (*power < vif->bss_conf.txpower)
1284 *power = vif->bss_conf.txpower;
1285}
1286
1287/* Called with sc->mutex held. */
1288void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1289{
1290 int power;
1291 struct ath_hw *ah = sc->sc_ah;
1292 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1293
1294 ath9k_ps_wakeup(sc);
1295 if (ah->tpc_enabled) {
1296 power = (vif) ? vif->bss_conf.txpower : -1;
1297 ieee80211_iterate_active_interfaces_atomic(
1298 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1299 ath9k_tpc_vif_iter, &power);
1300 if (power == -1)
1301 power = sc->hw->conf.power_level;
1302 } else {
1303 power = sc->hw->conf.power_level;
1304 }
1305 sc->cur_chan->txpower = 2 * power;
1306 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1307 sc->cur_chan->cur_txpower = reg->max_power_level;
1308 ath9k_ps_restore(sc);
1309}
1310
a4027644
SM		 1311static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1312 struct ieee80211_vif *vif)
1313{
1314 int i;
1315
868caae3
SM		 1316 if (!ath9k_is_chanctx_enabled())
1317 return;
1318
a4027644
SM		 1319 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1320 vif->hw_queue[i] = i;
1321
4b870c26
CYY		 1322 if (vif->type == NL80211_IFTYPE_AP ||
1323 vif->type == NL80211_IFTYPE_MESH_POINT)
a4027644
SM		 1324 vif->cab_queue = hw->queues - 2;
1325 else
1326 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1327}
1328
4801416c
BG		 1329static int ath9k_add_interface(struct ieee80211_hw *hw,
1330 struct ieee80211_vif *vif)
6b3b991d 1331{
9ac58615 1332 struct ath_softc *sc = hw->priv;
4801416c
BG		 1333 struct ath_hw *ah = sc->sc_ah;
1334 struct ath_common *common = ath9k_hw_common(ah);
f89d1bc4
FF		 1335 struct ath_vif *avp = (void *)vif->drv_priv;
1336 struct ath_node *an = &avp->mcast_node;
6b3b991d 1337
461cf036 1338 mutex_lock(&sc->mutex);
6df0580b
FF		 1339 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
1340 if (sc->cur_chan->nvifs >= 1) {
1341 mutex_unlock(&sc->mutex);
1342 return -EOPNOTSUPP;
1343 }
1344 sc->tx99_vif = vif;
1345 }
6b3b991d 1346
d2182b69 1347 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
ca529c93 1348 sc->cur_chan->nvifs++;
4801416c 1349
b9a9693f
KV		 1350 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1351 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1352
130ef6e9
SM		 1353 if (ath9k_uses_beacons(vif->type))
1354 ath9k_beacon_assign_slot(sc, vif);
1355
d463af4a 1356 avp->vif = vif;
499afacc 1357 if (!ath9k_is_chanctx_enabled()) {
39305635 1358 avp->chanctx = sc->cur_chan;
9a9c4fbc
RM		 1359 list_add_tail(&avp->list, &avp->chanctx->vifs);
1360 }
a4027644 1361
daad1660
BG		 1362 ath9k_calculate_summary_state(sc, avp->chanctx);
1363
a4027644 1364 ath9k_assign_hw_queues(hw, vif);
0453531e 1365
283dd119
LB		 1366 ath9k_set_txpower(sc, vif);
1367
f89d1bc4
FF		 1368 an->sc = sc;
1369 an->sta = NULL;
1370 an->vif = vif;
1371 an->no_ps_filter = true;
1372 ath_tx_node_init(sc, an);
1373
4801416c 1374 mutex_unlock(&sc->mutex);
327967cb 1375 return 0;
6b3b991d
RM		 1376}
1377
1378static int ath9k_change_interface(struct ieee80211_hw *hw,
1379 struct ieee80211_vif *vif,
1380 enum nl80211_iftype new_type,
1381 bool p2p)
1382{
9ac58615 1383 struct ath_softc *sc = hw->priv;
6b3b991d 1384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
c083ce99 1385 struct ath_vif *avp = (void *)vif->drv_priv;
6b3b991d 1386
6b3b991d 1387 mutex_lock(&sc->mutex);
4801416c 1388
97f2645f 1389 if (IS_ENABLED(CONFIG_ATH9K_TX99)) {
89f927af
LR		 1390 mutex_unlock(&sc->mutex);
1391 return -EOPNOTSUPP;
1392 }
1393
1394 ath_dbg(common, CONFIG, "Change Interface\n");
1395
4801416c 1396 if (ath9k_uses_beacons(vif->type))
130ef6e9 1397 ath9k_beacon_remove_slot(sc, vif);
4801416c 1398
6b3b991d
RM		 1399 vif->type = new_type;
1400 vif->p2p = p2p;
1401
130ef6e9
SM		 1402 if (ath9k_uses_beacons(vif->type))
1403 ath9k_beacon_assign_slot(sc, vif);
9a9c4fbc 1404
a4027644 1405 ath9k_assign_hw_queues(hw, vif);
9a9c4fbc 1406 ath9k_calculate_summary_state(sc, avp->chanctx);
130ef6e9 1407
283dd119
LB		 1408 ath9k_set_txpower(sc, vif);
1409
6b3b991d 1410 mutex_unlock(&sc->mutex);
327967cb 1411 return 0;
6b3b991d
RM		 1412}
1413
8feceb67 1414static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1415 struct ieee80211_vif *vif)
f078f209 1416{
9ac58615 1417 struct ath_softc *sc = hw->priv;
c46917bb 1418 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
f89d1bc4 1419 struct ath_vif *avp = (void *)vif->drv_priv;
f078f209 1420
d2182b69 1421 ath_dbg(common, CONFIG, "Detach Interface\n");
f078f209 1422
141b38b6
S		 1423 mutex_lock(&sc->mutex);
1424
c7dd40c9 1425 ath9k_p2p_remove_vif(sc, vif);
d463af4a 1426
ca529c93 1427 sc->cur_chan->nvifs--;
6df0580b 1428 sc->tx99_vif = NULL;
499afacc 1429 if (!ath9k_is_chanctx_enabled())
9a9c4fbc 1430 list_del(&avp->list);
580f0b8a 1431
4801416c 1432 if (ath9k_uses_beacons(vif->type))
130ef6e9 1433 ath9k_beacon_remove_slot(sc, vif);
2c3db3d5 1434
f89d1bc4
FF		 1435 ath_tx_node_cleanup(sc, &avp->mcast_node);
1436
daad1660
BG		 1437 ath9k_calculate_summary_state(sc, avp->chanctx);
1438
283dd119
LB		 1439 ath9k_set_txpower(sc, NULL);
1440
141b38b6 1441 mutex_unlock(&sc->mutex);
f078f209
LR		 1442}
1443
fbab7390 1444static void ath9k_enable_ps(struct ath_softc *sc)
3f7c5c10 1445{
3069168c 1446 struct ath_hw *ah = sc->sc_ah;
ad128860 1447 struct ath_common *common = ath9k_hw_common(ah);
3069168c 1448
97f2645f 1449 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR		 1450 return;
1451
3f7c5c10 1452 sc->ps_enabled = true;
3069168c
PR		 1453 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1454 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1455 ah->imask |= ATH9K_INT_TIM_TIMER;
72d874c6 1456 ath9k_hw_set_interrupts(ah);
3f7c5c10 1457 }
fdf76622 1458 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1459 }
ad128860 1460 ath_dbg(common, PS, "PowerSave enabled\n");
3f7c5c10
SB		 1461}
1462
845d708e
SB		 1463static void ath9k_disable_ps(struct ath_softc *sc)
1464{
1465 struct ath_hw *ah = sc->sc_ah;
ad128860 1466 struct ath_common *common = ath9k_hw_common(ah);
845d708e 1467
97f2645f 1468 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR		 1469 return;
1470
845d708e
SB		 1471 sc->ps_enabled = false;
1472 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1473 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1474 ath9k_hw_setrxabort(ah, 0);
1475 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1476 PS_WAIT_FOR_CAB |
1477 PS_WAIT_FOR_PSPOLL_DATA |
1478 PS_WAIT_FOR_TX_ACK);
1479 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1480 ah->imask &= ~ATH9K_INT_TIM_TIMER;
72d874c6 1481 ath9k_hw_set_interrupts(ah);
845d708e
SB		 1482 }
1483 }
ad128860 1484 ath_dbg(common, PS, "PowerSave disabled\n");
845d708e
SB		 1485}
1486
e8975581 1487static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1488{
9ac58615 1489 struct ath_softc *sc = hw->priv;
3430098a
FF		 1490 struct ath_hw *ah = sc->sc_ah;
1491 struct ath_common *common = ath9k_hw_common(ah);
e8975581 1492 struct ieee80211_conf *conf = &hw->conf;
fbbcd146 1493 struct ath_chanctx *ctx = sc->cur_chan;
f078f209 1494
c0c11741 1495 ath9k_ps_wakeup(sc);
aa33de09 1496 mutex_lock(&sc->mutex);
141b38b6 1497
daa1b6ee 1498 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
7545daf4 1499 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
b73f3e78 1500 if (sc->ps_idle) {
daa1b6ee 1501 ath_cancel_work(sc);
b73f3e78
RM		 1502 ath9k_stop_btcoex(sc);
1503 } else {
1504 ath9k_start_btcoex(sc);
75600abf
FF		 1505 /*
1506 * The chip needs a reset to properly wake up from
1507 * full sleep
1508 */
39305635 1509 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
b73f3e78 1510 }
daa1b6ee 1511 }
64839170 1512
e7824a50
LR		 1513 /*
1514 * We just prepare to enable PS. We have to wait until our AP has
1515 * ACK'd our null data frame to disable RX otherwise we'll ignore
1516 * those ACKs and end up retransmitting the same null data frames.
1517 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1518 */
3cbb5dd7 1519 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR		 1520 unsigned long flags;
1521 spin_lock_irqsave(&sc->sc_pm_lock, flags);
fbab7390
SB		 1522 if (conf->flags & IEEE80211_CONF_PS)
1523 ath9k_enable_ps(sc);
845d708e
SB		 1524 else
1525 ath9k_disable_ps(sc);
8ab2cd09 1526 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN		 1527 }
1528
199afd9d
S		 1529 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1530 if (conf->flags & IEEE80211_CONF_MONITOR) {
d2182b69 1531 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
5f841b41
RM		 1532 sc->sc_ah->is_monitoring = true;
1533 } else {
d2182b69 1534 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
5f841b41 1535 sc->sc_ah->is_monitoring = false;
199afd9d
S		 1536 }
1537 }
1538
499afacc 1539 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
fbbcd146 1540 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
bff11766 1541 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
094d05dc 1542 }
f078f209 1543
968ae2ca
RP		 1544 if (changed & IEEE80211_CONF_CHANGE_POWER)
1545 ath9k_set_txpower(sc, NULL);
1546
aa33de09 1547 mutex_unlock(&sc->mutex);
c0c11741 1548 ath9k_ps_restore(sc);
141b38b6 1549
f078f209
LR		 1550 return 0;
1551}
1552
8feceb67 1553#define SUPPORTED_FILTERS \
df140465 1554 (FIF_ALLMULTI | \
8feceb67 1555 FIF_CONTROL | \
af6a3fc7 1556 FIF_PSPOLL | \
8feceb67
VT		 1557 FIF_OTHER_BSS | \
1558 FIF_BCN_PRBRESP_PROMISC | \
9c1d8e4a 1559 FIF_PROBE_REQ | \
c01c320d 1560 FIF_MCAST_ACTION | \
8feceb67 1561 FIF_FCSFAIL)
c83be688 1562
8feceb67
VT		 1563/* FIXME: sc->sc_full_reset ? */
1564static void ath9k_configure_filter(struct ieee80211_hw *hw,
1565 unsigned int changed_flags,
1566 unsigned int *total_flags,
3ac64bee 1567 u64 multicast)
8feceb67 1568{
9ac58615 1569 struct ath_softc *sc = hw->priv;
f3771c08 1570 struct ath_chanctx *ctx;
8feceb67 1571 u32 rfilt;
f078f209 1572
8feceb67
VT		 1573 changed_flags &= SUPPORTED_FILTERS;
1574 *total_flags &= SUPPORTED_FILTERS;
f078f209 1575
fce34430 1576 spin_lock_bh(&sc->chan_lock);
f3771c08
JD		 1577 ath_for_each_chanctx(sc, ctx)
1578 ctx->rxfilter = *total_flags;
1738203e
JD		 1579#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1580 sc->offchannel.chan.rxfilter = *total_flags;
1581#endif
fce34430
SM		 1582 spin_unlock_bh(&sc->chan_lock);
1583
aa68aeaa 1584 ath9k_ps_wakeup(sc);
8feceb67
VT		 1585 rfilt = ath_calcrxfilter(sc);
1586 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1587 ath9k_ps_restore(sc);
f078f209 1588
d2182b69
JP		 1589 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1590 rfilt);
8feceb67 1591}
f078f209 1592
4ca77860
JB		 1593static int ath9k_sta_add(struct ieee80211_hw *hw,
1594 struct ieee80211_vif *vif,
1595 struct ieee80211_sta *sta)
8feceb67 1596{
9ac58615 1597 struct ath_softc *sc = hw->priv;
93ae2dd2
FF		 1598 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1599 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1600 struct ieee80211_key_conf ps_key = { };
4ef69d03 1601 int key;
f078f209 1602
7e1e3864 1603 ath_node_attach(sc, sta, vif);
f59a59fe
FF		 1604
1605 if (vif->type != NL80211_IFTYPE_AP &&
1606 vif->type != NL80211_IFTYPE_AP_VLAN)
1607 return 0;
1608
4ef69d03 1609 key = ath_key_config(common, vif, sta, &ps_key);
4bbf4414 1610 if (key > 0) {
4ef69d03 1611 an->ps_key = key;
4bbf4414
RM		 1612 an->key_idx[0] = key;
1613 }
4ca77860
JB		 1614
1615 return 0;
1616}
1617
93ae2dd2
FF		 1618static void ath9k_del_ps_key(struct ath_softc *sc,
1619 struct ieee80211_vif *vif,
1620 struct ieee80211_sta *sta)
1621{
1622 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1623 struct ath_node *an = (struct ath_node *) sta->drv_priv;
93ae2dd2
FF		 1624
1625 if (!an->ps_key)
1626 return;
1627
144cd24d 1628 ath_key_delete(common, an->ps_key);
4ef69d03 1629 an->ps_key = 0;
4bbf4414 1630 an->key_idx[0] = 0;
93ae2dd2
FF		 1631}
1632
4ca77860
JB		 1633static int ath9k_sta_remove(struct ieee80211_hw *hw,
1634 struct ieee80211_vif *vif,
1635 struct ieee80211_sta *sta)
1636{
9ac58615 1637 struct ath_softc *sc = hw->priv;
4ca77860 1638
93ae2dd2 1639 ath9k_del_ps_key(sc, vif, sta);
4ca77860
JB		 1640 ath_node_detach(sc, sta);
1641
1642 return 0;
f078f209
LR		 1643}
1644
df3c6eb3
SM		 1645static int ath9k_sta_state(struct ieee80211_hw *hw,
1646 struct ieee80211_vif *vif,
1647 struct ieee80211_sta *sta,
1648 enum ieee80211_sta_state old_state,
1649 enum ieee80211_sta_state new_state)
1650{
1651 struct ath_softc *sc = hw->priv;
1652 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1653 int ret = 0;
1654
7711aaf0
FF		 1655 if (old_state == IEEE80211_STA_NOTEXIST &&
1656 new_state == IEEE80211_STA_NONE) {
df3c6eb3
SM		 1657 ret = ath9k_sta_add(hw, vif, sta);
1658 ath_dbg(common, CONFIG,
1659 "Add station: %pM\n", sta->addr);
7711aaf0
FF		 1660 } else if (old_state == IEEE80211_STA_NONE &&
1661 new_state == IEEE80211_STA_NOTEXIST) {
df3c6eb3
SM		 1662 ret = ath9k_sta_remove(hw, vif, sta);
1663 ath_dbg(common, CONFIG,
1664 "Remove station: %pM\n", sta->addr);
1665 }
1666
b8f9279b 1667 if (ath9k_is_chanctx_enabled()) {
91e6ceb3
SM		 1668 if (vif->type == NL80211_IFTYPE_STATION) {
1669 if (old_state == IEEE80211_STA_ASSOC &&
1670 new_state == IEEE80211_STA_AUTHORIZED)
1671 ath_chanctx_event(sc, vif,
1672 ATH_CHANCTX_EVENT_AUTHORIZED);
1673 }
b8f9279b
SM		 1674 }
1675
df3c6eb3
SM		 1676 return ret;
1677}
1678
4bbf4414
RM		 1679static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1680 struct ath_node *an,
1681 bool set)
1682{
1683 int i;
1684
1685 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1686 if (!an->key_idx[i])
1687 continue;
1688 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1689 }
1690}
1691
5519541d
FF		 1692static void ath9k_sta_notify(struct ieee80211_hw *hw,
1693 struct ieee80211_vif *vif,
1694 enum sta_notify_cmd cmd,
1695 struct ieee80211_sta *sta)
1696{
1697 struct ath_softc *sc = hw->priv;
1698 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1699
1700 switch (cmd) {
1701 case STA_NOTIFY_SLEEP:
1702 an->sleeping = true;
042ec453 1703 ath_tx_aggr_sleep(sta, sc, an);
4bbf4414 1704 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
5519541d
FF		 1705 break;
1706 case STA_NOTIFY_AWAKE:
4bbf4414 1707 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
5519541d
FF		 1708 an->sleeping = false;
1709 ath_tx_aggr_wakeup(sc, an);
1710 break;
1711 }
1712}
1713
8a3a3c85
EP		 1714static int ath9k_conf_tx(struct ieee80211_hw *hw,
1715 struct ieee80211_vif *vif, u16 queue,
8feceb67 1716 const struct ieee80211_tx_queue_params *params)
f078f209 1717{
9ac58615 1718 struct ath_softc *sc = hw->priv;
c46917bb 1719 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
066dae93 1720 struct ath_txq *txq;
8feceb67 1721 struct ath9k_tx_queue_info qi;
066dae93 1722 int ret = 0;
f078f209 1723
bea843c7 1724 if (queue >= IEEE80211_NUM_ACS)
8feceb67 1725 return 0;
f078f209 1726
066dae93
FF		 1727 txq = sc->tx.txq_map[queue];
1728
96f372c9 1729 ath9k_ps_wakeup(sc);
141b38b6
S		 1730 mutex_lock(&sc->mutex);
1731
1ffb0610
S		 1732 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1733
8feceb67
VT		 1734 qi.tqi_aifs = params->aifs;
1735 qi.tqi_cwmin = params->cw_min;
1736 qi.tqi_cwmax = params->cw_max;
531bd079 1737 qi.tqi_burstTime = params->txop * 32;
f078f209 1738
d2182b69 1739 ath_dbg(common, CONFIG,
226afe68
JP		 1740 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1741 queue, txq->axq_qnum, params->aifs, params->cw_min,
1742 params->cw_max, params->txop);
f078f209 1743
aa5955c3 1744 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
066dae93 1745 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
8feceb67 1746 if (ret)
3800276a 1747 ath_err(common, "TXQ Update failed\n");
f078f209 1748
141b38b6 1749 mutex_unlock(&sc->mutex);
96f372c9 1750 ath9k_ps_restore(sc);
141b38b6 1751
8feceb67
VT		 1752 return ret;
1753}
f078f209 1754
8feceb67
VT		 1755static int ath9k_set_key(struct ieee80211_hw *hw,
1756 enum set_key_cmd cmd,
dc822b5d
JB		 1757 struct ieee80211_vif *vif,
1758 struct ieee80211_sta *sta,
8feceb67
VT		 1759 struct ieee80211_key_conf *key)
1760{
9ac58615 1761 struct ath_softc *sc = hw->priv;
c46917bb 1762 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4bbf4414
RM		 1763 struct ath_node *an = NULL;
1764 int ret = 0, i;
f078f209 1765
3e6109c5 1766 if (ath9k_modparam_nohwcrypt)
b3bd89ce
JM		 1767 return -ENOSPC;
1768
5bd5e9a6
CYY		 1769 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1770 vif->type == NL80211_IFTYPE_MESH_POINT) &&
cfdc9a8b
JM		 1771 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1772 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1773 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1774 /*
1775 * For now, disable hw crypto for the RSN IBSS group keys. This
1776 * could be optimized in the future to use a modified key cache
1777 * design to support per-STA RX GTK, but until that gets
1778 * implemented, use of software crypto for group addressed
1779 * frames is a acceptable to allow RSN IBSS to be used.
1780 */
1781 return -EOPNOTSUPP;
1782 }
1783
4bad3a20
AW		 1784 /* There may be MPDUs queued for the outgoing PTK key. Flush queues to
1785 * make sure these are not send unencrypted or with a wrong (new) key
1786 */
1787 if (cmd == DISABLE_KEY && key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
1788 ieee80211_stop_queues(hw);
1789 ath9k_flush(hw, vif, 0, true);
1790 ieee80211_wake_queues(hw);
1791 }
1792
141b38b6 1793 mutex_lock(&sc->mutex);
3cbb5dd7 1794 ath9k_ps_wakeup(sc);
4bbf4414
RM		 1795 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1796 if (sta)
1797 an = (struct ath_node *)sta->drv_priv;
f078f209 1798
ca284802
JM		 1799 /* Delete pending key cache entries if no more frames are pointing to
1800 * them in TXQs.
1801 */
1802 for (i = 0; i < ATH_KEYMAX; i++)
1803 ath9k_pending_key_del(sc, i);
1804
8feceb67
VT		 1805 switch (cmd) {
1806 case SET_KEY:
93ae2dd2
FF		 1807 if (sta)
1808 ath9k_del_ps_key(sc, vif, sta);
1809
4bbf4414 1810 key->hw_key_idx = 0;
040e539e 1811 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM		 1812 if (ret >= 0) {
1813 key->hw_key_idx = ret;
8feceb67
VT		 1814 /* push IV and Michael MIC generation to stack */
1815 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1816 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1817 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e6510b11 1818 if (sc->sc_ah->sw_mgmt_crypto_tx &&
97359d12 1819 key->cipher == WLAN_CIPHER_SUITE_CCMP)
e548c49e 1820 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6ace2891 1821 ret = 0;
8feceb67 1822 }
4bbf4414
RM		 1823 if (an && key->hw_key_idx) {
1824 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1825 if (an->key_idx[i])
1826 continue;
1827 an->key_idx[i] = key->hw_key_idx;
1828 break;
1829 }
1830 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1831 }
8feceb67
VT		 1832 break;
1833 case DISABLE_KEY:
ca284802
JM		 1834 if (ath9k_txq_has_key(sc, key->hw_key_idx)) {
1835 /* Delay key cache entry deletion until there are no
1836 * remaining TXQ frames pointing to this entry.
1837 */
1838 set_bit(key->hw_key_idx, sc->sc_ah->pending_del_keymap);
1839 ath_hw_keysetmac(common, key->hw_key_idx, NULL);
1840 } else {
1841 ath_key_delete(common, key->hw_key_idx);
1842 }
4bbf4414
RM		 1843 if (an) {
1844 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1845 if (an->key_idx[i] != key->hw_key_idx)
1846 continue;
1847 an->key_idx[i] = 0;
1848 break;
1849 }
1850 }
1851 key->hw_key_idx = 0;
8feceb67
VT		 1852 break;
1853 default:
1854 ret = -EINVAL;
1855 }
f078f209 1856
3cbb5dd7 1857 ath9k_ps_restore(sc);
141b38b6
S		 1858 mutex_unlock(&sc->mutex);
1859
8feceb67
VT		 1860 return ret;
1861}
6c43c090 1862
8feceb67
VT		 1863static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1864 struct ieee80211_vif *vif,
1865 struct ieee80211_bss_conf *bss_conf,
1866 u32 changed)
1867{
da0d45f7
SM		 1868#define CHECK_ANI \
1869 (BSS_CHANGED_ASSOC | \
1870 BSS_CHANGED_IBSS | \
1871 BSS_CHANGED_BEACON_ENABLED)
1872
9ac58615 1873 struct ath_softc *sc = hw->priv;
2d0ddec5 1874 struct ath_hw *ah = sc->sc_ah;
1510718d 1875 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1876 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1877 int slottime;
f078f209 1878
96f372c9 1879 ath9k_ps_wakeup(sc);
141b38b6
S		 1880 mutex_lock(&sc->mutex);
1881
9f61903c 1882 if (changed & BSS_CHANGED_ASSOC) {
6c43c090
SM		 1883 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1884 bss_conf->bssid, bss_conf->assoc);
1885
62ae1aef 1886 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
cb35582a
SM		 1887 avp->aid = bss_conf->aid;
1888 avp->assoc = bss_conf->assoc;
1889
9a9c4fbc 1890 ath9k_calculate_summary_state(sc, avp->chanctx);
c6089ccc 1891 }
2d0ddec5 1892
862a336c
JK		 1893 if ((changed & BSS_CHANGED_IBSS) ||
1894 (changed & BSS_CHANGED_OCB)) {
2e5ef459
RM		 1895 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1896 common->curaid = bss_conf->aid;
1897 ath9k_hw_write_associd(sc->sc_ah);
2e5ef459
RM		 1898 }
1899
ef4ad633 1900 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
9198cf4a
RM		 1901 (changed & BSS_CHANGED_BEACON_INT) ||
1902 (changed & BSS_CHANGED_BEACON_INFO)) {
cfda2d8e 1903 ath9k_calculate_summary_state(sc, avp->chanctx);
9a9c4fbc 1904 }
0005baf4 1905
9a9c4fbc
RM		 1906 if ((avp->chanctx == sc->cur_chan) &&
1907 (changed & BSS_CHANGED_ERP_SLOT)) {
0005baf4
FF		 1908 if (bss_conf->use_short_slot)
1909 slottime = 9;
1910 else
1911 slottime = 20;
11b0ac2e 1912
0005baf4
FF		 1913 if (vif->type == NL80211_IFTYPE_AP) {
1914 /*
1915 * Defer update, so that connected stations can adjust
1916 * their settings at the same time.
1917 * See beacon.c for more details
1918 */
1919 sc->beacon.slottime = slottime;
1920 sc->beacon.updateslot = UPDATE;
1921 } else {
1922 ah->slottime = slottime;
1923 ath9k_hw_init_global_settings(ah);
1924 }
2d0ddec5
JB		 1925 }
1926
c7dd40c9
SM		 1927 if (changed & BSS_CHANGED_P2P_PS)
1928 ath9k_p2p_bss_info_changed(sc, vif);
d463af4a 1929
da0d45f7
SM		 1930 if (changed & CHECK_ANI)
1931 ath_check_ani(sc);
1932
283dd119
LB		 1933 if (changed & BSS_CHANGED_TXPOWER) {
1934 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1935 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1936 ath9k_set_txpower(sc, vif);
1937 }
1938
141b38b6 1939 mutex_unlock(&sc->mutex);
96f372c9 1940 ath9k_ps_restore(sc);
da0d45f7
SM		 1941
1942#undef CHECK_ANI
8feceb67 1943}
f078f209 1944
37a41b4a 1945static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1946{
9ac58615 1947 struct ath_softc *sc = hw->priv;
9580cb88 1948 struct ath_vif *avp = (void *)vif->drv_priv;
8feceb67 1949 u64 tsf;
f078f209 1950
141b38b6 1951 mutex_lock(&sc->mutex);
9abbfb27 1952 ath9k_ps_wakeup(sc);
9580cb88
BB		 1953 /* Get current TSF either from HW or kernel time. */
1954 if (sc->cur_chan == avp->chanctx) {
1955 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1956 } else {
1957 tsf = sc->cur_chan->tsf_val +
1958 ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts, NULL);
1959 }
7fde5122 1960 tsf += le64_to_cpu(avp->tsf_adjust);
9abbfb27 1961 ath9k_ps_restore(sc);
141b38b6 1962 mutex_unlock(&sc->mutex);
f078f209 1963
8feceb67
VT		 1964 return tsf;
1965}
f078f209 1966
37a41b4a
EP		 1967static void ath9k_set_tsf(struct ieee80211_hw *hw,
1968 struct ieee80211_vif *vif,
1969 u64 tsf)
3b5d665b 1970{
9ac58615 1971 struct ath_softc *sc = hw->priv;
9580cb88 1972 struct ath_vif *avp = (void *)vif->drv_priv;
3b5d665b 1973
141b38b6 1974 mutex_lock(&sc->mutex);
9abbfb27 1975 ath9k_ps_wakeup(sc);
7fde5122 1976 tsf -= le64_to_cpu(avp->tsf_adjust);
fe041deb 1977 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
9580cb88
BB		 1978 if (sc->cur_chan == avp->chanctx)
1979 ath9k_hw_settsf64(sc->sc_ah, tsf);
1980 avp->chanctx->tsf_val = tsf;
9abbfb27 1981 ath9k_ps_restore(sc);
141b38b6 1982 mutex_unlock(&sc->mutex);
3b5d665b
AF		 1983}
1984
37a41b4a 1985static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8feceb67 1986{
9ac58615 1987 struct ath_softc *sc = hw->priv;
9580cb88 1988 struct ath_vif *avp = (void *)vif->drv_priv;
c83be688 1989
141b38b6 1990 mutex_lock(&sc->mutex);
21526d57
LR		 1991
1992 ath9k_ps_wakeup(sc);
fe041deb 1993 ktime_get_raw_ts64(&avp->chanctx->tsf_ts);
9580cb88
BB		 1994 if (sc->cur_chan == avp->chanctx)
1995 ath9k_hw_reset_tsf(sc->sc_ah);
1996 avp->chanctx->tsf_val = 0;
21526d57
LR		 1997 ath9k_ps_restore(sc);
1998
141b38b6 1999 mutex_unlock(&sc->mutex);
8feceb67 2000}
f078f209 2001
8feceb67 2002static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2003 struct ieee80211_vif *vif,
50ea05ef 2004 struct ieee80211_ampdu_params *params)
8feceb67 2005{
9ac58615 2006 struct ath_softc *sc = hw->priv;
1e929d3e 2007 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
16e23428 2008 bool flush = false;
8feceb67 2009 int ret = 0;
50ea05ef 2010 struct ieee80211_sta *sta = params->sta;
50f08edf 2011 struct ath_node *an = (struct ath_node *)sta->drv_priv;
50ea05ef
SS		 2012 enum ieee80211_ampdu_mlme_action action = params->action;
2013 u16 tid = params->tid;
2014 u16 *ssn = &params->ssn;
50f08edf 2015 struct ath_atx_tid *atid;
f078f209 2016
7ca7c776 2017 mutex_lock(&sc->mutex);
85ad181e 2018
8feceb67
VT		 2019 switch (action) {
2020 case IEEE80211_AMPDU_RX_START:
8feceb67
VT		 2021 break;
2022 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2023 break;
2024 case IEEE80211_AMPDU_TX_START:
1e929d3e
SM		 2025 if (ath9k_is_chanctx_enabled()) {
2026 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2027 ret = -EBUSY;
2028 break;
2029 }
2030 }
8b685ba9 2031 ath9k_ps_wakeup(sc);
231c3a1f
FF		 2032 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2033 if (!ret)
2ce113de 2034 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE;
8b685ba9 2035 ath9k_ps_restore(sc);
8feceb67 2036 break;
18b559d5
JB		 2037 case IEEE80211_AMPDU_TX_STOP_FLUSH:
2038 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
16e23428 2039 flush = true;
221af813 2040 fallthrough;
16e23428 2041 case IEEE80211_AMPDU_TX_STOP_CONT:
8b685ba9 2042 ath9k_ps_wakeup(sc);
f83da965 2043 ath_tx_aggr_stop(sc, sta, tid);
08c96abd 2044 if (!flush)
16e23428 2045 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2046 ath9k_ps_restore(sc);
8feceb67 2047 break;
b1720231 2048 case IEEE80211_AMPDU_TX_OPERATIONAL:
50f08edf
THJ		 2049 atid = ath_node_to_tid(an, tid);
2050 atid->baw_size = IEEE80211_MIN_AMPDU_BUF <<
2051 sta->ht_cap.ampdu_factor;
8469cdef 2052 break;
8feceb67 2053 default:
3800276a 2054 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
8feceb67
VT		 2055 }
2056
7ca7c776 2057 mutex_unlock(&sc->mutex);
85ad181e 2058
8feceb67 2059 return ret;
f078f209
LR		 2060}
2061
62dad5b0
BP		 2062static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2063 struct survey_info *survey)
2064{
9ac58615 2065 struct ath_softc *sc = hw->priv;
3430098a 2066 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39162dbe 2067 struct ieee80211_supported_band *sband;
3430098a 2068 struct ieee80211_channel *chan;
ba24d63d 2069 unsigned long flags;
3430098a
FF		 2070 int pos;
2071
97f2645f 2072 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR		 2073 return -EOPNOTSUPP;
2074
ba24d63d 2075 spin_lock_irqsave(&common->cc_lock, flags);
3430098a
FF		 2076 if (idx == 0)
2077 ath_update_survey_stats(sc);
39162dbe 2078
57fbcce3 2079 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
39162dbe
FF		 2080 if (sband && idx >= sband->n_channels) {
2081 idx -= sband->n_channels;
2082 sband = NULL;
2083 }
62dad5b0 2084
39162dbe 2085 if (!sband)
57fbcce3 2086 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
62dad5b0 2087
3430098a 2088 if (!sband || idx >= sband->n_channels) {
ba24d63d 2089 spin_unlock_irqrestore(&common->cc_lock, flags);
3430098a 2090 return -ENOENT;
4f1a5a4b 2091 }
62dad5b0 2092
3430098a
FF		 2093 chan = &sband->channels[idx];
2094 pos = chan->hw_value;
2095 memcpy(survey, &sc->survey[pos], sizeof(*survey));
2096 survey->channel = chan;
ba24d63d 2097 spin_unlock_irqrestore(&common->cc_lock, flags);
3430098a 2098
62dad5b0
BP		 2099 return 0;
2100}
2101
24a1936b
LB		 2102static void ath9k_enable_dynack(struct ath_softc *sc)
2103{
2104#ifdef CONFIG_ATH9K_DYNACK
2105 u32 rfilt;
2106 struct ath_hw *ah = sc->sc_ah;
2107
2108 ath_dynack_reset(ah);
2109
2110 ah->dynack.enabled = true;
2111 rfilt = ath_calcrxfilter(sc);
2112 ath9k_hw_setrxfilter(ah, rfilt);
2113#endif
2114}
2115
a4bcaf55
LB		 2116static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
2117 s16 coverage_class)
e239d859 2118{
9ac58615 2119 struct ath_softc *sc = hw->priv;
e239d859
FF		 2120 struct ath_hw *ah = sc->sc_ah;
2121
97f2645f 2122 if (IS_ENABLED(CONFIG_ATH9K_TX99))
89f927af
LR		 2123 return;
2124
e239d859 2125 mutex_lock(&sc->mutex);
8b2a3827 2126
24a1936b
LB		 2127 if (coverage_class >= 0) {
2128 ah->coverage_class = coverage_class;
2129 if (ah->dynack.enabled) {
2130 u32 rfilt;
2131
2132 ah->dynack.enabled = false;
2133 rfilt = ath_calcrxfilter(sc);
2134 ath9k_hw_setrxfilter(ah, rfilt);
2135 }
2136 ath9k_ps_wakeup(sc);
2137 ath9k_hw_init_global_settings(ah);
2138 ath9k_ps_restore(sc);
2139 } else if (!ah->dynack.enabled) {
2140 ath9k_enable_dynack(sc);
2141 }
8b2a3827 2142
e239d859
FF		 2143 mutex_unlock(&sc->mutex);
2144}
2145
e2d389b5
SM		 2146static bool ath9k_has_tx_pending(struct ath_softc *sc,
2147 bool sw_pending)
10e23181 2148{
f7838073 2149 int i, npend = 0;
10e23181
FF		 2150
2151 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2152 if (!ATH_TXQ_SETUP(sc, i))
2153 continue;
2154
e2d389b5
SM		 2155 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2156 sw_pending);
10e23181
FF		 2157 if (npend)
2158 break;
2159 }
2160
2161 return !!npend;
2162}
2163
77be2c54
EG		 2164static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2165 u32 queues, bool drop)
bff11766
FF		 2166{
2167 struct ath_softc *sc = hw->priv;
25f3bc7d
SM		 2168 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2169
2170 if (ath9k_is_chanctx_enabled()) {
2171 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2172 goto flush;
bff11766 2173
25f3bc7d
SM		 2174 /*
2175 * If MCC is active, extend the flush timeout
2176 * and wait for the HW/SW queues to become
2177 * empty. This needs to be done outside the
2178 * sc->mutex lock to allow the channel scheduler
2179 * to switch channel contexts.
2180 *
2181 * The vif queues have been stopped in mac80211,
2182 * so there won't be any incoming frames.
2183 */
2184 __ath9k_flush(hw, queues, drop, true, true);
2185 return;
2186 }
2187flush:
bff11766 2188 mutex_lock(&sc->mutex);
25f3bc7d 2189 __ath9k_flush(hw, queues, drop, true, false);
bff11766
FF		 2190 mutex_unlock(&sc->mutex);
2191}
2192
e2d389b5 2193void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
25f3bc7d 2194 bool sw_pending, bool timeout_override)
69081624 2195{
69081624 2196 struct ath_softc *sc = hw->priv;
99aa55b6
MSS		 2197 struct ath_hw *ah = sc->sc_ah;
2198 struct ath_common *common = ath9k_hw_common(ah);
2fae0d9f 2199 int timeout;
2f6fc351 2200 bool drain_txq;
69081624 2201
d63ffc45 2202 cancel_delayed_work_sync(&sc->hw_check_work);
69081624 2203
6a6b3f3e 2204 if (ah->ah_flags & AH_UNPLUGGED) {
d2182b69 2205 ath_dbg(common, ANY, "Device has been unplugged!\n");
6a6b3f3e
MSS		 2206 return;
2207 }
2208
eefa01dd 2209 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
d2182b69 2210 ath_dbg(common, ANY, "Device not present\n");
99aa55b6
MSS		 2211 return;
2212 }
2213
2fae0d9f 2214 spin_lock_bh(&sc->chan_lock);
25f3bc7d
SM		 2215 if (timeout_override)
2216 timeout = HZ / 5;
2217 else
2218 timeout = sc->cur_chan->flush_timeout;
2fae0d9f
SM		 2219 spin_unlock_bh(&sc->chan_lock);
2220
2221 ath_dbg(common, CHAN_CTX,
2222 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2223
e2d389b5 2224 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
10e23181
FF		 2225 timeout) > 0)
2226 drop = false;
69081624 2227
9df0d6a2
FF		 2228 if (drop) {
2229 ath9k_ps_wakeup(sc);
2230 spin_lock_bh(&sc->sc_pcu_lock);
1381559b 2231 drain_txq = ath_drain_all_txq(sc);
9df0d6a2 2232 spin_unlock_bh(&sc->sc_pcu_lock);
9adcf440 2233
9df0d6a2 2234 if (!drain_txq)
5555c955 2235 ath_reset(sc, NULL);
9adcf440 2236
9df0d6a2 2237 ath9k_ps_restore(sc);
9df0d6a2 2238 }
d78f4b3e 2239
d63ffc45
FF		 2240 ieee80211_queue_delayed_work(hw, &sc->hw_check_work,
2241 ATH_HW_CHECK_POLL_INT);
69081624
VT		 2242}
2243
15b91e83
VN		 2244static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2245{
2246 struct ath_softc *sc = hw->priv;
15b91e83 2247
e2d389b5 2248 return ath9k_has_tx_pending(sc, true);
15b91e83
VN		 2249}
2250
5595f119 2251static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
ba4903f9
FF		 2252{
2253 struct ath_softc *sc = hw->priv;
2254 struct ath_hw *ah = sc->sc_ah;
2255 struct ieee80211_vif *vif;
2256 struct ath_vif *avp;
2257 struct ath_buf *bf;
2258 struct ath_tx_status ts;
4286df60 2259 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
ba4903f9
FF		 2260 int status;
2261
2262 vif = sc->beacon.bslot[0];
2263 if (!vif)
2264 return 0;
2265
aa45fe96 2266 if (!vif->bss_conf.enable_beacon)
ba4903f9
FF		 2267 return 0;
2268
aa45fe96
SM		 2269 avp = (void *)vif->drv_priv;
2270
4286df60 2271 if (!sc->beacon.tx_processed && !edma) {
ba4903f9
FF		 2272 tasklet_disable(&sc->bcon_tasklet);
2273
2274 bf = avp->av_bcbuf;
2275 if (!bf || !bf->bf_mpdu)
2276 goto skip;
2277
2278 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2279 if (status == -EINPROGRESS)
2280 goto skip;
2281
2282 sc->beacon.tx_processed = true;
2283 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2284
2285skip:
2286 tasklet_enable(&sc->bcon_tasklet);
2287 }
2288
2289 return sc->beacon.tx_last;
2290}
2291
52c94f41
MSS		 2292static int ath9k_get_stats(struct ieee80211_hw *hw,
2293 struct ieee80211_low_level_stats *stats)
2294{
2295 struct ath_softc *sc = hw->priv;
2296 struct ath_hw *ah = sc->sc_ah;
2297 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2298
2299 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2300 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2301 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2302 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2303 return 0;
2304}
2305
43c35284
FF		 2306static u32 fill_chainmask(u32 cap, u32 new)
2307{
2308 u32 filled = 0;
2309 int i;
2310
2311 for (i = 0; cap && new; i++, cap >>= 1) {
2312 if (!(cap & BIT(0)))
2313 continue;
2314
2315 if (new & BIT(0))
2316 filled |= BIT(i);
2317
2318 new >>= 1;
2319 }
2320
2321 return filled;
2322}
2323
5d9c7e3c
FF		 2324static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2325{
fea92cbf
FF		 2326 if (AR_SREV_9300_20_OR_LATER(ah))
2327 return true;
2328
5d9c7e3c
FF		 2329 switch (val & 0x7) {
2330 case 0x1:
2331 case 0x3:
2332 case 0x7:
2333 return true;
2334 case 0x2:
2335 return (ah->caps.rx_chainmask == 1);
2336 default:
2337 return false;
2338 }
2339}
2340
43c35284
FF		 2341static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2342{
2343 struct ath_softc *sc = hw->priv;
2344 struct ath_hw *ah = sc->sc_ah;
2345
5d9c7e3c
FF		 2346 if (ah->caps.rx_chainmask != 1)
2347 rx_ant |= tx_ant;
2348
2349 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
43c35284
FF		 2350 return -EINVAL;
2351
2352 sc->ant_rx = rx_ant;
2353 sc->ant_tx = tx_ant;
2354
2355 if (ah->caps.rx_chainmask == 1)
2356 return 0;
2357
2358 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2359 if (AR_SREV_9100(ah))
2360 ah->rxchainmask = 0x7;
2361 else
2362 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2363
2364 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
b57ba3b2 2365 ath9k_cmn_reload_chainmask(ah);
43c35284
FF		 2366
2367 return 0;
2368}
2369
2370static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2371{
2372 struct ath_softc *sc = hw->priv;
2373
2374 *tx_ant = sc->ant_tx;
2375 *rx_ant = sc->ant_rx;
2376 return 0;
2377}
2378
a344d677
JB		 2379static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2380 struct ieee80211_vif *vif,
2381 const u8 *mac_addr)
e93d083f
SW		 2382{
2383 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2384 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2385 set_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f
SW		 2386}
2387
a344d677
JB		 2388static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2389 struct ieee80211_vif *vif)
e93d083f
SW		 2390{
2391 struct ath_softc *sc = hw->priv;
eefa01dd
OR		 2392 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2393 clear_bit(ATH_OP_SCANNING, &common->op_flags);
e93d083f 2394}
b11e640a 2395
499afacc
SM		 2396#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2397
6185672a
SM		 2398static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2399{
2400 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2401
2402 if (sc->offchannel.roc_vif) {
2403 ath_dbg(common, CHAN_CTX,
2404 "%s: Aborting RoC\n", __func__);
2405
2406 del_timer_sync(&sc->offchannel.timer);
2407 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
d83520b7 2408 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
6185672a
SM		 2409 }
2410
2411 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2412 ath_dbg(common, CHAN_CTX,
2413 "%s: Aborting HW scan\n", __func__);
2414
2415 del_timer_sync(&sc->offchannel.timer);
2416 ath_scan_complete(sc, true);
2417 }
2418}
2419
78b21949 2420static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
855df36d 2421 struct ieee80211_scan_request *hw_req)
78b21949 2422{
855df36d 2423 struct cfg80211_scan_request *req = &hw_req->req;
78b21949
FF		 2424 struct ath_softc *sc = hw->priv;
2425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2426 int ret = 0;
2427
2428 mutex_lock(&sc->mutex);
2429
2430 if (WARN_ON(sc->offchannel.scan_req)) {
2431 ret = -EBUSY;
2432 goto out;
2433 }
2434
2435 ath9k_ps_wakeup(sc);
2436 set_bit(ATH_OP_SCANNING, &common->op_flags);
2437 sc->offchannel.scan_vif = vif;
2438 sc->offchannel.scan_req = req;
2439 sc->offchannel.scan_idx = 0;
78b21949 2440
bc81d43a
SM		 2441 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2442 vif->addr);
2443
2444 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2445 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
405393cf 2446 ath_offchannel_next(sc);
bc81d43a 2447 }
78b21949
FF		 2448
2449out:
2450 mutex_unlock(&sc->mutex);
2451
2452 return ret;
2453}
2454
2455static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2456 struct ieee80211_vif *vif)
2457{
2458 struct ath_softc *sc = hw->priv;
bc81d43a
SM		 2459 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2460
2461 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
78b21949
FF		 2462
2463 mutex_lock(&sc->mutex);
2464 del_timer_sync(&sc->offchannel.timer);
2465 ath_scan_complete(sc, true);
2466 mutex_unlock(&sc->mutex);
2467}
2468
405393cf
FF		 2469static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2470 struct ieee80211_vif *vif,
2471 struct ieee80211_channel *chan, int duration,
2472 enum ieee80211_roc_type type)
2473{
2474 struct ath_softc *sc = hw->priv;
bc81d43a 2475 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2476 int ret = 0;
2477
2478 mutex_lock(&sc->mutex);
2479
2480 if (WARN_ON(sc->offchannel.roc_vif)) {
2481 ret = -EBUSY;
2482 goto out;
2483 }
2484
2485 ath9k_ps_wakeup(sc);
2486 sc->offchannel.roc_vif = vif;
2487 sc->offchannel.roc_chan = chan;
2488 sc->offchannel.roc_duration = duration;
2489
bc81d43a
SM		 2490 ath_dbg(common, CHAN_CTX,
2491 "RoC request on vif: %pM, type: %d duration: %d\n",
2492 vif->addr, type, duration);
2493
2494 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2495 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
405393cf 2496 ath_offchannel_next(sc);
bc81d43a 2497 }
405393cf
FF		 2498
2499out:
2500 mutex_unlock(&sc->mutex);
2501
2502 return ret;
2503}
2504
5db4c4b9
EG		 2505static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw,
2506 struct ieee80211_vif *vif)
405393cf
FF		 2507{
2508 struct ath_softc *sc = hw->priv;
bc81d43a 2509 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
405393cf
FF		 2510
2511 mutex_lock(&sc->mutex);
2512
bc81d43a 2513 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
405393cf
FF		 2514 del_timer_sync(&sc->offchannel.timer);
2515
2516 if (sc->offchannel.roc_vif) {
2517 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
d83520b7 2518 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
405393cf
FF		 2519 }
2520
2521 mutex_unlock(&sc->mutex);
2522
2523 return 0;
2524}
2525
39305635
FF		 2526static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2527 struct ieee80211_chanctx_conf *conf)
2528{
2529 struct ath_softc *sc = hw->priv;
bc81d43a 2530 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635 2531 struct ath_chanctx *ctx, **ptr;
3ad9c386 2532 int pos;
39305635
FF		 2533
2534 mutex_lock(&sc->mutex);
c4dc0d04
RM		 2535
2536 ath_for_each_chanctx(sc, ctx) {
2537 if (ctx->assigned)
2538 continue;
2539
2540 ptr = (void *) conf->drv_priv;
2541 *ptr = ctx;
2542 ctx->assigned = true;
3ad9c386
RM		 2543 pos = ctx - &sc->chanctx[0];
2544 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
bc81d43a
SM		 2545
2546 ath_dbg(common, CHAN_CTX,
2547 "Add channel context: %d MHz\n",
2548 conf->def.chan->center_freq);
2549
c4dc0d04 2550 ath_chanctx_set_channel(sc, ctx, &conf->def);
4c7e9aee 2551
39305635 2552 mutex_unlock(&sc->mutex);
c4dc0d04 2553 return 0;
39305635 2554 }
bc81d43a 2555
39305635 2556 mutex_unlock(&sc->mutex);
c4dc0d04 2557 return -ENOSPC;
39305635
FF		 2558}
2559
2560
2561static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2562 struct ieee80211_chanctx_conf *conf)
2563{
2564 struct ath_softc *sc = hw->priv;
bc81d43a 2565 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2566 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2567
2568 mutex_lock(&sc->mutex);
bc81d43a
SM		 2569
2570 ath_dbg(common, CHAN_CTX,
2571 "Remove channel context: %d MHz\n",
2572 conf->def.chan->center_freq);
2573
39305635 2574 ctx->assigned = false;
b18111d9 2575 ctx->hw_queue_base = 0;
73fa2f26 2576 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
bc81d43a 2577
39305635
FF		 2578 mutex_unlock(&sc->mutex);
2579}
2580
2581static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2582 struct ieee80211_chanctx_conf *conf,
2583 u32 changed)
2584{
2585 struct ath_softc *sc = hw->priv;
bc81d43a 2586 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2587 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2588
2589 mutex_lock(&sc->mutex);
bc81d43a
SM		 2590 ath_dbg(common, CHAN_CTX,
2591 "Change channel context: %d MHz\n",
2592 conf->def.chan->center_freq);
39305635
FF		 2593 ath_chanctx_set_channel(sc, ctx, &conf->def);
2594 mutex_unlock(&sc->mutex);
2595}
2596
2597static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2598 struct ieee80211_vif *vif,
2599 struct ieee80211_chanctx_conf *conf)
2600{
2601 struct ath_softc *sc = hw->priv;
bc81d43a 2602 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2603 struct ath_vif *avp = (void *)vif->drv_priv;
2604 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2605 int i;
39305635 2606
6185672a
SM		 2607 ath9k_cancel_pending_offchannel(sc);
2608
39305635 2609 mutex_lock(&sc->mutex);
bc81d43a
SM		 2610
2611 ath_dbg(common, CHAN_CTX,
2612 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2613 vif->addr, vif->type, vif->p2p,
2614 conf->def.chan->center_freq);
2615
39305635 2616 avp->chanctx = ctx;
2ce73c02 2617 ctx->nvifs_assigned++;
39305635 2618 list_add_tail(&avp->list, &ctx->vifs);
9a9c4fbc 2619 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2620 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2621 vif->hw_queue[i] = ctx->hw_queue_base + i;
bc81d43a 2622
39305635
FF		 2623 mutex_unlock(&sc->mutex);
2624
2625 return 0;
2626}
2627
2628static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2629 struct ieee80211_vif *vif,
2630 struct ieee80211_chanctx_conf *conf)
2631{
2632 struct ath_softc *sc = hw->priv;
bc81d43a 2633 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
39305635
FF		 2634 struct ath_vif *avp = (void *)vif->drv_priv;
2635 struct ath_chanctx *ctx = ath_chanctx_get(conf);
3ad9c386 2636 int ac;
39305635 2637
6185672a
SM		 2638 ath9k_cancel_pending_offchannel(sc);
2639
39305635 2640 mutex_lock(&sc->mutex);
bc81d43a
SM		 2641
2642 ath_dbg(common, CHAN_CTX,
2643 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2644 vif->addr, vif->type, vif->p2p,
2645 conf->def.chan->center_freq);
2646
39305635 2647 avp->chanctx = NULL;
2ce73c02 2648 ctx->nvifs_assigned--;
39305635 2649 list_del(&avp->list);
9a9c4fbc 2650 ath9k_calculate_summary_state(sc, ctx);
3ad9c386
RM		 2651 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2652 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
bc81d43a 2653
39305635
FF		 2654 mutex_unlock(&sc->mutex);
2655}
2656
e20a854e 2657static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
d4e36e55 2658 struct ieee80211_vif *vif,
15fae341 2659 struct ieee80211_prep_tx_info *info)
e20a854e
SM		 2660{
2661 struct ath_softc *sc = hw->priv;
2662 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2663 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
c6500ea2
SM		 2664 struct ath_beacon_config *cur_conf;
2665 struct ath_chanctx *go_ctx;
2666 unsigned long timeout;
e20a854e 2667 bool changed = false;
c6500ea2 2668 u32 beacon_int;
e20a854e
SM		 2669
2670 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2671 return;
2672
2673 if (!avp->chanctx)
2674 return;
2675
2676 mutex_lock(&sc->mutex);
2677
2678 spin_lock_bh(&sc->chan_lock);
c6500ea2 2679 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
e20a854e 2680 changed = true;
c6500ea2
SM		 2681 spin_unlock_bh(&sc->chan_lock);
2682
2683 if (!changed)
2684 goto out;
2685
6185672a 2686 ath9k_cancel_pending_offchannel(sc);
23aab0c2 2687
c6500ea2
SM		 2688 go_ctx = ath_is_go_chanctx_present(sc);
2689
2690 if (go_ctx) {
2691 /*
2692 * Wait till the GO interface gets a chance
2693 * to send out an NoA.
2694 */
2695 spin_lock_bh(&sc->chan_lock);
2696 sc->sched.mgd_prepare_tx = true;
2697 cur_conf = &go_ctx->beacon;
2698 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2699 spin_unlock_bh(&sc->chan_lock);
2700
6185672a 2701 timeout = usecs_to_jiffies(beacon_int * 2);
c6500ea2
SM		 2702 init_completion(&sc->go_beacon);
2703
6185672a 2704 mutex_unlock(&sc->mutex);
2c3634a8 2705
c6500ea2 2706 if (wait_for_completion_timeout(&sc->go_beacon,
2c3634a8 2707 timeout) == 0) {
c6500ea2
SM		 2708 ath_dbg(common, CHAN_CTX,
2709 "Failed to send new NoA\n");
2c3634a8
SM		 2710
2711 spin_lock_bh(&sc->chan_lock);
2712 sc->sched.mgd_prepare_tx = false;
2713 spin_unlock_bh(&sc->chan_lock);
2714 }
2715
6185672a 2716 mutex_lock(&sc->mutex);
e20a854e 2717 }
c6500ea2 2718
878066e7 2719 ath_dbg(common, CHAN_CTX,
c6500ea2
SM		 2720 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2721 __func__, vif->addr);
2722
2723 spin_lock_bh(&sc->chan_lock);
2724 sc->next_chan = avp->chanctx;
e20a854e
SM		 2725 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2726 spin_unlock_bh(&sc->chan_lock);
2727
c6500ea2
SM		 2728 ath_chanctx_set_next(sc, true);
2729out:
e20a854e
SM		 2730 mutex_unlock(&sc->mutex);
2731}
2732
78b21949
FF		 2733void ath9k_fill_chanctx_ops(void)
2734{
499afacc 2735 if (!ath9k_is_chanctx_enabled())
78b21949
FF		 2736 return;
2737
bc81d43a
SM		 2738 ath9k_ops.hw_scan = ath9k_hw_scan;
2739 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2740 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
405393cf 2741 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
bc81d43a
SM		 2742 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2743 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2744 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2745 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2746 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
e20a854e 2747 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
78b21949
FF		 2748}
2749
499afacc
SM		 2750#endif
2751
d385c5c2
FF		 2752static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2753 int *dbm)
2754{
2755 struct ath_softc *sc = hw->priv;
2756 struct ath_vif *avp = (void *)vif->drv_priv;
2757
2758 mutex_lock(&sc->mutex);
2759 if (avp->chanctx)
2760 *dbm = avp->chanctx->cur_txpower;
2761 else
2762 *dbm = sc->cur_chan->cur_txpower;
2763 mutex_unlock(&sc->mutex);
2764
2765 *dbm /= 2;
2766
2767 return 0;
2768}
2769
6baff7f9 2770struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2771 .tx = ath9k_tx,
2772 .start = ath9k_start,
2773 .stop = ath9k_stop,
2774 .add_interface = ath9k_add_interface,
6b3b991d 2775 .change_interface = ath9k_change_interface,
8feceb67
VT		 2776 .remove_interface = ath9k_remove_interface,
2777 .config = ath9k_config,
8feceb67 2778 .configure_filter = ath9k_configure_filter,
df3c6eb3 2779 .sta_state = ath9k_sta_state,
5519541d 2780 .sta_notify = ath9k_sta_notify,
8feceb67 2781 .conf_tx = ath9k_conf_tx,
8feceb67 2782 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2783 .set_key = ath9k_set_key,
8feceb67 2784 .get_tsf = ath9k_get_tsf,
3b5d665b 2785 .set_tsf = ath9k_set_tsf,
8feceb67 2786 .reset_tsf = ath9k_reset_tsf,
4233df6b 2787 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2788 .get_survey = ath9k_get_survey,
3b319aae 2789 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2790 .set_coverage_class = ath9k_set_coverage_class,
69081624 2791 .flush = ath9k_flush,
15b91e83 2792 .tx_frames_pending = ath9k_tx_frames_pending,
52c94f41 2793 .tx_last_beacon = ath9k_tx_last_beacon,
86a22acf 2794 .release_buffered_frames = ath9k_release_buffered_frames,
52c94f41 2795 .get_stats = ath9k_get_stats,
43c35284
FF		 2796 .set_antenna = ath9k_set_antenna,
2797 .get_antenna = ath9k_get_antenna,
b90bd9d1 2798
e60001e7 2799#ifdef CONFIG_ATH9K_WOW
b11e640a
MSS		 2800 .suspend = ath9k_suspend,
2801 .resume = ath9k_resume,
2802 .set_wakeup = ath9k_set_wakeup,
2803#endif
2804
b90bd9d1
BG		 2805#ifdef CONFIG_ATH9K_DEBUGFS
2806 .get_et_sset_count = ath9k_get_et_sset_count,
a145daf7
SM		 2807 .get_et_stats = ath9k_get_et_stats,
2808 .get_et_strings = ath9k_get_et_strings,
2809#endif
2810
1cdbaf0d 2811#if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
a145daf7 2812 .sta_add_debugfs = ath9k_sta_add_debugfs,
b90bd9d1 2813#endif
e93d083f
SW		 2814 .sw_scan_start = ath9k_sw_scan_start,
2815 .sw_scan_complete = ath9k_sw_scan_complete,
d385c5c2 2816 .get_txpower = ath9k_get_txpower,
50f08edf 2817 .wake_tx_queue = ath9k_wake_tx_queue,
8feceb67 2818};
Linux 6.x block layer and io_uring tree(s)